[
  {
    "path": ".gitmodules",
    "content": "[submodule \"0.SubModules/Peak\"]\n\tpath = 0.SubModules/Peak\n\turl = git@github.com:peng-zhihui/Peak.git\n"
  },
  {
    "path": "1.Hardware/.gitattributes",
    "content": "# author: GitHub@TitanRGB\n# This document allows GitHub to correctly identify Altium Designer, KiCAD, Gerber and Eagle documents and add them to GitHub Repository's language statistics.  \n# 这个文档可以使GitHub正确的识别Altium Designer、KiCAD、Gerber以及Eagle的文档，并将它们加入到GitHub Repository的语言统计中。\n\n# https://gist.github.com/TitanRGB/61c37bf71159cc9a511558ec7c218339\n\n*.OutJob linguist-detectable=true\n*.PcbDoc linguist-detectable=true\n*.PrjPCB linguist-detectable=true\n*.SchDoc linguist-detectable=true\n*.outjob linguist-detectable=true\n*.pcbdoc linguist-detectable=true\n*.prjpcb linguist-detectable=true\n*.schdoc linguist-detectable=true\n*.PCB linguist-detectable=true\n*.sch linguist-detectable=true\n*.lib linguist-detectable=true\n*.epf linguist-detectable=true\n*.brd linguist-detectable=true\n*.pro linguist-detectable=true\n*.gbr linguist-detectable=true\n*.cmp linguist-detectable=true\n*.gbl linguist-detectable=true\n*.gbo linguist-detectable=true\n*.gbp linguist-detectable=true\n*.gbs linguist-detectable=true\n*.gko linguist-detectable=true\n*.gml linguist-detectable=true\n*.gpb linguist-detectable=true\n*.gpt linguist-detectable=true\n*.gtl linguist-detectable=true\n*.gto linguist-detectable=true\n*.gtp linguist-detectable=true\n*.gts linguist-detectable=true\n*.ncl linguist-detectable=true\n*.sol linguist-detectable=true\n*.GBR linguist-detectable=true\n*.CMP linguist-detectable=true\n*.GBL linguist-detectable=true\n*.GBO linguist-detectable=true\n*.GBP linguist-detectable=true\n*.GBS linguist-detectable=true\n*.GKO linguist-detectable=true\n*.GML linguist-detectable=true\n*.GBP linguist-detectable=true\n*.GPT linguist-detectable=true\n*.GTL linguist-detectable=true\n*.GTO linguist-detectable=true\n*.GTP linguist-detectable=true\n*.GTS linguist-detectable=true\n*.NCL linguist-detectable=true\n*.SOL linguist-detectable=true\n*.kicad_pcb linguist-detectable=true\n*.pro linguist-detectable=true\n*.obj linguist-detectable=true\n*.stl linguist-detectable=true\n*.md linguist-detectable=true\n*.dxf linguist-detectable=true\n*.dwg linguist-detectable=true"
  },
  {
    "path": "1.Hardware/Controller/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/Controller/Controller.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=2\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=0\nAppendSheetNumberToLocalNets=1\nNetlistSinglePinNets=0\nDefaultConfiguration=Default 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Outputs for Controller\\Design Rule Check - Controller.html\nDItemRevisionGUID=\n\n[SearchPath1]\nPath=E:\\OneDrive\\[软件配置备份]\\Altium Designer\\1.元件库\\*.*\nIncludeSubFolders=1\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small 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Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 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Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908292~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16908304~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\OpenMotion-dev\\1.Hardware\\Controller\\Controller.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Export Comments\nOutputName7=Export Comments\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=BOM_ReportCompare\nOutputName8=BOM Compare\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/Controller/Controller.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/Dangle/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/Dangle/Dangle.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=2\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=0\nAppendSheetNumberToLocalNets=1\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=1\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Main.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=QVBBULDQ\n\n[Document2]\nDocumentPath=Dangle.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=SPYPGENJ\n\n[GeneratedDocument1]\nDocumentPath=Project Outputs for Dangle\\Design Rule Check - Dangle.html\nDItemRevisionGUID=\n\n[SearchPath1]\nPath=E:\\OneDrive\\[软件配置备份]\\Altium Designer\\1.元件库\\*.*\nIncludeSubFolders=1\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Plane\nOutputName1=Power-Plane Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Board Stack Report\nOutputName2=Report Board Stack\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=ODB\nOutputName3=ODB++ Files\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Test Points\nOutputName4=Test Point Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=NC Drill\nOutputName5=NC Drill Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nConfiguration5_Name1=ForceUpdateSettings\nConfiguration5_Item1=False\nConfiguration5_Name2=OutputConfigurationParameter1\nConfiguration5_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\OpenMotion-dev\\1.Hardware\\Controller\\Controller.PcbDoc\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Drill\nOutputName7=Drill Drawing/Guides\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=CompositeDrill\nOutputName9=Composite Drill Drawing\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType10=Gerber X2\nOutputName10=Gerber X2 Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908292~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16908304~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\OpenMotion-dev\\1.Hardware\\Controller\\Controller.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Export Comments\nOutputName7=Export Comments\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=BOM_ReportCompare\nOutputName8=BOM Compare\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/Dangle/Dangle.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/HandModule/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/HandModule/HandModule.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=2\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=0\nAppendSheetNumberToLocalNets=1\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=1\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Main.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=QVBBULDQ\n\n[Document2]\nDocumentPath=HandModule.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=SPYPGENJ\n\n[SearchPath1]\nPath=E:\\OneDrive\\[软件配置备份]\\Altium Designer\\1.元件库\\*.*\nIncludeSubFolders=1\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Plane\nOutputName1=Power-Plane Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Board Stack Report\nOutputName2=Report Board Stack\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=ODB\nOutputName3=ODB++ Files\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Test Points\nOutputName4=Test Point Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=NC Drill\nOutputName5=NC Drill Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nConfiguration5_Name1=ForceUpdateSettings\nConfiguration5_Item1=False\nConfiguration5_Name2=OutputConfigurationParameter1\nConfiguration5_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\Dummy-Robot-dev\\1.Hardware\\HandModule\\HandModule.PcbDoc\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Drill\nOutputName7=Drill Drawing/Guides\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=CompositeDrill\nOutputName9=Composite Drill Drawing\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType10=Gerber X2\nOutputName10=Gerber X2 Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908292~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16908304~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\Dummy-Robot-dev\\1.Hardware\\HandModule\\HandModule.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Export Comments\nOutputName7=Export Comments\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=BOM_ReportCompare\nOutputName8=BOM Compare\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOut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  },
  {
    "path": "1.Hardware/HandModule/HandModule.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/LedRing/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs*\n__Previews"
  },
  {
    "path": "1.Hardware/LedRing/LedRing.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=0\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=1\nAppendSheetNumberToLocalNets=0\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=0\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Main.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=OTRBEYFQ\n\n[Document2]\nDocumentPath=LedRing.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=OBQETHQV\n\n[GeneratedDocument1]\nDocumentPath=Project Outputs for LedRing\\Design Rule Check - LedRing.html\nDItemRevisionGUID=\n\n[GeneratedDocument2]\nDocumentPath=Project Outputs for LedRing\\LedRing.DRR\nDItemRevisionGUID=\n\n[GeneratedDocument3]\nDocumentPath=Project Outputs for LedRing\\LedRing.EXTREP\nDItemRevisionGUID=\n\n[GeneratedDocument4]\nDocumentPath=Project Outputs for LedRing\\LedRing.GBL\nDItemRevisionGUID=\n\n[GeneratedDocument5]\nDocumentPath=Project Outputs for LedRing\\LedRing.GBO\nDItemRevisionGUID=\n\n[GeneratedDocument6]\nDocumentPath=Project Outputs for LedRing\\LedRing.GBP\nDItemRevisionGUID=\n\n[GeneratedDocument7]\nDocumentPath=Project Outputs for LedRing\\LedRing.GBS\nDItemRevisionGUID=\n\n[GeneratedDocument8]\nDocumentPath=Project Outputs for LedRing\\LedRing.GD1\nDItemRevisionGUID=\n\n[GeneratedDocument9]\nDocumentPath=Project Outputs for LedRing\\LedRing.GG1\nDItemRevisionGUID=\n\n[GeneratedDocument10]\nDocumentPath=Project Outputs for LedRing\\LedRing.GKO\nDItemRevisionGUID=\n\n[GeneratedDocument11]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM1\nDItemRevisionGUID=\n\n[GeneratedDocument12]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM10\nDItemRevisionGUID=\n\n[GeneratedDocument13]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM12\nDItemRevisionGUID=\n\n[GeneratedDocument14]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM13\nDItemRevisionGUID=\n\n[GeneratedDocument15]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM14\nDItemRevisionGUID=\n\n[GeneratedDocument16]\nDocumentPath=Project Outputs for LedRing\\LedRing.GM15\nDItemRevisionGUID=\n\n[GeneratedDocument17]\nDocumentPath=Project Outputs for LedRing\\LedRing.GPB\nDItemRevisionGUID=\n\n[GeneratedDocument18]\nDocumentPath=Project Outputs for LedRing\\LedRing.GPT\nDItemRevisionGUID=\n\n[GeneratedDocument19]\nDocumentPath=Project Outputs for LedRing\\LedRing.GTL\nDItemRevisionGUID=\n\n[GeneratedDocument20]\nDocumentPath=Project Outputs for LedRing\\LedRing.GTO\nDItemRevisionGUID=\n\n[GeneratedDocument21]\nDocumentPath=Project Outputs for LedRing\\LedRing.GTP\nDItemRevisionGUID=\n\n[GeneratedDocument22]\nDocumentPath=Project Outputs for LedRing\\LedRing.GTS\nDItemRevisionGUID=\n\n[GeneratedDocument23]\nDocumentPath=Project Outputs for LedRing\\LedRing.LDP\nDItemRevisionGUID=\n\n[GeneratedDocument24]\nDocumentPath=Project Outputs for LedRing\\LedRing.REP\nDItemRevisionGUID=\n\n[GeneratedDocument25]\nDocumentPath=Project Outputs for LedRing\\LedRing.RUL\nDItemRevisionGUID=\n\n[GeneratedDocument26]\nDocumentPath=Project Outputs for LedRing\\LedRing.TXT\nDItemRevisionGUID=\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal 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Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Plane\nOutputName1=Power-Plane Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Board Stack Report\nOutputName2=Report Board Stack\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=ODB\nOutputName3=ODB++ Files\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Test Points\nOutputName4=Test Point Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=NC Drill\nOutputName5=NC Drill Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nConfiguration5_Name1=ForceUpdateSettings\nConfiguration5_Item1=False\nConfiguration5_Name2=OutputConfigurationParameter1\nConfiguration5_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\Dummy-Robot-dev\\1.Hardware\\LedRing\\LedRing.PcbDoc\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Drill\nOutputName7=Drill Drawing/Guides\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=CompositeDrill\nOutputName9=Composite Drill Drawing\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType10=Gerber X2\nOutputName10=Gerber X2 Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\Dummy-Robot-dev\\1.Hardware\\LedRing\\LedRing.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=BOM_ReportCompare\nOutputName7=BOM Compare\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Export Comments\nOutputName8=Export Comments\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/LedRing/LedRing.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber= \n"
  },
  {
    "path": "1.Hardware/MotorDriver-20/.gitignore",
    "content": "History\nProject Logs for littleVisual-ESP32\n__Previews"
  },
  {
    "path": "1.Hardware/MotorDriver-20/Motor-20.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=0\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=1\nAppendSheetNumberToLocalNets=0\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=0\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Drive.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=OTRBEYFQ\n\n[Document2]\nDocumentPath=MCU.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=MMRIIHEF\n\n[Document3]\nDocumentPath=Port.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=2\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=ZMLSMFEG\n\n[Document4]\nDocumentPath=Power.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=3\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RMXANKZL\n\n[Document5]\nDocumentPath=Interface.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=4\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=DXHCOWHD\n\n[Document6]\nDocumentPath=Motor-20.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RPGXAMXA\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Mask\nOutputName1=Solder/Paste Mask Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Drill\nOutputName2=Drill Drawing/Guides\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=CompositeDrill\nOutputName3=Composite Drill Drawing\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=IPC2581\nOutputName4=IPC-2581 Files\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Gerber X2\nOutputName5=Gerber X2 Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Board Stack Report\nOutputName7=Report Board Stack\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Plane\nOutputName8=Power-Plane Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=ODB\nOutputName9=ODB++ Files\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nOutputType10=NC Drill\nOutputName10=NC Drill Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nConfiguration10_Name1=ForceUpdateSettings\nConfiguration10_Item1=False\nConfiguration10_Name2=OutputConfigurationParameter1\nConfiguration10_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\Ctrl-Step-Drive\\1.Hardware\\Unibody\\Motor-20\\Motor-20.PcbDoc\nOutputType11=Test Points\nOutputName11=Test Point Report\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\Ctrl-Step-Drive\\1.Hardware\\Unibody\\Motor-20\\Motor-20.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=BOM_ReportCompare\nOutputName7=BOM Compare\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Export Comments\nOutputName8=Export Comments\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite 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    "path": "1.Hardware/MotorDriver-20/Motor-20.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Drive.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Interface.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=MCU.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Port.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Power.SchDoc|SheetNumber=1\n"
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    "path": "1.Hardware/MotorDriver-42/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42-macro.APR_LIB",
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"G04:AMPARAMS|DCode=16|XSize=20mil|YSize=20mil|CornerRadius=5mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD16*\n21,1,0.02000,0.01000,0,0,0.0*\n21,1,0.01000,0.02000,0,0,0.0*\n1,1,0.01000,0.00500,-0.00500*\n1,1,0.01000,-0.00500,-0.00500*\n1,1,0.01000,-0.00500,0.00500*\n1,1,0.01000,0.00500,0.00500*\n%\nG04:AMPARAMS|DCode=17|XSize=23.62mil|YSize=39.37mil|CornerRadius=5.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD17*\n21,1,0.02362,0.02756,0,0,180.0*\n21,1,0.01181,0.03937,0,0,180.0*\n1,1,0.01181,-0.00591,0.01378*\n1,1,0.01181,0.00591,0.01378*\n1,1,0.01181,0.00591,-0.01378*\n1,1,0.01181,-0.00591,-0.01378*\n%\nG04:AMPARAMS|DCode=18|XSize=39.37mil|YSize=59.06mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD18*\n21,1,0.03937,0.03937,0,0,270.0*\n21,1,0.01968,0.05906,0,0,270.0*\n1,1,0.01968,-0.01968,-0.00984*\n1,1,0.01968,-0.01968,0.00984*\n1,1,0.01968,0.01968,0.00984*\n1,1,0.01968,0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=19|XSize=15.75mil|YSize=59.06mil|CornerRadius=3.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD19*\n21,1,0.01575,0.05118,0,0,90.0*\n21,1,0.00787,0.05906,0,0,90.0*\n1,1,0.00787,0.02559,0.00394*\n1,1,0.00787,0.02559,-0.00394*\n1,1,0.00787,-0.02559,-0.00394*\n1,1,0.00787,-0.02559,0.00394*\n%\nG04:AMPARAMS|DCode=20|XSize=40mil|YSize=60mil|CornerRadius=10mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD20*\n21,1,0.04000,0.04000,0,0,180.0*\n21,1,0.02000,0.06000,0,0,180.0*\n1,1,0.02000,-0.01000,0.02000*\n1,1,0.02000,0.01000,0.02000*\n1,1,0.02000,0.01000,-0.02000*\n1,1,0.02000,-0.01000,-0.02000*\n%\nG04:AMPARAMS|DCode=21|XSize=16mil|YSize=16mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD21*\n21,1,0.01600,0.00000,0,0,270.0*\n21,1,0.00000,0.01600,0,0,270.0*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n%\nG04:AMPARAMS|DCode=22|XSize=39.37mil|YSize=59.06mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD22*\n21,1,0.03937,0.03937,0,0,0.0*\n21,1,0.01968,0.05906,0,0,0.0*\n1,1,0.01968,0.00984,-0.01968*\n1,1,0.01968,-0.00984,-0.01968*\n1,1,0.01968,-0.00984,0.01968*\n1,1,0.01968,0.00984,0.01968*\n%\nG04:AMPARAMS|DCode=23|XSize=15.75mil|YSize=59.06mil|CornerRadius=3.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD23*\n21,1,0.01575,0.05118,0,0,180.0*\n21,1,0.00787,0.05906,0,0,180.0*\n1,1,0.00787,-0.00394,0.02559*\n1,1,0.00787,0.00394,0.02559*\n1,1,0.00787,0.00394,-0.02559*\n1,1,0.00787,-0.00394,-0.02559*\n%\nG04:AMPARAMS|DCode=25|XSize=40mil|YSize=74mil|CornerRadius=10mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD25*\n21,1,0.04000,0.05400,0,0,90.0*\n21,1,0.02000,0.07400,0,0,90.0*\n1,1,0.02000,0.02700,0.01000*\n1,1,0.02000,0.02700,-0.01000*\n1,1,0.02000,-0.02700,-0.01000*\n1,1,0.02000,-0.02700,0.01000*\n%\nG04:AMPARAMS|DCode=26|XSize=59.06mil|YSize=39.37mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD26*\n21,1,0.05906,0.01968,0,0,180.0*\n21,1,0.03937,0.03937,0,0,180.0*\n1,1,0.01968,-0.01968,0.00984*\n1,1,0.01968,0.01968,0.00984*\n1,1,0.01968,0.01968,-0.00984*\n1,1,0.01968,-0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=27|XSize=55mil|YSize=65mil|CornerRadius=13.75mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD27*\n21,1,0.05500,0.03750,0,0,90.0*\n21,1,0.02750,0.06500,0,0,90.0*\n1,1,0.02750,0.01875,0.01375*\n1,1,0.02750,0.01875,-0.01375*\n1,1,0.02750,-0.01875,-0.01375*\n1,1,0.02750,-0.01875,0.01375*\n%\nG04:AMPARAMS|DCode=28|XSize=85.04mil|YSize=88.98mil|CornerRadius=21.26mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD28*\n21,1,0.08504,0.04646,0,0,0.0*\n21,1,0.04252,0.08898,0,0,0.0*\n1,1,0.04252,0.02126,-0.02323*\n1,1,0.04252,-0.02126,-0.02323*\n1,1,0.04252,-0.02126,0.02323*\n1,1,0.04252,0.02126,0.02323*\n%\nG04:AMPARAMS|DCode=29|XSize=19.68mil|YSize=23.62mil|CornerRadius=4.92mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD29*\n21,1,0.01968,0.01378,0,0,90.0*\n21,1,0.00984,0.02362,0,0,90.0*\n1,1,0.00984,0.00689,0.00492*\n1,1,0.00984,0.00689,-0.00492*\n1,1,0.00984,-0.00689,-0.00492*\n1,1,0.00984,-0.00689,0.00492*\n%\nG04:AMPARAMS|DCode=30|XSize=25mil|YSize=50mil|CornerRadius=6.25mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD30*\n21,1,0.02500,0.03750,0,0,0.0*\n21,1,0.01250,0.05000,0,0,0.0*\n1,1,0.01250,0.00625,-0.01875*\n1,1,0.01250,-0.00625,-0.01875*\n1,1,0.01250,-0.00625,0.01875*\n1,1,0.01250,0.00625,0.01875*\n%\nG04:AMPARAMS|DCode=31|XSize=65mil|YSize=120mil|CornerRadius=16.25mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD31*\n21,1,0.06500,0.08750,0,0,180.0*\n21,1,0.03250,0.12000,0,0,180.0*\n1,1,0.03250,-0.01625,0.04375*\n1,1,0.03250,0.01625,0.04375*\n1,1,0.03250,0.01625,-0.04375*\n1,1,0.03250,-0.01625,-0.04375*\n%\nG04:AMPARAMS|DCode=36|XSize=26mil|YSize=26mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD36*\n21,1,0.02600,0.01000,0,0,0.0*\n21,1,0.01000,0.02600,0,0,0.0*\n1,1,0.01600,0.00500,-0.00500*\n1,1,0.01600,-0.00500,-0.00500*\n1,1,0.01600,-0.00500,0.00500*\n1,1,0.01600,0.00500,0.00500*\n%\nG04:AMPARAMS|DCode=37|XSize=29.62mil|YSize=45.37mil|CornerRadius=8.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD37*\n21,1,0.02962,0.02756,0,0,180.0*\n21,1,0.01181,0.04537,0,0,180.0*\n1,1,0.01781,-0.00591,0.01378*\n1,1,0.01781,0.00591,0.01378*\n1,1,0.01781,0.00591,-0.01378*\n1,1,0.01781,-0.00591,-0.01378*\n%\nG04:AMPARAMS|DCode=38|XSize=45.37mil|YSize=65.06mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD38*\n21,1,0.04537,0.03937,0,0,270.0*\n21,1,0.01968,0.06506,0,0,270.0*\n1,1,0.02568,-0.01968,-0.00984*\n1,1,0.02568,-0.01968,0.00984*\n1,1,0.02568,0.01968,0.00984*\n1,1,0.02568,0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=39|XSize=21.75mil|YSize=65.06mil|CornerRadius=6.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD39*\n21,1,0.02175,0.05118,0,0,90.0*\n21,1,0.00787,0.06506,0,0,90.0*\n1,1,0.01387,0.02559,0.00394*\n1,1,0.01387,0.02559,-0.00394*\n1,1,0.01387,-0.02559,-0.00394*\n1,1,0.01387,-0.02559,0.00394*\n%\nG04:AMPARAMS|DCode=40|XSize=46mil|YSize=66mil|CornerRadius=13mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD40*\n21,1,0.04600,0.04000,0,0,180.0*\n21,1,0.02000,0.06600,0,0,180.0*\n1,1,0.02600,-0.01000,0.02000*\n1,1,0.02600,0.01000,0.02000*\n1,1,0.02600,0.01000,-0.02000*\n1,1,0.02600,-0.01000,-0.02000*\n%\nG04:AMPARAMS|DCode=41|XSize=22mil|YSize=22mil|CornerRadius=11mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD41*\n21,1,0.02200,0.00000,0,0,270.0*\n21,1,0.00000,0.02200,0,0,270.0*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n%\nG04:AMPARAMS|DCode=42|XSize=45.37mil|YSize=65.06mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD42*\n21,1,0.04537,0.03937,0,0,0.0*\n21,1,0.01968,0.06506,0,0,0.0*\n1,1,0.02568,0.00984,-0.01968*\n1,1,0.02568,-0.00984,-0.01968*\n1,1,0.02568,-0.00984,0.01968*\n1,1,0.02568,0.00984,0.01968*\n%\nG04:AMPARAMS|DCode=43|XSize=21.75mil|YSize=65.06mil|CornerRadius=6.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD43*\n21,1,0.02175,0.05118,0,0,180.0*\n21,1,0.00787,0.06506,0,0,180.0*\n1,1,0.01387,-0.00394,0.02559*\n1,1,0.01387,0.00394,0.02559*\n1,1,0.01387,0.00394,-0.02559*\n1,1,0.01387,-0.00394,-0.02559*\n%\nG04:AMPARAMS|DCode=45|XSize=46mil|YSize=80mil|CornerRadius=13mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD45*\n21,1,0.04600,0.05400,0,0,90.0*\n21,1,0.02000,0.08000,0,0,90.0*\n1,1,0.02600,0.02700,0.01000*\n1,1,0.02600,0.02700,-0.01000*\n1,1,0.02600,-0.02700,-0.01000*\n1,1,0.02600,-0.02700,0.01000*\n%\nG04:AMPARAMS|DCode=46|XSize=65.06mil|YSize=45.37mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD46*\n21,1,0.06506,0.01968,0,0,180.0*\n21,1,0.03937,0.04537,0,0,180.0*\n1,1,0.02568,-0.01968,0.00984*\n1,1,0.02568,0.01968,0.00984*\n1,1,0.02568,0.01968,-0.00984*\n1,1,0.02568,-0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=47|XSize=61mil|YSize=71mil|CornerRadius=16.75mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD47*\n21,1,0.06100,0.03750,0,0,90.0*\n21,1,0.02750,0.07100,0,0,90.0*\n1,1,0.03350,0.01875,0.01375*\n1,1,0.03350,0.01875,-0.01375*\n1,1,0.03350,-0.01875,-0.01375*\n1,1,0.03350,-0.01875,0.01375*\n%\nG04:AMPARAMS|DCode=48|XSize=25.68mil|YSize=29.62mil|CornerRadius=7.92mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD48*\n21,1,0.02568,0.01378,0,0,90.0*\n21,1,0.00984,0.02962,0,0,90.0*\n1,1,0.01584,0.00689,0.00492*\n1,1,0.01584,0.00689,-0.00492*\n1,1,0.01584,-0.00689,-0.00492*\n1,1,0.01584,-0.00689,0.00492*\n%\nG04:AMPARAMS|DCode=60|XSize=20mil|YSize=20mil|CornerRadius=5mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD60*\n21,1,0.02000,0.01000,0,0,270.0*\n21,1,0.01000,0.02000,0,0,270.0*\n1,1,0.01000,-0.00500,-0.00500*\n1,1,0.01000,-0.00500,0.00500*\n1,1,0.01000,0.00500,0.00500*\n1,1,0.01000,0.00500,-0.00500*\n%\nG04:AMPARAMS|DCode=61|XSize=37.64mil|YSize=63.38mil|CornerRadius=9.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD61*\n21,1,0.03764,0.04456,0,0,270.0*\n21,1,0.01882,0.06338,0,0,270.0*\n1,1,0.01882,-0.02228,-0.00941*\n1,1,0.01882,-0.02228,0.00941*\n1,1,0.01882,0.02228,0.00941*\n1,1,0.01882,0.02228,-0.00941*\n%\nG04:AMPARAMS|DCode=62|XSize=90.55mil|YSize=90.55mil|CornerRadius=22.64mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD62*\n21,1,0.09055,0.04528,0,0,0.0*\n21,1,0.04528,0.09055,0,0,0.0*\n1,1,0.04528,0.02264,-0.02264*\n1,1,0.04528,-0.02264,-0.02264*\n1,1,0.04528,-0.02264,0.02264*\n1,1,0.04528,0.02264,0.02264*\n%\nG04:AMPARAMS|DCode=63|XSize=200mil|YSize=80mil|CornerRadius=20mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD63*\n21,1,0.20000,0.04000,0,0,270.0*\n21,1,0.16000,0.08000,0,0,270.0*\n1,1,0.04000,-0.02000,-0.08000*\n1,1,0.04000,-0.02000,0.08000*\n1,1,0.04000,0.02000,0.08000*\n1,1,0.04000,0.02000,-0.08000*\n%\nG04:AMPARAMS|DCode=64|XSize=21.65mil|YSize=57.09mil|CornerRadius=5.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD64*\n21,1,0.02165,0.04626,0,0,270.0*\n21,1,0.01083,0.05709,0,0,270.0*\n1,1,0.01083,-0.02313,-0.00541*\n1,1,0.01083,-0.02313,0.00541*\n1,1,0.01083,0.02313,0.00541*\n1,1,0.01083,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=65|XSize=21.65mil|YSize=57.09mil|CornerRadius=5.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD65*\n21,1,0.02165,0.04626,0,0,270.0*\n21,1,0.01083,0.05709,0,0,270.0*\n1,1,0.01083,-0.02313,-0.00541*\n1,1,0.01083,-0.02313,0.00541*\n1,1,0.01083,0.02313,0.00541*\n1,1,0.01083,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=66|XSize=23.62mil|YSize=35mil|CornerRadius=5.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD66*\n21,1,0.02362,0.02319,0,0,0.0*\n21,1,0.01181,0.03500,0,0,0.0*\n1,1,0.01181,0.00591,-0.01159*\n1,1,0.01181,-0.00591,-0.01159*\n1,1,0.01181,-0.00591,0.01159*\n1,1,0.01181,0.00591,0.01159*\n%\nG04:AMPARAMS|DCode=67|XSize=27.56mil|YSize=51.18mil|CornerRadius=6.89mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD67*\n21,1,0.02756,0.03740,0,0,0.0*\n21,1,0.01378,0.05118,0,0,0.0*\n1,1,0.01378,0.00689,-0.01870*\n1,1,0.01378,-0.00689,-0.01870*\n1,1,0.01378,-0.00689,0.01870*\n1,1,0.01378,0.00689,0.01870*\n%\nG04:AMPARAMS|DCode=74|XSize=26mil|YSize=26mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD74*\n21,1,0.02600,0.01000,0,0,270.0*\n21,1,0.01000,0.02600,0,0,270.0*\n1,1,0.01600,-0.00500,-0.00500*\n1,1,0.01600,-0.00500,0.00500*\n1,1,0.01600,0.00500,0.00500*\n1,1,0.01600,0.00500,-0.00500*\n%\nG04:AMPARAMS|DCode=75|XSize=96.55mil|YSize=96.55mil|CornerRadius=25.64mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD75*\n21,1,0.09655,0.04528,0,0,0.0*\n21,1,0.04528,0.09655,0,0,0.0*\n1,1,0.05128,0.02264,-0.02264*\n1,1,0.05128,-0.02264,-0.02264*\n1,1,0.05128,-0.02264,0.02264*\n1,1,0.05128,0.02264,0.02264*\n%\nG04:AMPARAMS|DCode=76|XSize=206mil|YSize=86mil|CornerRadius=23mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD76*\n21,1,0.20600,0.04000,0,0,270.0*\n21,1,0.16000,0.08600,0,0,270.0*\n1,1,0.04600,-0.02000,-0.08000*\n1,1,0.04600,-0.02000,0.08000*\n1,1,0.04600,0.02000,0.08000*\n1,1,0.04600,0.02000,-0.08000*\n%\nG04:AMPARAMS|DCode=77|XSize=27.65mil|YSize=63.09mil|CornerRadius=8.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD77*\n21,1,0.02765,0.04626,0,0,270.0*\n21,1,0.01083,0.06309,0,0,270.0*\n1,1,0.01683,-0.02313,-0.00541*\n1,1,0.01683,-0.02313,0.00541*\n1,1,0.01683,0.02313,0.00541*\n1,1,0.01683,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=78|XSize=27.65mil|YSize=63.09mil|CornerRadius=8.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD78*\n21,1,0.02765,0.04626,0,0,270.0*\n21,1,0.01083,0.06309,0,0,270.0*\n1,1,0.01683,-0.02313,-0.00541*\n1,1,0.01683,-0.02313,0.00541*\n1,1,0.01683,0.02313,0.00541*\n1,1,0.01683,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=79|XSize=29.62mil|YSize=41mil|CornerRadius=8.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD79*\n21,1,0.02962,0.02319,0,0,0.0*\n21,1,0.01181,0.04100,0,0,0.0*\n1,1,0.01781,0.00591,-0.01159*\n1,1,0.01781,-0.00591,-0.01159*\n1,1,0.01781,-0.00591,0.01159*\n1,1,0.01781,0.00591,0.01159*\n%\nG04:AMPARAMS|DCode=80|XSize=33.56mil|YSize=57.18mil|CornerRadius=9.89mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD80*\n21,1,0.03356,0.03740,0,0,0.0*\n21,1,0.01378,0.05718,0,0,0.0*\n1,1,0.01978,0.00689,-0.01870*\n1,1,0.01978,-0.00689,-0.01870*\n1,1,0.01978,-0.00689,0.01870*\n1,1,0.01978,0.00689,0.01870*\n%\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.DRR",
    "content": "----------------------------------------------------------------------------------------------------------------------------------\nNCDrill File Report For: Motor-42.PcbDoc   ܶ 01-18  19:21:45\n----------------------------------------------------------------------------------------------------------------------------------\n\nLayer Pair : Top1 to Bottom4\nASCII RoundHoles File : Motor-42.TXT\n\nTool       Hole Size               Hole Tolerance               Hole Type       Hole Count   Plated         Tool Travel\n----------------------------------------------------------------------------------------------------------------------------------\nT1      10mil (0.254mm)                                           Round             146       PTH        12.15inch (308.67mm)\nT2      16mil (0.4mm)                                             Round             139       PTH        7.73inch (196.44mm)\nT3      122mil (3.1mm)                                            Round             4         PTH        3.66inch (93.00mm)\n----------------------------------------------------------------------------------------------------------------------------------\nTotals                                                                              289\n\nTotal Processing Time (hh:mm:ss) : 00:00:01\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.EXTREP",
    "content": "------------------------------------------------------------------------------------------\nGerber File Extension Report For: Motor-42.GBR   ܶ 01-18  19:21:37\n------------------------------------------------------------------------------------------\n\n\n------------------------------------------------------------------------------------------\nLayer Extension     Layer Description                      \n------------------------------------------------------------------------------------------\n.GTO                Top Overlay                             \n.GTP                Top Paste                               \n.GTS                Top Solder                              \n.GTL                Top1                                    \n.G1                 Signal2                                 \n.G2                 Gnd3                                    \n.GBL                Bottom4                                 \n.GBS                Bottom Solder                           \n.GBP                Bottom Paste                            \n.GBO                Bottom Overlay                          \n.GM1                Mechanical 1                            \n.GM10               Mechanical 10                           \n.GM12               Mechanical 12                           \n.GM13               Mechanical 13                           \n.GM14               Mechanical 14                           \n.GM15               Mechanical 15                           \n.GKO                Keep-Out Layer                          \n.GPT                Top Pad Master                          \n.GPB                Bottom Pad Master                       \n.GD1                Drill Drawing                           \n.GG1                Drill Guide                             \n------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.G1",
    "content": "G04*\nG04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*\nG04*\nG04 Layer_Physical_Order=2*\nG04 Layer_Color=14461039*\n%FSLAX25Y25*%\n%MOIN*%\nG70*\nG04*\nG04 #@! TF.SameCoordinates,B24A499B-10B0-4348-9313-877DE5855C24*\nG04*\nG04*\nG04 #@! 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  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.GTL",
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  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.LDP",
    "content": "Layer Pairs Export File for PCB: I:\\onWorking\\Dummy-Robot\\1.Hardware\\MotorDriver-42\\Motor-42.PcbDoc\nLayersSetName=Top_Bot_Thru_Holes|DrillFile=motor-42.txt|DrillLayers=gtl,g1,g2,gbl\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.REP",
    "content": "*************************************************************\nFileName = Motor-42.GBR\nAutoAperture = True\n*************************************************************\nGenerating : Mechanical 15\n      File : Motor-42.GM15\n\n    Adding Layer      : Mechanical 15\n\n\nUsed DCodes :\n    D13\n    D85\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 14\n      File : Motor-42.GM14\n\n    Adding Layer      : Mechanical 14\n\n\nUsed DCodes :\n    D86\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 13\n      File : Motor-42.GM13\n\n    Adding Layer      : Mechanical 13\n\n\nUsed DCodes :\n    D85\n    D86\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 12\n      File : Motor-42.GM12\n\n    Adding Layer      : Mechanical 12\n\n\nUsed DCodes :\n    D13\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 10\n      File : Motor-42.GM10\n\n    Adding Layer      : Mechanical 10\n\n\nUsed DCodes :\n    D13\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 1\n      File : Motor-42.GM1\n\n    Adding Layer      : Mechanical 1\n\n\nUsed DCodes :\n    D10\n*************************************************************\n\n*************************************************************\nGenerating : Keep-Out Layer\n      File : Motor-42.GKO\n\n    Adding Layer      : Keep-Out Layer\n\n\nUsed DCodes :\n    D10\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Overlay\n      File : Motor-42.GBO\n\n    Adding Layer      : Bottom Overlay\n\n\nUsed DCodes :\n    D12\n    D13\n    D14\n    D84\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Paste\n      File : Motor-42.GBP\n\n    Adding Layer      : Bottom Paste\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Solder\n      File : Motor-42.GBS\n\n    Adding Layer      : Bottom Solder\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D36\n    D49\n    D61\n    D73\n    D74\n    D75\n    D76\n    D77\n    D78\n    D79\n    D80\n    D81\n    D82\n    D83\n*************************************************************\n\n*************************************************************\nGenerating : Top Solder\n      File : Motor-42.GTS\n\n    Adding Layer      : Top Solder\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D28\n    D30\n    D31\n    D32\n    D33\n    D34\n    D35\n    D36\n    D37\n    D38\n    D39\n    D40\n    D41\n    D42\n    D43\n    D44\n    D45\n    D46\n    D47\n    D48\n    D49\n*************************************************************\n\n*************************************************************\nGenerating : Top Paste\n      File : Motor-42.GTP\n\n    Adding Layer      : Top Paste\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n*************************************************************\n\n*************************************************************\nGenerating : Top Overlay\n      File : Motor-42.GTO\n\n    Adding Layer      : Top Overlay\n\n\nUsed DCodes :\n    D10\n    D11\n    D12\n    D13\n    D14\n    D15\n*************************************************************\n\n*************************************************************\nGenerating : Top Pad Master\n      File : Motor-42.GPT\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n    D54\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Pad Master\n      File : Motor-42.GPB\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D54\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n*************************************************************\n\n*************************************************************\nGenerating : Bottom4\n      File : Motor-42.GBL\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D16\n    D50\n    D54\n    D55\n    D56\n    D57\n    D58\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n    D71\n    D72\n*************************************************************\n\n*************************************************************\nGenerating : Gnd3\n      File : Motor-42.G2\n\n    Adding Layer      : Gnd3\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D54\n    D55\n    D56\n*************************************************************\n\n*************************************************************\nGenerating : Signal2\n      File : Motor-42.G1\n\n    Adding Layer      : Signal2\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D50\n    D54\n    D55\n    D56\n    D57\n    D58\n*************************************************************\n\n*************************************************************\nGenerating : Top1\n      File : Motor-42.GTL\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n    D50\n    D51\n    D52\n    D53\n    D54\n    D55\n    D56\n*************************************************************\n\n*************************************************************\nGenerating : Drill Drawing\n      File : Motor-42.GD1\n\n    Adding Drill Pair : Top1-Bottom4\n\n    Adding Layer      : Drill Drawing\n\n\nUsed DCodes :\n    D86\n    D87\n*************************************************************\n\n*************************************************************\nGenerating : Drill Guide\n      File : Motor-42.GG1\n\n    Adding Drill Pair : Top1-Bottom4\n\n    Adding Layer      : Drill Guide\n\n\nUsed DCodes :\n    D86\n*************************************************************\n\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.RUL",
    "content": "DRC Rules Export File for PCB: I:\\onWorking\\Dummy-Robot\\1.Hardware\\MotorDriver-42\\Motor-42.PcbDoc\nRuleKind=Width|RuleName=VCC|Scope=Board|Minimum=4.00\nRuleKind=Width|RuleName=GND|Scope=Board|Minimum=4.00\nRuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=3.00\nRuleKind=Width|RuleName=Width|Scope=Board|Minimum=4.00\nRuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=4.00\nRuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.TXT",
    "content": "M48\n;Layer_Color=9474304\n;FILE_FORMAT=2:5\nINCH,TZ\n;TYPE=PLATED\nT1F00S00C0.01000\nT2F00S00C0.01575\nT3F00S00C0.12205\n%\nT01\nX-78400Y-53500\nX-73500Y-55000\nY-52000\nX-71366Y-45734\nX-77000Y-37500\nY-34000\nY-30500\nY-21000\nX-70800Y-3100\nX-77000Y13000\nY24000\nY30000\nY36000\nX-60000Y36400\nX-59900Y40300\nY32500\nX-53700Y30300\nX-56600Y26900\nX-57000Y23500\nX-53800\nX-59000Y17500\nX-56300Y12500\nX-57500Y5000\nX-54300Y4800\nX-50400\nX-45000Y5000\nX-41000\nY2500\nX-33500Y2000\nY5500\nX-35300Y-8400\nX-31800Y-12300\nX-35000Y-16500\nX-38000Y-17000\nX-40500\nX-42700Y-10600\nX-51900Y-11100\nX-51400Y-14500\nX-56300Y-13100\nX-55784Y-19016\nX-55500Y-23000\nY-25500\nY-28000\nX-51500Y-31600\nX-51000Y-22000\nX-66000\nX-66500Y-15500\nX-66600Y-2500\nX-67500Y100\nX-60500Y3000\nX-56500Y700\nX-52358Y658\nX-44300Y26900\nX-44100Y31200\nX-14500Y31000\nX-9500\nX0Y37000\nY43500\nX9500Y31000\nX14500\nX10800Y7500\nX15800Y300\nX15500Y-13000\nX18000\nX20500\nX23000\nX25500\nY-15500\nX23000\nX19900Y-17400\nX18000Y-16300\nX15800\nX19800Y-22100\nX22454Y-21500\nX28500Y-21200\nY-18700\nY-16400\nX32500Y-16500\nY-19500\nY-22500\nY-25500\nY-28500\nY-31500\nY-34500\nY-37500\nX27000Y-49500\nX27300Y-52900\nX29500Y-52300\nX24000Y-57500\nX8500Y-51100\nX2500Y-47500\nX-2000Y-41500\nX-5000\nX-3500Y-38000\nY-35000\nX300Y-36200\nY-38700\nX240Y-33540\nX-11500Y-31900\nX-10800Y-44100\nX-12500Y-45800\nX-28500Y-43000\nX-27000Y-40500\nY-38000\nX-23500\nX-34620Y-41200\nX-39700Y-41600\nX-37700Y-43700\nX-36600Y-33400\nX-38600Y-31800\nX-40547Y-33553\nX-57000Y-37000\nX-58500Y-41000\nX-56500Y-42500\nX-54300Y-41000\nX-52100Y-42400\nX-62100Y-42600\nX-37500Y-59000\nX-34500\nX-28000Y-63000\nX-2000Y-65500\nX1969Y-62500\nX5500Y-24100\nX8500\nY-21000\nX5500\nX-5000Y-20000\nY-23000\nX-22500Y-19300\nX-18300Y-4200\nX-11400Y-7500\nX-10600Y2500\nX-11000Y5500\nX-13500\nY9500\nX-11000\nX29300Y-4100\nY-7200\nX50000\nY-4000\nX73000Y-4700\nY3500\nX32100Y53700\nX28100Y54000\nX17000Y-32500\nY-35000\nT02\nX-20000Y-72000\nX-17000\nX-14000\nY-69000\nX-17000\nX-20000\nY-66000\nX-17000\nX-14000\nX19000Y-75500\nY-78500\nX22000\nX25000\nX28000\nX31000\nX34000\nX37000\nX40000Y-73000\nY-70000\nY-67000\nX43000\nX46000\nY-70000\nX43000\nY-73000\nX46000\nX70000Y-18000\nY-15000\nX73000\nX76000\nY-12000\nX73000\nX70000\nX73000Y-18000\nX76000\nY12000\nX73000\nY15000\nY18000\nX76000\nY15000\nX70000\nY12000\nY18000\nX32000Y16000\nX29000\nX26000\nX23000\nX20000\nX17000\nX14000\nX11000\nX8000\nX5000\nX2000\nX-1000\nX-4000\nX-7000\nX-10000\nX-13000\nX-16000\nX-19000\nX-19500Y38000\nY41000\nY44000\nX-15000Y43000\nY46000\nX-12000\nX-9000\nY43000\nY40000\nX-12000\nX-15000\nX-12000Y43000\nX-4200Y42100\nY45100\nY39100\nX4300\nY42100\nY45100\nX9000Y46000\nY43000\nX12000\nX15000\nY40000\nX12000\nX9000\nX12000Y46000\nX15000\nX19300Y44700\nY41700\nY38700\nX33100Y38400\nY41400\nY44400\nY35400\nY32400\nY29400\nX4500Y52100\nY55100\nX1500\nY52100\nX-19500\nX-22500\nY55100\nX-19500\nX-27500Y60000\nX-30500\nY63000\nY66000\nX-27500\nY63000\nX-33500\nY60000\nX-36500\nX-39500\nY63000\nY66000\nX-36500\nX-33500\nX-36500Y63000\nX-42500\nY60000\nY66000\nX-34200Y52000\nY49000\nY46000\nY43000\nY40000\nY37000\nX-33500Y-21500\nY-24500\nY-27500\nX-36546\nY-24500\nY-21500\nX-39592\nY-24566\nY-27500\nT03\nX-61024Y-61024\nX61024\nY61024\nX-61024\nM30\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Motor-42.apr",
    "content": "D10   ROUNDED            10.000      10.000       0.000  LINE       0.000\nD11   ROUNDED             4.000       4.000       0.000  LINE       0.000\nD12   ROUNDED             1.000       1.000       0.000  LINE       0.000\nD13   ROUNDED             7.874       7.874       0.000  LINE       0.000\nD14   ROUNDED             6.000       6.000       0.000  LINE       0.000\nD15   ROUNDED             5.000       5.000       0.000  LINE       0.000\nD24   RECTANGULAR        19.685      19.685       0.000 FLASH     270.000\nD32   RECTANGULAR        65.000      60.000       0.000 FLASH       0.000\nD33   RECTANGULAR        77.000      25.000       0.000 FLASH       0.000\nD34   RECTANGULAR        89.000     211.000       0.000 FLASH       0.000\nD35   RECTANGULAR       100.000     100.000       0.000 FLASH       0.000\nD44   RECTANGULAR        25.685      25.685       0.000 FLASH     270.000\nD49   ROUNDED           206.000     206.000       0.000 FLASH       0.000\nD50   ROUNDED            20.000      20.000       0.000  LINE       0.000\nD51   ROUNDED            80.000      80.000       0.000  LINE       0.000\nD52   ROUNDED            40.000      40.000       0.000  LINE       0.000\nD53   ROUNDED            30.000      30.000       0.000  LINE       0.000\nD54   ROUNDED           200.000     200.000       0.000 FLASH       0.000\nD55   ROUNDED            18.000      18.000       0.000 FLASH       0.000\nD56   ROUNDED            23.622      23.622       0.000 FLASH       0.000\nD57   ROUNDED            70.000      70.000       0.000  LINE       0.000\nD58   ROUNDED             7.000       7.000       0.000  LINE       0.000\nD59   ROUNDED            19.685      51.181       0.000 FLASH       0.000\nD68   ROUNDED            19.685      51.181       0.000 FLASH     270.000\nD69   ROUNDED            12.000      54.000       0.000 FLASH       0.000\nD70   ROUNDED            12.000      54.000       0.000 FLASH     270.000\nD71   ROUNDED            25.000      25.000       0.000  LINE       0.000\nD72   ROUNDED            45.000      45.000       0.000  LINE       0.000\nD73   ROUNDED            25.685      57.181       0.000 FLASH       0.000\nD81   ROUNDED            25.685      57.181       0.000 FLASH     270.000\nD82   ROUNDED            18.000      60.000       0.000 FLASH       0.000\nD83   ROUNDED            18.000      60.000       0.000 FLASH     270.000\nD84   ROUNDED             9.842       9.842       0.000  LINE       0.000\nD85   ROUNDED             3.937       3.937       0.000  LINE       0.000\nD86   ROUNDED             2.000       2.000       0.000  LINE       0.000\nD87   ROUNDED             2.667       2.667       0.000  LINE       0.000\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Gerber/Status Report.Txt",
    "content": "Output: NC Drill Files\nType  : NC Drill\nFrom  : Project [Motor-42.PrjPCB]\n   Generated File[Motor-42.TXT]\n   Generated File[Motor-42.LDP]\n   Generated File[Motor-42.DRR]\n\n\nFiles Generated   : 3\nDocuments Printed : 0\n\nFinished Output Generation At 19:21:46 On ܶ 01-18\n"
  },
  {
    "path": "1.Hardware/MotorDriver-42/Motor-42.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=0\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=1\nAppendSheetNumberToLocalNets=0\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=0\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\nCrossRefSheetStyle=1\nCrossRefLocationStyle=1\nCrossRefPorts=3\nCrossRefCrossSheets=1\nCrossRefSheetEntries=0\nCrossRefFollowFromMainSettings=1\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Drive.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=OTRBEYFQ\n\n[Document2]\nDocumentPath=MCU.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=MMRIIHEF\n\n[Document3]\nDocumentPath=Port.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=2\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=ZMLSMFEG\n\n[Document4]\nDocumentPath=Power.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=3\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RMXANKZL\n\n[Document5]\nDocumentPath=Interface.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=4\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=DXHCOWHD\n\n[Document6]\nDocumentPath=Motor-42.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RPGXAMXA\n\n[GeneratedDocument1]\nDocumentPath=Project Outputs for Motor-42\\Design Rule Check - Motor-42.html\nDItemRevisionGUID=\n\n[GeneratedDocument2]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.DRR\nDItemRevisionGUID=\n\n[GeneratedDocument3]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.EXTREP\nDItemRevisionGUID=\n\n[GeneratedDocument4]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.G1\nDItemRevisionGUID=\n\n[GeneratedDocument5]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.G2\nDItemRevisionGUID=\n\n[GeneratedDocument6]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GBL\nDItemRevisionGUID=\n\n[GeneratedDocument7]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GBO\nDItemRevisionGUID=\n\n[GeneratedDocument8]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GBP\nDItemRevisionGUID=\n\n[GeneratedDocument9]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GBS\nDItemRevisionGUID=\n\n[GeneratedDocument10]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GD1\nDItemRevisionGUID=\n\n[GeneratedDocument11]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GG1\nDItemRevisionGUID=\n\n[GeneratedDocument12]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GKO\nDItemRevisionGUID=\n\n[GeneratedDocument13]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM1\nDItemRevisionGUID=\n\n[GeneratedDocument14]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM10\nDItemRevisionGUID=\n\n[GeneratedDocument15]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM12\nDItemRevisionGUID=\n\n[GeneratedDocument16]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM13\nDItemRevisionGUID=\n\n[GeneratedDocument17]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM14\nDItemRevisionGUID=\n\n[GeneratedDocument18]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GM15\nDItemRevisionGUID=\n\n[GeneratedDocument19]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GPB\nDItemRevisionGUID=\n\n[GeneratedDocument20]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GPT\nDItemRevisionGUID=\n\n[GeneratedDocument21]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GTL\nDItemRevisionGUID=\n\n[GeneratedDocument22]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GTO\nDItemRevisionGUID=\n\n[GeneratedDocument23]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GTP\nDItemRevisionGUID=\n\n[GeneratedDocument24]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.GTS\nDItemRevisionGUID=\n\n[GeneratedDocument25]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.LDP\nDItemRevisionGUID=\n\n[GeneratedDocument26]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.REP\nDItemRevisionGUID=\n\n[GeneratedDocument27]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.RUL\nDItemRevisionGUID=\n\n[GeneratedDocument28]\nDocumentPath=Project Outputs for Motor-42\\Motor-42.TXT\nDItemRevisionGUID=\n\n[Configuration1]\nName=Default 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Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 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Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No 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Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=BOM_ReportCompare\nOutputName7=BOM Compare\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Export Comments\nOutputName8=Export Comments\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite 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    "path": "1.Hardware/MotorDriver-42/Motor-42.PrjPCBStructure",
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    "path": "1.Hardware/MotorDriver-57-unused/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57-macro.APR_LIB",
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"G04:AMPARAMS|DCode=16|XSize=15.75mil|YSize=59.06mil|CornerRadius=3.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD16*\n21,1,0.01575,0.05118,0,0,90.0*\n21,1,0.00787,0.05906,0,0,90.0*\n1,1,0.00787,0.02559,0.00394*\n1,1,0.00787,0.02559,-0.00394*\n1,1,0.00787,-0.02559,-0.00394*\n1,1,0.00787,-0.02559,0.00394*\n%\nG04:AMPARAMS|DCode=17|XSize=39.37mil|YSize=59.06mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD17*\n21,1,0.03937,0.03937,0,0,90.0*\n21,1,0.01968,0.05906,0,0,90.0*\n1,1,0.01968,0.01968,0.00984*\n1,1,0.01968,0.01968,-0.00984*\n1,1,0.01968,-0.01968,-0.00984*\n1,1,0.01968,-0.01968,0.00984*\n%\nG04:AMPARAMS|DCode=18|XSize=20mil|YSize=20mil|CornerRadius=5mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD18*\n21,1,0.02000,0.01000,0,0,0.0*\n21,1,0.01000,0.02000,0,0,0.0*\n1,1,0.01000,0.00500,-0.00500*\n1,1,0.01000,-0.00500,-0.00500*\n1,1,0.01000,-0.00500,0.00500*\n1,1,0.01000,0.00500,0.00500*\n%\nG04:AMPARAMS|DCode=19|XSize=23.62mil|YSize=39.37mil|CornerRadius=5.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD19*\n21,1,0.02362,0.02756,0,0,180.0*\n21,1,0.01181,0.03937,0,0,180.0*\n1,1,0.01181,-0.00591,0.01378*\n1,1,0.01181,0.00591,0.01378*\n1,1,0.01181,0.00591,-0.01378*\n1,1,0.01181,-0.00591,-0.01378*\n%\nG04:AMPARAMS|DCode=20|XSize=40mil|YSize=60mil|CornerRadius=10mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD20*\n21,1,0.04000,0.04000,0,0,180.0*\n21,1,0.02000,0.06000,0,0,180.0*\n1,1,0.02000,-0.01000,0.02000*\n1,1,0.02000,0.01000,0.02000*\n1,1,0.02000,0.01000,-0.02000*\n1,1,0.02000,-0.01000,-0.02000*\n%\nG04:AMPARAMS|DCode=21|XSize=16mil|YSize=16mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD21*\n21,1,0.01600,0.00000,0,0,270.0*\n21,1,0.00000,0.01600,0,0,270.0*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n1,1,0.01600,0.00000,0.00000*\n%\nG04:AMPARAMS|DCode=22|XSize=39.37mil|YSize=59.06mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD22*\n21,1,0.03937,0.03937,0,0,0.0*\n21,1,0.01968,0.05906,0,0,0.0*\n1,1,0.01968,0.00984,-0.01968*\n1,1,0.01968,-0.00984,-0.01968*\n1,1,0.01968,-0.00984,0.01968*\n1,1,0.01968,0.00984,0.01968*\n%\nG04:AMPARAMS|DCode=23|XSize=15.75mil|YSize=59.06mil|CornerRadius=3.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD23*\n21,1,0.01575,0.05118,0,0,180.0*\n21,1,0.00787,0.05906,0,0,180.0*\n1,1,0.00787,-0.00394,0.02559*\n1,1,0.00787,0.00394,0.02559*\n1,1,0.00787,0.00394,-0.02559*\n1,1,0.00787,-0.00394,-0.02559*\n%\nG04:AMPARAMS|DCode=25|XSize=40mil|YSize=74mil|CornerRadius=10mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD25*\n21,1,0.04000,0.05400,0,0,90.0*\n21,1,0.02000,0.07400,0,0,90.0*\n1,1,0.02000,0.02700,0.01000*\n1,1,0.02000,0.02700,-0.01000*\n1,1,0.02000,-0.02700,-0.01000*\n1,1,0.02000,-0.02700,0.01000*\n%\nG04:AMPARAMS|DCode=26|XSize=59.06mil|YSize=39.37mil|CornerRadius=9.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD26*\n21,1,0.05906,0.01968,0,0,180.0*\n21,1,0.03937,0.03937,0,0,180.0*\n1,1,0.01968,-0.01968,0.00984*\n1,1,0.01968,0.01968,0.00984*\n1,1,0.01968,0.01968,-0.00984*\n1,1,0.01968,-0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=27|XSize=55mil|YSize=65mil|CornerRadius=13.75mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD27*\n21,1,0.05500,0.03750,0,0,90.0*\n21,1,0.02750,0.06500,0,0,90.0*\n1,1,0.02750,0.01875,0.01375*\n1,1,0.02750,0.01875,-0.01375*\n1,1,0.02750,-0.01875,-0.01375*\n1,1,0.02750,-0.01875,0.01375*\n%\nG04:AMPARAMS|DCode=28|XSize=85.04mil|YSize=88.98mil|CornerRadius=21.26mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD28*\n21,1,0.08504,0.04646,0,0,0.0*\n21,1,0.04252,0.08898,0,0,0.0*\n1,1,0.04252,0.02126,-0.02323*\n1,1,0.04252,-0.02126,-0.02323*\n1,1,0.04252,-0.02126,0.02323*\n1,1,0.04252,0.02126,0.02323*\n%\nG04:AMPARAMS|DCode=29|XSize=19.68mil|YSize=23.62mil|CornerRadius=4.92mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD29*\n21,1,0.01968,0.01378,0,0,90.0*\n21,1,0.00984,0.02362,0,0,90.0*\n1,1,0.00984,0.00689,0.00492*\n1,1,0.00984,0.00689,-0.00492*\n1,1,0.00984,-0.00689,-0.00492*\n1,1,0.00984,-0.00689,0.00492*\n%\nG04:AMPARAMS|DCode=30|XSize=25mil|YSize=50mil|CornerRadius=6.25mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD30*\n21,1,0.02500,0.03750,0,0,0.0*\n21,1,0.01250,0.05000,0,0,0.0*\n1,1,0.01250,0.00625,-0.01875*\n1,1,0.01250,-0.00625,-0.01875*\n1,1,0.01250,-0.00625,0.01875*\n1,1,0.01250,0.00625,0.01875*\n%\nG04:AMPARAMS|DCode=31|XSize=65mil|YSize=120mil|CornerRadius=16.25mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD31*\n21,1,0.06500,0.08750,0,0,180.0*\n21,1,0.03250,0.12000,0,0,180.0*\n1,1,0.03250,-0.01625,0.04375*\n1,1,0.03250,0.01625,0.04375*\n1,1,0.03250,0.01625,-0.04375*\n1,1,0.03250,-0.01625,-0.04375*\n%\nG04:AMPARAMS|DCode=36|XSize=21.75mil|YSize=65.06mil|CornerRadius=6.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD36*\n21,1,0.02175,0.05118,0,0,90.0*\n21,1,0.00787,0.06506,0,0,90.0*\n1,1,0.01387,0.02559,0.00394*\n1,1,0.01387,0.02559,-0.00394*\n1,1,0.01387,-0.02559,-0.00394*\n1,1,0.01387,-0.02559,0.00394*\n%\nG04:AMPARAMS|DCode=37|XSize=45.37mil|YSize=65.06mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD37*\n21,1,0.04537,0.03937,0,0,90.0*\n21,1,0.01968,0.06506,0,0,90.0*\n1,1,0.02568,0.01968,0.00984*\n1,1,0.02568,0.01968,-0.00984*\n1,1,0.02568,-0.01968,-0.00984*\n1,1,0.02568,-0.01968,0.00984*\n%\nG04:AMPARAMS|DCode=38|XSize=26mil|YSize=26mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD38*\n21,1,0.02600,0.01000,0,0,0.0*\n21,1,0.01000,0.02600,0,0,0.0*\n1,1,0.01600,0.00500,-0.00500*\n1,1,0.01600,-0.00500,-0.00500*\n1,1,0.01600,-0.00500,0.00500*\n1,1,0.01600,0.00500,0.00500*\n%\nG04:AMPARAMS|DCode=39|XSize=29.62mil|YSize=45.37mil|CornerRadius=8.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD39*\n21,1,0.02962,0.02756,0,0,180.0*\n21,1,0.01181,0.04537,0,0,180.0*\n1,1,0.01781,-0.00591,0.01378*\n1,1,0.01781,0.00591,0.01378*\n1,1,0.01781,0.00591,-0.01378*\n1,1,0.01781,-0.00591,-0.01378*\n%\nG04:AMPARAMS|DCode=40|XSize=46mil|YSize=66mil|CornerRadius=13mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD40*\n21,1,0.04600,0.04000,0,0,180.0*\n21,1,0.02000,0.06600,0,0,180.0*\n1,1,0.02600,-0.01000,0.02000*\n1,1,0.02600,0.01000,0.02000*\n1,1,0.02600,0.01000,-0.02000*\n1,1,0.02600,-0.01000,-0.02000*\n%\nG04:AMPARAMS|DCode=41|XSize=22mil|YSize=22mil|CornerRadius=11mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD41*\n21,1,0.02200,0.00000,0,0,270.0*\n21,1,0.00000,0.02200,0,0,270.0*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n1,1,0.02200,0.00000,0.00000*\n%\nG04:AMPARAMS|DCode=42|XSize=45.37mil|YSize=65.06mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD42*\n21,1,0.04537,0.03937,0,0,0.0*\n21,1,0.01968,0.06506,0,0,0.0*\n1,1,0.02568,0.00984,-0.01968*\n1,1,0.02568,-0.00984,-0.01968*\n1,1,0.02568,-0.00984,0.01968*\n1,1,0.02568,0.00984,0.01968*\n%\nG04:AMPARAMS|DCode=43|XSize=21.75mil|YSize=65.06mil|CornerRadius=6.94mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD43*\n21,1,0.02175,0.05118,0,0,180.0*\n21,1,0.00787,0.06506,0,0,180.0*\n1,1,0.01387,-0.00394,0.02559*\n1,1,0.01387,0.00394,0.02559*\n1,1,0.01387,0.00394,-0.02559*\n1,1,0.01387,-0.00394,-0.02559*\n%\nG04:AMPARAMS|DCode=45|XSize=46mil|YSize=80mil|CornerRadius=13mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD45*\n21,1,0.04600,0.05400,0,0,90.0*\n21,1,0.02000,0.08000,0,0,90.0*\n1,1,0.02600,0.02700,0.01000*\n1,1,0.02600,0.02700,-0.01000*\n1,1,0.02600,-0.02700,-0.01000*\n1,1,0.02600,-0.02700,0.01000*\n%\nG04:AMPARAMS|DCode=46|XSize=65.06mil|YSize=45.37mil|CornerRadius=12.84mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=180.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD46*\n21,1,0.06506,0.01968,0,0,180.0*\n21,1,0.03937,0.04537,0,0,180.0*\n1,1,0.02568,-0.01968,0.00984*\n1,1,0.02568,0.01968,0.00984*\n1,1,0.02568,0.01968,-0.00984*\n1,1,0.02568,-0.01968,-0.00984*\n%\nG04:AMPARAMS|DCode=47|XSize=61mil|YSize=71mil|CornerRadius=16.75mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD47*\n21,1,0.06100,0.03750,0,0,90.0*\n21,1,0.02750,0.07100,0,0,90.0*\n1,1,0.03350,0.01875,0.01375*\n1,1,0.03350,0.01875,-0.01375*\n1,1,0.03350,-0.01875,-0.01375*\n1,1,0.03350,-0.01875,0.01375*\n%\nG04:AMPARAMS|DCode=48|XSize=25.68mil|YSize=29.62mil|CornerRadius=7.92mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=90.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD48*\n21,1,0.02568,0.01378,0,0,90.0*\n21,1,0.00984,0.02962,0,0,90.0*\n1,1,0.01584,0.00689,0.00492*\n1,1,0.01584,0.00689,-0.00492*\n1,1,0.01584,-0.00689,-0.00492*\n1,1,0.01584,-0.00689,0.00492*\n%\nG04:AMPARAMS|DCode=60|XSize=20mil|YSize=20mil|CornerRadius=5mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD60*\n21,1,0.02000,0.01000,0,0,270.0*\n21,1,0.01000,0.02000,0,0,270.0*\n1,1,0.01000,-0.00500,-0.00500*\n1,1,0.01000,-0.00500,0.00500*\n1,1,0.01000,0.00500,0.00500*\n1,1,0.01000,0.00500,-0.00500*\n%\nG04:AMPARAMS|DCode=61|XSize=37.64mil|YSize=63.38mil|CornerRadius=9.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD61*\n21,1,0.03764,0.04456,0,0,270.0*\n21,1,0.01882,0.06338,0,0,270.0*\n1,1,0.01882,-0.02228,-0.00941*\n1,1,0.01882,-0.02228,0.00941*\n1,1,0.01882,0.02228,0.00941*\n1,1,0.01882,0.02228,-0.00941*\n%\nG04:AMPARAMS|DCode=62|XSize=90.55mil|YSize=90.55mil|CornerRadius=22.64mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD62*\n21,1,0.09055,0.04528,0,0,0.0*\n21,1,0.04528,0.09055,0,0,0.0*\n1,1,0.04528,0.02264,-0.02264*\n1,1,0.04528,-0.02264,-0.02264*\n1,1,0.04528,-0.02264,0.02264*\n1,1,0.04528,0.02264,0.02264*\n%\nG04:AMPARAMS|DCode=63|XSize=200mil|YSize=80mil|CornerRadius=20mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD63*\n21,1,0.20000,0.04000,0,0,270.0*\n21,1,0.16000,0.08000,0,0,270.0*\n1,1,0.04000,-0.02000,-0.08000*\n1,1,0.04000,-0.02000,0.08000*\n1,1,0.04000,0.02000,0.08000*\n1,1,0.04000,0.02000,-0.08000*\n%\nG04:AMPARAMS|DCode=64|XSize=21.65mil|YSize=57.09mil|CornerRadius=5.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD64*\n21,1,0.02165,0.04626,0,0,270.0*\n21,1,0.01083,0.05709,0,0,270.0*\n1,1,0.01083,-0.02313,-0.00541*\n1,1,0.01083,-0.02313,0.00541*\n1,1,0.01083,0.02313,0.00541*\n1,1,0.01083,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=65|XSize=21.65mil|YSize=57.09mil|CornerRadius=5.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD65*\n21,1,0.02165,0.04626,0,0,270.0*\n21,1,0.01083,0.05709,0,0,270.0*\n1,1,0.01083,-0.02313,-0.00541*\n1,1,0.01083,-0.02313,0.00541*\n1,1,0.01083,0.02313,0.00541*\n1,1,0.01083,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=66|XSize=23.62mil|YSize=35mil|CornerRadius=5.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD66*\n21,1,0.02362,0.02319,0,0,0.0*\n21,1,0.01181,0.03500,0,0,0.0*\n1,1,0.01181,0.00591,-0.01159*\n1,1,0.01181,-0.00591,-0.01159*\n1,1,0.01181,-0.00591,0.01159*\n1,1,0.01181,0.00591,0.01159*\n%\nG04:AMPARAMS|DCode=67|XSize=27.56mil|YSize=51.18mil|CornerRadius=6.89mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD67*\n21,1,0.02756,0.03740,0,0,0.0*\n21,1,0.01378,0.05118,0,0,0.0*\n1,1,0.01378,0.00689,-0.01870*\n1,1,0.01378,-0.00689,-0.01870*\n1,1,0.01378,-0.00689,0.01870*\n1,1,0.01378,0.00689,0.01870*\n%\nG04:AMPARAMS|DCode=74|XSize=26mil|YSize=26mil|CornerRadius=8mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD74*\n21,1,0.02600,0.01000,0,0,270.0*\n21,1,0.01000,0.02600,0,0,270.0*\n1,1,0.01600,-0.00500,-0.00500*\n1,1,0.01600,-0.00500,0.00500*\n1,1,0.01600,0.00500,0.00500*\n1,1,0.01600,0.00500,-0.00500*\n%\nG04:AMPARAMS|DCode=75|XSize=96.55mil|YSize=96.55mil|CornerRadius=25.64mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD75*\n21,1,0.09655,0.04528,0,0,0.0*\n21,1,0.04528,0.09655,0,0,0.0*\n1,1,0.05128,0.02264,-0.02264*\n1,1,0.05128,-0.02264,-0.02264*\n1,1,0.05128,-0.02264,0.02264*\n1,1,0.05128,0.02264,0.02264*\n%\nG04:AMPARAMS|DCode=76|XSize=206mil|YSize=86mil|CornerRadius=23mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD76*\n21,1,0.20600,0.04000,0,0,270.0*\n21,1,0.16000,0.08600,0,0,270.0*\n1,1,0.04600,-0.02000,-0.08000*\n1,1,0.04600,-0.02000,0.08000*\n1,1,0.04600,0.02000,0.08000*\n1,1,0.04600,0.02000,-0.08000*\n%\nG04:AMPARAMS|DCode=77|XSize=27.65mil|YSize=63.09mil|CornerRadius=8.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD77*\n21,1,0.02765,0.04626,0,0,270.0*\n21,1,0.01083,0.06309,0,0,270.0*\n1,1,0.01683,-0.02313,-0.00541*\n1,1,0.01683,-0.02313,0.00541*\n1,1,0.01683,0.02313,0.00541*\n1,1,0.01683,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=78|XSize=27.65mil|YSize=63.09mil|CornerRadius=8.41mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=270.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD78*\n21,1,0.02765,0.04626,0,0,270.0*\n21,1,0.01083,0.06309,0,0,270.0*\n1,1,0.01683,-0.02313,-0.00541*\n1,1,0.01683,-0.02313,0.00541*\n1,1,0.01683,0.02313,0.00541*\n1,1,0.01683,0.02313,-0.00541*\n%\nG04:AMPARAMS|DCode=79|XSize=29.62mil|YSize=41mil|CornerRadius=8.91mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD79*\n21,1,0.02962,0.02319,0,0,0.0*\n21,1,0.01181,0.04100,0,0,0.0*\n1,1,0.01781,0.00591,-0.01159*\n1,1,0.01781,-0.00591,-0.01159*\n1,1,0.01781,-0.00591,0.01159*\n1,1,0.01781,0.00591,0.01159*\n%\nG04:AMPARAMS|DCode=80|XSize=33.56mil|YSize=57.18mil|CornerRadius=9.89mil|HoleSize=0mil|Usage=FLASHONLY|Rotation=0.000|XOffset=0mil|YOffset=0mil|HoleType=Round|Shape=RoundedRectangle|*\n%AMROUNDEDRECTD80*\n21,1,0.03356,0.03740,0,0,0.0*\n21,1,0.01378,0.05718,0,0,0.0*\n1,1,0.01978,0.00689,-0.01870*\n1,1,0.01978,-0.00689,-0.01870*\n1,1,0.01978,-0.00689,0.01870*\n1,1,0.01978,0.00689,0.01870*\n%\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.DRR",
    "content": "----------------------------------------------------------------------------------------------------------------------------------\nNCDrill File Report For: Motor-57.PcbDoc   ܶ 01-18  19:39:57\n----------------------------------------------------------------------------------------------------------------------------------\n\nLayer Pair : Top1 to Bottom4\nASCII RoundHoles File : Motor-57.TXT\n\nTool       Hole Size               Hole Tolerance               Hole Type       Hole Count   Plated         Tool Travel\n----------------------------------------------------------------------------------------------------------------------------------\nT1      10mil (0.254mm)                                           Round             146       PTH        12.15inch (308.67mm)\nT2      16mil (0.4mm)                                             Round             139       PTH        7.73inch (196.44mm)\nT3      122mil (3.1mm)                                            Round             4         PTH        4.08inch (103.55mm)\n----------------------------------------------------------------------------------------------------------------------------------\nTotals                                                                              289\n\nTotal Processing Time (hh:mm:ss) : 00:00:00\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.EXTREP",
    "content": "------------------------------------------------------------------------------------------\nGerber File Extension Report For: Motor-57.GBR   ܶ 01-18  19:39:48\n------------------------------------------------------------------------------------------\n\n\n------------------------------------------------------------------------------------------\nLayer Extension     Layer Description                      \n------------------------------------------------------------------------------------------\n.GTO                Top Overlay                             \n.GTP                Top Paste                               \n.GTS                Top Solder                              \n.GTL                Top1                                    \n.G1                 Signal2                                 \n.G2                 Gnd3                                    \n.GBL                Bottom4                                 \n.GBS                Bottom Solder                           \n.GBP                Bottom Paste                            \n.GBO                Bottom Overlay                          \n.GM1                Mechanical 1                            \n.GM10               Mechanical 10                           \n.GM12               Mechanical 12                           \n.GM13               Mechanical 13                           \n.GM14               Mechanical 14                           \n.GM15               Mechanical 15                           \n.GKO                Keep-Out Layer                          \n.GPT                Top Pad Master                          \n.GPB                Bottom Pad Master                       \n.GD1                Drill Drawing                           \n.GG1                Drill Guide                             \n------------------------------------------------------------------------------------------\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.G1",
    "content": "G04*\nG04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*\nG04*\nG04 Layer_Physical_Order=2*\nG04 Layer_Color=14461039*\n%FSLAX25Y25*%\n%MOIN*%\nG70*\nG04*\nG04 #@! TF.SameCoordinates,A7353FC2-99F2-474C-B2A2-24993EA34B63*\nG04*\nG04*\nG04 #@! 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    "content": "G04*\nG04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*\nG04*\nG04 Layer_Color=8388736*\n%FSLAX25Y25*%\n%MOIN*%\nG70*\nG04*\nG04 #@! TF.SameCoordinates,A7353FC2-99F2-474C-B2A2-24993EA34B63*\nG04*\nG04*\nG04 #@! TF.FilePolarity,Positive*\nG04*\nG01*\nG75*\n%ADD13C,0.00787*%\nD13*\nX-29740Y50398D02*\nX-22260D01*\nY35602D02*\nY50398D01*\nX-29740Y35602D02*\nX-22260D01*\nX-29740D02*\nY50398D01*\nX22260Y35602D02*\nY50398D01*\nY35602D02*\nX29740D01*\nY50398D01*\nX22260D02*\nX29740D01*\nX-39291Y-17850D02*\nX-10709D01*\nY-34150D02*\nY-17850D01*\nX-39291Y-34150D02*\nX-10709D01*\nX-39291D02*\nY-17850D01*\nX19988Y-25437D02*\nY-17563D01*\nY-25437D02*\nX31012D01*\nY-17563D01*\nX19988D02*\nX31012D01*\nM02*\n"
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    "content": "G04*\nG04 #@! TF.GenerationSoftware,Altium Limited,Altium Designer,22.0.2 (36)*\nG04*\nG04 Layer_Color=32896*\n%FSLAX25Y25*%\n%MOIN*%\nG70*\nG04*\nG04 #@! TF.SameCoordinates,A7353FC2-99F2-474C-B2A2-24993EA34B63*\nG04*\nG04*\nG04 #@! TF.FilePolarity,Positive*\nG04*\nG01*\nG75*\n%ADD13C,0.00787*%\nD13*\nX-29051Y49102D02*\nX-22949D01*\nY36898D02*\nY49102D01*\nX-29051Y36898D02*\nX-22949D01*\nX-29051D02*\nY49102D01*\nX22949Y36898D02*\nY49102D01*\nY36898D02*\nX29051D01*\nY49102D01*\nX22949D02*\nX29051D01*\nX-34350Y-18244D02*\nX-15650D01*\nY-33756D02*\nY-18244D01*\nX-34350Y-33756D02*\nX-15650D01*\nX-34350D02*\nY-18244D01*\nX21169Y-25043D02*\nY-17957D01*\nY-25043D02*\nX29831D01*\nY-17957D01*\nX21169D02*\nX29831D01*\nM02*\n"
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    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.GTL",
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  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.LDP",
    "content": "Layer Pairs Export File for PCB: I:\\onWorking\\Dummy-Robot\\1.Hardware\\MotorDriver-57-unused\\Motor-57.PcbDoc\nLayersSetName=Top_Bot_Thru_Holes|DrillFile=motor-57.txt|DrillLayers=gtl,g1,g2,gbl\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.REP",
    "content": "*************************************************************\nFileName = Motor-57.GBR\nAutoAperture = True\n*************************************************************\nGenerating : Mechanical 15\n      File : Motor-57.GM15\n\n    Adding Layer      : Mechanical 15\n\n\nUsed DCodes :\n    D13\n    D85\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 14\n      File : Motor-57.GM14\n\n    Adding Layer      : Mechanical 14\n\n\nUsed DCodes :\n    D86\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 13\n      File : Motor-57.GM13\n\n    Adding Layer      : Mechanical 13\n\n\nUsed DCodes :\n    D85\n    D86\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 12\n      File : Motor-57.GM12\n\n    Adding Layer      : Mechanical 12\n\n\nUsed DCodes :\n    D13\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 10\n      File : Motor-57.GM10\n\n    Adding Layer      : Mechanical 10\n\n\nUsed DCodes :\n    D13\n*************************************************************\n\n*************************************************************\nGenerating : Mechanical 1\n      File : Motor-57.GM1\n\n    Adding Layer      : Mechanical 1\n\n\nUsed DCodes :\n    D10\n*************************************************************\n\n*************************************************************\nGenerating : Keep-Out Layer\n      File : Motor-57.GKO\n\n    Adding Layer      : Keep-Out Layer\n\n\nUsed DCodes :\n    D10\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Overlay\n      File : Motor-57.GBO\n\n    Adding Layer      : Bottom Overlay\n\n\nUsed DCodes :\n    D12\n    D13\n    D14\n    D84\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Paste\n      File : Motor-57.GBP\n\n    Adding Layer      : Bottom Paste\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D18\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Solder\n      File : Motor-57.GBS\n\n    Adding Layer      : Bottom Solder\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D38\n    D49\n    D61\n    D73\n    D74\n    D75\n    D76\n    D77\n    D78\n    D79\n    D80\n    D81\n    D82\n    D83\n*************************************************************\n\n*************************************************************\nGenerating : Top Solder\n      File : Motor-57.GTS\n\n    Adding Layer      : Top Solder\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D28\n    D30\n    D31\n    D32\n    D33\n    D34\n    D35\n    D36\n    D37\n    D38\n    D39\n    D40\n    D41\n    D42\n    D43\n    D44\n    D45\n    D46\n    D47\n    D48\n    D49\n*************************************************************\n\n*************************************************************\nGenerating : Top Paste\n      File : Motor-57.GTP\n\n    Adding Layer      : Top Paste\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n*************************************************************\n\n*************************************************************\nGenerating : Top Overlay\n      File : Motor-57.GTO\n\n    Adding Layer      : Top Overlay\n\n\nUsed DCodes :\n    D10\n    D11\n    D12\n    D13\n    D14\n    D15\n*************************************************************\n\n*************************************************************\nGenerating : Top Pad Master\n      File : Motor-57.GPT\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n    D54\n*************************************************************\n\n*************************************************************\nGenerating : Bottom Pad Master\n      File : Motor-57.GPB\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D18\n    D54\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n*************************************************************\n\n*************************************************************\nGenerating : Bottom4\n      File : Motor-57.GBL\n\n    Adding Layer      : Bottom4\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D18\n    D50\n    D54\n    D55\n    D56\n    D57\n    D58\n    D59\n    D60\n    D61\n    D62\n    D63\n    D64\n    D65\n    D66\n    D67\n    D68\n    D69\n    D70\n    D71\n    D72\n*************************************************************\n\n*************************************************************\nGenerating : Gnd3\n      File : Motor-57.G2\n\n    Adding Layer      : Gnd3\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D54\n    D55\n    D56\n*************************************************************\n\n*************************************************************\nGenerating : Signal2\n      File : Motor-57.G1\n\n    Adding Layer      : Signal2\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D50\n    D54\n    D55\n    D56\n    D57\n    D58\n*************************************************************\n\n*************************************************************\nGenerating : Top1\n      File : Motor-57.GTL\n\n    Adding Layer      : Top1\n\n    Adding Layer      : Multi-Layer\n\n\nUsed DCodes :\n    D10\n    D11\n    D14\n    D16\n    D17\n    D18\n    D19\n    D20\n    D21\n    D22\n    D23\n    D24\n    D25\n    D26\n    D27\n    D28\n    D29\n    D30\n    D50\n    D51\n    D52\n    D53\n    D54\n    D55\n    D56\n*************************************************************\n\n*************************************************************\nGenerating : Drill Drawing\n      File : Motor-57.GD1\n\n    Adding Drill Pair : Top1-Bottom4\n\n    Adding Layer      : Drill Drawing\n\n\nUsed DCodes :\n    D86\n    D87\n*************************************************************\n\n*************************************************************\nGenerating : Drill Guide\n      File : Motor-57.GG1\n\n    Adding Drill Pair : Top1-Bottom4\n\n    Adding Layer      : Drill Guide\n\n\nUsed DCodes :\n    D86\n*************************************************************\n\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.RUL",
    "content": "DRC Rules Export File for PCB: I:\\onWorking\\Dummy-Robot\\1.Hardware\\MotorDriver-57-unused\\Motor-57.PcbDoc\nRuleKind=Width|RuleName=VCC|Scope=Board|Minimum=4.00\nRuleKind=Width|RuleName=GND|Scope=Board|Minimum=4.00\nRuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=3.00\nRuleKind=Width|RuleName=Width|Scope=Board|Minimum=4.00\nRuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=4.00\nRuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.TXT",
    "content": "M48\n;Layer_Color=9474304\n;FILE_FORMAT=2:5\nINCH,TZ\n;TYPE=PLATED\nT1F00S00C0.01000\nT2F00S00C0.01575\nT3F00S00C0.12205\n%\nT01\nX-78400Y-53500\nX-73500Y-55000\nY-52000\nX-71366Y-45734\nX-77000Y-37500\nY-34000\nY-30500\nY-21000\nX-70800Y-3100\nX-77000Y13000\nY24000\nY30000\nY36000\nX-60000Y36400\nX-59900Y40300\nY32500\nX-53700Y30300\nX-56600Y26900\nX-57000Y23500\nX-53800\nX-59000Y17500\nX-56300Y12500\nX-57500Y5000\nX-54300Y4800\nX-50400\nX-45000Y5000\nX-41000\nY2500\nX-33500Y2000\nY5500\nX-35300Y-8400\nX-31800Y-12300\nX-35000Y-16500\nX-38000Y-17000\nX-40500\nX-42700Y-10600\nX-51900Y-11100\nX-51400Y-14500\nX-56300Y-13100\nX-55784Y-19016\nX-55500Y-23000\nY-25500\nY-28000\nX-51500Y-31600\nX-51000Y-22000\nX-66000\nX-66500Y-15500\nX-66600Y-2500\nX-67500Y100\nX-60500Y3000\nX-56500Y700\nX-52358Y658\nX-44300Y26900\nX-44100Y31200\nX-14500Y31000\nX-9500\nX0Y37000\nY43500\nX9500Y31000\nX14500\nX10800Y7500\nX15800Y300\nX15500Y-13000\nX18000\nX20500\nX23000\nX25500\nY-15500\nX23000\nX19900Y-17400\nX18000Y-16300\nX15800\nX19800Y-22100\nX22454Y-21500\nX28500Y-21200\nY-18700\nY-16400\nX32500Y-16500\nY-19500\nY-22500\nY-25500\nY-28500\nY-31500\nY-34500\nY-37500\nX27000Y-49500\nX27300Y-52900\nX29500Y-52300\nX24000Y-57500\nX8500Y-51100\nX2500Y-47500\nX-2000Y-41500\nX-5000\nX-3500Y-38000\nY-35000\nX300Y-36200\nY-38700\nX240Y-33540\nX-11500Y-31900\nX-10800Y-44100\nX-12500Y-45800\nX-28500Y-43000\nX-27000Y-40500\nY-38000\nX-23500\nX-34620Y-41200\nX-39700Y-41600\nX-37700Y-43700\nX-36600Y-33400\nX-38600Y-31800\nX-40547Y-33553\nX-57000Y-37000\nX-58500Y-41000\nX-56500Y-42500\nX-54300Y-41000\nX-52100Y-42400\nX-62100Y-42600\nX-37500Y-59000\nX-34500\nX-28000Y-63000\nX-2000Y-65500\nX1969Y-62500\nX5500Y-24100\nX8500\nY-21000\nX5500\nX-5000Y-20000\nY-23000\nX-22500Y-19300\nX-18300Y-4200\nX-11400Y-7500\nX-10600Y2500\nX-11000Y5500\nX-13500\nY9500\nX-11000\nX29300Y-4100\nY-7200\nX50000\nY-4000\nX73000Y-4700\nY3500\nX32100Y53700\nX28100Y54000\nX17000Y-32500\nY-35000\nT02\nX-20000Y-72000\nX-17000\nX-14000\nY-69000\nX-17000\nX-20000\nY-66000\nX-17000\nX-14000\nX19000Y-75500\nY-78500\nX22000\nX25000\nX28000\nX31000\nX34000\nX37000\nX40000Y-73000\nY-70000\nY-67000\nX43000\nX46000\nY-70000\nX43000\nY-73000\nX46000\nX70000Y-18000\nY-15000\nX73000\nX76000\nY-12000\nX73000\nX70000\nX73000Y-18000\nX76000\nY12000\nX73000\nY15000\nY18000\nX76000\nY15000\nX70000\nY12000\nY18000\nX32000Y16000\nX29000\nX26000\nX23000\nX20000\nX17000\nX14000\nX11000\nX8000\nX5000\nX2000\nX-1000\nX-4000\nX-7000\nX-10000\nX-13000\nX-16000\nX-19000\nX-19500Y38000\nY41000\nY44000\nX-15000Y43000\nY46000\nX-12000\nX-9000\nY43000\nY40000\nX-12000\nX-15000\nX-12000Y43000\nX-4200Y42100\nY45100\nY39100\nX4300\nY42100\nY45100\nX9000Y46000\nY43000\nX12000\nX15000\nY40000\nX12000\nX9000\nX12000Y46000\nX15000\nX19300Y44700\nY41700\nY38700\nX33100Y38400\nY41400\nY44400\nY35400\nY32400\nY29400\nX4500Y52100\nY55100\nX1500\nY52100\nX-19500\nX-22500\nY55100\nX-19500\nX-27500Y60000\nX-30500\nY63000\nY66000\nX-27500\nY63000\nX-33500\nY60000\nX-36500\nX-39500\nY63000\nY66000\nX-36500\nX-33500\nX-36500Y63000\nX-42500\nY60000\nY66000\nX-34200Y52000\nY49000\nY46000\nY43000\nY40000\nY37000\nX-33500Y-21500\nY-24500\nY-27500\nX-36546\nY-24500\nY-21500\nX-39592\nY-24566\nY-27500\nT03\nX-98287Y-52776\nY52776\nX98287\nY-52776\nM30\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Motor-57.apr",
    "content": "D10   ROUNDED            10.000      10.000       0.000  LINE       0.000\nD11   ROUNDED             4.000       4.000       0.000  LINE       0.000\nD12   ROUNDED             1.000       1.000       0.000  LINE       0.000\nD13   ROUNDED             7.874       7.874       0.000  LINE       0.000\nD14   ROUNDED             6.000       6.000       0.000  LINE       0.000\nD15   ROUNDED             5.000       5.000       0.000  LINE       0.000\nD24   RECTANGULAR        19.685      19.685       0.000 FLASH     270.000\nD32   RECTANGULAR        65.000      60.000       0.000 FLASH       0.000\nD33   RECTANGULAR        77.000      25.000       0.000 FLASH       0.000\nD34   RECTANGULAR        89.000     211.000       0.000 FLASH       0.000\nD35   RECTANGULAR       100.000     100.000       0.000 FLASH       0.000\nD44   RECTANGULAR        25.685      25.685       0.000 FLASH     270.000\nD49   ROUNDED           206.000     206.000       0.000 FLASH       0.000\nD50   ROUNDED            20.000      20.000       0.000  LINE       0.000\nD51   ROUNDED            80.000      80.000       0.000  LINE       0.000\nD52   ROUNDED            40.000      40.000       0.000  LINE       0.000\nD53   ROUNDED            30.000      30.000       0.000  LINE       0.000\nD54   ROUNDED           200.000     200.000       0.000 FLASH       0.000\nD55   ROUNDED            18.000      18.000       0.000 FLASH       0.000\nD56   ROUNDED            23.622      23.622       0.000 FLASH       0.000\nD57   ROUNDED            70.000      70.000       0.000  LINE       0.000\nD58   ROUNDED             7.000       7.000       0.000  LINE       0.000\nD59   ROUNDED            19.685      51.181       0.000 FLASH       0.000\nD68   ROUNDED            19.685      51.181       0.000 FLASH     270.000\nD69   ROUNDED            12.000      54.000       0.000 FLASH       0.000\nD70   ROUNDED            12.000      54.000       0.000 FLASH     270.000\nD71   ROUNDED            25.000      25.000       0.000  LINE       0.000\nD72   ROUNDED            45.000      45.000       0.000  LINE       0.000\nD73   ROUNDED            25.685      57.181       0.000 FLASH       0.000\nD81   ROUNDED            25.685      57.181       0.000 FLASH     270.000\nD82   ROUNDED            18.000      60.000       0.000 FLASH       0.000\nD83   ROUNDED            18.000      60.000       0.000 FLASH     270.000\nD84   ROUNDED             9.842       9.842       0.000  LINE       0.000\nD85   ROUNDED             3.937       3.937       0.000  LINE       0.000\nD86   ROUNDED             2.000       2.000       0.000  LINE       0.000\nD87   ROUNDED             2.667       2.667       0.000  LINE       0.000\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Gerber/Status Report.Txt",
    "content": "Output: NC Drill Files\nType  : NC Drill\nFrom  : Project [Motor-57.PrjPCB]\n   Generated File[Motor-57.TXT]\n   Generated File[Motor-57.LDP]\n   Generated File[Motor-57.DRR]\n\n\nFiles Generated   : 3\nDocuments Printed : 0\n\nFinished Output Generation At 19:39:57 On ܶ 01-18\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Motor-57.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=0\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=1\nAppendSheetNumberToLocalNets=0\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=0\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\nCrossRefSheetStyle=1\nCrossRefLocationStyle=1\nCrossRefPorts=3\nCrossRefCrossSheets=1\nCrossRefSheetEntries=0\nCrossRefFollowFromMainSettings=1\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Drive.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=OTRBEYFQ\n\n[Document2]\nDocumentPath=MCU.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=MMRIIHEF\n\n[Document3]\nDocumentPath=Port.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=2\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=ZMLSMFEG\n\n[Document4]\nDocumentPath=Power.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=3\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RMXANKZL\n\n[Document5]\nDocumentPath=Interface.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=4\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=DXHCOWHD\n\n[Document6]\nDocumentPath=Motor-57.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=RPGXAMXA\n\n[GeneratedDocument1]\nDocumentPath=Project Outputs for Motor-57\\Design Rule Check - Motor-57.html\nDItemRevisionGUID=\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Mask\nOutputName1=Solder/Paste Mask Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Drill\nOutputName2=Drill Drawing/Guides\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=CompositeDrill\nOutputName3=Composite Drill Drawing\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=IPC2581\nOutputName4=IPC-2581 Files\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Gerber X2\nOutputName5=Gerber X2 Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Board Stack Report\nOutputName7=Report Board Stack\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Plane\nOutputName8=Power-Plane Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=ODB\nOutputName9=ODB++ Files\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nOutputType10=NC Drill\nOutputName10=NC Drill Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nConfiguration10_Name1=ForceUpdateSettings\nConfiguration10_Item1=False\nConfiguration10_Name2=OutputConfigurationParameter1\nConfiguration10_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\Ctrl-Step-Drive\\1.Hardware\\Unibody\\Motor-42\\Motor-42.PcbDoc\nOutputType11=Test Points\nOutputName11=Test Point Report\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777218~1,16777219~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\Ctrl-Step-Drive\\1.Hardware\\Unibody\\Motor-42\\Motor-42.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=BOM_ReportCompare\nOutputName7=BOM Compare\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Export Comments\nOutputName8=Export Comments\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/MotorDriver-57-unused/Motor-57.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Drive.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Interface.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=MCU.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Port.SchDoc|SheetNumber=1\nRecord=NoMainPathDocument|SourceDocument=Drive.SchDoc|FileName=Power.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/REF/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/REF/REF-Base/.gitignore",
    "content": "History\nProject Logs for*\nProject Outputs for*\n__Previews"
  },
  {
    "path": "1.Hardware/REF/REF-Base/REF-Base.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=2\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=0\nAppendSheetNumberToLocalNets=1\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=1\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Main.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=QVBBULDQ\n\n[Document2]\nDocumentPath=REF-Base.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=SPYPGENJ\n\n[SearchPath1]\nPath=E:\\OneDrive\\[软件配置备份]\\Altium Designer\\1.元件库\\*.*\nIncludeSubFolders=1\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Plane\nOutputName1=Power-Plane Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Board Stack Report\nOutputName2=Report Board Stack\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=ODB\nOutputName3=ODB++ Files\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Test Points\nOutputName4=Test Point Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=NC Drill\nOutputName5=NC Drill Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nConfiguration5_Name1=ForceUpdateSettings\nConfiguration5_Item1=False\nConfiguration5_Name2=OutputConfigurationParameter1\nConfiguration5_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\REF-STM32F4-dev\\1.Hardware\\REF\\REF-Base\\REF-Base.PcbDoc\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Drill\nOutputName7=Drill Drawing/Guides\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=CompositeDrill\nOutputName9=Composite Drill Drawing\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType10=Gerber X2\nOutputName10=Gerber X2 Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908298~1,16908300~1,16908301~1,16908302~1,16908303~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\REF-STM32F4-dev\\1.Hardware\\REF\\REF-Base\\REF-Base.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Export Comments\nOutputName7=Export Comments\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=BOM_ReportCompare\nOutputName8=BOM Compare\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/REF/REF-Base/REF-Base.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/REF/REF-Unit/REF-Unit.PrjPCB",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=2\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=0\nAppendSheetNumberToLocalNets=1\nNetlistSinglePinNets=0\nDefaultConfiguration=Default Configuration\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=1\nAutoSheetNumbering=0\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=1\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=1\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=33A43DB9-A699-40BA-9058-E8C83D527678\nVaultGUID=53F48F8D-0842-4B75-8A0D-548028E961BE\nReleaseVaultName=稚晖君的DigiPCBA创作空间\nItemGUID=33A43DB9-A699-40BA-9058-E8C83D527678\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=Main.SchDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=0\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=QVBBULDQ\n\n[Document2]\nDocumentPath=REF-Unit.PcbDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=SPYPGENJ\n\n[SearchPath1]\nPath=E:\\OneDrive\\[软件配置备份]\\Altium Designer\\1.元件库\\*.*\nIncludeSubFolders=1\n\n[Configuration1]\nName=Default Configuration\nParameterCount=0\nConstraintFileCount=0\nReleaseItemId=\nVariant=[No Variations]\nOutputJobsCount=0\nContentTypeGUID=\nConfigurationType=\n\n[Generic_SmartPDF]\nAutoOpenFile=-1\nAutoOpenOutJob=-1\n\n[Generic_SmartPDFSettings]\nProjectMode=0\nZoomPrecision=50\nAddNetsInformation=-1\nAddNetPins=-1\nAddNetNetLabels=-1\nAddNetPorts=-1\nShowComponentParameters=-1\nGlobalBookmarks=0\nExportBOM=-1\nTemplateFilename=Board Stack Report.XLT\nTemplateStoreRelative=-1\nPCB_PrintColor=1\nSCH_PrintColor=0\nPrintQuality=-3\nSCH_ShowNoErc=-1\nSCH_ShowParameter=-1\nSCH_ShowProbes=-1\nSCH_ShowBlankets=-1\nSCH_NoERCSymbolsToShow=\"Thin Cross\",\"Thick Cross\",\"Small Cross\",Checkbox,Triangle\nSCH_ShowNote=-1\nSCH_ShowNoteCollapsed=-1\nSCH_ExpandLogicalToPhysical=-1\nSCH_VariantName=\nSCH_ExpandComponentDesignators=-1\nSCH_ExpandNetlabels=0\nSCH_ExpandPorts=0\nSCH_ExpandSheetNumber=0\nSCH_ExpandDocumentNumber=0\nSCH_HasExpandLogicalToPhysicalSheets=0\nSaveSettingsToOutJob=0\n\n[Generic_EDE]\nOutputDir=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=PCADNetlist\nOutputName1=PCAD Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CadnetixNetlist\nOutputName2=Cadnetix Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=CalayNetlist\nOutputName3=Calay Netlist\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EDIF\nOutputName4=EDIF for PCB\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=EESofNetlist\nOutputName5=EESof Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=IntergraphNetlist\nOutputName6=Intergraph Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MentorBoardStationNetlist\nOutputName7=Mentor BoardStation Netlist\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MultiWire\nOutputName8=MultiWire\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=OrCadPCB2Netlist\nOutputName9=Orcad/PCB2 Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=PADSNetlist\nOutputName10=PADS ASCII Netlist\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Pcad\nOutputName11=Pcad for PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=E:\\厩砃舱\\ゅЩ\\My Protel\\STM32F103C8\\STM32F103C8_PCB.PcbDoc\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=2|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=0|PaperKind=A4\nConfiguration1_Name1=OutputConfigurationParameter1\nConfiguration1_Item1=PrintArea=SpecificArea|PrintAreaLowerLeftCornerX=27900000|PrintAreaLowerLeftCornerY=21300000|PrintAreaUpperRightCornerX=44800000|PrintAreaUpperRightCornerY=37100000|Record=PcbPrintView\nConfiguration1_Name2=OutputConfigurationParameter2\nConfiguration1_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=True|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=True|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration1_Name3=OutputConfigurationParameter3\nConfiguration1_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration1_Name4=OutputConfigurationParameter4\nConfiguration1_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType5=Report Print\nOutputName5=Report Prints\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType6=Schematic Print\nOutputName6=Schematic Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=SimView Print\nOutputName7=SimView Prints\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=PCBLIB Print\nOutputName8=PCBLIB Prints\nOutputDocumentPath8=C:\\Users\\Pengzhihui\\Desktop\\onWorking\\NanoPi\\PcbLib\\mLib.PcbLib\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=12.85|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration8_Name1=OutputConfigurationParameter1\nConfiguration8_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration8_Name2=OutputConfigurationParameter2\nConfiguration8_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration8_Name3=OutputConfigurationParameter3\nConfiguration8_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name4=OutputConfigurationParameter4\nConfiguration8_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration8_Name5=OutputConfigurationParameter5\nConfiguration8_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nOutputType9=PCBDrawing\nOutputName9=Draftsman\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=PDF3D\nOutputName10=PDF3D\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=PDF3D MBA\nOutputName11=PDF3D MBA\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Plane\nOutputName1=Power-Plane Prints\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Board Stack Report\nOutputName2=Report Board Stack\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=ODB\nOutputName3=ODB++ Files\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Test Points\nOutputName4=Test Point Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=NC Drill\nOutputName5=NC Drill Files\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nConfiguration5_Name1=ForceUpdateSettings\nConfiguration5_Item1=False\nConfiguration5_Name2=OutputConfigurationParameter1\nConfiguration5_Item2=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateEIADrillFile=False|GenerateSeparatePlatedNonPlatedFiles=False|NumberOfDecimals=5|NumberOfUnits=2|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Imperial|ZeroesMode=SuppressLeadingZeroes|DocumentPath=I:\\onWorking\\_Private\\REF-STM32F4\\1.Hardware\\REF\\REF-Unit\\REF-Unit.PcbDoc\nOutputType6=Final\nOutputName6=Final Artwork Prints\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType7=Drill\nOutputName7=Drill Drawing/Guides\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType9=CompositeDrill\nOutputName9=Composite Drill Drawing\nOutputDocumentPath9=\nOutputVariantName9=[No Variations]\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType10=Gerber X2\nOutputName10=Gerber X2 Files\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=IPC2581\nOutputName11=IPC-2581 Files\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=Gerber\nOutputName12=Gerber Files\nOutputDocumentPath12=\nOutputVariantName12=[No Variations]\nOutputDefault12=0\nConfiguration12_Name1=ForceUpdateSettings\nConfiguration12_Item1=False\nConfiguration12_Name2=OutputConfigurationParameter1\nConfiguration12_Item2=AddToAllLayerClasses.Set= |AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=200000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Imperial|GerberUnit=Imperial|IncludeUnconnectedMidLayerPads=False|LayerClassesMirror.Set= |LayerClassesPlot.Set= |LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=40|MinusApertureTolerance=40|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NoRegularPolygons=False|NumberOfDecimals=5|NumberOfDecimals=5|OptimizeChangeLocationCommands=True|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TPlotLayerStateArray,16973830~1,16973832~1,16973834~1,16777217~1,16777219~1,16777218~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16908298~1,16908301~1,16908302~1,16908303~1,16973837~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=True|PlotUsedDrillGuideLayerPairs=True|PlusApertureTolerance=40|PlusApertureTolerance=40|Record=GerberView|SoftwareArcs=False|Sorted=False|Sorted=False|DocumentPath=I:\\onWorking\\_Private\\REF-STM32F4\\1.Hardware\\REF\\REF-Unit\\REF-Unit.PcbDoc\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=ReportHierarchy\nOutputName3=Report Project Hierarchy\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nOutputType4=Script\nOutputName4=Script Output\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=SimpleBOM\nOutputName5=Simple BOM\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SinglePinNetReporter\nOutputName6=Report Single Pin Nets\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Export Comments\nOutputName7=Export Comments\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=BOM_ReportCompare\nOutputName8=BOM Compare\nOutputDocumentPath8=\nOutputVariantName8=[No Variations]\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Design Rules Check\nOutputName1=Design Rules Check\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType2=Differences Report\nOutputName2=Differences Report\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType3=Electrical Rules Check\nOutputName3=Electrical Rules Check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nOutputType4=Footprint Comparison Report\nOutputName4=Footprint Comparison Report\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=Configuration compliance\nOutputName5=Environment configuration compliance check\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=Component states check\nOutputName6=Server's components states check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=BOM_Violations\nOutputName7=BOM Checks Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=ExportSTEP\nOutputName1=Export STEP\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nOutputType2=ExportIDF\nOutputName2=Export IDF\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=AutoCAD dwg/dxf PCB\nOutputName3=AutoCAD dwg/dxf File PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=AutoCAD dwg/dxf Schematic\nOutputName4=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=ExportPARASOLID\nOutputName5=Export PARASOLID\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=Save As/Export PCB\nOutputName7=Save As/Export PCB\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Save As/Export Schematic\nOutputName8=Save As/Export Schematic\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Specctra Design PCB\nOutputName9=Specctra Design PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=MBAExportPARASOLID\nOutputName10=Export PARASOLID\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=MBAExportSTEP\nOutputName11=Export STEP\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=0\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=0\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=1\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=3\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4\nConfiguration_Name1=OutputConfigurationParameter1\nConfiguration_Item1=DesignatorDisplayMode=Physical|PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView\nConfiguration_Name2=OutputConfigurationParameter2\nConfiguration_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|IncludeViewports=True|Index=0|Mirror=False|Name=Multilayer Composite Print|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False\nConfiguration_Name3=OutputConfigurationParameter3\nConfiguration_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name4=OutputConfigurationParameter4\nConfiguration_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=TopLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name5=OutputConfigurationParameter5\nConfiguration_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MidLayer1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name6=OutputConfigurationParameter6\nConfiguration_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name7=OutputConfigurationParameter7\nConfiguration_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=MultiLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name8=OutputConfigurationParameter8\nConfiguration_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=BottomOverlay|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name9=OutputConfigurationParameter9\nConfiguration_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=KeepOutLayer|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name10=OutputConfigurationParameter10\nConfiguration_Item10=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name11=OutputConfigurationParameter11\nConfiguration_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name12=OutputConfigurationParameter12\nConfiguration_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\nConfiguration_Name13=OutputConfigurationParameter13\nConfiguration_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer\n\n"
  },
  {
    "path": "1.Hardware/REF/REF-Unit/REF-Unit.PrjPCBStructure",
    "content": "Record=TopLevelDocument|FileName=Main.SchDoc|SheetNumber=1\n"
  },
  {
    "path": "1.Hardware/REF/REF.PrjMbd",
    "content": "[Design]\nVersion=1.0\nHierarchyMode=0\nChannelRoomNamingStyle=0\nReleasesFolder=\nChannelDesignatorFormatString=$Component_$RoomName\nChannelRoomLevelSeperator=_\nOpenOutputs=1\nArchiveProject=0\nTimestampOutput=0\nSeparateFolders=0\nTemplateLocationPath=\nPinSwapBy_Netlabel=1\nPinSwapBy_Pin=1\nAllowPortNetNames=0\nAllowSheetEntryNetNames=1\nAppendSheetNumberToLocalNets=0\nNetlistSinglePinNets=0\nDefaultConfiguration=Default - All Constraints\nUserID=0xFFFFFFFF\nDefaultPcbProtel=1\nDefaultPcbPcad=0\nReorderDocumentsOnCompile=1\nNameNetsHierarchically=0\nPowerPortNamesTakePriority=0\nAutoSheetNumbering=1\nAutoCrossReferences=0\nPushECOToAnnotationFile=1\nDItemRevisionGUID=\nReportSuppressedErrorsInMessages=0\nFSMCodingStyle=eFMSDropDownList_OneProcess\nFSMEncodingStyle=eFMSDropDownList_OneHot\nIsProjectConflictPreventionWarningsEnabled=0\nOutputPath=\nLogFolderPath=\nManagedProjectGUID=\nIncludeDesignInRelease=0\n\n[Preferences]\nPrefsVaultGUID=\nPrefsRevisionGUID=\n\n[Document1]\nDocumentPath=REF.MbsDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=5799f555-f5bd-4c42-bea4-605194077990\n\n[Document2]\nDocumentPath=REF.MbaDoc\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=c6814e28-6654-4337-a2e8-5ec303354078\n\n[Document3]\nDocumentPath=REF-Unit\\REF-Unit.PrjPCB\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=\n\n[Document4]\nDocumentPath=REF-Base\\REF-Base.PrjPCB\nAnnotationEnabled=1\nAnnotateStartValue=1\nAnnotationIndexControlEnabled=0\nAnnotateSuffix=\nAnnotateScope=All\nAnnotateOrder=-1\nDoLibraryUpdate=1\nDoDatabaseUpdate=1\nClassGenCCAutoEnabled=1\nClassGenCCAutoRoomEnabled=1\nClassGenNCAutoScope=None\nDItemRevisionGUID=\nGenerateClassCluster=0\nDocumentUniqueId=\n\n[OutputGroup1]\nName=Netlist Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=CadnetixNetlist\nOutputName1=Cadnetix Netlist\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=CalayNetlist\nOutputName2=Calay Netlist\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=EDIF\nOutputName3=EDIF for PCB\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=EESofNetlist\nOutputName4=EESof Netlist\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nOutputType5=IntergraphNetlist\nOutputName5=Intergraph Netlist\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nOutputType6=MentorBoardStationNetlist\nOutputName6=Mentor BoardStation Netlist\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=MultiWire\nOutputName7=MultiWire\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=OrCadPCB2Netlist\nOutputName8=Orcad/PCB2 Netlist\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=PADSNetlist\nOutputName9=PADS ASCII Netlist\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=Pcad\nOutputName10=Pcad for PCB\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=PCADNetlist\nOutputName11=PCAD Netlist\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nOutputType12=PCADnltNetlist\nOutputName12=PCADnlt Netlist\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nOutputType13=Protel2Netlist\nOutputName13=Protel2 Netlist\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nOutputType14=ProtelNetlist\nOutputName14=Protel\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nOutputType15=RacalNetlist\nOutputName15=Racal Netlist\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nOutputType16=RINFNetlist\nOutputName16=RINF Netlist\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nOutputType17=SciCardsNetlist\nOutputName17=SciCards Netlist\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nOutputType18=TangoNetlist\nOutputName18=Tango Netlist\nOutputDocumentPath18=\nOutputVariantName18=\nOutputDefault18=0\nOutputType19=TelesisNetlist\nOutputName19=Telesis Netlist\nOutputDocumentPath19=\nOutputVariantName19=\nOutputDefault19=0\nOutputType20=WireListNetlist\nOutputName20=WireList Netlist\nOutputDocumentPath20=\nOutputVariantName20=\nOutputDefault20=0\n\n[OutputGroup2]\nName=Simulator Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\n\n[OutputGroup3]\nName=Documentation Outputs\nDescription=\nTargetPrinter=Virtual Printer\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Composite\nOutputName1=Composite Drawing\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType2=PCB 3D Print\nOutputName2=PCB 3D Print\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=PCB 3D Video\nOutputName3=PCB 3D Video\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=PCB Print\nOutputName4=PCB Prints\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=PCBDrawing\nOutputName5=Draftsman\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=PCBLIB Print\nOutputName6=PCBLIB Prints\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=PDF3D\nOutputName7=PDF3D\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=PDF3D MBA\nOutputName8=PDF3D MBA\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Report Print\nOutputName9=Report Prints\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Schematic Print\nOutputName10=Schematic Prints\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=SimView Print\nOutputName11=SimView Prints\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup4]\nName=Assembly Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Assembly\nOutputName1=Assembly Drawings\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType2=Pick Place\nOutputName2=Generates pick and place files\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Test Points For Assembly\nOutputName3=Test Point Report\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\n\n[OutputGroup5]\nName=Fabrication Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Board Stack Report\nOutputName1=Report Board Stack\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType2=CompositeDrill\nOutputName2=Composite Drill Drawing\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Drill\nOutputName3=Drill Drawing/Guides\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Final\nOutputName4=Final Artwork Prints\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Gerber\nOutputName5=Gerber Files\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=Gerber X2\nOutputName6=Gerber X2 Files\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nOutputType7=IPC2581\nOutputName7=IPC-2581 Files\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=Mask\nOutputName8=Solder/Paste Mask Prints\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=NC Drill\nOutputName9=NC Drill Files\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=ODB\nOutputName10=ODB++ Files\nOutputDocumentPath10=\nOutputVariantName10=[No Variations]\nOutputDefault10=0\nOutputType11=Plane\nOutputName11=Power-Plane Prints\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Test Points\nOutputName12=Test Point Report\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\n\n[OutputGroup6]\nName=Report Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_PartType\nOutputName1=Bill of Materials\nOutputDocumentPath1=\nOutputVariantName1=[No Variations]\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType2=ComponentCrossReference\nOutputName2=Component Cross Reference Report\nOutputDocumentPath2=\nOutputVariantName2=[No Variations]\nOutputDefault2=0\nOutputType3=Export Comments\nOutputName3=Export Comments\nOutputDocumentPath3=\nOutputVariantName3=[No Variations]\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=ReportHierarchy\nOutputName4=Report Project Hierarchy\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=Script\nOutputName5=Script Output\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=SimpleBOM\nOutputName6=Simple BOM\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=SinglePinNetReporter\nOutputName7=Report Single Pin Nets\nOutputDocumentPath7=\nOutputVariantName7=[No Variations]\nOutputDefault7=0\n\n[OutputGroup7]\nName=Other Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Text Print\nOutputName1=Text Print\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nPageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType2=Text Print\nOutputName2=Text Print\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nPageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType3=Text Print\nOutputName3=Text Print\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nPageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType4=Text Print\nOutputName4=Text Print\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Text Print\nOutputName5=Text Print\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Text Print\nOutputName6=Text Print\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Text Print\nOutputName7=Text Print\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nPageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType8=Text Print\nOutputName8=Text Print\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nPageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType9=Text Print\nOutputName9=Text Print\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nPageOptions9=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType10=Text Print\nOutputName10=Text Print\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nPageOptions10=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType11=Text Print\nOutputName11=Text Print\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\nPageOptions11=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType12=Text Print\nOutputName12=Text Print\nOutputDocumentPath12=\nOutputVariantName12=\nOutputDefault12=0\nPageOptions12=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType13=Text Print\nOutputName13=Text Print\nOutputDocumentPath13=\nOutputVariantName13=\nOutputDefault13=0\nPageOptions13=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType14=Text Print\nOutputName14=Text Print\nOutputDocumentPath14=\nOutputVariantName14=\nOutputDefault14=0\nPageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType15=Text Print\nOutputName15=Text Print\nOutputDocumentPath15=\nOutputVariantName15=\nOutputDefault15=0\nPageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType16=Text Print\nOutputName16=Text Print\nOutputDocumentPath16=\nOutputVariantName16=\nOutputDefault16=0\nPageOptions16=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType17=Text Print\nOutputName17=Text Print\nOutputDocumentPath17=\nOutputVariantName17=\nOutputDefault17=0\nPageOptions17=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n[OutputGroup8]\nName=Validation Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=BOM_Violations\nOutputName1=BOM Checks Report\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=Component states check\nOutputName2=Server's components states check\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=Configuration compliance\nOutputName3=Environment configuration compliance check\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=Design Rules Check\nOutputName4=Design Rules Check\nOutputDocumentPath4=\nOutputVariantName4=\nOutputDefault4=0\nPageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType5=Differences Report\nOutputName5=Differences Report\nOutputDocumentPath5=\nOutputVariantName5=\nOutputDefault5=0\nPageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType6=Electrical Rules Check\nOutputName6=Electrical Rules Check\nOutputDocumentPath6=\nOutputVariantName6=\nOutputDefault6=0\nPageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\nOutputType7=Footprint Comparison Report\nOutputName7=Footprint Comparison Report\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\n\n[OutputGroup9]\nName=Export Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=AutoCAD dwg/dxf PCB\nOutputName1=AutoCAD dwg/dxf File PCB\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\nOutputType2=AutoCAD dwg/dxf Schematic\nOutputName2=AutoCAD dwg/dxf File Schematic\nOutputDocumentPath2=\nOutputVariantName2=\nOutputDefault2=0\nOutputType3=ExportIDF\nOutputName3=Export IDF\nOutputDocumentPath3=\nOutputVariantName3=\nOutputDefault3=0\nOutputType4=ExportPARASOLID\nOutputName4=Export PARASOLID\nOutputDocumentPath4=\nOutputVariantName4=[No Variations]\nOutputDefault4=0\nOutputType5=ExportSTEP\nOutputName5=Export STEP\nOutputDocumentPath5=\nOutputVariantName5=[No Variations]\nOutputDefault5=0\nOutputType6=ExportVRML\nOutputName6=Export VRML\nOutputDocumentPath6=\nOutputVariantName6=[No Variations]\nOutputDefault6=0\nOutputType7=MBAExportPARASOLID\nOutputName7=Export PARASOLID\nOutputDocumentPath7=\nOutputVariantName7=\nOutputDefault7=0\nOutputType8=MBAExportSTEP\nOutputName8=Export STEP\nOutputDocumentPath8=\nOutputVariantName8=\nOutputDefault8=0\nOutputType9=Save As/Export PCB\nOutputName9=Save As/Export PCB\nOutputDocumentPath9=\nOutputVariantName9=\nOutputDefault9=0\nOutputType10=Save As/Export Schematic\nOutputName10=Save As/Export Schematic\nOutputDocumentPath10=\nOutputVariantName10=\nOutputDefault10=0\nOutputType11=Specctra Design PCB\nOutputName11=Specctra Design PCB\nOutputDocumentPath11=\nOutputVariantName11=\nOutputDefault11=0\n\n[OutputGroup10]\nName=PostProcess Outputs\nDescription=\nTargetPrinter=Microsoft Print to PDF\nPrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1\nOutputType1=Copy Files\nOutputName1=Copy Files\nOutputDocumentPath1=\nOutputVariantName1=\nOutputDefault1=0\n\n[Modification Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\nType69=1\nType70=1\nType71=1\nType72=1\nType73=1\nType74=1\nType75=1\nType76=1\nType77=1\nType78=1\nType79=1\nType80=1\nType81=1\nType82=1\nType83=1\nType84=1\nType85=1\nType86=1\nType87=1\nType88=1\nType89=1\nType90=1\nType91=1\nType92=1\nType93=1\nType94=1\nType95=1\nType96=1\nType97=1\nType98=1\nType99=1\nType100=1\nType101=1\nType102=1\nType103=1\nType104=1\nType105=1\nType106=1\nType107=1\nType108=1\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=1\nType115=1\nType116=1\nType117=1\nType118=1\nType119=1\n\n[Difference Levels]\nType1=1\nType2=1\nType3=1\nType4=1\nType5=1\nType6=1\nType7=1\nType8=1\nType9=1\nType10=1\nType11=1\nType12=1\nType13=1\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=1\nType21=1\nType22=1\nType23=1\nType24=1\nType25=1\nType26=1\nType27=1\nType28=1\nType29=1\nType30=1\nType31=1\nType32=1\nType33=1\nType34=1\nType35=1\nType36=1\nType37=1\nType38=1\nType39=1\nType40=1\nType41=1\nType42=1\nType43=1\nType44=1\nType45=1\nType46=1\nType47=1\nType48=1\nType49=1\nType50=1\nType51=1\nType52=1\nType53=1\nType54=1\nType55=1\nType56=1\nType57=1\nType58=1\nType59=1\nType60=1\nType61=1\nType62=1\nType63=1\nType64=1\nType65=1\nType66=1\nType67=1\nType68=1\n\n[Electrical Rules Check]\nType1=1\nType2=1\nType3=2\nType4=1\nType5=2\nType6=2\nType7=0\nType8=1\nType9=1\nType10=1\nType11=2\nType12=0\nType13=0\nType14=1\nType15=1\nType16=1\nType17=1\nType18=1\nType19=1\nType20=0\nType21=0\nType22=0\nType23=0\nType24=1\nType25=2\nType26=0\nType27=2\nType28=1\nType29=1\nType30=1\nType31=1\nType32=2\nType33=0\nType34=2\nType35=1\nType36=2\nType37=1\nType38=2\nType39=2\nType40=2\nType41=0\nType42=2\nType43=1\nType44=0\nType45=0\nType46=0\nType47=0\nType48=0\nType49=0\nType50=2\nType51=0\nType52=0\nType53=1\nType54=1\nType55=1\nType56=2\nType57=1\nType58=1\nType59=2\nType60=0\nType61=0\nType62=0\nType63=0\nType64=0\nType65=2\nType66=3\nType67=2\nType68=2\nType69=0\nType70=2\nType71=2\nType72=2\nType73=2\nType74=1\nType75=2\nType76=1\nType77=1\nType78=1\nType79=1\nType80=2\nType81=3\nType82=3\nType83=3\nType84=3\nType85=3\nType86=2\nType87=2\nType88=2\nType89=1\nType90=1\nType91=3\nType92=3\nType93=2\nType94=2\nType95=2\nType96=2\nType97=2\nType98=0\nType99=1\nType100=2\nType101=0\nType102=2\nType103=2\nType104=1\nType105=2\nType106=2\nType107=2\nType108=2\nType109=1\nType110=1\nType111=1\nType112=1\nType113=1\nType114=2\nType115=2\nType116=2\nType117=3\nType118=3\nType119=3\nMultiChannelAlternate=2\nAlternateItemFail=3\nType122=2\nType123=1\nType124=1\nType125=1\n\n[ERC Connection Matrix]\nL1=NNNNNNNNNNNWNNNWW\nL2=NNWNNNNWWWNWNWNWN\nL3=NWEENEEEENEWNEEWN\nL4=NNENNNWEENNWNENWN\nL5=NNNNNNNNNNNNNNNNN\nL6=NNENNNNEENNWNENWN\nL7=NNEWNNWEENNWNENWN\nL8=NWEENEENEEENNEENN\nL9=NWEENEEEENEWNEEWW\nL10=NWNNNNNENNEWNNEWN\nL11=NNENNNNEEENWNENWN\nL12=WWWWNWWNWWWNWWWNN\nL13=NNNNNNNNNNNWNNNWW\nL14=NWEENEEEENEWNEEWW\nL15=NNENNNNEEENWNENWW\nL16=WWWWNWWNWWWNWWWNW\nL17=WNNNNNNNWNNNWWWWN\n\n[Annotate]\nSortOrder=3\nSortLocation=0\nReplaceSubparts=0\nMatchParameter1=Comment\nMatchStrictly1=1\nMatchParameter2=Library Reference\nMatchStrictly2=1\nPhysicalNamingFormat=$Component_$RoomName\nGlobalIndexSortOrder=3\nGlobalIndexSortLocation=0\n\n[PrjClassGen]\nCompClassManualEnabled=0\nCompClassManualRoomEnabled=0\nNetClassAutoBusEnabled=1\nNetClassAutoCompEnabled=0\nNetClassAutoNamedHarnessEnabled=0\nNetClassManualEnabled=1\nNetClassSeparateForBusSections=0\n\n[LibraryUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\nFullReplace=1\nUpdateDesignatorLock=1\nUpdatePartIDLock=1\nPreserveParameterLocations=1\nPreserveParameterVisibility=1\nDoGraphics=1\nDoParameters=1\nDoModels=1\nAddParameters=0\nRemoveParameters=0\nAddModels=1\nRemoveModels=1\nUpdateCurrentModels=1\n\n[DatabaseUpdateOptions]\nSelectedOnly=0\nUpdateVariants=1\nUpdateToLatestRevision=1\nPartTypes=0\n\n[Comparison Options]\nComparisonOptions0=Kind=Net|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0\nComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0\nComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0\nComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0\nComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|UseName=0|InclAllRules=0\nComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=0|UseName=-1|InclAllRules=0\n\n[SmartPDF]\nPageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9\n\n"
  },
  {
    "path": "1.Hardware/REF/REF.PrjMbdStructure",
    "content": "Record=DiagramHierarchy|SourceDocument=REF.MbsDoc|Kind=Multi-board Schematic Module|Designator=2|Source=REF-Base\\REF-Base.PrjPCB\nRecord=SubProject|SourceDocument=REF.MbsDoc|ProjectPath=REF-Base\\REF-Base.PrjPCB\nRecord=DiagramHierarchy|SourceDocument=REF.MbsDoc|Kind=Multi-board Schematic Module|Designator=1|Source=REF-Unit\\REF-Unit.PrjPCB\nRecord=SubProject|SourceDocument=REF.MbsDoc|ProjectPath=REF-Unit\\REF-Unit.PrjPCB\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/.cproject",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<?fileVersion 4.0.0?><cproject storage_type_id=\"org.eclipse.cdt.core.XmlProjectDescriptionStorage\">\n\t<storageModule moduleId=\"org.eclipse.cdt.core.settings\">\n\t\t<cconfiguration id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.1465527105\">\n\t\t\t<storageModule buildSystemId=\"org.eclipse.cdt.managedbuilder.core.configurationDataProvider\" id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.1465527105\" moduleId=\"org.eclipse.cdt.core.settings\" name=\"Debug\">\n\t\t\t\t<externalSettings />\n\t\t\t\t<extensions>\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.ELF\" point=\"org.eclipse.cdt.core.BinaryParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GASErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GmakeErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GLDErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.CWDLocator\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GCCErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t</extensions>\n\t\t\t</storageModule>\n\t\t\t<storageModule moduleId=\"cdtBuildSystem\" version=\"4.0.0\">\n\t\t\t\t<configuration artifactExtension=\"elf\" artifactName=\"${ProjName}\" buildArtefactType=\"org.eclipse.cdt.build.core.buildArtefactType.exe\" buildProperties=\"org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug\" cleanCommand=\"rm -rf\" description=\"\" id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.1465527105\" name=\"Debug\" parent=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug\" postannouncebuildStep=\"Generating hex and Printing size information:\" postbuildStep=\"arm-none-eabi-objcopy -O ihex &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.hex&quot; &amp;&amp; arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;\">\n\t\t\t\t\t<folderInfo id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.1465527105.\" name=\"/\" resourcePath=\"\">\n\t\t\t\t\t\t<toolChain id=\"fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug.682049980\" name=\"Ac6 STM32 MCU GCC\" superClass=\"fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug\">\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.prefix.14716717\" name=\"Prefix\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.prefix\" value=\"arm-none-eabi-\" valueType=\"string\" />\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.mcu.1649063108\" name=\"Mcu\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.mcu\" value=\"STM32F405RGTx\" valueType=\"string\" />\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.board.1450084087\" name=\"Board\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.board\" value=\"REF-STM32F4-fw\" valueType=\"string\" />\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.core.1083960614\" name=\"Core\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.core\" valueType=\"stringList\">\n\t\t\t\t\t\t\t\t<listOptionValue builtIn=\"false\" value=\"ARM Cortex-M4\" />\n\t\t\t\t\t\t\t\t<listOptionValue builtIn=\"false\" value=\"CM4\" />\n\t\t\t\t\t\t\t</option>\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.instructionSet.1135067759\" name=\"Instruction Set\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.instructionSet\" value=\"fr.ac6.managedbuild.option.gnu.cross.instructionSet.thumbII\" valueType=\"enumerated\" />\n\t\t\t\t\t\t\t<option id=\"fr.ac6.managedbuild.option.gnu.cross.fpu.381891948\" name=\"Floating point hardware\" superClass=\"fr.ac6.managedbuild.option.gnu.cross.fpu\" value=\"fr.ac6.managedbuild.option.gnu.cross.fpu.fpv4-sp-d16\" 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    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<projectDescription>\n\t<name>REF-STM32F4</name>\n\t<comment />\n\t<projects>\n\t</projects>\n\t<buildSpec>\n\t\t<buildCommand>\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>\n\t\t\t<triggers>clean,full,incremental,</triggers>\n\t\t\t<arguments>\n\t\t\t</arguments>\n\t\t</buildCommand>\n\t\t<buildCommand>\n\t\t\t<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>\n\t\t\t<triggers>full,incremental,</triggers>\n\t\t\t<arguments>\n\t\t\t</arguments>\n\t\t</buildCommand>\n\t</buildSpec>\n\t<natures>\n\t\t<nature>org.eclipse.cdt.core.cnature</nature>\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>\n\t\t<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>\n\t\t<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature>\n\t</natures>\n\t<linkedResources>\n\t\t\n\t<link>\n\t\t\t<name>FreeRTOS/croutine.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/croutine.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/event_groups.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/list.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/list.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/queue.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/queue.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/stream_buffer.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/tasks.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/tasks.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/timers.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/timers.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/cmsis_os2.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/heap_4.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c</location>\n\t\t</link><link>\n\t\t\t<name>FreeRTOS/port.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c</location>\n\t\t</link><link>\n\t\t\t<name>USB_Device_Library/usbd_core.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c</location>\n\t\t</link><link>\n\t\t\t<name>USB_Device_Library/usbd_ctlreq.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c</location>\n\t\t</link><link>\n\t\t\t<name>USB_Device_Library/usbd_ioreq.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c</location>\n\t\t</link><link>\n\t\t\t<name>USB_Device_Library/usbd_cdc.c</name>\n\t\t\t<type>1</type>\n\t\t\t<location>PARENT-2-PROJECT_LOC/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c</location>\n\t\t</link></linkedResources>\n</projectDescription>\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/include/fibre/cpp_utils.hpp",
    "content": "#ifndef __CPP_UTILS_HPP\n#define __CPP_UTILS_HPP\n\n/*\n\n## Advanced C++ Topics\n\nThis is an overview of some of the more obscure C++ techniques used in this project.\nThis assumes you're already familiar with templates in C++.\n\n### Template recursion\n\n[TODO]\n\n### Almost perfect template forwarding\n\nThis is adapted from https://akrzemi1.wordpress.com/2013/10/10/too-perfect-forwarding/\n\nSuppose you have a inner class, with a couple of constructors:\n```\nclass InnerClass {\npublic:\n    InnerClass(int arg1, int arg2);\n    InnerClass(int arg1);\n    InnerClass();\n};\n```\n\nNow you want to create a wrapper class. This wrapper class should provide the exact same constructors as `InnerClass`, so you use perfect forwarding:\n```\nclass WrapperClass {\npublic:\n    template<typename ... Args>\n    WrapperClass(Args&& ... args)\n        : inner_object(std::forward<Args>(args)...)\n    {}\n    InnerClass inner_object;\n};\n```\n\nNow you can almost use the wrapper class as expected, but only almost:\n```\nvoid make_wrappers(void) {\n    WrapperClass wrapper1;              // ok, maps to InnerClass()\n    WrapperClass wrapper2(1);           // ok, maps to InnerClass(int arg1)\n    WrapperClass wrapper3(1,2);         // ok, maps to InnerClass(int arg1, arg2)\n    WrapperClass wrapper4 = wrapper1;   // does not compile\n}\n```\n\nThe last assignment fails. What _you_ obviously wanted, is to use the copy constructor of WrapperClass.\nHowever the compiler will use the perfect forwarding constructor of WrapperClass for this assignment.\nSo after template expansion it would try to use the following constructor:\n\n```\n    WrapperClass(InnerClass& arg)\n        : inner_object(arg)\n    {}\n```\n\nClearly this is not what we wanted and in this case it will fail because the exists no\nconstructor of the form `InnerClass(WrapperClass& arg)`.\n\nAnd thus we need to make the perfect forwarding a little less perfect, by telling it\n\"only enable this constructor if the first argument of the argument list is not of type WrapperClass\".\n\nThe modified version thus looks like this:\n```\nclass WrapperClass {\npublic:\n    template<typename ... Args, ENABLE_IF(TypeChecker<Args...>::template first_is_not<WrapperClass>())>\n    WrapperClass(Args&& ... args)\n        : inner_object(std::forward<Args>(args)...)\n    {} \n    InnerClass inner_object;\n};\n```\n\n*/\n\n// Backport definitions from C++14\n#if __cplusplus <= 201103L\nnamespace std {\n    template< class T >\n    using underlying_type_t = typename underlying_type<T>::type;\n\n    // source: http://en.cppreference.com/w/cpp/types/enable_if\n    template< bool B, class T = void >\n    using enable_if_t = typename enable_if<B,T>::type;\n}\n#endif\n\n// @brief Supports various queries on a list of types\ntemplate<typename ... Ts>\nclass TypeChecker;\n\ntemplate<typename T, typename ... Ts>\nclass TypeChecker<T, Ts...>\n{\npublic:\n    using DecayedT = typename std::decay<T>::type;\n\n    // @brief Returns false if type T is equal to U or inherits from U. Returns true otherwise.\n    template<typename U>\n    constexpr static inline bool first_is_not()\n    {\n        return !std::is_same<DecayedT, U>::value\n               && !std::is_base_of<U, DecayedT>::value;\n    }\n\n    // @brief Returns true if all types [T, Ts...] are either equal to U or inherit from U.\n    template<typename U>\n    constexpr static inline bool all_are()\n    {\n        return std::is_base_of<U, DecayedT>::value\n               && TypeChecker<Ts...>::template all_are<U>();\n    }\n};\n\ntemplate<>\nclass TypeChecker<>\n{\npublic:\n    template<typename U>\n    constexpr static inline bool first_is_not()\n    {\n        return std::true_type::value;\n    }\n\n    template<typename U>\n    constexpr static inline bool all_are()\n    {\n        return std::true_type::value;\n    }\n};\n\n#include <type_traits>\n\n#define ENABLE_IF(...) \\\n    typename = std::enable_if_t<__VA_ARGS__>\n\n#define ENABLE_IF_SAME(a, b, type) \\\n    template<typename T = a> typename std::enable_if_t<std::is_same<T, b>::value, type>\n\ntemplate<class T, class M>\nM get_member_type(M T::*);\n\n#define GET_TYPE_OF(mem) decltype(get_member_type(mem))\n\n\n//#include <type_traits>\n// @brief Statically asserts that T is derived from type BaseType\n#define EXPECT_TYPE(T, BaseType) static_assert(std::is_base_of<BaseType, typename std::decay<T>::type>::value || std::is_convertible<typename std::decay<T>::type, BaseType>::value, \"expected template argument of type \" #BaseType)\n//#define EXPECT_TYPE(T, BaseType) static_assert(, \"expected template argument of type \" #BaseType)\n\n\n\n\ntemplate<typename TObj, typename TRet, typename ... TArgs>\nclass function_traits\n{\npublic:\n    template<unsigned IUnpacked, typename ... TUnpackedArgs, ENABLE_IF(IUnpacked != sizeof...(TArgs)) >\n    static TRet\n    invoke(TObj &obj, TRet(TObj::*func_ptr)(TArgs...), std::tuple<TArgs...> packed_args, TUnpackedArgs ... args)\n    {\n        return invoke<IUnpacked + 1>(obj, func_ptr, packed_args, args..., std::get<IUnpacked>(packed_args));\n    }\n\n    template<unsigned IUnpacked>\n    static TRet invoke(TObj &obj, TRet(TObj::*func_ptr)(TArgs...), std::tuple<TArgs...> packed_args, TArgs ... args)\n    {\n        return (obj.*func_ptr)(args...);\n    }\n};\n\n/* @brief Invoke a class member function with a variable number of arguments that are supplied as a tuple\n\nExample usage:\n\nclass MyClass {\npublic:\n    int MyFunction(int a, int b) {\n        return 0;\n    }\n};\n\nMyClass my_object;\nstd::tuple<int, int> my_args(3, 4); // arguments are supplied as a tuple\nint result = invoke_function_with_tuple(my_object, &MyClass::MyFunction, my_args);\n*/\ntemplate<typename TObj, typename TRet, typename ... TArgs>\nTRet invoke_function_with_tuple(TObj &obj, TRet(TObj::*func_ptr)(TArgs...), std::tuple<TArgs...> packed_args)\n{\n    return function_traits<TObj, TRet, TArgs...>::template invoke<0>(obj, func_ptr, packed_args);\n}\n\n#endif // __CPP_UTILS_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/include/fibre/crc.hpp",
    "content": "#ifndef __CRC_HPP\n#define __CRC_HPP\n\n#include <stdint.h>\n#include <limits.h>\n\n// Calculates an arbitrary CRC for one byte.\n// Adapted from https://barrgroup.com/Embedded-Systems/How-To/CRC-Calculation-C-Code\ntemplate<typename T, unsigned POLYNOMIAL>\nstatic T calc_crc(T remainder, uint8_t value)\n{\n    constexpr T BIT_WIDTH = (CHAR_BIT * sizeof(T));\n    constexpr T TOPBIT = ((T) 1 << (BIT_WIDTH - 1));\n\n    // Bring the next byte into the remainder.\n    remainder ^= (value << (BIT_WIDTH - 8));\n\n    // Perform modulo-2 division, a bit at a time.\n    for (uint8_t bit = 8; bit; --bit)\n    {\n        if (remainder & TOPBIT)\n        {\n            remainder = (remainder << 1) ^ POLYNOMIAL;\n        } else\n        {\n            remainder = (remainder << 1);\n        }\n    }\n\n    return remainder;\n}\n\ntemplate<typename T, unsigned POLYNOMIAL>\nstatic T calc_crc(T remainder, const uint8_t *buffer, size_t length)\n{\n    while (length--)\n        remainder = calc_crc<T, POLYNOMIAL>(remainder, *(buffer++));\n    return remainder;\n}\n\ntemplate<unsigned POLYNOMIAL>\nstatic uint8_t calc_crc8(uint8_t remainder, uint8_t value)\n{\n    return calc_crc<uint8_t, POLYNOMIAL>(remainder, value);\n}\n\ntemplate<unsigned POLYNOMIAL>\nstatic uint16_t calc_crc16(uint16_t remainder, uint8_t value)\n{\n    return calc_crc<uint16_t, POLYNOMIAL>(remainder, value);\n}\n\ntemplate<unsigned POLYNOMIAL>\nstatic uint8_t calc_crc8(uint8_t remainder, const uint8_t *buffer, size_t length)\n{\n    return calc_crc<uint8_t, POLYNOMIAL>(remainder, buffer, length);\n}\n\ntemplate<unsigned POLYNOMIAL>\nstatic uint16_t calc_crc16(uint16_t remainder, const uint8_t *buffer, size_t length)\n{\n    return calc_crc<uint16_t, POLYNOMIAL>(remainder, buffer, length);\n}\n\n#endif /* __CRC_HPP */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/include/fibre/decoders.hpp",
    "content": "\n#ifndef __DECODERS_HPP\n#define __DECODERS_HPP\n\n#include \"protocol.hpp\"\n#include \"crc.hpp\"\n#include \"cpp_utils.hpp\"\n#include <utility>\n\n\n/* Base classes --------------------------------------------------------------*/\n\n// @brief Base class for stream based decoders.\n// A stream based decoder is a decoder that processes arbitrary length data blocks.\nclass StreamDecoder : public StreamSink\n{\npublic:\n    // @brief Returns 0 if no error ocurred, otherwise a non-zero error code.\n    // Once process_bytes returned an error, subsequent calls to get_status must return the same error.\n    // If the decoder is in an error state, the behavior of get_expected_bytes and process_bytes is undefined.\n    virtual int get_status() = 0;\n\n    // @brief Returns the minimum number of bytes that are still needed to complete this decoder.\n    // If 0, the decoder is considered complete and any subsequent call to process_bytes must process\n    // exactly 0 bytes.\n    // process_bytes() must always process all provided bytes unless the decoder expects no more bytes\n    // afterwards\n    virtual size_t get_expected_bytes() = 0;\n};\n\n// @brief Base class for a decoder that is fed in a block-wise fashion.\n// This base class is provided for convenience when implementing certain types of decoders.\n// A StreamDecoder can be obtained from a BlockDecoder by using StreamDecoder_from_BlockDecoder.\ntemplate<unsigned BLOCKSIZE>\nclass BlockDecoder\n{\npublic:\n    typedef std::integral_constant<size_t, BLOCKSIZE> block_size;\n\n    virtual int get_status() = 0;\n\n    virtual size_t get_expected_blocks() = 0;\n\n    virtual int process_block(const uint8_t block[BLOCKSIZE]) = 0;\n\nprivate:\n};\n\n// @brief Base class for a decoder that is fed in a byte-wise fashion\n// This base class is provided for convenience when implementing certain types of decoders.\n// A StreamDecoder can be obtained from a ByteDecoder by using StreamDecoder_from_ByteDecoder.\nclass ByteDecoder\n{\npublic:\n    virtual int get_status() = 0;\n\n    virtual size_t get_expected_bytes() = 0;\n\n    virtual int process_byte(uint8_t byte) = 0;\n};\n\n/* Converter classes ---------------------------------------------------------*/\n\n// @brief Encapsulates a BlockDecoder to make it look like a StreamDecoder\n// @tparam T The encapsulated BlockDecoder type.\n//           Must inherit from BlockDecoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<BlockDecoder<T::block_size::value>>()) >\nclass StreamDecoder_from_BlockDecoder : public StreamDecoder\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<StreamDecoder_from_BlockDecoder>()) >\n    explicit StreamDecoder_from_BlockDecoder(Args &&... args)\n            : block_decoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, BlockDecoder<T::block_size::value>);\n    }\n\n    inline int get_status() final\n    {\n        return block_decoder_.get_status();\n    }\n\n    inline size_t get_expected_bytes() final\n    {\n        size_t expected_bytes = block_decoder_.get_expected_blocks() * T::block_size::value;\n        return expected_bytes - std::min(expected_bytes, buffer_pos_);\n    }\n\n    inline int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes) final\n    {\n        while (!get_status() && get_expected_bytes() && length)\n        {\n            // use the incoming bytes to fill internal buffer to get a complete block\n            size_t n_copy = std::min(length, T::block_size::value - buffer_pos_);\n            memcpy(buffer_ + buffer_pos_, buffer, n_copy);\n            buffer += n_copy;\n            length -= n_copy;\n            if (processed_bytes) (*processed_bytes) += n_copy;\n            buffer_pos_ += n_copy;\n\n            // if we have a full block, process it\n            if (buffer_pos_ == T::block_size::value)\n            {\n                block_decoder_.process_block(buffer_);\n                buffer_pos_ = 0;\n            }\n        }\n        return get_status();\n    }\n\n    size_t get_free_space()\n    { return SIZE_MAX; } // TODO: deprecate\nprivate:\n    T block_decoder_;\n    size_t buffer_pos_ = 0;\n    uint8_t buffer_[T::block_size::value];\n};\n\n// @brief Encapsulates a ByteDecoder to make it look like a BlockDecoder\n// @tparam T The encapsulated ByteDecoder type.\n//           Must inherit from ByteDecoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<ByteDecoder>()) >\nclass BlockDecoder_from_ByteDecoder : public BlockDecoder<1>\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<BlockDecoder_from_ByteDecoder>()) >\n    BlockDecoder_from_ByteDecoder(Args &&... args)\n            : byte_decoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, ByteDecoder);\n    }\n\n    inline int get_status() final\n    {\n        return byte_decoder_.get_status();\n    }\n\n    inline size_t get_expected_blocks() final\n    {\n        return byte_decoder_.get_expected_bytes();\n    }\n\n    inline int process_block(const uint8_t block[1]) final\n    {\n        int status = byte_decoder_.process_byte(*block);\n        return status;\n    }\n\nprivate:\n    T byte_decoder_;\n};\n\n// @brief Encapsulates a ByteDecoder to make it look like a StreamDecoder\n// @tparam T The encapsulated ByteDecoder type.\n//           Must inherit from ByteDecoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<ByteDecoder>()) >\nclass StreamDecoder_from_ByteDecoder : public StreamDecoder\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<StreamDecoder_from_ByteDecoder>()) >\n    StreamDecoder_from_ByteDecoder(Args &&... args)\n            : byte_decoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, ByteDecoder);\n    }\n\n    inline int get_status() final\n    {\n        return byte_decoder_.get_status();\n    }\n\n    inline size_t get_expected_bytes() final\n    {\n        return byte_decoder_.get_expected_bytes();\n    }\n\n    inline size_t get_free_space()\n    { return SIZE_MAX; }\n\n    inline int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes) final\n    {\n        while (!byte_decoder_.get_status() && byte_decoder_.get_expected_bytes() && length)\n        {\n            length--;\n            if (processed_bytes) (*processed_bytes)++;\n            byte_decoder_.process_byte(*(buffer++));\n        }\n        return byte_decoder_.get_status();\n    }\n\nprivate:\n    T byte_decoder_;\n};\n\n/* Decoder implementations ---------------------------------------------------*/\n\ntemplate<typename T>\nclass VarintByteDecoder : public ByteDecoder\n{\npublic:\n    static constexpr T BIT_WIDTH = (CHAR_BIT * sizeof(T));\n\n    VarintByteDecoder(T &state_variable) :\n            state_variable_(state_variable)\n    {\n    }\n\n    size_t get_expected_bytes() final\n    {\n        return done_ ? 0 : 1;\n    }\n\n    int get_status() final\n    {\n        return status_;\n    }\n\n    int process_byte(uint8_t input_byte) final\n    {\n        if (bit_pos_ == 0)\n        {\n            LOG_FIBRE(\"start decoding varint, with 0x%02x => %zx\\n\", input_byte, (uintptr_t) &state_variable_);\n            state_variable_ = 0;\n        }\n        LOG_FIBRE(\"varint: decode %02x << %zu at %zx\\n\", input_byte, bit_pos_, &bit_pos_);\n        // we assume bit_pos_ < BIT_WIDTH\n        state_variable_ |= (static_cast<T>(input_byte & 0x7f) << bit_pos_);\n        if (((state_variable_ >> bit_pos_) & 0x7f) != static_cast<T>(input_byte & 0x7f))\n        {\n            LOG_FIBRE(\"varint overflow: tried to add %02x << %zu\\n\", input_byte, bit_pos_);\n            return (status_ = -1); // overflow\n        }\n        bit_pos_ += 7;\n        done_ = !(input_byte & 0x80);\n        return (status_ = (done_ || bit_pos_ < BIT_WIDTH) ? 0 : -1);\n    }\n\nprivate:\n    T &state_variable_;\n    // At all times where status_ != 0 the following statement holds:\n    // (done_ || bit_pos_ < BIT_WIDTH)\n    //size_t bit_pos_ = 0; // bit position\n    size_t bit_pos_ = 0; // bit position\n    int status_ = 0;\n    bool done_ = false;\n    int data[1024] = {0};\n};\n\ntemplate<typename T>\nusing VarintStreamDecoder = StreamDecoder_from_ByteDecoder<VarintByteDecoder<T>>;\n\n// This double nested type should work identically but makes it way harder for the compiler to optimize\n//template<typename T>\n//using VarintBlockDecoder = BlockDecoder_from_ByteDecoder<VarintByteDecoder<T>>;\n//template<typename T>\n//using VarintStreamDecoder = StreamDecoder_from_BlockDecoder<VarintBlockDecoder<T>>;\n\ntemplate<typename T>\ninline VarintStreamDecoder<T> make_varint_decoder(T &variable)\n{\n    return VarintStreamDecoder<T>(variable);\n}\n\ninline VarintStreamDecoder<GET_TYPE_OF(&ReceiverState::endpoint_id)> make_endpoint_id_decoder(ReceiverState &state)\n{\n    return make_varint_decoder(state.endpoint_id);\n}\n\ninline VarintStreamDecoder<GET_TYPE_OF(&ReceiverState::length)> make_length_decoder(ReceiverState &state)\n{\n    return make_varint_decoder(state.length);\n}\n\n\ntemplate<uint8_t INIT, uint8_t POLYNOMIAL, typename TDecoder,\n        ENABLE_IF(TypeChecker<TDecoder>::template all_are<StreamDecoder>()) >\nclass CRC8BlockDecoder : public BlockDecoder<CRC8_BLOCKSIZE>\n{\npublic:\n    CRC8BlockDecoder(TDecoder &&inner_decoder) :\n            inner_decoder_(std::forward<TDecoder>(inner_decoder))\n    {\n    }\n\n    int get_status() final\n    {\n        return status_;\n    }\n\n    size_t get_expected_blocks() final\n    {\n        return (inner_decoder_.get_expected_bytes() + CRC8_BLOCKSIZE - 2) / (CRC8_BLOCKSIZE - 1);\n    }\n\n    int process_block(const uint8_t input_block[4]) final\n    {\n        current_crc_ = calc_crc8<POLYNOMIAL>(current_crc_, input_block, CRC8_BLOCKSIZE - 1);\n        if (current_crc_ != input_block[CRC8_BLOCKSIZE - 1])\n            return status_ = -1;\n        return status_ = inner_decoder_.process_bytes(input_block, CRC8_BLOCKSIZE - 1, nullptr);\n    }\n\nprivate:\n    TDecoder inner_decoder_;\n    int status_ = 0;\n    uint8_t current_crc_ = INIT;\n};\n\ntemplate<unsigned INIT, unsigned POLYNOMIAL, typename TDecoder>\nusing CRC8StreamDecoder = StreamDecoder_from_BlockDecoder<CRC8BlockDecoder<INIT, POLYNOMIAL, TDecoder>>;\n\ntemplate<unsigned INIT, unsigned POLYNOMIAL, typename TDecoder>\ninline CRC8StreamDecoder<INIT, POLYNOMIAL, TDecoder> make_crc8_decoder(TDecoder &&decoder)\n{\n    return CRC8StreamDecoder<INIT, POLYNOMIAL, TDecoder>(std::forward<TDecoder>(decoder));\n}\n\n// TODO: ENABLE_IF(TypeChecker<TDecoders...>::template all_are<StreamDecoder>())\ntemplate<typename ... TDecoders>\nclass DecoderChain;\n\ntemplate<>\nclass DecoderChain<> : public StreamDecoder\n{\npublic:\n    size_t get_expected_bytes()\n    { return 0; }\n\n    int get_status()\n    { return 0; }\n\n    int process_bytes(const uint8_t *input, size_t length, size_t *processed_bytes)\n    { return 0; }\n\n    size_t get_free_space()\n    { return SIZE_MAX; } // TODO: deprecate\n};\n\ntemplate<typename TDecoder, typename ... TDecoders>\nclass DecoderChain<TDecoder, TDecoders...> : public StreamDecoder\n{\npublic:\n    DecoderChain(TDecoder &&this_decoder, TDecoders &&... subsequent_decoders) :\n            this_decoder_(std::forward<TDecoder>(this_decoder)),\n            subsequent_decoders_(std::forward<TDecoders>(subsequent_decoders)...)\n    {\n        EXPECT_TYPE(TDecoder, StreamDecoder);\n    }\n\n    int get_status() final\n    {\n        // If this decoder or any of the subsequent decoders failed, return error code.\n        int this_status = this_decoder_.get_status();\n        int subsequent_status = subsequent_decoders_.get_status();\n        if (this_status)\n            return this_status;\n        else if (subsequent_status)\n            return subsequent_status;\n        else\n            return 0;\n    }\n\n    size_t get_expected_bytes() final\n    {\n        return this_decoder_.get_expected_bytes() + subsequent_decoders_.get_expected_bytes();\n    }\n\n    int process_bytes(const uint8_t *input, size_t length, size_t *processed_bytes) final\n    {\n        if (this_decoder_.get_expected_bytes())\n        {\n            LOG_FIBRE(\"decoder chain: process %zu bytes in segment %s\\n\", length, typeid(TDecoder).name());\n            size_t chunk = 0;\n            int status = this_decoder_.process_bytes(input, length, &chunk);\n            input += chunk;\n            length -= chunk;\n            if (processed_bytes) (*processed_bytes) += chunk;\n            if (status)\n                return status;\n            if (!length)\n                return 0;\n        }\n        return subsequent_decoders_.process_bytes(input, length, processed_bytes);\n    }\n\n    size_t get_free_space()\n    { return SIZE_MAX; } // TODO: deprecate\nprivate:\n    TDecoder this_decoder_;\n    DecoderChain<TDecoders...> subsequent_decoders_;\n};\n\ntemplate<typename ... TDecoders>\ninline DecoderChain<TDecoders...> make_decoder_chain(TDecoders &&... decoders)\n{\n    return DecoderChain<TDecoders...>(std::forward<TDecoders>(decoders)...);\n}\n\n#endif // __DECODERS_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/include/fibre/encoders.hpp",
    "content": "\n#ifndef __ENCODERS_HPP\n#define __ENCODERS_HPP\n\n#include \"protocol.hpp\"\n#include \"crc.hpp\"\n#include \"cpp_utils.hpp\"\n#include <utility>\n\nstruct Request\n{\n    endpoint_id_t endpoint_id;\n    size_t length;\n};\n\n/* Base classes --------------------------------------------------------------*/\n\n// @brief Base class for all stream encoders\n// A stream based encoder is an encoder that generates arbitrary length data blocks.\nclass StreamEncoder : public StreamSource\n{\npublic:\n    // @brief Returns 0 if no error ocurred, otherwise a non-zero error code.\n    // Once get_bytes returned an error, subsequent calls to get_status must return the same error.\n    // If the encoder is in an error state, the behavior of get_available_bytes and get_bytes is undefined.\n    virtual int get_status() = 0;\n\n    // @brief Returns the minimum number of bytes that will still be generated by this encoder.\n    // If 0, the encoder is considered complete and any subsequent call to get_bytes must generate\n    // exactly 0 bytes.\n    // get_bytes() must always generate as many bytes as requested unless the encoder generates no more bytes\n    // afterwards\n    virtual size_t get_available_bytes() = 0;\n};\n\n// @brief Base class for an encoder that is fed in a block-wise fashion.\n// This base class is provided for convenience when implementing certain types of encoders.\n// A StreamEncoder can be obtained from a BlockEncoder by using StreamEncoder_from_BlockEncoder.\ntemplate<unsigned BLOCKSIZE>\nclass BlockEncoder\n{\npublic:\n    typedef std::integral_constant<size_t, BLOCKSIZE> block_size;\n\n    virtual int get_status() = 0;\n\n    virtual size_t get_available_blocks() = 0;\n\n    virtual int get_block(uint8_t block[BLOCKSIZE]) = 0;\n\nprivate:\n};\n\n// @brief Base class for an encoder that is fed in a byte-wise fashion\n// This base class is provided for convenience when implementing certain types of encoders.\n// A StreamEncoder can be obtained from a ByteEncoder by using StreamEncoder_from_ByteEncoder.\nclass ByteEncoder\n{\npublic:\n    virtual int get_status() = 0;\n\n    virtual size_t get_available_bytes() = 0;\n\n    virtual int get_byte(uint8_t *output_byte) = 0;\n};\n\n/* Converter classes ---------------------------------------------------------*/\n\n// @brief Encapsulates a BlockEncoder to make it look like a StreamEncoder\n// @tparam T The encapsulated BlockEncoder type.\n//           Must inherit from to BlockEncoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<BlockEncoder<T::block_size::value>>()) >\nclass StreamEncoder_from_BlockEncoder : public StreamEncoder\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<StreamEncoder_from_BlockEncoder>()) >\n    explicit StreamEncoder_from_BlockEncoder(Args &&... args)\n            : block_encoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, BlockEncoder<T::block_size::value>);\n    }\n\n    inline int get_status() final\n    {\n        return buffered_bytes_ ? 0 : block_encoder_.get_status();\n    }\n\n    inline size_t get_available_bytes() final\n    {\n        size_t available_bytes = block_encoder_.get_available_blocks() * T::block_size::value;\n        return available_bytes + buffered_bytes_;\n    }\n\n    inline int get_bytes(uint8_t *buffer, size_t length, size_t *generated_bytes) final\n    {\n        while (!get_status() && get_available_bytes() && length)\n        {\n            // if the buffer is empty, retrieve a new block from the encode\n            if (!buffered_bytes_)\n            {\n                block_encoder_.get_block(buffer_);\n                buffered_bytes_ = T::block_size::value;\n            }\n\n            // hand the buffered bytes to the encoder\n            size_t n_copy = std::min(buffered_bytes_, length);\n            memcpy(buffer, buffer_ + T::block_size::value - n_copy, n_copy);\n            length -= n_copy;\n            buffer += n_copy;\n            if (generated_bytes) (*generated_bytes) += n_copy;\n            buffered_bytes_ -= n_copy;\n        }\n        return get_status();\n    }\n\nprivate:\n    T block_encoder_;\n    size_t buffered_bytes_ = 0;\n    uint8_t buffer_[T::block_size::value];\n};\n\n// @brief Encapsulates a ByteEncoder to make it look like a BlockEncoder\n// @tparam T The encapsulated ByteEncoder type.\n//           Must inherit from ByteEncoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<ByteEncoder>()) >\nclass BlockEncoder_from_ByteEncoder : public BlockEncoder<1>\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<BlockEncoder_from_ByteEncoder>()) >\n    BlockEncoder_from_ByteEncoder(Args &&... args)\n            : byte_encoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, ByteEncoder);\n    }\n\n    inline int get_status() final\n    {\n        return byte_encoder_.get_status();\n    }\n\n    inline size_t get_available_blocks() final\n    {\n        return byte_encoder_.get_available_bytes();\n    }\n\n    inline int get_block(uint8_t block[1]) final\n    {\n        int status = byte_encoder_.get_byte(*block);\n        return status;\n    }\n\nprivate:\n    T byte_encoder_;\n};\n\n// @brief Encapsulates a ByteEncoder to make it look like a StreamEncoder\n// @tparam T The encapsulated ByteEncoder type.\n//           Must inherit from ByteEncoder.\ntemplate<typename T, ENABLE_IF(TypeChecker<T>::template all_are<ByteEncoder>()) >\nclass StreamEncoder_from_ByteEncoder : public StreamEncoder\n{\npublic:\n    // @brief Imitates the constructor signature of the encapsulated type.\n    template<typename ... Args, ENABLE_IF(\n            TypeChecker<Args...>::template first_is_not<StreamEncoder_from_ByteEncoder>()) >\n    StreamEncoder_from_ByteEncoder(Args &&... args)\n            : byte_encoder_(std::forward<Args>(args)...)\n    {\n        EXPECT_TYPE(T, ByteEncoder);\n    }\n\n    inline int get_status() final\n    {\n        return byte_encoder_.get_status();\n    }\n\n    inline size_t get_available_bytes() final\n    {\n        return byte_encoder_.get_available_bytes();\n    }\n\n    inline int get_bytes(uint8_t *buffer, size_t length, size_t *generated_bytes) final\n    {\n        while (!byte_encoder_.get_status() && byte_encoder_.get_available_bytes() && length)\n        {\n            length--;\n            if (generated_bytes) (*generated_bytes)++;\n            byte_encoder_.get_byte(buffer++);\n        }\n        return byte_encoder_.get_status();\n    }\n\nprivate:\n    T byte_encoder_;\n};\n\n/* Encoder implementations ---------------------------------------------------*/\n\ntemplate<typename T>\nclass VarintByteEncoder : public ByteEncoder\n{\npublic:\n    static constexpr T BIT_WIDTH = (CHAR_BIT * sizeof(T));\n\n    VarintByteEncoder(const T &state_variable) :\n            state_variable_(state_variable)\n    {}\n\n    size_t get_available_bytes() final\n    {\n        return done_ ? 0 : 1;\n    }\n\n    int get_status() final\n    {\n        return 0;\n    }\n\n    int get_byte(uint8_t *output_byte) final\n    {\n        if (bit_pos_ == 0)\n            LOG_FIBRE(\"start encoding varint, from pos %d\\n\", bit_pos_);\n        *output_byte = (state_variable_ >> bit_pos_) & 0x7f;\n        bit_pos_ += 7;\n        if (bit_pos_ < BIT_WIDTH && (state_variable_ >> bit_pos_))\n        {\n            LOG_FIBRE(\"remainder: %x\\n\", state_variable_ >> bit_pos_);\n            *output_byte |= 0x80;\n        } else\n            done_ = true;\n        return 0;\n    }\n\nprivate:\n    const T &state_variable_;\n    size_t bit_pos_ = 0; // bit position\n    int status_ = 0;\n    bool done_ = false;\n};\n\ntemplate<typename T>\nusing VarintStreamEncoder = StreamEncoder_from_ByteEncoder<VarintByteEncoder<T>>;\n\ntemplate<typename T>\nVarintStreamEncoder<T> make_varint_encoder(const T &variable)\n{\n    return VarintStreamEncoder<T>(variable);\n}\n\nVarintStreamEncoder<GET_TYPE_OF(&Request::endpoint_id)> make_endpoint_id_encoder(const Request &request)\n{\n    return make_varint_encoder(request.endpoint_id);\n}\n\nVarintStreamEncoder<GET_TYPE_OF(&Request::length)> make_length_encoder(const Request &request)\n{\n    return make_varint_encoder(request.length);\n}\n\ntemplate<uint8_t INIT, uint8_t POLYNOMIAL, typename TEncoder,\n        ENABLE_IF(TypeChecker<TEncoder>::template all_are<StreamEncoder>()) >\nclass CRC8BlockEncoder : public BlockEncoder<CRC8_BLOCKSIZE>\n{\npublic:\n    CRC8BlockEncoder(TEncoder &&inner_encoder)\n            : inner_encoder_(std::forward<TEncoder>(inner_encoder))\n    {}\n\n    int get_status() final\n    {\n        return status_;\n    }\n\n    size_t get_available_blocks() final\n    {\n        return (inner_encoder_.get_available_bytes() + CRC8_BLOCKSIZE - 2) / (CRC8_BLOCKSIZE - 1);\n    }\n\n    int get_block(uint8_t block[4]) final\n    {\n        size_t generated_bytes = 0;\n        status_ = inner_encoder_.get_bytes(block, CRC8_BLOCKSIZE - 1, &generated_bytes);\n        if (status_)\n            return status_;\n\n        // zero out unused end of the block\n        while (generated_bytes < CRC8_BLOCKSIZE)\n            block[generated_bytes++] = 0;\n\n        block[CRC8_BLOCKSIZE - 1] = current_crc_ = calc_crc8<POLYNOMIAL>(current_crc_, block, CRC8_BLOCKSIZE - 1);\n        return 0;\n    }\n\nprivate:\n    TEncoder inner_encoder_;\n    int status_ = 0;\n    uint8_t current_crc_ = INIT;\n};\n\ntemplate<unsigned INIT, unsigned POLYNOMIAL, typename TEncoder>\nusing CRC8StreamEncoder = StreamEncoder_from_BlockEncoder<CRC8BlockEncoder<INIT, POLYNOMIAL, TEncoder>>;\n\ntemplate<unsigned INIT, unsigned POLYNOMIAL, typename TEncoder>\nCRC8StreamEncoder<INIT, POLYNOMIAL, TEncoder> make_crc8_encoder(TEncoder &&encoder)\n{\n    return CRC8StreamEncoder<INIT, POLYNOMIAL, TEncoder>(std::forward<TEncoder>(encoder));\n}\n\ntemplate<typename ... TEncoders>\nclass EncoderChain;\n\ntemplate<>\nclass EncoderChain<> : public StreamEncoder\n{\npublic:\n    size_t get_available_bytes() final\n    { return 0; }\n\n    int get_status() final\n    { return 0; }\n\n    int get_bytes(uint8_t *output, size_t length, size_t *generated_bytes) final\n    { return 0; }\n};\n\ntemplate<typename TEncoder, typename ... TEncoders>\nclass EncoderChain<TEncoder, TEncoders...> : public StreamEncoder\n{\npublic:\n    EncoderChain(TEncoder &&this_encoder, TEncoders &&... subsequent_encoders) :\n            this_encoder_(std::forward<TEncoder>(this_encoder)),\n            subsequent_encoders_(std::forward<TEncoders>(subsequent_encoders)...)\n    {\n        EXPECT_TYPE(TEncoder, StreamEncoder);\n    }\n\n    size_t get_available_bytes() final\n    {\n        return this_encoder_.get_available_bytes() + subsequent_encoders_.get_available_bytes();\n    }\n\n    int get_status() final\n    {\n        // If this encoder or any of the subsequent encoders failed, return error code.\n        int this_status = this_encoder_.get_status();\n        int subsequent_status = subsequent_encoders_.get_status();\n        if (this_status)\n            return this_status;\n        else if (subsequent_status)\n            return subsequent_status;\n        else\n            return 0;\n    }\n\n    int get_bytes(uint8_t *output, size_t length, size_t *generated_bytes) final\n    {\n        if (this_encoder_.get_available_bytes())\n        {\n            LOG_FIBRE(\"encoder chain: generate %zu bytes in segment %s\\n\", length, typeid(TEncoder).name());\n            size_t chunk = 0;\n            int status = this_encoder_.get_bytes(output, length, &chunk);\n            if (status)\n                return status;\n            output += chunk;\n            length -= chunk;\n            if (generated_bytes) *generated_bytes += chunk;\n            if (!length)\n                return 0;\n        }\n        return subsequent_encoders_.get_bytes(output, length, generated_bytes);\n    }\n\nprivate:\n    TEncoder this_encoder_;\n    EncoderChain<TEncoders...> subsequent_encoders_;\n};\n\ntemplate<typename ... TEncoders>\nEncoderChain<TEncoders...> make_encoder_chain(TEncoders &&... encoders)\n{\n    return EncoderChain<TEncoders...>(std::forward<TEncoders>(encoders)...);\n}\n\n#endif // __ENCODERS_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/include/fibre/protocol.hpp",
    "content": "/*\nsee protocol.md for the protocol specification\n*/\n\n#ifndef __PROTOCOL_HPP\n#define __PROTOCOL_HPP\n\n// TODO: resolve assert\n#define assert(expr)\n\n#include <functional>\n#include <limits>\n#include <cmath>\n//#include <stdint.h>\n#include <string.h>\n#include \"crc.hpp\"\n#include \"cpp_utils.hpp\"\n\n// Note that this option cannot be used to debug UART because it prints on UART\n//#define DEBUG_FIBRE\n#ifdef DEBUG_FIBRE\n#define LOG_FIBRE(...)  do { printf(__VA_ARGS__); } while (0)\n#else\n#define LOG_FIBRE(...)  ((void) 0)\n#endif\n\n\n// Default CRC-8 Polynomial: x^8 + x^5 + x^4 + x^2 + x + 1\n// Can protect a 4 byte payload against toggling of up to 5 bits\n//  source: https://users.ece.cmu.edu/~koopman/crc/index.html\nconstexpr uint8_t CANONICAL_CRC8_POLYNOMIAL = 0x37;\nconstexpr uint8_t CANONICAL_CRC8_INIT = 0x42;\n\nconstexpr size_t CRC8_BLOCKSIZE = 4;\n\n// Default CRC-16 Polynomial: 0x9eb2 x^16 + x^13 + x^12 + x^11 + x^10 + x^8 + x^6 + x^5 + x^2 + 1\n// Can protect a 135 byte payload against toggling of up to 5 bits\n//  source: https://users.ece.cmu.edu/~koopman/crc/index.html\n// Also known as CRC-16-DNP\nconstexpr uint16_t CANONICAL_CRC16_POLYNOMIAL = 0x3d65;\nconstexpr uint16_t CANONICAL_CRC16_INIT = 0x1337;\n\nconstexpr uint8_t CANONICAL_PREFIX = 0xAA;\n\n\n/* move to fibre_config.h ******************************/\n\ntypedef size_t endpoint_id_t;\n\nstruct ReceiverState\n{\n    endpoint_id_t endpoint_id;\n    size_t length;\n    uint16_t seqno_thread;\n    uint16_t seqno;\n    bool expect_ack;\n    bool expect_response;\n    bool enforce_ordering;\n};\n\n/*******************************************************/\n\n\n\n#include <unistd.h>\n\nconstexpr uint16_t PROTOCOL_VERSION = 1;\n\n// This value must not be larger than USB_TX_DATA_SIZE defined in usbd_cdc_if.h\nconstexpr uint16_t TX_BUF_SIZE = 32; // does not work with 64 for some reason\nconstexpr uint16_t RX_BUF_SIZE = 128; // larger values than 128 have currently no effect because of protocol limitations\n\n// Maximum time we allocate for processing and responding to a request\nconstexpr uint32_t PROTOCOL_SERVER_TIMEOUT_MS = 10;\n\n\ntypedef struct\n{\n    uint16_t json_crc;\n    uint16_t node_id;\n    uint16_t endpoint_id;\n} endpoint_ref_t;\n\n#include <cstring>\n\ntemplate<typename T, typename = typename std::enable_if_t<!std::is_const<T>::value>>\ninline size_t write_le(T value, uint8_t *buffer)\n{\n    //TODO: add static_assert that this is still a little endian machine\n    std::memcpy(&buffer[0], &value, sizeof(value));\n    return sizeof(value);\n}\n\ntemplate<typename T>\ntypename std::enable_if_t<std::is_const<T>::value, size_t>\nwrite_le(T value, uint8_t *buffer)\n{\n    return write_le<std::remove_const_t<T>>(value, buffer);\n}\n\ntemplate<>\ninline size_t write_le<float>(float value, uint8_t *buffer)\n{\n    static_assert(CHAR_BIT * sizeof(float) == 32, \"32 bit floating point expected\");\n    static_assert(std::numeric_limits<float>::is_iec559, \"IEEE 754 floating point expected\");\n    const uint32_t *value_as_uint32 = reinterpret_cast<const uint32_t *>(&value);\n    return write_le<uint32_t>(*value_as_uint32, buffer);\n}\n\ntemplate<typename T>\ninline size_t read_le(T *value, const uint8_t *buffer)\n{\n    // TODO: add static_assert that this is still a little endian machine\n    std::memcpy(value, buffer, sizeof(*value));\n    return sizeof(*value);\n}\n\ntemplate<>\ninline size_t read_le<float>(float *value, const uint8_t *buffer)\n{\n    static_assert(CHAR_BIT * sizeof(float) == 32, \"32 bit floating point expected\");\n    static_assert(std::numeric_limits<float>::is_iec559, \"IEEE 754 floating point expected\");\n\n    return read_le(reinterpret_cast<uint32_t *>(value), buffer);\n}\n\n// @brief Reads a value of type T from the buffer.\n// @param buffer    Pointer to the buffer to be read. The pointer is updated by the number of bytes that were read.\n// @param length    The number of available bytes in buffer. This value is updated to subtract the bytes that were read.\ntemplate<typename T>\nstatic inline T read_le(const uint8_t **buffer, size_t *length)\n{\n    T result;\n    size_t cnt = read_le(&result, *buffer);\n    *buffer += cnt;\n    *length -= cnt;\n    return result;\n}\n\nclass PacketSink\n{\npublic:\n    // @brief Get the maximum packet length (aka maximum transmission unit)\n    // A packet size shall take no action and return an error code if the\n    // caller attempts to send an oversized packet.\n    //virtual size_t get_mtu() = 0;\n\n    // @brief Processes a packet.\n    // The blocking behavior shall depend on the thread-local deadline_ms variable.\n    // @return: 0 on success, otherwise a non-zero error code\n    // TODO: define what happens when the packet is larger than what the implementation can handle.\n    virtual int process_packet(const uint8_t *buffer, size_t length) = 0;\n};\n\nclass StreamSink\n{\npublic:\n    enum ChannelType_t\n    {\n        CHANNEL_TYPE_USB,\n        CHANNEL_TYPE_UART4,\n        CHANNEL_TYPE_UART5\n    };\n\n    ChannelType_t channelType;\n    // @brief Processes a chunk of bytes that is part of a continuous stream.\n    // The blocking behavior shall depend on the thread-local deadline_ms variable.\n    // @param processed_bytes: if not NULL, shall be incremented by the number of\n    //        bytes that were consumed.\n    // @return: 0 on success, otherwise a non-zero error code\n    virtual int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes) = 0;\n\n    // @brief Returns the number of bytes that can still be written to the stream.\n    // Shall return SIZE_MAX if the stream has unlimited lenght.\n    // TODO: deprecate\n    virtual size_t get_free_space() = 0;\n\n    /*int process_bytes(const uint8_t* buffer, size_t length) {\n        size_t processed_bytes = 0;\n        return process_bytes(buffer, length, &processed_bytes);\n    }*/\n};\n\nclass StreamSource\n{\npublic:\n    // @brief Generate a chunk of bytes that are part of a continuous stream.\n    // The blocking behavior shall depend on the thread-local deadline_ms variable.\n    // @param generated_bytes: if not NULL, shall be incremented by the number of\n    //        bytes that were written to buffer.\n    // @return: 0 on success, otherwise a non-zero error code\n    virtual int get_bytes(uint8_t *buffer, size_t length, size_t *generated_bytes) = 0;\n\n    // @brief Returns the number of bytes that can still be written to the stream.\n    // Shall return SIZE_MAX if the stream has unlimited lenght.\n    // TODO: deprecate\n    //virtual size_t get_free_space() = 0;\n};\n\nclass StreamToPacketSegmenter : public StreamSink\n{\npublic:\n    StreamToPacketSegmenter(PacketSink &output) :\n            output_(output)\n    {\n    };\n\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes);\n\n    size_t get_free_space()\n    { return SIZE_MAX; }\n\nprivate:\n    uint8_t header_buffer_[3];\n    size_t header_index_ = 0;\n    uint8_t packet_buffer_[RX_BUF_SIZE];\n    size_t packet_index_ = 0;\n    size_t packet_length_ = 0;\n    PacketSink &output_;\n};\n\n\nclass StreamBasedPacketSink : public PacketSink\n{\npublic:\n    StreamBasedPacketSink(StreamSink &output) :\n            output_(output)\n    {\n    };\n\n    //size_t get_mtu() { return SIZE_MAX; }\n    int process_packet(const uint8_t *buffer, size_t length);\n\nprivate:\n    StreamSink &output_;\n};\n\n// @brief: Represents a stream sink that's based on an underlying packet sink.\n// A single call to process_bytes may result in multiple packets being sent.\nclass PacketBasedStreamSink : public StreamSink\n{\npublic:\n    PacketBasedStreamSink(PacketSink &packet_sink) : _packet_sink(packet_sink)\n    {}\n\n    ~PacketBasedStreamSink()\n    {}\n\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes)\n    {\n        // Loop to ensure all bytes get sent\n        while (length)\n        {\n            size_t chunk = length;\n            // send chunk as packet\n            if (_packet_sink.process_packet(buffer, chunk))\n                return -1;\n            buffer += chunk;\n            length -= chunk;\n            if (processed_bytes)\n                *processed_bytes += chunk;\n        }\n        return 0;\n    }\n\n    size_t get_free_space()\n    { return SIZE_MAX; }\n\nprivate:\n    PacketSink &_packet_sink;\n};\n\n// Implements the StreamSink interface by writing into a fixed size\n// memory buffer.\nclass MemoryStreamSink : public StreamSink\n{\npublic:\n    MemoryStreamSink(uint8_t *buffer, size_t length) :\n            buffer_(buffer),\n            buffer_length_(length)\n    {}\n\n    // Returns 0 on success and -1 if the buffer could not accept everything because it became full\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes)\n    {\n        size_t chunk = length < buffer_length_ ? length : buffer_length_;\n        memcpy(buffer_, buffer, chunk);\n        buffer_ += chunk;\n        buffer_length_ -= chunk;\n        if (processed_bytes)\n            *processed_bytes += chunk;\n        return chunk == length ? 0 : -1;\n    }\n\n    size_t get_free_space()\n    { return buffer_length_; }\n\nprivate:\n    uint8_t *buffer_;\n    size_t buffer_length_;\n};\n\n// Implements the StreamSink interface by discarding the first couple of bytes\n// and then forwarding the rest to another stream.\nclass NullStreamSink : public StreamSink\n{\npublic:\n    NullStreamSink(size_t skip, StreamSink &follow_up_stream) :\n            skip_(skip),\n            follow_up_stream_(follow_up_stream)\n    {}\n\n    // Returns 0 on success and -1 if the buffer could not accept everything because it became full\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes)\n    {\n        if (skip_ < length)\n        {\n            buffer += skip_;\n            length -= skip_;\n            if (processed_bytes)\n                *processed_bytes += skip_;\n            skip_ = 0;\n            return follow_up_stream_.process_bytes(buffer, length, processed_bytes);\n        } else\n        {\n            skip_ -= length;\n            if (processed_bytes)\n                *processed_bytes += length;\n            return 0;\n        }\n    }\n\n    size_t get_free_space()\n    { return skip_ + follow_up_stream_.get_free_space(); }\n\nprivate:\n    size_t skip_;\n    StreamSink &follow_up_stream_;\n};\n\n\n// Implements the StreamSink interface by calculating the CRC16 checksum\n// on the data that is sent to it.\nclass CRC16Calculator : public StreamSink\n{\npublic:\n    CRC16Calculator(uint16_t crc16_init) :\n            crc16_(crc16_init)\n    {}\n\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes)\n    {\n        crc16_ = calc_crc16<CANONICAL_CRC16_POLYNOMIAL>(crc16_, buffer, length);\n        if (processed_bytes)\n            *processed_bytes += length;\n        return 0;\n    }\n\n    size_t get_free_space()\n    { return SIZE_MAX; }\n\n    uint16_t get_crc16()\n    { return crc16_; }\n\nprivate:\n    uint16_t crc16_;\n};\n\n\n// @brief Endpoint request handler\n//\n// When passed a valid endpoint context, implementing functions shall handle an\n// endpoint read/write request by reading the provided input data and filling in\n// output data. The exact semantics of this function depends on the corresponding\n// endpoint's specification.\n//\n// @param input: pointer to the input data\n// @param input_length: number of available input bytes\n// @param output: The stream where to write the output to. Can be null.\n//                The handler shall abort as soon as the stream returns\n//                a non-zero error code on write.\ntypedef std::function<void(void *ctx, const uint8_t *input, size_t input_length, StreamSink *output)> EndpointHandler;\n\n\n// @brief Default endpoint handler for const types\n// @return: True if endpoint was written to, False otherwise\ntemplate<typename T>\nstd::enable_if_t<!std::is_same<T, endpoint_ref_t>::value && std::is_const<T>::value, bool>\ndefault_readwrite_endpoint_handler(T *value, const uint8_t *input, size_t input_length, StreamSink *output)\n{\n    // If the old value was requested, call the corresponding little endian serialization function\n    if (output)\n    {\n        // TODO: make buffer size dependent on the type\n        uint8_t buffer[sizeof(T)];\n        size_t cnt = write_le<T>(*value, buffer);\n        if (cnt <= output->get_free_space())\n            output->process_bytes(buffer, cnt, nullptr);\n    }\n    return false; // We don't ever write to const types\n}\n\n// @brief Default endpoint handler for non-const types\ntemplate<typename T>\nstd::enable_if_t<!std::is_same<T, endpoint_ref_t>::value && !std::is_const<T>::value, bool>\ndefault_readwrite_endpoint_handler(T *value, const uint8_t *input, size_t input_length, StreamSink *output)\n{\n    // Read the endpoint value into output\n    default_readwrite_endpoint_handler<const T>(const_cast<const T *>(value), input, input_length, output);\n\n    // If a new value was passed, call the corresponding little endian deserialization function\n    uint8_t buffer[sizeof(T)] = {0}; // TODO: make buffer size dependent on the type\n    if (input_length >= sizeof(buffer))\n    {\n        read_le<T>(value, input);\n        return true;\n    } else\n    {\n        return false;\n    }\n}\n\n// @brief Default endpoint handler for endpoint_ref_t types\ntemplate<typename T>\nbool\ndefault_readwrite_endpoint_handler(endpoint_ref_t *value, const uint8_t *input, size_t input_length, StreamSink *output)\n{\n    constexpr size_t size = sizeof(value->endpoint_id) + sizeof(value->json_crc);\n    if (output)\n    {\n        // TODO: make buffer size dependent on the type\n        uint8_t buffer[size];\n        size_t cnt = write_le<decltype(value->endpoint_id)>(value->endpoint_id, buffer);\n        cnt += write_le<decltype(value->json_crc)>(value->json_crc, buffer + cnt);\n        if (cnt <= output->get_free_space())\n            output->process_bytes(buffer, cnt, nullptr);\n    }\n\n    // If a new value was passed, call the corresponding little endian deserialization function\n    if (input_length >= size)\n    {\n        read_le<decltype(value->endpoint_id)>(&value->endpoint_id, input);\n        read_le<decltype(value->json_crc)>(&value->json_crc, input + 2);\n        return true;\n    } else\n    {\n        return false;\n    }\n}\n\ntemplate<typename T>\nstatic inline const char *get_default_json_modifier();\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const float>()\n{\n    return \"\\\"type\\\":\\\"float\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<float>()\n{\n    return \"\\\"type\\\":\\\"float\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const int64_t>()\n{\n    return \"\\\"type\\\":\\\"int64\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<int64_t>()\n{\n    return \"\\\"type\\\":\\\"int64\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const uint64_t>()\n{\n    return \"\\\"type\\\":\\\"uint64\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<uint64_t>()\n{\n    return \"\\\"type\\\":\\\"uint64\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const int32_t>()\n{\n    return \"\\\"type\\\":\\\"int32\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<int32_t>()\n{\n    return \"\\\"type\\\":\\\"int32\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const uint32_t>()\n{\n    return \"\\\"type\\\":\\\"uint32\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<uint32_t>()\n{\n    return \"\\\"type\\\":\\\"uint32\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const uint16_t>()\n{\n    return \"\\\"type\\\":\\\"uint16\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<uint16_t>()\n{\n    return \"\\\"type\\\":\\\"uint16\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const uint8_t>()\n{\n    return \"\\\"type\\\":\\\"uint8\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<uint8_t>()\n{\n    return \"\\\"type\\\":\\\"uint8\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<const bool>()\n{\n    return \"\\\"type\\\":\\\"bool\\\",\\\"access\\\":\\\"r\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<bool>()\n{\n    return \"\\\"type\\\":\\\"bool\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\ntemplate<>\ninline constexpr const char *get_default_json_modifier<endpoint_ref_t>()\n{\n    return \"\\\"type\\\":\\\"endpoint_ref\\\",\\\"access\\\":\\\"rw\\\"\";\n}\n\nclass Endpoint\n{\npublic:\n    //const char* const name_;\n    virtual void handle(const uint8_t *input, size_t input_length, StreamSink *output) = 0;\n\n    virtual bool get_string(char *output, size_t length)\n    { return false; }\n\n    virtual bool set_string(char *buffer, size_t length)\n    { return false; }\n\n    virtual bool set_from_float(float value)\n    { return false; }\n};\n\nstatic inline int write_string(const char *str, StreamSink *output)\n{\n    return output->process_bytes(reinterpret_cast<const uint8_t *>(str), strlen(str), nullptr);\n}\n\n\n/* @brief Handles the communication protocol on one channel.\n*\n* When instantiated with a list of endpoints and an output packet sink,\n* objects of this class will handle packets passed into process_packet,\n* pass the relevant data to the corresponding endpoints and dispatch response\n* packets on the output.\n*/\nclass BidirectionalPacketBasedChannel : public PacketSink\n{\npublic:\n    BidirectionalPacketBasedChannel(PacketSink &output) :\n            output_(output)\n    {}\n\n    //size_t get_mtu() {\n    //    return SIZE_MAX;\n    //}\n    int process_packet(const uint8_t *buffer, size_t length);\n\nprivate:\n    PacketSink &output_;\n    uint8_t tx_buf_[TX_BUF_SIZE];\n};\n\n\n/* ToString / FromString functions -------------------------------------------*/\n/*\n* These functions are currently not used by Fibre and only here to\n* support the ODrive ASCII protocol.\n* TODO: find a general way for client code to augment endpoints with custom\n* functions\n*/\n\ntemplate<typename T>\nstruct format_traits_t;\n\n// template<> struct format_traits_t<float> { using type = void;\n//     static constexpr const char * fmt = \"%f\";\n//     static constexpr const char * fmtp = \"%f\";\n// };\ntemplate<>\nstruct format_traits_t<int64_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%lld\";\n    static constexpr const char *fmtp = \"%lld\";\n};\ntemplate<>\nstruct format_traits_t<uint64_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%llu\";\n    static constexpr const char *fmtp = \"%llu\";\n};\ntemplate<>\nstruct format_traits_t<int32_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%ld\";\n    static constexpr const char *fmtp = \"%ld\";\n};\ntemplate<>\nstruct format_traits_t<uint32_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%lu\";\n    static constexpr const char *fmtp = \"%lu\";\n};\ntemplate<>\nstruct format_traits_t<int16_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%hd\";\n    static constexpr const char *fmtp = \"%hd\";\n};\ntemplate<>\nstruct format_traits_t<uint16_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%hu\";\n    static constexpr const char *fmtp = \"%hu\";\n};\ntemplate<>\nstruct format_traits_t<int8_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%hhd\";\n    static constexpr const char *fmtp = \"%d\";\n};\ntemplate<>\nstruct format_traits_t<uint8_t>\n{\n    using type = void;\n    static constexpr const char *fmt = \"%hhu\";\n    static constexpr const char *fmtp = \"%u\";\n};\n\ntemplate<typename T, typename = typename format_traits_t<T>::type>\nstatic bool to_string(const T &value, char *buffer, size_t length, int)\n{\n    snprintf(buffer, length, format_traits_t<T>::fmtp, value);\n    return true;\n}\n\n// Special case for float because printf promotes float to double, and we get warnings\ntemplate<typename T = float>\nstatic bool to_string(const float &value, char *buffer, size_t length, int)\n{\n    snprintf(buffer, length, \"%f\", (double) value);\n    return true;\n}\n\ntemplate<typename T = bool>\nstatic bool to_string(const bool &value, char *buffer, size_t length, int)\n{\n    buffer[0] = value ? '1' : '0';\n    buffer[1] = 0;\n    return true;\n}\n\ntemplate<typename T>\nstatic bool to_string(const T &value, char *buffer, size_t length, ...)\n{\n    return false;\n}\n\ntemplate<typename T, typename = typename format_traits_t<T>::type>\nstatic bool from_string(const char *buffer, size_t length, T *property, int)\n{\n    return sscanf(buffer, format_traits_t<T>::fmt, property) == 1;\n}\n\n// Special case for float because printf promotes float to double, and we get warnings\ntemplate<typename T = float>\nstatic bool from_string(const char *buffer, size_t length, float *property, int)\n{\n    return sscanf(buffer, \"%f\", property) == 1;\n}\n\ntemplate<typename T = bool>\nstatic bool from_string(const char *buffer, size_t length, bool *property, int)\n{\n    int val;\n    if (sscanf(buffer, \"%d\", &val) != 1)\n        return false;\n    *property = val;\n    return true;\n}\n\ntemplate<typename T>\nstatic bool from_string(const char *buffer, size_t length, T *property, ...)\n{\n    return false;\n}\n\n\n/* Object tree ---------------------------------------------------------------*/\n\ntemplate<typename ... TMembers>\nstruct MemberList;\n\ntemplate<>\nstruct MemberList<>\n{\npublic:\n    static constexpr size_t endpoint_count = 0;\n    static constexpr bool is_empty = true;\n\n    void write_json(size_t id, StreamSink *output)\n    {\n        // no action\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length)\n    {\n        // no action\n    }\n\n    Endpoint *get_by_name(const char *name, size_t length)\n    {\n        return nullptr;\n    }\n\n    std::tuple<> get_names_as_tuple() const\n    { return std::tuple<>(); }\n};\n\ntemplate<typename TMember, typename ... TMembers>\nstruct MemberList<TMember, TMembers...>\n{\npublic:\n    static constexpr size_t endpoint_count = TMember::endpoint_count + MemberList<TMembers...>::endpoint_count;\n    static constexpr bool is_empty = false;\n\n    MemberList(TMember &&this_member, TMembers &&... subsequent_members) :\n            this_member_(std::forward<TMember>(this_member)),\n            subsequent_members_(std::forward<TMembers>(subsequent_members)...)\n    {}\n\n    MemberList(TMember &&this_member, MemberList<TMembers...> &&subsequent_members) :\n            this_member_(std::forward<TMember>(this_member)),\n            subsequent_members_(std::forward<MemberList<TMembers...>>(subsequent_members))\n    {}\n\n    // @brief Move constructor\n/*    MemberList(MemberList&& other) :\n        this_member_(std::move(other.this_member_)),\n        subsequent_members_(std::move(other.subsequent_members_)) {}*/\n\n    void write_json(size_t id, StreamSink *output) /*final*/ {\n        this_member_.write_json(id, output);\n        if (!MemberList<TMembers...>::is_empty)\n            write_string(\",\", output);\n        subsequent_members_.write_json(id + TMember::endpoint_count, output);\n    }\n\n    Endpoint *get_by_name(const char *name, size_t length)\n    {\n        Endpoint *result = this_member_.get_by_name(name, length);\n        if (result) return result;\n        else return subsequent_members_.get_by_name(name, length);\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length) /*final*/ {\n        this_member_.register_endpoints(list, id, length);\n        subsequent_members_.register_endpoints(list, id + TMember::endpoint_count, length);\n    }\n\n    TMember this_member_;\n    MemberList<TMembers...> subsequent_members_;\n};\n\ntemplate<typename ... TMembers>\nMemberList<TMembers...> make_protocol_member_list(TMembers &&... member_list)\n{\n    return MemberList<TMembers...>(std::forward<TMembers>(member_list)...);\n}\n\ntemplate<typename ... TMembers>\nclass ProtocolObject\n{\npublic:\n    ProtocolObject(const char *name, TMembers &&... member_list) :\n            name_(name),\n            member_list_(std::forward<TMembers>(member_list)...)\n    {}\n\n    static constexpr size_t endpoint_count = MemberList<TMembers...>::endpoint_count;\n\n    void write_json(size_t id, StreamSink *output)\n    {\n        write_string(\"{\\\"name\\\":\\\"\", output);\n        write_string(name_, output);\n        write_string(\"\\\",\\\"type\\\":\\\"object\\\",\\\"members\\\":[\", output);\n        member_list_.write_json(id, output),\n                write_string(\"]}\", output);\n    }\n\n    Endpoint *get_by_name(const char *name, size_t length)\n    {\n        size_t segment_length = strlen(name);\n        if (!strncmp(name, name_, length))\n            return member_list_.get_by_name(name + segment_length + 1, length - segment_length - 1);\n        else\n            return nullptr;\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length)\n    {\n        member_list_.register_endpoints(list, id, length);\n    }\n\n    const char *name_;\n    MemberList<TMembers...> member_list_;\n};\n\ntemplate<typename ... TMembers>\nProtocolObject<TMembers...> make_protocol_object(const char *name, TMembers &&... member_list)\n{\n    return ProtocolObject<TMembers...>(name, std::forward<TMembers>(member_list)...);\n}\n\n//template<typename T, typename = typename std>\n//bool set_from_float_ex(float value, T* property) {\n//    return false;\n//}\n\nnamespace conversion\n{\n//template<typename T>\n    template<typename T>\n    bool set_from_float_ex(float value, float *property, int)\n    {\n        return *property = value, true;\n    }\n\n    template<typename T>\n    bool set_from_float_ex(float value, bool *property, int)\n    {\n        return *property = (value >= 0.0f), true;\n    }\n\n    template<typename T, typename = std::enable_if_t<std::is_integral<T>::value && !std::is_const<T>::value>>\n    bool set_from_float_ex(float value, T *property, int)\n    {\n        return *property = static_cast<T>(std::round(value)), true;\n    }\n\n    template<typename T>\n    bool set_from_float_ex(float value, T *property, ...)\n    {\n        return false;\n    }\n\n    template<typename T>\n    bool set_from_float(float value, T *property)\n    {\n        return set_from_float_ex<T>(value, property, 0);\n    }\n}\n\n//template<typename T>\n//bool set_from_float_ex<>(float value, T* property) {\n//    return false;\n//}\n\n\ntemplate<typename TProperty>\nclass ProtocolProperty : public Endpoint\n{\npublic:\n    static constexpr const char *json_modifier = get_default_json_modifier<TProperty>();\n    static constexpr size_t endpoint_count = 1;\n\n    ProtocolProperty(const char *name, TProperty *property,\n                     void (*written_hook)(void *), void *ctx)\n            : name_(name), property_(property), written_hook_(written_hook), ctx_(ctx)\n    {}\n\n/*  TODO: find out why the move constructor is not used when it could be\n    ProtocolProperty(const ProtocolProperty&) = delete;\n    // @brief Move constructor\n    ProtocolProperty(ProtocolProperty&& other) :\n        Endpoint(std::move(other)),\n        name_(std::move(other.name_)),\n        property_(other.property_)\n    {}\n    constexpr ProtocolProperty& operator=(const ProtocolProperty& other) = delete;\n    constexpr ProtocolProperty& operator=(const ProtocolProperty& other) {\n        //Endpoint(std::move(other)),\n        //name_(std::move(other.name_)),\n        //property_(other.property_)\n        name_ = other.name_;\n        property_ = other.property_;\n        return *this;\n    }\n    ProtocolProperty& operator=(ProtocolProperty&& other)\n        : name_(other.name_), property_(other.property_)\n    {}\n    ProtocolProperty& operator=(const ProtocolProperty& other)\n        : name_(other.name_), property_(other.property_)\n    {}*/\n\n    void write_json(size_t id, StreamSink *output)\n    {\n        // write name\n        write_string(\"{\\\"name\\\":\\\"\", output);\n        LOG_FIBRE(\"json: this at %x, name at %x is s\\r\\n\", (uintptr_t) this, (uintptr_t) name_);\n        //LOG_FIBRE(\"json\\r\\n\");\n        write_string(name_, output);\n\n        // write endpoint ID\n        write_string(\"\\\",\\\"id\\\":\", output);\n        char id_buf[10];\n        snprintf(id_buf, sizeof(id_buf), \"%u\", (unsigned) id); // TODO: get rid of printf\n        write_string(id_buf, output);\n\n        // write additional JSON data\n        if (json_modifier && json_modifier[0])\n        {\n            write_string(\",\", output);\n            write_string(json_modifier, output);\n        }\n\n        write_string(\"}\", output);\n    }\n\n    // special-purpose function - to be moved\n    Endpoint *get_by_name(const char *name, size_t length)\n    {\n        if (!strncmp(name, name_, length))\n            return this;\n        else\n            return nullptr;\n    }\n\n    // special-purpose function - to be moved\n    bool get_string(char *buffer, size_t length) final\n    {\n        return to_string(*property_, buffer, length, 0);\n    }\n\n    // special-purpose function - to be moved\n    bool set_string(char *buffer, size_t length) final\n    {\n        return from_string(buffer, length, property_, 0);\n    }\n\n    bool set_from_float(float value) final\n    {\n        return conversion::set_from_float(value, property_);\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length)\n    {\n        if (id < length)\n            list[id] = this;\n    }\n\n    void handle(const uint8_t *input, size_t input_length, StreamSink *output) final\n    {\n        bool wrote = default_readwrite_endpoint_handler<TProperty>(property_, input, input_length, output);\n        if (wrote && written_hook_ != nullptr)\n        {\n            written_hook_(ctx_);\n        }\n    }\n\n    /*void handle(const uint8_t* input, size_t input_length, StreamSink* output) {\n        handle(input, input_length, output);\n    }*/\n\n    const char *name_;\n    TProperty *property_;\n\n    void (*written_hook_)(void *);\n\n    void *ctx_;\n};\n\n// Non-const non-enum types\ntemplate<typename TProperty, ENABLE_IF(!std::is_enum<TProperty>::value) >\nProtocolProperty<TProperty> make_protocol_property(const char *name, TProperty *property,\n                                                   void (*written_hook)(void *) = nullptr, void *ctx = nullptr)\n{\n    return ProtocolProperty<TProperty>(name, property, written_hook, ctx);\n};\n\n// Const non-enum types\ntemplate<typename TProperty, ENABLE_IF(!std::is_enum<TProperty>::value) >\nProtocolProperty<const TProperty> make_protocol_ro_property(const char *name, TProperty *property,\n                                                            void (*written_hook)(void *) = nullptr, void *ctx = nullptr)\n{\n    return ProtocolProperty<const TProperty>(name, property, written_hook, ctx);\n};\n\n// Non-const enum types\ntemplate<typename TProperty, ENABLE_IF(std::is_enum<TProperty>::value) >\nProtocolProperty<std::underlying_type_t<TProperty>> make_protocol_property(const char *name, TProperty *property,\n                                                                           void (*written_hook)(void *) = nullptr,\n                                                                           void *ctx = nullptr)\n{\n    return ProtocolProperty<std::underlying_type_t<TProperty>>(\n            name, reinterpret_cast<std::underlying_type_t<TProperty> *>(property), written_hook, ctx);\n};\n\n// Const enum types\ntemplate<typename TProperty, ENABLE_IF(std::is_enum<TProperty>::value) >\nProtocolProperty<const std::underlying_type_t<TProperty>>\nmake_protocol_ro_property(const char *name, TProperty *property,\n                          void (*written_hook)(void *) = nullptr, void *ctx = nullptr)\n{\n    return ProtocolProperty<const std::underlying_type_t<TProperty>>(\n            name, reinterpret_cast<const std::underlying_type_t<TProperty> *>(property), written_hook, ctx);\n};\n\n\ntemplate<typename ... TArgs>\nstruct PropertyListFactory;\n\ntemplate<>\nstruct PropertyListFactory<>\n{\n    template<unsigned IPos, typename ... TAllProperties>\n    static MemberList<>\n    make_property_list(std::array<const char *, sizeof...(TAllProperties)> names, std::tuple<TAllProperties...> &values)\n    {\n        return MemberList<>();\n    }\n};\n\ntemplate<typename TProperty, typename ... TProperties>\nstruct PropertyListFactory<TProperty, TProperties...>\n{\n    template<unsigned IPos, typename ... TAllProperties>\n    static MemberList<ProtocolProperty<TProperty>, ProtocolProperty<TProperties>...>\n    make_property_list(std::array<const char *, sizeof...(TAllProperties)> names, std::tuple<TAllProperties...> &values)\n    {\n        return MemberList<ProtocolProperty<TProperty>, ProtocolProperty<TProperties>...>(\n                make_protocol_property(std::get<IPos>(names), &std::get<IPos>(values)),\n                PropertyListFactory<TProperties...>::template make_property_list<IPos + 1>(names, values)\n        );\n    }\n};\n\n/* @brief return_type<TypeList>::type represents the true return type\n* of a function returning 0 or more arguments.\n*\n* For an empty TypeList, the return type is void. For a list with\n* one type, the return type is equal to that type. For a list with\n* more than one items, the return type is a tuple.\n*/\ntemplate<typename ... Types>\nstruct return_type;\n\ntemplate<>\nstruct return_type<>\n{\n    typedef void type;\n};\ntemplate<typename T>\nstruct return_type<T>\n{\n    typedef T type;\n};\ntemplate<typename T, typename ... Ts>\nstruct return_type<T, Ts...>\n{\n    typedef std::tuple<T, Ts...> type;\n};\n\n\ntemplate<typename TObj, typename ... TInputsAndOutputs>\nclass ProtocolFunction;\n\ntemplate<typename TObj, typename ... TInputs, typename ... TOutputs>\nclass ProtocolFunction<TObj, std::tuple<TInputs...>, std::tuple<TOutputs...>> : Endpoint\n{\npublic:\n    // @brief The return type of the function as written by a C++ programmer\n    using TRet = typename return_type<TOutputs...>::type;\n\n    static constexpr size_t endpoint_count = 1 + MemberList<ProtocolProperty<TInputs>...>::endpoint_count +\n                                             MemberList<ProtocolProperty<TOutputs>...>::endpoint_count;\n\n    ProtocolFunction(const char *name, TObj &obj, TRet(TObj::*func_ptr)(TInputs...),\n                     std::array<const char *, sizeof...(TInputs)> input_names,\n                     std::array<const char *, sizeof...(TOutputs)> output_names) :\n            name_(name), obj_(&obj), func_ptr_(func_ptr),\n            input_names_{input_names}, output_names_{output_names},\n            input_properties_(PropertyListFactory<TInputs...>::template make_property_list<0>(input_names_, in_args_)),\n            output_properties_(\n                    PropertyListFactory<TOutputs...>::template make_property_list<0>(output_names_, out_args_))\n    {\n        LOG_FIBRE(\"my tuple is at %x and of size %u\\r\\n\", (uintptr_t) &in_args_, sizeof(in_args_));\n    }\n\n    // The custom copy constructor is needed because otherwise the\n    // input_properties_ and output_properties_ would point to memory\n    // locations of the old object.\n    ProtocolFunction(const ProtocolFunction &other) :\n            name_(other.name_), obj_(other.obj_), func_ptr_(other.func_ptr_),\n            input_names_{other.input_names_}, output_names_{other.output_names_},\n            input_properties_(PropertyListFactory<TInputs...>::template make_property_list<0>(input_names_, in_args_)),\n            output_properties_(\n                    PropertyListFactory<TOutputs...>::template make_property_list<0>(output_names_, out_args_))\n    {\n        LOG_FIBRE(\"COPIED! my tuple is at %x and of size %u\\r\\n\", (uintptr_t) &in_args_, sizeof(in_args_));\n    }\n\n    void write_json(size_t id, StreamSink *output)\n    {\n        // write name\n        write_string(\"{\\\"name\\\":\\\"\", output);\n        write_string(name_, output);\n\n        // write endpoint ID\n        write_string(\"\\\",\\\"id\\\":\", output);\n        char id_buf[10];\n        snprintf(id_buf, sizeof(id_buf), \"%u\", (unsigned) id); // TODO: get rid of printf\n        write_string(id_buf, output);\n\n        // write arguments\n        write_string(\",\\\"type\\\":\\\"function\\\",\\\"inputs\\\":[\", output);\n        input_properties_.write_json(id + 1, output),\n                write_string(\"],\\\"outputs\\\":[\", output);\n        output_properties_.write_json(id + 1 + decltype(input_properties_)::endpoint_count, output),\n                write_string(\"]}\", output);\n    }\n\n    // special-purpose function - to be moved\n    Endpoint *get_by_name(const char *name, size_t length)\n    {\n        return nullptr; // can't address functions by name\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length)\n    {\n        if (id < length)\n            list[id] = this;\n        input_properties_.register_endpoints(list, id + 1, length);\n        output_properties_.register_endpoints(list, id + 1 + decltype(input_properties_)::endpoint_count, length);\n    }\n\n    template<size_t i = sizeof...(TOutputs)>\n    std::enable_if_t<i == 0>\n    handle_ex()\n    {\n        invoke_function_with_tuple(*obj_, func_ptr_, in_args_);\n    }\n\n    template<size_t i = sizeof...(TOutputs)>\n    std::enable_if_t<i == 1>\n    handle_ex()\n    {\n        std::get<0>(out_args_) = invoke_function_with_tuple(*obj_, func_ptr_, in_args_);\n    }\n\n    template<size_t i = sizeof...(TOutputs)>\n    std::enable_if_t<i >= 2>\n    handle_ex()\n    {\n        out_args_ = invoke_function_with_tuple(*obj_, func_ptr_, in_args_);\n    }\n\n    void handle(const uint8_t *input, size_t input_length, StreamSink *output) final\n    {\n        (void) input;\n        (void) input_length;\n        (void) output;\n        LOG_FIBRE(\"tuple still at %x and of size %u\\r\\n\", (uintptr_t) &in_args_, sizeof(in_args_));\n        LOG_FIBRE(\"invoke function using %d and %.3f\\r\\n\", std::get<0>(in_args_), std::get<1>(in_args_));\n        handle_ex();\n    }\n\n    const char *name_;\n    TObj *obj_;\n\n    TRet (TObj::*func_ptr_)(TInputs...);\n\n    std::array<const char *, sizeof...(TInputs)> input_names_; // TODO: remove\n    std::array<const char *, sizeof...(TOutputs)> output_names_; // TODO: remove\n    std::tuple<TInputs...> in_args_;\n    std::tuple<TOutputs...> out_args_;\n    MemberList<ProtocolProperty<TInputs>...> input_properties_;\n    MemberList<ProtocolProperty<TOutputs>...> output_properties_;\n};\n\ntemplate<typename TObj, typename ... TArgs, typename ... TNames,\n        typename = std::enable_if_t<sizeof...(TArgs) == sizeof...(TNames)>>\nProtocolFunction<TObj, std::tuple<TArgs...>, std::tuple<>>\nmake_protocol_function(const char *name, TObj &obj, void(TObj::*func_ptr)(TArgs...), TNames ... names)\n{\n    return ProtocolFunction<TObj, std::tuple<TArgs...>, std::tuple<>>(name, obj, func_ptr, {names...}, {});\n}\n\ntemplate<typename TObj, typename TRet, typename ... TArgs, typename ... TNames,\n        typename = std::enable_if_t<sizeof...(TArgs) == sizeof...(TNames) && !std::is_void<TRet>::value>>\nProtocolFunction<TObj, std::tuple<TArgs...>, std::tuple<TRet>>\nmake_protocol_function(const char *name, TObj &obj, TRet(TObj::*func_ptr)(TArgs...), TNames ... names)\n{\n    return ProtocolFunction<TObj, std::tuple<TArgs...>, std::tuple<TRet>>(name, obj, func_ptr, {names...}, {\"result\"});\n}\n\n\n#define FIBRE_EXPORTS(CLASS, ...) \\\n    struct fibre_export_t { \\\n        static CLASS* obj; \\\n        using type = decltype(make_protocol_member_list(__VA_ARGS__)); \\\n    }; \\\n    fibre_export_t::type make_fibre_definitions() { \\\n        CLASS* obj = this; \\\n        return make_protocol_member_list(__VA_ARGS__); \\\n    } \\\n    fibre_export_t::type fibre_definitions = make_fibre_definitions()\n\n\nclass EndpointProvider\n{\npublic:\n    virtual size_t get_endpoint_count() = 0;\n\n    virtual void write_json(size_t id, StreamSink *output) = 0;\n\n    virtual Endpoint *get_by_name(char *name, size_t length) = 0;\n\n    virtual void register_endpoints(Endpoint **list, size_t id, size_t length) = 0;\n};\n\ntemplate<typename T>\nclass EndpointProvider_from_MemberList : public EndpointProvider\n{\npublic:\n    EndpointProvider_from_MemberList(T &member_list) : member_list_(member_list)\n    {}\n\n    size_t get_endpoint_count() final\n    {\n        return T::endpoint_count;\n    }\n\n    void write_json(size_t id, StreamSink *output) final\n    {\n        return member_list_.write_json(id, output);\n    }\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length) final\n    {\n        return member_list_.register_endpoints(list, id, length);\n    }\n\n    Endpoint *get_by_name(char *name, size_t length) final\n    {\n        for (size_t i = 0; i < length; i++)\n        {\n            if (name[i] == '.')\n                name[i] = 0;\n        }\n        name[length - 1] = 0;\n        return member_list_.get_by_name(name, length);\n    }\n\n    T &member_list_;\n};\n\n\nclass JSONDescriptorEndpoint : Endpoint\n{\npublic:\n    static constexpr size_t endpoint_count = 1;\n\n    void write_json(size_t id, StreamSink *output);\n\n    void register_endpoints(Endpoint **list, size_t id, size_t length);\n\n    void handle(const uint8_t *input, size_t input_length, StreamSink *output);\n};\n\n// defined in protocol.cpp\nextern Endpoint **endpoint_list_;\nextern size_t n_endpoints_;\nextern uint16_t json_crc_;\nextern JSONDescriptorEndpoint json_file_endpoint_;\nextern EndpointProvider *application_endpoints_;\n\nbool is_endpoint_ref_valid(endpoint_ref_t endpoint_ref);\n\nEndpoint *get_endpoint(endpoint_ref_t endpoint_ref);\n\n// @brief Registers the specified application object list using the provided endpoint table.\n// This function should only be called once during the lifetime of the application. TODO: fix this.\n// @param application_objects The application objects to be registred.\ntemplate<typename T>\nint fibre_publish(T &application_objects)\n{\n    static constexpr size_t endpoint_list_size = 1 + T::endpoint_count;\n    static Endpoint *endpoint_list[endpoint_list_size];\n    static auto endpoint_provider = EndpointProvider_from_MemberList<T>(application_objects);\n\n    json_file_endpoint_.register_endpoints(endpoint_list, 0, endpoint_list_size);\n    application_objects.register_endpoints(endpoint_list, 1, endpoint_list_size);\n\n    // Update the global endpoint table\n    endpoint_list_ = endpoint_list;\n    n_endpoints_ = endpoint_list_size;\n    application_endpoints_ = &endpoint_provider;\n\n    // Calculate the CRC16 of the JSON file.\n    // The init value is the protocol version.\n    CRC16Calculator crc16_calculator(PROTOCOL_VERSION);\n    uint8_t offset[4] = {0};\n    json_file_endpoint_.handle(offset, sizeof(offset), &crc16_calculator);\n    json_crc_ = crc16_calculator.get_crc16();\n\n    return 0;\n}\n\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/package.lua",
    "content": "\ntup.include('../tupfiles/build.lua')\n\nfibre_package = define_package{\n    sources={'protocol.cpp', 'posix_tcp.cpp', 'posix_udp.cpp'},\n    libs={'pthread'},\n    headers={'include'}\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/fibre/cpp/protocol.cpp",
    "content": "\n/* Includes ------------------------------------------------------------------*/\n\n#include <memory>\n#include <stdlib.h>\n\n#include <fibre/protocol.hpp>\n#include <fibre/crc.hpp>\n\n/* Private defines -----------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private typedef -----------------------------------------------------------*/\n/* Global constant data ------------------------------------------------------*/\n/* Global variables ----------------------------------------------------------*/\n\nEndpoint** endpoint_list_ = nullptr; // initialized by calling fibre_publish\nsize_t n_endpoints_ = 0; // initialized by calling fibre_publish\nuint16_t json_crc_; // initialized by calling fibre_publish\nJSONDescriptorEndpoint json_file_endpoint_ = JSONDescriptorEndpoint();\nEndpointProvider* application_endpoints_;\n\n/* Private constant data -----------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n\nstatic void hexdump(const uint8_t* buf, size_t len);\nstatic inline int write_string(const char* str, StreamSink* output);\n\n/* Function implementations --------------------------------------------------*/\n\n#if 0\nvoid hexdump(const uint8_t* buf, size_t len) {\n    for (size_t pos = 0; pos < len; ++pos) {\n        printf(\" %02x\", buf[pos]);\n        if ((((pos + 1) % 16) == 0) || ((pos + 1) == len))\n            printf(\"\\r\\n\");\n        osDelay(2);\n    }\n}\n#else\nvoid hexdump(const uint8_t* buf, size_t len) {\n    (void) buf;\n    (void) len;\n}\n#endif\n\n\n\nint StreamToPacketSegmenter::process_bytes(const uint8_t *buffer, size_t length, size_t* processed_bytes) {\n    int result = 0;\n\n    while (length--) {\n        if (header_index_ < sizeof(header_buffer_)) {\n            // Process header byte\n            header_buffer_[header_index_++] = *buffer;\n            if (header_index_ == 1 && header_buffer_[0] != CANONICAL_PREFIX) {\n                header_index_ = 0;\n            } else if (header_index_ == 2 && (header_buffer_[1] & 0x80)) {\n                header_index_ = 0; // TODO: support packets larger than 128 bytes\n            } else if (header_index_ == 3 && calc_crc8<CANONICAL_CRC8_POLYNOMIAL>(CANONICAL_CRC8_INIT, header_buffer_, 3)) {\n                header_index_ = 0;\n            } else if (header_index_ == 3) {\n                packet_length_ = header_buffer_[1] + 2;\n            }\n        } else if (packet_index_ < sizeof(packet_buffer_)) {\n            // Process payload byte\n            packet_buffer_[packet_index_++] = *buffer;\n        }\n\n        // If both header and packet are fully received, hand it on to the packet processor\n        if (header_index_ == 3 && packet_index_ == packet_length_) {\n            if (calc_crc16<CANONICAL_CRC16_POLYNOMIAL>(CANONICAL_CRC16_INIT, packet_buffer_, packet_length_) == 0) {\n                result |= output_.process_packet(packet_buffer_, packet_length_ - 2);\n            }\n            header_index_ = packet_index_ = packet_length_ = 0;\n        }\n        buffer++;\n        if (processed_bytes)\n            (*processed_bytes)++;\n    }\n\n    return result;\n}\n\nint StreamBasedPacketSink::process_packet(const uint8_t *buffer, size_t length) {\n    // TODO: support buffer size >= 128\n    if (length >= 128)\n        return -1;\n\n    LOG_FIBRE(\"send header\\r\\n\");\n    uint8_t header[] = {\n        CANONICAL_PREFIX,\n        static_cast<uint8_t>(length),\n        0\n    };\n    header[2] = calc_crc8<CANONICAL_CRC8_POLYNOMIAL>(CANONICAL_CRC8_INIT, header, 2);\n\n    if (output_.process_bytes(header, sizeof(header), nullptr))\n        return -1;\n    LOG_FIBRE(\"send payload:\\r\\n\");\n    hexdump(buffer, length);\n    if (output_.process_bytes(buffer, length, nullptr))\n        return -1;\n\n    LOG_FIBRE(\"send crc16\\r\\n\");\n    uint16_t crc16 = calc_crc16<CANONICAL_CRC16_POLYNOMIAL>(CANONICAL_CRC16_INIT, buffer, length);\n    uint8_t crc16_buffer[] = {\n        (uint8_t)((crc16 >> 8) & 0xff),\n        (uint8_t)((crc16 >> 0) & 0xff)\n    };\n    if (output_.process_bytes(crc16_buffer, 2, nullptr))\n        return -1;\n    LOG_FIBRE(\"sent!\\r\\n\");\n    return 0;\n}\n\n\n\nvoid JSONDescriptorEndpoint::write_json(size_t id, StreamSink* output) {\n    write_string(\"{\\\"name\\\":\\\"\\\",\", output);\n\n    // write endpoint ID\n    write_string(\"\\\"id\\\":\", output);\n    char id_buf[10];\n    snprintf(id_buf, sizeof(id_buf), \"%u\", (unsigned)id); // TODO: get rid of printf\n    write_string(id_buf, output);\n\n    write_string(\",\\\"type\\\":\\\"json\\\",\\\"access\\\":\\\"r\\\"}\", output);\n}\n\nvoid JSONDescriptorEndpoint::register_endpoints(Endpoint** list, size_t id, size_t length) {\n    if (id < length)\n        list[id] = this;\n}\n\n// Returns part of the JSON interface definition.\nvoid JSONDescriptorEndpoint::handle(const uint8_t* input, size_t input_length, StreamSink* output) {\n    // The request must contain a 32 bit integer to specify an offset\n    if (input_length < 4)\n        return;\n    uint32_t offset = 0;\n    read_le<uint32_t>(&offset, input);\n    NullStreamSink output_with_offset = NullStreamSink(offset, *output);\n\n    size_t id = 0;\n    write_string(\"[\", &output_with_offset);\n    json_file_endpoint_.write_json(id, &output_with_offset);\n    id += decltype(json_file_endpoint_)::endpoint_count;\n    write_string(\",\", &output_with_offset);\n    application_endpoints_->write_json(id, &output_with_offset);\n    write_string(\"]\", &output_with_offset);\n}\n\nint BidirectionalPacketBasedChannel::process_packet(const uint8_t* buffer, size_t length) {\n    LOG_FIBRE(\"got packet of length %d: \\r\\n\", length);\n    hexdump(buffer, length);\n    if (length < 4)\n        return -1;\n\n    uint16_t seq_no = read_le<uint16_t>(&buffer, &length);\n\n    if (seq_no & 0x8000) {\n        // TODO: ack handling\n    } else {\n        // TODO: think about some kind of ordering guarantees\n        // currently the seq_no is just used to associate a response with a request\n\n        uint16_t endpoint_id = read_le<uint16_t>(&buffer, &length);\n        bool expect_response = endpoint_id & 0x8000;\n        endpoint_id &= 0x7fff;\n\n        if (endpoint_id >= n_endpoints_)\n            return -1;\n\n        Endpoint* endpoint = endpoint_list_[endpoint_id];\n        if (!endpoint) {\n            LOG_FIBRE(\"critical: no endpoint at %d\", endpoint_id);\n            return -1;\n        }\n\n        // Verify packet trailer. The expected trailer value depends on the selected endpoint.\n        // For endpoint 0 this is just the protocol version, for all other endpoints it's a\n        // CRC over the entire JSON descriptor tree (this may change in future versions).\n        uint16_t expected_trailer = endpoint_id ? json_crc_ : PROTOCOL_VERSION;\n        uint16_t actual_trailer = buffer[length - 2] | (buffer[length - 1] << 8);\n        if (expected_trailer != actual_trailer) {\n            LOG_FIBRE(\"trailer mismatch for endpoint %d: expected %04x, got %04x\\r\\n\", endpoint_id, expected_trailer, actual_trailer);\n            return -1;\n        }\n        LOG_FIBRE(\"trailer ok for endpoint %d\\r\\n\", endpoint_id);\n\n        // TODO: if more bytes than the MTU were requested, should we abort or just return as much as possible?\n\n        uint16_t expected_response_length = read_le<uint16_t>(&buffer, &length);\n\n        // Limit response length according to our local TX buffer size\n        if (expected_response_length > sizeof(tx_buf_) - 2)\n            expected_response_length = sizeof(tx_buf_) - 2;\n\n        MemoryStreamSink output(tx_buf_ + 2, expected_response_length);\n        endpoint->handle(buffer, length - 2, &output);\n\n        // Send response\n        if (expect_response) {\n            size_t actual_response_length = expected_response_length - output.get_free_space() + 2;\n            write_le<uint16_t>(seq_no | 0x8000, tx_buf_);\n\n            LOG_FIBRE(\"send packet:\\r\\n\");\n            hexdump(tx_buf_, actual_response_length);\n            output_.process_packet(tx_buf_, actual_response_length);\n        }\n    }\n\n    return 0;\n}\n\nbool is_endpoint_ref_valid(endpoint_ref_t endpoint_ref) {\n    return (endpoint_ref.json_crc == json_crc_)\n        && (endpoint_ref.endpoint_id < n_endpoints_);\n}\n\nEndpoint* get_endpoint(endpoint_ref_t endpoint_ref) {\n    if (is_endpoint_ref_valid(endpoint_ref))\n        return endpoint_list_[endpoint_ref.endpoint_id];\n    else\n        return nullptr;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/Print.cpp",
    "content": "/*\n Print.cpp - Base class that provides print() and println()\n Copyright (c) 2008 David A. Mellis.  All right reserved.\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n Modified 23 November 2006 by David A. Mellis\n Modified December 2014 by Ivan Grokhotkov\n Modified May 2015 by Michael C. Miller - ESP31B progmem support\n */\n\n#include <stdlib.h>\n#include <stdio.h>\n#include <string.h>\n#include <math.h>\n#include <cstdarg>\n\n#include \"Print.h\"\nextern \"C\" {\n    #include \"time.h\"\n}\n\n// Public Methods //////////////////////////////////////////////////////////////\n\n/* default implementation: may be overridden */\nsize_t Print::write(const uint8_t *buffer, size_t size)\n{\n    size_t n = 0;\n    while(size--) {\n        n += write(*buffer++);\n    }\n    return n;\n}\n\nsize_t Print::printf(const char *format, ...)\n{\n    char loc_buf[64];\n    char * temp = loc_buf;\n    va_list arg;\n    va_list copy;\n    va_start(arg, format);\n    va_copy(copy, arg);\n    int len = vsnprintf(temp, sizeof(loc_buf), format, copy);\n    va_end(copy);\n    if(len < 0) {\n        va_end(arg);\n        return 0;\n    };\n    if(len >= sizeof(loc_buf)){\n        temp = (char*) malloc(len+1);\n        if(temp == NULL) {\n            va_end(arg);\n            return 0;\n        }\n        len = vsnprintf(temp, len+1, format, arg);\n    }\n    va_end(arg);\n    len = write((uint8_t*)temp, len);\n    if(temp != loc_buf){\n        free(temp);\n    }\n    return len;\n}\n\nsize_t Print::print(const __FlashStringHelper *ifsh)\n{\n    return print(reinterpret_cast<const char *>(ifsh));\n}\n\nsize_t Print::print(const String &s)\n{\n    return write(s.c_str(), s.length());\n}\n\nsize_t Print::print(const char str[])\n{\n    return write(str);\n}\n\nsize_t Print::print(char c)\n{\n    return write(c);\n}\n\nsize_t Print::print(unsigned char b, int base)\n{\n    return print((unsigned long) b, base);\n}\n\nsize_t Print::print(int n, int base)\n{\n    return print((long) n, base);\n}\n\nsize_t Print::print(unsigned int n, int base)\n{\n    return print((unsigned long) n, base);\n}\n\nsize_t Print::print(long n, int base)\n{\n    int t = 0;\n    if (base == 10 && n < 0) {\n        t = print('-');\n        n = -n;\n    }\n    return printNumber(static_cast<unsigned long>(n), base) + t;\n}\n\nsize_t Print::print(unsigned long n, int base)\n{\n    if(base == 0) {\n        return write(n);\n    } else {\n        return printNumber(n, base);\n    }\n}\n\nsize_t Print::print(long long n, int base)\n{\n    int t = 0;\n    if (base == 10 && n < 0) {\n        t = print('-');\n        n = -n;\n    }\n    return printNumber(static_cast<unsigned long long>(n), base) + t;\n}\n\nsize_t Print::print(unsigned long long n, int base)\n{\n    if (base == 0) {\n        return write(n);\n    } else {\n        return printNumber(n, base);\n    }\n}\n\nsize_t Print::print(double n, int digits)\n{\n    return printFloat(n, digits);\n}\n\nsize_t Print::println(const __FlashStringHelper *ifsh)\n{\n    size_t n = print(ifsh);\n    n += println();\n    return n;\n}\n\nsize_t Print::print(const Printable& x)\n{\n    return x.printTo(*this);\n}\n\n\nsize_t Print::println(void)\n{\n    return print(\"\\r\\n\");\n}\n\nsize_t Print::println(const String &s)\n{\n    size_t n = print(s);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(const char c[])\n{\n    size_t n = print(c);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(char c)\n{\n    size_t n = print(c);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(unsigned char b, int base)\n{\n    size_t n = print(b, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(int num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(unsigned int num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(long num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(unsigned long num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(long long num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(unsigned long long num, int base)\n{\n    size_t n = print(num, base);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(double num, int digits)\n{\n    size_t n = print(num, digits);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(const Printable& x)\n{\n    size_t n = print(x);\n    n += println();\n    return n;\n}\n\nsize_t Print::println(struct tm * timeinfo, const char * format)\n{\n    size_t n = print(timeinfo, format);\n    n += println();\n    return n;\n}\n\n// Private Methods /////////////////////////////////////////////////////////////\n\nsize_t Print::printNumber(unsigned long n, uint8_t base)\n{\n    char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte.\n    char *str = &buf[sizeof(buf) - 1];\n\n    *str = '\\0';\n\n    // prevent crash if called with base == 1\n    if(base < 2) {\n        base = 10;\n    }\n\n    do {\n        char c = n % base;\n        n /= base;\n\n        *--str = c < 10 ? c + '0' : c + 'A' - 10;\n    } while (n);\n\n    return write(str);\n}\n\nsize_t Print::printNumber(unsigned long long n, uint8_t base)\n{\n    char buf[8 * sizeof(n) + 1]; // Assumes 8-bit chars plus zero byte.\n    char* str = &buf[sizeof(buf) - 1];\n\n    *str = '\\0';\n\n    // prevent crash if called with base == 1\n    if (base < 2) {\n        base = 10;\n    }\n\n    do {\n        auto m = n;\n        n /= base;\n        char c = m - base * n;\n\n        *--str = c < 10 ? c + '0' : c + 'A' - 10;\n    } while (n);\n\n    return write(str);\n}\n\nsize_t Print::printFloat(double number, uint8_t digits)\n{\n    size_t n = 0;\n\n    if(isnan(number)) {\n        return print(\"nan\");\n    }\n    if(isinf(number)) {\n        return print(\"inf\");\n    }\n    if(number > 4294967040.0) {\n        return print(\"ovf\");    // constant determined empirically\n    }\n    if(number < -4294967040.0) {\n        return print(\"ovf\");    // constant determined empirically\n    }\n\n    // Handle negative numbers\n    if(number < 0.0) {\n        n += print('-');\n        number = -number;\n    }\n\n    // Round correctly so that print(1.999, 2) prints as \"2.00\"\n    double rounding = 0.5;\n    for(uint8_t i = 0; i < digits; ++i) {\n        rounding /= 10.0;\n    }\n\n    number += rounding;\n\n    // Extract the integer part of the number and print it\n    unsigned long int_part = (unsigned long) number;\n    double remainder = number - (double) int_part;\n    n += print(int_part);\n\n    // Print the decimal point, but only if there are digits beyond\n    if(digits > 0) {\n        n += print(\".\");\n    }\n\n    // Extract digits from the remainder one at a time\n    while(digits-- > 0) {\n        remainder *= 10.0;\n        int toPrint = int(remainder);\n        n += print(toPrint);\n        remainder -= toPrint;\n    }\n\n    return n;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/Print.h",
    "content": "/*\n Print.h - Base class that provides print() and println()\n Copyright (c) 2008 David A. Mellis.  All right reserved.\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n\n#ifndef Print_h\n#define Print_h\n\n#include <stdint.h>\n#include <stddef.h>\n\n#include \"WString.h\"\n#include \"Printable.h\"\n\n#define DEC 10\n#define HEX 16\n#define OCT 8\n#define BIN 2\n\nclass Print\n{\nprivate:\n    int write_error;\n    size_t printNumber(unsigned long, uint8_t);\n    size_t printNumber(unsigned long long, uint8_t);\n    size_t printFloat(double, uint8_t);\nprotected:\n    void setWriteError(int err = 1)\n    {\n        write_error = err;\n    }\npublic:\n    Print() :\n        write_error(0)\n    {\n    }\n    virtual ~Print() {}\n    int getWriteError()\n    {\n        return write_error;\n    }\n    void clearWriteError()\n    {\n        setWriteError(0);\n    }\n\n    virtual size_t write(uint8_t) = 0;\n    size_t write(const char *str)\n    {\n        if(str == NULL) {\n            return 0;\n        }\n        return write((const uint8_t *) str, strlen(str));\n    }\n    virtual size_t write(const uint8_t *buffer, size_t size);\n    size_t write(const char *buffer, size_t size)\n    {\n        return write((const uint8_t *) buffer, size);\n    }\n\n    size_t printf(const char * format, ...)  __attribute__ ((format (printf, 2, 3)));\n\n    // add availableForWrite to make compatible with Arduino Print.h\n    // default to zero, meaning \"a single write may block\"\n    // should be overriden by subclasses with buffering\n    virtual int availableForWrite() { return 0; }\n    size_t print(const __FlashStringHelper *);\n    size_t print(const String &);\n    size_t print(const char[]);\n    size_t print(char);\n    size_t print(unsigned char, int = DEC);\n    size_t print(int, int = DEC);\n    size_t print(unsigned int, int = DEC);\n    size_t print(long, int = DEC);\n    size_t print(unsigned long, int = DEC);\n    size_t print(long long, int = DEC);\n    size_t print(unsigned long long, int = DEC);\n    size_t print(double, int = 2);\n    size_t print(const Printable&);\n    size_t print(struct tm * timeinfo, const char * format = NULL);\n\n    size_t println(const __FlashStringHelper *);\n    size_t println(const String &s);\n    size_t println(const char[]);\n    size_t println(char);\n    size_t println(unsigned char, int = DEC);\n    size_t println(int, int = DEC);\n    size_t println(unsigned int, int = DEC);\n    size_t println(long, int = DEC);\n    size_t println(unsigned long, int = DEC);\n    size_t println(long long, int = DEC);\n    size_t println(unsigned long long, int = DEC);\n    size_t println(double, int = 2);\n    size_t println(const Printable&);\n    size_t println(struct tm * timeinfo, const char * format = NULL);\n    size_t println(void);\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/Printable.h",
    "content": "/*\n Printable.h - Interface class that allows printing of complex types\n Copyright (c) 2011 Adrian McEwen.  All right reserved.\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n\n#ifndef Printable_h\n#define Printable_h\n\n#include <stdlib.h>\n\nclass Print;\n\n/** The Printable class provides a way for new classes to allow themselves to be printed.\n By deriving from Printable and implementing the printTo method, it will then be possible\n for users to print out instances of this class by passing them into the usual\n Print::print and Print::println methods.\n */\n\nclass Printable\n{\npublic:\n    virtual ~Printable() {}\n    virtual size_t printTo(Print& p) const = 0;\n};\n\n#endif\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/U8g2lib.hpp",
    "content": "#ifndef U8G2LIB_HH\n#define U8G2LIB_HH\n\n#include <Print.h>\n#include \"U8x8lib.h\"\n#include \"u8g2.h\"\n#include \"soft_i2c.h\"\n\nextern I2C_HandleTypeDef *U8G2_I2C_HANDLE;\nextern SPI_HandleTypeDef *U8G2_SPI_HANDLE;\n\nclass U8G2 : public Print\n{\nprotected:\n    u8g2_t u8g2;\n    u8x8_char_cb cpp_next_cb; /*  the cpp interface has its own decoding function for the Arduino print command */\npublic:\n    u8g2_uint_t tx, ty;\n\n    U8G2(void)\n    {\n        cpp_next_cb = u8x8_ascii_next;\n        home();\n    }\n\n    u8x8_t *getU8x8(void)\n    { return u8g2_GetU8x8(&u8g2); }\n\n    u8g2_t *getU8g2(void)\n    { return &u8g2; }\n\n    void sendF(const char *fmt, ...)\n    {\n        va_list va;\n        va_start(va, fmt);\n        u8x8_cad_vsendf(u8g2_GetU8x8(&u8g2), fmt, va);\n        va_end(va);\n    }\n\n\n    uint32_t getBusClock(void)\n    { return u8g2_GetU8x8(&u8g2)->bus_clock; }\n\n    void setBusClock(uint32_t clock_speed)\n    { u8g2_GetU8x8(&u8g2)->bus_clock = clock_speed; }\n\n    void setI2CAddress(uint8_t adr)\n    { u8g2_SetI2CAddress(&u8g2, adr); }\n\n\n    void enableUTF8Print(void)\n    { cpp_next_cb = u8x8_utf8_next; }\n\n    void disableUTF8Print(void)\n    { cpp_next_cb = u8x8_ascii_next; }\n\n    /* u8x8 interface */\n    uint8_t getCols(void)\n    { return u8x8_GetCols(u8g2_GetU8x8(&u8g2)); }\n\n    uint8_t getRows(void)\n    { return u8x8_GetRows(u8g2_GetU8x8(&u8g2)); }\n\n    void drawTile(uint8_t x, uint8_t y, uint8_t cnt, uint8_t *tile_ptr)\n    {\n        u8x8_DrawTile(u8g2_GetU8x8(&u8g2), x, y, cnt, tile_ptr);\n    }\n\n    /* return 0 for no event or U8X8_MSG_GPIO_MENU_SELECT, */\n    /* U8X8_MSG_GPIO_MENU_NEXT, U8X8_MSG_GPIO_MENU_PREV, */\n    /* U8X8_MSG_GPIO_MENU_HOME */\n    uint8_t getMenuEvent(void)\n    { return u8x8_GetMenuEvent(u8g2_GetU8x8(&u8g2)); }\n\n    void initDisplay(void)\n    {\n        u8g2_InitDisplay(&u8g2);\n    }\n\n    void clearDisplay(void)\n    {\n        u8g2_ClearDisplay(&u8g2);\n    }\n\n    void setPowerSave(uint8_t is_enable)\n    {\n        u8g2_SetPowerSave(&u8g2, is_enable);\n    }\n\n    void setFlipMode(uint8_t mode)\n    {\n        u8g2_SetFlipMode(&u8g2, mode);\n    }\n\n    void setContrast(uint8_t value)\n    {\n        u8g2_SetContrast(&u8g2, value);\n    }\n\n    void setDisplayRotation(const u8g2_cb_t *u8g2_cb)\n    {\n        u8g2_SetDisplayRotation(&u8g2, u8g2_cb);\n    }\n\n\n    bool Init()\n    {\n        if (U8G2_I2C_HANDLE->Instance == I2C_SOFT)\n            Soft_I2C_Init();\n\n        /* note: call to u8x8_utf8_init is not required here, this is done in the setup procedures before */\n        setPowerSave(1);\n        initDisplay();\n        clearDisplay();\n        clearBuffer();\n        setPowerSave(0);\n\n        return 1;\n    }\n\n    void beginSimple()\n    {\n        /* does not clear the display and does not wake up the display */\n        /* user is responsible for calling clearDisplay() and setPowerSave(0) */\n        initDisplay();\n    }\n\n    /* u8g2  */\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n\n    void setMaxClipWindow()\n    { u8g2_SetMaxClipWindow(&u8g2); }\n\n    void setClipWindow(u8g2_uint_t clip_x0, u8g2_uint_t clip_y0, u8g2_uint_t clip_x1, u8g2_uint_t clip_y1)\n    {\n        u8g2_SetClipWindow(&u8g2, clip_x0, clip_y0, clip_x1, clip_y1);\n    }\n\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n\n\n    u8g2_uint_t getDisplayHeight(void)\n    { return u8g2_GetDisplayHeight(&u8g2); }\n\n    u8g2_uint_t getDisplayWidth(void)\n    { return u8g2_GetDisplayWidth(&u8g2); }\n\n\n    /* u8g2_buffer.c */\n    void sendBuffer(void)\n    { u8g2_SendBuffer(&u8g2); }\n\n    void clearBuffer(void)\n    { u8g2_ClearBuffer(&u8g2); }\n\n    void firstPage(void)\n    { u8g2_FirstPage(&u8g2); }\n\n    uint8_t nextPage(void)\n    { return u8g2_NextPage(&u8g2); }\n\n    uint8_t *getBufferPtr(void)\n    { return u8g2_GetBufferPtr(&u8g2); }\n\n    uint8_t getBufferTileHeight(void)\n    { return u8g2_GetBufferTileHeight(&u8g2); }\n\n    uint8_t getBufferTileWidth(void)\n    { return u8g2_GetBufferTileWidth(&u8g2); }\n\n    uint8_t getPageCurrTileRow(void)\n    { return u8g2_GetBufferCurrTileRow(&u8g2); }    // obsolete\n    void setPageCurrTileRow(uint8_t row)\n    { u8g2_SetBufferCurrTileRow(&u8g2, row); }    // obsolete\n    uint8_t getBufferCurrTileRow(void)\n    { return u8g2_GetBufferCurrTileRow(&u8g2); }\n\n    void setBufferCurrTileRow(uint8_t row)\n    { u8g2_SetBufferCurrTileRow(&u8g2, row); }\n\n    // this should be renamed to setBufferAutoClear\n    void setAutoPageClear(uint8_t mode)\n    { u8g2_SetAutoPageClear(&u8g2, mode); }\n\n    void updateDisplayArea(uint8_t tx, uint8_t ty, uint8_t tw, uint8_t th)\n    { u8g2_UpdateDisplayArea(&u8g2, tx, ty, tw, th); }\n\n    void updateDisplay(void)\n    { u8g2_UpdateDisplay(&u8g2); }\n\n    void refreshDisplay(void)\n    { u8x8_RefreshDisplay(u8g2_GetU8x8(&u8g2)); }\n\n\n    /* clib/u8g2.hvline.c */\n    void setDrawColor(uint8_t color_index)\n    { u8g2_SetDrawColor(&u8g2, color_index); }\n\n    uint8_t getDrawColor(void)\n    { return u8g2_GetDrawColor(&u8g2); }\n\n    void drawPixel(u8g2_uint_t x, u8g2_uint_t y)\n    { u8g2_DrawPixel(&u8g2, x, y); }\n\n    void drawHLine(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w)\n    { u8g2_DrawHLine(&u8g2, x, y, w); }\n\n    void drawVLine(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t h)\n    { u8g2_DrawVLine(&u8g2, x, y, h); }\n\n    void drawHVLine(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n    {\n        u8g2_DrawHVLine(&u8g2, x, y, len, dir);\n    }\n\n    /* u8g2_box.c */\n    void drawFrame(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h)\n    { u8g2_DrawFrame(&u8g2, x, y, w, h); }\n\n    void drawRFrame(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r)\n    { u8g2_DrawRFrame(&u8g2, x, y, w, h, r); }\n\n    void drawBox(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h)\n    { u8g2_DrawBox(&u8g2, x, y, w, h); }\n\n    void drawRBox(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r)\n    { u8g2_DrawRBox(&u8g2, x, y, w, h, r); }\n\n    /* u8g2_circle.c */\n    void drawCircle(u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t opt = U8G2_DRAW_ALL)\n    { u8g2_DrawCircle(&u8g2, x0, y0, rad, opt); }\n\n    void drawDisc(u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t opt = U8G2_DRAW_ALL)\n    { u8g2_DrawDisc(&u8g2, x0, y0, rad, opt); }\n\n    void drawEllipse(u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t opt = U8G2_DRAW_ALL)\n    { u8g2_DrawEllipse(&u8g2, x0, y0, rx, ry, opt); }\n\n    void drawFilledEllipse(u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t opt = U8G2_DRAW_ALL)\n    { u8g2_DrawFilledEllipse(&u8g2, x0, y0, rx, ry, opt); }\n\n    /* u8g2_line.c */\n    void drawLine(u8g2_uint_t x1, u8g2_uint_t y1, u8g2_uint_t x2, u8g2_uint_t y2)\n    { u8g2_DrawLine(&u8g2, x1, y1, x2, y2); }\n\n    /* u8g2_bitmap.c */\n    void setBitmapMode(uint8_t is_transparent)\n    { u8g2_SetBitmapMode(&u8g2, is_transparent); }\n\n    void drawBitmap(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t cnt, u8g2_uint_t h, const uint8_t *bitmap)\n    { u8g2_DrawBitmap(&u8g2, x, y, cnt, h, bitmap); }\n\n    void drawXBM(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap)\n    { u8g2_DrawXBM(&u8g2, x, y, w, h, bitmap); }\n\n    void drawXBMP(u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap)\n    { u8g2_DrawXBMP(&u8g2, x, y, w, h, bitmap); }\n\n\n    /* u8g2_polygon.c */\n    void drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2)\n    { u8g2_DrawTriangle(&u8g2, x0, y0, x1, y1, x2, y2); }\n\n    /* u8log_u8g2.c */\n    void drawLog(u8g2_uint_t x, u8g2_uint_t y, class U8G2LOG &u8g2log);\n\n    /* u8g2_font.c */\n\n    void setFont(const uint8_t *font)\n    { u8g2_SetFont(&u8g2, font); }\n\n    void setFontMode(uint8_t is_transparent)\n    { u8g2_SetFontMode(&u8g2, is_transparent); }\n\n    void setFontDirection(uint8_t dir)\n    { u8g2_SetFontDirection(&u8g2, dir); }\n\n    int8_t getAscent(void)\n    { return u8g2_GetAscent(&u8g2); }\n\n    int8_t getDescent(void)\n    { return u8g2_GetDescent(&u8g2); }\n\n    void setFontPosBaseline(void)\n    { u8g2_SetFontPosBaseline(&u8g2); }\n\n    void setFontPosBottom(void)\n    { u8g2_SetFontPosBottom(&u8g2); }\n\n    void setFontPosTop(void)\n    { u8g2_SetFontPosTop(&u8g2); }\n\n    void setFontPosCenter(void)\n    { u8g2_SetFontPosCenter(&u8g2); }\n\n    void setFontRefHeightText(void)\n    { u8g2_SetFontRefHeightText(&u8g2); }\n\n    void setFontRefHeightExtendedText(void)\n    { u8g2_SetFontRefHeightExtendedText(&u8g2); }\n\n    void setFontRefHeightAll(void)\n    { u8g2_SetFontRefHeightAll(&u8g2); }\n\n\n/*\nuint8_t u8g2_IsGlyph(u8g2_t *u8g2, uint16_t requested_encoding);\nint8_t u8g2_GetGlyphWidth(u8g2_t *u8g2, uint16_t requested_encoding);\nu8g2_uint_t u8g2_GetStrWidth(u8g2_t *u8g2, const char *s);\nu8g2_uint_t u8g2_GetUTF8Width(u8g2_t *u8g2, const char *str);\n*/\n\n    u8g2_uint_t drawGlyph(u8g2_uint_t x, u8g2_uint_t y, uint16_t encoding)\n    { return u8g2_DrawGlyph(&u8g2, x, y, encoding); }\n\n    u8g2_uint_t drawStr(u8g2_uint_t x, u8g2_uint_t y, const char *s)\n    { return u8g2_DrawStr(&u8g2, x, y, s); }\n\n    u8g2_uint_t drawUTF8(u8g2_uint_t x, u8g2_uint_t y, const char *s)\n    { return u8g2_DrawUTF8(&u8g2, x, y, s); }\n\n    u8g2_uint_t drawExtUTF8(u8g2_uint_t x, u8g2_uint_t y, uint8_t to_left, const uint16_t *kerning_table, const char *s)\n    { return u8g2_DrawExtUTF8(&u8g2, x, y, to_left, kerning_table, s); }\n\n\n    u8g2_uint_t getStrWidth(const char *s)\n    { return u8g2_GetStrWidth(&u8g2, s); }\n\n    u8g2_uint_t getUTF8Width(const char *s)\n    { return u8g2_GetUTF8Width(&u8g2, s); }\n\n    // not required any more, enable UTF8 for print \n    //void printUTF8(const char *s) { tx += u8g2_DrawUTF8(&u8g2, tx, ty, s); }\n\n    /* screenshot functions for full buffer mode */\n    /* vertical top lsb memory architecture */\n    void writeBufferPBM(Print &p);\n\n    void writeBufferXBM(Print &p);\n    /* horizontal right lsb memory architecture */\n    /* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */\n    void writeBufferPBM2(Print &p);\n\n    void writeBufferXBM2(Print &p);\n\n    /* virtual function for print base class */\n    size_t write(uint8_t v)\n    {\n        uint16_t e = cpp_next_cb(&(u8g2.u8x8), v);\n\n        if (e < 0x0fffe)\n        {\n            u8g2_uint_t delta = u8g2_DrawGlyph(&u8g2, tx, ty, e);\n\n#ifdef U8G2_WITH_FONT_ROTATION\n            switch (u8g2.font_decode.dir)\n            {\n                case 0:\n                    tx += delta;\n                    break;\n                case 1:\n                    ty += delta;\n                    break;\n                case 2:\n                    tx -= delta;\n                    break;\n                case 3:\n                    ty -= delta;\n                    break;\n            }\n\n            // requires 10 bytes more on avr\n            //tx = u8g2_add_vector_x(tx, delta, 0, u8g2.font_decode.dir);\n            //ty = u8g2_add_vector_y(ty, delta, 0, u8g2.font_decode.dir);\n\n#else\n            tx += delta;\n#endif\n\n        }\n        return 1;\n    }\n\n    size_t write(const uint8_t *buffer, size_t size)\n    {\n        size_t cnt = 0;\n        while (size > 0)\n        {\n            cnt += write(*buffer++);\n            size--;\n        }\n        return cnt;\n    }\n\n\n    /* user interface */\n/*\nuint8_t u8g2_UserInterfaceSelectionList(u8g2_t *u8g2, const char *title, uint8_t start_pos, const char *sl);\nuint8_t u8g2_UserInterfaceMessage(u8g2_t *u8g2, const char *title1, const char *title2, const char *title3, const char *buttons);\nuint8_t u8g2_UserInterfaceInputValue(u8g2_t *u8g2, const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits, const char *post);\n*/\n\n    uint8_t userInterfaceSelectionList(const char *title, uint8_t start_pos, const char *sl)\n    {\n        return u8g2_UserInterfaceSelectionList(&u8g2, title, start_pos, sl);\n    }\n\n    uint8_t userInterfaceMessage(const char *title1, const char *title2, const char *title3, const char *buttons)\n    {\n        return u8g2_UserInterfaceMessage(&u8g2, title1, title2, title3, buttons);\n    }\n\n    uint8_t\n    userInterfaceInputValue(const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits,\n                            const char *post)\n    {\n        return u8g2_UserInterfaceInputValue(&u8g2, title, pre, value, lo, hi, digits, post);\n    }\n\n\n    /* LiquidCrystal compatible functions */\n    void home(void)\n    {\n        tx = 0;\n        ty = 0;\n        u8x8_utf8_init(u8g2_GetU8x8(&u8g2));\n    }\n\n    void clear(void)\n    {\n        home();\n        clearDisplay();\n        clearBuffer();\n    }\n\n    void noDisplay(void)\n    { u8g2_SetPowerSave(&u8g2, 1); }\n\n    void display(void)\n    { u8g2_SetPowerSave(&u8g2, 0); }\n\n    void setCursor(u8g2_uint_t x, u8g2_uint_t y)\n    {\n        tx = x;\n        ty = y;\n    }\n\n    /* u8glib compatible functions */\n    void sleepOn(void)\n    { u8g2_SetPowerSave(&u8g2, 1); }\n\n    void sleepOff(void)\n    { u8g2_SetPowerSave(&u8g2, 0); }\n\n    void setColorIndex(uint8_t color_index)\n    { u8g2_SetDrawColor(&u8g2, color_index); }\n\n    uint8_t getColorIndex(void)\n    { return u8g2_GetDrawColor(&u8g2); }\n\n    int8_t getFontAscent(void)\n    { return u8g2_GetAscent(&u8g2); }\n\n    int8_t getFontDescent(void)\n    { return u8g2_GetDescent(&u8g2); }\n\n    int8_t getMaxCharHeight(void)\n    { return u8g2_GetMaxCharHeight(&u8g2); }\n\n    int8_t getMaxCharWidth(void)\n    { return u8g2_GetMaxCharWidth(&u8g2); }\n\n    u8g2_uint_t getHeight()\n    { return u8g2_GetDisplayHeight(&u8g2); }\n\n    u8g2_uint_t getWidth()\n    { return u8g2_GetDisplayWidth(&u8g2); }\n};\n\nvoid u8g2_print_callback(const char *s);  /* U8g2lib.cpp */\n\n\nclass U8G2LOG : public Print\n{\n\npublic:\n    u8log_t u8log;\n\n    /* the constructor does nothing, use begin() instead */\n    U8G2LOG(void)\n    {}\n\n    /* connect to u8g2, draw to u8g2 whenever required */\n    bool begin(class U8G2 &u8g2, uint8_t width, uint8_t height, uint8_t *buf)\n    {\n        u8log_Init(&u8log, width, height, buf);\n        u8log_SetCallback(&u8log, u8log_u8g2_cb, u8g2.getU8g2());\n        return true;\n    }\n\n    /* disconnected version, manual redraw required */\n    bool begin(uint8_t width, uint8_t height, uint8_t *buf)\n    {\n        u8log_Init(&u8log, width, height, buf);\n        return true;\n    }\n\n    void setLineHeightOffset(int8_t line_height_offset)\n    {\n        u8log_SetLineHeightOffset(&u8log, line_height_offset);\n    }\n\n    void setRedrawMode(uint8_t is_redraw_line_for_each_char)\n    {\n        u8log_SetRedrawMode(&u8log, is_redraw_line_for_each_char);\n    }\n\n    /* virtual function for print base class */\n    size_t write(uint8_t v)\n    {\n        u8log_WriteChar(&u8log, v);\n        return 1;\n    }\n\n    size_t write(const uint8_t *buffer, size_t size)\n    {\n        size_t cnt = 0;\n        while (size > 0)\n        {\n            cnt += write(*buffer++);\n            size--;\n        }\n        return cnt;\n    }\n\n    void writeString(const char *s)\n    { u8log_WriteString(&u8log, s); }\n\n    void writeChar(uint8_t c)\n    { u8log_WriteChar(&u8log, c); }\n\n    void writeHex8(uint8_t b)\n    { u8log_WriteHex8(&u8log, b); }\n\n    void writeHex16(uint16_t v)\n    { u8log_WriteHex16(&u8log, v); }\n\n    void writeHex32(uint32_t v)\n    { u8log_WriteHex32(&u8log, v); }\n\n    void writeDec8(uint8_t v, uint8_t d)\n    { u8log_WriteDec8(&u8log, v, d); }\n\n    void writeDec16(uint8_t v, uint8_t d)\n    { u8log_WriteDec16(&u8log, v, d); }\n};\n\n/* u8log_u8g2.c */\ninline void U8G2::drawLog(u8g2_uint_t x, u8g2_uint_t y, class U8G2LOG &u8g2log)\n{\n    u8g2_DrawLog(&u8g2, x, y, &(u8g2log.u8log));\n}\n\n\nclass U8G2_BITMAP : public U8G2\n{\npublic:\n    U8G2_BITMAP(uint16_t pixel_width, uint16_t pixel_height, const u8g2_cb_t *rotation)\n    {\n        u8g2_SetupBitmap(getU8g2(), rotation, pixel_width, pixel_height);\n    }\n\n    // This completely resets various settings, such as the\n    // font, so be sure to re-initialize things\n    void changeSize(uint16_t pixel_width, uint16_t pixel_height)\n    {\n        u8g2_SetupBitmap(getU8g2(), getU8g2()->cb, pixel_width, pixel_height);\n    }\n};\n\nclass SSD1306 : public U8G2\n{\nprivate:\n\npublic:\n    explicit SSD1306(I2C_HandleTypeDef *_hi2c, const u8g2_cb_t *rotation = U8G2_R3) : U8G2()\n    {\n        U8G2_I2C_HANDLE = _hi2c;\n        u8g2_Setup_ssd1306_i2c_128x80_noname_f(&u8g2, rotation, u8x8_byte_stm32_hw_i2c, u8x8_stm32_gpio_and_delay);\n    }\n};\n\n#endif /* _U8G2LIB_HH */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/U8x8lib.cpp",
    "content": "#include \"U8x8lib.h\"\n\n\n/*=============================================*/\n\nsize_t U8X8::write(uint8_t v) \n{\n  if ( v == '\\n' )\n  {\n    uint8_t dy = u8x8_pgm_read(u8x8.font+3);\t\t/* new 2019 format */\n    ty+=dy;\n    tx=0;\n  }\n  else\n  {\n    uint8_t dx = u8x8_pgm_read(u8x8.font+2);\t\t/* new 2019 format */\n    u8x8_DrawGlyph(&u8x8, tx, ty, v);\n\n    tx+=dx;\n  }\n  return 1;\n}\n\n\n\n/*=============================================*/\n/*=== ARDUINO GPIO & DELAY ===*/\n\n#ifdef U8X8_USE_PINS\nextern \"C\" uint8_t u8x8_gpio_and_delay_arduino(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n  uint8_t i;\n  switch(msg)\n  {\n    case U8X8_MSG_GPIO_AND_DELAY_INIT:\n    \n      for( i = 0; i < U8X8_PIN_CNT; i++ )\n\tif ( u8x8->pins[i] != U8X8_PIN_NONE )\n\t{\n\t  if ( i < U8X8_PIN_OUTPUT_CNT )\n\t  {\n\t    pinMode(u8x8->pins[i], OUTPUT);\n\t  }\n\t  else\n\t  {\n#ifdef INPUT_PULLUP\n\t    pinMode(u8x8->pins[i], INPUT_PULLUP);\n#else\n\t    pinMode(u8x8->pins[i], OUTPUT);\n\t    digitalWrite(u8x8->pins[i], 1);\n#endif \n\t  }\n\t}\n\t  \n      break;\n\n#ifndef __AVR__\t\n    /* this case is not compiled for any AVR, because AVR uC are so slow */\n    /* that this delay does not matter */\n    case U8X8_MSG_DELAY_NANO:\n      delayMicroseconds(arg_int==0?0:1);\n      break;\n#endif\n    \n    case U8X8_MSG_DELAY_10MICRO:\n      /* not used at the moment */\n      break;\n    \n    case U8X8_MSG_DELAY_100NANO:\n      /* not used at the moment */\n      break;\n   \n    case U8X8_MSG_DELAY_MILLI:\n      delay(arg_int);\n      break;\n    case U8X8_MSG_DELAY_I2C:\n      /* arg_int is 1 or 4: 100KHz (5us) or 400KHz (1.25us) */\n      delayMicroseconds(arg_int<=2?5:2);\n      break;\n    case U8X8_MSG_GPIO_I2C_CLOCK:\n    case U8X8_MSG_GPIO_I2C_DATA:\n      if ( arg_int == 0 )\n      {\n\tpinMode(u8x8_GetPinValue(u8x8, msg), OUTPUT);\n\tdigitalWrite(u8x8_GetPinValue(u8x8, msg), 0);\n      }\n      else\n      {\n#ifdef INPUT_PULLUP\n\tpinMode(u8x8_GetPinValue(u8x8, msg), INPUT_PULLUP);\n#else\n\tpinMode(u8x8_GetPinValue(u8x8, msg), OUTPUT);\n\tdigitalWrite(u8x8_GetPinValue(u8x8, msg), 1);\n#endif \n      }\n      break;\n    default:\n      if ( msg >= U8X8_MSG_GPIO(0) )\n      {\n\ti = u8x8_GetPinValue(u8x8, msg);\n\tif ( i != U8X8_PIN_NONE )\n\t{\n\t  if ( u8x8_GetPinIndex(u8x8, msg) < U8X8_PIN_OUTPUT_CNT )\n\t  {\n\t    digitalWrite(i, arg_int);\n\t  }\n\t  else\n\t  {\n\t    if ( u8x8_GetPinIndex(u8x8, msg) == U8X8_PIN_OUTPUT_CNT )\n\t    {\n\t      // call yield() for the first pin only, u8x8 will always request all the pins, so this should be ok\n\t      yield();\n\t    }\n\t    u8x8_SetGPIOResult(u8x8, digitalRead(i) == 0 ? 0 : 1);\n\t  }\n\t}\n\tbreak;\n      }\n      \n      return 0;\n  }\n  return 1;\n}\n#endif // U8X8_USE_PINS\n\n\n\n\n/*=============================================*/\n/*=== 3 WIRE SOFTWARE SPI ===*/\n\n/*\n  replacement for a more faster u8x8_byte_3wire_sw_spi\n  in general u8x8_byte_3wire_sw_spi could be a fallback:\n\n  uint8_t u8x8_byte_arduino_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_3wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n\n\n\n*/\n\n#ifndef __AVR_ARCH__\n#define __AVR_ARCH__ 0\n#endif \n\n#if !defined(U8X8_USE_PINS)\n  /* no pin information (very strange), so fallback */\n  uint8_t u8x8_byte_arduino_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_3wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n\n#elif __AVR_ARCH__ == 4 || __AVR_ARCH__ == 5 || __AVR_ARCH__ == 51 || __AVR_ARCH__ == 6 || __AVR_ARCH__ == 103\n\n/* this function completly replaces u8x8_byte_4wire_sw_spi*/\nextern \"C\" uint8_t u8x8_byte_arduino_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i;\n  uint8_t takeover_edge = u8x8_GetSPIClockPhase(u8x8);\n  uint16_t b;\n  uint8_t *data;\n\n  /* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n  /* so, it should be possible to use multiple displays with different pins */\n  \n  static volatile uint8_t *arduino_clock_port;\n  \n  static uint8_t arduino_clock_mask;\n  static uint8_t arduino_clock_n_mask;\n  \n  static volatile uint8_t *arduino_data_port;\n  static uint8_t arduino_data_mask;\n  static uint8_t arduino_data_n_mask;\n\n  static uint8_t last_dc;\n\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n    \n      data = (uint8_t *)arg_ptr;      \n      if ( takeover_edge == 0 )\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  if ( last_dc != 0 )\n\t    b |= 256;\n\t  data++;\n\t  arg_int--;\n\t  /* issue 156, check for speed */\n#if F_CPU <= 17000000\n\t  if ( b == 0 )\n\t  {\n\t    *arduino_data_port &= arduino_data_n_mask;\n\t    for( i = 0; i < 9; i++ )\n\t    {\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t    }\n\t  }\n\t  else\n#endif\n\t  {\n\t    for( i = 0; i < 9; i++ )\n\t    {\n\t      if ( b & 256 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t      b <<= 1;\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t    }\n\t  }\n\t}\n      }\n      else\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  if ( last_dc != 0 )\n\t    b |= 256;\n\t  data++;\n\t  arg_int--;\n\t  /* issue 156, check for speed */\n#if F_CPU <= 17000000\n\t  if ( b == 0 )\n\t  {\n\t    *arduino_data_port &= arduino_data_n_mask;\n\t    for( i = 0; i < 9; i++ )\n\t    {\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t    }\n\t  }\n\t  else\n#endif\n\t  {\n\t    for( i = 0; i < 9; i++ )\n\t    {\n\t      if ( b & 256 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t      b <<= 1;\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t    }\n\t  }\n\t}\n      }      \n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      u8x8_gpio_SetSPIClock(u8x8, u8x8_GetSPIClockPhase(u8x8));\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      last_dc = arg_int;\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_SPI_CLOCK] */\n    \n      arduino_clock_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_CLOCK]));\n      arduino_clock_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_CLOCK]);\n      arduino_clock_n_mask = ~arduino_clock_mask;\n    \n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_SPI_DATA] */\n\n      arduino_data_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_DATA]));\n      arduino_data_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_DATA]);\n      arduino_data_n_mask = ~arduino_data_mask;\n      \n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n#else\n  /* fallback */\n  uint8_t u8x8_byte_arduino_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_3wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n  \n#endif\n\n\n\n\n\n/*=============================================*/\n/*=== 4 WIRE SOFTWARE SPI ===*/\n\n/*\n  replacement for a more faster u8x8_byte_4wire_sw_spi\n  in general u8x8_byte_4wire_sw_spi could be a fallback:\n\n  uint8_t u8x8_byte_arduino_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_4wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n\n\n\n*/\n\n#ifndef __AVR_ARCH__\n#define __AVR_ARCH__ 0\n#endif \n\n#if !defined(U8X8_USE_PINS)\n  /* no pin information (very strange), so fallback */\n  uint8_t u8x8_byte_arduino_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_4wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n\n#elif __AVR_ARCH__ == 4 || __AVR_ARCH__ == 5 || __AVR_ARCH__ == 51 || __AVR_ARCH__ == 6 || __AVR_ARCH__ == 103\n\n/* this function completly replaces u8x8_byte_4wire_sw_spi*/\nextern \"C\" uint8_t u8x8_byte_arduino_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t SREG_backup;\n  uint8_t i, b;\n  uint8_t *data;\n  uint8_t takeover_edge = u8x8_GetSPIClockPhase(u8x8);\n  //uint8_t not_takeover_edge = 1 - takeover_edge;\n\n  /* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n  /* so, it should be possible to use multiple displays with different pins */\n  \n  static volatile uint8_t *arduino_clock_port;\n  \n  static uint8_t arduino_clock_mask;\n  static uint8_t arduino_clock_n_mask;\n  \n  static volatile uint8_t *arduino_data_port;\n  static uint8_t arduino_data_mask;\n  static uint8_t arduino_data_n_mask;\n\n\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n    \n      data = (uint8_t *)arg_ptr;      \n      if ( takeover_edge == 0 )\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  data++;\n\t  arg_int--;\n\t  SREG_backup = SREG; cli();\n\t  /* issue 156, check for speed */\n#if F_CPU <= 17000000\n\t  if ( b == 0 )\n\t  {\n\t    *arduino_data_port &= arduino_data_n_mask;\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t    }\n\t  }\n\t  else\n#endif\n\t  {\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      if ( b & 128 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t      b <<= 1;\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t    }\n\t  }\n\t  SREG = SREG_backup;\n\t}\n      }\n      else\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  data++;\n\t  arg_int--;\n\t  SREG_backup = SREG; cli();\n\t  /* issue 156, check for speed */\n#if F_CPU <= 17000000\n\t  if ( b == 0 )\n\t  {\n\t    *arduino_data_port &= arduino_data_n_mask;\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t    }\n\t  }\n\t  else\n#endif\n\t  {\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      if ( b & 128 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\n\t      *arduino_clock_port &= arduino_clock_n_mask;\n\t      b <<= 1;\n\t      *arduino_clock_port |= arduino_clock_mask;\t    \n\t    }\n\t  }\n\t  SREG = SREG_backup;\n\t}\n      }      \n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      u8x8_gpio_SetSPIClock(u8x8, u8x8_GetSPIClockPhase(u8x8));\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_SPI_CLOCK] */\n    \n      arduino_clock_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_CLOCK]));\n      arduino_clock_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_CLOCK]);\n      arduino_clock_n_mask = ~arduino_clock_mask;\n    \n      \n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_SPI_DATA] */\n\n      arduino_data_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_DATA]));\n      arduino_data_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_DATA]);\n      arduino_data_n_mask = ~arduino_data_mask;\n      \n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n#elif defined(__SAM3X8E__) \t\t/* Arduino DUE */\n\n/* this function completly replaces u8x8_byte_4wire_sw_spi*/\nextern \"C\" uint8_t u8x8_byte_arduino_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint16_t us = ((u8x8->display_info->sck_pulse_width_ns + 999)/1000);\n  uint8_t *data;\n  uint8_t takeover_edge = u8x8_GetSPIClockPhase(u8x8);\n  //uint8_t not_takeover_edge = 1 - takeover_edge;\n\n  /* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n  /* so, it should be possible to use multiple displays with different pins */\n  \n  /*\n  static volatile uint32_t *arduino_clock_port;  \n  static uint32_t arduino_clock_mask;\n  static uint32_t arduino_clock_n_mask;\n  \n  static volatile uint32_t *arduino_data_port;\n  static uint32_t arduino_data_mask;\n  static uint32_t arduino_data_n_mask;\n  */\n\n  static WoReg *arduinoSetClockPort, *arduinoUnsetClockPort;\n  static uint32_t arduino_clock_mask;\n\n  static WoReg *arduinoSetDataPort, *arduinoUnsetDataPort;\n  static uint32_t arduino_data_mask;\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n    \n      data = (uint8_t *)arg_ptr;      \n      if ( takeover_edge == 0 )\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  data++;\n\t  arg_int--;\n\t  {\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      /*\n\t      if ( b & 128 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\t      */\n\t      if (b & 128)\n\t\t  *arduinoSetDataPort = arduino_data_mask;\n\t      else\n\t\t  *arduinoUnsetDataPort = arduino_data_mask;\n\n\t      //delayMicroseconds(us);\n\t      //*arduino_clock_port |= arduino_clock_mask;\n\t      *arduinoSetClockPort = arduino_clock_mask;\n\t      b <<= 1;\n\t      delayMicroseconds(us);\n\t      //*arduino_clock_port &= arduino_clock_n_mask;\n\t      *arduinoUnsetClockPort = arduino_clock_mask;\n\t    }\n\t  }\n\t}\n      }\n      else\n      {\n\twhile( arg_int > 0 )\n\t{\n\t  b = *data;\n\t  data++;\n\t  arg_int--;\n\t  {\n\t    for( i = 0; i < 8; i++ )\n\t    {\n\t      /*\n\t      if ( b & 128 )\n\t\t*arduino_data_port |= arduino_data_mask;\n\t      else\n\t\t*arduino_data_port &= arduino_data_n_mask;\n\t      */\n\t      if (b & 128)\n\t\t  *arduinoSetDataPort = arduino_data_mask;\n\t      else\n\t\t  *arduinoUnsetDataPort = arduino_data_mask;\n\n\t      //delayMicroseconds(us);\n\t      //*arduino_clock_port &= arduino_clock_n_mask;\n\t      *arduinoUnsetClockPort = arduino_clock_mask;\n\t      b <<= 1;\n\t      delayMicroseconds(us);\n\t      //*arduino_clock_port |= arduino_clock_mask;\t    \n\t      *arduinoSetClockPort = arduino_clock_mask;\n\t    }\n\t  }\n\t}\n      }      \n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      u8x8_gpio_SetSPIClock(u8x8, u8x8_GetSPIClockPhase(u8x8));\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_SPI_CLOCK] */\n    \n      /*\n      arduino_clock_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_CLOCK]));\n      arduino_clock_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_CLOCK]);\n      arduino_clock_n_mask = ~arduino_clock_mask;\n    \n      arduino_data_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_DATA]));\n      arduino_data_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_DATA]);\n      arduino_data_n_mask = ~arduino_data_mask;\n      */\n      \n      arduinoSetClockPort = &digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_CLOCK])->PIO_SODR;\n      arduinoUnsetClockPort = &digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_CLOCK])->PIO_CODR;\n      arduino_clock_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_CLOCK]);      \n\n      arduinoSetDataPort = &digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_DATA])->PIO_SODR;\n      arduinoUnsetDataPort = &digitalPinToPort(u8x8->pins[U8X8_PIN_SPI_DATA])->PIO_CODR;\n      arduino_data_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_SPI_DATA]);\n    \n      \n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n#else\n  /* fallback */\n  uint8_t u8x8_byte_arduino_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_4wire_sw_spi(u8x8, msg,arg_int, arg_ptr);\n  }\n  \n#endif\n\n\n/*=============================================*/\n/*=== 3 WIRE HARDWARE SPI with 8 bit HW SPI Subsystem ===*/\n/* \nreferences: \n  https://github.com/olikraus/ucglib/blob/master/cppsrc/Ucglib.cpp#L581\t\n  https://github.com/olikraus/u8g2/issues/1041 \n*/\n\nstatic uint8_t arduino_hw_spi_3w_buffer[9];\nstatic uint8_t arduino_hw_spi_3w_bytepos;\nstatic uint16_t arduino_hw_spi_3w_dc; // 0 = dc==0, 256 = dc==1\n\nstatic void arduino_hw_spi_3w_init() \n{\n    memset(arduino_hw_spi_3w_buffer, 0, 9);\n    arduino_hw_spi_3w_bytepos = 0;\n}\n\nstatic void arduino_hw_spi_3w_flush(void) \n{\n#ifdef U8X8_HAVE_HW_SPI  \n  uint8_t i;\n  for(i = 0; i <= arduino_hw_spi_3w_bytepos; i++) \n  {\n      SPI.transfer(arduino_hw_spi_3w_buffer[i]);\n  }\n#endif\n}\n\nstatic void arduino_hw_spi_3w_sendbyte(uint8_t data) \n{\n  static union { uint16_t val; struct { uint8_t lsb; uint8_t msb; }; } data16;\t\t// well well, not legal ISO 9899 code\n  \n  data16.val = (arduino_hw_spi_3w_dc + data) << (7 - arduino_hw_spi_3w_bytepos);\n#ifdef __BYTE_ORDER__ \n#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos]   |= data16.msb;\n  ++arduino_hw_spi_3w_bytepos;\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos] |= data16.lsb;\n#else\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos]   |= data16.lsb;\n  ++arduino_hw_spi_3w_bytepos;\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos] |= data16.msb;\n#endif  \n#else // __BYTE_ORDER__  not defined (no gcc)\n  // assume little endian\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos]   |= data16.msb;\n  ++arduino_hw_spi_3w_bytepos;\n  arduino_hw_spi_3w_buffer[arduino_hw_spi_3w_bytepos] |= data16.lsb;\n#endif\n  \n  if (arduino_hw_spi_3w_bytepos == 8) \n  {\n      arduino_hw_spi_3w_flush();\n      arduino_hw_spi_3w_init();\n  }\n}\n\nextern \"C\" uint8_t u8x8_byte_arduino_3wire_hw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) \n{\n#ifdef U8X8_HAVE_HW_SPI\n  \n  uint8_t *data;\n  uint8_t internal_spi_mode;\n\n  switch(msg) \n  {\n    case U8X8_MSG_BYTE_SEND:\n\tdata = (uint8_t *)arg_ptr;\n\twhile(arg_int > 0) {\n\t    arduino_hw_spi_3w_sendbyte((uint8_t)*data);\n\t    data++;\n\t    arg_int--;\n\t}\n\tbreak;\n\n    case U8X8_MSG_BYTE_INIT:\n\tif ( u8x8->bus_clock == 0 ) \t/* issue 769 */\n\t  u8x8->bus_clock = u8x8->display_info->sck_clock_hz;\n\t/* disable chipselect */\n\tu8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      \n#if defined(ESP_PLATFORM) || defined(ARDUINO_ARCH_ESP32)\n\t/* ESP32 has the following begin: SPI.begin(int8_t sck=SCK, int8_t miso=MISO, int8_t mosi=MOSI, int8_t ss=-1); */\n\t/* not sure about ESP8266 */\n\tif ( u8x8->pins[U8X8_PIN_I2C_CLOCK] != U8X8_PIN_NONE && u8x8->pins[U8X8_PIN_I2C_DATA] != U8X8_PIN_NONE )\n\t{\n\t  /* SPI.begin(int8_t sck=SCK, int8_t miso=MISO, int8_t mosi=MOSI, int8_t ss=-1); */\n\t  /* actually MISO is not used, but what else could be used here??? */\n\t  SPI.begin(u8x8->pins[U8X8_PIN_I2C_CLOCK], MISO, u8x8->pins[U8X8_PIN_I2C_DATA]);\n\t}\n\telse\n\t{\n\t  SPI.begin();\n\t}\n#else\n\tSPI.begin();\n#endif \n      break;\n      \n    case U8X8_MSG_BYTE_SET_DC:\n      arduino_hw_spi_3w_dc = arg_int ? 256 : 0;\n      break;\n      \n    case U8X8_MSG_BYTE_START_TRANSFER:\n            /* SPI mode has to be mapped to the mode of the current controller;\n               at least Uno, Due, 101 have different SPI_MODEx values */\n            internal_spi_mode =  0;\n            switch(u8x8->display_info->spi_mode) {\n                case 0: internal_spi_mode = SPI_MODE0; break;\n                case 1: internal_spi_mode = SPI_MODE1; break;\n                case 2: internal_spi_mode = SPI_MODE2; break;\n                case 3: internal_spi_mode = SPI_MODE3; break;\n            }\n      \n#if ARDUINO >= 10600\n            SPI.beginTransaction(\n                SPISettings(u8x8->bus_clock, MSBFIRST, internal_spi_mode));\n#else\n            SPI.begin();\n            if (u8x8->display_info->sck_pulse_width_ns < 70)\n                SPI.setClockDivider(SPI_CLOCK_DIV2);\n            else if (u8x8->display_info->sck_pulse_width_ns < 140)\n                SPI.setClockDivider(SPI_CLOCK_DIV4);\n            else\n                SPI.setClockDivider(SPI_CLOCK_DIV8);\n            SPI.setDataMode(internal_spi_mode);\n            SPI.setBitOrder(MSBFIRST);\n#endif\n            u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n            u8x8->gpio_and_delay_cb(\n                u8x8,\n                U8X8_MSG_DELAY_NANO,\n                u8x8->display_info->post_chip_enable_wait_ns,\n                NULL);\n            arduino_hw_spi_3w_init();\n        break;\n\n        case U8X8_MSG_BYTE_END_TRANSFER:      \n            u8x8->gpio_and_delay_cb(\n                u8x8,\n                U8X8_MSG_DELAY_NANO,\n                u8x8->display_info->pre_chip_disable_wait_ns,\n                NULL);\n            if (arduino_hw_spi_3w_bytepos)\n                arduino_hw_spi_3w_flush();\n            u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n\n#if ARDUINO >= 10600\n            SPI.endTransaction();\n#else\n            SPI.end();\n#endif\n        break;\n\n        default:\n            return 0;\n    }\n\n#endif // U8X8_HAVE_HW_SPI\n\n\n    return 1;\n}\n\n\n/*=============================================*/\n/*=== 4 WIRE HARDWARE SPI ===*/\n\n#ifdef U8X8_USE_PINS\n\nextern \"C\" uint8_t u8x8_byte_arduino_hw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n#ifdef U8X8_HAVE_HW_SPI\n  uint8_t *data;\n  uint8_t internal_spi_mode;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      \n      // 1.6.5 offers a block transfer, but the problem is, that the\n      // buffer is overwritten with the incoming data\n      // so it can not be used...\n      // SPI.transfer((uint8_t *)arg_ptr, arg_int);\n      \n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tSPI.transfer((uint8_t)*data);\n\tdata++;\n\targ_int--;\n      }\n  \n      break;\n    case U8X8_MSG_BYTE_INIT:\n      if ( u8x8->bus_clock == 0 ) \t/* issue 769 */\n\tu8x8->bus_clock = u8x8->display_info->sck_clock_hz;\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      \n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      // removed, use SPI.begin() instead: pinMode(11, OUTPUT);\n      // removed, use SPI.begin() instead: pinMode(13, OUTPUT);\n      // removed, use SPI.begin() instead: digitalWrite(13, u8x8_GetSPIClockPhase(u8x8));\n      \n      /* setup hardware with SPI.begin() instead of previous digitalWrite() and pinMode() calls */\n\n\n      /* issue #377 */\n      /* issue #378: removed ESP8266 support, which is implemented differently */\n#if defined(ESP_PLATFORM) || defined(ARDUINO_ARCH_ESP32)\n      /* ESP32 has the following begin: SPI.begin(int8_t sck=SCK, int8_t miso=MISO, int8_t mosi=MOSI, int8_t ss=-1); */\n      /* not sure about ESP8266 */\n      if ( u8x8->pins[U8X8_PIN_I2C_CLOCK] != U8X8_PIN_NONE && u8x8->pins[U8X8_PIN_I2C_DATA] != U8X8_PIN_NONE )\n      {\n\t/* SPI.begin(int8_t sck=SCK, int8_t miso=MISO, int8_t mosi=MOSI, int8_t ss=-1); */\n\t/* actually MISO is not used, but what else could be used here??? */\n\tSPI.begin(u8x8->pins[U8X8_PIN_I2C_CLOCK], MISO, u8x8->pins[U8X8_PIN_I2C_DATA]);\n      }\n      else\n      {\n\tSPI.begin();\n      }\n#else\n      SPI.begin();\n#endif \n\n      \n\n      break;\n      \n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n      \n    case U8X8_MSG_BYTE_START_TRANSFER:\n      /* SPI mode has to be mapped to the mode of the current controller, at least Uno, Due, 101 have different SPI_MODEx values */\n      internal_spi_mode =  0;\n      switch(u8x8->display_info->spi_mode)\n      {\n\tcase 0: internal_spi_mode = SPI_MODE0; break;\n\tcase 1: internal_spi_mode = SPI_MODE1; break;\n\tcase 2: internal_spi_mode = SPI_MODE2; break;\n\tcase 3: internal_spi_mode = SPI_MODE3; break;\n      }\n      \n#if ARDUINO >= 10600\n      SPI.beginTransaction(SPISettings(u8x8->bus_clock, MSBFIRST, internal_spi_mode));\n#else\n      SPI.begin();\n      \n      if ( u8x8->display_info->sck_pulse_width_ns < 70 )\n\tSPI.setClockDivider( SPI_CLOCK_DIV2 );\n      else if ( u8x8->display_info->sck_pulse_width_ns < 140 )\n\tSPI.setClockDivider( SPI_CLOCK_DIV4 );\n      else\n\tSPI.setClockDivider( SPI_CLOCK_DIV8 );\n      SPI.setDataMode(internal_spi_mode);\n      SPI.setBitOrder(MSBFIRST);\n#endif\n      \n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n      \n    case U8X8_MSG_BYTE_END_TRANSFER:      \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n\n#if ARDUINO >= 10600\n      SPI.endTransaction();\n#else\n      SPI.end();\n#endif\n\n      break;\n    default:\n      return 0;\n  }\n  \n#else\t/* U8X8_HAVE_HW_SPI */\n\n#endif\t/* U8X8_HAVE_HW_SPI */\n  return 1;\n}\n\n\n/* issue #244 */\nextern \"C\" uint8_t u8x8_byte_arduino_2nd_hw_spi(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n#ifdef U8X8_HAVE_2ND_HW_SPI\n  uint8_t *data;\n  uint8_t internal_spi_mode;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      \n      // 1.6.5 offers a block transfer, but the problem is, that the\n      // buffer is overwritten with the incoming data\n      // so it can not be used...\n      // SPI.transfer((uint8_t *)arg_ptr, arg_int);\n      \n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tSPI1.transfer((uint8_t)*data);\n\tdata++;\n\targ_int--;\n      }\n  \n      break;\n    case U8X8_MSG_BYTE_INIT:\n      if ( u8x8->bus_clock == 0 ) \t/* issue 769 */\n\tu8x8->bus_clock = u8x8->display_info->sck_clock_hz;\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI1: setup correct level of the clock signal */\n      // removed, use SPI.begin() instead: pinMode(11, OUTPUT);\n      // removed, use SPI.begin() instead: pinMode(13, OUTPUT);\n      // removed, use SPI.begin() instead: digitalWrite(13, u8x8_GetSPIClockPhase(u8x8));\n      \n      /* setup hardware with SPI.begin() instead of previous digitalWrite() and pinMode() calls */\n      SPI1.begin();\t\n\n      break;\n      \n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n      \n    case U8X8_MSG_BYTE_START_TRANSFER:\n      /* SPI1 mode has to be mapped to the mode of the current controller, at least Uno, Due, 101 have different SPI_MODEx values */\n      internal_spi_mode =  0;\n      switch(u8x8->display_info->spi_mode)\n      {\n\tcase 0: internal_spi_mode = SPI_MODE0; break;\n\tcase 1: internal_spi_mode = SPI_MODE1; break;\n\tcase 2: internal_spi_mode = SPI_MODE2; break;\n\tcase 3: internal_spi_mode = SPI_MODE3; break;\n      }\n      \n#if ARDUINO >= 10600\n      SPI1.beginTransaction(SPISettings(u8x8->bus_clock, MSBFIRST, internal_spi_mode));\n#else\n      SPI1.begin();\n      \n      if ( u8x8->display_info->sck_pulse_width_ns < 70 )\n\tSPI1.setClockDivider( SPI_CLOCK_DIV2 );\n      else if ( u8x8->display_info->sck_pulse_width_ns < 140 )\n\tSPI1.setClockDivider( SPI_CLOCK_DIV4 );\n      else\n\tSPI1.setClockDivider( SPI_CLOCK_DIV8 );\n      SPI1.setDataMode(internal_spi_mode);\n      SPI1.setBitOrder(MSBFIRST);\n#endif\n      \n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n      \n    case U8X8_MSG_BYTE_END_TRANSFER:      \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n\n#if ARDUINO >= 10600\n      SPI1.endTransaction();\n#else\n      SPI1.end();\n#endif\n\n      break;\n    default:\n      return 0;\n  }\n  \n#else\n#endif\n  return 1;\n}\n\n/*=============================================*/\n/* fast SW I2C for AVR uC */\n\n\n#if !defined(U8X8_USE_PINS)\n  /* no pin information (very strange), so fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_sw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n    return u8x8_byte_sw_i2c(u8x8, msg,arg_int, arg_ptr);\n}\n\n#elif !defined(U8X8_USE_ARDUINO_AVR_SW_I2C_OPTIMIZATION)\n\nextern \"C\" uint8_t u8x8_byte_arduino_sw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n    return u8x8_byte_sw_i2c(u8x8, msg,arg_int, arg_ptr);\n}\n\n#elif __AVR_ARCH__ == 4 || __AVR_ARCH__ == 5 || __AVR_ARCH__ == 51 || __AVR_ARCH__ == 6 || __AVR_ARCH__ == 103\n\n\n/* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n/* so, it should be possible to use multiple displays with different pins */\n\nstatic volatile uint8_t *arduino_i2c_clock_port;\n\nstatic uint8_t arduino_i2c_clock_mask;\nstatic uint8_t arduino_i2c_clock_n_mask;\n\nstatic volatile uint8_t *arduino_i2c_data_port;\nstatic uint8_t arduino_i2c_data_mask;\nstatic uint8_t arduino_i2c_data_n_mask;\n\n/*\n  software i2c,\n  ignores ACK response (which is anyway not provided by some displays)\n  also does not allow reading from the device\n*/\nstatic void i2c_delay(u8x8_t *u8x8) U8X8_NOINLINE;\nstatic void i2c_delay(u8x8_t *u8x8)\n{\n  //u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_10MICRO, u8x8->display_info->i2c_bus_clock_100kHz);\n  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_I2C, u8x8->display_info->i2c_bus_clock_100kHz);\n}\n\nstatic void i2c_init(u8x8_t *u8x8)\n{\n  *arduino_i2c_clock_port |= arduino_i2c_clock_mask;\n  *arduino_i2c_data_port |= arduino_i2c_data_mask;\n  i2c_delay(u8x8);\n}\n\n/* actually, the scl line is not observed, so this procedure does not return a value */\n\nstatic void i2c_read_scl_and_delay(u8x8_t *u8x8)\n{\n  /* set as input (line will be high) */\n  *arduino_i2c_clock_port |= arduino_i2c_clock_mask;\n\n  i2c_delay(u8x8);\n}\n\nstatic void i2c_clear_scl(u8x8_t *u8x8)\n{\n  *arduino_i2c_clock_port &= arduino_i2c_clock_n_mask;\n}\n\nstatic void i2c_read_sda(u8x8_t *u8x8)\n{\n  /* set as input (line will be high) */\n  *arduino_i2c_data_port |= arduino_i2c_data_mask;\n}\n\nstatic void i2c_clear_sda(u8x8_t *u8x8)\n{\n  /* set open collector and drive low */\n  *arduino_i2c_data_port &= arduino_i2c_data_n_mask;\n}\n\nstatic void i2c_start(u8x8_t *u8x8)\n{\n  if ( u8x8->i2c_started != 0 )\n  {\n    /* if already started: do restart */\n    i2c_read_sda(u8x8);     /* SDA = 1 */\n    i2c_delay(u8x8);\n    i2c_read_scl_and_delay(u8x8);\n  }\n  i2c_read_sda(u8x8);\n  /* send the start condition, both lines go from 1 to 0 */\n  i2c_clear_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_clear_scl(u8x8);\n  u8x8->i2c_started = 1;\n}\n\n\nstatic void i2c_stop(u8x8_t *u8x8)\n{\n  /* set SDA to 0 */\n  i2c_clear_sda(u8x8);  \n  i2c_delay(u8x8);\n \n  /* now release all lines */\n  i2c_read_scl_and_delay(u8x8);\n \n  /* set SDA to 1 */\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  u8x8->i2c_started = 0;\n}\n\nstatic void i2c_write_bit(u8x8_t *u8x8, uint8_t val)\n{\n  if (val)\n    i2c_read_sda(u8x8);\n  else\n    i2c_clear_sda(u8x8);\n \n  i2c_delay(u8x8);\n  i2c_read_scl_and_delay(u8x8);\n  i2c_clear_scl(u8x8);\n}\n\nstatic void i2c_read_bit(u8x8_t *u8x8)\n{\n  //uint8_t val;\n  /* do not drive SDA */\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_read_scl_and_delay(u8x8);\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_clear_scl(u8x8);\n  //return val;\n}\n\nstatic void i2c_write_byte(u8x8_t *u8x8, uint8_t b)\n{\n  i2c_write_bit(u8x8, b & 128);\n  i2c_write_bit(u8x8, b & 64);\n  i2c_write_bit(u8x8, b & 32);\n  i2c_write_bit(u8x8, b & 16);\n  i2c_write_bit(u8x8, b & 8);\n  i2c_write_bit(u8x8, b & 4);\n  i2c_write_bit(u8x8, b & 2);\n  i2c_write_bit(u8x8, b & 1);\n    \n  /* read ack from client */\n  /* 0: ack was given by client */\n  /* 1: nothing happend during ack cycle */  \n  i2c_read_bit(u8x8);\n}\n\n\nextern \"C\" uint8_t u8x8_byte_arduino_sw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n  uint8_t *data;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      \n      while( arg_int > 0 )\n      {\n\ti2c_write_byte(u8x8, *data);\n\tdata++;\n\targ_int--;\n      }\n      \n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      pinMode(u8x8->pins[U8X8_PIN_I2C_CLOCK], OUTPUT);\n      digitalWrite(u8x8->pins[U8X8_PIN_I2C_CLOCK], 1);\n\n      pinMode(u8x8->pins[U8X8_PIN_I2C_DATA], OUTPUT);\n      digitalWrite(u8x8->pins[U8X8_PIN_I2C_DATA], 1);\n\n      i2c_init(u8x8);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n    \n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_I2C_CLOCK] */\n    \n      arduino_i2c_clock_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_I2C_CLOCK]));\n      arduino_i2c_clock_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_I2C_CLOCK]);\n      arduino_i2c_clock_n_mask = ~arduino_i2c_clock_mask;\n    \n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_I2C_DATA] */\n\n      arduino_i2c_data_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_I2C_DATA]));\n      arduino_i2c_data_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_I2C_DATA]);\n      arduino_i2c_data_n_mask = ~arduino_i2c_data_mask;\n\n      i2c_start(u8x8);\n      i2c_write_byte(u8x8, u8x8_GetI2CAddress(u8x8));\n      \n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      i2c_stop(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n  \n}\n\n#else\n\n/* not AVR architecture, fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_sw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n    return u8x8_byte_sw_i2c(u8x8, msg,arg_int, arg_ptr);\n}\n\n#endif\n\n/*=============================================*/\n/*=== HARDWARE I2C ===*/\n\nextern \"C\" uint8_t u8x8_byte_arduino_hw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n#ifdef U8X8_HAVE_HW_I2C\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      Wire.write((uint8_t *)arg_ptr, (int)arg_int);\n      break;\n    case U8X8_MSG_BYTE_INIT:\n      if ( u8x8->bus_clock == 0 ) \t/* issue 769 */\n\tu8x8->bus_clock = u8x8->display_info->i2c_bus_clock_100kHz * 100000UL;\n#if defined(ESP8266) || defined(ARDUINO_ARCH_ESP8266) || defined(ESP_PLATFORM) || defined(ARDUINO_ARCH_ESP32)\n      /* for ESP8266/ESP32, Wire.begin has two more arguments: clock and data */          \n      if ( u8x8->pins[U8X8_PIN_I2C_CLOCK] != U8X8_PIN_NONE && u8x8->pins[U8X8_PIN_I2C_DATA] != U8X8_PIN_NONE )\n      {\n\t// second argument for the wire lib is the clock pin. In u8g2, the first argument of the  clock pin in the clock/data pair\n\tWire.begin(u8x8->pins[U8X8_PIN_I2C_DATA] , u8x8->pins[U8X8_PIN_I2C_CLOCK]);\n      }\n      else\n      {\n\tWire.begin();\n      }\n#else\n      Wire.begin();\n#endif\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n#if ARDUINO >= 10600\n      /* not sure when the setClock function was introduced, but it is there since 1.6.0 */\n      /* if there is any error with Wire.setClock() just remove this function call */\n      Wire.setClock(u8x8->bus_clock); \n#endif\n      Wire.beginTransmission(u8x8_GetI2CAddress(u8x8)>>1);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      Wire.endTransmission();\n      break;\n    default:\n      return 0;\n  }\n#endif\n  return 1;\n}\n\nextern \"C\" uint8_t u8x8_byte_arduino_2nd_hw_i2c(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n#ifdef U8X8_HAVE_2ND_HW_I2C\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      Wire1.write((uint8_t *)arg_ptr, (int)arg_int);\n      break;\n    case U8X8_MSG_BYTE_INIT:\n      if ( u8x8->bus_clock == 0 ) \t/* issue 769 */\n\tu8x8->bus_clock = u8x8->display_info->i2c_bus_clock_100kHz * 100000UL;\n      Wire1.begin();\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n#if ARDUINO >= 10600\n      /* not sure when the setClock function was introduced, but it is there since 1.6.0 */\n      /* if there is any error with Wire.setClock() just remove this function call */\n      Wire1.setClock(u8x8->bus_clock); \n#endif\n      Wire1.beginTransmission(u8x8_GetI2CAddress(u8x8)>>1);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      Wire1.endTransmission();\n      break;\n    default:\n      return 0;\n  }\n#endif\n  return 1;\n}\n\n#endif // U8X8_USE_PINS\n\n/*=============================================*/\n\n/*\n  replacement for a more faster u8x8_byte_8bit_8080mode\n  in general u8x8_byte_8bit_8080mode could be a fallback:\n\n  uint8_t u8x8_byte_arduino_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_8bit_8080mode(u8x8, msg,arg_int, arg_ptr);\n  }\n\n\n\n*/\n\n#ifndef __AVR_ARCH__\n#define __AVR_ARCH__ 0\n#endif \n\n#if !defined(U8X8_USE_PINS)\n  /* no pin information (very strange), so fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_byte_8bit_8080mode(u8x8, msg,arg_int, arg_ptr);\n}\n\n#elif __AVR_ARCH__ == 4 || __AVR_ARCH__ == 5 || __AVR_ARCH__ == 51 || __AVR_ARCH__ == 6 || __AVR_ARCH__ == 103\n\n/* this function completly replaces u8x8_byte_8bit_8080mode*/\nextern \"C\" uint8_t u8x8_byte_arduino_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n\n  /* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n  /* so, it should be possible to use multiple displays with different pins */\n  \n  static volatile uint8_t *arduino_e_port;\n  static volatile uint8_t arduino_e_mask;\n  static volatile uint8_t arduino_e_n_mask;\n  \n  static volatile uint8_t *arduino_data_port[8];\n  static volatile uint8_t arduino_data_mask[8];\n  static volatile uint8_t arduino_data_n_mask[8];\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = 0; i < 8; i++ )\n\t{\n\t  if ( b & 1 )\n\t    *arduino_data_port[i] |= arduino_data_mask[i];\n\t  else\n\t    *arduino_data_port[i] &= arduino_data_n_mask[i];\n\t  b >>= 1;\n\n\t}\n\t\n\t*arduino_e_port &= arduino_e_n_mask;\n\n\t      \n\t/* AVR Architecture is very slow, extra call is not required */\n\t//u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sda_setup_time_ns);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\t\n\t*arduino_e_port |= arduino_e_mask;\n\t\n\t/* AVR Architecture is very slow, extra call is not required */\n\t//u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sck_pulse_width_ns);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);\n\t\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* ensure that the enable signal is high */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 1);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_E] */\n    \n      arduino_e_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_E]));\n      arduino_e_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_E]);\n      arduino_e_n_mask = ~arduino_e_mask;\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_D0] */\n\n      for( i = 0; i < 8; i++ )\n      {\n\tarduino_data_port[i] = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_D0+i]));\n\tarduino_data_mask[i] = digitalPinToBitMask(u8x8->pins[U8X8_PIN_D0+i]);\n\tarduino_data_n_mask[i] = ~arduino_data_mask[i];\n      }\n\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n#else\n  /* fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_byte_8bit_8080mode(u8x8, msg,arg_int, arg_ptr);\n}\n  \n#endif\n\n\n/*=============================================*/\n\n/*\n  replacement for a more faster u8x8_byte_ks0108\n  in general u8x8_byte_ks0108 could be a fallback:\n\n  uint8_t u8x8_byte_arduino_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n  {\n    return u8x8_byte_ks0108(u8x8, msg,arg_int, arg_ptr);\n  }\n\n\n\n*/\n\n#ifndef __AVR_ARCH__\n#define __AVR_ARCH__ 0\n#endif \n\n#if !defined(U8X8_USE_PINS)\n  /* no pin information (very strange), so fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_byte_ks0108(u8x8, msg,arg_int, arg_ptr);\n}\n\n#elif __AVR_ARCH__ == 4 || __AVR_ARCH__ == 5 || __AVR_ARCH__ == 51 || __AVR_ARCH__ == 6 || __AVR_ARCH__ == 103\n\n/* this function completly replaces u8x8_byte_ks0108*/\nextern \"C\" uint8_t u8x8_byte_arduino_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n\n  /* the following static vars are recalculated in U8X8_MSG_BYTE_START_TRANSFER */\n  /* so, it should be possible to use multiple displays with different pins */\n  \n  static volatile uint8_t *arduino_e_port;\n  static volatile uint8_t arduino_e_mask;\n  static volatile uint8_t arduino_e_n_mask;\n  \n  static volatile uint8_t *arduino_data_port[8];\n  static volatile uint8_t arduino_data_mask[8];\n  static volatile uint8_t arduino_data_n_mask[8];\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = 0; i < 8; i++ )\n\t{\n\t  if ( b & 1 )\n\t    *arduino_data_port[i] |= arduino_data_mask[i];\n\t  else\n\t    *arduino_data_port[i] &= arduino_data_n_mask[i];\n\t  b >>= 1;\n\n\t}\n\t\n\t*arduino_e_port |= arduino_e_mask;\n\n\t      \n\t/* AVR Architecture is very slow, extra call is not required */\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\t\n\t*arduino_e_port &= arduino_e_n_mask;\n\t\n\t/* AVR Architecture is very slow, extra call is not required */\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);\n\t\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* ensure that the enable signal is low */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_byte_set_ks0108_cs(u8x8, arg_int);\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_E] */\n    \n      arduino_e_port = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_E]));\n      arduino_e_mask = digitalPinToBitMask(u8x8->pins[U8X8_PIN_E]);\n      arduino_e_n_mask = ~arduino_e_mask;\n\n      /* there is no consistency checking for u8x8->pins[U8X8_PIN_D0] */\n\n      for( i = 0; i < 8; i++ )\n      {\n\tarduino_data_port[i] = portOutputRegister(digitalPinToPort(u8x8->pins[U8X8_PIN_D0+i]));\n\tarduino_data_mask[i] = digitalPinToBitMask(u8x8->pins[U8X8_PIN_D0+i]);\n\tarduino_data_n_mask[i] = ~arduino_data_mask[i];\n      }\n\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_byte_set_ks0108_cs(u8x8, arg_int);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n#else\n  /* fallback */\nextern \"C\" uint8_t u8x8_byte_arduino_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_byte_ks0108(u8x8, msg,arg_int, arg_ptr);\n}\n  \n#endif\n\n\n\n\n\n\n\n\n#ifdef U8X8_USE_PINS\n\n/*\n  use U8X8_PIN_NONE as value for \"reset\", if there is no reset line\n*/\n\nvoid u8x8_SetPin_4Wire_SW_SPI(u8x8_t *u8x8, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_4Wire_SW_SPI(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t clock, uint8_t data, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_4wire_sw_spi, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\nvoid u8x8_SetPin_3Wire_SW_SPI(u8x8_t *u8x8, uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_3Wire_SW_SPI(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t clock, uint8_t data, uint8_t cs, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_3wire_sw_spi, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_SPI_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\n/*\n  use U8X8_PIN_NONE as value for \"reset\", if there is no reset line\n*/\nvoid u8x8_SetPin_3Wire_HW_SPI(u8x8_t *u8x8, uint8_t cs, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n/*\n  use U8X8_PIN_NONE as value for \"reset\", if there is no reset line\n*/\nvoid u8x8_SetPin_4Wire_HW_SPI(u8x8_t *u8x8, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\nvoid u8x8_SetPin_ST7920_HW_SPI(u8x8_t *u8x8, uint8_t cs, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_4Wire_HW_SPI(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_arduino_hw_spi, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\n\nvoid u8x8_SetPin_SW_I2C(u8x8_t *u8x8, uint8_t clock, uint8_t data, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_SSD13xx_SW_I2C(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t clock, uint8_t data, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_ssd13xx_sw_i2c, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_DATA, data);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\nvoid u8x8_SetPin_HW_I2C(u8x8_t *u8x8, uint8_t reset, uint8_t clock, uint8_t data)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_CLOCK, clock);\n  u8x8_SetPin(u8x8, U8X8_PIN_I2C_DATA, data);\n}\n\nvoid u8x8_SetPin_8Bit_6800(u8x8_t *u8x8, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, enable);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_8Bit_6800(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_8bit_6800mode, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, enable);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\n\nvoid u8x8_SetPin_8Bit_8080(u8x8_t *u8x8, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t wr, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, wr);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\n\n#ifdef _obsolete_com_specific_setup\nvoid u8x8_Setup_8Bit_8080(u8x8_t *u8x8, u8x8_msg_cb display_cb, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t wr, uint8_t cs, uint8_t dc, uint8_t reset)\n{\n  u8x8_Setup(u8x8, display_cb, u8x8_cad_001, u8x8_byte_8bit_8080mode, u8x8_gpio_and_delay_arduino);\n  \n  /* assign individual pin values (only for ARDUINO, if pin_list is available) */\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, wr);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif /* obsolete com specific setup */\n\nvoid u8x8_SetPin_KS0108(u8x8_t *u8x8, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t enable, uint8_t dc, uint8_t cs0, uint8_t cs1, uint8_t cs2, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, enable);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, cs0);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS1, cs1);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS2, cs2);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n\nvoid u8x8_SetPin_SED1520(u8x8_t *u8x8, uint8_t d0, uint8_t d1, uint8_t d2, uint8_t d3, uint8_t d4, uint8_t d5, uint8_t d6, uint8_t d7, uint8_t dc, uint8_t e1, uint8_t e2, uint8_t reset)\n{\n  u8x8_SetPin(u8x8, U8X8_PIN_D0, d0);\n  u8x8_SetPin(u8x8, U8X8_PIN_D1, d1);\n  u8x8_SetPin(u8x8, U8X8_PIN_D2, d2);\n  u8x8_SetPin(u8x8, U8X8_PIN_D3, d3);\n  u8x8_SetPin(u8x8, U8X8_PIN_D4, d4);\n  u8x8_SetPin(u8x8, U8X8_PIN_D5, d5);\n  u8x8_SetPin(u8x8, U8X8_PIN_D6, d6);\n  u8x8_SetPin(u8x8, U8X8_PIN_D7, d7);\n  u8x8_SetPin(u8x8, U8X8_PIN_E, e1);\n  u8x8_SetPin(u8x8, U8X8_PIN_CS, e2);\n  u8x8_SetPin(u8x8, U8X8_PIN_DC, dc);\n  u8x8_SetPin(u8x8, U8X8_PIN_RESET, reset);\n}\n#endif // U8X8_USE_PINS\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/U8x8lib.h",
    "content": "#ifndef U8X8LIB_HH\n#define U8X8LIB_HH\n\n#include <Print.h>\n#include \"u8x8.h\"\n\n#define U8X8_HAVE_HW_I2C\n\n/* Exported variables --------------------------------------------------------*/\nextern \"C\" uint8_t u8x8_byte_stm32_hw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\nextern \"C\" uint8_t u8x8_stm32_gpio_and_delay(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, U8X8_UNUSED void *arg_ptr);\n\nclass U8X8 : public Print\n{\nprotected:\n    u8x8_t u8x8;\npublic:\n    uint8_t tx, ty;\n\n    U8X8(void)\n    { home(); }\n\n    u8x8_t *getU8x8(void)\n    { return &u8x8; }\n\n    void sendF(const char *fmt, ...)\n    {\n        va_list va;\n        va_start(va, fmt);\n        u8x8_cad_vsendf(&u8x8, fmt, va);\n        va_end(va);\n    }\n\n    uint32_t getBusClock(void)\n    { return u8x8.bus_clock; }\n\n    void setBusClock(uint32_t clock_speed)\n    { u8x8.bus_clock = clock_speed; }\n\n    void setI2CAddress(uint8_t adr)\n    { u8x8_SetI2CAddress(&u8x8, adr); }\n\n    uint8_t getCols(void)\n    { return u8x8_GetCols(&u8x8); }\n\n    uint8_t getRows(void)\n    { return u8x8_GetRows(&u8x8); }\n\n    void drawTile(uint8_t x, uint8_t y, uint8_t cnt, uint8_t *tile_ptr)\n    {\n        u8x8_DrawTile(&u8x8, x, y, cnt, tile_ptr);\n    }\n\n    void initDisplay(void)\n    {\n        u8x8_InitDisplay(&u8x8);\n    }\n\n    void clearDisplay(void)\n    {\n        u8x8_ClearDisplay(&u8x8);\n    }\n\n    void fillDisplay(void)\n    {\n        u8x8_FillDisplay(&u8x8);\n    }\n\n    void setPowerSave(uint8_t is_enable)\n    {\n        u8x8_SetPowerSave(&u8x8, is_enable);\n    }\n\n    bool begin(void)\n    {\n        initDisplay();\n        clearDisplay();\n        setPowerSave(0);\n        return 1;\n    }\n\n    void setFlipMode(uint8_t mode)\n    {\n        u8x8_SetFlipMode(&u8x8, mode);\n    }\n\n    void refreshDisplay(void)\n    {            // Dec 16: Only required for SSD1606\n        u8x8_RefreshDisplay(&u8x8);\n    }\n\n    void clearLine(uint8_t line)\n    {\n        u8x8_ClearLine(&u8x8, line);\n    }\n\n    void setContrast(uint8_t value)\n    {\n        u8x8_SetContrast(&u8x8, value);\n    }\n\n    void setInverseFont(uint8_t value)\n    {\n        u8x8_SetInverseFont(&u8x8, value);\n    }\n\n    void setFont(const uint8_t *font_8x8)\n    {\n        u8x8_SetFont(&u8x8, font_8x8);\n    }\n\n    void drawGlyph(uint8_t x, uint8_t y, uint8_t encoding)\n    {\n        u8x8_DrawGlyph(&u8x8, x, y, encoding);\n    }\n\n    void draw2x2Glyph(uint8_t x, uint8_t y, uint8_t encoding)\n    {\n        u8x8_Draw2x2Glyph(&u8x8, x, y, encoding);\n    }\n\n    void draw1x2Glyph(uint8_t x, uint8_t y, uint8_t encoding)\n    {\n        u8x8_Draw1x2Glyph(&u8x8, x, y, encoding);\n    }\n\n    void drawString(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_DrawString(&u8x8, x, y, s);\n    }\n\n    void drawUTF8(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_DrawUTF8(&u8x8, x, y, s);\n    }\n\n    void draw2x2String(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_Draw2x2String(&u8x8, x, y, s);\n    }\n\n    void draw1x2String(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_Draw1x2String(&u8x8, x, y, s);\n    }\n\n    void draw2x2UTF8(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_Draw2x2UTF8(&u8x8, x, y, s);\n    }\n\n    void draw1x2UTF8(uint8_t x, uint8_t y, const char *s)\n    {\n        u8x8_Draw1x2UTF8(&u8x8, x, y, s);\n    }\n\n    uint8_t getUTF8Len(const char *s)\n    {\n        return u8x8_GetUTF8Len(&u8x8, s);\n    }\n\n    size_t write(uint8_t v);\n\n    /* code extended and moved to .cpp file, issue 74\n    size_t write(uint8_t v) {\n      u8x8_DrawGlyph(&u8x8, tx, ty, v);\n      tx++;\n      return 1;\n     }\n      */\n\n    size_t write(const uint8_t *buffer, size_t size)\n    {\n        size_t cnt = 0;\n        while (size > 0)\n        {\n            cnt += write(*buffer++);\n            size--;\n        }\n        return cnt;\n    }\n\n    void inverse(void)\n    { setInverseFont(1); }\n\n    void noInverse(void)\n    { setInverseFont(0); }\n\n    /* return 0 for no event or U8X8_MSG_GPIO_MENU_SELECT, */\n    /* U8X8_MSG_GPIO_MENU_NEXT, U8X8_MSG_GPIO_MENU_PREV, */\n    /* U8X8_MSG_GPIO_MENU_HOME */\n    uint8_t getMenuEvent(void)\n    { return u8x8_GetMenuEvent(&u8x8); }\n\n    uint8_t userInterfaceSelectionList(const char *title, uint8_t start_pos, const char *sl)\n    {\n        return u8x8_UserInterfaceSelectionList(&u8x8, title, start_pos, sl);\n    }\n\n    uint8_t userInterfaceMessage(const char *title1, const char *title2, const char *title3, const char *buttons)\n    {\n        return u8x8_UserInterfaceMessage(&u8x8, title1, title2, title3, buttons);\n    }\n\n    uint8_t\n    userInterfaceInputValue(const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits,\n                            const char *post)\n    {\n        return u8x8_UserInterfaceInputValue(&u8x8, title, pre, value, lo, hi, digits, post);\n    }\n\n    /* LiquidCrystal compatible functions */\n    void home(void)\n    {\n        tx = 0;\n        ty = 0;\n    }\n\n    void clear(void)\n    {\n        clearDisplay();\n        home();\n    }\n\n    void noDisplay(void)\n    { u8x8_SetPowerSave(&u8x8, 1); }\n\n    void display(void)\n    { u8x8_SetPowerSave(&u8x8, 0); }\n\n    void setCursor(uint8_t x, uint8_t y)\n    {\n        tx = x;\n        ty = y;\n    }\n\n    void drawLog(uint8_t x, uint8_t y, class U8X8LOG &u8x8log);\n\n};\n\nclass U8X8LOG : public Print\n{\n\npublic:\n    u8log_t u8log;\n\n    /* the constructor does nothing, use begin() instead */\n    U8X8LOG(void)\n    {}\n\n    /* connect to u8g2, draw to u8g2 whenever required */\n    bool begin(class U8X8 &u8x8, uint8_t width, uint8_t height, uint8_t *buf)\n    {\n        u8log_Init(&u8log, width, height, buf);\n        u8log_SetCallback(&u8log, u8log_u8x8_cb, u8x8.getU8x8());\n        return true;\n    }\n\n    /* disconnected version, manual redraw required */\n    bool begin(uint8_t width, uint8_t height, uint8_t *buf)\n    {\n        u8log_Init(&u8log, width, height, buf);\n        return true;\n    }\n\n    void setLineHeightOffset(int8_t line_height_offset)\n    {\n        u8log_SetLineHeightOffset(&u8log, line_height_offset);\n    }\n\n    void setRedrawMode(uint8_t is_redraw_line_for_each_char)\n    {\n        u8log_SetRedrawMode(&u8log, is_redraw_line_for_each_char);\n    }\n\n    /* virtual function for print base class */\n    size_t write(uint8_t v)\n    {\n        u8log_WriteChar(&u8log, v);\n        return 1;\n    }\n\n    size_t write(const uint8_t *buffer, size_t size)\n    {\n        size_t cnt = 0;\n        while (size > 0)\n        {\n            cnt += write(*buffer++);\n            size--;\n        }\n        return cnt;\n    }\n\n    void writeString(const char *s)\n    { u8log_WriteString(&u8log, s); }\n\n    void writeChar(uint8_t c)\n    { u8log_WriteChar(&u8log, c); }\n\n    void writeHex8(uint8_t b)\n    { u8log_WriteHex8(&u8log, b); }\n\n    void writeHex16(uint16_t v)\n    { u8log_WriteHex16(&u8log, v); }\n\n    void writeHex32(uint32_t v)\n    { u8log_WriteHex32(&u8log, v); }\n\n    void writeDec8(uint8_t v, uint8_t d)\n    { u8log_WriteDec8(&u8log, v, d); }\n\n    void writeDec16(uint8_t v, uint8_t d)\n    { u8log_WriteDec16(&u8log, v, d); }\n};\n\n\n/* u8log_u8x8.c */\ninline void U8X8::drawLog(uint8_t x, uint8_t y, class U8X8LOG &u8x8log)\n{\n    u8x8_DrawLog(&u8x8, x, y, &(u8x8log.u8log));\n}\n\n\n#endif /* _U8X8LIB_HH */\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/WString.cpp",
    "content": "/*\n WString.cpp - String library for Wiring & Arduino\n ...mostly rewritten by Paul Stoffregen...\n Copyright (c) 2009-10 Hernando Barragan.  All rights reserved.\n Copyright 2011, Paul Stoffregen, paul@pjrc.com\n Modified by Ivan Grokhotkov, 2014 - esp8266 support\n Modified by Michael C. Miller, 2015 - esp8266 progmem support\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n\n#include <cstdio>\n#include \"WString.h\"\n#include \"stdlib_noniso.h\"\n#include \"pgmspace.h\"\n\n/*********************************************/\n/*  Constructors                             */\n/*********************************************/\n\nString::String(const char *cstr) {\n    init();\n    if (cstr)\n        copy(cstr, strlen(cstr));\n}\n\nString::String(const String &value) {\n    init();\n    *this = value;\n}\n\nString::String(const __FlashStringHelper *pstr) {\n    init();\n    *this = pstr; // see operator =\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nString::String(String &&rval) {\n    init();\n    move(rval);\n}\n\nString::String(StringSumHelper &&rval) {\n    init();\n    move(rval);\n}\n#endif\n\nString::String(char c) {\n    init();\n    char buf[2];\n    buf[0] = c;\n    buf[1] = 0;\n    *this = buf;\n}\n\nString::String(unsigned char value, unsigned char base) {\n    init();\n    char buf[1 + 8 * sizeof(unsigned char)];\n    utoa(value, buf, base);\n    *this = buf;\n}\n\nString::String(int value, unsigned char base) {\n    init();\n    char buf[2 + 8 * sizeof(int)];\n    if (base == 10) {\n        sprintf(buf, \"%d\", value);\n    } else {\n        itoa(value, buf, base);\n    }\n    *this = buf;\n}\n\nString::String(unsigned int value, unsigned char base) {\n    init();\n    char buf[1 + 8 * sizeof(unsigned int)];\n    utoa(value, buf, base);\n    *this = buf;\n}\n\nString::String(long value, unsigned char base) {\n    init();\n    char buf[2 + 8 * sizeof(long)];\n    if (base==10) {\n        sprintf(buf, \"%ld\", value);\n    } else {\n        ltoa(value, buf, base);\n    }\n    *this = buf;\n}\n\nString::String(unsigned long value, unsigned char base) {\n    init();\n    char buf[1 + 8 * sizeof(unsigned long)];\n    ultoa(value, buf, base);\n    *this = buf;\n}\n\nString::String(float value, unsigned char decimalPlaces) {\n    init();\n    char buf[33];\n    *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);\n}\n\nString::String(double value, unsigned char decimalPlaces) {\n    init();\n    char buf[33];\n    *this = dtostrf(value, (decimalPlaces + 2), decimalPlaces, buf);\n}\n\nString::~String() {\n    invalidate();\n}\n\n// /*********************************************/\n// /*  Memory Management                        */\n// /*********************************************/\n\ninline void String::init(void) {\n    setSSO(false);\n    setBuffer(nullptr);\n    setCapacity(0);\n    setLen(0);\n}\n\nvoid String::invalidate(void) {\n    if(!isSSO() && wbuffer())\n        free(wbuffer());\n    init();\n}\n\nunsigned char String::reserve(unsigned int size) {\n    if(buffer() && capacity() >= size)\n        return 1;\n    if(changeBuffer(size)) {\n        if(len() == 0)\n            wbuffer()[0] = 0;\n        return 1;\n    }\n    return 0;\n}\n\nunsigned char String::changeBuffer(unsigned int maxStrLen) {\n    // Can we use SSO here to avoid allocation?\n    if (maxStrLen < sizeof(sso.buff) - 1) {\n        if (isSSO() || !buffer()) {\n            // Already using SSO, nothing to do\n\t    uint16_t oldLen = len();\n            setSSO(true);\n            setLen(oldLen);\n            return 1;\n        } else { // if bufptr && !isSSO()\n            // Using bufptr, need to shrink into sso.buff\n            char temp[sizeof(sso.buff)];\n            memcpy(temp, buffer(), maxStrLen);\n            free(wbuffer());\n            uint16_t oldLen = len();\n            setSSO(true);\n            memcpy(wbuffer(), temp, maxStrLen);\n            setLen(oldLen);\n            return 1;\n        }\n    }\n    // Fallthrough to normal allocator\n    size_t newSize = (maxStrLen + 16) & (~0xf);\n    // Make sure we can fit newsize in the buffer\n    if (newSize > CAPACITY_MAX) {\n        return false;\n    }\n    uint16_t oldLen = len();\n    char *newbuffer = (char *) realloc(isSSO() ? nullptr : wbuffer(), newSize);\n    if (newbuffer) {\n        size_t oldSize = capacity() + 1; // include NULL.\n        if (isSSO()) {\n            // Copy the SSO buffer into allocated space\n            memmove(newbuffer, sso.buff, sizeof(sso.buff));\n        }\n        if (newSize > oldSize)\n        {\n            memset(newbuffer + oldSize, 0, newSize - oldSize);\n        }\n        setSSO(false);\n        setCapacity(newSize - 1);\n        setBuffer(newbuffer);\n        setLen(oldLen); // Needed in case of SSO where len() never existed\n        return 1;\n    }\n    return 0;\n}\n\n// /*********************************************/\n// /*  Copy and Move                            */\n// /*********************************************/\n\nString & String::copy(const char *cstr, unsigned int length) {\n    if(!reserve(length)) {\n        invalidate();\n        return *this;\n    }\n    memmove(wbuffer(), cstr, length + 1);\n    setLen(length);\n    return *this;\n}\n\nString & String::copy(const __FlashStringHelper *pstr, unsigned int length) {\n    if (!reserve(length)) {\n        invalidate();\n        return *this;\n    }\n    memcpy_P(wbuffer(), (PGM_P)pstr, length + 1); // We know wbuffer() cannot ever be in PROGMEM, so memcpy safe here\n    setLen(length);\n    return *this;\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nvoid String::move(String &rhs) {\n    if(buffer()) {\n        if(capacity() >= rhs.len()) {\n            memmove(wbuffer(), rhs.buffer(), rhs.length() + 1);\n            setLen(rhs.len());\n\t    rhs.invalidate();\n            return;\n        } else {\n            if (!isSSO()) {\n                free(wbuffer());\n                setBuffer(nullptr);\n            }\n        }\n    }\n    if (rhs.isSSO()) {\n        setSSO(true);\n        memmove(sso.buff, rhs.sso.buff, sizeof(sso.buff));\n    } else {\n        setSSO(false);\n        setBuffer(rhs.wbuffer());\n    }\n    setCapacity(rhs.capacity());\n    setLen(rhs.len());\n    rhs.setSSO(false);\n    rhs.setCapacity(0);\n    rhs.setBuffer(nullptr);\n    rhs.setLen(0);\n}\n#endif\n\nString & String::operator =(const String &rhs) {\n    if(this == &rhs)\n        return *this;\n\n    if(rhs.buffer())\n        copy(rhs.buffer(), rhs.len());\n    else\n        invalidate();\n\n    return *this;\n}\n\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\nString & String::operator =(String &&rval) {\n    if(this != &rval)\n        move(rval);\n    return *this;\n}\n\nString & String::operator =(StringSumHelper &&rval) {\n    if(this != &rval)\n        move(rval);\n    return *this;\n}\n#endif\n\nString & String::operator =(const char *cstr) {\n    if(cstr)\n        copy(cstr, strlen(cstr));\n    else\n        invalidate();\n\n    return *this;\n}\n\nString & String::operator = (const __FlashStringHelper *pstr)\n{\n    if (pstr) copy(pstr, strlen_P((PGM_P)pstr));\n    else invalidate();\n\n    return *this;\n}\n\n// /*********************************************/\n// /*  concat                                   */\n// /*********************************************/\n\nunsigned char String::concat(const String &s) {\n    // Special case if we're concatting ourself (s += s;) since we may end up\n    // realloc'ing the buffer and moving s.buffer in the method called\n    if (&s == this) {\n        unsigned int newlen = 2 * len();\n        if (!s.buffer())\n            return 0;\n        if (s.len() == 0)\n            return 1;\n        if (!reserve(newlen))\n            return 0;\n        memmove(wbuffer() + len(), buffer(), len());\n        setLen(newlen);\n        wbuffer()[len()] = 0;\n        return 1;\n    } else {\n        return concat(s.buffer(), s.len());\n    }\n}\n\nunsigned char String::concat(const char *cstr, unsigned int length) {\n    unsigned int newlen = len() + length;\n    if(!cstr)\n        return 0;\n    if(length == 0)\n        return 1;\n    if(!reserve(newlen))\n        return 0;\n    if (cstr >= wbuffer() && cstr < wbuffer() + len())\n        // compatible with SSO in ram #6155 (case \"x += x.c_str()\")\n        memmove(wbuffer() + len(), cstr, length + 1);\n    else\n        // compatible with source in flash #6367\n        memcpy_P(wbuffer() + len(), cstr, length + 1);\n    setLen(newlen);\n    return 1;\n}\n\nunsigned char String::concat(const char *cstr) {\n    if(!cstr)\n        return 0;\n    return concat(cstr, strlen(cstr));\n}\n\nunsigned char String::concat(char c) {\n    char buf[2];\n    buf[0] = c;\n    buf[1] = 0;\n    return concat(buf, 1);\n}\n\nunsigned char String::concat(unsigned char num) {\n    char buf[1 + 3 * sizeof(unsigned char)];\n    sprintf(buf, \"%d\", num);\n    return concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(int num) {\n    char buf[2 + 3 * sizeof(int)];\n    sprintf(buf, \"%d\", num);\n    return concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(unsigned int num) {\n    char buf[1 + 3 * sizeof(unsigned int)];\n    utoa(num, buf, 10);\n    return concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(long num) {\n    char buf[2 + 3 * sizeof(long)];\n    sprintf(buf, \"%ld\", num);\n    return concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(unsigned long num) {\n    char buf[1 + 3 * sizeof(unsigned long)];\n    ultoa(num, buf, 10);\n    return concat(buf, strlen(buf));\n}\n\nunsigned char String::concat(float num) {\n    char buf[20];\n    char* string = dtostrf(num, 4, 2, buf);\n    return concat(string, strlen(string));\n}\n\nunsigned char String::concat(double num) {\n    char buf[20];\n    char* string = dtostrf(num, 4, 2, buf);\n    return concat(string, strlen(string));\n}\n\nunsigned char String::concat(const __FlashStringHelper * str) {\n    if (!str) return 0;\n    int length = strlen_P((PGM_P)str);\n    if (length == 0) return 1;\n    unsigned int newlen = len() + length;\n    if (!reserve(newlen)) return 0;\n    memcpy_P(wbuffer() + len(), (PGM_P)str, length + 1);\n    setLen(newlen);\n    return 1;\n}\n\n/*********************************************/\n/*  Concatenate                              */\n/*********************************************/\n\nStringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(rhs.buffer(), rhs.len()))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!cstr || !a.concat(cstr, strlen(cstr)))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, char c) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(c))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, int num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, long num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, float num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator +(const StringSumHelper &lhs, double num) {\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if(!a.concat(num))\n        a.invalidate();\n    return a;\n}\n\nStringSumHelper & operator + (const StringSumHelper &lhs, const __FlashStringHelper *rhs)\n{\n    StringSumHelper &a = const_cast<StringSumHelper&>(lhs);\n    if (!a.concat(rhs))\n        a.invalidate();\n    return a;\n}\n\n// /*********************************************/\n// /*  Comparison                               */\n// /*********************************************/\n\nint String::compareTo(const String &s) const {\n    if(!buffer() || !s.buffer()) {\n        if(s.buffer() && s.len() > 0)\n            return 0 - *(unsigned char *) s.buffer();\n        if(buffer() && len() > 0)\n            return *(unsigned char *) buffer();\n        return 0;\n    }\n    return strcmp(buffer(), s.buffer());\n}\n\nunsigned char String::equals(const String &s2) const {\n    return (len() == s2.len() && compareTo(s2) == 0);\n}\n\nunsigned char String::equals(const char *cstr) const {\n    if(len() == 0)\n        return (cstr == NULL || *cstr == 0);\n    if(cstr == NULL)\n        return buffer()[0] == 0;\n    return strcmp(buffer(), cstr) == 0;\n}\n\nunsigned char String::operator<(const String &rhs) const {\n    return compareTo(rhs) < 0;\n}\n\nunsigned char String::operator>(const String &rhs) const {\n    return compareTo(rhs) > 0;\n}\n\nunsigned char String::operator<=(const String &rhs) const {\n    return compareTo(rhs) <= 0;\n}\n\nunsigned char String::operator>=(const String &rhs) const {\n    return compareTo(rhs) >= 0;\n}\n\nunsigned char String::equalsIgnoreCase(const String &s2) const {\n    if(this == &s2)\n        return 1;\n    if(len() != s2.len())\n        return 0;\n    if(len() == 0)\n        return 1;\n    const char *p1 = buffer();\n    const char *p2 = s2.buffer();\n    while(*p1) {\n        if(tolower(*p1++) != tolower(*p2++))\n            return 0;\n    }\n    return 1;\n}\n\nunsigned char String::equalsConstantTime(const String &s2) const {\n    // To avoid possible time-based attacks present function\n    // compares given strings in a constant time.\n    if(len() != s2.len())\n        return 0;\n    //at this point lengths are the same\n    if(len() == 0)\n        return 1;\n    //at this point lenghts are the same and non-zero\n    const char *p1 = buffer();\n    const char *p2 = s2.buffer();\n    unsigned int equalchars = 0;\n    unsigned int diffchars = 0;\n    while(*p1) {\n        if(*p1 == *p2)\n            ++equalchars;\n        else\n            ++diffchars;\n        ++p1;\n        ++p2;\n    }\n    //the following should force a constant time eval of the condition without a compiler \"logical shortcut\"\n    unsigned char equalcond = (equalchars == len());\n    unsigned char diffcond = (diffchars == 0);\n    return (equalcond & diffcond); //bitwise AND\n}\n\nunsigned char String::startsWith(const String &s2) const {\n    if(len() < s2.len())\n        return 0;\n    return startsWith(s2, 0);\n}\n\nunsigned char String::startsWith(const String &s2, unsigned int offset) const {\n    if(offset > (unsigned)(len() - s2.len()) || !buffer() || !s2.buffer())\n        return 0;\n    return strncmp(&buffer()[offset], s2.buffer(), s2.len()) == 0;\n}\n\nunsigned char String::endsWith(const String &s2) const {\n    if(len() < s2.len() || !buffer() || !s2.buffer())\n        return 0;\n    return strcmp(&buffer()[len() - s2.len()], s2.buffer()) == 0;\n}\n\n// /*********************************************/\n// /*  Character Access                         */\n// /*********************************************/\n\nchar String::charAt(unsigned int loc) const {\n    return operator[](loc);\n}\n\nvoid String::setCharAt(unsigned int loc, char c) {\n    if(loc < len())\n        wbuffer()[loc] = c;\n}\n\nchar & String::operator[](unsigned int index) {\n    static char dummy_writable_char;\n    if(index >= len() || !buffer()) {\n        dummy_writable_char = 0;\n        return dummy_writable_char;\n    }\n    return wbuffer()[index];\n}\n\nchar String::operator[](unsigned int index) const {\n    if(index >= len() || !buffer())\n        return 0;\n    return buffer()[index];\n}\n\nvoid String::getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index) const {\n    if(!bufsize || !buf)\n        return;\n    if(index >= len()) {\n        buf[0] = 0;\n        return;\n    }\n    unsigned int n = bufsize - 1;\n    if(n > len() - index)\n        n = len() - index;\n    strncpy((char *) buf, buffer() + index, n);\n    buf[n] = 0;\n}\n\n// /*********************************************/\n// /*  Search                                   */\n// /*********************************************/\n\nint String::indexOf(char c) const {\n    return indexOf(c, 0);\n}\n\nint String::indexOf(char ch, unsigned int fromIndex) const {\n    if(fromIndex >= len())\n        return -1;\n    const char* temp = strchr(buffer() + fromIndex, ch);\n    if(temp == NULL)\n        return -1;\n    return temp - buffer();\n}\n\nint String::indexOf(const String &s2) const {\n    return indexOf(s2, 0);\n}\n\nint String::indexOf(const String &s2, unsigned int fromIndex) const {\n    if(fromIndex >= len())\n        return -1;\n    const char *found = strstr(buffer() + fromIndex, s2.buffer());\n    if(found == NULL)\n        return -1;\n    return found - buffer();\n}\n\nint String::lastIndexOf(char theChar) const {\n    return lastIndexOf(theChar, len() - 1);\n}\n\nint String::lastIndexOf(char ch, unsigned int fromIndex) const {\n    if(fromIndex >= len())\n        return -1;\n    char tempchar = buffer()[fromIndex + 1];\n    wbuffer()[fromIndex + 1] = '\\0';\n    char* temp = strrchr(wbuffer(), ch);\n    wbuffer()[fromIndex + 1] = tempchar;\n    if(temp == NULL)\n        return -1;\n    return temp - buffer();\n}\n\nint String::lastIndexOf(const String &s2) const {\n    return lastIndexOf(s2, len() - s2.len());\n}\n\nint String::lastIndexOf(const String &s2, unsigned int fromIndex) const {\n    if(s2.len() == 0 || len() == 0 || s2.len() > len())\n        return -1;\n    if(fromIndex >= len())\n        fromIndex = len() - 1;\n    int found = -1;\n    for(char *p = wbuffer(); p <= wbuffer() + fromIndex; p++) {\n        p = strstr(p, s2.buffer());\n        if(!p)\n            break;\n        if((unsigned int) (p - wbuffer()) <= fromIndex)\n            found = p - buffer();\n    }\n    return found;\n}\n\nString String::substring(unsigned int left, unsigned int right) const {\n    if(left > right) {\n        unsigned int temp = right;\n        right = left;\n        left = temp;\n    }\n    String out;\n    if(left >= len())\n        return out;\n    if(right > len())\n        right = len();\n    char temp = buffer()[right];  // save the replaced character\n    wbuffer()[right] = '\\0';\n    out = wbuffer() + left;  // pointer arithmetic\n    wbuffer()[right] = temp;  //restore character\n    return out;\n}\n\n// /*********************************************/\n// /*  Modification                             */\n// /*********************************************/\n\nvoid String::replace(char find, char replace) {\n    if(!buffer())\n        return;\n    for(char *p = wbuffer(); *p; p++) {\n        if(*p == find)\n            *p = replace;\n    }\n}\n\nvoid String::replace(const String& find, const String& replace) {\n    if(len() == 0 || find.len() == 0)\n        return;\n    int diff = replace.len() - find.len();\n    char *readFrom = wbuffer();\n    char *foundAt;\n    if(diff == 0) {\n        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {\n            memmove(foundAt, replace.buffer(), replace.len());\n            readFrom = foundAt + replace.len();\n        }\n    } else if(diff < 0) {\n        char *writeTo = wbuffer();\n        unsigned int l = len();\n        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {\n            unsigned int n = foundAt - readFrom;\n            memmove(writeTo, readFrom, n);\n            writeTo += n;\n            memmove(writeTo, replace.buffer(), replace.len());\n            writeTo += replace.len();\n            readFrom = foundAt + find.len();\n            l += diff;\n        }\n        memmove(writeTo, readFrom, strlen(readFrom)+1);\n        setLen(l);\n    } else {\n        unsigned int size = len(); // compute size needed for result\n        while((foundAt = strstr(readFrom, find.buffer())) != NULL) {\n            readFrom = foundAt + find.len();\n            size += diff;\n        }\n        if(size == len())\n            return;\n        if(size > capacity() && !changeBuffer(size))\n            return; // XXX: tell user!\n        int index = len() - 1;\n        while(index >= 0 && (index = lastIndexOf(find, index)) >= 0) {\n            readFrom = wbuffer() + index + find.len();\n            memmove(readFrom + diff, readFrom, len() - (readFrom - buffer()));\n            int newLen = len() + diff;\n            memmove(wbuffer() + index, replace.buffer(), replace.len());\n            setLen(newLen);\n            wbuffer()[newLen] = 0;\n            index--;\n        }\n    }\n}\n\nvoid String::remove(unsigned int index) {\n    // Pass the biggest integer as the count. The remove method\n    // below will take care of truncating it at the end of the\n    // string.\n    remove(index, (unsigned int) -1);\n}\n\nvoid String::remove(unsigned int index, unsigned int count) {\n    if(index >= len()) {\n        return;\n    }\n    if(count <= 0) {\n        return;\n    }\n    if(count > len() - index) {\n        count = len() - index;\n    }\n    char *writeTo = wbuffer() + index;\n    unsigned int newlen = len() - count;\n    memmove(writeTo, wbuffer() + index + count, newlen - index);\n    setLen(newlen);\n    wbuffer()[newlen] = 0;\n}\n\nvoid String::toLowerCase(void) {\n    if(!buffer())\n        return;\n    for(char *p = wbuffer(); *p; p++) {\n        *p = tolower(*p);\n    }\n}\n\nvoid String::toUpperCase(void) {\n    if(!buffer())\n        return;\n    for(char *p = wbuffer(); *p; p++) {\n        *p = toupper(*p);\n    }\n}\n\nvoid String::trim(void) {\n    if(!buffer() || len() == 0)\n        return;\n    char *begin = wbuffer();\n    while(isspace(*begin))\n        begin++;\n    char *end = wbuffer() + len() - 1;\n    while(isspace(*end) && end >= begin)\n        end--;\n    unsigned int newlen = end + 1 - begin;\n    if(begin > buffer())\n        memmove(wbuffer(), begin, newlen);\n    setLen(newlen);\n    wbuffer()[newlen] = 0;\n}\n\n// /*********************************************/\n// /*  Parsing / Conversion                     */\n// /*********************************************/\n\nlong String::toInt(void) const {\n    if (buffer())\n        return atol(buffer());\n    return 0;\n}\n\nfloat String::toFloat(void) const {\n    if (buffer())\n        return atof(buffer());\n    return 0;\n}\n\ndouble String::toDouble(void) const\n{\n    if (buffer())\n        return atof(buffer());\n    return 0.0;\n}\n\n// global empty string to allow returning const String& with nothing\n\nconst String emptyString;\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/WString.h",
    "content": "/*\n WString.h - String library for Wiring & Arduino\n ...mostly rewritten by Paul Stoffregen...\n Copyright (c) 2009-10 Hernando Barragan.  All right reserved.\n Copyright 2011, Paul Stoffregen, paul@pjrc.com\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n */\n\n#ifndef String_class_h\n#define String_class_h\n#ifdef __cplusplus\n\n#include <stdlib.h>\n#include <string.h>\n#include <ctype.h>\n#include <stdint.h>\n\n// An inherited class for holding the result of a concatenation.  These\n// result objects are assumed to be writable by subsequent concatenations.\nclass StringSumHelper;\n\n// an abstract class used as a means to proide a unique pointer type\n// but really has no body\nclass __FlashStringHelper;\n#define FPSTR(pstr_pointer) (reinterpret_cast<const __FlashStringHelper *>(pstr_pointer))\n#define F(string_literal) (FPSTR(PSTR(string_literal)))\n\n// The string class\nclass String {\n        // use a function pointer to allow for \"if (s)\" without the\n        // complications of an operator bool(). for more information, see:\n        // http://www.artima.com/cppsource/safebool.html\n        typedef void (String::*StringIfHelperType)() const;\n        void StringIfHelper() const {\n        }\n\n    public:\n        // constructors\n        // creates a copy of the initial value.\n        // if the initial value is null or invalid, or if memory allocation\n        // fails, the string will be marked as invalid (i.e. \"if (s)\" will\n        // be false).\n        String(const char *cstr = \"\");\n        String(const String &str);\n        String(const __FlashStringHelper *str);\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\n        String(String &&rval);\n        String(StringSumHelper &&rval);\n#endif\n        explicit String(char c);\n        explicit String(unsigned char, unsigned char base = 10);\n        explicit String(int, unsigned char base = 10);\n        explicit String(unsigned int, unsigned char base = 10);\n        explicit String(long, unsigned char base = 10);\n        explicit String(unsigned long, unsigned char base = 10);\n        explicit String(float, unsigned char decimalPlaces = 2);\n        explicit String(double, unsigned char decimalPlaces = 2);\n        ~String(void);\n\n        // memory management\n        // return true on success, false on failure (in which case, the string\n        // is left unchanged).  reserve(0), if successful, will validate an\n        // invalid string (i.e., \"if (s)\" will be true afterwards)\n        unsigned char reserve(unsigned int size);\n        inline unsigned int length(void) const {\n            if(buffer()) {\n                return len();\n            } else {\n                return 0;\n            }\n        }\n        inline void clear(void) {\n            setLen(0);\n        }\n        inline bool isEmpty(void) const {\n            return length() == 0;\n        }\n\n        // creates a copy of the assigned value.  if the value is null or\n        // invalid, or if the memory allocation fails, the string will be\n        // marked as invalid (\"if (s)\" will be false).\n        String & operator =(const String &rhs);\n        String & operator =(const char *cstr);\n        String & operator = (const __FlashStringHelper *str);\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\n        String & operator =(String &&rval);\n        String & operator =(StringSumHelper &&rval);\n#endif\n\n        // concatenate (works w/ built-in types)\n\n        // returns true on success, false on failure (in which case, the string\n        // is left unchanged).  if the argument is null or invalid, the\n        // concatenation is considered unsuccessful.\n        unsigned char concat(const String &str);\n        unsigned char concat(const char *cstr);\n        unsigned char concat(char c);\n        unsigned char concat(unsigned char c);\n        unsigned char concat(int num);\n        unsigned char concat(unsigned int num);\n        unsigned char concat(long num);\n        unsigned char concat(unsigned long num);\n        unsigned char concat(float num);\n        unsigned char concat(double num);\n        unsigned char concat(const __FlashStringHelper * str);\n\n        // if there's not enough memory for the concatenated value, the string\n        // will be left unchanged (but this isn't signalled in any way)\n        String & operator +=(const String &rhs) {\n            concat(rhs);\n            return (*this);\n        }\n        String & operator +=(const char *cstr) {\n            concat(cstr);\n            return (*this);\n        }\n        String & operator +=(char c) {\n            concat(c);\n            return (*this);\n        }\n        String & operator +=(unsigned char num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(int num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(unsigned int num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(long num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(unsigned long num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(float num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator +=(double num) {\n            concat(num);\n            return (*this);\n        }\n        String & operator += (const __FlashStringHelper *str){\n            concat(str);\n            return (*this);\n        }\n\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, const String &rhs);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, const char *cstr);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, char c);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned char num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, int num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned int num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, long num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, unsigned long num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, float num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, double num);\n        friend StringSumHelper & operator +(const StringSumHelper &lhs, const __FlashStringHelper *rhs);\n\n        // comparison (only works w/ Strings and \"strings\")\n        operator StringIfHelperType() const {\n            return buffer() ? &String::StringIfHelper : 0;\n        }\n        int compareTo(const String &s) const;\n        unsigned char equals(const String &s) const;\n        unsigned char equals(const char *cstr) const;\n        unsigned char operator ==(const String &rhs) const {\n            return equals(rhs);\n        }\n        unsigned char operator ==(const char *cstr) const {\n            return equals(cstr);\n        }\n        unsigned char operator !=(const String &rhs) const {\n            return !equals(rhs);\n        }\n        unsigned char operator !=(const char *cstr) const {\n            return !equals(cstr);\n        }\n        unsigned char operator <(const String &rhs) const;\n        unsigned char operator >(const String &rhs) const;\n        unsigned char operator <=(const String &rhs) const;\n        unsigned char operator >=(const String &rhs) const;\n        unsigned char equalsIgnoreCase(const String &s) const;\n        unsigned char equalsConstantTime(const String &s) const;\n        unsigned char startsWith(const String &prefix) const;\n        unsigned char startsWith(const char *prefix) const {\n            return this->startsWith(String(prefix));\n        }\n        unsigned char startsWith(const __FlashStringHelper *prefix) const {\n            return this->startsWith(String(prefix));\n        }\n        unsigned char startsWith(const String &prefix, unsigned int offset) const;\n        unsigned char endsWith(const String &suffix) const;\n        unsigned char endsWith(const char *suffix) const {\n            return this->endsWith(String(suffix));\n        }\n        unsigned char endsWith(const __FlashStringHelper * suffix) const {\n            return this->endsWith(String(suffix));\n        }\n\n        // character access\n        char charAt(unsigned int index) const;\n        void setCharAt(unsigned int index, char c);\n        char operator [](unsigned int index) const;\n        char& operator [](unsigned int index);\n        void getBytes(unsigned char *buf, unsigned int bufsize, unsigned int index = 0) const;\n        void toCharArray(char *buf, unsigned int bufsize, unsigned int index = 0) const {\n            getBytes((unsigned char *) buf, bufsize, index);\n        }\n        const char* c_str() const { return buffer(); }\n        char* begin() { return wbuffer(); }\n        char* end() { return wbuffer() + length(); }\n        const char* begin() const { return c_str(); }\n        const char* end() const { return c_str() + length(); }\n\n        // search\n        int indexOf(char ch) const;\n        int indexOf(char ch, unsigned int fromIndex) const;\n        int indexOf(const String &str) const;\n        int indexOf(const String &str, unsigned int fromIndex) const;\n        int lastIndexOf(char ch) const;\n        int lastIndexOf(char ch, unsigned int fromIndex) const;\n        int lastIndexOf(const String &str) const;\n        int lastIndexOf(const String &str, unsigned int fromIndex) const;\n        String substring(unsigned int beginIndex) const {\n            return substring(beginIndex, len());\n        }\n        ;\n        String substring(unsigned int beginIndex, unsigned int endIndex) const;\n\n        // modification\n        void replace(char find, char replace);\n        void replace(const String &find, const String &replace);\n        void replace(const char *find, const String &replace) {\n            this->replace(String(find), replace);\n        }\n        void replace(const __FlashStringHelper *find, const String &replace) {\n            this->replace(String(find), replace);\n        }\n        void replace(const char *find, const char *replace) {\n            this->replace(String(find), String(replace));\n        }\n        void replace(const __FlashStringHelper *find, const char *replace) {\n            this->replace(String(find), String(replace));\n        }\n        void replace(const __FlashStringHelper *find, const __FlashStringHelper *replace) {\n            this->replace(String(find), String(replace));\n        }\n        void remove(unsigned int index);\n        void remove(unsigned int index, unsigned int count);\n        void toLowerCase(void);\n        void toUpperCase(void);\n        void trim(void);\n\n        // parsing/conversion\n        long toInt(void) const;\n        float toFloat(void) const;\n\tdouble toDouble(void) const;\n\n    protected:\n        // Contains the string info when we're not in SSO mode\n        struct _ptr { \n            char *   buff;\n            uint16_t cap;\n            uint16_t len;\n        };\n        // This allows strings up up to 11 (10 + \\0 termination) without any extra space.\n        enum { SSOSIZE = sizeof(struct _ptr) + 4 - 1 }; // Characters to allocate space for SSO, must be 12 or more\n        struct _sso {\n            char     buff[SSOSIZE];\n            unsigned char len   : 7; // Ensure only one byte is allocated by GCC for the bitfields\n            unsigned char isSSO : 1;\n        } __attribute__((packed)); // Ensure that GCC doesn't expand the flag byte to a 32-bit word for alignment issues\n        enum { CAPACITY_MAX = 65535 }; // If typeof(cap) changed from uint16_t, be sure to update this enum to the max value storable in the type\n        union {\n            struct _ptr ptr;\n            struct _sso sso;\n        };\n        // Accessor functions\n        inline bool isSSO() const { return sso.isSSO; }\n        inline unsigned int len() const { return isSSO() ? sso.len : ptr.len; }\n        inline unsigned int capacity() const { return isSSO() ? (unsigned int)SSOSIZE - 1 : ptr.cap; } // Size of max string not including terminal NUL\n        inline void setSSO(bool set) { sso.isSSO = set; }\n        inline void setLen(int len) {\n            if (isSSO()) {\n                sso.len = len;\n                sso.buff[len] = 0;\n            } else {\n                ptr.len = len;\n                if (ptr.buff) {\n                    ptr.buff[len] = 0;\n                }\n            }\n        }\n        inline void setCapacity(int cap) { if (!isSSO()) ptr.cap = cap; }\n        inline void setBuffer(char *buff) { if (!isSSO()) ptr.buff = buff; }\n        // Buffer accessor functions\n        inline const char *buffer() const { return (const char *)(isSSO() ? sso.buff : ptr.buff); }\n        inline char *wbuffer() const { return isSSO() ? const_cast<char *>(sso.buff) : ptr.buff; } // Writable version of buffer\n\n    protected:\n        void init(void);\n        void invalidate(void);\n        unsigned char changeBuffer(unsigned int maxStrLen);\n        unsigned char concat(const char *cstr, unsigned int length);\n\n        // copy and move\n        String & copy(const char *cstr, unsigned int length);\n        String & copy(const __FlashStringHelper *pstr, unsigned int length);\n#ifdef __GXX_EXPERIMENTAL_CXX0X__\n        void move(String &rhs);\n#endif\n};\n\nclass StringSumHelper: public String {\n    public:\n        StringSumHelper(const String &s) :\n                String(s) {\n        }\n        StringSumHelper(const char *p) :\n                String(p) {\n        }\n        StringSumHelper(char c) :\n                String(c) {\n        }\n        StringSumHelper(unsigned char num) :\n                String(num) {\n        }\n        StringSumHelper(int num) :\n                String(num) {\n        }\n        StringSumHelper(unsigned int num) :\n                String(num) {\n        }\n        StringSumHelper(long num) :\n                String(num) {\n        }\n        StringSumHelper(unsigned long num) :\n                String(num) {\n        }\n        StringSumHelper(float num) :\n                String(num) {\n        }\n        StringSumHelper(double num) :\n                String(num) {\n        }\n};\n\nextern const String emptyString;\n\n#endif  // __cplusplus\n#endif  // String_class_h\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/pgmspace.h",
    "content": "/* \n  Copyright (c) 2015 Hristo Gochkov. All rights reserved.\n  This file is part of the RaspberryPi core for Arduino environment.\n \n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n#ifndef PGMSPACE_INCLUDE\n#define PGMSPACE_INCLUDE\n\ntypedef void prog_void;\ntypedef char prog_char;\ntypedef unsigned char prog_uchar;\ntypedef char prog_int8_t;\ntypedef unsigned char prog_uint8_t;\ntypedef short prog_int16_t;\ntypedef unsigned short prog_uint16_t;\ntypedef long prog_int32_t;\ntypedef unsigned long prog_uint32_t;\n\n#define PROGMEM\n#define PGM_P         const char *\n#define PGM_VOID_P    const void *\n#define PSTR(s)       (s)\n#define _SFR_BYTE(n)  (n)\n\n#define pgm_read_byte(addr)   (*(const unsigned char *)(addr))\n#define pgm_read_word(addr) ({ \\\n  typeof(addr) _addr = (addr); \\\n  *(const unsigned short *)(_addr); \\\n})\n#define pgm_read_dword(addr) ({ \\\n  typeof(addr) _addr = (addr); \\\n  *(const unsigned long *)(_addr); \\\n})\n#define pgm_read_float(addr) ({ \\\n  typeof(addr) _addr = (addr); \\\n  *(const float *)(_addr); \\\n})\n#define pgm_read_ptr(addr) ({ \\\n  typeof(addr) _addr = (addr); \\\n  *(void * const *)(_addr); \\\n})\n\n#define pgm_get_far_address(x) ((uint32_t)(&(x)))\n\n#define pgm_read_byte_near(addr)  pgm_read_byte(addr)\n#define pgm_read_word_near(addr)  pgm_read_word(addr)\n#define pgm_read_dword_near(addr) pgm_read_dword(addr)\n#define pgm_read_float_near(addr) pgm_read_float(addr)\n#define pgm_read_ptr_near(addr)   pgm_read_ptr(addr)\n#define pgm_read_byte_far(addr)   pgm_read_byte(addr)\n#define pgm_read_word_far(addr)   pgm_read_word(addr)\n#define pgm_read_dword_far(addr)  pgm_read_dword(addr)\n#define pgm_read_float_far(addr)  pgm_read_float(addr)\n#define pgm_read_ptr_far(addr)    pgm_read_ptr(addr)\n\n#define memcmp_P      memcmp\n#define memccpy_P     memccpy\n#define memmem_P      memmem\n#define memcpy_P      memcpy\n#define strcpy_P      strcpy\n#define strncpy_P     strncpy\n#define strcat_P      strcat\n#define strncat_P     strncat\n#define strcmp_P      strcmp\n#define strncmp_P     strncmp\n#define strcasecmp_P  strcasecmp\n#define strncasecmp_P strncasecmp\n#define strlen_P      strlen\n#define strnlen_P     strnlen\n#define strstr_P      strstr\n#define printf_P      printf\n#define sprintf_P     sprintf\n#define snprintf_P    snprintf\n#define vsnprintf_P   vsnprintf\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/stdlib_noniso.c",
    "content": "/*\n core_esp8266_noniso.c - nonstandard (but usefull) conversion functions\n\n Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.\n This file is part of the esp8266 core for Arduino environment.\n\n This library is free software; you can redistribute it and/or\n modify it under the terms of the GNU Lesser General Public\n License as published by the Free Software Foundation; either\n version 2.1 of the License, or (at your option) any later version.\n\n This library is distributed in the hope that it will be useful,\n but WITHOUT ANY WARRANTY; without even the implied warranty of\n MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n Lesser General Public License for more details.\n\n You should have received a copy of the GNU Lesser General Public\n License along with this library; if not, write to the Free Software\n Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n\n Modified 03 April 2015 by Markus Sattler\n\n */\n\n#include <stdlib.h>\n#include <string.h>\n#include <stdbool.h>\n#include <stdint.h>\n#include <math.h>\n#include \"stdlib_noniso.h\"\n\nvoid reverse(char* begin, char* end) {\n    char *is = begin;\n    char *ie = end - 1;\n    while(is < ie) {\n        char tmp = *ie;\n        *ie = *is;\n        *is = tmp;\n        ++is;\n        --ie;\n    }\n}\n\nchar* ltoa(long value, char* result, int base) {\n    if(base < 2 || base > 16) {\n        *result = 0;\n        return result;\n    }\n\n    char* out = result;\n    long quotient = abs(value);\n\n    do {\n        const long tmp = quotient / base;\n        *out = \"0123456789abcdef\"[quotient - (tmp * base)];\n        ++out;\n        quotient = tmp;\n    } while(quotient);\n\n    // Apply negative sign\n    if(value < 0)\n        *out++ = '-';\n\n    reverse(result, out);\n    *out = 0;\n    return result;\n}\n\nchar* ultoa(unsigned long value, char* result, int base) {\n    if(base < 2 || base > 16) {\n        *result = 0;\n        return result;\n    }\n\n    char* out = result;\n    unsigned long quotient = value;\n\n    do {\n        const unsigned long tmp = quotient / base;\n        *out = \"0123456789abcdef\"[quotient - (tmp * base)];\n        ++out;\n        quotient = tmp;\n    } while(quotient);\n\n    reverse(result, out);\n    *out = 0;\n    return result;\n}\n\nchar * dtostrf(double number, signed char width, unsigned char prec, char *s) {\n    bool negative = false;\n\n    if (isnan(number)) {\n        strcpy(s, \"nan\");\n        return s;\n    }\n    if (isinf(number)) {\n        strcpy(s, \"inf\");\n        return s;\n    }\n\n    char* out = s;\n\n    int fillme = width; // how many cells to fill for the integer part\n    if (prec > 0) {\n        fillme -= (prec+1);\n    }\n\n    // Handle negative numbers\n    if (number < 0.0) {\n        negative = true;\n        fillme--;\n        number = -number;\n    }\n\n    // Round correctly so that print(1.999, 2) prints as \"2.00\"\n    // I optimized out most of the divisions\n    double rounding = 2.0;\n    for (uint8_t i = 0; i < prec; ++i)\n        rounding *= 10.0;\n    rounding = 1.0 / rounding;\n\n    number += rounding;\n\n    // Figure out how big our number really is\n    double tenpow = 1.0;\n    int digitcount = 1;\n    while (number >= 10.0 * tenpow) {\n        tenpow *= 10.0;\n        digitcount++;\n    }\n\n    number /= tenpow;\n    fillme -= digitcount;\n\n    // Pad unused cells with spaces\n    while (fillme-- > 0) {\n        *out++ = ' ';\n    }\n\n    // Handle negative sign\n    if (negative) *out++ = '-';\n\n    // Print the digits, and if necessary, the decimal point\n    digitcount += prec;\n    int8_t digit = 0;\n    while (digitcount-- > 0) {\n        digit = (int8_t)number;\n        if (digit > 9) digit = 9; // insurance\n        *out++ = (char)('0' | digit);\n        if ((digitcount == prec) && (prec > 0)) {\n            *out++ = '.';\n        }\n        number -= digit;\n        number *= 10.0;\n    }\n\n    // make sure the string is terminated\n    *out = 0;\n    return s;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/cpp/stdlib_noniso.h",
    "content": "/*\n  stdlib_noniso.h - nonstandard (but usefull) conversion functions\n\n  Copyright (c) 2014 Ivan Grokhotkov. All rights reserved.\n\n  This library is free software; you can redistribute it and/or\n  modify it under the terms of the GNU Lesser General Public\n  License as published by the Free Software Foundation; either\n  version 2.1 of the License, or (at your option) any later version.\n\n  This library is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU\n  Lesser General Public License for more details.\n\n  You should have received a copy of the GNU Lesser General Public\n  License along with this library; if not, write to the Free Software\n  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA\n*/\n\n#ifndef STDLIB_NONISO_H\n#define STDLIB_NONISO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nint atoi(const char *s);\n\nlong atol(const char* s);\n\ndouble atof(const char* s);\n\nchar* itoa (int val, char *s, int radix);\n\nchar* ltoa (long val, char *s, int radix);\n\nchar* utoa (unsigned int val, char *s, int radix);\n\nchar* ultoa (unsigned long val, char *s, int radix);\n\nchar* dtostrf (double val, signed char width, unsigned char prec, char *s);\n\n#ifdef __cplusplus\n} // extern \"C\"\n#endif\n\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2.h",
    "content": "/*\n\n  u8g2.h\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  call sequence\n  \n  u8g2_SetupBuffer_XYZ\n    u8x8_Setup_XYZ\n      u8x8_SetupDefaults(u8g2);\n      assign u8x8 callbacks\n      u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SETUP_MEMORY, 0, NULL);  \n    setup tile buffer\n    \n  \n  Arduino Uno Text Example\n>\tFONT_ROTATION\tINTERSECTION\tCLIPPING\ttext\t   \tdata\t\tbss\t\tdec\t\thex\t\n>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t8700\n>\tx\t\t\t\tx\t\t\t\tx\t\t\t7450\t104\t\t1116\t8670\t21de\n>\t-\t\t\t\tx\t\t\t\tx\t\t\t7132\t104\t\t1115\t8351\t209f\n>\tx\t\t\t\t-\t\t\t\tx\t\t\t7230\t104\t\t1116\t8450\t2102\n>\t-\t\t\t\t-\t\t\t\tx\t\t\t7010\t104\t\t1115\t8229\t2025\n>\t-\t\t\t\t-\t\t\t\t-\t\t\t6880\t104\t\t1115\t8099\t1fa3\n  \n  \n*/\n\n\n#ifndef U8G2_H\n#define U8G2_H\n\n#include \"u8x8.h\"\n\n/*\n  The following macro enables 16 Bit mode. \n  Without defining this macro all calulations are done with 8 Bit (1 Byte) variables.\n  Especially on AVR architecture, this will save some space. \n  If this macro is defined, then U8g2 will switch to 16 Bit mode.\n  Use 16 Bit mode for any display with more than 240 pixel in one \n  direction.\n*/\n//#define U8G2_16BIT\n\n\n/* always enable U8G2_16BIT on 32bit environments, see issue https://github.com/olikraus/u8g2/issues/1222 */\n#ifndef U8G2_16BIT\n#if defined(unix) || defined(__arm__) || defined(__xtensa__) || defined(xtensa) || defined(__arc__) || defined(ESP8266) || defined(ESP_PLATFORM)\n#define U8G2_16BIT\n#endif\n#endif\n\n/*\n  The following macro switches the library into dynamic display buffer allocation mode.\n  Defining this constant will disable all static memory allocation for device memory buffer and thus allows the user to allocate device buffers statically.\n  Before using any display functions, the dynamic buffer *must* be assigned to the u8g2 struct using the u8g2_SetBufferPtr function.\n  When using dynamic allocation, the stack size must be increased by u8g2_GetBufferSize bytes.\n */\n//#define U8G2_USE_DYNAMIC_ALLOC\n\n\n/* U8g2 feature selection, see also https://github.com/olikraus/u8g2/wiki/u8g2optimization */\n\n/*\n  The following macro enables the HVLine speed optimization.\n  It will consume about 40 bytes more in flash memory of the AVR.\n  HVLine procedures are also used by the text drawing functions.\n*/\n#define U8G2_WITH_HVLINE_SPEED_OPTIMIZATION\n\n/*\n  The following macro activates the early intersection check with the current visible area.\n  Clipping (and low level intersection calculation) will still happen and is controlled by U8G2_WITH_CLIPPING.\n  This early intersection check only improves speed for the picture loop (u8g2_FirstPage/NextPage).\n  With a full framebuffer in RAM and if most graphical elements are drawn within the visible area, then this\n  macro can be commented to reduce code size.\n*/\n#define U8G2_WITH_INTERSECTION\n\n\n/*\n  Enable clip window support:\n    void u8g2_SetMaxClipWindow(u8g2_t *u8g2)\n    void u8g2_SetClipWindow(u8g2_t *u8g2, u8g2_uint_t clip_x0, u8g2_uint_t clip_y0, u8g2_uint_t clip_x1, u8g2_uint_t clip_y1 )\n  Setting a clip window will restrict all drawing to this window.\n  Clip window support requires about 200 bytes flash memory on AVR systems\n*/\n#define U8G2_WITH_CLIP_WINDOW_SUPPORT\n\n/*\n  The following macro enables all four drawing directions for glyphs and strings.\n  If this macro is not defined, than a string can be drawn only in horizontal direction.\n  \n  Jan 2020: Disabling this macro will save up to 600 bytes on AVR \n*/\n#define U8G2_WITH_FONT_ROTATION\n\n/*\n  U8glib V2 contains support for unicode plane 0 (Basic Multilingual Plane, BMP).\n  The following macro activates this support. Deactivation would save some ROM.\n  This definition also defines the behavior of the expected string encoding.\n  If the following macro is defined, then the DrawUTF8 function is enabled and \n  the string argument for this function is assumed \n  to be UTF-8 encoded.\n  If the following macro is not defined, then all strings in the c-code are assumed \n  to be ISO 8859-1/CP1252 encoded. \n  Independently from this macro, the Arduino print function never accepts UTF-8\n  strings.\n  \n  This macro does not affect the u8x8 string draw function.\n  u8x8 has also two function, one for pure strings and one for UTF8\n  \n  Conclusion:\n    U8G2_WITH_UNICODE defined\n      - C-Code Strings must be UTF-8 encoded\n      - Full support of all 65536 glyphs of the unicode basic multilingual plane\n      - Up to 65536 glyphs of the font file can be used.\n    U8G2_WITH_UNICODE not defined\n      - C-Code Strings are assumbed to be ISO 8859-1/CP1252 encoded\n      - Only character values 0 to 255 are supported in the font file.\n*/\n#define U8G2_WITH_UNICODE\n\n\n\n\n/*==========================================*/\n\n\n#ifdef __GNUC__\n#  define U8G2_NOINLINE __attribute__((noinline))\n#else\n#  define U8G2_NOINLINE\n#endif\n\n#define U8G2_FONT_SECTION(name) U8X8_FONT_SECTION(name) \n\n\n/* the macro U8G2_USE_LARGE_FONTS enables large fonts (>32K) */\n/* it can be enabled for those uC supporting larger arrays */\n#if defined(unix) || defined(__arm__) || defined(__arc__) || defined(ESP8266) || defined(ESP_PLATFORM)\n#ifndef U8G2_USE_LARGE_FONTS\n#define U8G2_USE_LARGE_FONTS\n#endif \n#endif\n\n/*==========================================*/\n/* C++ compatible */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*==========================================*/\n\n#ifdef U8G2_16BIT\ntypedef uint16_t u8g2_uint_t;\t/* for pixel position only */\ntypedef int16_t u8g2_int_t;\t\t/* introduced for circle calculation */\ntypedef int32_t u8g2_long_t;\t\t/* introduced for ellipse calculation */\n#else\ntypedef uint8_t u8g2_uint_t;\t\t/* for pixel position only */\ntypedef int8_t u8g2_int_t;\t\t/* introduced for circle calculation */\ntypedef int16_t u8g2_long_t;\t\t/* introduced for ellipse calculation */\n#endif\n\n\ntypedef struct u8g2_struct u8g2_t;\ntypedef struct u8g2_cb_struct u8g2_cb_t;\n\ntypedef void (*u8g2_update_dimension_cb)(u8g2_t *u8g2);\ntypedef void (*u8g2_update_page_win_cb)(u8g2_t *u8g2);\ntypedef void (*u8g2_draw_l90_cb)(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\ntypedef void (*u8g2_draw_ll_hvline_cb)(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n\ntypedef uint8_t (*u8g2_get_kerning_cb)(u8g2_t *u8g2, uint16_t e1, uint16_t e2);\n\n\n/* from ucglib... */\nstruct _u8g2_font_info_t\n{\n  /* offset 0 */\n  uint8_t glyph_cnt;\n  uint8_t bbx_mode;\n  uint8_t bits_per_0;\n  uint8_t bits_per_1;\n  \n  /* offset 4 */\n  uint8_t bits_per_char_width;\n  uint8_t bits_per_char_height;\t\t\n  uint8_t bits_per_char_x;\n  uint8_t bits_per_char_y;\n  uint8_t bits_per_delta_x;\n  \n  /* offset 9 */\n  int8_t max_char_width;\n  int8_t max_char_height; /* overall height, NOT ascent. Instead ascent = max_char_height + y_offset */\n  int8_t x_offset;\n  int8_t y_offset;\n  \n  /* offset 13 */\n  int8_t  ascent_A;\n  int8_t  descent_g;\t/* usually a negative value */\n  int8_t  ascent_para;\n  int8_t  descent_para;\n    \n  /* offset 17 */\n  uint16_t start_pos_upper_A;\n  uint16_t start_pos_lower_a; \n  \n  /* offset 21 */\n#ifdef U8G2_WITH_UNICODE  \n  uint16_t start_pos_unicode;\n#endif\n};\ntypedef struct _u8g2_font_info_t u8g2_font_info_t;\n\n/* from ucglib... */\nstruct _u8g2_font_decode_t\n{\n  const uint8_t *decode_ptr;\t\t\t/* pointer to the compressed data */\n  \n  u8g2_uint_t target_x;\n  u8g2_uint_t target_y;\n  \n  int8_t x;\t\t\t\t\t\t/* local coordinates, (0,0) is upper left */\n  int8_t y;\n  int8_t glyph_width;\t\n  int8_t glyph_height;\n\n  uint8_t decode_bit_pos;\t\t\t/* bitpos inside a byte of the compressed data */\n  uint8_t is_transparent;\n  uint8_t fg_color;\n  uint8_t bg_color;\n#ifdef U8G2_WITH_FONT_ROTATION  \n  uint8_t dir;\t\t\t\t/* direction */\n#endif\n};\ntypedef struct _u8g2_font_decode_t u8g2_font_decode_t;\n\nstruct _u8g2_kerning_t\n{\n  uint16_t first_table_cnt;\n  uint16_t second_table_cnt;\n  const uint16_t *first_encoding_table;  \n  const uint16_t *index_to_second_table;\n  const uint16_t *second_encoding_table;\n  const uint8_t *kerning_values;\n};\ntypedef struct _u8g2_kerning_t u8g2_kerning_t;\n\n\nstruct u8g2_cb_struct\n{\n  u8g2_update_dimension_cb update_dimension;\n  u8g2_update_page_win_cb update_page_win;\n  u8g2_draw_l90_cb draw_l90;\n};\n\ntypedef u8g2_uint_t (*u8g2_font_calc_vref_fnptr)(u8g2_t *u8g2);\n\n\nstruct u8g2_struct\n{\n  u8x8_t u8x8;\n  u8g2_draw_ll_hvline_cb ll_hvline;\t/* low level hvline procedure */\n  const u8g2_cb_t *cb;\t\t/* callback drawprocedures, can be replaced for rotation */\n  \n  /* the following variables must be assigned during u8g2 setup */\n  uint8_t *tile_buf_ptr;\t/* ptr to memory area with u8x8.display_info->tile_width * 8 * tile_buf_height bytes */\n  uint8_t tile_buf_height;\t/* height of the tile memory area in tile rows */\n  uint8_t tile_curr_row;\t/* current row for picture loop */\n  \n  /* dimension of the buffer in pixel */\n  u8g2_uint_t pixel_buf_width;\t\t/* equal to tile_buf_width*8 */\n  u8g2_uint_t pixel_buf_height;\t\t/* tile_buf_height*8 */\n  u8g2_uint_t pixel_curr_row;\t\t/* u8g2.tile_curr_row*8 */\n  \n  /* the following variables are set by the update dimension callback */\n  /* this is the clipbox after rotation for the hvline procedures */\n  //u8g2_uint_t buf_x0;\t/* left corner of the buffer */\n  //u8g2_uint_t buf_x1;\t/* right corner of the buffer (excluded) */\n  u8g2_uint_t buf_y0;\n  u8g2_uint_t buf_y1;\n  \n  /* display dimensions in pixel for the user, calculated in u8g2_update_dimension_common()  */\n  u8g2_uint_t width;\n  u8g2_uint_t height;\n  \n  /* ths is the clip box for the user to check if a specific box has an intersection */\n  /* use u8g2_IsIntersection from u8g2_intersection.c to test against this intersection */\n  /* actually, this window describes the positon of the current page */\n  u8g2_uint_t user_x0;\t/* left corner of the buffer */\n  u8g2_uint_t user_x1;\t/* right corner of the buffer (excluded) */\n  u8g2_uint_t user_y0;\t/* upper edge of the buffer */\n  u8g2_uint_t user_y1;\t/* lower edge of the buffer (excluded) */\n  \n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  /* clip window */\n  u8g2_uint_t clip_x0;\t/* left corner of the clip window */\n  u8g2_uint_t clip_x1;\t/* right corner of the clip window (excluded) */\n  u8g2_uint_t clip_y0;\t/* upper edge of the clip window */\n  u8g2_uint_t clip_y1;\t/* lower edge of the clip window (excluded) */\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n  \n  \n  /* information about the current font */\n  const uint8_t *font;             /* current font for all text procedures */\n  // removed: const u8g2_kerning_t *kerning;\t\t/* can be NULL */\n  // removed: u8g2_get_kerning_cb get_kerning_cb;\n  \n  u8g2_font_calc_vref_fnptr font_calc_vref;\n  u8g2_font_decode_t font_decode;\t\t/* new font decode structure */\n  u8g2_font_info_t font_info;\t\t\t/* new font info structure */\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  /* 1 of there is an intersection between user_?? and clip_?? box */\n  uint8_t is_page_clip_window_intersection;\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n\n  uint8_t font_height_mode;\n  int8_t font_ref_ascent;\n  int8_t font_ref_descent;\n  \n  int8_t glyph_x_offset;\t\t/* set by u8g2_GetGlyphWidth as a side effect */\n  \n  uint8_t bitmap_transparency;\t/* black pixels will be treated as transparent (not drawn) */\n\n  uint8_t draw_color;\t\t/* 0: clear pixel, 1: set pixel, modified and restored by font procedures */\n\t\t\t\t\t/* draw_color can be used also directly by the user API */\n\t\t\t\t\t\n\t// the following variable should be renamed to is_buffer_auto_clear\n  uint8_t is_auto_page_clear; \t\t/* set to 0 to disable automatic clear of the buffer in firstPage() and nextPage() */\n  \n};\n\n#define u8g2_GetU8x8(u8g2) ((u8x8_t *)(u8g2))\n//#define u8g2_GetU8x8(u8g2) (&((u8g2)->u8x8))\n\n#ifdef U8X8_WITH_USER_PTR\n#define u8g2_GetUserPtr(u8g2) ((u8g2_GetU8x8(u8g2))->user_ptr)\n#define u8g2_SetUserPtr(u8g2, p) ((u8g2_GetU8x8(u8g2))->user_ptr = (p))\n#endif\n\n// this should be renamed to SetBufferAutoClear \n#define u8g2_SetAutoPageClear(u8g2, mode) ((u8g2)->is_auto_page_clear = (mode))\n\n/*==========================================*/\n/* u8x8 wrapper */\n\n#define u8g2_SetupDisplay(u8g2, display_cb, cad_cb, byte_cb, gpio_and_delay_cb) \\\n  u8x8_Setup(u8g2_GetU8x8(u8g2), (display_cb), (cad_cb), (byte_cb), (gpio_and_delay_cb))\n\n#define u8g2_InitDisplay(u8g2) u8x8_InitDisplay(u8g2_GetU8x8(u8g2))\n#define u8g2_SetPowerSave(u8g2, is_enable) u8x8_SetPowerSave(u8g2_GetU8x8(u8g2), (is_enable))\n#define u8g2_SetFlipMode(u8g2, mode) u8x8_SetFlipMode(u8g2_GetU8x8(u8g2), (mode))\n#define u8g2_SetContrast(u8g2, value) u8x8_SetContrast(u8g2_GetU8x8(u8g2), (value))\n//#define u8g2_ClearDisplay(u8g2) u8x8_ClearDisplay(u8g2_GetU8x8(u8g2))  obsolete, can not be used in all cases\nvoid u8g2_ClearDisplay(u8g2_t *u8g2);\n\n#define u8g2_GetDisplayHeight(u8g2) ((u8g2)->height)\n#define u8g2_GetDisplayWidth(u8g2) ((u8g2)->width)\n#define u8g2_GetDrawColor(u8g2) ((u8g2)->draw_color)\n\n#define u8g2_SetI2CAddress(u8g2, address) ((u8g2_GetU8x8(u8g2))->i2c_address = (address))\n#define u8g2_GetI2CAddress(u8g2)   u8x8_GetI2CAddress(u8g2_GetU8x8(u8g2))\n\n#ifdef U8X8_USE_PINS \n#define u8g2_SetMenuSelectPin(u8g2, val) u8x8_SetMenuSelectPin(u8g2_GetU8x8(u8g2), (val)) \n#define u8g2_SetMenuNextPin(u8g2, val) u8x8_SetMenuNextPin(u8g2_GetU8x8(u8g2), (val))\n#define u8g2_SetMenuPrevPin(u8g2, val) u8x8_SetMenuPrevPin(u8g2_GetU8x8(u8g2), (val))\n#define u8g2_SetMenuHomePin(u8g2, val) u8x8_SetMenuHomePin(u8g2_GetU8x8(u8g2), (val))\n#define u8g2_SetMenuUpPin(u8g2, val) u8x8_SetMenuUpPin(u8g2_GetU8x8(u8g2), (val))\n#define u8g2_SetMenuDownPin(u8g2, val) u8x8_SetMenuDownPin(u8g2_GetU8x8(u8g2), (val))\n#endif\n\n/*==========================================*/\n/* u8g2_setup.c */\n\nvoid u8g2_draw_l90_r0(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n\nextern const u8g2_cb_t u8g2_cb_r0;\nextern const u8g2_cb_t u8g2_cb_r1;\nextern const u8g2_cb_t u8g2_cb_r2;\nextern const u8g2_cb_t u8g2_cb_r3;\nextern const u8g2_cb_t u8g2_cb_mirror;\nextern const u8g2_cb_t u8g2_cb_mirror_vertical;\n\n#define U8G2_R0\t(&u8g2_cb_r0)\n#define U8G2_R1\t(&u8g2_cb_r1)\n#define U8G2_R2\t(&u8g2_cb_r2)\n#define U8G2_R3\t(&u8g2_cb_r3)\n#define U8G2_MIRROR\t(&u8g2_cb_mirror)\n#define U8G2_MIRROR_VERTICAL\t(&u8g2_cb_mirror_vertical)\n/*\n  u8g2:\t\t\tA new, not yet initialized u8g2 memory areay\n  buf:\t\t\tMemory are of size tile_buf_height*<width of the display in pixel>\n  tile_buf_height:\tNumber of full lines\n  ll_hvline_cb:\t\tone of:\n    u8g2_ll_hvline_vertical_top_lsb\n    u8g2_ll_hvline_horizontal_right_lsb\n  u8g2_cb\t\t\tU8G2_R0 .. U8G2_R3\n      \n*/\n\nvoid u8g2_SetMaxClipWindow(u8g2_t *u8g2);\nvoid u8g2_SetClipWindow(u8g2_t *u8g2, u8g2_uint_t clip_x0, u8g2_uint_t clip_y0, u8g2_uint_t clip_x1, u8g2_uint_t clip_y1 );\n\nvoid u8g2_SetupBuffer(u8g2_t *u8g2, uint8_t *buf, uint8_t tile_buf_height, u8g2_draw_ll_hvline_cb ll_hvline_cb, const u8g2_cb_t *u8g2_cb);\nvoid u8g2_SetDisplayRotation(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\n\nvoid u8g2_SendF(u8g2_t * u8g2, const char *fmt, ...);\n\n/* null device setup */\nvoid u8g2_Setup_null(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\n\n/*==========================================*/\n/* u8g2_d_memory.c generated code start */\nuint8_t *u8g2_m_16_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_10_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_255_2_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_255_2_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_255_2_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_9_5_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_9_5_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_9_5_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_12_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_12_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_12_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_20_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_20_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_20_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_6_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_6_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_6_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_6_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_6_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_6_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_2_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_2_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_2_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_12_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_12_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_16_12_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_50_30_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_50_30_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_50_30_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_18_21_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_18_21_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_18_21_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_13_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_13_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_13_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_11_6_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_11_6_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_11_6_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_9_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_9_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_12_9_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_15_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_15_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_15_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_13_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_13_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_13_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_20_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_20_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_30_20_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_40_30_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_40_30_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_40_30_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_8_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_8_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_17_8_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_17_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_17_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_17_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_20_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_20_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_32_20_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_13_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_13_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_13_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_12_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_12_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_24_12_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_10_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_10_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_10_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_4_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_4_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_4_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_17_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_17_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_20_17_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_9_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_9_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_22_9_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_25_25_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_25_25_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_25_25_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_37_16_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_37_16_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_37_16_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_1_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_1_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_8_1_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_4_1_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_4_1_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_4_1_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_1_1_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_1_1_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_1_1_f(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_30_1(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_30_2(uint8_t *page_cnt);\nuint8_t *u8g2_m_48_30_f(uint8_t *page_cnt);\n\n/* u8g2_d_memory.c generated code end */\n\n/*==========================================*/\n/* u8g2_d_setup.c generated code start */\nvoid u8g2_Setup_ssd1305_128x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x32_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x32_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x32_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_raystar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_raystar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_128x64_raystar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_2040x16_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_2040x16_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_2040x16_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_alt0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_alt0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x64_alt0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x80_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_72x40_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_72x40_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_72x40_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_72x40_wise_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_72x40_wise_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_72x40_wise_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_64x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_64x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_64x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_64x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_64x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_64x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_pimoroni_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_pimoroni_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_pimoroni_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_seeed_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_i2c_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_i2c_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1108_i2c_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_i2c_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_i2c_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1122_i2c_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_univision_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_univision_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_univision_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_128x32_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x32_visionox_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x32_visionox_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_128x32_visionox_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x48_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x48_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x48_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_48x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_48x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_48x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_1f_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_1f_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_64x32_1f_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_96x16_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_96x16_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_96x16_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname2_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname2_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname2_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_128x64_noname0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_i2c_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_i2c_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1316_i2c_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_i2c_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_i2c_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1317_i2c_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_xcp_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_xcp_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_128x96_xcp_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_os128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_os128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_os128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_i2c_os128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_i2c_os128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd0323_i2c_os128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_er_256x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_er_256x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ea_w128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_midas_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ea_w128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_midas_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ea_w128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_midas_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_ws_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_visionox_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_visionox_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_visionox_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1329_128x96_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1329_128x96_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1329_128x96_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_60x32_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_p_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7920_s_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh03_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh03_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh03_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_400x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_400x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_400x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh05_144x168_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh05_144x168_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ls013b7dh05_144x168_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_ea_dogs102_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_ea_dogs102_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_ea_dogs102_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_mini12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_mini12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1701_mini12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcd8544_84x48_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcd8544_84x48_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcd8544_84x48_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcf8812_96x65_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcf8812_96x65_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_pcf8812_96x65_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_hx1230_96x68_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_hx1230_96x68_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_hx1230_96x68_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_jlx19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_jlx19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_jlx19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_i2c_jlx19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_i2c_jlx19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1604_i2c_jlx19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc24064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_dem240064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc24064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_dem240064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc24064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_dem240064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc24064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_dem240064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc24064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_dem240064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc24064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_dem240064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc240120_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc240120_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_erc240120_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc240120_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc240120_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_erc240120_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1608_i2c_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1638_160x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1638_160x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1638_160x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_ea_dogxl160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_ea_dogxl160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_ea_dogxl160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogm240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogm240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogm240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogxl240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogxl240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ea_dogxl240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ew50850_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ew50850_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ew50850_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ew50850_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ew50850_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ew50850_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_cg160160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_cg160160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_cg160160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_cg160160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_cg160160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_cg160160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ids4073_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ids4073_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_ids4073_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ids4073_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ids4073_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1611_i2c_ids4073_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7511_avd_320x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7511_avd_320x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7511_avd_320x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_nhd_c160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_nhd_c160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_nhd_c160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_erc16064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_erc16064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_erc16064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_erc16064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_erc16064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7528_i2c_erc16064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_jlx128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_jlx128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_jlx128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_i2c_jlx128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_i2c_jlx128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1617_i2c_jlx128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6063_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_64128n_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_zolen_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6059_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ks0713_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6063_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_64128n_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_zolen_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6059_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ks0713_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6063_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_64128n_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_zolen_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lm6059_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ks0713_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_lx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_erc12864_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12832_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12832_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_nhd_c12832_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_i2c_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_i2c_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_uc1601_i2c_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm132_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm132_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7565_ea_dogm132_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_pi_132x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_pi_132x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_pi_132x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064i_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_os12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064i_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_os12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_enh_dg128064i_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_os12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_hem6432_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_hem6432_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_hem6432_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_hem6432_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_hem6432_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7567_i2c_hem6432_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_i2c_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_i2c_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7571_i2c_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_s028hn118a_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_s028hn118a_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_s028hn118a_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_erc240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_ymc240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_erc240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_ymc240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_erc240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7586s_ymc240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_i2c_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_i2c_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st7588_i2c_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_wo256x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_wo256x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_wo256x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_wo256x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_wo256x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_wo256x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160m_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160m_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160m_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx256160_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160m_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160m_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160m_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx25664_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx25664_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx25664_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx25664_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx25664_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx25664_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx172104_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx172104_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx172104_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx172104_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx172104_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx172104_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx19296_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx19296_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_jlx19296_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx19296_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx19296_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75256_i2c_jlx19296_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_jlx320240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_jlx320240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_jlx320240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_i2c_jlx320240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_i2c_jlx320240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_st75320_i2c_jlx320240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_nt7534_tg12864r_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_nt7534_tg12864r_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_nt7534_tg12864r_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist3020_erc19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist3020_erc19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist3020_erc19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist7920_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist7920_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ist7920_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sbn1661_122x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sbn1661_122x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sbn1661_122x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1520_122x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1520_122x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1520_122x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_erm19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_erm19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ks0108_erm19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x80_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x80_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x80_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_lc7981_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_128x64_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_160x80_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_160x80_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_t6963_160x80_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x132_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x132_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1320_160x132_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1322_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1606_172x72_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1606_172x72_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1606_172x72_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_gd_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_ws_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_gd_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_ws_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_gd_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ssd1607_ws_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_296x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_v2_296x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_296x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_v2_296x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_296x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_il3820_v2_296x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1330_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1330_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_sed1330_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_nhd_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_nhd_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_nhd_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_320x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_320x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_ra8835_320x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_64x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_64x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_64x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_32x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_32x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_32x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_8x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_8x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_max7219_8x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15e06_160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15e06_160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15e06_160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15721_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15721_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_s1d15721_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_a2printer_384x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_a2printer_384x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\nvoid u8g2_Setup_a2printer_384x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\n\n/* u8g2_d_setup.c generated code end */\n\n/*==========================================*/\n/* u8g2_buffer.c */\n\nvoid u8g2_SendBuffer(u8g2_t *u8g2);\nvoid u8g2_ClearBuffer(u8g2_t *u8g2);\n\nvoid u8g2_SetBufferCurrTileRow(u8g2_t *u8g2, uint8_t row) U8G2_NOINLINE;\n\nvoid u8g2_FirstPage(u8g2_t *u8g2);\nuint8_t u8g2_NextPage(u8g2_t *u8g2);\n\n#ifdef U8G2_USE_DYNAMIC_ALLOC\n#define u8g2_SetBufferPtr(u8g2, buf) ((u8g2)->tile_buf_ptr = (buf));\n#define u8g2_GetBufferSize(u8g2) ((u8g2)->u8x8.display_info->tile_width * 8 * (u8g2)->tile_buf_height)\n#endif\n#define u8g2_GetBufferPtr(u8g2) ((u8g2)->tile_buf_ptr)\n#define u8g2_GetBufferTileHeight(u8g2)\t((u8g2)->tile_buf_height)\n#define u8g2_GetBufferTileWidth(u8g2)\t(u8g2_GetU8x8(u8g2)->display_info->tile_width)\n/* the following variable is only valid after calling u8g2_FirstPage */\n/* renamed from Page to Buffer: the CurrTileRow is the current row of the buffer, issue #370 */\n#define u8g2_GetPageCurrTileRow(u8g2) ((u8g2)->tile_curr_row)\n#define u8g2_GetBufferCurrTileRow(u8g2) ((u8g2)->tile_curr_row)\n\nvoid u8g2_UpdateDisplayArea(u8g2_t *u8g2, uint8_t  tx, uint8_t ty, uint8_t tw, uint8_t th);\nvoid u8g2_UpdateDisplay(u8g2_t *u8g2);\n\nvoid u8g2_WriteBufferPBM(u8g2_t *u8g2, void (*out)(const char *s));\nvoid u8g2_WriteBufferXBM(u8g2_t *u8g2, void (*out)(const char *s));\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nvoid u8g2_WriteBufferPBM2(u8g2_t *u8g2, void (*out)(const char *s));\nvoid u8g2_WriteBufferXBM2(u8g2_t *u8g2, void (*out)(const char *s));\n\n\n/*==========================================*/\n/* u8g2_ll_hvline.c */\n/*\n  x,y\t\tUpper left position of the line within the local buffer (not the display!)\n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  asumption: \n    all clipping done\n*/\n\n/* SSD13xx, UC17xx, UC16xx */\nvoid u8g2_ll_hvline_vertical_top_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n/* ST7920 */\nvoid u8g2_ll_hvline_horizontal_right_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n\n\n/*==========================================*/\n/* u8g2_hvline.c */\n\n/* u8g2_DrawHVLine does not use u8g2_IsIntersection */\nvoid u8g2_DrawHVLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n\n/* the following three function will do an intersection test of this is enabled with U8G2_WITH_INTERSECTION */\nvoid u8g2_DrawHLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len);\nvoid u8g2_DrawVLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len);\nvoid u8g2_DrawPixel(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y);\nvoid u8g2_SetDrawColor(u8g2_t *u8g2, uint8_t color) U8G2_NOINLINE;  /* u8g: u8g_SetColorIndex(u8g_t *u8g, uint8_t idx); */\n\n\n/*==========================================*/\n/* u8g2_bitmap.c */\nvoid u8g2_SetBitmapMode(u8g2_t *u8g2, uint8_t is_transparent);\nvoid u8g2_DrawHorizontalBitmap(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, const uint8_t *b);\nvoid u8g2_DrawBitmap(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t cnt, u8g2_uint_t h, const uint8_t *bitmap);\nvoid u8g2_DrawXBM(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap);\nvoid u8g2_DrawXBMP(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap);\t/* assumes bitmap in PROGMEM */\n\n\n/*==========================================*/\n/* u8g2_intersection.c */\n#ifdef U8G2_WITH_INTERSECTION    \nuint8_t u8g2_IsIntersection(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t x1, u8g2_uint_t y1);\n#endif /* U8G2_WITH_INTERSECTION */\n\n\n\n/*==========================================*/\n/* u8g2_circle.c */\n#define U8G2_DRAW_UPPER_RIGHT 0x01\n#define U8G2_DRAW_UPPER_LEFT  0x02\n#define U8G2_DRAW_LOWER_LEFT 0x04\n#define U8G2_DRAW_LOWER_RIGHT  0x08\n#define U8G2_DRAW_ALL (U8G2_DRAW_UPPER_RIGHT|U8G2_DRAW_UPPER_LEFT|U8G2_DRAW_LOWER_RIGHT|U8G2_DRAW_LOWER_LEFT)\nvoid u8g2_DrawCircle(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option);\nvoid u8g2_DrawDisc(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option);\nvoid u8g2_DrawEllipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option);\nvoid u8g2_DrawFilledEllipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option);\n\n/*==========================================*/\n/* u8g2_line.c */\nvoid u8g2_DrawLine(u8g2_t *u8g2, u8g2_uint_t x1, u8g2_uint_t y1, u8g2_uint_t x2, u8g2_uint_t y2);\n\n\n/*==========================================*/\n/* u8g2_box.c */\nvoid u8g2_DrawBox(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h);\nvoid u8g2_DrawFrame(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h);\nvoid u8g2_DrawRBox(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r);\nvoid u8g2_DrawRFrame(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r);\n\n\n/*==========================================*/\n/* u8g2_polygon.c */\nvoid u8g2_ClearPolygonXY(void);\nvoid u8g2_AddPolygonXY(u8g2_t *u8g2, int16_t x, int16_t y);\nvoid u8g2_DrawPolygon(u8g2_t *u8g2);\nvoid u8g2_DrawTriangle(u8g2_t *u8g2, int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2);\n\n\n\n/*==========================================*/\n/* u8g2_kerning.c */\n//uint8_t u8g2_GetNullKerning(u8g2_t *u8g2, uint16_t e1, uint16_t e2);\nuint8_t u8g2_GetKerning(u8g2_t *u8g2, u8g2_kerning_t *kerning, uint16_t e1, uint16_t e2);\nuint8_t u8g2_GetKerningByTable(u8g2_t *u8g2, const uint16_t *kt, uint16_t e1, uint16_t e2);\n\n\n/*==========================================*/\n/* u8g2_font.c */\n\nu8g2_uint_t u8g2_add_vector_y(u8g2_uint_t dy, int8_t x, int8_t y, uint8_t dir) U8G2_NOINLINE;\nu8g2_uint_t u8g2_add_vector_x(u8g2_uint_t dx, int8_t x, int8_t y, uint8_t dir) U8G2_NOINLINE;\n\n\nsize_t u8g2_GetFontSize(const uint8_t *font_arg);\n\n#define U8G2_FONT_HEIGHT_MODE_TEXT 0\n#define U8G2_FONT_HEIGHT_MODE_XTEXT 1\n#define U8G2_FONT_HEIGHT_MODE_ALL 2\n\nvoid u8g2_SetFont(u8g2_t *u8g2, const uint8_t  *font);\nvoid u8g2_SetFontMode(u8g2_t *u8g2, uint8_t is_transparent);\n\nuint8_t u8g2_IsGlyph(u8g2_t *u8g2, uint16_t requested_encoding);\nint8_t u8g2_GetGlyphWidth(u8g2_t *u8g2, uint16_t requested_encoding);\nu8g2_uint_t u8g2_DrawGlyph(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint16_t encoding);\nint8_t u8g2_GetStrX(u8g2_t *u8g2, const char *s);\t/* for u8g compatibility */\n\nvoid u8g2_SetFontDirection(u8g2_t *u8g2, uint8_t dir);\nu8g2_uint_t u8g2_DrawStr(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str);\nu8g2_uint_t u8g2_DrawUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str);\nu8g2_uint_t u8g2_DrawExtendedUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint8_t to_left, u8g2_kerning_t *kerning, const char *str);\nu8g2_uint_t u8g2_DrawExtUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint8_t to_left, const uint16_t *kerning_table, const char *str);\n\n#define u8g2_GetMaxCharHeight(u8g2) ((u8g2)->font_info.max_char_height)\n#define u8g2_GetMaxCharWidth(u8g2) ((u8g2)->font_info.max_char_width)\n#define u8g2_GetAscent(u8g2) ((u8g2)->font_ref_ascent)\n#define u8g2_GetDescent(u8g2) ((u8g2)->font_ref_descent)\n#define u8g2_GetFontAscent(u8g2) ((u8g2)->font_ref_ascent)\n#define u8g2_GetFontDescent(u8g2) ((u8g2)->font_ref_descent)\n\nuint8_t u8g2_IsAllValidUTF8(u8g2_t *u8g2, const char *str);\t// checks whether all codes are valid\n\nu8g2_uint_t u8g2_GetStrWidth(u8g2_t *u8g2, const char *s);\nu8g2_uint_t u8g2_GetUTF8Width(u8g2_t *u8g2, const char *str);\n\nvoid u8g2_SetFontPosBaseline(u8g2_t *u8g2);\nvoid u8g2_SetFontPosBottom(u8g2_t *u8g2);\nvoid u8g2_SetFontPosTop(u8g2_t *u8g2);\nvoid u8g2_SetFontPosCenter(u8g2_t *u8g2);\n\nvoid u8g2_SetFontRefHeightText(u8g2_t *u8g2);\nvoid u8g2_SetFontRefHeightExtendedText(u8g2_t *u8g2);\nvoid u8g2_SetFontRefHeightAll(u8g2_t *u8g2);\n\n/*==========================================*/\n/* u8log_u8g2.c */\nvoid u8g2_DrawLog(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8log_t *u8log);\nvoid u8log_u8g2_cb(u8log_t * u8log);\n\n\n/*==========================================*/\n/* u8g2_selection_list.c */\nvoid u8g2_DrawUTF8Line(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, const char *s, uint8_t border_size, uint8_t is_invert);\nu8g2_uint_t u8g2_DrawUTF8Lines(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t line_height, const char *s);\nuint8_t u8g2_UserInterfaceSelectionList(u8g2_t *u8g2, const char *title, uint8_t start_pos, const char *sl);\n\n/*==========================================*/\n/* u8g2_message.c */\nuint8_t u8g2_UserInterfaceMessage(u8g2_t *u8g2, const char *title1, const char *title2, const char *title3, const char *buttons);\n\n/*==========================================*/\n/* u8g2_input_value.c */\nuint8_t u8g2_UserInterfaceInputValue(u8g2_t *u8g2, const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits, const char *post);\n\n\n/*==========================================*/\n/* u8x8_d_sdl_128x64.c */\nvoid u8g2_SetupBuffer_SDL_128x64(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\nvoid u8g2_SetupBuffer_SDL_128x64_4(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\nvoid u8g2_SetupBuffer_SDL_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\n\n/*==========================================*/\n/* u8x8_d_tga.c */\nvoid u8g2_SetupBuffer_TGA_DESC(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\nvoid u8g2_SetupBuffer_TGA_LCD(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\n\n/*==========================================*/\n/* u8x8_d_bitmap.c */\nvoid u8g2_SetupBitmap(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb, uint16_t pixel_width, uint16_t pixel_height);\n\n\n/*==========================================*/\n/* u8x8_d_utf8.c */\n/* 96x32 stdout */\nvoid u8g2_SetupBuffer_Utf8(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb);\n\n\n\n\n/*==========================================*/\n/* itoa procedures */\n#define u8g2_u8toa u8x8_u8toa\n#define u8g2_u16toa u8x8_u16toa\n\n\n/*==========================================*/\n\n/* start font list */\nextern const uint8_t u8g2_font_u8glib_4_tf[] U8G2_FONT_SECTION(\"u8g2_font_u8glib_4_tf\");\nextern const uint8_t u8g2_font_u8glib_4_tr[] U8G2_FONT_SECTION(\"u8g2_font_u8glib_4_tr\");\nextern const uint8_t u8g2_font_u8glib_4_hf[] U8G2_FONT_SECTION(\"u8g2_font_u8glib_4_hf\");\nextern const uint8_t u8g2_font_u8glib_4_hr[] U8G2_FONT_SECTION(\"u8g2_font_u8glib_4_hr\");\nextern const uint8_t u8g2_font_m2icon_5_tf[] U8G2_FONT_SECTION(\"u8g2_font_m2icon_5_tf\");\nextern const uint8_t u8g2_font_m2icon_7_tf[] U8G2_FONT_SECTION(\"u8g2_font_m2icon_7_tf\");\nextern const uint8_t u8g2_font_m2icon_9_tf[] U8G2_FONT_SECTION(\"u8g2_font_m2icon_9_tf\");\nextern const uint8_t u8g2_font_emoticons21_tr[] U8G2_FONT_SECTION(\"u8g2_font_emoticons21_tr\");\nextern const uint8_t u8g2_font_battery19_tn[] U8G2_FONT_SECTION(\"u8g2_font_battery19_tn\");\nextern const uint8_t u8g2_font_freedoomr10_tu[] U8G2_FONT_SECTION(\"u8g2_font_freedoomr10_tu\");\nextern const uint8_t u8g2_font_freedoomr10_mu[] U8G2_FONT_SECTION(\"u8g2_font_freedoomr10_mu\");\nextern const uint8_t u8g2_font_freedoomr25_tn[] U8G2_FONT_SECTION(\"u8g2_font_freedoomr25_tn\");\nextern const uint8_t u8g2_font_freedoomr25_mn[] U8G2_FONT_SECTION(\"u8g2_font_freedoomr25_mn\");\nextern const uint8_t u8g2_font_7Segments_26x42_mn[] U8G2_FONT_SECTION(\"u8g2_font_7Segments_26x42_mn\");\nextern const uint8_t u8g2_font_amstrad_cpc_extended_8f[] U8G2_FONT_SECTION(\"u8g2_font_amstrad_cpc_extended_8f\");\nextern const uint8_t u8g2_font_amstrad_cpc_extended_8r[] U8G2_FONT_SECTION(\"u8g2_font_amstrad_cpc_extended_8r\");\nextern const uint8_t u8g2_font_amstrad_cpc_extended_8n[] U8G2_FONT_SECTION(\"u8g2_font_amstrad_cpc_extended_8n\");\nextern const uint8_t u8g2_font_amstrad_cpc_extended_8u[] U8G2_FONT_SECTION(\"u8g2_font_amstrad_cpc_extended_8u\");\nextern const uint8_t u8g2_font_cursor_tf[] U8G2_FONT_SECTION(\"u8g2_font_cursor_tf\");\nextern const uint8_t u8g2_font_cursor_tr[] U8G2_FONT_SECTION(\"u8g2_font_cursor_tr\");\nextern const uint8_t u8g2_font_micro_tr[] U8G2_FONT_SECTION(\"u8g2_font_micro_tr\");\nextern const uint8_t u8g2_font_micro_tn[] U8G2_FONT_SECTION(\"u8g2_font_micro_tn\");\nextern const uint8_t u8g2_font_micro_mr[] U8G2_FONT_SECTION(\"u8g2_font_micro_mr\");\nextern const uint8_t u8g2_font_micro_mn[] U8G2_FONT_SECTION(\"u8g2_font_micro_mn\");\nextern const uint8_t u8g2_font_4x6_tf[] U8G2_FONT_SECTION(\"u8g2_font_4x6_tf\");\nextern const uint8_t u8g2_font_4x6_tr[] U8G2_FONT_SECTION(\"u8g2_font_4x6_tr\");\nextern const uint8_t u8g2_font_4x6_tn[] U8G2_FONT_SECTION(\"u8g2_font_4x6_tn\");\nextern const uint8_t u8g2_font_4x6_mf[] U8G2_FONT_SECTION(\"u8g2_font_4x6_mf\");\nextern const uint8_t u8g2_font_4x6_mr[] U8G2_FONT_SECTION(\"u8g2_font_4x6_mr\");\nextern const uint8_t u8g2_font_4x6_mn[] U8G2_FONT_SECTION(\"u8g2_font_4x6_mn\");\nextern const uint8_t u8g2_font_4x6_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_4x6_t_cyrillic\");\nextern const uint8_t u8g2_font_5x7_tf[] U8G2_FONT_SECTION(\"u8g2_font_5x7_tf\");\nextern const uint8_t u8g2_font_5x7_tr[] U8G2_FONT_SECTION(\"u8g2_font_5x7_tr\");\nextern const uint8_t u8g2_font_5x7_tn[] U8G2_FONT_SECTION(\"u8g2_font_5x7_tn\");\nextern const uint8_t u8g2_font_5x7_mf[] U8G2_FONT_SECTION(\"u8g2_font_5x7_mf\");\nextern const uint8_t u8g2_font_5x7_mr[] U8G2_FONT_SECTION(\"u8g2_font_5x7_mr\");\nextern const uint8_t u8g2_font_5x7_mn[] U8G2_FONT_SECTION(\"u8g2_font_5x7_mn\");\nextern const uint8_t u8g2_font_5x7_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_5x7_t_cyrillic\");\nextern const uint8_t u8g2_font_5x8_tf[] U8G2_FONT_SECTION(\"u8g2_font_5x8_tf\");\nextern const uint8_t u8g2_font_5x8_tr[] U8G2_FONT_SECTION(\"u8g2_font_5x8_tr\");\nextern const uint8_t u8g2_font_5x8_tn[] U8G2_FONT_SECTION(\"u8g2_font_5x8_tn\");\nextern const uint8_t u8g2_font_5x8_mf[] U8G2_FONT_SECTION(\"u8g2_font_5x8_mf\");\nextern const uint8_t u8g2_font_5x8_mr[] U8G2_FONT_SECTION(\"u8g2_font_5x8_mr\");\nextern const uint8_t u8g2_font_5x8_mn[] U8G2_FONT_SECTION(\"u8g2_font_5x8_mn\");\nextern const uint8_t u8g2_font_5x8_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_5x8_t_cyrillic\");\nextern const uint8_t u8g2_font_6x10_tf[] U8G2_FONT_SECTION(\"u8g2_font_6x10_tf\");\nextern const uint8_t u8g2_font_6x10_tr[] U8G2_FONT_SECTION(\"u8g2_font_6x10_tr\");\nextern const uint8_t u8g2_font_6x10_tn[] U8G2_FONT_SECTION(\"u8g2_font_6x10_tn\");\nextern const uint8_t u8g2_font_6x10_mf[] U8G2_FONT_SECTION(\"u8g2_font_6x10_mf\");\nextern const uint8_t u8g2_font_6x10_mr[] U8G2_FONT_SECTION(\"u8g2_font_6x10_mr\");\nextern const uint8_t u8g2_font_6x10_mn[] U8G2_FONT_SECTION(\"u8g2_font_6x10_mn\");\nextern const uint8_t u8g2_font_6x12_tf[] U8G2_FONT_SECTION(\"u8g2_font_6x12_tf\");\nextern const uint8_t u8g2_font_6x12_tr[] U8G2_FONT_SECTION(\"u8g2_font_6x12_tr\");\nextern const uint8_t u8g2_font_6x12_tn[] U8G2_FONT_SECTION(\"u8g2_font_6x12_tn\");\nextern const uint8_t u8g2_font_6x12_te[] U8G2_FONT_SECTION(\"u8g2_font_6x12_te\");\nextern const uint8_t u8g2_font_6x12_mf[] U8G2_FONT_SECTION(\"u8g2_font_6x12_mf\");\nextern const uint8_t u8g2_font_6x12_mr[] U8G2_FONT_SECTION(\"u8g2_font_6x12_mr\");\nextern const uint8_t u8g2_font_6x12_mn[] U8G2_FONT_SECTION(\"u8g2_font_6x12_mn\");\nextern const uint8_t u8g2_font_6x12_me[] U8G2_FONT_SECTION(\"u8g2_font_6x12_me\");\nextern const uint8_t u8g2_font_6x12_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_6x12_t_symbols\");\nextern const uint8_t u8g2_font_6x12_m_symbols[] U8G2_FONT_SECTION(\"u8g2_font_6x12_m_symbols\");\nextern const uint8_t u8g2_font_6x12_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_6x12_t_cyrillic\");\nextern const uint8_t u8g2_font_6x13_tf[] U8G2_FONT_SECTION(\"u8g2_font_6x13_tf\");\nextern const uint8_t u8g2_font_6x13_tr[] U8G2_FONT_SECTION(\"u8g2_font_6x13_tr\");\nextern const uint8_t u8g2_font_6x13_tn[] U8G2_FONT_SECTION(\"u8g2_font_6x13_tn\");\nextern const uint8_t u8g2_font_6x13_te[] U8G2_FONT_SECTION(\"u8g2_font_6x13_te\");\nextern const uint8_t u8g2_font_6x13_mf[] U8G2_FONT_SECTION(\"u8g2_font_6x13_mf\");\nextern const uint8_t u8g2_font_6x13_mr[] U8G2_FONT_SECTION(\"u8g2_font_6x13_mr\");\nextern const uint8_t u8g2_font_6x13_mn[] U8G2_FONT_SECTION(\"u8g2_font_6x13_mn\");\nextern const uint8_t u8g2_font_6x13_me[] U8G2_FONT_SECTION(\"u8g2_font_6x13_me\");\nextern const uint8_t u8g2_font_6x13_t_hebrew[] U8G2_FONT_SECTION(\"u8g2_font_6x13_t_hebrew\");\nextern const uint8_t u8g2_font_6x13_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_6x13_t_cyrillic\");\nextern const uint8_t u8g2_font_6x13B_tf[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_tf\");\nextern const uint8_t u8g2_font_6x13B_tr[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_tr\");\nextern const uint8_t u8g2_font_6x13B_tn[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_tn\");\nextern const uint8_t u8g2_font_6x13B_mf[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_mf\");\nextern const uint8_t u8g2_font_6x13B_mr[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_mr\");\nextern const uint8_t u8g2_font_6x13B_mn[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_mn\");\nextern const uint8_t u8g2_font_6x13B_t_hebrew[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_t_hebrew\");\nextern const uint8_t u8g2_font_6x13B_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_6x13B_t_cyrillic\");\nextern const uint8_t u8g2_font_6x13O_tf[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_tf\");\nextern const uint8_t u8g2_font_6x13O_tr[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_tr\");\nextern const uint8_t u8g2_font_6x13O_tn[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_tn\");\nextern const uint8_t u8g2_font_6x13O_mf[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_mf\");\nextern const uint8_t u8g2_font_6x13O_mr[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_mr\");\nextern const uint8_t u8g2_font_6x13O_mn[] U8G2_FONT_SECTION(\"u8g2_font_6x13O_mn\");\nextern const uint8_t u8g2_font_7x13_tf[] U8G2_FONT_SECTION(\"u8g2_font_7x13_tf\");\nextern const uint8_t u8g2_font_7x13_tr[] U8G2_FONT_SECTION(\"u8g2_font_7x13_tr\");\nextern const uint8_t u8g2_font_7x13_tn[] U8G2_FONT_SECTION(\"u8g2_font_7x13_tn\");\nextern const uint8_t u8g2_font_7x13_te[] U8G2_FONT_SECTION(\"u8g2_font_7x13_te\");\nextern const uint8_t u8g2_font_7x13_mf[] U8G2_FONT_SECTION(\"u8g2_font_7x13_mf\");\nextern const uint8_t u8g2_font_7x13_mr[] U8G2_FONT_SECTION(\"u8g2_font_7x13_mr\");\nextern const uint8_t u8g2_font_7x13_mn[] U8G2_FONT_SECTION(\"u8g2_font_7x13_mn\");\nextern const uint8_t u8g2_font_7x13_me[] U8G2_FONT_SECTION(\"u8g2_font_7x13_me\");\nextern const uint8_t u8g2_font_7x13_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_7x13_t_symbols\");\nextern const uint8_t u8g2_font_7x13_m_symbols[] U8G2_FONT_SECTION(\"u8g2_font_7x13_m_symbols\");\nextern const uint8_t u8g2_font_7x13_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_7x13_t_cyrillic\");\nextern const uint8_t u8g2_font_7x13B_tf[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_tf\");\nextern const uint8_t u8g2_font_7x13B_tr[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_tr\");\nextern const uint8_t u8g2_font_7x13B_tn[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_tn\");\nextern const uint8_t u8g2_font_7x13B_mf[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_mf\");\nextern const uint8_t u8g2_font_7x13B_mr[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_mr\");\nextern const uint8_t u8g2_font_7x13B_mn[] U8G2_FONT_SECTION(\"u8g2_font_7x13B_mn\");\nextern const uint8_t u8g2_font_7x13O_tf[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_tf\");\nextern const uint8_t u8g2_font_7x13O_tr[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_tr\");\nextern const uint8_t u8g2_font_7x13O_tn[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_tn\");\nextern const uint8_t u8g2_font_7x13O_mf[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_mf\");\nextern const uint8_t u8g2_font_7x13O_mr[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_mr\");\nextern const uint8_t u8g2_font_7x13O_mn[] U8G2_FONT_SECTION(\"u8g2_font_7x13O_mn\");\nextern const uint8_t u8g2_font_7x14_tf[] U8G2_FONT_SECTION(\"u8g2_font_7x14_tf\");\nextern const uint8_t u8g2_font_7x14_tr[] U8G2_FONT_SECTION(\"u8g2_font_7x14_tr\");\nextern const uint8_t u8g2_font_7x14_tn[] U8G2_FONT_SECTION(\"u8g2_font_7x14_tn\");\nextern const uint8_t u8g2_font_7x14_mf[] U8G2_FONT_SECTION(\"u8g2_font_7x14_mf\");\nextern const uint8_t u8g2_font_7x14_mr[] U8G2_FONT_SECTION(\"u8g2_font_7x14_mr\");\nextern const uint8_t u8g2_font_7x14_mn[] U8G2_FONT_SECTION(\"u8g2_font_7x14_mn\");\nextern const uint8_t u8g2_font_7x14B_tf[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_tf\");\nextern const uint8_t u8g2_font_7x14B_tr[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_tr\");\nextern const uint8_t u8g2_font_7x14B_tn[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_tn\");\nextern const uint8_t u8g2_font_7x14B_mf[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_mf\");\nextern const uint8_t u8g2_font_7x14B_mr[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_mr\");\nextern const uint8_t u8g2_font_7x14B_mn[] U8G2_FONT_SECTION(\"u8g2_font_7x14B_mn\");\nextern const uint8_t u8g2_font_8x13_tf[] U8G2_FONT_SECTION(\"u8g2_font_8x13_tf\");\nextern const uint8_t u8g2_font_8x13_tr[] U8G2_FONT_SECTION(\"u8g2_font_8x13_tr\");\nextern const uint8_t u8g2_font_8x13_tn[] U8G2_FONT_SECTION(\"u8g2_font_8x13_tn\");\nextern const uint8_t u8g2_font_8x13_te[] U8G2_FONT_SECTION(\"u8g2_font_8x13_te\");\nextern const uint8_t u8g2_font_8x13_mf[] U8G2_FONT_SECTION(\"u8g2_font_8x13_mf\");\nextern const uint8_t u8g2_font_8x13_mr[] U8G2_FONT_SECTION(\"u8g2_font_8x13_mr\");\nextern const uint8_t u8g2_font_8x13_mn[] U8G2_FONT_SECTION(\"u8g2_font_8x13_mn\");\nextern const uint8_t u8g2_font_8x13_me[] U8G2_FONT_SECTION(\"u8g2_font_8x13_me\");\nextern const uint8_t u8g2_font_8x13_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_8x13_t_symbols\");\nextern const uint8_t u8g2_font_8x13_m_symbols[] U8G2_FONT_SECTION(\"u8g2_font_8x13_m_symbols\");\nextern const uint8_t u8g2_font_8x13_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_8x13_t_cyrillic\");\nextern const uint8_t u8g2_font_8x13B_tf[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_tf\");\nextern const uint8_t u8g2_font_8x13B_tr[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_tr\");\nextern const uint8_t u8g2_font_8x13B_tn[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_tn\");\nextern const uint8_t u8g2_font_8x13B_mf[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_mf\");\nextern const uint8_t u8g2_font_8x13B_mr[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_mr\");\nextern const uint8_t u8g2_font_8x13B_mn[] U8G2_FONT_SECTION(\"u8g2_font_8x13B_mn\");\nextern const uint8_t u8g2_font_8x13O_tf[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_tf\");\nextern const uint8_t u8g2_font_8x13O_tr[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_tr\");\nextern const uint8_t u8g2_font_8x13O_tn[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_tn\");\nextern const uint8_t u8g2_font_8x13O_mf[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_mf\");\nextern const uint8_t u8g2_font_8x13O_mr[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_mr\");\nextern const uint8_t u8g2_font_8x13O_mn[] U8G2_FONT_SECTION(\"u8g2_font_8x13O_mn\");\nextern const uint8_t u8g2_font_9x15_tf[] U8G2_FONT_SECTION(\"u8g2_font_9x15_tf\");\nextern const uint8_t u8g2_font_9x15_tr[] U8G2_FONT_SECTION(\"u8g2_font_9x15_tr\");\nextern const uint8_t u8g2_font_9x15_tn[] U8G2_FONT_SECTION(\"u8g2_font_9x15_tn\");\nextern const uint8_t u8g2_font_9x15_te[] U8G2_FONT_SECTION(\"u8g2_font_9x15_te\");\nextern const uint8_t u8g2_font_9x15_mf[] U8G2_FONT_SECTION(\"u8g2_font_9x15_mf\");\nextern const uint8_t u8g2_font_9x15_mr[] U8G2_FONT_SECTION(\"u8g2_font_9x15_mr\");\nextern const uint8_t u8g2_font_9x15_mn[] U8G2_FONT_SECTION(\"u8g2_font_9x15_mn\");\nextern const uint8_t u8g2_font_9x15_me[] U8G2_FONT_SECTION(\"u8g2_font_9x15_me\");\nextern const uint8_t u8g2_font_9x15_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_9x15_t_symbols\");\nextern const uint8_t u8g2_font_9x15_m_symbols[] U8G2_FONT_SECTION(\"u8g2_font_9x15_m_symbols\");\nextern const uint8_t u8g2_font_9x15_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_9x15_t_cyrillic\");\nextern const uint8_t u8g2_font_9x15B_tf[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_tf\");\nextern const uint8_t u8g2_font_9x15B_tr[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_tr\");\nextern const uint8_t u8g2_font_9x15B_tn[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_tn\");\nextern const uint8_t u8g2_font_9x15B_mf[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_mf\");\nextern const uint8_t u8g2_font_9x15B_mr[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_mr\");\nextern const uint8_t u8g2_font_9x15B_mn[] U8G2_FONT_SECTION(\"u8g2_font_9x15B_mn\");\nextern const uint8_t u8g2_font_9x18_tf[] U8G2_FONT_SECTION(\"u8g2_font_9x18_tf\");\nextern const uint8_t u8g2_font_9x18_tr[] U8G2_FONT_SECTION(\"u8g2_font_9x18_tr\");\nextern const uint8_t u8g2_font_9x18_tn[] U8G2_FONT_SECTION(\"u8g2_font_9x18_tn\");\nextern const uint8_t u8g2_font_9x18_mf[] U8G2_FONT_SECTION(\"u8g2_font_9x18_mf\");\nextern const uint8_t u8g2_font_9x18_mr[] U8G2_FONT_SECTION(\"u8g2_font_9x18_mr\");\nextern const uint8_t u8g2_font_9x18_mn[] U8G2_FONT_SECTION(\"u8g2_font_9x18_mn\");\nextern const uint8_t u8g2_font_9x18B_tf[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_tf\");\nextern const uint8_t u8g2_font_9x18B_tr[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_tr\");\nextern const uint8_t u8g2_font_9x18B_tn[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_tn\");\nextern const uint8_t u8g2_font_9x18B_mf[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_mf\");\nextern const uint8_t u8g2_font_9x18B_mr[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_mr\");\nextern const uint8_t u8g2_font_9x18B_mn[] U8G2_FONT_SECTION(\"u8g2_font_9x18B_mn\");\nextern const uint8_t u8g2_font_10x20_tf[] U8G2_FONT_SECTION(\"u8g2_font_10x20_tf\");\nextern const uint8_t u8g2_font_10x20_tr[] U8G2_FONT_SECTION(\"u8g2_font_10x20_tr\");\nextern const uint8_t u8g2_font_10x20_tn[] U8G2_FONT_SECTION(\"u8g2_font_10x20_tn\");\nextern const uint8_t u8g2_font_10x20_te[] U8G2_FONT_SECTION(\"u8g2_font_10x20_te\");\nextern const uint8_t u8g2_font_10x20_mf[] U8G2_FONT_SECTION(\"u8g2_font_10x20_mf\");\nextern const uint8_t u8g2_font_10x20_mr[] U8G2_FONT_SECTION(\"u8g2_font_10x20_mr\");\nextern const uint8_t u8g2_font_10x20_mn[] U8G2_FONT_SECTION(\"u8g2_font_10x20_mn\");\nextern const uint8_t u8g2_font_10x20_me[] U8G2_FONT_SECTION(\"u8g2_font_10x20_me\");\nextern const uint8_t u8g2_font_10x20_t_greek[] U8G2_FONT_SECTION(\"u8g2_font_10x20_t_greek\");\nextern const uint8_t u8g2_font_10x20_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_10x20_t_cyrillic\");\nextern const uint8_t u8g2_font_10x20_t_arabic[] U8G2_FONT_SECTION(\"u8g2_font_10x20_t_arabic\");\nextern const uint8_t u8g2_font_siji_t_6x10[] U8G2_FONT_SECTION(\"u8g2_font_siji_t_6x10\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_t_all[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_t_all\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_tf[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_tf\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_tr[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_tr\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_tn[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_tn\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_te[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_te\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_mf[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_mf\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_mr[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_mr\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_mn[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_mn\");\nextern const uint8_t u8g2_font_tom_thumb_4x6_me[] U8G2_FONT_SECTION(\"u8g2_font_tom_thumb_4x6_me\");\nextern const uint8_t u8g2_font_t0_11_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_tf\");\nextern const uint8_t u8g2_font_t0_11_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_tr\");\nextern const uint8_t u8g2_font_t0_11_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_tn\");\nextern const uint8_t u8g2_font_t0_11_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_te\");\nextern const uint8_t u8g2_font_t0_11_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_mf\");\nextern const uint8_t u8g2_font_t0_11_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_mr\");\nextern const uint8_t u8g2_font_t0_11_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_mn\");\nextern const uint8_t u8g2_font_t0_11_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_me\");\nextern const uint8_t u8g2_font_t0_11_t_all[] U8G2_FONT_SECTION(\"u8g2_font_t0_11_t_all\");\nextern const uint8_t u8g2_font_t0_11b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_tf\");\nextern const uint8_t u8g2_font_t0_11b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_tr\");\nextern const uint8_t u8g2_font_t0_11b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_tn\");\nextern const uint8_t u8g2_font_t0_11b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_te\");\nextern const uint8_t u8g2_font_t0_11b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_mf\");\nextern const uint8_t u8g2_font_t0_11b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_mr\");\nextern const uint8_t u8g2_font_t0_11b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_mn\");\nextern const uint8_t u8g2_font_t0_11b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_11b_me\");\nextern const uint8_t u8g2_font_t0_12_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_tf\");\nextern const uint8_t u8g2_font_t0_12_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_tr\");\nextern const uint8_t u8g2_font_t0_12_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_tn\");\nextern const uint8_t u8g2_font_t0_12_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_te\");\nextern const uint8_t u8g2_font_t0_12_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_mf\");\nextern const uint8_t u8g2_font_t0_12_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_mr\");\nextern const uint8_t u8g2_font_t0_12_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_mn\");\nextern const uint8_t u8g2_font_t0_12_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_12_me\");\nextern const uint8_t u8g2_font_t0_12b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_tf\");\nextern const uint8_t u8g2_font_t0_12b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_tr\");\nextern const uint8_t u8g2_font_t0_12b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_tn\");\nextern const uint8_t u8g2_font_t0_12b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_te\");\nextern const uint8_t u8g2_font_t0_12b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_mf\");\nextern const uint8_t u8g2_font_t0_12b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_mr\");\nextern const uint8_t u8g2_font_t0_12b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_mn\");\nextern const uint8_t u8g2_font_t0_12b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_12b_me\");\nextern const uint8_t u8g2_font_t0_13_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_tf\");\nextern const uint8_t u8g2_font_t0_13_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_tr\");\nextern const uint8_t u8g2_font_t0_13_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_tn\");\nextern const uint8_t u8g2_font_t0_13_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_te\");\nextern const uint8_t u8g2_font_t0_13_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_mf\");\nextern const uint8_t u8g2_font_t0_13_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_mr\");\nextern const uint8_t u8g2_font_t0_13_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_mn\");\nextern const uint8_t u8g2_font_t0_13_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_13_me\");\nextern const uint8_t u8g2_font_t0_13b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_tf\");\nextern const uint8_t u8g2_font_t0_13b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_tr\");\nextern const uint8_t u8g2_font_t0_13b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_tn\");\nextern const uint8_t u8g2_font_t0_13b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_te\");\nextern const uint8_t u8g2_font_t0_13b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_mf\");\nextern const uint8_t u8g2_font_t0_13b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_mr\");\nextern const uint8_t u8g2_font_t0_13b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_mn\");\nextern const uint8_t u8g2_font_t0_13b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_13b_me\");\nextern const uint8_t u8g2_font_t0_14_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_tf\");\nextern const uint8_t u8g2_font_t0_14_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_tr\");\nextern const uint8_t u8g2_font_t0_14_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_tn\");\nextern const uint8_t u8g2_font_t0_14_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_te\");\nextern const uint8_t u8g2_font_t0_14_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_mf\");\nextern const uint8_t u8g2_font_t0_14_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_mr\");\nextern const uint8_t u8g2_font_t0_14_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_mn\");\nextern const uint8_t u8g2_font_t0_14_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_14_me\");\nextern const uint8_t u8g2_font_t0_14b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_tf\");\nextern const uint8_t u8g2_font_t0_14b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_tr\");\nextern const uint8_t u8g2_font_t0_14b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_tn\");\nextern const uint8_t u8g2_font_t0_14b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_te\");\nextern const uint8_t u8g2_font_t0_14b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_mf\");\nextern const uint8_t u8g2_font_t0_14b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_mr\");\nextern const uint8_t u8g2_font_t0_14b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_mn\");\nextern const uint8_t u8g2_font_t0_14b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_14b_me\");\nextern const uint8_t u8g2_font_t0_15_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_tf\");\nextern const uint8_t u8g2_font_t0_15_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_tr\");\nextern const uint8_t u8g2_font_t0_15_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_tn\");\nextern const uint8_t u8g2_font_t0_15_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_te\");\nextern const uint8_t u8g2_font_t0_15_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_mf\");\nextern const uint8_t u8g2_font_t0_15_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_mr\");\nextern const uint8_t u8g2_font_t0_15_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_mn\");\nextern const uint8_t u8g2_font_t0_15_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_15_me\");\nextern const uint8_t u8g2_font_t0_15b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_tf\");\nextern const uint8_t u8g2_font_t0_15b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_tr\");\nextern const uint8_t u8g2_font_t0_15b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_tn\");\nextern const uint8_t u8g2_font_t0_15b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_te\");\nextern const uint8_t u8g2_font_t0_15b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_mf\");\nextern const uint8_t u8g2_font_t0_15b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_mr\");\nextern const uint8_t u8g2_font_t0_15b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_mn\");\nextern const uint8_t u8g2_font_t0_15b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_15b_me\");\nextern const uint8_t u8g2_font_t0_16_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_tf\");\nextern const uint8_t u8g2_font_t0_16_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_tr\");\nextern const uint8_t u8g2_font_t0_16_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_tn\");\nextern const uint8_t u8g2_font_t0_16_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_te\");\nextern const uint8_t u8g2_font_t0_16_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_mf\");\nextern const uint8_t u8g2_font_t0_16_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_mr\");\nextern const uint8_t u8g2_font_t0_16_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_mn\");\nextern const uint8_t u8g2_font_t0_16_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_16_me\");\nextern const uint8_t u8g2_font_t0_16b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_tf\");\nextern const uint8_t u8g2_font_t0_16b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_tr\");\nextern const uint8_t u8g2_font_t0_16b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_tn\");\nextern const uint8_t u8g2_font_t0_16b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_te\");\nextern const uint8_t u8g2_font_t0_16b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_mf\");\nextern const uint8_t u8g2_font_t0_16b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_mr\");\nextern const uint8_t u8g2_font_t0_16b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_mn\");\nextern const uint8_t u8g2_font_t0_16b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_16b_me\");\nextern const uint8_t u8g2_font_t0_17_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_tf\");\nextern const uint8_t u8g2_font_t0_17_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_tr\");\nextern const uint8_t u8g2_font_t0_17_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_tn\");\nextern const uint8_t u8g2_font_t0_17_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_te\");\nextern const uint8_t u8g2_font_t0_17_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_mf\");\nextern const uint8_t u8g2_font_t0_17_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_mr\");\nextern const uint8_t u8g2_font_t0_17_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_mn\");\nextern const uint8_t u8g2_font_t0_17_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_17_me\");\nextern const uint8_t u8g2_font_t0_17b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_tf\");\nextern const uint8_t u8g2_font_t0_17b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_tr\");\nextern const uint8_t u8g2_font_t0_17b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_tn\");\nextern const uint8_t u8g2_font_t0_17b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_te\");\nextern const uint8_t u8g2_font_t0_17b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_mf\");\nextern const uint8_t u8g2_font_t0_17b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_mr\");\nextern const uint8_t u8g2_font_t0_17b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_mn\");\nextern const uint8_t u8g2_font_t0_17b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_17b_me\");\nextern const uint8_t u8g2_font_t0_18_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_tf\");\nextern const uint8_t u8g2_font_t0_18_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_tr\");\nextern const uint8_t u8g2_font_t0_18_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_tn\");\nextern const uint8_t u8g2_font_t0_18_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_te\");\nextern const uint8_t u8g2_font_t0_18_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_mf\");\nextern const uint8_t u8g2_font_t0_18_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_mr\");\nextern const uint8_t u8g2_font_t0_18_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_mn\");\nextern const uint8_t u8g2_font_t0_18_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_18_me\");\nextern const uint8_t u8g2_font_t0_18b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_tf\");\nextern const uint8_t u8g2_font_t0_18b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_tr\");\nextern const uint8_t u8g2_font_t0_18b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_tn\");\nextern const uint8_t u8g2_font_t0_18b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_te\");\nextern const uint8_t u8g2_font_t0_18b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_mf\");\nextern const uint8_t u8g2_font_t0_18b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_mr\");\nextern const uint8_t u8g2_font_t0_18b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_mn\");\nextern const uint8_t u8g2_font_t0_18b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_18b_me\");\nextern const uint8_t u8g2_font_t0_22_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_tf\");\nextern const uint8_t u8g2_font_t0_22_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_tr\");\nextern const uint8_t u8g2_font_t0_22_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_tn\");\nextern const uint8_t u8g2_font_t0_22_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_te\");\nextern const uint8_t u8g2_font_t0_22_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_mf\");\nextern const uint8_t u8g2_font_t0_22_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_mr\");\nextern const uint8_t u8g2_font_t0_22_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_mn\");\nextern const uint8_t u8g2_font_t0_22_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_22_me\");\nextern const uint8_t u8g2_font_t0_22b_tf[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_tf\");\nextern const uint8_t u8g2_font_t0_22b_tr[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_tr\");\nextern const uint8_t u8g2_font_t0_22b_tn[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_tn\");\nextern const uint8_t u8g2_font_t0_22b_te[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_te\");\nextern const uint8_t u8g2_font_t0_22b_mf[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_mf\");\nextern const uint8_t u8g2_font_t0_22b_mr[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_mr\");\nextern const uint8_t u8g2_font_t0_22b_mn[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_mn\");\nextern const uint8_t u8g2_font_t0_22b_me[] U8G2_FONT_SECTION(\"u8g2_font_t0_22b_me\");\nextern const uint8_t u8g2_font_open_iconic_all_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_all_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_app_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_app_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_arrow_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_arrow_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_check_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_check_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_email_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_email_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_embedded_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_embedded_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_gui_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_gui_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_human_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_human_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_mime_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_mime_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_other_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_other_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_play_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_play_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_text_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_text_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_thing_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_thing_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_weather_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_weather_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_www_1x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_www_1x_t\");\nextern const uint8_t u8g2_font_open_iconic_all_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_all_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_app_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_app_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_arrow_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_arrow_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_check_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_check_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_email_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_email_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_embedded_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_embedded_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_gui_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_gui_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_human_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_human_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_mime_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_mime_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_other_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_other_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_play_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_play_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_text_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_text_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_thing_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_thing_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_weather_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_weather_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_www_2x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_www_2x_t\");\nextern const uint8_t u8g2_font_open_iconic_all_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_all_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_app_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_app_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_arrow_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_arrow_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_check_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_check_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_email_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_email_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_embedded_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_embedded_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_gui_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_gui_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_human_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_human_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_mime_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_mime_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_other_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_other_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_play_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_play_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_text_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_text_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_thing_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_thing_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_weather_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_weather_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_www_4x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_www_4x_t\");\nextern const uint8_t u8g2_font_open_iconic_all_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_all_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_app_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_app_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_arrow_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_arrow_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_check_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_check_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_email_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_email_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_embedded_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_embedded_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_gui_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_gui_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_human_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_human_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_mime_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_mime_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_other_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_other_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_play_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_play_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_text_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_text_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_thing_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_thing_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_weather_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_weather_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_www_6x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_www_6x_t\");\nextern const uint8_t u8g2_font_open_iconic_all_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_all_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_app_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_app_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_arrow_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_arrow_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_check_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_check_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_email_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_email_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_embedded_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_embedded_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_gui_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_gui_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_human_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_human_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_mime_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_mime_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_other_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_other_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_play_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_play_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_text_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_text_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_thing_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_thing_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_weather_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_weather_8x_t\");\nextern const uint8_t u8g2_font_open_iconic_www_8x_t[] U8G2_FONT_SECTION(\"u8g2_font_open_iconic_www_8x_t\");\nextern const uint8_t u8g2_font_profont10_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont10_tf\");\nextern const uint8_t u8g2_font_profont10_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont10_tr\");\nextern const uint8_t u8g2_font_profont10_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont10_tn\");\nextern const uint8_t u8g2_font_profont10_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont10_mf\");\nextern const uint8_t u8g2_font_profont10_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont10_mr\");\nextern const uint8_t u8g2_font_profont10_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont10_mn\");\nextern const uint8_t u8g2_font_profont11_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont11_tf\");\nextern const uint8_t u8g2_font_profont11_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont11_tr\");\nextern const uint8_t u8g2_font_profont11_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont11_tn\");\nextern const uint8_t u8g2_font_profont11_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont11_mf\");\nextern const uint8_t u8g2_font_profont11_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont11_mr\");\nextern const uint8_t u8g2_font_profont11_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont11_mn\");\nextern const uint8_t u8g2_font_profont12_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont12_tf\");\nextern const uint8_t u8g2_font_profont12_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont12_tr\");\nextern const uint8_t u8g2_font_profont12_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont12_tn\");\nextern const uint8_t u8g2_font_profont12_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont12_mf\");\nextern const uint8_t u8g2_font_profont12_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont12_mr\");\nextern const uint8_t u8g2_font_profont12_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont12_mn\");\nextern const uint8_t u8g2_font_profont15_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont15_tf\");\nextern const uint8_t u8g2_font_profont15_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont15_tr\");\nextern const uint8_t u8g2_font_profont15_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont15_tn\");\nextern const uint8_t u8g2_font_profont15_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont15_mf\");\nextern const uint8_t u8g2_font_profont15_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont15_mr\");\nextern const uint8_t u8g2_font_profont15_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont15_mn\");\nextern const uint8_t u8g2_font_profont17_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont17_tf\");\nextern const uint8_t u8g2_font_profont17_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont17_tr\");\nextern const uint8_t u8g2_font_profont17_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont17_tn\");\nextern const uint8_t u8g2_font_profont17_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont17_mf\");\nextern const uint8_t u8g2_font_profont17_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont17_mr\");\nextern const uint8_t u8g2_font_profont17_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont17_mn\");\nextern const uint8_t u8g2_font_profont22_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont22_tf\");\nextern const uint8_t u8g2_font_profont22_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont22_tr\");\nextern const uint8_t u8g2_font_profont22_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont22_tn\");\nextern const uint8_t u8g2_font_profont22_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont22_mf\");\nextern const uint8_t u8g2_font_profont22_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont22_mr\");\nextern const uint8_t u8g2_font_profont22_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont22_mn\");\nextern const uint8_t u8g2_font_profont29_tf[] U8G2_FONT_SECTION(\"u8g2_font_profont29_tf\");\nextern const uint8_t u8g2_font_profont29_tr[] U8G2_FONT_SECTION(\"u8g2_font_profont29_tr\");\nextern const uint8_t u8g2_font_profont29_tn[] U8G2_FONT_SECTION(\"u8g2_font_profont29_tn\");\nextern const uint8_t u8g2_font_profont29_mf[] U8G2_FONT_SECTION(\"u8g2_font_profont29_mf\");\nextern const uint8_t u8g2_font_profont29_mr[] U8G2_FONT_SECTION(\"u8g2_font_profont29_mr\");\nextern const uint8_t u8g2_font_profont29_mn[] U8G2_FONT_SECTION(\"u8g2_font_profont29_mn\");\nextern const uint8_t u8g2_font_samim_10_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_10_t_all\");\nextern const uint8_t u8g2_font_samim_12_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_12_t_all\");\nextern const uint8_t u8g2_font_samim_14_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_14_t_all\");\nextern const uint8_t u8g2_font_samim_16_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_16_t_all\");\nextern const uint8_t u8g2_font_samim_fd_10_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_fd_10_t_all\");\nextern const uint8_t u8g2_font_samim_fd_12_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_fd_12_t_all\");\nextern const uint8_t u8g2_font_samim_fd_14_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_fd_14_t_all\");\nextern const uint8_t u8g2_font_samim_fd_16_t_all[] U8G2_FONT_SECTION(\"u8g2_font_samim_fd_16_t_all\");\nextern const uint8_t u8g2_font_ganj_nameh_sans10_t_all[] U8G2_FONT_SECTION(\"u8g2_font_ganj_nameh_sans10_t_all\");\nextern const uint8_t u8g2_font_ganj_nameh_sans12_t_all[] U8G2_FONT_SECTION(\"u8g2_font_ganj_nameh_sans12_t_all\");\nextern const uint8_t u8g2_font_ganj_nameh_sans14_t_all[] U8G2_FONT_SECTION(\"u8g2_font_ganj_nameh_sans14_t_all\");\nextern const uint8_t u8g2_font_ganj_nameh_sans16_t_all[] U8G2_FONT_SECTION(\"u8g2_font_ganj_nameh_sans16_t_all\");\nextern const uint8_t u8g2_font_iranian_sans_8_t_all[] U8G2_FONT_SECTION(\"u8g2_font_iranian_sans_8_t_all\");\nextern const uint8_t u8g2_font_iranian_sans_10_t_all[] U8G2_FONT_SECTION(\"u8g2_font_iranian_sans_10_t_all\");\nextern const uint8_t u8g2_font_iranian_sans_12_t_all[] U8G2_FONT_SECTION(\"u8g2_font_iranian_sans_12_t_all\");\nextern const uint8_t u8g2_font_iranian_sans_14_t_all[] U8G2_FONT_SECTION(\"u8g2_font_iranian_sans_14_t_all\");\nextern const uint8_t u8g2_font_iranian_sans_16_t_all[] U8G2_FONT_SECTION(\"u8g2_font_iranian_sans_16_t_all\");\nextern const uint8_t u8g2_font_mozart_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_mozart_nbp_tf\");\nextern const uint8_t u8g2_font_mozart_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_mozart_nbp_tr\");\nextern const uint8_t u8g2_font_mozart_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_mozart_nbp_tn\");\nextern const uint8_t u8g2_font_mozart_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_mozart_nbp_t_all\");\nextern const uint8_t u8g2_font_mozart_nbp_h_all[] U8G2_FONT_SECTION(\"u8g2_font_mozart_nbp_h_all\");\nextern const uint8_t u8g2_font_glasstown_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_glasstown_nbp_tf\");\nextern const uint8_t u8g2_font_glasstown_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_glasstown_nbp_tr\");\nextern const uint8_t u8g2_font_glasstown_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_glasstown_nbp_tn\");\nextern const uint8_t u8g2_font_glasstown_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_glasstown_nbp_t_all\");\nextern const uint8_t u8g2_font_shylock_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_shylock_nbp_tf\");\nextern const uint8_t u8g2_font_shylock_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_shylock_nbp_tr\");\nextern const uint8_t u8g2_font_shylock_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_shylock_nbp_tn\");\nextern const uint8_t u8g2_font_shylock_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_shylock_nbp_t_all\");\nextern const uint8_t u8g2_font_roentgen_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_roentgen_nbp_tf\");\nextern const uint8_t u8g2_font_roentgen_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_roentgen_nbp_tr\");\nextern const uint8_t u8g2_font_roentgen_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_roentgen_nbp_tn\");\nextern const uint8_t u8g2_font_roentgen_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_roentgen_nbp_t_all\");\nextern const uint8_t u8g2_font_roentgen_nbp_h_all[] U8G2_FONT_SECTION(\"u8g2_font_roentgen_nbp_h_all\");\nextern const uint8_t u8g2_font_calibration_gothic_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_calibration_gothic_nbp_tf\");\nextern const uint8_t u8g2_font_calibration_gothic_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_calibration_gothic_nbp_tr\");\nextern const uint8_t u8g2_font_calibration_gothic_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_calibration_gothic_nbp_tn\");\nextern const uint8_t u8g2_font_calibration_gothic_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_calibration_gothic_nbp_t_all\");\nextern const uint8_t u8g2_font_smart_patrol_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_smart_patrol_nbp_tf\");\nextern const uint8_t u8g2_font_smart_patrol_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_smart_patrol_nbp_tr\");\nextern const uint8_t u8g2_font_smart_patrol_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_smart_patrol_nbp_tn\");\nextern const uint8_t u8g2_font_prospero_bold_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_prospero_bold_nbp_tf\");\nextern const uint8_t u8g2_font_prospero_bold_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_prospero_bold_nbp_tr\");\nextern const uint8_t u8g2_font_prospero_bold_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_prospero_bold_nbp_tn\");\nextern const uint8_t u8g2_font_prospero_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_prospero_nbp_tf\");\nextern const uint8_t u8g2_font_prospero_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_prospero_nbp_tr\");\nextern const uint8_t u8g2_font_prospero_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_prospero_nbp_tn\");\nextern const uint8_t u8g2_font_balthasar_regular_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_regular_nbp_tf\");\nextern const uint8_t u8g2_font_balthasar_regular_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_regular_nbp_tr\");\nextern const uint8_t u8g2_font_balthasar_regular_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_regular_nbp_tn\");\nextern const uint8_t u8g2_font_balthasar_titling_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_titling_nbp_tf\");\nextern const uint8_t u8g2_font_balthasar_titling_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_titling_nbp_tr\");\nextern const uint8_t u8g2_font_balthasar_titling_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_balthasar_titling_nbp_tn\");\nextern const uint8_t u8g2_font_synchronizer_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_synchronizer_nbp_tf\");\nextern const uint8_t u8g2_font_synchronizer_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_synchronizer_nbp_tr\");\nextern const uint8_t u8g2_font_synchronizer_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_synchronizer_nbp_tn\");\nextern const uint8_t u8g2_font_mercutio_basic_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_basic_nbp_tf\");\nextern const uint8_t u8g2_font_mercutio_basic_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_basic_nbp_tr\");\nextern const uint8_t u8g2_font_mercutio_basic_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_basic_nbp_tn\");\nextern const uint8_t u8g2_font_mercutio_basic_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_basic_nbp_t_all\");\nextern const uint8_t u8g2_font_mercutio_sc_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_sc_nbp_tf\");\nextern const uint8_t u8g2_font_mercutio_sc_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_sc_nbp_tr\");\nextern const uint8_t u8g2_font_mercutio_sc_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_sc_nbp_tn\");\nextern const uint8_t u8g2_font_mercutio_sc_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_mercutio_sc_nbp_t_all\");\nextern const uint8_t u8g2_font_miranda_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_miranda_nbp_tf\");\nextern const uint8_t u8g2_font_miranda_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_miranda_nbp_tr\");\nextern const uint8_t u8g2_font_miranda_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_miranda_nbp_tn\");\nextern const uint8_t u8g2_font_nine_by_five_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_nine_by_five_nbp_tf\");\nextern const uint8_t u8g2_font_nine_by_five_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_nine_by_five_nbp_tr\");\nextern const uint8_t u8g2_font_nine_by_five_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_nine_by_five_nbp_tn\");\nextern const uint8_t u8g2_font_nine_by_five_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_nine_by_five_nbp_t_all\");\nextern const uint8_t u8g2_font_rosencrantz_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_rosencrantz_nbp_tf\");\nextern const uint8_t u8g2_font_rosencrantz_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_rosencrantz_nbp_tr\");\nextern const uint8_t u8g2_font_rosencrantz_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_rosencrantz_nbp_tn\");\nextern const uint8_t u8g2_font_rosencrantz_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_rosencrantz_nbp_t_all\");\nextern const uint8_t u8g2_font_guildenstern_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_guildenstern_nbp_tf\");\nextern const uint8_t u8g2_font_guildenstern_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_guildenstern_nbp_tr\");\nextern const uint8_t u8g2_font_guildenstern_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_guildenstern_nbp_tn\");\nextern const uint8_t u8g2_font_guildenstern_nbp_t_all[] U8G2_FONT_SECTION(\"u8g2_font_guildenstern_nbp_t_all\");\nextern const uint8_t u8g2_font_astragal_nbp_tf[] U8G2_FONT_SECTION(\"u8g2_font_astragal_nbp_tf\");\nextern const uint8_t u8g2_font_astragal_nbp_tr[] U8G2_FONT_SECTION(\"u8g2_font_astragal_nbp_tr\");\nextern const uint8_t u8g2_font_astragal_nbp_tn[] U8G2_FONT_SECTION(\"u8g2_font_astragal_nbp_tn\");\nextern const uint8_t u8g2_font_habsburgchancery_tf[] U8G2_FONT_SECTION(\"u8g2_font_habsburgchancery_tf\");\nextern const uint8_t u8g2_font_habsburgchancery_tr[] U8G2_FONT_SECTION(\"u8g2_font_habsburgchancery_tr\");\nextern const uint8_t u8g2_font_habsburgchancery_tn[] U8G2_FONT_SECTION(\"u8g2_font_habsburgchancery_tn\");\nextern const uint8_t u8g2_font_habsburgchancery_t_all[] U8G2_FONT_SECTION(\"u8g2_font_habsburgchancery_t_all\");\nextern const uint8_t u8g2_font_missingplanet_tf[] U8G2_FONT_SECTION(\"u8g2_font_missingplanet_tf\");\nextern const uint8_t u8g2_font_missingplanet_tr[] U8G2_FONT_SECTION(\"u8g2_font_missingplanet_tr\");\nextern const uint8_t u8g2_font_missingplanet_tn[] U8G2_FONT_SECTION(\"u8g2_font_missingplanet_tn\");\nextern const uint8_t u8g2_font_missingplanet_t_all[] U8G2_FONT_SECTION(\"u8g2_font_missingplanet_t_all\");\nextern const uint8_t u8g2_font_ordinarybasis_tf[] U8G2_FONT_SECTION(\"u8g2_font_ordinarybasis_tf\");\nextern const uint8_t u8g2_font_ordinarybasis_tr[] U8G2_FONT_SECTION(\"u8g2_font_ordinarybasis_tr\");\nextern const uint8_t u8g2_font_ordinarybasis_tn[] U8G2_FONT_SECTION(\"u8g2_font_ordinarybasis_tn\");\nextern const uint8_t u8g2_font_ordinarybasis_t_all[] U8G2_FONT_SECTION(\"u8g2_font_ordinarybasis_t_all\");\nextern const uint8_t u8g2_font_pixelmordred_tf[] U8G2_FONT_SECTION(\"u8g2_font_pixelmordred_tf\");\nextern const uint8_t u8g2_font_pixelmordred_tr[] U8G2_FONT_SECTION(\"u8g2_font_pixelmordred_tr\");\nextern const uint8_t u8g2_font_pixelmordred_tn[] U8G2_FONT_SECTION(\"u8g2_font_pixelmordred_tn\");\nextern const uint8_t u8g2_font_pixelmordred_t_all[] U8G2_FONT_SECTION(\"u8g2_font_pixelmordred_t_all\");\nextern const uint8_t u8g2_font_secretaryhand_tf[] U8G2_FONT_SECTION(\"u8g2_font_secretaryhand_tf\");\nextern const uint8_t u8g2_font_secretaryhand_tr[] U8G2_FONT_SECTION(\"u8g2_font_secretaryhand_tr\");\nextern const uint8_t u8g2_font_secretaryhand_tn[] U8G2_FONT_SECTION(\"u8g2_font_secretaryhand_tn\");\nextern const uint8_t u8g2_font_secretaryhand_t_all[] U8G2_FONT_SECTION(\"u8g2_font_secretaryhand_t_all\");\nextern const uint8_t u8g2_font_beanstalk_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_beanstalk_mel_tr\");\nextern const uint8_t u8g2_font_beanstalk_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_beanstalk_mel_tn\");\nextern const uint8_t u8g2_font_cube_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_cube_mel_tr\");\nextern const uint8_t u8g2_font_cube_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_cube_mel_tn\");\nextern const uint8_t u8g2_font_mademoiselle_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_mademoiselle_mel_tr\");\nextern const uint8_t u8g2_font_mademoiselle_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_mademoiselle_mel_tn\");\nextern const uint8_t u8g2_font_pieceofcake_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_pieceofcake_mel_tr\");\nextern const uint8_t u8g2_font_pieceofcake_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_pieceofcake_mel_tn\");\nextern const uint8_t u8g2_font_press_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_press_mel_tr\");\nextern const uint8_t u8g2_font_press_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_press_mel_tn\");\nextern const uint8_t u8g2_font_repress_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_repress_mel_tr\");\nextern const uint8_t u8g2_font_repress_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_repress_mel_tn\");\nextern const uint8_t u8g2_font_sticker_mel_tr[] U8G2_FONT_SECTION(\"u8g2_font_sticker_mel_tr\");\nextern const uint8_t u8g2_font_sticker_mel_tn[] U8G2_FONT_SECTION(\"u8g2_font_sticker_mel_tn\");\nextern const uint8_t u8g2_font_celibatemonk_tr[] U8G2_FONT_SECTION(\"u8g2_font_celibatemonk_tr\");\nextern const uint8_t u8g2_font_disrespectfulteenager_tu[] U8G2_FONT_SECTION(\"u8g2_font_disrespectfulteenager_tu\");\nextern const uint8_t u8g2_font_michaelmouse_tu[] U8G2_FONT_SECTION(\"u8g2_font_michaelmouse_tu\");\nextern const uint8_t u8g2_font_sandyforest_tr[] U8G2_FONT_SECTION(\"u8g2_font_sandyforest_tr\");\nextern const uint8_t u8g2_font_sandyforest_tn[] U8G2_FONT_SECTION(\"u8g2_font_sandyforest_tn\");\nextern const uint8_t u8g2_font_sandyforest_tu[] U8G2_FONT_SECTION(\"u8g2_font_sandyforest_tu\");\nextern const uint8_t u8g2_font_cupcakemetoyourleader_tr[] U8G2_FONT_SECTION(\"u8g2_font_cupcakemetoyourleader_tr\");\nextern const uint8_t u8g2_font_cupcakemetoyourleader_tn[] U8G2_FONT_SECTION(\"u8g2_font_cupcakemetoyourleader_tn\");\nextern const uint8_t u8g2_font_cupcakemetoyourleader_tu[] U8G2_FONT_SECTION(\"u8g2_font_cupcakemetoyourleader_tu\");\nextern const uint8_t u8g2_font_oldwizard_tf[] U8G2_FONT_SECTION(\"u8g2_font_oldwizard_tf\");\nextern const uint8_t u8g2_font_oldwizard_tr[] U8G2_FONT_SECTION(\"u8g2_font_oldwizard_tr\");\nextern const uint8_t u8g2_font_oldwizard_tn[] U8G2_FONT_SECTION(\"u8g2_font_oldwizard_tn\");\nextern const uint8_t u8g2_font_oldwizard_tu[] U8G2_FONT_SECTION(\"u8g2_font_oldwizard_tu\");\nextern const uint8_t u8g2_font_squirrel_tr[] U8G2_FONT_SECTION(\"u8g2_font_squirrel_tr\");\nextern const uint8_t u8g2_font_squirrel_tn[] U8G2_FONT_SECTION(\"u8g2_font_squirrel_tn\");\nextern const uint8_t u8g2_font_squirrel_tu[] U8G2_FONT_SECTION(\"u8g2_font_squirrel_tu\");\nextern const uint8_t u8g2_font_diodesemimono_tr[] U8G2_FONT_SECTION(\"u8g2_font_diodesemimono_tr\");\nextern const uint8_t u8g2_font_questgiver_tr[] U8G2_FONT_SECTION(\"u8g2_font_questgiver_tr\");\nextern const uint8_t u8g2_font_seraphimb1_tr[] U8G2_FONT_SECTION(\"u8g2_font_seraphimb1_tr\");\nextern const uint8_t u8g2_font_jinxedwizards_tr[] U8G2_FONT_SECTION(\"u8g2_font_jinxedwizards_tr\");\nextern const uint8_t u8g2_font_lastpriestess_tr[] U8G2_FONT_SECTION(\"u8g2_font_lastpriestess_tr\");\nextern const uint8_t u8g2_font_lastpriestess_tu[] U8G2_FONT_SECTION(\"u8g2_font_lastpriestess_tu\");\nextern const uint8_t u8g2_font_bitcasual_tf[] U8G2_FONT_SECTION(\"u8g2_font_bitcasual_tf\");\nextern const uint8_t u8g2_font_bitcasual_tr[] U8G2_FONT_SECTION(\"u8g2_font_bitcasual_tr\");\nextern const uint8_t u8g2_font_bitcasual_tn[] U8G2_FONT_SECTION(\"u8g2_font_bitcasual_tn\");\nextern const uint8_t u8g2_font_bitcasual_tu[] U8G2_FONT_SECTION(\"u8g2_font_bitcasual_tu\");\nextern const uint8_t u8g2_font_bitcasual_t_all[] U8G2_FONT_SECTION(\"u8g2_font_bitcasual_t_all\");\nextern const uint8_t u8g2_font_koleeko_tf[] U8G2_FONT_SECTION(\"u8g2_font_koleeko_tf\");\nextern const uint8_t u8g2_font_koleeko_tr[] U8G2_FONT_SECTION(\"u8g2_font_koleeko_tr\");\nextern const uint8_t u8g2_font_koleeko_tn[] U8G2_FONT_SECTION(\"u8g2_font_koleeko_tn\");\nextern const uint8_t u8g2_font_koleeko_tu[] U8G2_FONT_SECTION(\"u8g2_font_koleeko_tu\");\nextern const uint8_t u8g2_font_tenfatguys_tf[] U8G2_FONT_SECTION(\"u8g2_font_tenfatguys_tf\");\nextern const uint8_t u8g2_font_tenfatguys_tr[] U8G2_FONT_SECTION(\"u8g2_font_tenfatguys_tr\");\nextern const uint8_t u8g2_font_tenfatguys_tn[] U8G2_FONT_SECTION(\"u8g2_font_tenfatguys_tn\");\nextern const uint8_t u8g2_font_tenfatguys_tu[] U8G2_FONT_SECTION(\"u8g2_font_tenfatguys_tu\");\nextern const uint8_t u8g2_font_tenfatguys_t_all[] U8G2_FONT_SECTION(\"u8g2_font_tenfatguys_t_all\");\nextern const uint8_t u8g2_font_tenstamps_mf[] U8G2_FONT_SECTION(\"u8g2_font_tenstamps_mf\");\nextern const uint8_t u8g2_font_tenstamps_mr[] U8G2_FONT_SECTION(\"u8g2_font_tenstamps_mr\");\nextern const uint8_t u8g2_font_tenstamps_mn[] U8G2_FONT_SECTION(\"u8g2_font_tenstamps_mn\");\nextern const uint8_t u8g2_font_tenstamps_mu[] U8G2_FONT_SECTION(\"u8g2_font_tenstamps_mu\");\nextern const uint8_t u8g2_font_tenthinguys_tf[] U8G2_FONT_SECTION(\"u8g2_font_tenthinguys_tf\");\nextern const uint8_t u8g2_font_tenthinguys_tr[] U8G2_FONT_SECTION(\"u8g2_font_tenthinguys_tr\");\nextern const uint8_t u8g2_font_tenthinguys_tn[] U8G2_FONT_SECTION(\"u8g2_font_tenthinguys_tn\");\nextern const uint8_t u8g2_font_tenthinguys_tu[] U8G2_FONT_SECTION(\"u8g2_font_tenthinguys_tu\");\nextern const uint8_t u8g2_font_tenthinguys_t_all[] U8G2_FONT_SECTION(\"u8g2_font_tenthinguys_t_all\");\nextern const uint8_t u8g2_font_tenthinnerguys_tf[] U8G2_FONT_SECTION(\"u8g2_font_tenthinnerguys_tf\");\nextern const uint8_t u8g2_font_tenthinnerguys_tr[] U8G2_FONT_SECTION(\"u8g2_font_tenthinnerguys_tr\");\nextern const uint8_t u8g2_font_tenthinnerguys_tn[] U8G2_FONT_SECTION(\"u8g2_font_tenthinnerguys_tn\");\nextern const uint8_t u8g2_font_tenthinnerguys_tu[] U8G2_FONT_SECTION(\"u8g2_font_tenthinnerguys_tu\");\nextern const uint8_t u8g2_font_tenthinnerguys_t_all[] U8G2_FONT_SECTION(\"u8g2_font_tenthinnerguys_t_all\");\nextern const uint8_t u8g2_font_twelvedings_t_all[] U8G2_FONT_SECTION(\"u8g2_font_twelvedings_t_all\");\nextern const uint8_t u8g2_font_fewture_tf[] U8G2_FONT_SECTION(\"u8g2_font_fewture_tf\");\nextern const uint8_t u8g2_font_fewture_tr[] U8G2_FONT_SECTION(\"u8g2_font_fewture_tr\");\nextern const uint8_t u8g2_font_fewture_tn[] U8G2_FONT_SECTION(\"u8g2_font_fewture_tn\");\nextern const uint8_t u8g2_font_halftone_tf[] U8G2_FONT_SECTION(\"u8g2_font_halftone_tf\");\nextern const uint8_t u8g2_font_halftone_tr[] U8G2_FONT_SECTION(\"u8g2_font_halftone_tr\");\nextern const uint8_t u8g2_font_halftone_tn[] U8G2_FONT_SECTION(\"u8g2_font_halftone_tn\");\nextern const uint8_t u8g2_font_nerhoe_tf[] U8G2_FONT_SECTION(\"u8g2_font_nerhoe_tf\");\nextern const uint8_t u8g2_font_nerhoe_tr[] U8G2_FONT_SECTION(\"u8g2_font_nerhoe_tr\");\nextern const uint8_t u8g2_font_nerhoe_tn[] U8G2_FONT_SECTION(\"u8g2_font_nerhoe_tn\");\nextern const uint8_t u8g2_font_oskool_tf[] U8G2_FONT_SECTION(\"u8g2_font_oskool_tf\");\nextern const uint8_t u8g2_font_oskool_tr[] U8G2_FONT_SECTION(\"u8g2_font_oskool_tr\");\nextern const uint8_t u8g2_font_oskool_tn[] U8G2_FONT_SECTION(\"u8g2_font_oskool_tn\");\nextern const uint8_t u8g2_font_tinytim_tf[] U8G2_FONT_SECTION(\"u8g2_font_tinytim_tf\");\nextern const uint8_t u8g2_font_tinytim_tr[] U8G2_FONT_SECTION(\"u8g2_font_tinytim_tr\");\nextern const uint8_t u8g2_font_tinytim_tn[] U8G2_FONT_SECTION(\"u8g2_font_tinytim_tn\");\nextern const uint8_t u8g2_font_tooseornament_tf[] U8G2_FONT_SECTION(\"u8g2_font_tooseornament_tf\");\nextern const uint8_t u8g2_font_tooseornament_tr[] U8G2_FONT_SECTION(\"u8g2_font_tooseornament_tr\");\nextern const uint8_t u8g2_font_tooseornament_tn[] U8G2_FONT_SECTION(\"u8g2_font_tooseornament_tn\");\nextern const uint8_t u8g2_font_bauhaus2015_tr[] U8G2_FONT_SECTION(\"u8g2_font_bauhaus2015_tr\");\nextern const uint8_t u8g2_font_bauhaus2015_tn[] U8G2_FONT_SECTION(\"u8g2_font_bauhaus2015_tn\");\nextern const uint8_t u8g2_font_finderskeepers_tf[] U8G2_FONT_SECTION(\"u8g2_font_finderskeepers_tf\");\nextern const uint8_t u8g2_font_finderskeepers_tr[] U8G2_FONT_SECTION(\"u8g2_font_finderskeepers_tr\");\nextern const uint8_t u8g2_font_finderskeepers_tn[] U8G2_FONT_SECTION(\"u8g2_font_finderskeepers_tn\");\nextern const uint8_t u8g2_font_sirclivethebold_tr[] U8G2_FONT_SECTION(\"u8g2_font_sirclivethebold_tr\");\nextern const uint8_t u8g2_font_sirclivethebold_tn[] U8G2_FONT_SECTION(\"u8g2_font_sirclivethebold_tn\");\nextern const uint8_t u8g2_font_sirclive_tr[] U8G2_FONT_SECTION(\"u8g2_font_sirclive_tr\");\nextern const uint8_t u8g2_font_sirclive_tn[] U8G2_FONT_SECTION(\"u8g2_font_sirclive_tn\");\nextern const uint8_t u8g2_font_adventurer_tf[] U8G2_FONT_SECTION(\"u8g2_font_adventurer_tf\");\nextern const uint8_t u8g2_font_adventurer_tr[] U8G2_FONT_SECTION(\"u8g2_font_adventurer_tr\");\nextern const uint8_t u8g2_font_adventurer_t_all[] U8G2_FONT_SECTION(\"u8g2_font_adventurer_t_all\");\nextern const uint8_t u8g2_font_bracketedbabies_tr[] U8G2_FONT_SECTION(\"u8g2_font_bracketedbabies_tr\");\nextern const uint8_t u8g2_font_frikativ_tf[] U8G2_FONT_SECTION(\"u8g2_font_frikativ_tf\");\nextern const uint8_t u8g2_font_frikativ_tr[] U8G2_FONT_SECTION(\"u8g2_font_frikativ_tr\");\nextern const uint8_t u8g2_font_frikativ_t_all[] U8G2_FONT_SECTION(\"u8g2_font_frikativ_t_all\");\nextern const uint8_t u8g2_font_fancypixels_tf[] U8G2_FONT_SECTION(\"u8g2_font_fancypixels_tf\");\nextern const uint8_t u8g2_font_fancypixels_tr[] U8G2_FONT_SECTION(\"u8g2_font_fancypixels_tr\");\nextern const uint8_t u8g2_font_heavybottom_tr[] U8G2_FONT_SECTION(\"u8g2_font_heavybottom_tr\");\nextern const uint8_t u8g2_font_iconquadpix_m_all[] U8G2_FONT_SECTION(\"u8g2_font_iconquadpix_m_all\");\nextern const uint8_t u8g2_font_lastapprenticebold_tr[] U8G2_FONT_SECTION(\"u8g2_font_lastapprenticebold_tr\");\nextern const uint8_t u8g2_font_lastapprenticethin_tr[] U8G2_FONT_SECTION(\"u8g2_font_lastapprenticethin_tr\");\nextern const uint8_t u8g2_font_tallpix_tr[] U8G2_FONT_SECTION(\"u8g2_font_tallpix_tr\");\nextern const uint8_t u8g2_font_BBSesque_tf[] U8G2_FONT_SECTION(\"u8g2_font_BBSesque_tf\");\nextern const uint8_t u8g2_font_BBSesque_tr[] U8G2_FONT_SECTION(\"u8g2_font_BBSesque_tr\");\nextern const uint8_t u8g2_font_BBSesque_te[] U8G2_FONT_SECTION(\"u8g2_font_BBSesque_te\");\nextern const uint8_t u8g2_font_Born2bSportySlab_tf[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportySlab_tf\");\nextern const uint8_t u8g2_font_Born2bSportySlab_tr[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportySlab_tr\");\nextern const uint8_t u8g2_font_Born2bSportySlab_te[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportySlab_te\");\nextern const uint8_t u8g2_font_Born2bSportySlab_t_all[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportySlab_t_all\");\nextern const uint8_t u8g2_font_Born2bSportyV2_tf[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportyV2_tf\");\nextern const uint8_t u8g2_font_Born2bSportyV2_tr[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportyV2_tr\");\nextern const uint8_t u8g2_font_Born2bSportyV2_te[] U8G2_FONT_SECTION(\"u8g2_font_Born2bSportyV2_te\");\nextern const uint8_t u8g2_font_CursivePixel_tr[] U8G2_FONT_SECTION(\"u8g2_font_CursivePixel_tr\");\nextern const uint8_t u8g2_font_Engrish_tf[] U8G2_FONT_SECTION(\"u8g2_font_Engrish_tf\");\nextern const uint8_t u8g2_font_Engrish_tr[] U8G2_FONT_SECTION(\"u8g2_font_Engrish_tr\");\nextern const uint8_t u8g2_font_ImpactBits_tr[] U8G2_FONT_SECTION(\"u8g2_font_ImpactBits_tr\");\nextern const uint8_t u8g2_font_IPAandRUSLCD_tf[] U8G2_FONT_SECTION(\"u8g2_font_IPAandRUSLCD_tf\");\nextern const uint8_t u8g2_font_IPAandRUSLCD_tr[] U8G2_FONT_SECTION(\"u8g2_font_IPAandRUSLCD_tr\");\nextern const uint8_t u8g2_font_IPAandRUSLCD_te[] U8G2_FONT_SECTION(\"u8g2_font_IPAandRUSLCD_te\");\nextern const uint8_t u8g2_font_HelvetiPixel_tr[] U8G2_FONT_SECTION(\"u8g2_font_HelvetiPixel_tr\");\nextern const uint8_t u8g2_font_TimesNewPixel_tr[] U8G2_FONT_SECTION(\"u8g2_font_TimesNewPixel_tr\");\nextern const uint8_t u8g2_font_BitTypeWriter_tr[] U8G2_FONT_SECTION(\"u8g2_font_BitTypeWriter_tr\");\nextern const uint8_t u8g2_font_BitTypeWriter_te[] U8G2_FONT_SECTION(\"u8g2_font_BitTypeWriter_te\");\nextern const uint8_t u8g2_font_Georgia7px_tf[] U8G2_FONT_SECTION(\"u8g2_font_Georgia7px_tf\");\nextern const uint8_t u8g2_font_Georgia7px_tr[] U8G2_FONT_SECTION(\"u8g2_font_Georgia7px_tr\");\nextern const uint8_t u8g2_font_Georgia7px_te[] U8G2_FONT_SECTION(\"u8g2_font_Georgia7px_te\");\nextern const uint8_t u8g2_font_Wizzard_tr[] U8G2_FONT_SECTION(\"u8g2_font_Wizzard_tr\");\nextern const uint8_t u8g2_font_HelvetiPixelOutline_tr[] U8G2_FONT_SECTION(\"u8g2_font_HelvetiPixelOutline_tr\");\nextern const uint8_t u8g2_font_HelvetiPixelOutline_te[] U8G2_FONT_SECTION(\"u8g2_font_HelvetiPixelOutline_te\");\nextern const uint8_t u8g2_font_Untitled16PixelSansSerifBitmap_tr[] U8G2_FONT_SECTION(\"u8g2_font_Untitled16PixelSansSerifBitmap_tr\");\nextern const uint8_t u8g2_font_nokiafc22_tf[] U8G2_FONT_SECTION(\"u8g2_font_nokiafc22_tf\");\nextern const uint8_t u8g2_font_nokiafc22_tr[] U8G2_FONT_SECTION(\"u8g2_font_nokiafc22_tr\");\nextern const uint8_t u8g2_font_nokiafc22_tn[] U8G2_FONT_SECTION(\"u8g2_font_nokiafc22_tn\");\nextern const uint8_t u8g2_font_nokiafc22_tu[] U8G2_FONT_SECTION(\"u8g2_font_nokiafc22_tu\");\nextern const uint8_t u8g2_font_VCR_OSD_tf[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_tf\");\nextern const uint8_t u8g2_font_VCR_OSD_tr[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_tr\");\nextern const uint8_t u8g2_font_VCR_OSD_tn[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_tn\");\nextern const uint8_t u8g2_font_VCR_OSD_tu[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_tu\");\nextern const uint8_t u8g2_font_VCR_OSD_mf[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_mf\");\nextern const uint8_t u8g2_font_VCR_OSD_mr[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_mr\");\nextern const uint8_t u8g2_font_VCR_OSD_mn[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_mn\");\nextern const uint8_t u8g2_font_VCR_OSD_mu[] U8G2_FONT_SECTION(\"u8g2_font_VCR_OSD_mu\");\nextern const uint8_t u8g2_font_Pixellari_tf[] U8G2_FONT_SECTION(\"u8g2_font_Pixellari_tf\");\nextern const uint8_t u8g2_font_Pixellari_tr[] U8G2_FONT_SECTION(\"u8g2_font_Pixellari_tr\");\nextern const uint8_t u8g2_font_Pixellari_tn[] U8G2_FONT_SECTION(\"u8g2_font_Pixellari_tn\");\nextern const uint8_t u8g2_font_Pixellari_tu[] U8G2_FONT_SECTION(\"u8g2_font_Pixellari_tu\");\nextern const uint8_t u8g2_font_Pixellari_te[] U8G2_FONT_SECTION(\"u8g2_font_Pixellari_te\");\nextern const uint8_t u8g2_font_pixelpoiiz_tr[] U8G2_FONT_SECTION(\"u8g2_font_pixelpoiiz_tr\");\nextern const uint8_t u8g2_font_DigitalDiscoThin_tf[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDiscoThin_tf\");\nextern const uint8_t u8g2_font_DigitalDiscoThin_tr[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDiscoThin_tr\");\nextern const uint8_t u8g2_font_DigitalDiscoThin_tn[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDiscoThin_tn\");\nextern const uint8_t u8g2_font_DigitalDiscoThin_tu[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDiscoThin_tu\");\nextern const uint8_t u8g2_font_DigitalDiscoThin_te[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDiscoThin_te\");\nextern const uint8_t u8g2_font_DigitalDisco_tf[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDisco_tf\");\nextern const uint8_t u8g2_font_DigitalDisco_tr[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDisco_tr\");\nextern const uint8_t u8g2_font_DigitalDisco_tn[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDisco_tn\");\nextern const uint8_t u8g2_font_DigitalDisco_tu[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDisco_tu\");\nextern const uint8_t u8g2_font_DigitalDisco_te[] U8G2_FONT_SECTION(\"u8g2_font_DigitalDisco_te\");\nextern const uint8_t u8g2_font_pearfont_tr[] U8G2_FONT_SECTION(\"u8g2_font_pearfont_tr\");\nextern const uint8_t u8g2_font_etl14thai_t[] U8G2_FONT_SECTION(\"u8g2_font_etl14thai_t\");\nextern const uint8_t u8g2_font_etl16thai_t[] U8G2_FONT_SECTION(\"u8g2_font_etl16thai_t\");\nextern const uint8_t u8g2_font_etl24thai_t[] U8G2_FONT_SECTION(\"u8g2_font_etl24thai_t\");\nextern const uint8_t u8g2_font_crox1cb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_tf\");\nextern const uint8_t u8g2_font_crox1cb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_tr\");\nextern const uint8_t u8g2_font_crox1cb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_tn\");\nextern const uint8_t u8g2_font_crox1cb_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_mf\");\nextern const uint8_t u8g2_font_crox1cb_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_mr\");\nextern const uint8_t u8g2_font_crox1cb_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox1cb_mn\");\nextern const uint8_t u8g2_font_crox1c_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_tf\");\nextern const uint8_t u8g2_font_crox1c_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_tr\");\nextern const uint8_t u8g2_font_crox1c_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_tn\");\nextern const uint8_t u8g2_font_crox1c_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_mf\");\nextern const uint8_t u8g2_font_crox1c_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_mr\");\nextern const uint8_t u8g2_font_crox1c_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox1c_mn\");\nextern const uint8_t u8g2_font_crox1hb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1hb_tf\");\nextern const uint8_t u8g2_font_crox1hb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1hb_tr\");\nextern const uint8_t u8g2_font_crox1hb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1hb_tn\");\nextern const uint8_t u8g2_font_crox1h_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1h_tf\");\nextern const uint8_t u8g2_font_crox1h_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1h_tr\");\nextern const uint8_t u8g2_font_crox1h_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1h_tn\");\nextern const uint8_t u8g2_font_crox1tb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1tb_tf\");\nextern const uint8_t u8g2_font_crox1tb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1tb_tr\");\nextern const uint8_t u8g2_font_crox1tb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1tb_tn\");\nextern const uint8_t u8g2_font_crox1t_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox1t_tf\");\nextern const uint8_t u8g2_font_crox1t_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox1t_tr\");\nextern const uint8_t u8g2_font_crox1t_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox1t_tn\");\nextern const uint8_t u8g2_font_crox2cb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_tf\");\nextern const uint8_t u8g2_font_crox2cb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_tr\");\nextern const uint8_t u8g2_font_crox2cb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_tn\");\nextern const uint8_t u8g2_font_crox2cb_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_mf\");\nextern const uint8_t u8g2_font_crox2cb_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_mr\");\nextern const uint8_t u8g2_font_crox2cb_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox2cb_mn\");\nextern const uint8_t u8g2_font_crox2c_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_tf\");\nextern const uint8_t u8g2_font_crox2c_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_tr\");\nextern const uint8_t u8g2_font_crox2c_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_tn\");\nextern const uint8_t u8g2_font_crox2c_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_mf\");\nextern const uint8_t u8g2_font_crox2c_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_mr\");\nextern const uint8_t u8g2_font_crox2c_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox2c_mn\");\nextern const uint8_t u8g2_font_crox2hb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2hb_tf\");\nextern const uint8_t u8g2_font_crox2hb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2hb_tr\");\nextern const uint8_t u8g2_font_crox2hb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2hb_tn\");\nextern const uint8_t u8g2_font_crox2h_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2h_tf\");\nextern const uint8_t u8g2_font_crox2h_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2h_tr\");\nextern const uint8_t u8g2_font_crox2h_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2h_tn\");\nextern const uint8_t u8g2_font_crox2tb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2tb_tf\");\nextern const uint8_t u8g2_font_crox2tb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2tb_tr\");\nextern const uint8_t u8g2_font_crox2tb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2tb_tn\");\nextern const uint8_t u8g2_font_crox2t_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox2t_tf\");\nextern const uint8_t u8g2_font_crox2t_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox2t_tr\");\nextern const uint8_t u8g2_font_crox2t_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox2t_tn\");\nextern const uint8_t u8g2_font_crox3cb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_tf\");\nextern const uint8_t u8g2_font_crox3cb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_tr\");\nextern const uint8_t u8g2_font_crox3cb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_tn\");\nextern const uint8_t u8g2_font_crox3cb_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_mf\");\nextern const uint8_t u8g2_font_crox3cb_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_mr\");\nextern const uint8_t u8g2_font_crox3cb_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox3cb_mn\");\nextern const uint8_t u8g2_font_crox3c_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_tf\");\nextern const uint8_t u8g2_font_crox3c_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_tr\");\nextern const uint8_t u8g2_font_crox3c_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_tn\");\nextern const uint8_t u8g2_font_crox3c_mf[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_mf\");\nextern const uint8_t u8g2_font_crox3c_mr[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_mr\");\nextern const uint8_t u8g2_font_crox3c_mn[] U8G2_FONT_SECTION(\"u8g2_font_crox3c_mn\");\nextern const uint8_t u8g2_font_crox3hb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3hb_tf\");\nextern const uint8_t u8g2_font_crox3hb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3hb_tr\");\nextern const uint8_t u8g2_font_crox3hb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3hb_tn\");\nextern const uint8_t u8g2_font_crox3h_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3h_tf\");\nextern const uint8_t u8g2_font_crox3h_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3h_tr\");\nextern const uint8_t u8g2_font_crox3h_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3h_tn\");\nextern const uint8_t u8g2_font_crox3tb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3tb_tf\");\nextern const uint8_t u8g2_font_crox3tb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3tb_tr\");\nextern const uint8_t u8g2_font_crox3tb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3tb_tn\");\nextern const uint8_t u8g2_font_crox3t_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox3t_tf\");\nextern const uint8_t u8g2_font_crox3t_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox3t_tr\");\nextern const uint8_t u8g2_font_crox3t_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox3t_tn\");\nextern const uint8_t u8g2_font_crox4hb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox4hb_tf\");\nextern const uint8_t u8g2_font_crox4hb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox4hb_tr\");\nextern const uint8_t u8g2_font_crox4hb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox4hb_tn\");\nextern const uint8_t u8g2_font_crox4h_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox4h_tf\");\nextern const uint8_t u8g2_font_crox4h_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox4h_tr\");\nextern const uint8_t u8g2_font_crox4h_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox4h_tn\");\nextern const uint8_t u8g2_font_crox4tb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox4tb_tf\");\nextern const uint8_t u8g2_font_crox4tb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox4tb_tr\");\nextern const uint8_t u8g2_font_crox4tb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox4tb_tn\");\nextern const uint8_t u8g2_font_crox4t_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox4t_tf\");\nextern const uint8_t u8g2_font_crox4t_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox4t_tr\");\nextern const uint8_t u8g2_font_crox4t_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox4t_tn\");\nextern const uint8_t u8g2_font_crox5hb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox5hb_tf\");\nextern const uint8_t u8g2_font_crox5hb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox5hb_tr\");\nextern const uint8_t u8g2_font_crox5hb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox5hb_tn\");\nextern const uint8_t u8g2_font_crox5h_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox5h_tf\");\nextern const uint8_t u8g2_font_crox5h_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox5h_tr\");\nextern const uint8_t u8g2_font_crox5h_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox5h_tn\");\nextern const uint8_t u8g2_font_crox5tb_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox5tb_tf\");\nextern const uint8_t u8g2_font_crox5tb_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox5tb_tr\");\nextern const uint8_t u8g2_font_crox5tb_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox5tb_tn\");\nextern const uint8_t u8g2_font_crox5t_tf[] U8G2_FONT_SECTION(\"u8g2_font_crox5t_tf\");\nextern const uint8_t u8g2_font_crox5t_tr[] U8G2_FONT_SECTION(\"u8g2_font_crox5t_tr\");\nextern const uint8_t u8g2_font_crox5t_tn[] U8G2_FONT_SECTION(\"u8g2_font_crox5t_tn\");\nextern const uint8_t u8g2_font_cu12_tf[] U8G2_FONT_SECTION(\"u8g2_font_cu12_tf\");\nextern const uint8_t u8g2_font_cu12_tr[] U8G2_FONT_SECTION(\"u8g2_font_cu12_tr\");\nextern const uint8_t u8g2_font_cu12_tn[] U8G2_FONT_SECTION(\"u8g2_font_cu12_tn\");\nextern const uint8_t u8g2_font_cu12_te[] U8G2_FONT_SECTION(\"u8g2_font_cu12_te\");\nextern const uint8_t u8g2_font_cu12_hf[] U8G2_FONT_SECTION(\"u8g2_font_cu12_hf\");\nextern const uint8_t u8g2_font_cu12_hr[] U8G2_FONT_SECTION(\"u8g2_font_cu12_hr\");\nextern const uint8_t u8g2_font_cu12_hn[] U8G2_FONT_SECTION(\"u8g2_font_cu12_hn\");\nextern const uint8_t u8g2_font_cu12_he[] U8G2_FONT_SECTION(\"u8g2_font_cu12_he\");\nextern const uint8_t u8g2_font_cu12_mf[] U8G2_FONT_SECTION(\"u8g2_font_cu12_mf\");\nextern const uint8_t u8g2_font_cu12_mr[] U8G2_FONT_SECTION(\"u8g2_font_cu12_mr\");\nextern const uint8_t u8g2_font_cu12_mn[] U8G2_FONT_SECTION(\"u8g2_font_cu12_mn\");\nextern const uint8_t u8g2_font_cu12_me[] U8G2_FONT_SECTION(\"u8g2_font_cu12_me\");\nextern const uint8_t u8g2_font_cu12_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_symbols\");\nextern const uint8_t u8g2_font_cu12_h_symbols[] U8G2_FONT_SECTION(\"u8g2_font_cu12_h_symbols\");\nextern const uint8_t u8g2_font_cu12_t_greek[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_greek\");\nextern const uint8_t u8g2_font_cu12_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_cyrillic\");\nextern const uint8_t u8g2_font_cu12_t_tibetan[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_tibetan\");\nextern const uint8_t u8g2_font_cu12_t_hebrew[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_hebrew\");\nextern const uint8_t u8g2_font_cu12_t_arabic[] U8G2_FONT_SECTION(\"u8g2_font_cu12_t_arabic\");\nextern const uint8_t u8g2_font_unifont_tf[] U8G2_FONT_SECTION(\"u8g2_font_unifont_tf\");\nextern const uint8_t u8g2_font_unifont_tr[] U8G2_FONT_SECTION(\"u8g2_font_unifont_tr\");\nextern const uint8_t u8g2_font_unifont_te[] U8G2_FONT_SECTION(\"u8g2_font_unifont_te\");\nextern const uint8_t u8g2_font_unifont_t_latin[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_latin\");\nextern const uint8_t u8g2_font_unifont_t_extended[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_extended\");\nextern const uint8_t u8g2_font_unifont_t_72_73[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_72_73\");\nextern const uint8_t u8g2_font_unifont_t_0_72_73[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_72_73\");\nextern const uint8_t u8g2_font_unifont_t_75[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_75\");\nextern const uint8_t u8g2_font_unifont_t_0_75[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_75\");\nextern const uint8_t u8g2_font_unifont_t_76[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_76\");\nextern const uint8_t u8g2_font_unifont_t_0_76[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_76\");\nextern const uint8_t u8g2_font_unifont_t_77[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_77\");\nextern const uint8_t u8g2_font_unifont_t_0_77[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_77\");\nextern const uint8_t u8g2_font_unifont_t_78_79[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_78_79\");\nextern const uint8_t u8g2_font_unifont_t_0_78_79[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_78_79\");\nextern const uint8_t u8g2_font_unifont_t_86[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_86\");\nextern const uint8_t u8g2_font_unifont_t_0_86[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_0_86\");\nextern const uint8_t u8g2_font_unifont_t_greek[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_greek\");\nextern const uint8_t u8g2_font_unifont_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_cyrillic\");\nextern const uint8_t u8g2_font_unifont_t_hebrew[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_hebrew\");\nextern const uint8_t u8g2_font_unifont_t_bengali[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_bengali\");\nextern const uint8_t u8g2_font_unifont_t_tibetan[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_tibetan\");\nextern const uint8_t u8g2_font_unifont_t_urdu[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_urdu\");\nextern const uint8_t u8g2_font_unifont_t_polish[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_polish\");\nextern const uint8_t u8g2_font_unifont_t_devanagari[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_devanagari\");\nextern const uint8_t u8g2_font_unifont_t_arabic[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_arabic\");\nextern const uint8_t u8g2_font_unifont_t_symbols[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_symbols\");\nextern const uint8_t u8g2_font_unifont_h_symbols[] U8G2_FONT_SECTION(\"u8g2_font_unifont_h_symbols\");\nextern const uint8_t u8g2_font_unifont_t_emoticons[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_emoticons\");\nextern const uint8_t u8g2_font_unifont_t_animals[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_animals\");\nextern const uint8_t u8g2_font_unifont_t_domino[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_domino\");\nextern const uint8_t u8g2_font_unifont_t_cards[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_cards\");\nextern const uint8_t u8g2_font_unifont_t_weather[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_weather\");\nextern const uint8_t u8g2_font_unifont_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_chinese1\");\nextern const uint8_t u8g2_font_unifont_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_chinese2\");\nextern const uint8_t u8g2_font_unifont_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_chinese3\");\nextern const uint8_t u8g2_font_unifont_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_japanese1\");\nextern const uint8_t u8g2_font_unifont_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_japanese2\");\nextern const uint8_t u8g2_font_unifont_t_japanese3[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_japanese3\");\nextern const uint8_t u8g2_font_unifont_t_korean1[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_korean1\");\nextern const uint8_t u8g2_font_unifont_t_korean2[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_korean2\");\nextern const uint8_t u8g2_font_unifont_t_vietnamese1[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_vietnamese1\");\nextern const uint8_t u8g2_font_unifont_t_vietnamese2[] U8G2_FONT_SECTION(\"u8g2_font_unifont_t_vietnamese2\");\nextern const uint8_t u8g2_font_gb16st_t_1[] U8G2_FONT_SECTION(\"u8g2_font_gb16st_t_1\");\nextern const uint8_t u8g2_font_gb16st_t_2[] U8G2_FONT_SECTION(\"u8g2_font_gb16st_t_2\");\nextern const uint8_t u8g2_font_gb16st_t_3[] U8G2_FONT_SECTION(\"u8g2_font_gb16st_t_3\");\nextern const uint8_t u8g2_font_gb24st_t_1[] U8G2_FONT_SECTION(\"u8g2_font_gb24st_t_1\");\nextern const uint8_t u8g2_font_gb24st_t_2[] U8G2_FONT_SECTION(\"u8g2_font_gb24st_t_2\");\nextern const uint8_t u8g2_font_gb24st_t_3[] U8G2_FONT_SECTION(\"u8g2_font_gb24st_t_3\");\nextern const uint8_t u8g2_font_wqy12_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_chinese1\");\nextern const uint8_t u8g2_font_wqy12_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_chinese2\");\nextern const uint8_t u8g2_font_wqy12_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_chinese3\");\nextern const uint8_t u8g2_font_wqy12_t_gb2312[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_gb2312\");\nextern const uint8_t u8g2_font_wqy12_t_gb2312a[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_gb2312a\");\nextern const uint8_t u8g2_font_wqy12_t_gb2312b[] U8G2_FONT_SECTION(\"u8g2_font_wqy12_t_gb2312b\");\nextern const uint8_t u8g2_font_wqy13_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_chinese1\");\nextern const uint8_t u8g2_font_wqy13_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_chinese2\");\nextern const uint8_t u8g2_font_wqy13_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_chinese3\");\nextern const uint8_t u8g2_font_wqy13_t_gb2312[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_gb2312\");\nextern const uint8_t u8g2_font_wqy13_t_gb2312a[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_gb2312a\");\nextern const uint8_t u8g2_font_wqy13_t_gb2312b[] U8G2_FONT_SECTION(\"u8g2_font_wqy13_t_gb2312b\");\nextern const uint8_t u8g2_font_wqy14_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_chinese1\");\nextern const uint8_t u8g2_font_wqy14_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_chinese2\");\nextern const uint8_t u8g2_font_wqy14_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_chinese3\");\nextern const uint8_t u8g2_font_wqy14_t_gb2312[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_gb2312\");\nextern const uint8_t u8g2_font_wqy14_t_gb2312a[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_gb2312a\");\nextern const uint8_t u8g2_font_wqy14_t_gb2312b[] U8G2_FONT_SECTION(\"u8g2_font_wqy14_t_gb2312b\");\nextern const uint8_t u8g2_font_wqy15_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_chinese1\");\nextern const uint8_t u8g2_font_wqy15_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_chinese2\");\nextern const uint8_t u8g2_font_wqy15_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_chinese3\");\nextern const uint8_t u8g2_font_wqy15_t_gb2312[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_gb2312\");\nextern const uint8_t u8g2_font_wqy15_t_gb2312a[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_gb2312a\");\nextern const uint8_t u8g2_font_wqy15_t_gb2312b[] U8G2_FONT_SECTION(\"u8g2_font_wqy15_t_gb2312b\");\nextern const uint8_t u8g2_font_wqy16_t_chinese1[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_chinese1\");\nextern const uint8_t u8g2_font_wqy16_t_chinese2[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_chinese2\");\nextern const uint8_t u8g2_font_wqy16_t_chinese3[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_chinese3\");\nextern const uint8_t u8g2_font_wqy16_t_gb2312[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_gb2312\");\nextern const uint8_t u8g2_font_wqy16_t_gb2312a[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_gb2312a\");\nextern const uint8_t u8g2_font_wqy16_t_gb2312b[] U8G2_FONT_SECTION(\"u8g2_font_wqy16_t_gb2312b\");\nextern const uint8_t u8g2_font_b10_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b10_t_japanese1\");\nextern const uint8_t u8g2_font_b10_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b10_t_japanese2\");\nextern const uint8_t u8g2_font_b10_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b10_b_t_japanese1\");\nextern const uint8_t u8g2_font_b10_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b10_b_t_japanese2\");\nextern const uint8_t u8g2_font_f10_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f10_t_japanese1\");\nextern const uint8_t u8g2_font_f10_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f10_t_japanese2\");\nextern const uint8_t u8g2_font_f10_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f10_b_t_japanese1\");\nextern const uint8_t u8g2_font_f10_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f10_b_t_japanese2\");\nextern const uint8_t u8g2_font_b12_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b12_t_japanese1\");\nextern const uint8_t u8g2_font_b12_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b12_t_japanese2\");\nextern const uint8_t u8g2_font_b12_t_japanese3[] U8G2_FONT_SECTION(\"u8g2_font_b12_t_japanese3\");\nextern const uint8_t u8g2_font_b12_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b12_b_t_japanese1\");\nextern const uint8_t u8g2_font_b12_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b12_b_t_japanese2\");\nextern const uint8_t u8g2_font_b12_b_t_japanese3[] U8G2_FONT_SECTION(\"u8g2_font_b12_b_t_japanese3\");\nextern const uint8_t u8g2_font_f12_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f12_t_japanese1\");\nextern const uint8_t u8g2_font_f12_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f12_t_japanese2\");\nextern const uint8_t u8g2_font_f12_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f12_b_t_japanese1\");\nextern const uint8_t u8g2_font_f12_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f12_b_t_japanese2\");\nextern const uint8_t u8g2_font_b16_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b16_t_japanese1\");\nextern const uint8_t u8g2_font_b16_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b16_t_japanese2\");\nextern const uint8_t u8g2_font_b16_t_japanese3[] U8G2_FONT_SECTION(\"u8g2_font_b16_t_japanese3\");\nextern const uint8_t u8g2_font_b16_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_b16_b_t_japanese1\");\nextern const uint8_t u8g2_font_b16_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_b16_b_t_japanese2\");\nextern const uint8_t u8g2_font_b16_b_t_japanese3[] U8G2_FONT_SECTION(\"u8g2_font_b16_b_t_japanese3\");\nextern const uint8_t u8g2_font_f16_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f16_t_japanese1\");\nextern const uint8_t u8g2_font_f16_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f16_t_japanese2\");\nextern const uint8_t u8g2_font_f16_b_t_japanese1[] U8G2_FONT_SECTION(\"u8g2_font_f16_b_t_japanese1\");\nextern const uint8_t u8g2_font_f16_b_t_japanese2[] U8G2_FONT_SECTION(\"u8g2_font_f16_b_t_japanese2\");\nextern const uint8_t u8g2_font_artossans8_8r[] U8G2_FONT_SECTION(\"u8g2_font_artossans8_8r\");\nextern const uint8_t u8g2_font_artossans8_8n[] U8G2_FONT_SECTION(\"u8g2_font_artossans8_8n\");\nextern const uint8_t u8g2_font_artossans8_8u[] U8G2_FONT_SECTION(\"u8g2_font_artossans8_8u\");\nextern const uint8_t u8g2_font_artosserif8_8r[] U8G2_FONT_SECTION(\"u8g2_font_artosserif8_8r\");\nextern const uint8_t u8g2_font_artosserif8_8n[] U8G2_FONT_SECTION(\"u8g2_font_artosserif8_8n\");\nextern const uint8_t u8g2_font_artosserif8_8u[] U8G2_FONT_SECTION(\"u8g2_font_artosserif8_8u\");\nextern const uint8_t u8g2_font_chroma48medium8_8r[] U8G2_FONT_SECTION(\"u8g2_font_chroma48medium8_8r\");\nextern const uint8_t u8g2_font_chroma48medium8_8n[] U8G2_FONT_SECTION(\"u8g2_font_chroma48medium8_8n\");\nextern const uint8_t u8g2_font_chroma48medium8_8u[] U8G2_FONT_SECTION(\"u8g2_font_chroma48medium8_8u\");\nextern const uint8_t u8g2_font_saikyosansbold8_8n[] U8G2_FONT_SECTION(\"u8g2_font_saikyosansbold8_8n\");\nextern const uint8_t u8g2_font_saikyosansbold8_8u[] U8G2_FONT_SECTION(\"u8g2_font_saikyosansbold8_8u\");\nextern const uint8_t u8g2_font_torussansbold8_8r[] U8G2_FONT_SECTION(\"u8g2_font_torussansbold8_8r\");\nextern const uint8_t u8g2_font_torussansbold8_8n[] U8G2_FONT_SECTION(\"u8g2_font_torussansbold8_8n\");\nextern const uint8_t u8g2_font_torussansbold8_8u[] U8G2_FONT_SECTION(\"u8g2_font_torussansbold8_8u\");\nextern const uint8_t u8g2_font_victoriabold8_8r[] U8G2_FONT_SECTION(\"u8g2_font_victoriabold8_8r\");\nextern const uint8_t u8g2_font_victoriabold8_8n[] U8G2_FONT_SECTION(\"u8g2_font_victoriabold8_8n\");\nextern const uint8_t u8g2_font_victoriabold8_8u[] U8G2_FONT_SECTION(\"u8g2_font_victoriabold8_8u\");\nextern const uint8_t u8g2_font_victoriamedium8_8r[] U8G2_FONT_SECTION(\"u8g2_font_victoriamedium8_8r\");\nextern const uint8_t u8g2_font_victoriamedium8_8n[] U8G2_FONT_SECTION(\"u8g2_font_victoriamedium8_8n\");\nextern const uint8_t u8g2_font_victoriamedium8_8u[] U8G2_FONT_SECTION(\"u8g2_font_victoriamedium8_8u\");\nextern const uint8_t u8g2_font_courB08_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB08_tf\");\nextern const uint8_t u8g2_font_courB08_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB08_tr\");\nextern const uint8_t u8g2_font_courB08_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB08_tn\");\nextern const uint8_t u8g2_font_courB10_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB10_tf\");\nextern const uint8_t u8g2_font_courB10_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB10_tr\");\nextern const uint8_t u8g2_font_courB10_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB10_tn\");\nextern const uint8_t u8g2_font_courB12_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB12_tf\");\nextern const uint8_t u8g2_font_courB12_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB12_tr\");\nextern const uint8_t u8g2_font_courB12_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB12_tn\");\nextern const uint8_t u8g2_font_courB14_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB14_tf\");\nextern const uint8_t u8g2_font_courB14_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB14_tr\");\nextern const uint8_t u8g2_font_courB14_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB14_tn\");\nextern const uint8_t u8g2_font_courB18_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB18_tf\");\nextern const uint8_t u8g2_font_courB18_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB18_tr\");\nextern const uint8_t u8g2_font_courB18_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB18_tn\");\nextern const uint8_t u8g2_font_courB24_tf[] U8G2_FONT_SECTION(\"u8g2_font_courB24_tf\");\nextern const uint8_t u8g2_font_courB24_tr[] U8G2_FONT_SECTION(\"u8g2_font_courB24_tr\");\nextern const uint8_t u8g2_font_courB24_tn[] U8G2_FONT_SECTION(\"u8g2_font_courB24_tn\");\nextern const uint8_t u8g2_font_courR08_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR08_tf\");\nextern const uint8_t u8g2_font_courR08_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR08_tr\");\nextern const uint8_t u8g2_font_courR08_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR08_tn\");\nextern const uint8_t u8g2_font_courR10_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR10_tf\");\nextern const uint8_t u8g2_font_courR10_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR10_tr\");\nextern const uint8_t u8g2_font_courR10_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR10_tn\");\nextern const uint8_t u8g2_font_courR12_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR12_tf\");\nextern const uint8_t u8g2_font_courR12_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR12_tr\");\nextern const uint8_t u8g2_font_courR12_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR12_tn\");\nextern const uint8_t u8g2_font_courR14_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR14_tf\");\nextern const uint8_t u8g2_font_courR14_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR14_tr\");\nextern const uint8_t u8g2_font_courR14_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR14_tn\");\nextern const uint8_t u8g2_font_courR18_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR18_tf\");\nextern const uint8_t u8g2_font_courR18_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR18_tr\");\nextern const uint8_t u8g2_font_courR18_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR18_tn\");\nextern const uint8_t u8g2_font_courR24_tf[] U8G2_FONT_SECTION(\"u8g2_font_courR24_tf\");\nextern const uint8_t u8g2_font_courR24_tr[] U8G2_FONT_SECTION(\"u8g2_font_courR24_tr\");\nextern const uint8_t u8g2_font_courR24_tn[] U8G2_FONT_SECTION(\"u8g2_font_courR24_tn\");\nextern const uint8_t u8g2_font_helvB08_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB08_tf\");\nextern const uint8_t u8g2_font_helvB08_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB08_tr\");\nextern const uint8_t u8g2_font_helvB08_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB08_tn\");\nextern const uint8_t u8g2_font_helvB08_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB08_te\");\nextern const uint8_t u8g2_font_helvB10_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB10_tf\");\nextern const uint8_t u8g2_font_helvB10_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB10_tr\");\nextern const uint8_t u8g2_font_helvB10_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB10_tn\");\nextern const uint8_t u8g2_font_helvB10_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB10_te\");\nextern const uint8_t u8g2_font_helvB12_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB12_tf\");\nextern const uint8_t u8g2_font_helvB12_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB12_tr\");\nextern const uint8_t u8g2_font_helvB12_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB12_tn\");\nextern const uint8_t u8g2_font_helvB12_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB12_te\");\nextern const uint8_t u8g2_font_helvB14_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB14_tf\");\nextern const uint8_t u8g2_font_helvB14_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB14_tr\");\nextern const uint8_t u8g2_font_helvB14_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB14_tn\");\nextern const uint8_t u8g2_font_helvB14_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB14_te\");\nextern const uint8_t u8g2_font_helvB18_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB18_tf\");\nextern const uint8_t u8g2_font_helvB18_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB18_tr\");\nextern const uint8_t u8g2_font_helvB18_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB18_tn\");\nextern const uint8_t u8g2_font_helvB18_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB18_te\");\nextern const uint8_t u8g2_font_helvB24_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvB24_tf\");\nextern const uint8_t u8g2_font_helvB24_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvB24_tr\");\nextern const uint8_t u8g2_font_helvB24_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvB24_tn\");\nextern const uint8_t u8g2_font_helvB24_te[] U8G2_FONT_SECTION(\"u8g2_font_helvB24_te\");\nextern const uint8_t u8g2_font_helvR08_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR08_tf\");\nextern const uint8_t u8g2_font_helvR08_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR08_tr\");\nextern const uint8_t u8g2_font_helvR08_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR08_tn\");\nextern const uint8_t u8g2_font_helvR08_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR08_te\");\nextern const uint8_t u8g2_font_helvR10_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR10_tf\");\nextern const uint8_t u8g2_font_helvR10_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR10_tr\");\nextern const uint8_t u8g2_font_helvR10_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR10_tn\");\nextern const uint8_t u8g2_font_helvR10_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR10_te\");\nextern const uint8_t u8g2_font_helvR12_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR12_tf\");\nextern const uint8_t u8g2_font_helvR12_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR12_tr\");\nextern const uint8_t u8g2_font_helvR12_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR12_tn\");\nextern const uint8_t u8g2_font_helvR12_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR12_te\");\nextern const uint8_t u8g2_font_helvR14_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR14_tf\");\nextern const uint8_t u8g2_font_helvR14_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR14_tr\");\nextern const uint8_t u8g2_font_helvR14_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR14_tn\");\nextern const uint8_t u8g2_font_helvR14_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR14_te\");\nextern const uint8_t u8g2_font_helvR18_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR18_tf\");\nextern const uint8_t u8g2_font_helvR18_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR18_tr\");\nextern const uint8_t u8g2_font_helvR18_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR18_tn\");\nextern const uint8_t u8g2_font_helvR18_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR18_te\");\nextern const uint8_t u8g2_font_helvR24_tf[] U8G2_FONT_SECTION(\"u8g2_font_helvR24_tf\");\nextern const uint8_t u8g2_font_helvR24_tr[] U8G2_FONT_SECTION(\"u8g2_font_helvR24_tr\");\nextern const uint8_t u8g2_font_helvR24_tn[] U8G2_FONT_SECTION(\"u8g2_font_helvR24_tn\");\nextern const uint8_t u8g2_font_helvR24_te[] U8G2_FONT_SECTION(\"u8g2_font_helvR24_te\");\nextern const uint8_t u8g2_font_ncenB08_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB08_tf\");\nextern const uint8_t u8g2_font_ncenB08_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB08_tr\");\nextern const uint8_t u8g2_font_ncenB08_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB08_tn\");\nextern const uint8_t u8g2_font_ncenB08_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB08_te\");\nextern const uint8_t u8g2_font_ncenB10_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB10_tf\");\nextern const uint8_t u8g2_font_ncenB10_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB10_tr\");\nextern const uint8_t u8g2_font_ncenB10_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB10_tn\");\nextern const uint8_t u8g2_font_ncenB10_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB10_te\");\nextern const uint8_t u8g2_font_ncenB12_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB12_tf\");\nextern const uint8_t u8g2_font_ncenB12_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB12_tr\");\nextern const uint8_t u8g2_font_ncenB12_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB12_tn\");\nextern const uint8_t u8g2_font_ncenB12_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB12_te\");\nextern const uint8_t u8g2_font_ncenB14_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB14_tf\");\nextern const uint8_t u8g2_font_ncenB14_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB14_tr\");\nextern const uint8_t u8g2_font_ncenB14_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB14_tn\");\nextern const uint8_t u8g2_font_ncenB14_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB14_te\");\nextern const uint8_t u8g2_font_ncenB18_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB18_tf\");\nextern const uint8_t u8g2_font_ncenB18_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB18_tr\");\nextern const uint8_t u8g2_font_ncenB18_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB18_tn\");\nextern const uint8_t u8g2_font_ncenB18_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB18_te\");\nextern const uint8_t u8g2_font_ncenB24_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenB24_tf\");\nextern const uint8_t u8g2_font_ncenB24_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenB24_tr\");\nextern const uint8_t u8g2_font_ncenB24_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenB24_tn\");\nextern const uint8_t u8g2_font_ncenB24_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenB24_te\");\nextern const uint8_t u8g2_font_ncenR08_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR08_tf\");\nextern const uint8_t u8g2_font_ncenR08_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR08_tr\");\nextern const uint8_t u8g2_font_ncenR08_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR08_tn\");\nextern const uint8_t u8g2_font_ncenR08_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR08_te\");\nextern const uint8_t u8g2_font_ncenR10_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR10_tf\");\nextern const uint8_t u8g2_font_ncenR10_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR10_tr\");\nextern const uint8_t u8g2_font_ncenR10_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR10_tn\");\nextern const uint8_t u8g2_font_ncenR10_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR10_te\");\nextern const uint8_t u8g2_font_ncenR12_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR12_tf\");\nextern const uint8_t u8g2_font_ncenR12_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR12_tr\");\nextern const uint8_t u8g2_font_ncenR12_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR12_tn\");\nextern const uint8_t u8g2_font_ncenR12_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR12_te\");\nextern const uint8_t u8g2_font_ncenR14_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR14_tf\");\nextern const uint8_t u8g2_font_ncenR14_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR14_tr\");\nextern const uint8_t u8g2_font_ncenR14_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR14_tn\");\nextern const uint8_t u8g2_font_ncenR14_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR14_te\");\nextern const uint8_t u8g2_font_ncenR18_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR18_tf\");\nextern const uint8_t u8g2_font_ncenR18_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR18_tr\");\nextern const uint8_t u8g2_font_ncenR18_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR18_tn\");\nextern const uint8_t u8g2_font_ncenR18_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR18_te\");\nextern const uint8_t u8g2_font_ncenR24_tf[] U8G2_FONT_SECTION(\"u8g2_font_ncenR24_tf\");\nextern const uint8_t u8g2_font_ncenR24_tr[] U8G2_FONT_SECTION(\"u8g2_font_ncenR24_tr\");\nextern const uint8_t u8g2_font_ncenR24_tn[] U8G2_FONT_SECTION(\"u8g2_font_ncenR24_tn\");\nextern const uint8_t u8g2_font_ncenR24_te[] U8G2_FONT_SECTION(\"u8g2_font_ncenR24_te\");\nextern const uint8_t u8g2_font_timB08_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB08_tf\");\nextern const uint8_t u8g2_font_timB08_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB08_tr\");\nextern const uint8_t u8g2_font_timB08_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB08_tn\");\nextern const uint8_t u8g2_font_timB10_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB10_tf\");\nextern const uint8_t u8g2_font_timB10_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB10_tr\");\nextern const uint8_t u8g2_font_timB10_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB10_tn\");\nextern const uint8_t u8g2_font_timB12_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB12_tf\");\nextern const uint8_t u8g2_font_timB12_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB12_tr\");\nextern const uint8_t u8g2_font_timB12_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB12_tn\");\nextern const uint8_t u8g2_font_timB14_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB14_tf\");\nextern const uint8_t u8g2_font_timB14_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB14_tr\");\nextern const uint8_t u8g2_font_timB14_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB14_tn\");\nextern const uint8_t u8g2_font_timB18_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB18_tf\");\nextern const uint8_t u8g2_font_timB18_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB18_tr\");\nextern const uint8_t u8g2_font_timB18_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB18_tn\");\nextern const uint8_t u8g2_font_timB24_tf[] U8G2_FONT_SECTION(\"u8g2_font_timB24_tf\");\nextern const uint8_t u8g2_font_timB24_tr[] U8G2_FONT_SECTION(\"u8g2_font_timB24_tr\");\nextern const uint8_t u8g2_font_timB24_tn[] U8G2_FONT_SECTION(\"u8g2_font_timB24_tn\");\nextern const uint8_t u8g2_font_timR08_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR08_tf\");\nextern const uint8_t u8g2_font_timR08_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR08_tr\");\nextern const uint8_t u8g2_font_timR08_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR08_tn\");\nextern const uint8_t u8g2_font_timR10_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR10_tf\");\nextern const uint8_t u8g2_font_timR10_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR10_tr\");\nextern const uint8_t u8g2_font_timR10_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR10_tn\");\nextern const uint8_t u8g2_font_timR12_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR12_tf\");\nextern const uint8_t u8g2_font_timR12_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR12_tr\");\nextern const uint8_t u8g2_font_timR12_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR12_tn\");\nextern const uint8_t u8g2_font_timR14_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR14_tf\");\nextern const uint8_t u8g2_font_timR14_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR14_tr\");\nextern const uint8_t u8g2_font_timR14_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR14_tn\");\nextern const uint8_t u8g2_font_timR18_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR18_tf\");\nextern const uint8_t u8g2_font_timR18_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR18_tr\");\nextern const uint8_t u8g2_font_timR18_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR18_tn\");\nextern const uint8_t u8g2_font_timR24_tf[] U8G2_FONT_SECTION(\"u8g2_font_timR24_tf\");\nextern const uint8_t u8g2_font_timR24_tr[] U8G2_FONT_SECTION(\"u8g2_font_timR24_tr\");\nextern const uint8_t u8g2_font_timR24_tn[] U8G2_FONT_SECTION(\"u8g2_font_timR24_tn\");\nextern const uint8_t u8g2_font_lubB08_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB08_tf\");\nextern const uint8_t u8g2_font_lubB08_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB08_tr\");\nextern const uint8_t u8g2_font_lubB08_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB08_tn\");\nextern const uint8_t u8g2_font_lubB08_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB08_te\");\nextern const uint8_t u8g2_font_lubB10_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB10_tf\");\nextern const uint8_t u8g2_font_lubB10_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB10_tr\");\nextern const uint8_t u8g2_font_lubB10_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB10_tn\");\nextern const uint8_t u8g2_font_lubB10_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB10_te\");\nextern const uint8_t u8g2_font_lubB12_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB12_tf\");\nextern const uint8_t u8g2_font_lubB12_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB12_tr\");\nextern const uint8_t u8g2_font_lubB12_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB12_tn\");\nextern const uint8_t u8g2_font_lubB12_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB12_te\");\nextern const uint8_t u8g2_font_lubB14_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB14_tf\");\nextern const uint8_t u8g2_font_lubB14_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB14_tr\");\nextern const uint8_t u8g2_font_lubB14_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB14_tn\");\nextern const uint8_t u8g2_font_lubB14_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB14_te\");\nextern const uint8_t u8g2_font_lubB18_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB18_tf\");\nextern const uint8_t u8g2_font_lubB18_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB18_tr\");\nextern const uint8_t u8g2_font_lubB18_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB18_tn\");\nextern const uint8_t u8g2_font_lubB18_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB18_te\");\nextern const uint8_t u8g2_font_lubB19_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB19_tf\");\nextern const uint8_t u8g2_font_lubB19_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB19_tr\");\nextern const uint8_t u8g2_font_lubB19_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB19_tn\");\nextern const uint8_t u8g2_font_lubB19_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB19_te\");\nextern const uint8_t u8g2_font_lubB24_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubB24_tf\");\nextern const uint8_t u8g2_font_lubB24_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubB24_tr\");\nextern const uint8_t u8g2_font_lubB24_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubB24_tn\");\nextern const uint8_t u8g2_font_lubB24_te[] U8G2_FONT_SECTION(\"u8g2_font_lubB24_te\");\nextern const uint8_t u8g2_font_lubBI08_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI08_tf\");\nextern const uint8_t u8g2_font_lubBI08_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI08_tr\");\nextern const uint8_t u8g2_font_lubBI08_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI08_tn\");\nextern const uint8_t u8g2_font_lubBI08_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI08_te\");\nextern const uint8_t u8g2_font_lubBI10_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI10_tf\");\nextern const uint8_t u8g2_font_lubBI10_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI10_tr\");\nextern const uint8_t u8g2_font_lubBI10_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI10_tn\");\nextern const uint8_t u8g2_font_lubBI10_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI10_te\");\nextern const uint8_t u8g2_font_lubBI12_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI12_tf\");\nextern const uint8_t u8g2_font_lubBI12_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI12_tr\");\nextern const uint8_t u8g2_font_lubBI12_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI12_tn\");\nextern const uint8_t u8g2_font_lubBI12_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI12_te\");\nextern const uint8_t u8g2_font_lubBI14_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI14_tf\");\nextern const uint8_t u8g2_font_lubBI14_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI14_tr\");\nextern const uint8_t u8g2_font_lubBI14_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI14_tn\");\nextern const uint8_t u8g2_font_lubBI14_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI14_te\");\nextern const uint8_t u8g2_font_lubBI18_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI18_tf\");\nextern const uint8_t u8g2_font_lubBI18_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI18_tr\");\nextern const uint8_t u8g2_font_lubBI18_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI18_tn\");\nextern const uint8_t u8g2_font_lubBI18_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI18_te\");\nextern const uint8_t u8g2_font_lubBI19_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI19_tf\");\nextern const uint8_t u8g2_font_lubBI19_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI19_tr\");\nextern const uint8_t u8g2_font_lubBI19_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI19_tn\");\nextern const uint8_t u8g2_font_lubBI19_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI19_te\");\nextern const uint8_t u8g2_font_lubBI24_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubBI24_tf\");\nextern const uint8_t u8g2_font_lubBI24_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubBI24_tr\");\nextern const uint8_t u8g2_font_lubBI24_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubBI24_tn\");\nextern const uint8_t u8g2_font_lubBI24_te[] U8G2_FONT_SECTION(\"u8g2_font_lubBI24_te\");\nextern const uint8_t u8g2_font_lubI08_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI08_tf\");\nextern const uint8_t u8g2_font_lubI08_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI08_tr\");\nextern const uint8_t u8g2_font_lubI08_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI08_tn\");\nextern const uint8_t u8g2_font_lubI08_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI08_te\");\nextern const uint8_t u8g2_font_lubI10_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI10_tf\");\nextern const uint8_t u8g2_font_lubI10_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI10_tr\");\nextern const uint8_t u8g2_font_lubI10_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI10_tn\");\nextern const uint8_t u8g2_font_lubI10_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI10_te\");\nextern const uint8_t u8g2_font_lubI12_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI12_tf\");\nextern const uint8_t u8g2_font_lubI12_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI12_tr\");\nextern const uint8_t u8g2_font_lubI12_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI12_tn\");\nextern const uint8_t u8g2_font_lubI12_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI12_te\");\nextern const uint8_t u8g2_font_lubI14_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI14_tf\");\nextern const uint8_t u8g2_font_lubI14_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI14_tr\");\nextern const uint8_t u8g2_font_lubI14_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI14_tn\");\nextern const uint8_t u8g2_font_lubI14_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI14_te\");\nextern const uint8_t u8g2_font_lubI18_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI18_tf\");\nextern const uint8_t u8g2_font_lubI18_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI18_tr\");\nextern const uint8_t u8g2_font_lubI18_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI18_tn\");\nextern const uint8_t u8g2_font_lubI18_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI18_te\");\nextern const uint8_t u8g2_font_lubI19_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI19_tf\");\nextern const uint8_t u8g2_font_lubI19_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI19_tr\");\nextern const uint8_t u8g2_font_lubI19_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI19_tn\");\nextern const uint8_t u8g2_font_lubI19_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI19_te\");\nextern const uint8_t u8g2_font_lubI24_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubI24_tf\");\nextern const uint8_t u8g2_font_lubI24_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubI24_tr\");\nextern const uint8_t u8g2_font_lubI24_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubI24_tn\");\nextern const uint8_t u8g2_font_lubI24_te[] U8G2_FONT_SECTION(\"u8g2_font_lubI24_te\");\nextern const uint8_t u8g2_font_luBIS08_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS08_tf\");\nextern const uint8_t u8g2_font_luBIS08_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS08_tr\");\nextern const uint8_t u8g2_font_luBIS08_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS08_tn\");\nextern const uint8_t u8g2_font_luBIS08_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS08_te\");\nextern const uint8_t u8g2_font_luBIS10_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS10_tf\");\nextern const uint8_t u8g2_font_luBIS10_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS10_tr\");\nextern const uint8_t u8g2_font_luBIS10_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS10_tn\");\nextern const uint8_t u8g2_font_luBIS10_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS10_te\");\nextern const uint8_t u8g2_font_luBIS12_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS12_tf\");\nextern const uint8_t u8g2_font_luBIS12_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS12_tr\");\nextern const uint8_t u8g2_font_luBIS12_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS12_tn\");\nextern const uint8_t u8g2_font_luBIS12_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS12_te\");\nextern const uint8_t u8g2_font_luBIS14_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS14_tf\");\nextern const uint8_t u8g2_font_luBIS14_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS14_tr\");\nextern const uint8_t u8g2_font_luBIS14_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS14_tn\");\nextern const uint8_t u8g2_font_luBIS14_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS14_te\");\nextern const uint8_t u8g2_font_luBIS18_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS18_tf\");\nextern const uint8_t u8g2_font_luBIS18_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS18_tr\");\nextern const uint8_t u8g2_font_luBIS18_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS18_tn\");\nextern const uint8_t u8g2_font_luBIS18_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS18_te\");\nextern const uint8_t u8g2_font_luBIS19_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS19_tf\");\nextern const uint8_t u8g2_font_luBIS19_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS19_tr\");\nextern const uint8_t u8g2_font_luBIS19_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS19_tn\");\nextern const uint8_t u8g2_font_luBIS19_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS19_te\");\nextern const uint8_t u8g2_font_luBIS24_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBIS24_tf\");\nextern const uint8_t u8g2_font_luBIS24_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBIS24_tr\");\nextern const uint8_t u8g2_font_luBIS24_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBIS24_tn\");\nextern const uint8_t u8g2_font_luBIS24_te[] U8G2_FONT_SECTION(\"u8g2_font_luBIS24_te\");\nextern const uint8_t u8g2_font_lubR08_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR08_tf\");\nextern const uint8_t u8g2_font_lubR08_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR08_tr\");\nextern const uint8_t u8g2_font_lubR08_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR08_tn\");\nextern const uint8_t u8g2_font_lubR08_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR08_te\");\nextern const uint8_t u8g2_font_lubR10_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR10_tf\");\nextern const uint8_t u8g2_font_lubR10_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR10_tr\");\nextern const uint8_t u8g2_font_lubR10_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR10_tn\");\nextern const uint8_t u8g2_font_lubR10_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR10_te\");\nextern const uint8_t u8g2_font_lubR12_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR12_tf\");\nextern const uint8_t u8g2_font_lubR12_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR12_tr\");\nextern const uint8_t u8g2_font_lubR12_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR12_tn\");\nextern const uint8_t u8g2_font_lubR12_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR12_te\");\nextern const uint8_t u8g2_font_lubR14_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR14_tf\");\nextern const uint8_t u8g2_font_lubR14_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR14_tr\");\nextern const uint8_t u8g2_font_lubR14_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR14_tn\");\nextern const uint8_t u8g2_font_lubR14_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR14_te\");\nextern const uint8_t u8g2_font_lubR18_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR18_tf\");\nextern const uint8_t u8g2_font_lubR18_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR18_tr\");\nextern const uint8_t u8g2_font_lubR18_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR18_tn\");\nextern const uint8_t u8g2_font_lubR18_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR18_te\");\nextern const uint8_t u8g2_font_lubR19_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR19_tf\");\nextern const uint8_t u8g2_font_lubR19_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR19_tr\");\nextern const uint8_t u8g2_font_lubR19_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR19_tn\");\nextern const uint8_t u8g2_font_lubR19_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR19_te\");\nextern const uint8_t u8g2_font_lubR24_tf[] U8G2_FONT_SECTION(\"u8g2_font_lubR24_tf\");\nextern const uint8_t u8g2_font_lubR24_tr[] U8G2_FONT_SECTION(\"u8g2_font_lubR24_tr\");\nextern const uint8_t u8g2_font_lubR24_tn[] U8G2_FONT_SECTION(\"u8g2_font_lubR24_tn\");\nextern const uint8_t u8g2_font_lubR24_te[] U8G2_FONT_SECTION(\"u8g2_font_lubR24_te\");\nextern const uint8_t u8g2_font_luBS08_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS08_tf\");\nextern const uint8_t u8g2_font_luBS08_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS08_tr\");\nextern const uint8_t u8g2_font_luBS08_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS08_tn\");\nextern const uint8_t u8g2_font_luBS08_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS08_te\");\nextern const uint8_t u8g2_font_luBS10_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS10_tf\");\nextern const uint8_t u8g2_font_luBS10_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS10_tr\");\nextern const uint8_t u8g2_font_luBS10_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS10_tn\");\nextern const uint8_t u8g2_font_luBS10_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS10_te\");\nextern const uint8_t u8g2_font_luBS12_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS12_tf\");\nextern const uint8_t u8g2_font_luBS12_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS12_tr\");\nextern const uint8_t u8g2_font_luBS12_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS12_tn\");\nextern const uint8_t u8g2_font_luBS12_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS12_te\");\nextern const uint8_t u8g2_font_luBS14_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS14_tf\");\nextern const uint8_t u8g2_font_luBS14_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS14_tr\");\nextern const uint8_t u8g2_font_luBS14_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS14_tn\");\nextern const uint8_t u8g2_font_luBS14_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS14_te\");\nextern const uint8_t u8g2_font_luBS18_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS18_tf\");\nextern const uint8_t u8g2_font_luBS18_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS18_tr\");\nextern const uint8_t u8g2_font_luBS18_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS18_tn\");\nextern const uint8_t u8g2_font_luBS18_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS18_te\");\nextern const uint8_t u8g2_font_luBS19_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS19_tf\");\nextern const uint8_t u8g2_font_luBS19_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS19_tr\");\nextern const uint8_t u8g2_font_luBS19_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS19_tn\");\nextern const uint8_t u8g2_font_luBS19_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS19_te\");\nextern const uint8_t u8g2_font_luBS24_tf[] U8G2_FONT_SECTION(\"u8g2_font_luBS24_tf\");\nextern const uint8_t u8g2_font_luBS24_tr[] U8G2_FONT_SECTION(\"u8g2_font_luBS24_tr\");\nextern const uint8_t u8g2_font_luBS24_tn[] U8G2_FONT_SECTION(\"u8g2_font_luBS24_tn\");\nextern const uint8_t u8g2_font_luBS24_te[] U8G2_FONT_SECTION(\"u8g2_font_luBS24_te\");\nextern const uint8_t u8g2_font_luIS08_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS08_tf\");\nextern const uint8_t u8g2_font_luIS08_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS08_tr\");\nextern const uint8_t u8g2_font_luIS08_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS08_tn\");\nextern const uint8_t u8g2_font_luIS08_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS08_te\");\nextern const uint8_t u8g2_font_luIS10_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS10_tf\");\nextern const uint8_t u8g2_font_luIS10_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS10_tr\");\nextern const uint8_t u8g2_font_luIS10_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS10_tn\");\nextern const uint8_t u8g2_font_luIS10_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS10_te\");\nextern const uint8_t u8g2_font_luIS12_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS12_tf\");\nextern const uint8_t u8g2_font_luIS12_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS12_tr\");\nextern const uint8_t u8g2_font_luIS12_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS12_tn\");\nextern const uint8_t u8g2_font_luIS12_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS12_te\");\nextern const uint8_t u8g2_font_luIS14_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS14_tf\");\nextern const uint8_t u8g2_font_luIS14_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS14_tr\");\nextern const uint8_t u8g2_font_luIS14_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS14_tn\");\nextern const uint8_t u8g2_font_luIS14_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS14_te\");\nextern const uint8_t u8g2_font_luIS18_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS18_tf\");\nextern const uint8_t u8g2_font_luIS18_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS18_tr\");\nextern const uint8_t u8g2_font_luIS18_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS18_tn\");\nextern const uint8_t u8g2_font_luIS18_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS18_te\");\nextern const uint8_t u8g2_font_luIS19_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS19_tf\");\nextern const uint8_t u8g2_font_luIS19_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS19_tr\");\nextern const uint8_t u8g2_font_luIS19_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS19_tn\");\nextern const uint8_t u8g2_font_luIS19_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS19_te\");\nextern const uint8_t u8g2_font_luIS24_tf[] U8G2_FONT_SECTION(\"u8g2_font_luIS24_tf\");\nextern const uint8_t u8g2_font_luIS24_tr[] U8G2_FONT_SECTION(\"u8g2_font_luIS24_tr\");\nextern const uint8_t u8g2_font_luIS24_tn[] U8G2_FONT_SECTION(\"u8g2_font_luIS24_tn\");\nextern const uint8_t u8g2_font_luIS24_te[] U8G2_FONT_SECTION(\"u8g2_font_luIS24_te\");\nextern const uint8_t u8g2_font_luRS08_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS08_tf\");\nextern const uint8_t u8g2_font_luRS08_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS08_tr\");\nextern const uint8_t u8g2_font_luRS08_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS08_tn\");\nextern const uint8_t u8g2_font_luRS08_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS08_te\");\nextern const uint8_t u8g2_font_luRS10_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS10_tf\");\nextern const uint8_t u8g2_font_luRS10_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS10_tr\");\nextern const uint8_t u8g2_font_luRS10_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS10_tn\");\nextern const uint8_t u8g2_font_luRS10_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS10_te\");\nextern const uint8_t u8g2_font_luRS12_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS12_tf\");\nextern const uint8_t u8g2_font_luRS12_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS12_tr\");\nextern const uint8_t u8g2_font_luRS12_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS12_tn\");\nextern const uint8_t u8g2_font_luRS12_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS12_te\");\nextern const uint8_t u8g2_font_luRS14_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS14_tf\");\nextern const uint8_t u8g2_font_luRS14_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS14_tr\");\nextern const uint8_t u8g2_font_luRS14_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS14_tn\");\nextern const uint8_t u8g2_font_luRS14_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS14_te\");\nextern const uint8_t u8g2_font_luRS18_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS18_tf\");\nextern const uint8_t u8g2_font_luRS18_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS18_tr\");\nextern const uint8_t u8g2_font_luRS18_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS18_tn\");\nextern const uint8_t u8g2_font_luRS18_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS18_te\");\nextern const uint8_t u8g2_font_luRS19_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS19_tf\");\nextern const uint8_t u8g2_font_luRS19_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS19_tr\");\nextern const uint8_t u8g2_font_luRS19_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS19_tn\");\nextern const uint8_t u8g2_font_luRS19_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS19_te\");\nextern const uint8_t u8g2_font_luRS24_tf[] U8G2_FONT_SECTION(\"u8g2_font_luRS24_tf\");\nextern const uint8_t u8g2_font_luRS24_tr[] U8G2_FONT_SECTION(\"u8g2_font_luRS24_tr\");\nextern const uint8_t u8g2_font_luRS24_tn[] U8G2_FONT_SECTION(\"u8g2_font_luRS24_tn\");\nextern const uint8_t u8g2_font_luRS24_te[] U8G2_FONT_SECTION(\"u8g2_font_luRS24_te\");\nextern const uint8_t u8g2_font_baby_tf[] U8G2_FONT_SECTION(\"u8g2_font_baby_tf\");\nextern const uint8_t u8g2_font_baby_tr[] U8G2_FONT_SECTION(\"u8g2_font_baby_tr\");\nextern const uint8_t u8g2_font_baby_tn[] U8G2_FONT_SECTION(\"u8g2_font_baby_tn\");\nextern const uint8_t u8g2_font_blipfest_07_tr[] U8G2_FONT_SECTION(\"u8g2_font_blipfest_07_tr\");\nextern const uint8_t u8g2_font_blipfest_07_tn[] U8G2_FONT_SECTION(\"u8g2_font_blipfest_07_tn\");\nextern const uint8_t u8g2_font_chikita_tf[] U8G2_FONT_SECTION(\"u8g2_font_chikita_tf\");\nextern const uint8_t u8g2_font_chikita_tr[] U8G2_FONT_SECTION(\"u8g2_font_chikita_tr\");\nextern const uint8_t u8g2_font_chikita_tn[] U8G2_FONT_SECTION(\"u8g2_font_chikita_tn\");\nextern const uint8_t u8g2_font_lucasfont_alternate_tf[] U8G2_FONT_SECTION(\"u8g2_font_lucasfont_alternate_tf\");\nextern const uint8_t u8g2_font_lucasfont_alternate_tr[] U8G2_FONT_SECTION(\"u8g2_font_lucasfont_alternate_tr\");\nextern const uint8_t u8g2_font_lucasfont_alternate_tn[] U8G2_FONT_SECTION(\"u8g2_font_lucasfont_alternate_tn\");\nextern const uint8_t u8g2_font_p01type_tf[] U8G2_FONT_SECTION(\"u8g2_font_p01type_tf\");\nextern const uint8_t u8g2_font_p01type_tr[] U8G2_FONT_SECTION(\"u8g2_font_p01type_tr\");\nextern const uint8_t u8g2_font_p01type_tn[] U8G2_FONT_SECTION(\"u8g2_font_p01type_tn\");\nextern const uint8_t u8g2_font_pixelle_micro_tr[] U8G2_FONT_SECTION(\"u8g2_font_pixelle_micro_tr\");\nextern const uint8_t u8g2_font_pixelle_micro_tn[] U8G2_FONT_SECTION(\"u8g2_font_pixelle_micro_tn\");\nextern const uint8_t u8g2_font_robot_de_niro_tf[] U8G2_FONT_SECTION(\"u8g2_font_robot_de_niro_tf\");\nextern const uint8_t u8g2_font_robot_de_niro_tr[] U8G2_FONT_SECTION(\"u8g2_font_robot_de_niro_tr\");\nextern const uint8_t u8g2_font_robot_de_niro_tn[] U8G2_FONT_SECTION(\"u8g2_font_robot_de_niro_tn\");\nextern const uint8_t u8g2_font_trixel_square_tf[] U8G2_FONT_SECTION(\"u8g2_font_trixel_square_tf\");\nextern const uint8_t u8g2_font_trixel_square_tr[] U8G2_FONT_SECTION(\"u8g2_font_trixel_square_tr\");\nextern const uint8_t u8g2_font_trixel_square_tn[] U8G2_FONT_SECTION(\"u8g2_font_trixel_square_tn\");\nextern const uint8_t u8g2_font_haxrcorp4089_tr[] U8G2_FONT_SECTION(\"u8g2_font_haxrcorp4089_tr\");\nextern const uint8_t u8g2_font_haxrcorp4089_tn[] U8G2_FONT_SECTION(\"u8g2_font_haxrcorp4089_tn\");\nextern const uint8_t u8g2_font_haxrcorp4089_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_haxrcorp4089_t_cyrillic\");\nextern const uint8_t u8g2_font_bubble_tr[] U8G2_FONT_SECTION(\"u8g2_font_bubble_tr\");\nextern const uint8_t u8g2_font_bubble_tn[] U8G2_FONT_SECTION(\"u8g2_font_bubble_tn\");\nextern const uint8_t u8g2_font_cardimon_pixel_tf[] U8G2_FONT_SECTION(\"u8g2_font_cardimon_pixel_tf\");\nextern const uint8_t u8g2_font_cardimon_pixel_tr[] U8G2_FONT_SECTION(\"u8g2_font_cardimon_pixel_tr\");\nextern const uint8_t u8g2_font_cardimon_pixel_tn[] U8G2_FONT_SECTION(\"u8g2_font_cardimon_pixel_tn\");\nextern const uint8_t u8g2_font_maniac_tf[] U8G2_FONT_SECTION(\"u8g2_font_maniac_tf\");\nextern const uint8_t u8g2_font_maniac_tr[] U8G2_FONT_SECTION(\"u8g2_font_maniac_tr\");\nextern const uint8_t u8g2_font_maniac_tn[] U8G2_FONT_SECTION(\"u8g2_font_maniac_tn\");\nextern const uint8_t u8g2_font_maniac_te[] U8G2_FONT_SECTION(\"u8g2_font_maniac_te\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_o_tf[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_o_tf\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_o_tr[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_o_tr\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_o_tn[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_o_tn\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_r_tf[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_r_tf\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_r_tr[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_r_tr\");\nextern const uint8_t u8g2_font_lucasarts_scumm_subtitle_r_tn[] U8G2_FONT_SECTION(\"u8g2_font_lucasarts_scumm_subtitle_r_tn\");\nextern const uint8_t u8g2_font_fub11_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub11_tf\");\nextern const uint8_t u8g2_font_fub11_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub11_tr\");\nextern const uint8_t u8g2_font_fub11_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub11_tn\");\nextern const uint8_t u8g2_font_fub14_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub14_tf\");\nextern const uint8_t u8g2_font_fub14_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub14_tr\");\nextern const uint8_t u8g2_font_fub14_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub14_tn\");\nextern const uint8_t u8g2_font_fub17_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub17_tf\");\nextern const uint8_t u8g2_font_fub17_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub17_tr\");\nextern const uint8_t u8g2_font_fub17_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub17_tn\");\nextern const uint8_t u8g2_font_fub20_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub20_tf\");\nextern const uint8_t u8g2_font_fub20_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub20_tr\");\nextern const uint8_t u8g2_font_fub20_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub20_tn\");\nextern const uint8_t u8g2_font_fub25_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub25_tf\");\nextern const uint8_t u8g2_font_fub25_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub25_tr\");\nextern const uint8_t u8g2_font_fub25_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub25_tn\");\nextern const uint8_t u8g2_font_fub30_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub30_tf\");\nextern const uint8_t u8g2_font_fub30_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub30_tr\");\nextern const uint8_t u8g2_font_fub30_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub30_tn\");\nextern const uint8_t u8g2_font_fub35_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub35_tf\");\nextern const uint8_t u8g2_font_fub35_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub35_tr\");\nextern const uint8_t u8g2_font_fub35_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub35_tn\");\nextern const uint8_t u8g2_font_fub42_tf[] U8G2_FONT_SECTION(\"u8g2_font_fub42_tf\");\nextern const uint8_t u8g2_font_fub42_tr[] U8G2_FONT_SECTION(\"u8g2_font_fub42_tr\");\nextern const uint8_t u8g2_font_fub42_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub42_tn\");\nextern const uint8_t u8g2_font_fub49_tn[] U8G2_FONT_SECTION(\"u8g2_font_fub49_tn\");\nextern const uint8_t u8g2_font_fub11_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub11_t_symbol\");\nextern const uint8_t u8g2_font_fub14_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub14_t_symbol\");\nextern const uint8_t u8g2_font_fub17_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub17_t_symbol\");\nextern const uint8_t u8g2_font_fub20_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub20_t_symbol\");\nextern const uint8_t u8g2_font_fub25_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub25_t_symbol\");\nextern const uint8_t u8g2_font_fub30_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub30_t_symbol\");\nextern const uint8_t u8g2_font_fub35_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub35_t_symbol\");\nextern const uint8_t u8g2_font_fub42_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub42_t_symbol\");\nextern const uint8_t u8g2_font_fub49_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fub49_t_symbol\");\nextern const uint8_t u8g2_font_fur11_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur11_tf\");\nextern const uint8_t u8g2_font_fur11_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur11_tr\");\nextern const uint8_t u8g2_font_fur11_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur11_tn\");\nextern const uint8_t u8g2_font_fur14_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur14_tf\");\nextern const uint8_t u8g2_font_fur14_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur14_tr\");\nextern const uint8_t u8g2_font_fur14_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur14_tn\");\nextern const uint8_t u8g2_font_fur17_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur17_tf\");\nextern const uint8_t u8g2_font_fur17_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur17_tr\");\nextern const uint8_t u8g2_font_fur17_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur17_tn\");\nextern const uint8_t u8g2_font_fur20_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur20_tf\");\nextern const uint8_t u8g2_font_fur20_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur20_tr\");\nextern const uint8_t u8g2_font_fur20_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur20_tn\");\nextern const uint8_t u8g2_font_fur25_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur25_tf\");\nextern const uint8_t u8g2_font_fur25_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur25_tr\");\nextern const uint8_t u8g2_font_fur25_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur25_tn\");\nextern const uint8_t u8g2_font_fur30_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur30_tf\");\nextern const uint8_t u8g2_font_fur30_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur30_tr\");\nextern const uint8_t u8g2_font_fur30_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur30_tn\");\nextern const uint8_t u8g2_font_fur35_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur35_tf\");\nextern const uint8_t u8g2_font_fur35_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur35_tr\");\nextern const uint8_t u8g2_font_fur35_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur35_tn\");\nextern const uint8_t u8g2_font_fur42_tf[] U8G2_FONT_SECTION(\"u8g2_font_fur42_tf\");\nextern const uint8_t u8g2_font_fur42_tr[] U8G2_FONT_SECTION(\"u8g2_font_fur42_tr\");\nextern const uint8_t u8g2_font_fur42_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur42_tn\");\nextern const uint8_t u8g2_font_fur49_tn[] U8G2_FONT_SECTION(\"u8g2_font_fur49_tn\");\nextern const uint8_t u8g2_font_fur11_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur11_t_symbol\");\nextern const uint8_t u8g2_font_fur14_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur14_t_symbol\");\nextern const uint8_t u8g2_font_fur17_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur17_t_symbol\");\nextern const uint8_t u8g2_font_fur20_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur20_t_symbol\");\nextern const uint8_t u8g2_font_fur25_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur25_t_symbol\");\nextern const uint8_t u8g2_font_fur30_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur30_t_symbol\");\nextern const uint8_t u8g2_font_fur35_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur35_t_symbol\");\nextern const uint8_t u8g2_font_fur42_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur42_t_symbol\");\nextern const uint8_t u8g2_font_fur49_t_symbol[] U8G2_FONT_SECTION(\"u8g2_font_fur49_t_symbol\");\nextern const uint8_t u8g2_font_osb18_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb18_tf\");\nextern const uint8_t u8g2_font_osb18_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb18_tr\");\nextern const uint8_t u8g2_font_osb18_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb18_tn\");\nextern const uint8_t u8g2_font_osb21_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb21_tf\");\nextern const uint8_t u8g2_font_osb21_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb21_tr\");\nextern const uint8_t u8g2_font_osb21_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb21_tn\");\nextern const uint8_t u8g2_font_osb26_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb26_tf\");\nextern const uint8_t u8g2_font_osb26_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb26_tr\");\nextern const uint8_t u8g2_font_osb26_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb26_tn\");\nextern const uint8_t u8g2_font_osb29_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb29_tf\");\nextern const uint8_t u8g2_font_osb29_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb29_tr\");\nextern const uint8_t u8g2_font_osb29_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb29_tn\");\nextern const uint8_t u8g2_font_osb35_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb35_tf\");\nextern const uint8_t u8g2_font_osb35_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb35_tr\");\nextern const uint8_t u8g2_font_osb35_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb35_tn\");\nextern const uint8_t u8g2_font_osb41_tf[] U8G2_FONT_SECTION(\"u8g2_font_osb41_tf\");\nextern const uint8_t u8g2_font_osb41_tr[] U8G2_FONT_SECTION(\"u8g2_font_osb41_tr\");\nextern const uint8_t u8g2_font_osb41_tn[] U8G2_FONT_SECTION(\"u8g2_font_osb41_tn\");\nextern const uint8_t u8g2_font_osr18_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr18_tf\");\nextern const uint8_t u8g2_font_osr18_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr18_tr\");\nextern const uint8_t u8g2_font_osr18_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr18_tn\");\nextern const uint8_t u8g2_font_osr21_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr21_tf\");\nextern const uint8_t u8g2_font_osr21_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr21_tr\");\nextern const uint8_t u8g2_font_osr21_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr21_tn\");\nextern const uint8_t u8g2_font_osr26_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr26_tf\");\nextern const uint8_t u8g2_font_osr26_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr26_tr\");\nextern const uint8_t u8g2_font_osr26_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr26_tn\");\nextern const uint8_t u8g2_font_osr29_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr29_tf\");\nextern const uint8_t u8g2_font_osr29_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr29_tr\");\nextern const uint8_t u8g2_font_osr29_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr29_tn\");\nextern const uint8_t u8g2_font_osr35_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr35_tf\");\nextern const uint8_t u8g2_font_osr35_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr35_tr\");\nextern const uint8_t u8g2_font_osr35_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr35_tn\");\nextern const uint8_t u8g2_font_osr41_tf[] U8G2_FONT_SECTION(\"u8g2_font_osr41_tf\");\nextern const uint8_t u8g2_font_osr41_tr[] U8G2_FONT_SECTION(\"u8g2_font_osr41_tr\");\nextern const uint8_t u8g2_font_osr41_tn[] U8G2_FONT_SECTION(\"u8g2_font_osr41_tn\");\nextern const uint8_t u8g2_font_inr16_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr16_mf\");\nextern const uint8_t u8g2_font_inr16_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr16_mr\");\nextern const uint8_t u8g2_font_inr16_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr16_mn\");\nextern const uint8_t u8g2_font_inr19_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr19_mf\");\nextern const uint8_t u8g2_font_inr19_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr19_mr\");\nextern const uint8_t u8g2_font_inr19_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr19_mn\");\nextern const uint8_t u8g2_font_inr21_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr21_mf\");\nextern const uint8_t u8g2_font_inr21_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr21_mr\");\nextern const uint8_t u8g2_font_inr21_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr21_mn\");\nextern const uint8_t u8g2_font_inr24_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr24_mf\");\nextern const uint8_t u8g2_font_inr24_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr24_mr\");\nextern const uint8_t u8g2_font_inr24_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr24_mn\");\nextern const uint8_t u8g2_font_inr24_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr24_t_cyrillic\");\nextern const uint8_t u8g2_font_inr27_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr27_mf\");\nextern const uint8_t u8g2_font_inr27_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr27_mr\");\nextern const uint8_t u8g2_font_inr27_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr27_mn\");\nextern const uint8_t u8g2_font_inr27_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr27_t_cyrillic\");\nextern const uint8_t u8g2_font_inr30_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr30_mf\");\nextern const uint8_t u8g2_font_inr30_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr30_mr\");\nextern const uint8_t u8g2_font_inr30_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr30_mn\");\nextern const uint8_t u8g2_font_inr30_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr30_t_cyrillic\");\nextern const uint8_t u8g2_font_inr33_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr33_mf\");\nextern const uint8_t u8g2_font_inr33_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr33_mr\");\nextern const uint8_t u8g2_font_inr33_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr33_mn\");\nextern const uint8_t u8g2_font_inr33_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr33_t_cyrillic\");\nextern const uint8_t u8g2_font_inr38_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr38_mf\");\nextern const uint8_t u8g2_font_inr38_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr38_mr\");\nextern const uint8_t u8g2_font_inr38_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr38_mn\");\nextern const uint8_t u8g2_font_inr38_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr38_t_cyrillic\");\nextern const uint8_t u8g2_font_inr42_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr42_mf\");\nextern const uint8_t u8g2_font_inr42_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr42_mr\");\nextern const uint8_t u8g2_font_inr42_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr42_mn\");\nextern const uint8_t u8g2_font_inr42_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr42_t_cyrillic\");\nextern const uint8_t u8g2_font_inr46_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr46_mf\");\nextern const uint8_t u8g2_font_inr46_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr46_mr\");\nextern const uint8_t u8g2_font_inr46_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr46_mn\");\nextern const uint8_t u8g2_font_inr46_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr46_t_cyrillic\");\nextern const uint8_t u8g2_font_inr49_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr49_mf\");\nextern const uint8_t u8g2_font_inr49_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr49_mr\");\nextern const uint8_t u8g2_font_inr49_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr49_mn\");\nextern const uint8_t u8g2_font_inr49_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr49_t_cyrillic\");\nextern const uint8_t u8g2_font_inr53_mf[] U8G2_FONT_SECTION(\"u8g2_font_inr53_mf\");\nextern const uint8_t u8g2_font_inr53_mr[] U8G2_FONT_SECTION(\"u8g2_font_inr53_mr\");\nextern const uint8_t u8g2_font_inr53_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr53_mn\");\nextern const uint8_t u8g2_font_inr53_t_cyrillic[] U8G2_FONT_SECTION(\"u8g2_font_inr53_t_cyrillic\");\nextern const uint8_t u8g2_font_inr57_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr57_mn\");\nextern const uint8_t u8g2_font_inr62_mn[] U8G2_FONT_SECTION(\"u8g2_font_inr62_mn\");\nextern const uint8_t u8g2_font_inb16_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb16_mf\");\nextern const uint8_t u8g2_font_inb16_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb16_mr\");\nextern const uint8_t u8g2_font_inb16_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb16_mn\");\nextern const uint8_t u8g2_font_inb19_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb19_mf\");\nextern const uint8_t u8g2_font_inb19_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb19_mr\");\nextern const uint8_t u8g2_font_inb19_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb19_mn\");\nextern const uint8_t u8g2_font_inb21_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb21_mf\");\nextern const uint8_t u8g2_font_inb21_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb21_mr\");\nextern const uint8_t u8g2_font_inb21_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb21_mn\");\nextern const uint8_t u8g2_font_inb24_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb24_mf\");\nextern const uint8_t u8g2_font_inb24_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb24_mr\");\nextern const uint8_t u8g2_font_inb24_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb24_mn\");\nextern const uint8_t u8g2_font_inb27_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb27_mf\");\nextern const uint8_t u8g2_font_inb27_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb27_mr\");\nextern const uint8_t u8g2_font_inb27_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb27_mn\");\nextern const uint8_t u8g2_font_inb30_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb30_mf\");\nextern const uint8_t u8g2_font_inb30_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb30_mr\");\nextern const uint8_t u8g2_font_inb30_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb30_mn\");\nextern const uint8_t u8g2_font_inb33_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb33_mf\");\nextern const uint8_t u8g2_font_inb33_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb33_mr\");\nextern const uint8_t u8g2_font_inb33_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb33_mn\");\nextern const uint8_t u8g2_font_inb38_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb38_mf\");\nextern const uint8_t u8g2_font_inb38_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb38_mr\");\nextern const uint8_t u8g2_font_inb38_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb38_mn\");\nextern const uint8_t u8g2_font_inb42_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb42_mf\");\nextern const uint8_t u8g2_font_inb42_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb42_mr\");\nextern const uint8_t u8g2_font_inb42_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb42_mn\");\nextern const uint8_t u8g2_font_inb46_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb46_mf\");\nextern const uint8_t u8g2_font_inb46_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb46_mr\");\nextern const uint8_t u8g2_font_inb46_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb46_mn\");\nextern const uint8_t u8g2_font_inb49_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb49_mf\");\nextern const uint8_t u8g2_font_inb49_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb49_mr\");\nextern const uint8_t u8g2_font_inb49_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb49_mn\");\nextern const uint8_t u8g2_font_inb53_mf[] U8G2_FONT_SECTION(\"u8g2_font_inb53_mf\");\nextern const uint8_t u8g2_font_inb53_mr[] U8G2_FONT_SECTION(\"u8g2_font_inb53_mr\");\nextern const uint8_t u8g2_font_inb53_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb53_mn\");\nextern const uint8_t u8g2_font_inb57_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb57_mn\");\nextern const uint8_t u8g2_font_inb63_mn[] U8G2_FONT_SECTION(\"u8g2_font_inb63_mn\");\nextern const uint8_t u8g2_font_logisoso16_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso16_tf\");\nextern const uint8_t u8g2_font_logisoso16_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso16_tr\");\nextern const uint8_t u8g2_font_logisoso16_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso16_tn\");\nextern const uint8_t u8g2_font_logisoso18_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso18_tf\");\nextern const uint8_t u8g2_font_logisoso18_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso18_tr\");\nextern const uint8_t u8g2_font_logisoso18_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso18_tn\");\nextern const uint8_t u8g2_font_logisoso20_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso20_tf\");\nextern const uint8_t u8g2_font_logisoso20_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso20_tr\");\nextern const uint8_t u8g2_font_logisoso20_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso20_tn\");\nextern const uint8_t u8g2_font_logisoso22_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso22_tf\");\nextern const uint8_t u8g2_font_logisoso22_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso22_tr\");\nextern const uint8_t u8g2_font_logisoso22_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso22_tn\");\nextern const uint8_t u8g2_font_logisoso24_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso24_tf\");\nextern const uint8_t u8g2_font_logisoso24_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso24_tr\");\nextern const uint8_t u8g2_font_logisoso24_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso24_tn\");\nextern const uint8_t u8g2_font_logisoso26_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso26_tf\");\nextern const uint8_t u8g2_font_logisoso26_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso26_tr\");\nextern const uint8_t u8g2_font_logisoso26_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso26_tn\");\nextern const uint8_t u8g2_font_logisoso28_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso28_tf\");\nextern const uint8_t u8g2_font_logisoso28_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso28_tr\");\nextern const uint8_t u8g2_font_logisoso28_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso28_tn\");\nextern const uint8_t u8g2_font_logisoso30_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso30_tf\");\nextern const uint8_t u8g2_font_logisoso30_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso30_tr\");\nextern const uint8_t u8g2_font_logisoso30_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso30_tn\");\nextern const uint8_t u8g2_font_logisoso32_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso32_tf\");\nextern const uint8_t u8g2_font_logisoso32_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso32_tr\");\nextern const uint8_t u8g2_font_logisoso32_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso32_tn\");\nextern const uint8_t u8g2_font_logisoso34_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso34_tf\");\nextern const uint8_t u8g2_font_logisoso34_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso34_tr\");\nextern const uint8_t u8g2_font_logisoso34_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso34_tn\");\nextern const uint8_t u8g2_font_logisoso38_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso38_tf\");\nextern const uint8_t u8g2_font_logisoso38_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso38_tr\");\nextern const uint8_t u8g2_font_logisoso38_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso38_tn\");\nextern const uint8_t u8g2_font_logisoso42_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso42_tf\");\nextern const uint8_t u8g2_font_logisoso42_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso42_tr\");\nextern const uint8_t u8g2_font_logisoso42_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso42_tn\");\nextern const uint8_t u8g2_font_logisoso46_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso46_tf\");\nextern const uint8_t u8g2_font_logisoso46_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso46_tr\");\nextern const uint8_t u8g2_font_logisoso46_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso46_tn\");\nextern const uint8_t u8g2_font_logisoso50_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso50_tf\");\nextern const uint8_t u8g2_font_logisoso50_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso50_tr\");\nextern const uint8_t u8g2_font_logisoso50_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso50_tn\");\nextern const uint8_t u8g2_font_logisoso54_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso54_tf\");\nextern const uint8_t u8g2_font_logisoso54_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso54_tr\");\nextern const uint8_t u8g2_font_logisoso54_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso54_tn\");\nextern const uint8_t u8g2_font_logisoso58_tf[] U8G2_FONT_SECTION(\"u8g2_font_logisoso58_tf\");\nextern const uint8_t u8g2_font_logisoso58_tr[] U8G2_FONT_SECTION(\"u8g2_font_logisoso58_tr\");\nextern const uint8_t u8g2_font_logisoso58_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso58_tn\");\nextern const uint8_t u8g2_font_logisoso62_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso62_tn\");\nextern const uint8_t u8g2_font_logisoso78_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso78_tn\");\nextern const uint8_t u8g2_font_logisoso92_tn[] U8G2_FONT_SECTION(\"u8g2_font_logisoso92_tn\");\nextern const uint8_t u8g2_font_pressstart2p_8f[] U8G2_FONT_SECTION(\"u8g2_font_pressstart2p_8f\");\nextern const uint8_t u8g2_font_pressstart2p_8r[] U8G2_FONT_SECTION(\"u8g2_font_pressstart2p_8r\");\nextern const uint8_t u8g2_font_pressstart2p_8n[] U8G2_FONT_SECTION(\"u8g2_font_pressstart2p_8n\");\nextern const uint8_t u8g2_font_pressstart2p_8u[] U8G2_FONT_SECTION(\"u8g2_font_pressstart2p_8u\");\nextern const uint8_t u8g2_font_pcsenior_8f[] U8G2_FONT_SECTION(\"u8g2_font_pcsenior_8f\");\nextern const uint8_t u8g2_font_pcsenior_8r[] U8G2_FONT_SECTION(\"u8g2_font_pcsenior_8r\");\nextern const uint8_t u8g2_font_pcsenior_8n[] U8G2_FONT_SECTION(\"u8g2_font_pcsenior_8n\");\nextern const uint8_t u8g2_font_pcsenior_8u[] U8G2_FONT_SECTION(\"u8g2_font_pcsenior_8u\");\nextern const uint8_t u8g2_font_pxplusibmcgathin_8f[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcgathin_8f\");\nextern const uint8_t u8g2_font_pxplusibmcgathin_8r[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcgathin_8r\");\nextern const uint8_t u8g2_font_pxplusibmcgathin_8n[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcgathin_8n\");\nextern const uint8_t u8g2_font_pxplusibmcgathin_8u[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcgathin_8u\");\nextern const uint8_t u8g2_font_pxplusibmcga_8f[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcga_8f\");\nextern const uint8_t u8g2_font_pxplusibmcga_8r[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcga_8r\");\nextern const uint8_t u8g2_font_pxplusibmcga_8n[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcga_8n\");\nextern const uint8_t u8g2_font_pxplusibmcga_8u[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmcga_8u\");\nextern const uint8_t u8g2_font_pxplustandynewtv_8f[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_8f\");\nextern const uint8_t u8g2_font_pxplustandynewtv_8r[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_8r\");\nextern const uint8_t u8g2_font_pxplustandynewtv_8n[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_8n\");\nextern const uint8_t u8g2_font_pxplustandynewtv_8u[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_8u\");\nextern const uint8_t u8g2_font_pxplustandynewtv_t_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_t_all\");\nextern const uint8_t u8g2_font_pxplustandynewtv_8_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplustandynewtv_8_all\");\nextern const uint8_t u8g2_font_pxplusibmvga9_tf[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_tf\");\nextern const uint8_t u8g2_font_pxplusibmvga9_tr[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_tr\");\nextern const uint8_t u8g2_font_pxplusibmvga9_tn[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_tn\");\nextern const uint8_t u8g2_font_pxplusibmvga9_mf[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_mf\");\nextern const uint8_t u8g2_font_pxplusibmvga9_mr[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_mr\");\nextern const uint8_t u8g2_font_pxplusibmvga9_mn[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_mn\");\nextern const uint8_t u8g2_font_pxplusibmvga9_t_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_t_all\");\nextern const uint8_t u8g2_font_pxplusibmvga9_m_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga9_m_all\");\nextern const uint8_t u8g2_font_pxplusibmvga8_tf[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_tf\");\nextern const uint8_t u8g2_font_pxplusibmvga8_tr[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_tr\");\nextern const uint8_t u8g2_font_pxplusibmvga8_tn[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_tn\");\nextern const uint8_t u8g2_font_pxplusibmvga8_mf[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_mf\");\nextern const uint8_t u8g2_font_pxplusibmvga8_mr[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_mr\");\nextern const uint8_t u8g2_font_pxplusibmvga8_mn[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_mn\");\nextern const uint8_t u8g2_font_pxplusibmvga8_t_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_t_all\");\nextern const uint8_t u8g2_font_pxplusibmvga8_m_all[] U8G2_FONT_SECTION(\"u8g2_font_pxplusibmvga8_m_all\");\nextern const uint8_t u8g2_font_px437wyse700a_tf[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_tf\");\nextern const uint8_t u8g2_font_px437wyse700a_tr[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_tr\");\nextern const uint8_t u8g2_font_px437wyse700a_tn[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_tn\");\nextern const uint8_t u8g2_font_px437wyse700a_mf[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_mf\");\nextern const uint8_t u8g2_font_px437wyse700a_mr[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_mr\");\nextern const uint8_t u8g2_font_px437wyse700a_mn[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700a_mn\");\nextern const uint8_t u8g2_font_px437wyse700b_tf[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_tf\");\nextern const uint8_t u8g2_font_px437wyse700b_tr[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_tr\");\nextern const uint8_t u8g2_font_px437wyse700b_tn[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_tn\");\nextern const uint8_t u8g2_font_px437wyse700b_mf[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_mf\");\nextern const uint8_t u8g2_font_px437wyse700b_mr[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_mr\");\nextern const uint8_t u8g2_font_px437wyse700b_mn[] U8G2_FONT_SECTION(\"u8g2_font_px437wyse700b_mn\");\n\n/* end font list */\n\n/*==========================================*/\n/* u8g font mapping, might be incomplete.... */\n\n\n#define u8g_font_10x20   u8g2_font_10x20_tf\n#define u8g_font_10x20r   u8g2_font_10x20_tr\n#define u8g_font_4x6   u8g2_font_4x6_tf\n#define u8g_font_4x6r   u8g2_font_4x6_tr\n#define u8g_font_5x7   u8g2_font_5x7_tf\n#define u8g_font_5x7r   u8g2_font_5x7_tr\n#define u8g_font_5x8   u8g2_font_5x8_tf\n#define u8g_font_5x8r   u8g2_font_5x8_tr\n#define u8g_font_6x10   u8g2_font_6x10_tf\n#define u8g_font_6x10r   u8g2_font_6x10_tr\n#define u8g_font_6x12   u8g2_font_6x12_tf\n#define u8g_font_6x12r   u8g2_font_6x12_tr\n#define u8g_font_6x13B   u8g2_font_6x13B_tf\n#define u8g_font_6x13Br   u8g2_font_6x13B_tr\n#define u8g_font_6x13   u8g2_font_6x13_tf\n#define u8g_font_6x13r   u8g2_font_6x13_tr\n#define u8g_font_6x13O   u8g2_font_6x13O_tf\n#define u8g_font_6x13Or   u8g2_font_6x13O_tr\n#define u8g_font_7x13B   u8g2_font_7x13B_tf\n#define u8g_font_7x13Br   u8g2_font_7x13B_tr\n#define u8g_font_7x13   u8g2_font_7x13_tf\n#define u8g_font_7x13r   u8g2_font_7x13_tr\n#define u8g_font_7x13O   u8g2_font_7x13O_tf\n#define u8g_font_7x13Or   u8g2_font_7x13O_tr\n#define u8g_font_7x14B   u8g2_font_7x14B_tf\n#define u8g_font_7x14Br   u8g2_font_7x14B_tr\n#define u8g_font_7x14   u8g2_font_7x14_tf\n#define u8g_font_7x14r   u8g2_font_7x14_tr\n#define u8g_font_8x13B   u8g2_font_8x13B_tf\n#define u8g_font_8x13Br   u8g2_font_8x13B_tr\n#define u8g_font_8x13   u8g2_font_8x13_tf\n#define u8g_font_8x13r   u8g2_font_8x13_tr\n#define u8g_font_8x13O   u8g2_font_8x13O_tf\n#define u8g_font_8x13Or   u8g2_font_8x13O_tr\n#define u8g_font_9x15B   u8g2_font_9x15B_tf\n#define u8g_font_9x15Br   u8g2_font_9x15B_tr\n#define u8g_font_9x15   u8g2_font_9x15_tf\n#define u8g_font_9x15r   u8g2_font_9x15_tr\n#define u8g_font_9x18B   u8g2_font_9x18B_tf\n#define u8g_font_9x18   u8g2_font_9x18_tf\n#define u8g_font_9x18Br   u8g2_font_9x18B_tr\n#define u8g_font_9x18r   u8g2_font_9x18_tr\n#define u8g_font_cu12   u8g2_font_cu12_tf\n#define u8g_font_micro   u8g2_font_micro_tf\n#define u8g_font_unifont   u8g2_font_unifont_t_latin\n#define u8g_font_unifontr   u8g2_font_unifont_t_latin\n#define u8g_font_courB08   u8g2_font_courB08_tf\n#define u8g_font_courB08r   u8g2_font_courB08_tr\n#define u8g_font_courB10   u8g2_font_courB10_tf\n#define u8g_font_courB10r   u8g2_font_courB10_tr\n#define u8g_font_courB12   u8g2_font_courB12_tf\n#define u8g_font_courB12r   u8g2_font_courB12_tr\n#define u8g_font_courB14   u8g2_font_courB14_tf\n#define u8g_font_courB14r   u8g2_font_courB14_tr\n#define u8g_font_courB18   u8g2_font_courB18_tf\n#define u8g_font_courB18r   u8g2_font_courB18_tr\n#define u8g_font_courB24   u8g2_font_courB24_tf\n#define u8g_font_courB24r   u8g2_font_courB24_tr\n#define u8g_font_courB24n   u8g2_font_courB24_tn\n#define u8g_font_courR08   u8g2_font_courR08_tf\n#define u8g_font_courR08r   u8g2_font_courR08_tr\n#define u8g_font_courR10   u8g2_font_courR10_tf\n#define u8g_font_courR10r   u8g2_font_courR10_tr\n#define u8g_font_courR12   u8g2_font_courR12_tf\n#define u8g_font_courR12r   u8g2_font_courR12_tr\n#define u8g_font_courR14   u8g2_font_courR14_tf\n#define u8g_font_courR14r   u8g2_font_courR14_tr\n#define u8g_font_courR18   u8g2_font_courR18_tf\n#define u8g_font_courR18r   u8g2_font_courR18_tr\n#define u8g_font_courR24   u8g2_font_courR24_tf\n#define u8g_font_courR24r   u8g2_font_courR24_tr\n#define u8g_font_courR24n   u8g2_font_courR24_tn\n#define u8g_font_helvB08   u8g2_font_helvB08_tf\n#define u8g_font_helvB08r   u8g2_font_helvB08_tr\n#define u8g_font_helvB08n   u8g2_font_helvB08_tn\n#define u8g_font_helvB10   u8g2_font_helvB10_tf\n#define u8g_font_helvB10r   u8g2_font_helvB10_tr\n#define u8g_font_helvB10n   u8g2_font_helvB10_tn\n#define u8g_font_helvB12   u8g2_font_helvB12_tf\n#define u8g_font_helvB12r   u8g2_font_helvB12_tr\n#define u8g_font_helvB12n   u8g2_font_helvB12_tn\n#define u8g_font_helvB14   u8g2_font_helvB14_tf\n#define u8g_font_helvB14r   u8g2_font_helvB14_tr\n#define u8g_font_helvB14n   u8g2_font_helvB14_tn\n#define u8g_font_helvB18   u8g2_font_helvB18_tf\n#define u8g_font_helvB18r   u8g2_font_helvB18_tr\n#define u8g_font_helvB18n   u8g2_font_helvB18_tn\n#define u8g_font_helvB24   u8g2_font_helvB24_tf\n#define u8g_font_helvB24r   u8g2_font_helvB24_tr\n#define u8g_font_helvB24n   u8g2_font_helvB24_tn\n#define u8g_font_helvR08   u8g2_font_helvR08_tf\n#define u8g_font_helvR08r   u8g2_font_helvR08_tr\n#define u8g_font_helvR08n   u8g2_font_helvR08_tn\n#define u8g_font_helvR10   u8g2_font_helvR10_tf\n#define u8g_font_helvR10r   u8g2_font_helvR10_tr\n#define u8g_font_helvR10n   u8g2_font_helvR10_tn\n#define u8g_font_helvR12   u8g2_font_helvR12_tf\n#define u8g_font_helvR12r   u8g2_font_helvR12_tr\n#define u8g_font_helvR12n   u8g2_font_helvR12_tn\n#define u8g_font_helvR14   u8g2_font_helvR14_tf\n#define u8g_font_helvR14r   u8g2_font_helvR14_tr\n#define u8g_font_helvR14n   u8g2_font_helvR14_tn\n#define u8g_font_helvR18   u8g2_font_helvR18_tf\n#define u8g_font_helvR18r   u8g2_font_helvR18_tr\n#define u8g_font_helvR18n   u8g2_font_helvR18_tn\n#define u8g_font_helvR24   u8g2_font_helvR24_tf\n#define u8g_font_helvR24r   u8g2_font_helvR24_tr\n#define u8g_font_helvR24n   u8g2_font_helvR24_tn\n#define u8g_font_ncenB08   u8g2_font_ncenB08_tf\n#define u8g_font_ncenB08r   u8g2_font_ncenB08_tr\n#define u8g_font_ncenB10   u8g2_font_ncenB10_tf\n#define u8g_font_ncenB10r   u8g2_font_ncenB10_tr\n#define u8g_font_ncenB12   u8g2_font_ncenB12_tf\n#define u8g_font_ncenB12r   u8g2_font_ncenB12_tr\n#define u8g_font_ncenB14   u8g2_font_ncenB14_tf\n#define u8g_font_ncenB14r   u8g2_font_ncenB14_tr\n#define u8g_font_ncenB18   u8g2_font_ncenB18_tf\n#define u8g_font_ncenB18r   u8g2_font_ncenB18_tr\n#define u8g_font_ncenB24   u8g2_font_ncenB24_tf\n#define u8g_font_ncenB24r   u8g2_font_ncenB24_tr\n#define u8g_font_ncenB24n   u8g2_font_ncenB24_tn\n#define u8g_font_ncenR08   u8g2_font_ncenR08_tf\n#define u8g_font_ncenR08r   u8g2_font_ncenR08_tr\n#define u8g_font_ncenR10   u8g2_font_ncenR10_tf\n#define u8g_font_ncenR10r   u8g2_font_ncenR10_tr\n#define u8g_font_ncenR12   u8g2_font_ncenR12_tf\n#define u8g_font_ncenR12r   u8g2_font_ncenR12_tr\n#define u8g_font_ncenR14   u8g2_font_ncenR14_tf\n#define u8g_font_ncenR14r   u8g2_font_ncenR14_tr\n#define u8g_font_ncenR18   u8g2_font_ncenR18_tf\n#define u8g_font_ncenR18r   u8g2_font_ncenR18_tr\n#define u8g_font_ncenR24   u8g2_font_ncenR24_tf\n#define u8g_font_ncenR24r   u8g2_font_ncenR24_tr\n#define u8g_font_ncenR24n   u8g2_font_ncenR24_tn\n#define u8g_font_timB08   u8g2_font_timB08_tf\n#define u8g_font_timB08r   u8g2_font_timB08_tr\n#define u8g_font_timB10   u8g2_font_timB10_tf\n#define u8g_font_timB10r   u8g2_font_timB10_tr\n#define u8g_font_timB12   u8g2_font_timB12_tf\n#define u8g_font_timB12r   u8g2_font_timB12_tr\n#define u8g_font_timB14   u8g2_font_timB14_tf\n#define u8g_font_timB14r   u8g2_font_timB14_tr\n#define u8g_font_timB18   u8g2_font_timB18_tf\n#define u8g_font_timB18r   u8g2_font_timB18_tr\n#define u8g_font_timB24   u8g2_font_timB24_tf\n#define u8g_font_timB24r   u8g2_font_timB24_tr\n#define u8g_font_timB24n   u8g2_font_timB24_tn\n#define u8g_font_timR08   u8g2_font_timR08_tf\n#define u8g_font_timR08r   u8g2_font_timR08_tr\n#define u8g_font_timR10   u8g2_font_timR10_tf\n#define u8g_font_timR10r   u8g2_font_timR10_tr\n#define u8g_font_timR12   u8g2_font_timR12_tf\n#define u8g_font_timR12r   u8g2_font_timR12_tr\n#define u8g_font_timR14   u8g2_font_timR14_tf\n#define u8g_font_timR14r   u8g2_font_timR14_tr\n#define u8g_font_timR18   u8g2_font_timR18_tf\n#define u8g_font_timR18r   u8g2_font_timR18_tr\n#define u8g_font_timR24   u8g2_font_timR24_tf\n#define u8g_font_timR24r   u8g2_font_timR24_tr\n#define u8g_font_timR24n   u8g2_font_timR24_tn\n#define u8g_font_p01type   u8g2_font_p01type_tf\n#define u8g_font_p01typer   u8g2_font_p01type_tr\n#define u8g_font_lucasfont_alternate   u8g2_font_lucasfont_alternate_tf\n#define u8g_font_lucasfont_alternater   u8g2_font_lucasfont_alternate_tr\n#define u8g_font_chikita   u8g2_font_chikita_tf\n#define u8g_font_chikitar   u8g2_font_chikita_tr\n#define u8g_font_pixelle_micro   u8g2_font_pixelle_micro_tf\n#define u8g_font_pixelle_micror   u8g2_font_pixelle_micro_tr\n#define u8g_font_trixel_square   u8g2_font_trixel_square_tf\n#define u8g_font_trixel_squarer   u8g2_font_trixel_square_tr\n#define u8g_font_robot_de_niro   u8g2_font_robot_de_niro_tf\n#define u8g_font_robot_de_niror   u8g2_font_robot_de_niro_tr\n#define u8g_font_baby   u8g2_font_baby_tf\n#define u8g_font_babyr   u8g2_font_baby_tr\n#define u8g_font_blipfest_07   u8g2_font_blipfest_07_tr\n#define u8g_font_blipfest_07r   u8g2_font_blipfest_07_tr\n#define u8g_font_blipfest_07n   u8g2_font_blipfest_07_tn\n#define u8g_font_profont10   u8g2_font_profont10_tf\n#define u8g_font_profont10r   u8g2_font_profont10_tr\n#define u8g_font_profont11   u8g2_font_profont11_tf\n#define u8g_font_profont11r   u8g2_font_profont11_tr\n#define u8g_font_profont12   u8g2_font_profont12_tf\n#define u8g_font_profont12r   u8g2_font_profont12_tr\n#define u8g_font_profont15   u8g2_font_profont15_tf\n#define u8g_font_profont15r   u8g2_font_profont15_tr\n#define u8g_font_profont17   u8g2_font_profont17_tf\n#define u8g_font_profont17r   u8g2_font_profont17_tr\n#define u8g_font_profont22   u8g2_font_profont22_tf\n#define u8g_font_profont22r   u8g2_font_profont22_tr\n#define u8g_font_profont29   u8g2_font_profont29_tf\n#define u8g_font_profont29r   u8g2_font_profont29_tr\n\n\n/*==========================================*/\n/* C++ compatible */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_bitmap.c",
    "content": "/*\n\n  u8g2_bitmap.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n\nvoid u8g2_SetBitmapMode(u8g2_t *u8g2, uint8_t is_transparent) {\n  u8g2->bitmap_transparency = is_transparent;\n}\n\n/*\n  x,y \tPosition on the display\n  len\t\tLength of bitmap line in pixel. Note: This differs from u8glib which had a bytecount here.\n  b\t\tPointer to the bitmap line.\n  Only draw pixels which are set.\n*/\n\nvoid u8g2_DrawHorizontalBitmap(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, const uint8_t *b)\n{\n  uint8_t mask;\n  uint8_t color = u8g2->draw_color;\n  uint8_t ncolor = (color == 0 ? 1 : 0);\n\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+len, y+1) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  mask = 128;\n  while(len > 0)\n  {\n    if ( *b & mask ) {\n      u8g2->draw_color = color;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    } else if ( u8g2->bitmap_transparency == 0 ) {\n      u8g2->draw_color = ncolor;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    }\n\n    x++;\n    mask >>= 1;\n    if ( mask == 0 )\n    {\n      mask = 128;\n      b++;\n    }\n    len--;\n  }\n  u8g2->draw_color = color;\n}\n\n\n/* u8glib compatible bitmap draw function */\nvoid u8g2_DrawBitmap(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t cnt, u8g2_uint_t h, const uint8_t *bitmap)\n{\n  u8g2_uint_t w;\n  w = cnt;\n  w *= 8;\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  while( h > 0 )\n  {\n    u8g2_DrawHorizontalBitmap(u8g2, x, y, w, bitmap);\n    bitmap += cnt;\n    y++;\n    h--;\n  }\n}\n\n\n\nvoid u8g2_DrawHXBM(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, const uint8_t *b)\n{\n  uint8_t mask;\n  uint8_t color = u8g2->draw_color;\n  uint8_t ncolor = (color == 0 ? 1 : 0);\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+len, y+1) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  mask = 1;\n  while(len > 0) {\n    if ( *b & mask ) {\n      u8g2->draw_color = color;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    } else if ( u8g2->bitmap_transparency == 0 ) {\n      u8g2->draw_color = ncolor;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    }\n    x++;\n    mask <<= 1;\n    if ( mask == 0 )\n    {\n      mask = 1;\n      b++;\n    }\n    len--;\n  }\n  u8g2->draw_color = color;\n}\n\n\nvoid u8g2_DrawXBM(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap)\n{\n  u8g2_uint_t blen;\n  blen = w;\n  blen += 7;\n  blen >>= 3;\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  while( h > 0 )\n  {\n    u8g2_DrawHXBM(u8g2, x, y, w, bitmap);\n    bitmap += blen;\n    y++;\n    h--;\n  }\n}\n\n\n\n\n\n\nvoid u8g2_DrawHXBMP(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, const uint8_t *b)\n{\n  uint8_t mask;\n  uint8_t color = u8g2->draw_color;\n  uint8_t ncolor = (color == 0 ? 1 : 0);\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+len, y+1) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  mask = 1;\n  while(len > 0)\n  {\n    if( u8x8_pgm_read(b) & mask ) {\n      u8g2->draw_color = color;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    } else if( u8g2->bitmap_transparency == 0 ) {\n      u8g2->draw_color = ncolor;\n      u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n    }\n   \n    x++;\n    mask <<= 1;\n    if ( mask == 0 )\n    {\n      mask = 1;\n      b++;\n    }\n    len--;\n  }\n  u8g2->draw_color = color;\n}\n\n\nvoid u8g2_DrawXBMP(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, const uint8_t *bitmap)\n{\n  u8g2_uint_t blen;\n  blen = w;\n  blen += 7;\n  blen >>= 3;\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  while( h > 0 )\n  {\n    u8g2_DrawHXBMP(u8g2, x, y, w, bitmap);\n    bitmap += blen;\n    y++;\n    h--;\n  }\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_box.c",
    "content": "/*\n\n  u8g2_box.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n/*\n  draw a filled box\n  restriction: does not work for w = 0 or h = 0\n*/\nvoid u8g2_DrawBox(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h)\n{\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  while( h != 0 )\n  { \n    u8g2_DrawHVLine(u8g2, x, y, w, 0);\n    y++;    \n    h--;\n  }\n}\n\n\n/*\n  draw a frame (empty box)\n  restriction: does not work for w = 0 or h = 0\n*/\nvoid u8g2_DrawFrame(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h)\n{\n  u8g2_uint_t xtmp = x;\n  \n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  u8g2_DrawHVLine(u8g2, x, y, w, 0);\n  if (h >= 2) {\n    h-=2;\n    y++;\n    if (h > 0) {\n      u8g2_DrawHVLine(u8g2, x, y, h, 1);\n      x+=w;\n      x--;\n      u8g2_DrawHVLine(u8g2, x, y, h, 1);\n      y+=h;\n    }\n    u8g2_DrawHVLine(u8g2, xtmp, y, w, 0);\n  }\n}\n\n\n\n\nvoid u8g2_DrawRBox(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r)\n{\n  u8g2_uint_t xl, yu;\n  u8g2_uint_t yl, xr;\n\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n\n  xl = x;\n  xl += r;\n  yu = y;\n  yu += r;\n \n  xr = x;\n  xr += w;\n  xr -= r;\n  xr -= 1;\n  \n  yl = y;\n  yl += h;\n  yl -= r; \n  yl -= 1;\n\n  u8g2_DrawDisc(u8g2, xl, yu, r, U8G2_DRAW_UPPER_LEFT);\n  u8g2_DrawDisc(u8g2, xr, yu, r, U8G2_DRAW_UPPER_RIGHT);\n  u8g2_DrawDisc(u8g2, xl, yl, r, U8G2_DRAW_LOWER_LEFT);\n  u8g2_DrawDisc(u8g2, xr, yl, r, U8G2_DRAW_LOWER_RIGHT);\n\n  {\n    u8g2_uint_t ww, hh;\n\n    ww = w;\n    ww -= r;\n    ww -= r;\n    xl++;\n    yu++;\n    \n    if ( ww >= 3 )\n    {\n      ww -= 2;\n      u8g2_DrawBox(u8g2, xl, y, ww, r+1);\n      u8g2_DrawBox(u8g2, xl, yl, ww, r+1);\n    }\n    \n    hh = h;\n    hh -= r;\n    hh -= r;\n    //h--;\n    if ( hh >= 3 )\n    {\n      hh -= 2;\n      u8g2_DrawBox(u8g2, x, yu, w, hh);\n    }\n  }\n}\n\n\nvoid u8g2_DrawRFrame(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t h, u8g2_uint_t r)\n{\n  u8g2_uint_t xl, yu;\n\n#ifdef U8G2_WITH_INTERSECTION\n  if ( u8g2_IsIntersection(u8g2, x, y, x+w, y+h) == 0 ) \n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n\n  xl = x;\n  xl += r;\n  yu = y;\n  yu += r;\n \n  {\n    u8g2_uint_t yl, xr;\n      \n    xr = x;\n    xr += w;\n    xr -= r;\n    xr -= 1;\n    \n    yl = y;\n    yl += h;\n    yl -= r; \n    yl -= 1;\n\n    u8g2_DrawCircle(u8g2, xl, yu, r, U8G2_DRAW_UPPER_LEFT);\n    u8g2_DrawCircle(u8g2, xr, yu, r, U8G2_DRAW_UPPER_RIGHT);\n    u8g2_DrawCircle(u8g2, xl, yl, r, U8G2_DRAW_LOWER_LEFT);\n    u8g2_DrawCircle(u8g2, xr, yl, r, U8G2_DRAW_LOWER_RIGHT);\n  }\n\n  {\n    u8g2_uint_t ww, hh;\n\n    ww = w;\n    ww -= r;\n    ww -= r;\n    hh = h;\n    hh -= r;\n    hh -= r;\n    \n    xl++;\n    yu++;\n    \n    if ( ww >= 3 )\n    {\n      ww -= 2;\n      h--;\n      u8g2_DrawHLine(u8g2, xl, y, ww);\n      u8g2_DrawHLine(u8g2, xl, y+h, ww);\n    }\n    \n    if ( hh >= 3 )\n    {\n      hh -= 2;\n      w--;\n      u8g2_DrawVLine(u8g2, x, yu, hh);\n      u8g2_DrawVLine(u8g2, x+w, yu, hh);\n    }\n  }\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_buffer.c",
    "content": "/* \n\n  u8g2_buffer.c \n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n#include <string.h>\n\n/*============================================*/\nvoid u8g2_ClearBuffer(u8g2_t *u8g2)\n{\n  size_t cnt;\n  cnt = u8g2_GetU8x8(u8g2)->display_info->tile_width;\n  cnt *= u8g2->tile_buf_height;\n  cnt *= 8;\n  memset(u8g2->tile_buf_ptr, 0, cnt);\n}\n\n/*============================================*/\n\nstatic void u8g2_send_tile_row(u8g2_t *u8g2, uint8_t src_tile_row, uint8_t dest_tile_row)\n{\n  uint8_t *ptr;\n  uint16_t offset;\n  uint8_t w;\n  \n  w = u8g2_GetU8x8(u8g2)->display_info->tile_width;\n  offset = src_tile_row;\n  ptr = u8g2->tile_buf_ptr;\n  offset *= w;\n  offset *= 8;\n  ptr += offset;\n  u8x8_DrawTile(u8g2_GetU8x8(u8g2), 0, dest_tile_row, w, ptr);\n}\n\n/* \n  write the buffer to the display RAM. \n  For most displays, this will make the content visible to the user.\n  Some displays (like the SSD1606) require a u8x8_RefreshDisplay()\n*/\nstatic void u8g2_send_buffer(u8g2_t *u8g2) U8X8_NOINLINE;\nstatic void u8g2_send_buffer(u8g2_t *u8g2)\n{\n  uint8_t src_row;\n  uint8_t src_max;\n  uint8_t dest_row;\n  uint8_t dest_max;\n\n  src_row = 0;\n  src_max = u8g2->tile_buf_height;\n  dest_row = u8g2->tile_curr_row;\n  dest_max = u8g2_GetU8x8(u8g2)->display_info->tile_height;\n  \n  do\n  {\n    u8g2_send_tile_row(u8g2, src_row, dest_row);\n    src_row++;\n    dest_row++;\n  } while( src_row < src_max && dest_row < dest_max );\n}\n\n/* same as u8g2_send_buffer but also send the DISPLAY_REFRESH message (used by SSD1606) */\nvoid u8g2_SendBuffer(u8g2_t *u8g2)\n{\n  u8g2_send_buffer(u8g2);\n  u8x8_RefreshDisplay( u8g2_GetU8x8(u8g2) );  \n}\n\n/*============================================*/\nvoid u8g2_SetBufferCurrTileRow(u8g2_t *u8g2, uint8_t row)\n{\n  u8g2->tile_curr_row = row;\n  u8g2->cb->update_dimension(u8g2);\n  u8g2->cb->update_page_win(u8g2);\n}\n\nvoid u8g2_FirstPage(u8g2_t *u8g2)\n{\n  if ( u8g2->is_auto_page_clear )\n  {\n    u8g2_ClearBuffer(u8g2);\n  }\n  u8g2_SetBufferCurrTileRow(u8g2, 0);\n}\n\nuint8_t u8g2_NextPage(u8g2_t *u8g2)\n{\n  uint8_t row;\n  u8g2_send_buffer(u8g2);\n  row = u8g2->tile_curr_row;\n  row += u8g2->tile_buf_height;\n  if ( row >= u8g2_GetU8x8(u8g2)->display_info->tile_height )\n  {\n    u8x8_RefreshDisplay( u8g2_GetU8x8(u8g2) );\n    return 0;\n  }\n  if ( u8g2->is_auto_page_clear )\n  {\n    u8g2_ClearBuffer(u8g2);\n  }\n  u8g2_SetBufferCurrTileRow(u8g2, row);\n  return 1;\n}\n\n\n\n/*============================================*/\n/*\n  Description:\n    Update a sub area of the display, given by tile position, width and height.\n    The arguments are \"tile\" coordinates. Any u8g2 rotation is ignored.\n    This procedure only checks whether full buffer mode is active.\n    There is no error checking for the arguments: It is the responsibility of the\n    user to ensure, that the provided arguments are correct.\n\n  Limitations:\n    - Only available in full buffer mode (will not do anything in page mode)\n    - Tile positions and sizes (pixel position divided by 8)\n    - Any display rotation/mirror is ignored\n    - Only works with displays, which support U8x8 API\n    - Will not send the e-paper refresh message (will probably not work with e-paper devices)\n*/\nvoid u8g2_UpdateDisplayArea(u8g2_t *u8g2, uint8_t  tx, uint8_t ty, uint8_t tw, uint8_t th)\n{\n  uint16_t page_size;\n  uint8_t *ptr;\n  \n  /* check, whether we are in full buffer mode */\n  if ( u8g2->tile_buf_height != u8g2_GetU8x8(u8g2)->display_info->tile_height )\n    return; /* not in full buffer mode, do nothing */\n\n  page_size = u8g2->pixel_buf_width;  /* 8*u8g2->u8g2_GetU8x8(u8g2)->display_info->tile_width */\n    \n  ptr = u8g2_GetBufferPtr(u8g2);\n  ptr += tx*8;\n  ptr += page_size*ty;\n  \n  while( th > 0 )\n  {\n    u8x8_DrawTile( u8g2_GetU8x8(u8g2), tx, ty, tw, ptr );\n    ptr += page_size;\n    ty++;\n    th--;\n  }  \n}\n\n/* same as sendBuffer, but does not send the ePaper refresh message */\nvoid u8g2_UpdateDisplay(u8g2_t *u8g2)\n{\n  u8g2_send_buffer(u8g2);\n}\n\n\n/*============================================*/\n\n/* vertical_top memory architecture */\nvoid u8g2_WriteBufferPBM(u8g2_t *u8g2, void (*out)(const char *s))\n{\n  u8x8_capture_write_pbm_pre(u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), out);\n  u8x8_capture_write_pbm_buffer(u8g2_GetBufferPtr(u8g2), u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), u8x8_capture_get_pixel_1, out);\n}\n\nvoid u8g2_WriteBufferXBM(u8g2_t *u8g2, void (*out)(const char *s))\n{\n  u8x8_capture_write_xbm_pre(u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), out);\n  u8x8_capture_write_xbm_buffer(u8g2_GetBufferPtr(u8g2), u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), u8x8_capture_get_pixel_1, out);\n}\n\n\n/* horizontal right memory architecture */\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nvoid u8g2_WriteBufferPBM2(u8g2_t *u8g2, void (*out)(const char *s))\n{\n  u8x8_capture_write_pbm_pre(u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), out);\n  u8x8_capture_write_pbm_buffer(u8g2_GetBufferPtr(u8g2), u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), u8x8_capture_get_pixel_2, out);\n}\n\nvoid u8g2_WriteBufferXBM2(u8g2_t *u8g2, void (*out)(const char *s))\n{\n  u8x8_capture_write_xbm_pre(u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), out);\n  u8x8_capture_write_xbm_buffer(u8g2_GetBufferPtr(u8g2), u8g2_GetBufferTileWidth(u8g2), u8g2_GetBufferTileHeight(u8g2), u8x8_capture_get_pixel_2, out);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_circle.c",
    "content": "/*\n\n  u8g2_circle.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n/*==============================================*/\n/* Circle */\n\nstatic void u8g2_draw_circle_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option) U8G2_NOINLINE;\n\nstatic void u8g2_draw_circle_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option)\n{\n    /* upper right */\n    if ( option & U8G2_DRAW_UPPER_RIGHT )\n    {\n      u8g2_DrawPixel(u8g2, x0 + x, y0 - y);\n      u8g2_DrawPixel(u8g2, x0 + y, y0 - x);\n    }\n    \n    /* upper left */\n    if ( option & U8G2_DRAW_UPPER_LEFT )\n    {\n      u8g2_DrawPixel(u8g2, x0 - x, y0 - y);\n      u8g2_DrawPixel(u8g2, x0 - y, y0 - x);\n    }\n    \n    /* lower right */\n    if ( option & U8G2_DRAW_LOWER_RIGHT )\n    {\n      u8g2_DrawPixel(u8g2, x0 + x, y0 + y);\n      u8g2_DrawPixel(u8g2, x0 + y, y0 + x);\n    }\n    \n    /* lower left */\n    if ( option & U8G2_DRAW_LOWER_LEFT )\n    {\n      u8g2_DrawPixel(u8g2, x0 - x, y0 + y);\n      u8g2_DrawPixel(u8g2, x0 - y, y0 + x);\n    }\n}\n\nstatic void u8g2_draw_circle(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option)\n{\n    u8g2_int_t f;\n    u8g2_int_t ddF_x;\n    u8g2_int_t ddF_y;\n    u8g2_uint_t x;\n    u8g2_uint_t y;\n\n    f = 1;\n    f -= rad;\n    ddF_x = 1;\n    ddF_y = 0;\n    ddF_y -= rad;\n    ddF_y *= 2;\n    x = 0;\n    y = rad;\n\n    u8g2_draw_circle_section(u8g2, x, y, x0, y0, option);\n    \n    while ( x < y )\n    {\n      if (f >= 0) \n      {\n        y--;\n        ddF_y += 2;\n        f += ddF_y;\n      }\n      x++;\n      ddF_x += 2;\n      f += ddF_x;\n\n      u8g2_draw_circle_section(u8g2, x, y, x0, y0, option);    \n    }\n}\n\nvoid u8g2_DrawCircle(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option)\n{\n  /* check for bounding box */\n#ifdef U8G2_WITH_INTERSECTION\n  {\n    if ( u8g2_IsIntersection(u8g2, x0-rad, y0-rad, x0+rad+1, y0+rad+1) == 0 ) \n      return;\n  }\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  \n  /* draw circle */\n  u8g2_draw_circle(u8g2, x0, y0, rad, option);\n}\n\n/*==============================================*/\n/* Disk */\n\nstatic void u8g2_draw_disc_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option) U8G2_NOINLINE;\n\nstatic void u8g2_draw_disc_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option)\n{\n    /* upper right */\n    if ( option & U8G2_DRAW_UPPER_RIGHT )\n    {\n      u8g2_DrawVLine(u8g2, x0+x, y0-y, y+1);\n      u8g2_DrawVLine(u8g2, x0+y, y0-x, x+1);\n    }\n    \n    /* upper left */\n    if ( option & U8G2_DRAW_UPPER_LEFT )\n    {\n      u8g2_DrawVLine(u8g2, x0-x, y0-y, y+1);\n      u8g2_DrawVLine(u8g2, x0-y, y0-x, x+1);\n    }\n    \n    /* lower right */\n    if ( option & U8G2_DRAW_LOWER_RIGHT )\n    {\n      u8g2_DrawVLine(u8g2, x0+x, y0, y+1);\n      u8g2_DrawVLine(u8g2, x0+y, y0, x+1);\n    }\n    \n    /* lower left */\n    if ( option & U8G2_DRAW_LOWER_LEFT )\n    {\n      u8g2_DrawVLine(u8g2, x0-x, y0, y+1);\n      u8g2_DrawVLine(u8g2, x0-y, y0, x+1);\n    }\n}\n\nstatic void u8g2_draw_disc(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option)\n{\n  u8g2_int_t f;\n  u8g2_int_t ddF_x;\n  u8g2_int_t ddF_y;\n  u8g2_uint_t x;\n  u8g2_uint_t y;\n\n  f = 1;\n  f -= rad;\n  ddF_x = 1;\n  ddF_y = 0;\n  ddF_y -= rad;\n  ddF_y *= 2;\n  x = 0;\n  y = rad;\n\n  u8g2_draw_disc_section(u8g2, x, y, x0, y0, option);\n  \n  while ( x < y )\n  {\n    if (f >= 0) \n    {\n      y--;\n      ddF_y += 2;\n      f += ddF_y;\n    }\n    x++;\n    ddF_x += 2;\n    f += ddF_x;\n\n    u8g2_draw_disc_section(u8g2, x, y, x0, y0, option);    \n  }\n}\n\nvoid u8g2_DrawDisc(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rad, uint8_t option)\n{\n  /* check for bounding box */\n#ifdef U8G2_WITH_INTERSECTION\n  {\n    if ( u8g2_IsIntersection(u8g2, x0-rad, y0-rad, x0+rad+1, y0+rad+1) == 0 ) \n      return;\n  }\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  /* draw disc */\n  u8g2_draw_disc(u8g2, x0, y0, rad, option);\n}\n\n/*==============================================*/\n/* Ellipse */\n\n/*\n  Source: \n    Foley, Computer Graphics, p 90\n*/\nstatic void u8g2_draw_ellipse_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option) U8G2_NOINLINE;\nstatic void u8g2_draw_ellipse_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option)\n{\n    /* upper right */\n    if ( option & U8G2_DRAW_UPPER_RIGHT )\n    {\n      u8g2_DrawPixel(u8g2, x0 + x, y0 - y);\n    }\n    \n    /* upper left */\n    if ( option & U8G2_DRAW_UPPER_LEFT )\n    {\n      u8g2_DrawPixel(u8g2, x0 - x, y0 - y);\n    }\n    \n    /* lower right */\n    if ( option & U8G2_DRAW_LOWER_RIGHT )\n    {\n      u8g2_DrawPixel(u8g2, x0 + x, y0 + y);\n    }\n    \n    /* lower left */\n    if ( option & U8G2_DRAW_LOWER_LEFT )\n    {\n      u8g2_DrawPixel(u8g2, x0 - x, y0 + y);\n    }\n}\n\nstatic void u8g2_draw_ellipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option)\n{\n  u8g2_uint_t x, y;\n  u8g2_long_t xchg, ychg;\n  u8g2_long_t err;\n  u8g2_long_t rxrx2;\n  u8g2_long_t ryry2;\n  u8g2_long_t stopx, stopy;\n  \n  rxrx2 = rx;\n  rxrx2 *= rx;\n  rxrx2 *= 2;\n  \n  ryry2 = ry;\n  ryry2 *= ry;\n  ryry2 *= 2;\n  \n  x = rx;\n  y = 0;\n  \n  xchg = 1;\n  xchg -= rx;\n  xchg -= rx;\n  xchg *= ry;\n  xchg *= ry;\n  \n  ychg = rx;\n  ychg *= rx;\n  \n  err = 0;\n  \n  stopx = ryry2;\n  stopx *= rx;\n  stopy = 0;\n  \n  while( stopx >= stopy )\n  {\n    u8g2_draw_ellipse_section(u8g2, x, y, x0, y0, option);\n    y++;\n    stopy += rxrx2;\n    err += ychg;\n    ychg += rxrx2;\n    if ( 2*err+xchg > 0 )\n    {\n      x--;\n      stopx -= ryry2;\n      err += xchg;\n      xchg += ryry2;      \n    }\n  }\n\n  x = 0;\n  y = ry;\n  \n  xchg = ry;\n  xchg *= ry;\n  \n  ychg = 1;\n  ychg -= ry;\n  ychg -= ry;\n  ychg *= rx;\n  ychg *= rx;\n  \n  err = 0;\n  \n  stopx = 0;\n\n  stopy = rxrx2;\n  stopy *= ry;\n  \n\n  while( stopx <= stopy )\n  {\n    u8g2_draw_ellipse_section(u8g2, x, y, x0, y0, option);\n    x++;\n    stopx += ryry2;\n    err += xchg;\n    xchg += ryry2;\n    if ( 2*err+ychg > 0 )\n    {\n      y--;\n      stopy -= rxrx2;\n      err += ychg;\n      ychg += rxrx2;\n    }\n  }\n  \n}\n\nvoid u8g2_DrawEllipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option)\n{\n  /* check for bounding box */\n#ifdef U8G2_WITH_INTERSECTION\n  {\n    if ( u8g2_IsIntersection(u8g2, x0-rx, y0-ry, x0+rx+1, y0+ry+1) == 0 ) \n      return;\n  }\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  u8g2_draw_ellipse(u8g2, x0, y0, rx, ry, option);\n}\n\n/*==============================================*/\n/* Filled Ellipse */\n\nstatic void u8g2_draw_filled_ellipse_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option) U8G2_NOINLINE;\nstatic void u8g2_draw_filled_ellipse_section(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t x0, u8g2_uint_t y0, uint8_t option)\n{\n    /* upper right */\n    if ( option & U8G2_DRAW_UPPER_RIGHT )\n    {\n      u8g2_DrawVLine(u8g2, x0+x, y0-y, y+1);\n    }\n    \n    /* upper left */\n    if ( option & U8G2_DRAW_UPPER_LEFT )\n    {\n      u8g2_DrawVLine(u8g2, x0-x, y0-y, y+1);\n    }\n    \n    /* lower right */\n    if ( option & U8G2_DRAW_LOWER_RIGHT )\n    {\n      u8g2_DrawVLine(u8g2, x0+x, y0, y+1);\n    }\n    \n    /* lower left */\n    if ( option & U8G2_DRAW_LOWER_LEFT )\n    {\n      u8g2_DrawVLine(u8g2, x0-x, y0, y+1);\n    }\n}\n\nstatic void u8g2_draw_filled_ellipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option)\n{\n  u8g2_uint_t x, y;\n  u8g2_long_t xchg, ychg;\n  u8g2_long_t err;\n  u8g2_long_t rxrx2;\n  u8g2_long_t ryry2;\n  u8g2_long_t stopx, stopy;\n  \n  rxrx2 = rx;\n  rxrx2 *= rx;\n  rxrx2 *= 2;\n  \n  ryry2 = ry;\n  ryry2 *= ry;\n  ryry2 *= 2;\n  \n  x = rx;\n  y = 0;\n  \n  xchg = 1;\n  xchg -= rx;\n  xchg -= rx;\n  xchg *= ry;\n  xchg *= ry;\n  \n  ychg = rx;\n  ychg *= rx;\n  \n  err = 0;\n  \n  stopx = ryry2;\n  stopx *= rx;\n  stopy = 0;\n  \n  while( stopx >= stopy )\n  {\n    u8g2_draw_filled_ellipse_section(u8g2, x, y, x0, y0, option);\n    y++;\n    stopy += rxrx2;\n    err += ychg;\n    ychg += rxrx2;\n    if ( 2*err+xchg > 0 )\n    {\n      x--;\n      stopx -= ryry2;\n      err += xchg;\n      xchg += ryry2;      \n    }\n  }\n\n  x = 0;\n  y = ry;\n  \n  xchg = ry;\n  xchg *= ry;\n  \n  ychg = 1;\n  ychg -= ry;\n  ychg -= ry;\n  ychg *= rx;\n  ychg *= rx;\n  \n  err = 0;\n  \n  stopx = 0;\n\n  stopy = rxrx2;\n  stopy *= ry;\n  \n\n  while( stopx <= stopy )\n  {\n    u8g2_draw_filled_ellipse_section(u8g2, x, y, x0, y0, option);\n    x++;\n    stopx += ryry2;\n    err += xchg;\n    xchg += ryry2;\n    if ( 2*err+ychg > 0 )\n    {\n      y--;\n      stopy -= rxrx2;\n      err += ychg;\n      ychg += rxrx2;\n    }\n  }\n  \n}\n\nvoid u8g2_DrawFilledEllipse(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t rx, u8g2_uint_t ry, uint8_t option)\n{\n  /* check for bounding box */\n#ifdef U8G2_WITH_INTERSECTION\n  {\n    if ( u8g2_IsIntersection(u8g2, x0-rx, y0-ry, x0+rx+1, y0+ry+1) == 0 ) \n      return;\n  }\n#endif /* U8G2_WITH_INTERSECTION */\n  \n  u8g2_draw_filled_ellipse(u8g2, x0, y0, rx, ry, option);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_cleardisplay.c",
    "content": "/*\n\n  u8g2_cleardisplay.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n#include \"u8g2.h\"\n\n/* Clear screen buffer & display reliable for all u8g2 displays. */\n/* This is done with u8g2 picture loop, because we can not use the u8x8 function in all cases */\nvoid u8g2_ClearDisplay(u8g2_t *u8g2)\n{\n  u8g2_FirstPage(u8g2);\n  do {\n  } while ( u8g2_NextPage(u8g2) );\n  /* \n    This function is usually called during startup (u8g2.begin()).\n    However the user might want to use full buffer mode with clear and \n    send commands.\n    This will not work because the current tile row is modified by the picture \n    loop above. To fix this, reset the tile row to 0, issue #370\n    A workaround would be, that the user sets the current tile row to 0 manually.\n  */\n  u8g2_SetBufferCurrTileRow(u8g2, 0);  \n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_d_memory.c",
    "content": "/* u8g2_d_memory.c */\n/* generated code, codebuild, u8g2 project */\n\n#include \"u8g2.h\"\n\nuint8_t *u8g2_m_16_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[512];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[1024];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_10_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[1280];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_255_2_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[2040];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_255_2_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[4080];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_255_2_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[4080];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_9_5_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[72];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_9_5_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[144];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_9_5_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 5;\n  return 0;\n  #else\n  static uint8_t buf[360];\n  *page_cnt = 5;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[1024];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_12_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[96];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_12_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_12_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 12;\n  return 0;\n  #else\n  static uint8_t buf[1152];\n  *page_cnt = 12;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[2048];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_20_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_20_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_20_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 20;\n  return 0;\n  #else\n  static uint8_t buf[3200];\n  *page_cnt = 20;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[512];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[2048];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_6_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_6_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_6_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 6;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 6;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_6_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[48];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_6_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[96];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_6_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_2_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[96];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_2_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_2_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_12_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_12_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_16_12_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 12;\n  return 0;\n  #else\n  static uint8_t buf[1536];\n  *page_cnt = 12;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[512];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[1024];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[96];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[768];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[768];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_50_30_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[400];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_50_30_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[800];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_50_30_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 30;\n  return 0;\n  #else\n  static uint8_t buf[12000];\n  *page_cnt = 30;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_18_21_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[144];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_18_21_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[288];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_18_21_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 21;\n  return 0;\n  #else\n  static uint8_t buf[3024];\n  *page_cnt = 21;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_13_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[104];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_13_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[208];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_13_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[832];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_11_6_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[88];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_11_6_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[176];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_11_6_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 6;\n  return 0;\n  #else\n  static uint8_t buf[528];\n  *page_cnt = 6;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_9_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[96];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_9_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_12_9_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 9;\n  return 0;\n  #else\n  static uint8_t buf[864];\n  *page_cnt = 9;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[1536];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[240];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[480];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[1920];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_15_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[240];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_15_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[480];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_15_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 15;\n  return 0;\n  #else\n  static uint8_t buf[3600];\n  *page_cnt = 15;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[240];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[480];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[3840];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[2560];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_13_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_13_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_13_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 13;\n  return 0;\n  #else\n  static uint8_t buf[2080];\n  *page_cnt = 13;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_20_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[240];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_20_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[480];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_30_20_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 20;\n  return 0;\n  #else\n  static uint8_t buf[4800];\n  *page_cnt = 20;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[512];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[4096];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_40_30_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_40_30_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[640];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_40_30_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 30;\n  return 0;\n  #else\n  static uint8_t buf[9600];\n  *page_cnt = 30;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[1280];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[136];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[272];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[544];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_8_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[136];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_8_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[272];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_17_8_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 8;\n  return 0;\n  #else\n  static uint8_t buf[1088];\n  *page_cnt = 8;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_17_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_17_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[768];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_17_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 17;\n  return 0;\n  #else\n  static uint8_t buf[6528];\n  *page_cnt = 17;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_20_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[256];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_20_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[512];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_32_20_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 20;\n  return 0;\n  #else\n  static uint8_t buf[5120];\n  *page_cnt = 20;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_13_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[176];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_13_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[352];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_13_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 13;\n  return 0;\n  #else\n  static uint8_t buf[2288];\n  *page_cnt = 13;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_12_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[192];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_12_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_24_12_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 12;\n  return 0;\n  #else\n  static uint8_t buf[2304];\n  *page_cnt = 12;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_10_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_10_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_10_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 10;\n  return 0;\n  #else\n  static uint8_t buf[1600];\n  *page_cnt = 10;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_4_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_4_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_4_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 4;\n  return 0;\n  #else\n  static uint8_t buf[640];\n  *page_cnt = 4;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_17_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[160];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_17_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[320];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_20_17_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 17;\n  return 0;\n  #else\n  static uint8_t buf[2720];\n  *page_cnt = 17;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_9_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[176];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_9_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[352];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_22_9_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 9;\n  return 0;\n  #else\n  static uint8_t buf[1584];\n  *page_cnt = 9;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_25_25_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[200];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_25_25_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[400];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_25_25_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 25;\n  return 0;\n  #else\n  static uint8_t buf[5000];\n  *page_cnt = 25;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_37_16_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[296];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_37_16_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[592];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_37_16_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 16;\n  return 0;\n  #else\n  static uint8_t buf[4736];\n  *page_cnt = 16;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_1_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_1_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[128];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_8_1_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_4_1_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[32];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_4_1_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[64];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_4_1_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[32];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_1_1_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[8];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_1_1_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[16];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_1_1_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[8];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_30_1(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 1;\n  return 0;\n  #else\n  static uint8_t buf[384];\n  *page_cnt = 1;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_30_2(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 2;\n  return 0;\n  #else\n  static uint8_t buf[768];\n  *page_cnt = 2;\n  return buf;\n  #endif\n}\nuint8_t *u8g2_m_48_30_f(uint8_t *page_cnt)\n{\n  #ifdef U8G2_USE_DYNAMIC_ALLOC\n  *page_cnt = 30;\n  return 0;\n  #else\n  static uint8_t buf[11520];\n  *page_cnt = 30;\n  return buf;\n  #endif\n}\n/* end of generated code */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_d_setup.c",
    "content": "/* u8g2_d_setup.c */\n/* generated code, codebuild, u8g2 project */\n\n#include \"u8g2.h\"\n\n/* ssd1305 */\n/* ssd1305 1 */\nvoid u8g2_Setup_ssd1305_128x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x32_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 2 */\nvoid u8g2_Setup_ssd1305_128x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x32_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 f */\nvoid u8g2_Setup_ssd1305_128x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x32_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 */\n/* ssd1305 1 */\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 2 */\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 f */\nvoid u8g2_Setup_ssd1305_i2c_128x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x32_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x32_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 */\n/* ssd1305 1 */\nvoid u8g2_Setup_ssd1305_128x64_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x64_raystar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 2 */\nvoid u8g2_Setup_ssd1305_128x64_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x64_raystar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 f */\nvoid u8g2_Setup_ssd1305_128x64_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_128x64_raystar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 */\n/* ssd1305 1 */\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 2 */\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1305 f */\nvoid u8g2_Setup_ssd1305_i2c_128x64_adafruit_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_adafruit, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1305_i2c_128x64_raystar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1305_128x64_raystar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_2040x16_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_2040x16, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_255_2_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_2040x16_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_2040x16, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_255_2_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_2040x16_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_2040x16, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_255_2_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_alt0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_alt0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x64_alt0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x80_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x80_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_10_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_vcomh0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x64_alt0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x64_alt0, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_72x40_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_72x40_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_72x40_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_72x40_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_72x40_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_128x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_i2c_128x64_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_noname, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_vcomh0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_vcomh0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1106_i2c_128x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x64_winstar, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_72x40_wise_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_72x40_wise_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_72x40_wise_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_i2c_72x40_wise_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_72x40_wise, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_9_5_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_i2c_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_i2c_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_i2c_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_64x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_64x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_64x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_i2c_64x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_i2c_64x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_i2c_64x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_64x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_i2c_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_96x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_pimoroni_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_seeed_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_pimoroni_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_seeed_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_pimoroni_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_seeed_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 */\n/* sh1107 1 */\nvoid u8g2_Setup_sh1107_i2c_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 2 */\nvoid u8g2_Setup_sh1107_i2c_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1107 f */\nvoid u8g2_Setup_sh1107_i2c_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_pimoroni_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_pimoroni_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_sh1107_i2c_seeed_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1107_seeed_128x128, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 */\n/* sh1108 1 */\nvoid u8g2_Setup_sh1108_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 2 */\nvoid u8g2_Setup_sh1108_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 f */\nvoid u8g2_Setup_sh1108_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 */\n/* sh1108 1 */\nvoid u8g2_Setup_sh1108_i2c_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 2 */\nvoid u8g2_Setup_sh1108_i2c_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1108 f */\nvoid u8g2_Setup_sh1108_i2c_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1108_160x160, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1122 */\n/* sh1122 1 */\nvoid u8g2_Setup_sh1122_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sh1122 2 */\nvoid u8g2_Setup_sh1122_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sh1122 f */\nvoid u8g2_Setup_sh1122_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sh1122 */\n/* sh1122 1 */\nvoid u8g2_Setup_sh1122_i2c_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sh1122 2 */\nvoid u8g2_Setup_sh1122_i2c_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sh1122 f */\nvoid u8g2_Setup_sh1122_i2c_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1122_256x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_128x32_univision_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x32_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_128x32_univision_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x32_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_128x32_univision_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_128x32_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_128x32_univision_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_univision, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_128x32_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_128x32_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_128x32_visionox_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_128x32_visionox_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_128x32_visionox_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 */\n/* sh1106 1 */\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 2 */\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sh1106 f */\nvoid u8g2_Setup_sh1106_i2c_128x32_visionox_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sh1106_128x32_visionox, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_64x48_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_64x48_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_64x48_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_64x48_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x48_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_6_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_48x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_48x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_48x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_48x64_winstar_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_48x64_winstar, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_6_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_64x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_64x32_1f_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_64x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_64x32_1f_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_64x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_64x32_1f_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_64x32_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_noname, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1306_i2c_64x32_1f_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_64x32_1f, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_96x16_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_96x16_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_96x16_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 */\n/* ssd1306 1 */\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 2 */\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1306 f */\nvoid u8g2_Setup_ssd1306_i2c_96x16_er_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1306_96x16_er, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_2_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 */\n/* ssd1309 1 */\nvoid u8g2_Setup_ssd1309_128x64_noname2_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 2 */\nvoid u8g2_Setup_ssd1309_128x64_noname2_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 f */\nvoid u8g2_Setup_ssd1309_128x64_noname2_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 */\n/* ssd1309 1 */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 2 */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 f */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname2_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname2, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 */\n/* ssd1309 1 */\nvoid u8g2_Setup_ssd1309_128x64_noname0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 2 */\nvoid u8g2_Setup_ssd1309_128x64_noname0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 f */\nvoid u8g2_Setup_ssd1309_128x64_noname0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 */\n/* ssd1309 1 */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 2 */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1309 f */\nvoid u8g2_Setup_ssd1309_i2c_128x64_noname0_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1309_128x64_noname0, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 */\n/* ssd1316 1 */\nvoid u8g2_Setup_ssd1316_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 2 */\nvoid u8g2_Setup_ssd1316_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 f */\nvoid u8g2_Setup_ssd1316_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 */\n/* ssd1316 1 */\nvoid u8g2_Setup_ssd1316_i2c_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 2 */\nvoid u8g2_Setup_ssd1316_i2c_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1316 f */\nvoid u8g2_Setup_ssd1316_i2c_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1316_128x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 */\n/* ssd1317 1 */\nvoid u8g2_Setup_ssd1317_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 2 */\nvoid u8g2_Setup_ssd1317_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 f */\nvoid u8g2_Setup_ssd1317_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 */\n/* ssd1317 1 */\nvoid u8g2_Setup_ssd1317_i2c_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 2 */\nvoid u8g2_Setup_ssd1317_i2c_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1317 f */\nvoid u8g2_Setup_ssd1317_i2c_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1317_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 */\n/* ssd1318 1 */\nvoid u8g2_Setup_ssd1318_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_128x96_xcp_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 2 */\nvoid u8g2_Setup_ssd1318_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_128x96_xcp_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 f */\nvoid u8g2_Setup_ssd1318_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_128x96_xcp_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 */\n/* ssd1318 1 */\nvoid u8g2_Setup_ssd1318_i2c_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 2 */\nvoid u8g2_Setup_ssd1318_i2c_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1318 f */\nvoid u8g2_Setup_ssd1318_i2c_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1318_i2c_128x96_xcp_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1318_128x96_xcp, u8x8_cad_ssd13xx_fast_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 */\n/* ssd1325 1 */\nvoid u8g2_Setup_ssd1325_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 2 */\nvoid u8g2_Setup_ssd1325_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 f */\nvoid u8g2_Setup_ssd1325_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 */\n/* ssd1325 1 */\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 2 */\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1325 f */\nvoid u8g2_Setup_ssd1325_i2c_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1325_nhd_128x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 */\n/* ssd0323 1 */\nvoid u8g2_Setup_ssd0323_os128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 2 */\nvoid u8g2_Setup_ssd0323_os128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 f */\nvoid u8g2_Setup_ssd0323_os128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 */\n/* ssd0323 1 */\nvoid u8g2_Setup_ssd0323_i2c_os128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 2 */\nvoid u8g2_Setup_ssd0323_i2c_os128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd0323 f */\nvoid u8g2_Setup_ssd0323_i2c_os128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd0323_os128064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 */\n/* ssd1326 1 */\nvoid u8g2_Setup_ssd1326_er_256x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 2 */\nvoid u8g2_Setup_ssd1326_er_256x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 f */\nvoid u8g2_Setup_ssd1326_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 */\n/* ssd1326 1 */\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 2 */\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1326 f */\nvoid u8g2_Setup_ssd1326_i2c_er_256x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1326_er_256x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_i2c_ws_96x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_96x64, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_i2c_seeed_96x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_seeed_96x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_ea_w128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_midas_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_ws_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_ea_w128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_midas_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_ws_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_ea_w128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_midas_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_ws_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_i2c_ea_w128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ea_w128128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_midas_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_midas_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1327_i2c_ws_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_ws_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_visionox_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_visionox_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_visionox_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 */\n/* ssd1327 1 */\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 2 */\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1327 f */\nvoid u8g2_Setup_ssd1327_i2c_visionox_128x96_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1327_visionox_128x96, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1329 */\n/* ssd1329 1 */\nvoid u8g2_Setup_ssd1329_128x96_noname_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1329_128x96_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1329 2 */\nvoid u8g2_Setup_ssd1329_128x96_noname_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1329_128x96_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1329 f */\nvoid u8g2_Setup_ssd1329_128x96_noname_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1329_128x96_noname, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ld7032 */\n/* ld7032 1 */\nvoid u8g2_Setup_ld7032_60x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_60x32_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ld7032 2 */\nvoid u8g2_Setup_ld7032_60x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_60x32_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ld7032 f */\nvoid u8g2_Setup_ld7032_60x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_60x32_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ld7032 */\n/* ld7032 1 */\nvoid u8g2_Setup_ld7032_i2c_60x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ld7032 2 */\nvoid u8g2_Setup_ld7032_i2c_60x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ld7032 f */\nvoid u8g2_Setup_ld7032_i2c_60x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ld7032_i2c_60x32_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ld7032_60x32_alt, u8x8_cad_ld7032_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_p_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_p_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_p_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_s_192x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_s_192x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_s_192x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_192x32, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_p_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_p_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_p_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 */\n/* st7920 1 */\nvoid u8g2_Setup_st7920_s_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 2 */\nvoid u8g2_Setup_st7920_s_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7920 f */\nvoid u8g2_Setup_st7920_s_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7920_128x64, u8x8_cad_st7920_spi, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh03 */\n/* ls013b7dh03 1 */\nvoid u8g2_Setup_ls013b7dh03_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh03_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh03 2 */\nvoid u8g2_Setup_ls013b7dh03_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh03_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh03 f */\nvoid u8g2_Setup_ls013b7dh03_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh03_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls027b7dh01 */\n/* ls027b7dh01 1 */\nvoid u8g2_Setup_ls027b7dh01_400x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_m0_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls027b7dh01 2 */\nvoid u8g2_Setup_ls027b7dh01_400x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_m0_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls027b7dh01 f */\nvoid u8g2_Setup_ls027b7dh01_400x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_ls027b7dh01_m0_400x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls027b7dh01_m0_400x240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_50_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh05 */\n/* ls013b7dh05 1 */\nvoid u8g2_Setup_ls013b7dh05_144x168_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh05_144x168, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_18_21_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh05 2 */\nvoid u8g2_Setup_ls013b7dh05_144x168_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh05_144x168, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_18_21_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ls013b7dh05 f */\nvoid u8g2_Setup_ls013b7dh05_144x168_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ls013b7dh05_144x168, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_18_21_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* uc1701 */\n/* uc1701 1 */\nvoid u8g2_Setup_uc1701_ea_dogs102_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_ea_dogs102, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_13_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1701 2 */\nvoid u8g2_Setup_uc1701_ea_dogs102_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_ea_dogs102, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_13_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1701 f */\nvoid u8g2_Setup_uc1701_ea_dogs102_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_ea_dogs102, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_13_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1701 */\n/* uc1701 1 */\nvoid u8g2_Setup_uc1701_mini12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_mini12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1701 2 */\nvoid u8g2_Setup_uc1701_mini12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_mini12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1701 f */\nvoid u8g2_Setup_uc1701_mini12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1701_mini12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcd8544 */\n/* pcd8544 1 */\nvoid u8g2_Setup_pcd8544_84x48_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcd8544_84x48, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_11_6_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcd8544 2 */\nvoid u8g2_Setup_pcd8544_84x48_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcd8544_84x48, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_11_6_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcd8544 f */\nvoid u8g2_Setup_pcd8544_84x48_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcd8544_84x48, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_11_6_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcf8812 */\n/* pcf8812 1 */\nvoid u8g2_Setup_pcf8812_96x65_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcf8812_96x65, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcf8812 2 */\nvoid u8g2_Setup_pcf8812_96x65_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcf8812_96x65, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* pcf8812 f */\nvoid u8g2_Setup_pcf8812_96x65_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_pcf8812_96x65, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* hx1230 */\n/* hx1230 1 */\nvoid u8g2_Setup_hx1230_96x68_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_hx1230_96x68, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* hx1230 2 */\nvoid u8g2_Setup_hx1230_96x68_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_hx1230_96x68, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* hx1230 f */\nvoid u8g2_Setup_hx1230_96x68_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_hx1230_96x68, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_12_9_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 */\n/* uc1604 1 */\nvoid u8g2_Setup_uc1604_jlx19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 2 */\nvoid u8g2_Setup_uc1604_jlx19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 f */\nvoid u8g2_Setup_uc1604_jlx19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 */\n/* uc1604 1 */\nvoid u8g2_Setup_uc1604_i2c_jlx19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 2 */\nvoid u8g2_Setup_uc1604_i2c_jlx19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1604 f */\nvoid u8g2_Setup_uc1604_i2c_jlx19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1604_jlx19264, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_erc24064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_dem240064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_erc24064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_dem240064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_erc24064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_dem240064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_i2c_erc24064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_i2c_dem240064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_i2c_erc24064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_i2c_dem240064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_i2c_erc24064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc24064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_uc1608_i2c_dem240064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_dem240064, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_erc240120_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_erc240120_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_erc240120_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_i2c_erc240120_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_i2c_erc240120_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_i2c_erc240120_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_erc240120, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_15_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 */\n/* uc1608 1 */\nvoid u8g2_Setup_uc1608_i2c_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 2 */\nvoid u8g2_Setup_uc1608_i2c_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1608 f */\nvoid u8g2_Setup_uc1608_i2c_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1608_240x128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1638 */\n/* uc1638 1 */\nvoid u8g2_Setup_uc1638_160x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1638_160x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1638 2 */\nvoid u8g2_Setup_uc1638_160x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1638_160x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1638 f */\nvoid u8g2_Setup_uc1638_160x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1638_160x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 */\n/* uc1610 1 */\nvoid u8g2_Setup_uc1610_ea_dogxl160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 2 */\nvoid u8g2_Setup_uc1610_ea_dogxl160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 f */\nvoid u8g2_Setup_uc1610_ea_dogxl160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 */\n/* uc1610 1 */\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 2 */\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1610 f */\nvoid u8g2_Setup_uc1610_i2c_ea_dogxl160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1610_ea_dogxl160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_ea_dogm240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_ea_dogm240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_ea_dogm240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_i2c_ea_dogm240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogm240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_ea_dogxl240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_ea_dogxl240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_ea_dogxl240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_i2c_ea_dogxl240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ea_dogxl240, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_ew50850_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_ew50850_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_ew50850_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_i2c_ew50850_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_i2c_ew50850_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_i2c_ew50850_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ew50850, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_cg160160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_cg160160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_cg160160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_i2c_cg160160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_i2c_cg160160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_i2c_cg160160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_cg160160, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_ids4073_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_ids4073_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_ids4073_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 */\n/* uc1611 1 */\nvoid u8g2_Setup_uc1611_i2c_ids4073_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 2 */\nvoid u8g2_Setup_uc1611_i2c_ids4073_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1611 f */\nvoid u8g2_Setup_uc1611_i2c_ids4073_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1611_ids4073, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7511 */\n/* st7511 1 */\nvoid u8g2_Setup_st7511_avd_320x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7511_avd_320x240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7511 2 */\nvoid u8g2_Setup_st7511_avd_320x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7511_avd_320x240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7511 f */\nvoid u8g2_Setup_st7511_avd_320x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7511_avd_320x240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 */\n/* st7528 1 */\nvoid u8g2_Setup_st7528_nhd_c160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 2 */\nvoid u8g2_Setup_st7528_nhd_c160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 f */\nvoid u8g2_Setup_st7528_nhd_c160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 */\n/* st7528 1 */\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 2 */\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 f */\nvoid u8g2_Setup_st7528_i2c_nhd_c160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_nhd_c160100, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 */\n/* st7528 1 */\nvoid u8g2_Setup_st7528_erc16064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 2 */\nvoid u8g2_Setup_st7528_erc16064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 f */\nvoid u8g2_Setup_st7528_erc16064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 */\n/* st7528 1 */\nvoid u8g2_Setup_st7528_i2c_erc16064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 2 */\nvoid u8g2_Setup_st7528_i2c_erc16064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7528 f */\nvoid u8g2_Setup_st7528_i2c_erc16064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7528_erc16064, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 */\n/* uc1617 1 */\nvoid u8g2_Setup_uc1617_jlx128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 2 */\nvoid u8g2_Setup_uc1617_jlx128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 f */\nvoid u8g2_Setup_uc1617_jlx128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 */\n/* uc1617 1 */\nvoid u8g2_Setup_uc1617_i2c_jlx128128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 2 */\nvoid u8g2_Setup_uc1617_i2c_jlx128128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1617 f */\nvoid u8g2_Setup_uc1617_i2c_jlx128128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1617_jlx128128, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 */\n/* st7565 1 */\nvoid u8g2_Setup_st7565_ea_dogm128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6063_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6063, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_64128n_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_64128n, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_zolen_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_zolen_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6059_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6059, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_ks0713_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ks0713, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864_alt, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_nhd_c12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 2 */\nvoid u8g2_Setup_st7565_ea_dogm128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6063_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6063, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_64128n_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_64128n, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_zolen_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_zolen_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6059_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6059, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_ks0713_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ks0713, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864_alt, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_nhd_c12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 f */\nvoid u8g2_Setup_st7565_ea_dogm128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6063_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6063, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_64128n_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_64128n, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_zolen_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_zolen_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lm6059_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lm6059, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_ks0713_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ks0713, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_lx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_lx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_erc12864_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_erc12864_alt, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_nhd_c12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7565_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 */\n/* st7565 1 */\nvoid u8g2_Setup_st7565_nhd_c12832_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12832, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 2 */\nvoid u8g2_Setup_st7565_nhd_c12832_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12832, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 f */\nvoid u8g2_Setup_st7565_nhd_c12832_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_nhd_c12832, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 */\n/* uc1601 1 */\nvoid u8g2_Setup_uc1601_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 2 */\nvoid u8g2_Setup_uc1601_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 f */\nvoid u8g2_Setup_uc1601_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 */\n/* uc1601 1 */\nvoid u8g2_Setup_uc1601_i2c_128x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 2 */\nvoid u8g2_Setup_uc1601_i2c_128x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* uc1601 f */\nvoid u8g2_Setup_uc1601_i2c_128x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_uc1601_128x32, u8x8_cad_uc16xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 */\n/* st7565 1 */\nvoid u8g2_Setup_st7565_ea_dogm132_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 2 */\nvoid u8g2_Setup_st7565_ea_dogm132_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7565 f */\nvoid u8g2_Setup_st7565_ea_dogm132_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7565_ea_dogm132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 */\n/* st7567 1 */\nvoid u8g2_Setup_st7567_pi_132x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_pi_132x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 2 */\nvoid u8g2_Setup_st7567_pi_132x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_pi_132x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 f */\nvoid u8g2_Setup_st7567_pi_132x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_pi_132x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_17_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 */\n/* st7567 1 */\nvoid u8g2_Setup_st7567_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064i_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064i, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_os12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_os12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 2 */\nvoid u8g2_Setup_st7567_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064i_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064i, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_os12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_os12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 f */\nvoid u8g2_Setup_st7567_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_enh_dg128064i_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_enh_dg128064i, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_os12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_os12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 */\n/* st7567 1 */\nvoid u8g2_Setup_st7567_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_hem6432_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 2 */\nvoid u8g2_Setup_st7567_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_hem6432_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 f */\nvoid u8g2_Setup_st7567_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_hem6432_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 */\n/* st7567 1 */\nvoid u8g2_Setup_st7567_i2c_64x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_i2c_hem6432_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 2 */\nvoid u8g2_Setup_st7567_i2c_64x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_i2c_hem6432_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7567 f */\nvoid u8g2_Setup_st7567_i2c_64x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_64x32, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st7567_i2c_hem6432_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7567_hem6432, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 */\n/* st7571 1 */\nvoid u8g2_Setup_st7571_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 2 */\nvoid u8g2_Setup_st7571_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 f */\nvoid u8g2_Setup_st7571_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 */\n/* st7571 1 */\nvoid u8g2_Setup_st7571_i2c_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 2 */\nvoid u8g2_Setup_st7571_i2c_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7571 f */\nvoid u8g2_Setup_st7571_i2c_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7571_128x128, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7586s */\n/* st7586s 1 */\nvoid u8g2_Setup_st7586s_s028hn118a_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_s028hn118a, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_17_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7586s 2 */\nvoid u8g2_Setup_st7586s_s028hn118a_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_s028hn118a, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_17_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7586s f */\nvoid u8g2_Setup_st7586s_s028hn118a_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_s028hn118a, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_17_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7586s */\n/* st7586s 1 */\nvoid u8g2_Setup_st7586s_erc240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_erc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_st7586s_ymc240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_ymc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7586s 2 */\nvoid u8g2_Setup_st7586s_erc240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_erc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_st7586s_ymc240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_ymc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7586s f */\nvoid u8g2_Setup_st7586s_erc240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_erc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_st7586s_ymc240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7586s_ymc240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* st7588 */\n/* st7588 1 */\nvoid u8g2_Setup_st7588_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7588 2 */\nvoid u8g2_Setup_st7588_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7588 f */\nvoid u8g2_Setup_st7588_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7588 */\n/* st7588 1 */\nvoid u8g2_Setup_st7588_i2c_jlx12864_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7588 2 */\nvoid u8g2_Setup_st7588_i2c_jlx12864_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st7588 f */\nvoid u8g2_Setup_st7588_i2c_jlx12864_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st7588_jlx12864, u8x8_cad_ssd13xx_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx256128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_wo256x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx256128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_wo256x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx256128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_wo256x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx256128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_wo256x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx256128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_wo256x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx256128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_wo256x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_wo256x128, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx256160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160m_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx256160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160m_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx256160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160m_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_jlx256160_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx256160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160m_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx256160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160m_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx256160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160m_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160m, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_st75256_i2c_jlx256160_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx256160_alt, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx240160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx240160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx240160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx240160, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx25664_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx25664_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx25664_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx25664_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx25664_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx25664_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx25664, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx172104_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx172104_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx172104_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx172104_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx172104_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx172104_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx172104, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_jlx19296_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_jlx19296_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_jlx19296_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 */\n/* st75256 1 */\nvoid u8g2_Setup_st75256_i2c_jlx19296_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 2 */\nvoid u8g2_Setup_st75256_i2c_jlx19296_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75256 f */\nvoid u8g2_Setup_st75256_i2c_jlx19296_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75256_jlx19296, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_12_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 */\n/* st75320 1 */\nvoid u8g2_Setup_st75320_jlx320240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 2 */\nvoid u8g2_Setup_st75320_jlx320240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 f */\nvoid u8g2_Setup_st75320_jlx320240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 */\n/* st75320 1 */\nvoid u8g2_Setup_st75320_i2c_jlx320240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 2 */\nvoid u8g2_Setup_st75320_i2c_jlx320240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* st75320 f */\nvoid u8g2_Setup_st75320_i2c_jlx320240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_st75320_jlx320240, u8x8_cad_st75256_i2c, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* nt7534 */\n/* nt7534 1 */\nvoid u8g2_Setup_nt7534_tg12864r_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_nt7534_tg12864r, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* nt7534 2 */\nvoid u8g2_Setup_nt7534_tg12864r_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_nt7534_tg12864r, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* nt7534 f */\nvoid u8g2_Setup_nt7534_tg12864r_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_nt7534_tg12864r, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist3020 */\n/* ist3020 1 */\nvoid u8g2_Setup_ist3020_erc19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist3020_erc19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist3020 2 */\nvoid u8g2_Setup_ist3020_erc19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist3020_erc19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist3020 f */\nvoid u8g2_Setup_ist3020_erc19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist3020_erc19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist7920 */\n/* ist7920 1 */\nvoid u8g2_Setup_ist7920_128x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist7920_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist7920 2 */\nvoid u8g2_Setup_ist7920_128x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist7920_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ist7920 f */\nvoid u8g2_Setup_ist7920_128x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ist7920_128x128, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sbn1661 */\n/* sbn1661 1 */\nvoid u8g2_Setup_sbn1661_122x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sbn1661_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sbn1661 2 */\nvoid u8g2_Setup_sbn1661_122x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sbn1661_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sbn1661 f */\nvoid u8g2_Setup_sbn1661_122x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sbn1661_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sed1520 */\n/* sed1520 1 */\nvoid u8g2_Setup_sed1520_122x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1520_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sed1520 2 */\nvoid u8g2_Setup_sed1520_122x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1520_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sed1520 f */\nvoid u8g2_Setup_sed1520_122x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1520_122x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 */\n/* ks0108 1 */\nvoid u8g2_Setup_ks0108_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 2 */\nvoid u8g2_Setup_ks0108_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 f */\nvoid u8g2_Setup_ks0108_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_128x64, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 */\n/* ks0108 1 */\nvoid u8g2_Setup_ks0108_erm19264_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_erm19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 2 */\nvoid u8g2_Setup_ks0108_erm19264_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_erm19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ks0108 f */\nvoid u8g2_Setup_ks0108_erm19264_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ks0108_erm19264, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_24_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* lc7981 */\n/* lc7981 1 */\nvoid u8g2_Setup_lc7981_160x80_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 2 */\nvoid u8g2_Setup_lc7981_160x80_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 f */\nvoid u8g2_Setup_lc7981_160x80_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 */\n/* lc7981 1 */\nvoid u8g2_Setup_lc7981_160x160_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x160, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 2 */\nvoid u8g2_Setup_lc7981_160x160_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x160, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 f */\nvoid u8g2_Setup_lc7981_160x160_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_160x160, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_20_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 */\n/* lc7981 1 */\nvoid u8g2_Setup_lc7981_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 2 */\nvoid u8g2_Setup_lc7981_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 f */\nvoid u8g2_Setup_lc7981_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 */\n/* lc7981 1 */\nvoid u8g2_Setup_lc7981_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 2 */\nvoid u8g2_Setup_lc7981_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* lc7981 f */\nvoid u8g2_Setup_lc7981_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_lc7981_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 */\n/* t6963 1 */\nvoid u8g2_Setup_t6963_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 2 */\nvoid u8g2_Setup_t6963_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 f */\nvoid u8g2_Setup_t6963_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 */\n/* t6963 1 */\nvoid u8g2_Setup_t6963_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 2 */\nvoid u8g2_Setup_t6963_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 f */\nvoid u8g2_Setup_t6963_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_240x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 */\n/* t6963 1 */\nvoid u8g2_Setup_t6963_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_256x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 2 */\nvoid u8g2_Setup_t6963_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_256x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 f */\nvoid u8g2_Setup_t6963_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_256x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 */\n/* t6963 1 */\nvoid u8g2_Setup_t6963_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_t6963_128x64_alt_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64_alt, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 2 */\nvoid u8g2_Setup_t6963_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_t6963_128x64_alt_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64_alt, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 f */\nvoid u8g2_Setup_t6963_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\nvoid u8g2_Setup_t6963_128x64_alt_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_128x64_alt, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 */\n/* t6963 1 */\nvoid u8g2_Setup_t6963_160x80_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 2 */\nvoid u8g2_Setup_t6963_160x80_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* t6963 f */\nvoid u8g2_Setup_t6963_160x80_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_t6963_160x80, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_10_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ssd1320 */\n/* ssd1320 1 */\nvoid u8g2_Setup_ssd1320_160x32_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_4_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1320 2 */\nvoid u8g2_Setup_ssd1320_160x32_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_4_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1320 f */\nvoid u8g2_Setup_ssd1320_160x32_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x32, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_4_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1320 */\n/* ssd1320 1 */\nvoid u8g2_Setup_ssd1320_160x132_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_17_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1320 2 */\nvoid u8g2_Setup_ssd1320_160x132_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_17_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1320 f */\nvoid u8g2_Setup_ssd1320_160x132_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1320_160x132, u8x8_cad_001, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_17_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 */\n/* ssd1322 1 */\nvoid u8g2_Setup_ssd1322_nhd_256x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_256x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 2 */\nvoid u8g2_Setup_ssd1322_nhd_256x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_256x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 f */\nvoid u8g2_Setup_ssd1322_nhd_256x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_256x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_32_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 */\n/* ssd1322 1 */\nvoid u8g2_Setup_ssd1322_nhd_128x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_128x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 2 */\nvoid u8g2_Setup_ssd1322_nhd_128x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_128x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1322 f */\nvoid u8g2_Setup_ssd1322_nhd_128x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1322_nhd_128x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_16_8_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1606 */\n/* ssd1606 1 */\nvoid u8g2_Setup_ssd1606_172x72_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1606_172x72, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_9_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1606 2 */\nvoid u8g2_Setup_ssd1606_172x72_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1606_172x72, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_9_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1606 f */\nvoid u8g2_Setup_ssd1606_172x72_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1606_172x72, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_22_9_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1607 */\n/* ssd1607 1 */\nvoid u8g2_Setup_ssd1607_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_gd_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_gd_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_ws_200x200_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_ws_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1607 2 */\nvoid u8g2_Setup_ssd1607_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_gd_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_gd_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_ws_200x200_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_ws_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* ssd1607 f */\nvoid u8g2_Setup_ssd1607_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_gd_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_gd_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_ssd1607_ws_200x200_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ssd1607_ws_200x200, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_25_25_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* il3820 */\n/* il3820 1 */\nvoid u8g2_Setup_il3820_296x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_il3820_v2_296x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_v2_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* il3820 2 */\nvoid u8g2_Setup_il3820_296x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_il3820_v2_296x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_v2_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* il3820 f */\nvoid u8g2_Setup_il3820_296x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\nvoid u8g2_Setup_il3820_v2_296x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_il3820_v2_296x128, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_37_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* sed1330 */\n/* sed1330 1 */\nvoid u8g2_Setup_sed1330_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1330_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sed1330 2 */\nvoid u8g2_Setup_sed1330_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1330_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* sed1330 f */\nvoid u8g2_Setup_sed1330_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_sed1330_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 */\n/* ra8835 1 */\nvoid u8g2_Setup_ra8835_nhd_240x128_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_nhd_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 2 */\nvoid u8g2_Setup_ra8835_nhd_240x128_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_nhd_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 f */\nvoid u8g2_Setup_ra8835_nhd_240x128_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_nhd_240x128, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_30_16_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 */\n/* ra8835 1 */\nvoid u8g2_Setup_ra8835_320x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_320x240, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 2 */\nvoid u8g2_Setup_ra8835_320x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_320x240, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* ra8835 f */\nvoid u8g2_Setup_ra8835_320x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_ra8835_320x240, u8x8_cad_100, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_40_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 */\n/* max7219 1 */\nvoid u8g2_Setup_max7219_64x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_64x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_1_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 2 */\nvoid u8g2_Setup_max7219_64x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_64x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_1_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 f */\nvoid u8g2_Setup_max7219_64x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_64x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_8_1_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 */\n/* max7219 1 */\nvoid u8g2_Setup_max7219_32x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_32x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_4_1_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 2 */\nvoid u8g2_Setup_max7219_32x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_32x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_4_1_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 f */\nvoid u8g2_Setup_max7219_32x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_32x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_4_1_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 */\n/* max7219 1 */\nvoid u8g2_Setup_max7219_8x8_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_8x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_1_1_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 2 */\nvoid u8g2_Setup_max7219_8x8_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_8x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_1_1_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* max7219 f */\nvoid u8g2_Setup_max7219_8x8_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_max7219_8x8, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_1_1_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* s1d15e06 */\n/* s1d15e06 1 */\nvoid u8g2_Setup_s1d15e06_160100_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15e06_160100, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* s1d15e06 2 */\nvoid u8g2_Setup_s1d15e06_160100_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15e06_160100, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* s1d15e06 f */\nvoid u8g2_Setup_s1d15e06_160100_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15e06_160100, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* s1d15721 */\n/* s1d15721 1 */\nvoid u8g2_Setup_s1d15721_240x64_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15721_240x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* s1d15721 2 */\nvoid u8g2_Setup_s1d15721_240x64_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15721_240x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* s1d15721 f */\nvoid u8g2_Setup_s1d15721_240x64_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_s1d15721_240x64, u8x8_cad_011, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_20_13_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n/* a2printer */\n/* a2printer 1 */\nvoid u8g2_Setup_a2printer_384x240_1(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_a2printer_384x240, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_30_1(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* a2printer 2 */\nvoid u8g2_Setup_a2printer_384x240_2(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_a2printer_384x240, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_30_2(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* a2printer f */\nvoid u8g2_Setup_a2printer_384x240_f(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  uint8_t tile_buf_height;\n  uint8_t *buf;\n  u8g2_SetupDisplay(u8g2, u8x8_d_a2printer_384x240, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  buf = u8g2_m_48_30_f(&tile_buf_height);\n  u8g2_SetupBuffer(u8g2, buf, tile_buf_height, u8g2_ll_hvline_horizontal_right_lsb, rotation);\n}\n/* end of generated code */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_font.c",
    "content": "/*\n\n  u8g2_font.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n/* size of the font data structure, there is no struct or class... */\n/* this is the size for the new font format */\n#define U8G2_FONT_DATA_STRUCT_SIZE 23\n\n/*\n  font data:\n\n  offset\tbytes\tdescription\n  0\t\t1\t\tglyph_cnt\t\tnumber of glyphs\n  1\t\t1\t\tbbx_mode\t0: proportional, 1: common height, 2: monospace, 3: multiple of 8\n  2\t\t1\t\tbits_per_0\tglyph rle parameter\n  3\t\t1\t\tbits_per_1\tglyph rle parameter\n\n  4\t\t1\t\tbits_per_char_width\t\tglyph rle parameter\n  5\t\t1\t\tbits_per_char_height\tglyph rle parameter\n  6\t\t1\t\tbits_per_char_x\t\tglyph rle parameter\n  7\t\t1\t\tbits_per_char_y\t\tglyph rle parameter\n  8\t\t1\t\tbits_per_delta_x\t\tglyph rle parameter\n\n  9\t\t1\t\tmax_char_width\n  10\t\t1\t\tmax_char_height\n  11\t\t1\t\tx offset\n  12\t\t1\t\ty offset (descent)\n  \n  13\t\t1\t\tascent (capital A)\n  14\t\t1\t\tdescent (lower g)\n  15\t\t1\t\tascent '('\n  16\t\t1\t\tdescent ')'\n  \n  17\t\t1\t\tstart pos 'A' high byte\n  18\t\t1\t\tstart pos 'A' low byte\n\n  19\t\t1\t\tstart pos 'a' high byte\n  20\t\t1\t\tstart pos 'a' low byte\n\n  21\t\t1\t\tstart pos unicode high byte\n  22\t\t1\t\tstart pos unicode low byte\n\n  Font build mode, 0: proportional, 1: common height, 2: monospace, 3: multiple of 8\n\n  Font build mode 0:\t\t\n    - \"t\"\n    - Ref height mode: U8G2_FONT_HEIGHT_MODE_TEXT, U8G2_FONT_HEIGHT_MODE_XTEXT or U8G2_FONT_HEIGHT_MODE_ALL\n    - use in transparent mode only (does not look good in solid mode)\n    - most compact format\n    - different font heights possible\n    \n  Font build mode 1:\t\t\n    - \"h\"\n    - Ref height mode: U8G2_FONT_HEIGHT_MODE_ALL\n    - transparent or solid mode\n    - The height of the glyphs depend on the largest glyph in the font. This means font height depends on postfix \"r\", \"f\" and \"n\".\n\n*/\n\n/* use case: What is the width and the height of the minimal box into which string s fints? */\nvoid u8g2_font_GetStrSize(const void *font, const char *s, u8g2_uint_t *width, u8g2_uint_t *height);\nvoid u8g2_font_GetStrSizeP(const void *font, const char *s, u8g2_uint_t *width, u8g2_uint_t *height);\n\n/* use case: lower left edge of a minimal box is known, what is the correct x, y position for the string draw procedure */\nvoid u8g2_font_AdjustXYToDraw(const void *font, const char *s, u8g2_uint_t *x, u8g2_uint_t *y);\nvoid u8g2_font_AdjustXYToDrawP(const void *font, const char *s, u8g2_uint_t *x, u8g2_uint_t *y);\n\n/* use case: Baseline origin known, return minimal box */\nvoid u8g2_font_GetStrMinBox(u8g2_t *u8g2, const void *font, const char *s, u8g2_uint_t *x, u8g2_uint_t *y, u8g2_uint_t *width, u8g2_uint_t *height);\n\n/* procedures */\n\n/*========================================================================*/\n/* low level byte and word access */\n\n/* removed NOINLINE, because it leads to smaller code, might also be faster */\n//static uint8_t u8g2_font_get_byte(const uint8_t *font, uint8_t offset) U8G2_NOINLINE;\nstatic uint8_t u8g2_font_get_byte(const uint8_t *font, uint8_t offset)\n{\n  font += offset;\n  return u8x8_pgm_read( font );  \n}\n\nstatic uint16_t u8g2_font_get_word(const uint8_t *font, uint8_t offset) U8G2_NOINLINE; \nstatic uint16_t u8g2_font_get_word(const uint8_t *font, uint8_t offset)\n{\n    uint16_t pos;\n    font += offset;\n    pos = u8x8_pgm_read( font );\n    font++;\n    pos <<= 8;\n    pos += u8x8_pgm_read( font);\n    return pos;\n}\n\n/*========================================================================*/\n/* new font format */\nvoid u8g2_read_font_info(u8g2_font_info_t *font_info, const uint8_t *font)\n{\n  /* offset 0 */\n  font_info->glyph_cnt = u8g2_font_get_byte(font, 0);\n  font_info->bbx_mode = u8g2_font_get_byte(font, 1);\n  font_info->bits_per_0 = u8g2_font_get_byte(font, 2);\n  font_info->bits_per_1 = u8g2_font_get_byte(font, 3);\n  \n  /* offset 4 */\n  font_info->bits_per_char_width = u8g2_font_get_byte(font, 4);\n  font_info->bits_per_char_height = u8g2_font_get_byte(font, 5);\n  font_info->bits_per_char_x = u8g2_font_get_byte(font, 6);\n  font_info->bits_per_char_y = u8g2_font_get_byte(font, 7);\n  font_info->bits_per_delta_x = u8g2_font_get_byte(font, 8);\n  \n  /* offset 9 */\n  font_info->max_char_width = u8g2_font_get_byte(font, 9);\n  font_info->max_char_height = u8g2_font_get_byte(font, 10);\n  font_info->x_offset = u8g2_font_get_byte(font, 11);\n  font_info->y_offset = u8g2_font_get_byte(font, 12);\n  \n  /* offset 13 */\n  font_info->ascent_A = u8g2_font_get_byte(font, 13);\n  font_info->descent_g = u8g2_font_get_byte(font, 14);\n  font_info->ascent_para = u8g2_font_get_byte(font, 15);\n  font_info->descent_para = u8g2_font_get_byte(font, 16);\n  \n  /* offset 17 */\n  font_info->start_pos_upper_A = u8g2_font_get_word(font, 17);\n  font_info->start_pos_lower_a = u8g2_font_get_word(font, 19); \n  \n  /* offset 21 */\n#ifdef U8G2_WITH_UNICODE\n  font_info->start_pos_unicode = u8g2_font_get_word(font, 21); \n#endif\n}\n\n\n/* calculate the overall length of the font, only used to create the picture for the google wiki */\nsize_t u8g2_GetFontSize(const uint8_t *font_arg)\n{\n  uint16_t e;\n  const uint8_t *font = font_arg;\n  font += U8G2_FONT_DATA_STRUCT_SIZE;\n  \n  for(;;)\n  {\n    if ( u8x8_pgm_read( font + 1 ) == 0 )\n      break;\n    font += u8x8_pgm_read( font + 1 );\n  }\n  \n  /* continue with unicode section */\n  font += 2;\n\n  /* skip unicode lookup table */\n  font += u8g2_font_get_word(font, 0);\n  \n  for(;;)\n  {\n    e = u8x8_pgm_read( font );\n    e <<= 8;\n    e |= u8x8_pgm_read( font + 1 );\n    if ( e == 0 )\n      break;\n    font += u8x8_pgm_read( font + 2 );    \n  }\n  \n  return (font - font_arg) + 2;\n}\n\n/*========================================================================*/\n/* u8g2 interface, font access */\n\nuint8_t u8g2_GetFontBBXWidth(u8g2_t *u8g2)\n{\n  return u8g2->font_info.max_char_width;\t\t/* new font info structure */\n}\n\nuint8_t u8g2_GetFontBBXHeight(u8g2_t *u8g2)\n{\n  return u8g2->font_info.max_char_height;\t\t/* new font info structure */\n}\n\nint8_t u8g2_GetFontBBXOffX(u8g2_t *u8g2) U8G2_NOINLINE;\nint8_t u8g2_GetFontBBXOffX(u8g2_t *u8g2)\n{\n  return u8g2->font_info.x_offset;\t\t/* new font info structure */\n}\n\nint8_t u8g2_GetFontBBXOffY(u8g2_t *u8g2) U8G2_NOINLINE;\nint8_t u8g2_GetFontBBXOffY(u8g2_t *u8g2)\n{\n  return u8g2->font_info.y_offset;\t\t/* new font info structure */\n}\n\nuint8_t u8g2_GetFontCapitalAHeight(u8g2_t *u8g2) U8G2_NOINLINE; \nuint8_t u8g2_GetFontCapitalAHeight(u8g2_t *u8g2)\n{\n  return u8g2->font_info.ascent_A;\t\t/* new font info structure */\n}\n\n/*========================================================================*/\n/* glyph handling */\n\n/* optimized */\nuint8_t u8g2_font_decode_get_unsigned_bits(u8g2_font_decode_t *f, uint8_t cnt) \n{\n  uint8_t val;\n  uint8_t bit_pos = f->decode_bit_pos;\n  uint8_t bit_pos_plus_cnt;\n  \n  //val = *(f->decode_ptr);\n  val = u8x8_pgm_read( f->decode_ptr );  \n  \n  val >>= bit_pos;\n  bit_pos_plus_cnt = bit_pos;\n  bit_pos_plus_cnt += cnt;\n  if ( bit_pos_plus_cnt >= 8 )\n  {\n    uint8_t s = 8;\n    s -= bit_pos;\n    f->decode_ptr++;\n    //val |= *(f->decode_ptr) << (8-bit_pos);\n    val |= u8x8_pgm_read( f->decode_ptr ) << (s);\n    //bit_pos -= 8;\n    bit_pos_plus_cnt -= 8;\n  }\n  val &= (1U<<cnt)-1;\n  //bit_pos += cnt;\n  \n  f->decode_bit_pos = bit_pos_plus_cnt;\n  return val;\n}\n\n\n/*\n    2 bit --> cnt = 2\n      -2,-1,0. 1\n\n    3 bit --> cnt = 3\n      -2,-1,0. 1\n      -4,-3,-2,-1,0,1,2,3\n\n      if ( x < 0 )\n\tr = bits(x-1)+1;\n    else\n\tr = bits(x)+1;\n\n*/\n/* optimized */\nint8_t u8g2_font_decode_get_signed_bits(u8g2_font_decode_t *f, uint8_t cnt)\n{\n  int8_t v, d;\n  v = (int8_t)u8g2_font_decode_get_unsigned_bits(f, cnt);\n  d = 1;\n  cnt--;\n  d <<= cnt;\n  v -= d;\n  return v;\n  //return (int8_t)u8g2_font_decode_get_unsigned_bits(f, cnt) - ((1<<cnt)>>1);\n}\n\n\n#ifdef U8G2_WITH_FONT_ROTATION\nu8g2_uint_t u8g2_add_vector_y(u8g2_uint_t dy, int8_t x, int8_t y, uint8_t dir)\n{\n  switch(dir)\n  {\n    case 0:\n      dy += y;\n      break;\n    case 1:\n      dy += x;\n      break;\n    case 2:\n      dy -= y;\n      break;\n    default:\n      dy -= x;\n      break;      \n  }\n  return dy;\n}\n\nu8g2_uint_t u8g2_add_vector_x(u8g2_uint_t dx, int8_t x, int8_t y, uint8_t dir)\n{\n  switch(dir)\n  {\n    case 0:\n      dx += x;\n      break;\n    case 1:\n      dx -= y;\n      break;\n    case 2:\n      dx -= x;\n      break;\n    default:\n      dx += y;\n      break;      \n  }\n  return dx;\n}\n\n/*\n// does not make sense, 50 bytes more required on avr\nvoid u8g2_add_vector(u8g2_uint_t *xp, u8g2_uint_t *yp, int8_t x, int8_t y, uint8_t dir)\n{\n  u8g2_uint_t x_ = *xp;\n  u8g2_uint_t y_ = *yp;\n  switch(dir)\n  {\n    case 0:\n      y_ += y;\n      x_ += x;\n      break;\n    case 1:\n      y_ += x;\n      x_ -= y;\n      break;\n    case 2:\n      y_ -= y;\n      x_ -= x;\n      break;\n    default:\n      y_ -= x;\n      x_ += y;\n      break;      \n  }\n  *xp = x_;\n  *yp = y_;\n}\n*/\n#endif\n\n\n\n/*\n  Description:\n    Draw a run-length area of the glyph. \"len\" can have any size and the line\n    length has to be wrapped at the glyph border.\n  Args:\n    len: \t\t\t\t\tLength of the line\n    is_foreground\t\t\tforeground/background?\n    u8g2->font_decode.target_x\t\tX position\n    u8g2->font_decode.target_y\t\tY position\n    u8g2->font_decode.is_transparent\tTransparent mode\n  Return:\n    -\n  Calls:\n    u8g2_Draw90Line()\n  Called by:\n    u8g2_font_decode_glyph()\n*/\n/* optimized */\nvoid u8g2_font_decode_len(u8g2_t *u8g2, uint8_t len, uint8_t is_foreground)\n{\n  uint8_t cnt;\t/* total number of remaining pixels, which have to be drawn */\n  uint8_t rem; \t/* remaining pixel to the right edge of the glyph */\n  uint8_t current;\t/* number of pixels, which need to be drawn for the draw procedure */\n    /* current is either equal to cnt or equal to rem */\n  \n  /* local coordinates of the glyph */\n  uint8_t lx,ly;\n  \n  /* target position on the screen */\n  u8g2_uint_t x, y;\n  \n  u8g2_font_decode_t *decode = &(u8g2->font_decode);\n  \n  cnt = len;\n  \n  /* get the local position */\n  lx = decode->x;\n  ly = decode->y;\n  \n  for(;;)\n  {\n    /* calculate the number of pixel to the right edge of the glyph */\n    rem = decode->glyph_width;\n    rem -= lx;\n    \n    /* calculate how many pixel to draw. This is either to the right edge */\n    /* or lesser, if not enough pixel are left */\n    current = rem;\n    if ( cnt < rem )\n      current = cnt;\n    \n    \n    /* now draw the line, but apply the rotation around the glyph target position */\n    //u8g2_font_decode_draw_pixel(u8g2, lx,ly,current, is_foreground);\n\n    /* get target position */\n    x = decode->target_x;\n    y = decode->target_y;\n\n    /* apply rotation */\n#ifdef U8G2_WITH_FONT_ROTATION\n    \n    x = u8g2_add_vector_x(x, lx, ly, decode->dir);\n    y = u8g2_add_vector_y(y, lx, ly, decode->dir);\n    \n    //u8g2_add_vector(&x, &y, lx, ly, decode->dir);\n    \n#else\n    x += lx;\n    y += ly;\n#endif\n    \n    /* draw foreground and background (if required) */\n    if ( is_foreground )\n    {\n      u8g2->draw_color = decode->fg_color;\t\t\t/* draw_color will be restored later */\n      u8g2_DrawHVLine(u8g2, \n\tx, \n\ty, \n\tcurrent, \n#ifdef U8G2_WITH_FONT_ROTATION\n\t/* dir */ decode->dir\n#else\n\t0\n#endif\n      );\n    }\n    else if ( decode->is_transparent == 0 )    \n    {\n      u8g2->draw_color = decode->bg_color;\t\t\t/* draw_color will be restored later */\n      u8g2_DrawHVLine(u8g2, \n\tx, \n\ty, \n\tcurrent, \n#ifdef U8G2_WITH_FONT_ROTATION\n\t/* dir */ decode->dir\n#else\n\t0\n#endif\n      );   \n    }\n    \n    /* check, whether the end of the run length code has been reached */\n    if ( cnt < rem )\n      break;\n    cnt -= rem;\n    lx = 0;\n    ly++;\n  }\n  lx += cnt;\n  \n  decode->x = lx;\n  decode->y = ly;\n  \n}\n\nstatic void u8g2_font_setup_decode(u8g2_t *u8g2, const uint8_t *glyph_data)\n{\n  u8g2_font_decode_t *decode = &(u8g2->font_decode);\n  decode->decode_ptr = glyph_data;\n  decode->decode_bit_pos = 0;\n  \n  /* 8 Nov 2015, this is already done in the glyph data search procedure */\n  /*\n  decode->decode_ptr += 1;\n  decode->decode_ptr += 1;\n  */\n  \n  decode->glyph_width = u8g2_font_decode_get_unsigned_bits(decode, u8g2->font_info.bits_per_char_width);\n  decode->glyph_height = u8g2_font_decode_get_unsigned_bits(decode,u8g2->font_info.bits_per_char_height);\n  \n  decode->fg_color = u8g2->draw_color;\n  decode->bg_color = (decode->fg_color == 0 ? 1 : 0);\n}\n\n\n/*\n  Description:\n    Decode and draw a glyph.\n  Args:\n    glyph_data: \t\t\t\t\tPointer to the compressed glyph data of the font\n    u8g2->font_decode.target_x\t\tX position\n    u8g2->font_decode.target_y\t\tY position\n    u8g2->font_decode.is_transparent\tTransparent mode\n  Return:\n    Width (delta x advance) of the glyph.\n  Calls:\n    u8g2_font_decode_len()\n*/\n/* optimized */\nint8_t u8g2_font_decode_glyph(u8g2_t *u8g2, const uint8_t *glyph_data)\n{\n  uint8_t a, b;\n  int8_t x, y;\n  int8_t d;\n  int8_t h;\n  u8g2_font_decode_t *decode = &(u8g2->font_decode);\n    \n  u8g2_font_setup_decode(u8g2, glyph_data);\n  h = u8g2->font_decode.glyph_height;\n  \n  x = u8g2_font_decode_get_signed_bits(decode, u8g2->font_info.bits_per_char_x);\n  y = u8g2_font_decode_get_signed_bits(decode, u8g2->font_info.bits_per_char_y);\n  d = u8g2_font_decode_get_signed_bits(decode, u8g2->font_info.bits_per_delta_x);\n  \n  if ( decode->glyph_width > 0 )\n  {\n#ifdef U8G2_WITH_FONT_ROTATION\n    decode->target_x = u8g2_add_vector_x(decode->target_x, x, -(h+y), decode->dir);\n    decode->target_y = u8g2_add_vector_y(decode->target_y, x, -(h+y), decode->dir);\n    \n    //u8g2_add_vector(&(decode->target_x), &(decode->target_y), x, -(h+y), decode->dir);\n\n#else\n    decode->target_x += x;\n    decode->target_y -= h+y;\n#endif\n    //u8g2_add_vector(&(decode->target_x), &(decode->target_y), x, -(h+y), decode->dir);\n\n#ifdef U8G2_WITH_INTERSECTION\n    {\n      u8g2_uint_t x0, x1, y0, y1;\n      x0 = decode->target_x;\n      y0 = decode->target_y;\n      x1 = x0;\n      y1 = y0;\n      \n#ifdef U8G2_WITH_FONT_ROTATION\n      switch(decode->dir)\n      {\n\tcase 0:\n\t    x1 += decode->glyph_width;\n\t    y1 += h;\n\t    break;\n\tcase 1:\n\t    x0 -= h;\n\t    x0++;\t/* shift down, because of assymetric boundaries for the interseciton test */\n\t    x1++;\n\t    y1 += decode->glyph_width;\n\t    break;\n\tcase 2:\n\t    x0 -= decode->glyph_width;\n\t    x0++;\t/* shift down, because of assymetric boundaries for the interseciton test */\n\t    x1++;\n\t    y0 -= h;\n\t    y0++;\t/* shift down, because of assymetric boundaries for the interseciton test */\n\t    y1++;\n\t    break;\t  \n\tcase 3:\n\t    x1 += h;\n\t    y0 -= decode->glyph_width;\n\t    y0++;\t/* shift down, because of assymetric boundaries for the interseciton test */\n\t    y1++;\n\t    break;\t  \n      }\n#else /* U8G2_WITH_FONT_ROTATION */\n      x1 += decode->glyph_width;\n      y1 += h;      \n#endif\n      \n      if ( u8g2_IsIntersection(u8g2, x0, y0, x1, y1) == 0 ) \n\treturn d;\n    }\n#endif /* U8G2_WITH_INTERSECTION */\n   \n    /* reset local x/y position */\n    decode->x = 0;\n    decode->y = 0;\n    \n    /* decode glyph */\n    for(;;)\n    {\n      a = u8g2_font_decode_get_unsigned_bits(decode, u8g2->font_info.bits_per_0);\n      b = u8g2_font_decode_get_unsigned_bits(decode, u8g2->font_info.bits_per_1);\n      do\n      {\n\tu8g2_font_decode_len(u8g2, a, 0);\n\tu8g2_font_decode_len(u8g2, b, 1);\n      } while( u8g2_font_decode_get_unsigned_bits(decode, 1) != 0 );\n\n      if ( decode->y >= h )\n\tbreak;\n    }\n    \n    /* restore the u8g2 draw color, because this is modified by the decode algo */\n    u8g2->draw_color = decode->fg_color;\n  }\n  return d;\n}\n\n/*\n  Description:\n    Find the starting point of the glyph data.\n  Args:\n    encoding: Encoding (ASCII or Unicode) of the glyph\n  Return:\n    Address of the glyph data or NULL, if the encoding is not avialable in the font.\n*/\nconst uint8_t *u8g2_font_get_glyph_data(u8g2_t *u8g2, uint16_t encoding)\n{\n  const uint8_t *font = u8g2->font;\n  font += U8G2_FONT_DATA_STRUCT_SIZE;\n\n  \n  if ( encoding <= 255 )\n  {\n    if ( encoding >= 'a' )\n    {\n      font += u8g2->font_info.start_pos_lower_a;\n    }\n    else if ( encoding >= 'A' )\n    {\n      font += u8g2->font_info.start_pos_upper_A;\n    }\n    \n    for(;;)\n    {\n      if ( u8x8_pgm_read( font + 1 ) == 0 )\n\tbreak;\n      if ( u8x8_pgm_read( font ) == encoding )\n      {\n\treturn font+2;\t/* skip encoding and glyph size */\n      }\n      font += u8x8_pgm_read( font + 1 );\n    }\n  }\n#ifdef U8G2_WITH_UNICODE\n  else\n  {\n    uint16_t e;\n    const uint8_t *unicode_lookup_table;\n    \n// removed, there is now the new index table\n//#ifdef  __unix__\n//    if ( u8g2->last_font_data != NULL && encoding >= u8g2->last_unicode )\n//    {\n//\tfont = u8g2->last_font_data;\n//    }\n//    else\n//#endif \n\n    font += u8g2->font_info.start_pos_unicode;\n    unicode_lookup_table = font; \n  \n    /* issue 596: search for the glyph start in the unicode lookup table */\n    do\n    {\n      font += u8g2_font_get_word(unicode_lookup_table, 0);\n      e = u8g2_font_get_word(unicode_lookup_table, 2);\n      unicode_lookup_table+=4;\n    } while( e < encoding );\n    \n  \n    for(;;)\n    {\n      e = u8x8_pgm_read( font );\n      e <<= 8;\n      e |= u8x8_pgm_read( font + 1 );\n  \n// removed, there is now the new index table  \n//#ifdef  __unix__\n//      if ( encoding < e )\n//        break;\n//#endif \n\n      if ( e == 0 )\n\tbreak;\n  \n      if ( e == encoding )\n      {\n// removed, there is now the new index table\n//#ifdef  __unix__\n//\tu8g2->last_font_data = font;\n//\tu8g2->last_unicode = encoding;\n//#endif \n\treturn font+3;\t/* skip encoding and glyph size */\n      }\n      font += u8x8_pgm_read( font + 2 );\n    }  \n  }\n#endif\n  \n  return NULL;\n}\n\nstatic u8g2_uint_t u8g2_font_draw_glyph(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint16_t encoding)\n{\n  u8g2_uint_t dx = 0;\n  u8g2->font_decode.target_x = x;\n  u8g2->font_decode.target_y = y;\n  //u8g2->font_decode.is_transparent = is_transparent; this is already set\n  //u8g2->font_decode.dir = dir;\n  const uint8_t *glyph_data = u8g2_font_get_glyph_data(u8g2, encoding);\n  if ( glyph_data != NULL )\n  {\n    dx = u8g2_font_decode_glyph(u8g2, glyph_data);\n  }\n  return dx;\n}\n\n\n\nuint8_t u8g2_IsGlyph(u8g2_t *u8g2, uint16_t requested_encoding)\n{\n  /* updated to new code */\n  if ( u8g2_font_get_glyph_data(u8g2, requested_encoding) != NULL )\n    return 1;\n  return 0;\n}\n\n/* side effect: updates u8g2->font_decode and u8g2->glyph_x_offset */\nint8_t u8g2_GetGlyphWidth(u8g2_t *u8g2, uint16_t requested_encoding)\n{\n  const uint8_t *glyph_data = u8g2_font_get_glyph_data(u8g2, requested_encoding);\n  if ( glyph_data == NULL )\n    return 0; \n  \n  u8g2_font_setup_decode(u8g2, glyph_data);\n  u8g2->glyph_x_offset = u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_char_x);\n  u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_char_y);\n  \n  /* glyph width is here: u8g2->font_decode.glyph_width */\n\n  return u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_delta_x);\n}\n\n\n/*\n  set one of:\n    U8G2_FONT_MODE_TRANSPARENT\n    U8G2_FONT_MODE_SOLID\n    U8G2_FONT_MODE_NONE\n  This has been changed for the new font procedures  \n*/\nvoid u8g2_SetFontMode(u8g2_t *u8g2, uint8_t is_transparent)\n{\n  u8g2->font_decode.is_transparent = is_transparent;\t\t// new font procedures\n}\n\nu8g2_uint_t u8g2_DrawGlyph(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint16_t encoding)\n{\n#ifdef U8G2_WITH_FONT_ROTATION\n  switch(u8g2->font_decode.dir)\n  {\n    case 0:\n      y += u8g2->font_calc_vref(u8g2);\n      break;\n    case 1:\n      x -= u8g2->font_calc_vref(u8g2);\n      break;\n    case 2:\n      y -= u8g2->font_calc_vref(u8g2);\n      break;\n    case 3:\n      x += u8g2->font_calc_vref(u8g2);\n      break;\n  }\n#else\n  y += u8g2->font_calc_vref(u8g2);\n#endif\n  return u8g2_font_draw_glyph(u8g2, x, y, encoding);\n}\n\nstatic u8g2_uint_t u8g2_draw_string(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str) U8G2_NOINLINE;\nstatic u8g2_uint_t u8g2_draw_string(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str)\n{\n  uint16_t e;\n  u8g2_uint_t delta, sum;\n  u8x8_utf8_init(u8g2_GetU8x8(u8g2));\n  sum = 0;\n  for(;;)\n  {\n    e = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    if ( e == 0x0ffff )\n      break;\n    str++;\n    if ( e != 0x0fffe )\n    {\n      delta = u8g2_DrawGlyph(u8g2, x, y, e);\n    \n#ifdef U8G2_WITH_FONT_ROTATION\n      switch(u8g2->font_decode.dir)\n      {\n\tcase 0:\n\t  x += delta;\n\t  break;\n\tcase 1:\n\t  y += delta;\n\t  break;\n\tcase 2:\n\t  x -= delta;\n\t  break;\n\tcase 3:\n\t  y -= delta;\n\t  break;\n      }\n      \n      /*\n      // requires 10 bytes more on avr\n      x = u8g2_add_vector_x(x, delta, 0, u8g2->font_decode.dir);\n      y = u8g2_add_vector_y(y, delta, 0, u8g2->font_decode.dir);\n      */\n\n#else\n      x += delta;\n#endif\n\n      sum += delta;    \n    }\n  }\n  return sum;\n}\n\nu8g2_uint_t u8g2_DrawStr(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_ascii_next;\n  return u8g2_draw_string(u8g2, x, y, str);\n}\n\n/*\nsource: https://en.wikipedia.org/wiki/UTF-8\nBits\tfrom \t\tto\t\t\tbytes\tByte 1 \t\tByte 2 \t\tByte 3 \t\tByte 4 \t\tByte 5 \t\tByte 6\n  7 \tU+0000 \t\tU+007F \t\t1 \t\t0xxxxxxx\n11 \tU+0080 \t\tU+07FF \t\t2 \t\t110xxxxx \t10xxxxxx\n16 \tU+0800 \t\tU+FFFF \t\t3 \t\t1110xxxx \t10xxxxxx \t10xxxxxx\n21 \tU+10000 \tU+1FFFFF \t4 \t\t11110xxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n26 \tU+200000 \tU+3FFFFFF \t5 \t\t111110xx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n31 \tU+4000000 \tU+7FFFFFFF \t6 \t\t1111110x \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx  \n*/\nu8g2_uint_t u8g2_DrawUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_utf8_next;\n  return u8g2_draw_string(u8g2, x, y, str);\n}\n\n\n\nu8g2_uint_t u8g2_DrawExtendedUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint8_t to_left, u8g2_kerning_t *kerning, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_utf8_next;\n  uint16_t e_prev = 0x0ffff;\n  uint16_t e;\n  u8g2_uint_t delta, sum, k;\n  u8x8_utf8_init(u8g2_GetU8x8(u8g2));\n  sum = 0;\n  for(;;)\n  {\n    e = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    if ( e == 0x0ffff )\n      break;\n    str++;\n    if ( e != 0x0fffe )\n    {\n      delta = u8g2_GetGlyphWidth(u8g2, e);\n\t    \n      if ( to_left )\n      {\n        k = u8g2_GetKerning(u8g2, kerning, e, e_prev);\n\tdelta -= k;\n\tx -= delta;\n      }\n      else\n      {\n        k = u8g2_GetKerning(u8g2, kerning, e_prev, e);\n\tdelta -= k;\n      }\n      e_prev = e;\n\n      u8g2_DrawGlyph(u8g2, x, y, e);\n      if ( to_left )\n      {\n      }\n      else\n      {\n\tx += delta;\n\tx -= k;\n      }\n      \n      sum += delta;    \n    }\n  }\n  return sum;\n}\n\nu8g2_uint_t u8g2_DrawExtUTF8(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, uint8_t to_left, const uint16_t *kerning_table, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_utf8_next;\n  uint16_t e_prev = 0x0ffff;\n  uint16_t e;\n  u8g2_uint_t delta, sum, k;\n  u8x8_utf8_init(u8g2_GetU8x8(u8g2));\n  sum = 0;\n  for(;;)\n  {\n    e = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    if ( e == 0x0ffff )\n      break;\n    str++;\n    if ( e != 0x0fffe )\n    {\n      delta = u8g2_GetGlyphWidth(u8g2, e);\n\t    \n      if ( to_left )\n      {\n        k = u8g2_GetKerningByTable(u8g2, kerning_table, e, e_prev);\n\tdelta -= k;\n\tx -= delta;\n      }\n      else\n      {\n        k = u8g2_GetKerningByTable(u8g2, kerning_table, e_prev, e);\n\tdelta -= k;\n      }\n      e_prev = e;\n\n      if ( to_left )\n      {\n      }\n      else\n      {\n\tx += delta;\n      }\n      u8g2_DrawGlyph(u8g2, x, y, e);\n      if ( to_left )\n      {\n      }\n      else\n      {\n\t//x += delta;\n\t//x -= k;\n      }\n      \n      sum += delta;    \n    }\n  }\n  return sum;\n}\n\n\n\n/*===============================================*/\n\n/* set ascent/descent for reference point calculation */\n\nvoid u8g2_UpdateRefHeight(u8g2_t *u8g2)\n{\n  if ( u8g2->font == NULL )\n    return;\n  u8g2->font_ref_ascent = u8g2->font_info.ascent_A;\n  u8g2->font_ref_descent = u8g2->font_info.descent_g;\n  if ( u8g2->font_height_mode == U8G2_FONT_HEIGHT_MODE_TEXT )\n  {\n  }\n  else if ( u8g2->font_height_mode == U8G2_FONT_HEIGHT_MODE_XTEXT )\n  {\n    if ( u8g2->font_ref_ascent < u8g2->font_info.ascent_para )\n      u8g2->font_ref_ascent = u8g2->font_info.ascent_para;\n    if ( u8g2->font_ref_descent > u8g2->font_info.descent_para )\n      u8g2->font_ref_descent = u8g2->font_info.descent_para;\n  }\n  else\n  {\n    if ( u8g2->font_ref_ascent < u8g2->font_info.max_char_height+u8g2->font_info.y_offset )\n      u8g2->font_ref_ascent = u8g2->font_info.max_char_height+u8g2->font_info.y_offset;\n    if ( u8g2->font_ref_descent > u8g2->font_info.y_offset )\n      u8g2->font_ref_descent = u8g2->font_info.y_offset;\n  }  \n}\n\nvoid u8g2_SetFontRefHeightText(u8g2_t *u8g2)\n{\n  u8g2->font_height_mode = U8G2_FONT_HEIGHT_MODE_TEXT;\n  u8g2_UpdateRefHeight(u8g2);\n}\n\nvoid u8g2_SetFontRefHeightExtendedText(u8g2_t *u8g2)\n{\n  u8g2->font_height_mode = U8G2_FONT_HEIGHT_MODE_XTEXT;\n  u8g2_UpdateRefHeight(u8g2);\n}\n\nvoid u8g2_SetFontRefHeightAll(u8g2_t *u8g2)\n{\n  u8g2->font_height_mode = U8G2_FONT_HEIGHT_MODE_ALL;\n  u8g2_UpdateRefHeight(u8g2);\n}\n\n/*===============================================*/\n/* callback procedures to correct the y position */\n\nu8g2_uint_t u8g2_font_calc_vref_font(U8X8_UNUSED u8g2_t *u8g2)\n{\n  return 0;\n}\n\nvoid u8g2_SetFontPosBaseline(u8g2_t *u8g2)\n{\n  u8g2->font_calc_vref = u8g2_font_calc_vref_font;\n}\n\n\nu8g2_uint_t u8g2_font_calc_vref_bottom(u8g2_t *u8g2)\n{\n  return (u8g2_uint_t)(u8g2->font_ref_descent);\n}\n\nvoid u8g2_SetFontPosBottom(u8g2_t *u8g2)\n{\n  u8g2->font_calc_vref = u8g2_font_calc_vref_bottom;\n}\n\nu8g2_uint_t u8g2_font_calc_vref_top(u8g2_t *u8g2)\n{\n  u8g2_uint_t tmp;\n  /* reference pos is one pixel above the upper edge of the reference glyph */\n  tmp = (u8g2_uint_t)(u8g2->font_ref_ascent);\n  tmp++;\n  return tmp;\n}\n\nvoid u8g2_SetFontPosTop(u8g2_t *u8g2)\n{\n  u8g2->font_calc_vref = u8g2_font_calc_vref_top;\n}\n\nu8g2_uint_t u8g2_font_calc_vref_center(u8g2_t *u8g2)\n{\n  int8_t tmp;\n  tmp = u8g2->font_ref_ascent;\n  tmp -= u8g2->font_ref_descent;\n  tmp /= 2;\n  tmp += u8g2->font_ref_descent;  \n  return tmp;\n}\n\nvoid u8g2_SetFontPosCenter(u8g2_t *u8g2)\n{\n  u8g2->font_calc_vref = u8g2_font_calc_vref_center;\n}\n\n/*===============================================*/\n\nvoid u8g2_SetFont(u8g2_t *u8g2, const uint8_t  *font)\n{\n  if ( u8g2->font != font )\n  {\n//#ifdef  __unix__\n//\tu8g2->last_font_data = NULL;\n//\tu8g2->last_unicode = 0x0ffff;\n//#endif \n    u8g2->font = font;\n    u8g2_read_font_info(&(u8g2->font_info), font);\n    u8g2_UpdateRefHeight(u8g2);\n    /* u8g2_SetFontPosBaseline(u8g2); */ /* removed with issue 195 */\n  }\n}\n\n/*===============================================*/\n\nstatic uint8_t u8g2_is_all_valid(u8g2_t *u8g2, const char *str) U8G2_NOINLINE;\nstatic uint8_t u8g2_is_all_valid(u8g2_t *u8g2, const char *str)\n{\n  uint16_t e;\n  u8x8_utf8_init(u8g2_GetU8x8(u8g2));\n  for(;;)\n  {\n    e = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    if ( e == 0x0ffff )\n      break;\n    str++;\n    if ( e != 0x0fffe )\n    {\n      if ( u8g2_font_get_glyph_data(u8g2, e) == NULL )\n\treturn 0;\n    }\n  }\n  return 1;\n}\n\nuint8_t u8g2_IsAllValidUTF8(u8g2_t *u8g2, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_utf8_next;\n  return u8g2_is_all_valid(u8g2, str);\n}\n\n\n/* string calculation is stilll not 100% perfect as it addes the initial string offset to the overall size */\nstatic u8g2_uint_t u8g2_string_width(u8g2_t *u8g2, const char *str) U8G2_NOINLINE;\nstatic u8g2_uint_t u8g2_string_width(u8g2_t *u8g2, const char *str)\n{\n  uint16_t e;\n  u8g2_uint_t  w, dx;\n  \n  u8g2->font_decode.glyph_width = 0;\n  u8x8_utf8_init(u8g2_GetU8x8(u8g2));\n  \n  /* reset the total width to zero, this will be expanded during calculation */\n  w = 0;\n  dx = 0;\n\n  // printf(\"str=<%s>\\n\", str);\n\t\n  for(;;)\n  {\n    e = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    if ( e == 0x0ffff )\n      break;\n    str++;\n    if ( e != 0x0fffe )\n    {\n      dx = u8g2_GetGlyphWidth(u8g2, e);\t\t/* delta x value of the glyph */\n      w += dx;\n    }\n  }\n  \n  /* adjust the last glyph, check for issue #16: do not adjust if width is 0 */\n  if ( u8g2->font_decode.glyph_width != 0 )\n  {\n    w -= dx;\n    w += u8g2->font_decode.glyph_width;  /* the real pixel width of the glyph, sideeffect of GetGlyphWidth */\n    /* issue #46: we have to add the x offset also */\n    w += u8g2->glyph_x_offset;\t/* this value is set as a side effect of u8g2_GetGlyphWidth() */\n  }\n  // printf(\"w=%d \\n\", w);\n  \n  return w;  \n}\n\nstatic void u8g2_GetGlyphHorizontalProperties(u8g2_t *u8g2, uint16_t requested_encoding, uint8_t *w, int8_t *ox, int8_t *dx)\n{\n  const uint8_t *glyph_data = u8g2_font_get_glyph_data(u8g2, requested_encoding);\n  if ( glyph_data == NULL )\n    return; \n  \n  u8g2_font_setup_decode(u8g2, glyph_data);\n  *w = u8g2->font_decode.glyph_width;\n  *ox =  u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_char_x);\n  u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_char_y);\n  *dx = u8g2_font_decode_get_signed_bits(&(u8g2->font_decode), u8g2->font_info.bits_per_delta_x);\n}\n\n/* u8g compatible GetStrX function */\nint8_t u8g2_GetStrX(u8g2_t *u8g2, const char *s)\n{\n  uint8_t w;\n  int8_t ox, dx;\n  u8g2_GetGlyphHorizontalProperties(u8g2, *s, &w, &ox, &dx);\n  return ox;\n}\n\n\n\nstatic u8g2_uint_t u8g2_calculate_exact_string_width(u8g2_t *u8g2, const char *str)\n{\n\n  u8g2_uint_t  w;\n  uint16_t enc;\n  uint8_t gw; \n  int8_t ox, dx;\n  \n  /* reset the total minimal width to zero, this will be expanded during calculation */\n  w = 0;\n    \n  \n  /* check for empty string, width is already 0 */\n  do\n  {\n    enc = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n    str++;\n  } while( enc == 0x0fffe );\n  \n  if ( enc== 0x0ffff )\n     return w;\n  \n  /* get the glyph information of the first char. This must be valid, because we already checked for the empty string */\n  /* if *s is not inside the font, then the cached parameters of the glyph are all zero */\n  u8g2_GetGlyphHorizontalProperties(u8g2, enc, &gw, &ox, &dx);  \n\n  /* strlen(s) == 1:       width = width(s[0]) */\n  /* strlen(s) == 2:       width = - offx(s[0]) + deltax(s[0]) + offx(s[1]) + width(s[1]) */\n  /* strlen(s) == 3:       width = - offx(s[0]) + deltax(s[0]) + deltax(s[1]) + offx(s[2]) + width(s[2]) */\n  \n  /* assume that the string has size 2 or more, than start with negative offset-x */\n  /* for string with size 1, this will be nullified after the loop */\n  w = -ox;  \n  for(;;)\n  {\n    \n    /* check and stop if the end of the string is reached */\n    do\n    {\n      enc = u8g2->u8x8.next_cb(u8g2_GetU8x8(u8g2), (uint8_t)*str);\n      str++;\n    } while( enc == 0x0fffe );\n    if ( enc== 0x0ffff )\n      break;\n\n    u8g2_GetGlyphHorizontalProperties(u8g2, enc, &gw, &ox, &dx);  \n    \n    /* if there are still more characters, add the delta to the next glyph */\n    w += dx;    \n  }\n  \n  /* finally calculate the width of the last char */\n  /* here is another exception, if the last char is a black, use the dx value instead */\n  if ( enc != ' ' )\n  {\n    /* if g was not updated in the for loop (strlen() == 1), then the initial offset x gets removed */\n    w += gw;\n    w += ox;\n  }\n  else\n  {\n    w += dx;\n  }\n  \n  \n  return w;\n\t\n}\n\n\n\n\n\nu8g2_uint_t u8g2_GetStrWidth(u8g2_t *u8g2, const char *s)\n{\n  u8g2->u8x8.next_cb = u8x8_ascii_next;\n  return u8g2_string_width(u8g2, s);\n}\n\nu8g2_uint_t u8g2_GetExactStrWidth(u8g2_t *u8g2, const char *s)\n{\n  u8g2->u8x8.next_cb = u8x8_ascii_next;\n  return u8g2_calculate_exact_string_width(u8g2, s);\n}\n\n/*\nsource: https://en.wikipedia.org/wiki/UTF-8\nBits\tfrom \t\tto\t\t\tbytes\tByte 1 \t\tByte 2 \t\tByte 3 \t\tByte 4 \t\tByte 5 \t\tByte 6\n  7 \tU+0000 \t\tU+007F \t\t1 \t\t0xxxxxxx\n11 \tU+0080 \t\tU+07FF \t\t2 \t\t110xxxxx \t10xxxxxx\n16 \tU+0800 \t\tU+FFFF \t\t3 \t\t1110xxxx \t10xxxxxx \t10xxxxxx\n21 \tU+10000 \tU+1FFFFF \t4 \t\t11110xxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n26 \tU+200000 \tU+3FFFFFF \t5 \t\t111110xx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n31 \tU+4000000 \tU+7FFFFFFF \t6 \t\t1111110x \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx  \n*/\nu8g2_uint_t u8g2_GetUTF8Width(u8g2_t *u8g2, const char *str)\n{\n  u8g2->u8x8.next_cb = u8x8_utf8_next;\n  return u8g2_string_width(u8g2, str);\n}\n\n\n\nvoid u8g2_SetFontDirection(u8g2_t *u8g2, uint8_t dir)\n{\n#ifdef U8G2_WITH_FONT_ROTATION  \n  u8g2->font_decode.dir = dir;\n#endif\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_hvline.c",
    "content": "/*\n\n  u8g2_hvline.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  Calltree\n  \n    void u8g2_DrawHVLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n    u8g2->cb->draw_l90\n    u8g2_draw_hv_line_2dir\n    u8g2->ll_hvline(u8g2, x, y, len, dir);\n    \n\n*/\n\n#include \"u8g2.h\"\n#include <assert.h>\n\n/*==========================================================*/\n/* intersection procedure */\n\n/*\n  Description:\n    clip range from pos a (included) with line len (a+len excluded) agains c (included) to d (excluded)\n  Assumptions:\n    len > 0\n    c <= d\t\t(this is not checked)\n  will return 0 if there is no intersection and if a > b\n\n*/\n\nstatic uint8_t u8g2_clip_intersection2(u8g2_uint_t *ap, u8g2_uint_t *len, u8g2_uint_t c, u8g2_uint_t d)\n{\n  u8g2_uint_t a = *ap;\n  u8g2_uint_t b;\n  b  = a;\n  b += *len;\n\n  /*\n    Description:\n      clip range from a (included) to b (excluded) agains c (included) to d (excluded)\n    Assumptions:\n      a <= b\t\t(violation is checked and handled correctly)\n      c <= d\t\t(this is not checked)\n    will return 0 if there is no intersection and if a > b\n\n    optimized clipping: c is set to 0 --> 27 Oct 2018: again removed the c==0 assumption\n    \n    replaced by uint8_t u8g2_clip_intersection2\n  */\n\n  /* handle the a>b case correctly. If code and time is critical, this could */\n  /* be removed completly (be aware about memory curruption for wrong */\n  /* arguments) or return 0 for a>b (will lead to skipped lines for wrong */\n  /* arguments) */  \n  \n  /* removing the following if clause completly may lead to memory corruption of a>b */\n  if ( a > b )\n  {    \n    /* replacing this if with a simple \"return 0;\" will not handle the case with negative a */    \n    if ( a < d )\n    {\n      b = d;\n      b--;\n    }\n    else\n    {\n      a = c;\n    }\n  }\n  \n  /* from now on, the asumption a <= b is ok */\n  \n  if ( a >= d )\n    return 0;\n  if ( b <= c )\n    return 0;\n  if ( a < c )\t\t\n    a = c;\n  if ( b > d )\n    b = d;\n  \n  *ap = a;\n  b -= a;\n  *len = b;\n  return 1;\n}\n\n\n\n/*==========================================================*/\n/* draw procedures */\n\n/*\n  x,y\t\tUpper left position of the line within the pixel buffer \n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  This function first adjusts the y position to the local buffer. Then it\n  will clip the line and call u8g2_draw_low_level_hv_line()\n\n*/\nvoid u8g2_draw_hv_line_2dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n\n  /* clipping happens before the display rotation */\n\n  /* transform to pixel buffer coordinates */\n  y -= u8g2->pixel_curr_row;\n  \n  u8g2->ll_hvline(u8g2, x, y, len, dir);\n}\n\n\n/*\n  This is the toplevel function for the hv line draw procedures.\n  This function should be called by the user.\n  \n  \"dir\" may have 4 directions: 0 (left to right), 1, 2, 3 (down up)\n*/\nvoid u8g2_DrawHVLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  /* Make a call to the callback function (e.g. u8g2_draw_l90_r0). */\n  /* The callback may rotate the hv line */\n  /* after rotation this will call u8g2_draw_hv_line_4dir() */\n  \n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  if ( u8g2->is_page_clip_window_intersection != 0 )\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n    if ( len != 0 )\n    {\n    \n      /* convert to two directions */    \n      if ( len > 1 )\n      {\n\tif ( dir == 2 )\n\t{\n\t  x -= len;\n\t  x++;\n\t}\n\telse if ( dir == 3 )\n\t{\n\t  y -= len;\n\t  y++;\n\t}\n      }\n      dir &= 1;  \n      \n      /* clip against the user window */\n      if ( dir == 0 )\n      {\n\tif ( y < u8g2->user_y0 )\n\t  return;\n\tif ( y >= u8g2->user_y1 )\n\t  return;\n\tif ( u8g2_clip_intersection2(&x, &len, u8g2->user_x0, u8g2->user_x1) == 0 )\n\t  return;\n      }\n      else\n      {\n\tif ( x < u8g2->user_x0 )\n\t  return;\n\tif ( x >= u8g2->user_x1 )\n\t  return;\n\tif ( u8g2_clip_intersection2(&y, &len, u8g2->user_y0, u8g2->user_y1) == 0 )\n\t  return;\n      }\n      \n      \n      u8g2->cb->draw_l90(u8g2, x, y, len, dir);\n    }\n}\n\nvoid u8g2_DrawHLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len)\n{\n// #ifdef U8G2_WITH_INTERSECTION\n//   if ( u8g2_IsIntersection(u8g2, x, y, x+len, y+1) == 0 ) \n//     return;\n// #endif /* U8G2_WITH_INTERSECTION */\n  u8g2_DrawHVLine(u8g2, x, y, len, 0);\n}\n\nvoid u8g2_DrawVLine(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len)\n{\n// #ifdef U8G2_WITH_INTERSECTION\n//   if ( u8g2_IsIntersection(u8g2, x, y, x+1, y+len) == 0 ) \n//     return;\n// #endif /* U8G2_WITH_INTERSECTION */\n  u8g2_DrawHVLine(u8g2, x, y, len, 1);\n}\n\nvoid u8g2_DrawPixel(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y)\n{\n#ifdef U8G2_WITH_INTERSECTION\n  if ( y < u8g2->user_y0 )\n    return;\n  if ( y >= u8g2->user_y1 )\n    return;\n  if ( x < u8g2->user_x0 )\n    return;\n  if ( x >= u8g2->user_x1 )\n    return;\n#endif /* U8G2_WITH_INTERSECTION */\n  u8g2_DrawHVLine(u8g2, x, y, 1, 0);\n}\n\n/*\n  Assign the draw color for all drawing functions.\n  color may be 0 or 1. The actual color is defined by the display.\n  With color = 1 the drawing function will set the display memory to 1.\n  For OLEDs this ususally means, that the pixel is enabled and the LED \n  at the pixel is turned on.\n  On an LCD it usually means that the LCD segment of the pixel is enabled, \n  which absorbs the light.\n  For eInk/ePaper it means black ink.\n\n  7 Jan 2017: Allow color value 2 for XOR operation.\n  \n*/\nvoid u8g2_SetDrawColor(u8g2_t *u8g2, uint8_t color)\n{\n  u8g2->draw_color = color;\t/* u8g2_SetDrawColor: just assign the argument */ \n  if ( color >= 3 )\n    u8g2->draw_color = 1;\t/* u8g2_SetDrawColor: make color as one if arg is invalid */\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_input_value.c",
    "content": "/*\n\n  u8g2_input_value.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n/*\n  return:\n    0: value is not changed (HOME/Break Button pressed)\n    1: value has been updated\n*/\n\nuint8_t u8g2_UserInterfaceInputValue(u8g2_t *u8g2, const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits, const char *post)\n{\n  uint8_t line_height;\n  uint8_t height;\n  u8g2_uint_t pixel_height;\n  u8g2_uint_t  y, yy;\n  u8g2_uint_t  pixel_width;\n  u8g2_uint_t  x, xx;\n  \n  uint8_t local_value = *value;\n  //uint8_t r; /* not used ??? */\n  uint8_t event;\n\n  /* only horizontal strings are supported, so force this here */\n  u8g2_SetFontDirection(u8g2, 0);\n\n  /* force baseline position */\n  u8g2_SetFontPosBaseline(u8g2);\n  \n  /* calculate line height */\n  line_height = u8g2_GetAscent(u8g2);\n  line_height -= u8g2_GetDescent(u8g2);\n  \n  \n  /* calculate overall height of the input value box */\n  height = 1;\t/* value input line */\n  height += u8x8_GetStringLineCnt(title);\n\n  /* calculate the height in pixel */\n  pixel_height = height;\n  pixel_height *= line_height;\n\n\n  /* calculate offset from top */\n  y = 0;\n  if ( pixel_height < u8g2_GetDisplayHeight(u8g2)  )\n  {\n    y = u8g2_GetDisplayHeight(u8g2);\n    y -= pixel_height;\n    y /= 2;\n  }\n  \n  /* calculate offset from left for the label */\n  x = 0;\n  pixel_width = u8g2_GetUTF8Width(u8g2, pre);\n  pixel_width += u8g2_GetUTF8Width(u8g2, \"0\") * digits;\n  pixel_width += u8g2_GetUTF8Width(u8g2, post);\n  if ( pixel_width < u8g2_GetDisplayWidth(u8g2) )\n  {\n    x = u8g2_GetDisplayWidth(u8g2);\n    x -= pixel_width;\n    x /= 2;\n  }\n  \n  /* event loop */\n  for(;;)\n  {\n    u8g2_FirstPage(u8g2);\n    do\n    {\n      /* render */\n      yy = y;\n      yy += u8g2_DrawUTF8Lines(u8g2, 0, yy, u8g2_GetDisplayWidth(u8g2), line_height, title);\n      xx = x;\n      xx += u8g2_DrawUTF8(u8g2, xx, yy, pre);\n      xx += u8g2_DrawUTF8(u8g2, xx, yy, u8x8_u8toa(local_value, digits));\n      u8g2_DrawUTF8(u8g2, xx, yy, post);\n    } while( u8g2_NextPage(u8g2) );\n    \n#ifdef U8G2_REF_MAN_PIC\n      return 0;\n#endif\n    \n    for(;;)\n    {\n      event = u8x8_GetMenuEvent(u8g2_GetU8x8(u8g2));\n      if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n      {\n\t*value = local_value;\n\treturn 1;\n      }\n      else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n      {\n\treturn 0;\n      }\n      else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_UP )\n      {\n\tif ( local_value >= hi )\n\t  local_value = lo;\n\telse\n\t  local_value++;\n\tbreak;\n      }\n      else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_DOWN )\n      {\n\tif ( local_value <= lo )\n\t  local_value = hi;\n\telse\n\t  local_value--;\n\tbreak;\n      }        \n    }\n  }\n  \n  /* never reached */\n  //return r;  \n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_intersection.c",
    "content": "/*\n\n  u8g2_intersection.c \n  \n  Intersection calculation, code taken from u8g_clip.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n#ifdef __GNUC__\n#define U8G2_ALWAYS_INLINE __inline__ __attribute__((always_inline))\n#else\n#define U8G2_ALWAYS_INLINE\n#endif \n\n\n#if defined(U8G2_WITH_INTERSECTION) || defined(U8G2_WITH_CLIP_WINDOW_SUPPORT)\n\n#ifdef OLD_VERSION_WITH_SYMETRIC_BOUNDARIES\n\n/*\n  intersection assumptions:\n    a1 <= a2 is always true    \n    \n    minimized version\n    ---1----0 1             b1 <= a2 && b1 > b2\n    -----1--0 1             b2 >= a1 && b1 > b2\n    ---1-1--- 1             b1 <= a2 && b2 >= a1\n  */\n\n\n/*\n  calculate the intersection between a0/a1 and v0/v1\n  The intersection check returns one if the range of a0/a1 has an intersection with v0/v1.\n  The intersection check includes the boundary values v1 and a1.\n\n  The following asserts will succeed:\n    assert( u8g2_is_intersection_decision_tree(4, 6, 7, 9) == 0 );\n    assert( u8g2_is_intersection_decision_tree(4, 6, 6, 9) != 0 );\n    assert( u8g2_is_intersection_decision_tree(6, 9, 4, 6) != 0 );\n    assert( u8g2_is_intersection_decision_tree(7, 9, 4, 6) == 0 );  \n*/\n\n//static uint8_t U8G2_ALWAYS_INLINE u8g2_is_intersection_decision_tree(u8g_uint_t a0, u8g_uint_t a1, u8g_uint_t v0, u8g_uint_t v1) \nstatic uint8_t u8g2_is_intersection_decision_tree(u8g2_uint_t a0, u8g2_uint_t a1, u8g2_uint_t v0, u8g2_uint_t v1) \n{\n  if ( v0 <= a1 )\n  {\n    if ( v1 >= a0 )\n    {\n      return 1;\n    }\n    else\n    {\n      if ( v0 > v1 )\n      {\n\treturn 1;\n      }\n      else\n      {\n\treturn 0;\n      }\n    }\n  }\n  else\n  {\n    if ( v1 >= a0 )\n    {\n      if ( v0 > v1 )\n      {\n\treturn 1;\n      }\n      else\n      {\n\treturn 0;\n      }\n    }\n    else\n    {\n      return 0;\n    }\n  }\n}\n\n#endif\t/* OLD_VERSION_WITH_SYMETRIC_BOUNDARIES */\n\n\n/*\n  version with asymetric boundaries.\n  a1 and v1 are excluded\n  v0 == v1 is not support end return 1\n*/\nuint8_t u8g2_is_intersection_decision_tree(u8g2_uint_t a0, u8g2_uint_t a1, u8g2_uint_t v0, u8g2_uint_t v1)\n{\n  if ( v0 < a1 )\t\t// v0 <= a1\n  {\n    if ( v1 > a0 )\t// v1 >= a0\n    {\n      return 1;\n    }\n    else\n    {\n      if ( v0 > v1 )\t// v0 > v1\n      {\n\treturn 1;\n      }\n      else\n      {\n\treturn 0;\n      }\n    }\n  }\n  else\n  {\n    if ( v1 > a0 )\t// v1 >= a0\n    {\n      if ( v0 > v1 )\t// v0 > v1\n      {\n\treturn 1;\n      }\n      else\n      {\n\treturn 0;\n      }\n    }\n    else\n    {\n      return 0;\n    }\n  }\n}\n\n\n\n/* upper limits are not included (asymetric boundaries) */\nuint8_t u8g2_IsIntersection(u8g2_t *u8g2, u8g2_uint_t x0, u8g2_uint_t y0, u8g2_uint_t x1, u8g2_uint_t y1)\n{\n  if ( u8g2_is_intersection_decision_tree(u8g2->user_y0, u8g2->user_y1, y0, y1) == 0 )\n    return 0; \n  \n  return u8g2_is_intersection_decision_tree(u8g2->user_x0, u8g2->user_x1, x0, x1);\n}\n\n\n#endif /* U8G2_WITH_INTERSECTION */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_kerning.c",
    "content": "/*\n\n  u8g2_kerning.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n/* this function is used as \"u8g2_get_kerning_cb\" */\n/*\nuint8_t u8g2_GetNullKerning(u8g2_t *u8g2, uint16_t e1, uint16_t e2)\n{\n  return 0;\n}\n*/\n\n/* this function is used as \"u8g2_get_kerning_cb\" */\nuint8_t u8g2_GetKerning(U8X8_UNUSED u8g2_t *u8g2, u8g2_kerning_t *kerning, uint16_t e1, uint16_t e2)\n{\n  uint16_t i1, i2, cnt, end;\n  if ( kerning == NULL )\n    return 0;\n  \n  /* search for the encoding in the first table */\n  cnt = kerning->first_table_cnt;\n  cnt--;\t/* ignore the last element of the table, which is 0x0ffff */\n  for( i1 = 0; i1 < cnt; i1++ )\n  {\n    if ( kerning->first_encoding_table[i1] == e1 )\n      break;\n  }\n  if ( i1 >= cnt )\n    return 0;\t/* e1 not part of the kerning table, return 0 */\n\n  /* get the upper index for i2 */\n  end = kerning->index_to_second_table[i1+1];\n  for( i2 = kerning->index_to_second_table[i1]; i2 < end; i2++ )\n  {\n    if ( kerning->second_encoding_table[i2] == e2 )\n      break;\n  }\n  \n  if ( i2 >= end )\n    return 0;\t/* e2 not part of any pair with e1, return 0 */\n  \n  return kerning->kerning_values[i2];\n}\n\nuint8_t u8g2_GetKerningByTable(U8X8_UNUSED u8g2_t *u8g2, const uint16_t *kt, uint16_t e1, uint16_t e2)\n{\n  uint16_t i;\n  i = 0;\n  if ( kt == NULL )\n    return 0;\n  for(;;)\n  {\n    if ( kt[i] == 0x0ffff )\n      break;\n    if ( kt[i] == e1 && kt[i+1] == e2 )\n      return kt[i+2];\n    i+=3;\n  }\n  return 0;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_line.c",
    "content": "/*\n\n  u8g2_box.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n\n\nvoid u8g2_DrawLine(u8g2_t *u8g2, u8g2_uint_t x1, u8g2_uint_t y1, u8g2_uint_t x2, u8g2_uint_t y2)\n{\n  u8g2_uint_t tmp;\n  u8g2_uint_t x,y;\n  u8g2_uint_t dx, dy;\n  u8g2_int_t err;\n  u8g2_int_t ystep;\n\n  uint8_t swapxy = 0;\n  \n  /* no intersection check at the moment, should be added... */\n\n  if ( x1 > x2 ) dx = x1-x2; else dx = x2-x1;\n  if ( y1 > y2 ) dy = y1-y2; else dy = y2-y1;\n\n  if ( dy > dx ) \n  {\n    swapxy = 1;\n    tmp = dx; dx =dy; dy = tmp;\n    tmp = x1; x1 =y1; y1 = tmp;\n    tmp = x2; x2 =y2; y2 = tmp;\n  }\n  if ( x1 > x2 ) \n  {\n    tmp = x1; x1 =x2; x2 = tmp;\n    tmp = y1; y1 =y2; y2 = tmp;\n  }\n  err = dx >> 1;\n  if ( y2 > y1 ) ystep = 1; else ystep = -1;\n  y = y1;\n\n#ifndef  U8G2_16BIT\n  if ( x2 == 255 )\n    x2--;\n#else\n  if ( x2 == 0xffff )\n    x2--;\n#endif\n\n  for( x = x1; x <= x2; x++ )\n  {\n    if ( swapxy == 0 ) \n      u8g2_DrawPixel(u8g2, x, y); \n    else \n      u8g2_DrawPixel(u8g2, y, x); \n    err -= (uint8_t)dy;\n    if ( err < 0 ) \n    {\n      y += (u8g2_uint_t)ystep;\n      err += (u8g2_uint_t)dx;\n    }\n  }\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_ll_hvline.c",
    "content": "/*\n\n  u8g2_ll_hvline.c\n  \n  low level hvline\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  *ptr |= or_mask\n  *ptr ^= xor_mask\n  \n  color = 0:   or_mask = 1, xor_mask = 1\n  color = 1:   or_mask = 1, xor_mask = 0\n  color = 2:   or_mask = 0, xor_mask = 1\n\n  if ( color <= 1 )\n    or_mask  = mask;\n  if ( color != 1 )\n    xor_mask = mask;\n    \n*/\n\n#include \"u8g2.h\"\n#include <assert.h>\n\n/*=================================================*/\n/*\n  u8g2_ll_hvline_vertical_top_lsb\n    SSD13xx\n    UC1701    \n*/\n\n\n#ifdef U8G2_WITH_HVLINE_SPEED_OPTIMIZATION\n\n/*\n  x,y\t\tUpper left position of the line within the local buffer (not the display!)\n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  asumption: \n    all clipping done\n*/\nvoid u8g2_ll_hvline_vertical_top_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  uint16_t offset;\n  uint8_t *ptr;\n  uint8_t bit_pos, mask;\n  uint8_t or_mask, xor_mask;\n#ifdef __unix\n  uint8_t *max_ptr = u8g2->tile_buf_ptr + u8g2_GetU8x8(u8g2)->display_info->tile_width*u8g2->tile_buf_height*8;\n#endif\n\n  //assert(x >= u8g2->buf_x0);\n  //assert(x < u8g2_GetU8x8(u8g2)->display_info->tile_width*8);\n  //assert(y >= u8g2->buf_y0);\n  //assert(y < u8g2_GetU8x8(u8g2)->display_info->tile_height*8);\n  \n  /* bytes are vertical, lsb on top (y=0), msb at bottom (y=7) */\n  bit_pos = y;\t\t/* overflow truncate is ok here... */\n  bit_pos &= 7; \t/* ... because only the lowest 3 bits are needed */\n  mask = 1;\n  mask <<= bit_pos;\n\n  or_mask = 0;\n  xor_mask = 0;\n  if ( u8g2->draw_color <= 1 )\n    or_mask  = mask;\n  if ( u8g2->draw_color != 1 )\n    xor_mask = mask;\n\n\n  offset = y;\t\t/* y might be 8 or 16 bit, but we need 16 bit, so use a 16 bit variable */\n  offset &= ~7;\n  offset *= u8g2_GetU8x8(u8g2)->display_info->tile_width;\n  ptr = u8g2->tile_buf_ptr;\n  ptr += offset;\n  ptr += x;\n  \n  if ( dir == 0 )\n  {\n      do\n      {\n#ifdef __unix\n\tassert(ptr < max_ptr);\n#endif\n\t*ptr |= or_mask;\n\t*ptr ^= xor_mask;\n\tptr++;\n\tlen--;\n      } while( len != 0 );\n  }\n  else\n  {    \n    do\n    {\n#ifdef __unix\n      assert(ptr < max_ptr);\n#endif\n      *ptr |= or_mask;\n      *ptr ^= xor_mask;\n      \n      bit_pos++;\n      bit_pos &= 7;\n\n      len--;\n\n      if ( bit_pos == 0 )\n      {\n\tptr+=u8g2->pixel_buf_width;\t/* 6 Jan 17: Changed u8g2->width to u8g2->pixel_buf_width, issue #148 */\n\t\t\n\tif ( u8g2->draw_color <= 1 )\n\t  or_mask  = 1;\n\tif ( u8g2->draw_color != 1 )\n\t  xor_mask = 1;\n      }\n      else\n      {\n\tor_mask <<= 1;\n\txor_mask <<= 1;\n      }\n    } while( len != 0 );\n  }\n}\n\n\n\n#else /* U8G2_WITH_HVLINE_SPEED_OPTIMIZATION */\n\n/*\n  x,y position within the buffer\n*/\nstatic void u8g2_draw_pixel_vertical_top_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y)\n{\n  uint16_t offset;\n  uint8_t *ptr;\n  uint8_t bit_pos, mask;\n  \n  //assert(x >= u8g2->buf_x0);\n  //assert(x < u8g2_GetU8x8(u8g2)->display_info->tile_width*8);\n  //assert(y >= u8g2->buf_y0);\n  //assert(y < u8g2_GetU8x8(u8g2)->display_info->tile_height*8);\n  \n  /* bytes are vertical, lsb on top (y=0), msb at bottom (y=7) */\n  bit_pos = y;\t\t/* overflow truncate is ok here... */\n  bit_pos &= 7; \t/* ... because only the lowest 3 bits are needed */\n  mask = 1;\n  mask <<= bit_pos;\n\n  offset = y;\t\t/* y might be 8 or 16 bit, but we need 16 bit, so use a 16 bit variable */\n  offset &= ~7;\n  offset *= u8g2_GetU8x8(u8g2)->display_info->tile_width;\n  ptr = u8g2->tile_buf_ptr;\n  ptr += offset;\n  ptr += x;\n\n\n  if ( u8g2->draw_color <= 1 )\n    *ptr |= mask;\n  if ( u8g2->draw_color != 1 )\n    *ptr ^= mask;\n\n}\n\n/*\n  x,y\t\tUpper left position of the line within the local buffer (not the display!)\n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  asumption: \n    all clipping done\n*/\nvoid u8g2_ll_hvline_vertical_top_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  if ( dir == 0 )\n  {\n    do\n    {\n      u8g2_draw_pixel_vertical_top_lsb(u8g2, x, y);\n      x++;\n      len--;\n    } while( len != 0 );\n  }\n  else\n  {\n    do\n    {\n      u8g2_draw_pixel_vertical_top_lsb(u8g2, x, y);\n      y++;\n      len--;\n    } while( len != 0 );\n  }\n}\n\n\n#endif /* U8G2_WITH_HVLINE_SPEED_OPTIMIZATION */\n\n/*=================================================*/\n/*\n  u8g2_ll_hvline_horizontal_right_lsb\n    ST7920\n*/\n\n#ifdef U8G2_WITH_HVLINE_SPEED_OPTIMIZATION\n\n/*\n  x,y\t\tUpper left position of the line within the local buffer (not the display!)\n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  asumption: \n    all clipping done\n*/\n\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nvoid u8g2_ll_hvline_horizontal_right_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  uint16_t offset;\n  uint8_t *ptr;\n  uint8_t bit_pos;\n  uint8_t mask;\n  uint8_t tile_width = u8g2_GetU8x8(u8g2)->display_info->tile_width;\n\n  bit_pos = x;\t\t/* overflow truncate is ok here... */\n  bit_pos &= 7; \t/* ... because only the lowest 3 bits are needed */\n  mask = 128;\n  mask >>= bit_pos;\n\n  offset = y;\t\t/* y might be 8 or 16 bit, but we need 16 bit, so use a 16 bit variable */\n  offset *= tile_width;\n  offset += x>>3;\n  ptr = u8g2->tile_buf_ptr;\n  ptr += offset;\n  \n  if ( dir == 0 )\n  {\n      \n    do\n    {\n\n      if ( u8g2->draw_color <= 1 )\n\t*ptr |= mask;\n      if ( u8g2->draw_color != 1 )\n\t*ptr ^= mask;\n      \n      mask >>= 1;\n      if ( mask == 0 )\n      {\n\tmask = 128;\n        ptr++;\n      }\n      \n      //x++;\n      len--;\n    } while( len != 0 );\n  }\n  else\n  {\n    do\n    {\n      if ( u8g2->draw_color <= 1 )\n\t*ptr |= mask;\n      if ( u8g2->draw_color != 1 )\n\t*ptr ^= mask;\n      \n      ptr += tile_width;\n      //y++;\n      len--;\n    } while( len != 0 );\n  }\n}\n\n#else /* U8G2_WITH_HVLINE_SPEED_OPTIMIZATION */\n\n\n/*\n  x,y position within the buffer\n*/\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nstatic void u8g2_draw_pixel_horizontal_right_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y)\n{\n  uint16_t offset;\n  uint8_t *ptr;\n  uint8_t bit_pos, mask;\n\n  //assert(x >= u8g2->buf_x0);\n  //assert(x < u8g2_GetU8x8(u8g2)->display_info->tile_width*8);\n  //assert(y >= u8g2->buf_y0);\n  //assert(y < u8g2_GetU8x8(u8g2)->display_info->tile_height*8);\n  \n  /* bytes are vertical, lsb on top (y=0), msb at bottom (y=7) */\n  bit_pos = x;\t\t/* overflow truncate is ok here... */\n  bit_pos &= 7; \t/* ... because only the lowest 3 bits are needed */\n  mask = 128;\n  mask >>= bit_pos;\n  x >>= 3;\n\n  offset = y;\t\t/* y might be 8 or 16 bit, but we need 16 bit, so use a 16 bit variable */\n  offset *= u8g2_GetU8x8(u8g2)->display_info->tile_width;\n  offset += x;\n  ptr = u8g2->tile_buf_ptr;\n  ptr += offset;\n  \n\n  if ( u8g2->draw_color <= 1 )\n    *ptr |= mask;\n  if ( u8g2->draw_color != 1 )\n    *ptr ^= mask;\n  \n}\n\n/*\n  x,y\t\tUpper left position of the line within the local buffer (not the display!)\n  len\t\tlength of the line in pixel, len must not be 0\n  dir\t\t0: horizontal line (left to right)\n\t\t1: vertical line (top to bottom)\n  asumption: \n    all clipping done\n*/\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nvoid u8g2_ll_hvline_horizontal_right_lsb(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  if ( dir == 0 )\n  {\n    do\n    {\n      u8g2_draw_pixel_horizontal_right_lsb(u8g2, x, y);\n      x++;\n      len--;\n    } while( len != 0 );\n  }\n  else\n  {\n    do\n    {\n      u8g2_draw_pixel_horizontal_right_lsb(u8g2, x, y);\n      y++;\n      len--;\n    } while( len != 0 );\n  }\n}\n\n#endif /* U8G2_WITH_HVLINE_SPEED_OPTIMIZATION */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_message.c",
    "content": "/*\n\n  u8g2_message.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n#define SPACE_BETWEEN_BUTTONS_IN_PIXEL 6\n#define SPACE_BETWEEN_TEXT_AND_BUTTONS_IN_PIXEL 3\n\nuint8_t u8g2_draw_button_line(u8g2_t *u8g2, u8g2_uint_t y, u8g2_uint_t w, uint8_t cursor, const char *s)\n{\n  u8g2_uint_t button_line_width;\n\t\n  uint8_t i;\n  uint8_t cnt;\n  uint8_t is_invert;\n\t\n  u8g2_uint_t d;\n  u8g2_uint_t x;\n\t\n  cnt = u8x8_GetStringLineCnt(s);\n  \n\t\n  /* calculate the width of the button line */\n  button_line_width = 0;\n  for( i = 0; i < cnt; i++ )\n  {\n    button_line_width += u8g2_GetUTF8Width(u8g2, u8x8_GetStringLineStart(i, s));\n  }\n  button_line_width += (cnt-1)*SPACE_BETWEEN_BUTTONS_IN_PIXEL;\t/* add some space between the buttons */\n  \n  /* calculate the left offset */\n  d = 0;\n  if ( button_line_width < w )\n  {\n    d = w;\n    d -= button_line_width;\n    d /= 2;\n  }\n  \n  /* draw the buttons */\n  x = d;\n  for( i = 0; i < cnt; i++ )\n  {\n    is_invert = 0;\n    if ( i == cursor )\n      is_invert = 1;\n\n    u8g2_DrawUTF8Line(u8g2, x, y, 0, u8x8_GetStringLineStart(i, s), 1, is_invert);\n    x += u8g2_GetUTF8Width(u8g2, u8x8_GetStringLineStart(i, s));\n    x += SPACE_BETWEEN_BUTTONS_IN_PIXEL;\n  }\n  \n  /* return the number of buttons */\n  return cnt;\n}\n\n/*\n  title1:\tMultiple lines,separated by '\\n'\n  title2:\tA single line/string which is terminated by '\\0' or '\\n' . \"title2\" accepts the return value from u8x8_GetStringLineStart()\n  title3:\tMultiple lines,separated by '\\n'\n  buttons:\tone more more buttons separated by '\\n' and terminated with '\\0'\n  side effects:\n    u8g2_SetFontDirection(u8g2, 0);\n    u8g2_SetFontPosBaseline(u8g2);\n*/\n\nuint8_t u8g2_UserInterfaceMessage(u8g2_t *u8g2, const char *title1, const char *title2, const char *title3, const char *buttons)\n{\n  uint8_t height;\n  uint8_t line_height;\n  u8g2_uint_t pixel_height;\n  u8g2_uint_t y, yy;\n\t\n  uint8_t cursor = 0;\n  uint8_t button_cnt;\n  uint8_t event;\n\t\n  /* only horizontal strings are supported, so force this here */\n  u8g2_SetFontDirection(u8g2, 0);\n\n  /* force baseline position */\n  u8g2_SetFontPosBaseline(u8g2);\n\t\n\t\n  /* calculate line height */\n  line_height = u8g2_GetAscent(u8g2);\n  line_height -= u8g2_GetDescent(u8g2);\n\n  /* calculate overall height of the message box in lines*/\n  height = 1;\t/* button line */\n  height += u8x8_GetStringLineCnt(title1);\n  if ( title2 != NULL )\n    height++;\n  height += u8x8_GetStringLineCnt(title3);\n  \n  /* calculate the height in pixel */\n  pixel_height = height;\n  pixel_height *= line_height;\n  \n  /* ... and add the space between the text and the buttons */\n  pixel_height +=SPACE_BETWEEN_TEXT_AND_BUTTONS_IN_PIXEL;\n  \n  /* calculate offset from top */\n  y = 0;\n  if ( pixel_height < u8g2_GetDisplayHeight(u8g2)   )\n  {\n    y = u8g2_GetDisplayHeight(u8g2);\n    y -= pixel_height;\n    y /= 2;\n  }\n  y += u8g2_GetAscent(u8g2);\n\n  \n  for(;;)\n  {\n      u8g2_FirstPage(u8g2);\n      do\n      {\n\t  yy = y;\n\t  /* draw message box */\n\t  \n\t  yy += u8g2_DrawUTF8Lines(u8g2, 0, yy, u8g2_GetDisplayWidth(u8g2), line_height, title1);\n\t  if ( title2 != NULL )\n\t  {\n\t    u8g2_DrawUTF8Line(u8g2, 0, yy, u8g2_GetDisplayWidth(u8g2), title2, 0, 0);\n\t    yy+=line_height;\n\t  }\n\t  yy += u8g2_DrawUTF8Lines(u8g2, 0, yy, u8g2_GetDisplayWidth(u8g2), line_height, title3);\n\t  yy += SPACE_BETWEEN_TEXT_AND_BUTTONS_IN_PIXEL;\n\n\t  button_cnt = u8g2_draw_button_line(u8g2, yy, u8g2_GetDisplayWidth(u8g2), cursor, buttons);\n\t  \n      } while( u8g2_NextPage(u8g2) );\n\n#ifdef U8G2_REF_MAN_PIC\n      return 0;\n#endif\n\t  \n      for(;;)\n      {\n\t    event = u8x8_GetMenuEvent(u8g2_GetU8x8(u8g2));\n\t    if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n\t      return cursor+1;\n\t    else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n\t      return 0;\n\t    else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_DOWN )\n\t    {\n\t      cursor++;\n\t      if ( cursor >= button_cnt )\n\t\tcursor = 0;\n\t      break;\n\t    }\n\t    else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_UP )\n\t    {\n\t      if ( cursor == 0 )\n\t\tcursor = button_cnt;\n\t      cursor--;\n\t      break;\n\t    }    \n      }\n  }\n  /* never reached */\n  //return 0;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_polygon.c",
    "content": "/*\n\n  u8g22_polygon.c\n\n*/\t\n\n\n#include \"u8g2.h\"\n\n\n\n\n/*===========================================*/\n/* local definitions */\n\ntypedef int16_t pg_word_t;\n\n\nstruct pg_point_struct\n{\n  pg_word_t x;\n  pg_word_t y;\n};\n\ntypedef struct _pg_struct pg_struct;\t/* forward declaration */\n\nstruct pg_edge_struct\n{\n  pg_word_t x_direction;\t/* 1, if x2 is greater than x1, -1 otherwise */\n  pg_word_t height;\n  pg_word_t current_x_offset;\n  pg_word_t error_offset;\n  \n  /* --- line loop --- */\n  pg_word_t current_y;\n  pg_word_t max_y;\n  pg_word_t current_x;\n  pg_word_t error;\n\n  /* --- outer loop --- */\n  uint8_t (*next_idx_fn)(pg_struct *pg, uint8_t i);\n  uint8_t curr_idx;\n};\n\n/* maximum number of points in the polygon */\n/* can be redefined, but highest possible value is 254 */\n#define PG_MAX_POINTS 6\n\n/* index numbers for the pge structures below */\n#define PG_LEFT 0\n#define PG_RIGHT 1\n\n\nstruct _pg_struct\n{\n  struct pg_point_struct list[PG_MAX_POINTS];\n  uint8_t cnt;\n  uint8_t is_min_y_not_flat;\n  pg_word_t total_scan_line_cnt;\n  struct pg_edge_struct pge[2];\t/* left and right line draw structures */\n};\n\n\n/*===========================================*/\n/* procedures, which should not be inlined (save as much flash ROM as possible */\n\n#define PG_NOINLINE U8G2_NOINLINE\n\nstatic uint8_t pge_Next(struct pg_edge_struct *pge) PG_NOINLINE;\nstatic uint8_t pg_inc(pg_struct *pg, uint8_t i) PG_NOINLINE;\nstatic uint8_t pg_dec(pg_struct *pg, uint8_t i) PG_NOINLINE;\nstatic void pg_expand_min_y(pg_struct *pg, pg_word_t min_y, uint8_t pge_idx) PG_NOINLINE;\nstatic void pg_line_init(pg_struct * const pg, uint8_t pge_index) PG_NOINLINE;\n\n/*===========================================*/\n/* line draw algorithm */\n\nstatic uint8_t pge_Next(struct pg_edge_struct *pge)\n{\n  if ( pge->current_y >= pge->max_y )\n    return 0;\n  \n  pge->current_x += pge->current_x_offset;\n  pge->error += pge->error_offset;\n  if ( pge->error > 0 )\n  {\n    pge->current_x += pge->x_direction;\n    pge->error -= pge->height;\n  }  \n  \n  pge->current_y++;\n  return 1;\n}\n\n/* assumes y2 > y1 */\nstatic void pge_Init(struct pg_edge_struct *pge, pg_word_t x1, pg_word_t y1, pg_word_t x2, pg_word_t y2)\n{\n  pg_word_t dx = x2 - x1;\n  pg_word_t width;\n\n  pge->height = y2 - y1;\n  pge->max_y = y2;\n  pge->current_y = y1;\n  pge->current_x = x1;\n\n  if ( dx >= 0 )\n  {\n    pge->x_direction = 1;\n    width = dx;\n    pge->error = 0;\n  }\n  else\n  {\n    pge->x_direction = -1;\n    width = -dx;\n    pge->error = 1 - pge->height;\n  }\n  \n  pge->current_x_offset = dx / pge->height;\n  pge->error_offset = width % pge->height;\n}\n\n/*===========================================*/\n/* convex polygon algorithm */\n\nstatic uint8_t pg_inc(pg_struct *pg, uint8_t i)\n{\n    i++;\n    if ( i >= pg->cnt )\n      i = 0;\n    return i;\n}\n\nstatic uint8_t pg_dec(pg_struct *pg, uint8_t i)\n{\n    i--;\n    if ( i >= pg->cnt )\n      i = pg->cnt-1;\n    return i;\n}\n\nstatic void pg_expand_min_y(pg_struct *pg, pg_word_t min_y, uint8_t pge_idx)\n{\n  uint8_t i = pg->pge[pge_idx].curr_idx;\n  for(;;)\n  {\n    i = pg->pge[pge_idx].next_idx_fn(pg, i);\n    if ( pg->list[i].y != min_y )\n      break;\t\n    pg->pge[pge_idx].curr_idx = i;\n  }\n}\n\nstatic uint8_t pg_prepare(pg_struct *pg)\n{\n  pg_word_t max_y;\n  pg_word_t min_y;\n  uint8_t i;\n\n  /* setup the next index procedures */\n  pg->pge[PG_RIGHT].next_idx_fn = pg_inc;\n  pg->pge[PG_LEFT].next_idx_fn = pg_dec;\n  \n  /* search for highest and lowest point */\n  max_y = pg->list[0].y;\n  min_y = pg->list[0].y;\n  pg->pge[PG_LEFT].curr_idx = 0;\n  for( i = 1; i < pg->cnt; i++ )\n  {\n    if ( max_y < pg->list[i].y )\n    {\n      max_y = pg->list[i].y;\n    }\n    if ( min_y > pg->list[i].y )\n    {\n      pg->pge[PG_LEFT].curr_idx = i;\n      min_y = pg->list[i].y;\n    }\n  }\n\n  /* calculate total number of scan lines */\n  pg->total_scan_line_cnt = max_y;\n  pg->total_scan_line_cnt -= min_y;\n  \n  /* exit if polygon height is zero */\n  if ( pg->total_scan_line_cnt == 0 )\n    return 0;\n  \n  /* if the minimum y side is flat, try to find the lowest and highest x points */\n  pg->pge[PG_RIGHT].curr_idx = pg->pge[PG_LEFT].curr_idx;  \n  pg_expand_min_y(pg, min_y, PG_RIGHT);\n  pg_expand_min_y(pg, min_y, PG_LEFT);\n  \n  /* check if the min side is really flat (depends on the x values) */\n  pg->is_min_y_not_flat = 1;\n  if ( pg->list[pg->pge[PG_LEFT].curr_idx].x != pg->list[pg->pge[PG_RIGHT].curr_idx].x )\n  {\n    pg->is_min_y_not_flat = 0;\n  }\n  else\n  {\n    pg->total_scan_line_cnt--;\n    if ( pg->total_scan_line_cnt == 0 )\n      return 0;\n  }\n\n  return 1;\n}\n\nstatic void pg_hline(pg_struct *pg, u8g2_t *u8g2)\n{\n  pg_word_t x1, x2, y;\n  x1 = pg->pge[PG_LEFT].current_x;\n  x2 = pg->pge[PG_RIGHT].current_x;\n  y = pg->pge[PG_RIGHT].current_y;\n  \n  if ( y < 0 )\n    return;\n  if ( y >= u8g2_GetDisplayHeight(u8g2) )  // does not work for 256x64 display???\n    return;\n  if ( x1 < x2 )\n  {\n    if ( x2 < 0 )\n      return;\n    if ( x1 >= u8g2_GetDisplayWidth(u8g2) )\n      return;\n    if ( x1 < 0 )\n      x1 = 0;\n    if ( x2 >= u8g2_GetDisplayWidth(u8g2) )\n      x2 = u8g2_GetDisplayWidth(u8g2);\n    u8g2_DrawHLine(u8g2, x1, y, x2 - x1);\n  }\n  else\n  {\n    if ( x1 < 0 )\n      return;\n    if ( x2 >= u8g2_GetDisplayWidth(u8g2) )\n      return;\n    if ( x2 < 0 )\n      x1 = 0;\n    if ( x1 >= u8g2_GetDisplayWidth(u8g2) )\n      x1 = u8g2_GetDisplayWidth(u8g2);\n    u8g2_DrawHLine(u8g2, x2, y, x1 - x2);\n  }\n}\n\nstatic void pg_line_init(pg_struct * const pg, uint8_t pge_index)\n{\n  struct pg_edge_struct  *pge = pg->pge+pge_index;\n  uint8_t idx;  \n  pg_word_t x1;\n  pg_word_t y1;\n  pg_word_t x2;\n  pg_word_t y2;\n\n  idx = pge->curr_idx;  \n  y1 = pg->list[idx].y;\n  x1 = pg->list[idx].x;\n  idx = pge->next_idx_fn(pg, idx);\n  y2 = pg->list[idx].y;\n  x2 = pg->list[idx].x; \n  pge->curr_idx = idx;\n  \n  pge_Init(pge, x1, y1, x2, y2);\n}\n\nstatic void pg_exec(pg_struct *pg, u8g2_t *u8g2)\n{\n  pg_word_t i = pg->total_scan_line_cnt;\n\n  /* first line is skipped if the min y line is not flat */\n  pg_line_init(pg, PG_LEFT);\t\t\n  pg_line_init(pg, PG_RIGHT);\n  \n  if ( pg->is_min_y_not_flat != 0 )\n  {\n    pge_Next(&(pg->pge[PG_LEFT])); \n    pge_Next(&(pg->pge[PG_RIGHT]));\n  }\n\n  do\n  {\n    pg_hline(pg, u8g2);\n    while ( pge_Next(&(pg->pge[PG_LEFT])) == 0 )\n    {\n      pg_line_init(pg, PG_LEFT);\n    }\n    while ( pge_Next(&(pg->pge[PG_RIGHT])) == 0 )\n    {\n      pg_line_init(pg, PG_RIGHT);\n    }\n    i--;\n  } while( i > 0 );\n}\n\n/*===========================================*/\n/* API procedures */\n\nstatic void pg_ClearPolygonXY(pg_struct *pg)\n{\n  pg->cnt = 0;\n}\n\nstatic void pg_AddPolygonXY(pg_struct *pg, int16_t x, int16_t y)\n{\n  if ( pg->cnt < PG_MAX_POINTS )\n  {\n    pg->list[pg->cnt].x = x;\n    pg->list[pg->cnt].y = y;\n    pg->cnt++;\n  }\n}\n\nstatic void pg_DrawPolygon(pg_struct *pg, u8g2_t *u8g2)\n{\n  if ( pg_prepare(pg) == 0 )\n    return;\n  pg_exec(pg, u8g2);\n}\n\npg_struct u8g2_pg;\n\nvoid u8g2_ClearPolygonXY(void)\n{\n  pg_ClearPolygonXY(&u8g2_pg);\n}\n\nvoid u8g2_AddPolygonXY(U8X8_UNUSED u8g2_t *u8g2, int16_t x, int16_t y)\n{\n  pg_AddPolygonXY(&u8g2_pg, x, y);\n}\n\nvoid u8g2_DrawPolygon(u8g2_t *u8g2)\n{\n  pg_DrawPolygon(&u8g2_pg, u8g2);\n}\n\nvoid u8g2_DrawTriangle(u8g2_t *u8g2, int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2)\n{\n  u8g2_ClearPolygonXY();\n  u8g2_AddPolygonXY(u8g2, x0, y0);\n  u8g2_AddPolygonXY(u8g2, x1, y1);\n  u8g2_AddPolygonXY(u8g2, x2, y2);\n  u8g2_DrawPolygon(u8g2);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_selection_list.c",
    "content": "/*\n\n  u8g2_selection_list.c\n  \n  selection list with scroll option\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n#define MY_BORDER_SIZE 1\n\n\n/*\n  Draw a string at x,y\n  Center string within w (left adjust if w < pixel len of s)\n  \n  Side effects:\n    u8g2_SetFontDirection(u8g2, 0);\n    u8g2_SetFontPosBaseline(u8g2);\n\n*/\nvoid u8g2_DrawUTF8Line(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, const char *s, uint8_t border_size, uint8_t is_invert)\n{\n  u8g2_uint_t d, str_width;\n  u8g2_uint_t fx, fy, fw, fh;\n\n  /* only horizontal strings are supported, so force this here */\n  u8g2_SetFontDirection(u8g2, 0);\n\n  /* revert y position back to baseline ref */\n  y += u8g2->font_calc_vref(u8g2);   \n\n  /* calculate the width of the string in pixel */\n  str_width = u8g2_GetUTF8Width(u8g2, s);\n\n  /* calculate delta d within the box */\n  d = 0;\n  if ( str_width < w )\n  {\n    d = w;\n    d -=str_width;\n    d /= 2;\n  }\n  else\n  {\n    w = str_width;\n  }\n\n  /* caluclate text box */\n  fx = x;\n  fy = y - u8g2_GetAscent(u8g2) ;\n  fw = w;\n  fh = u8g2_GetAscent(u8g2) - u8g2_GetDescent(u8g2) ;\n\n  /* draw the box, if inverted */\n  u8g2_SetDrawColor(u8g2, 1);\n  if ( is_invert )\n  {\n    u8g2_DrawBox(u8g2, fx, fy, fw, fh);\n  }\n\n  /* draw the frame */\n  while( border_size > 0 )\n  {\n    fx--;\n    fy--;\n    fw +=2;\n    fh +=2;\n    u8g2_DrawFrame(u8g2, fx, fy, fw, fh );\n    border_size--;\n  }\n\n  if ( is_invert )\n  {\n    u8g2_SetDrawColor(u8g2, 0);\n  }\n  else\n  {\n    u8g2_SetDrawColor(u8g2, 1);\n  }\n\n  /* draw the text */\n  u8g2_DrawUTF8(u8g2, x+d, y, s);\n\n  /* revert draw color */\n  u8g2_SetDrawColor(u8g2, 1);\n\n}\n\n\n/*\n  draw several lines at position x,y.\n  lines are stored in s and must be separated with '\\n'.\n  lines can be centered with respect to \"w\"\n  if s == NULL nothing is drawn and 0 is returned\n  returns the number of lines in s multiplied with line_height\n*/\nu8g2_uint_t u8g2_DrawUTF8Lines(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t w, u8g2_uint_t line_height, const char *s)\n{\n  uint8_t i;\n  uint8_t cnt;\n  u8g2_uint_t yy = 0;\n  cnt = u8x8_GetStringLineCnt(s);\n  //printf(\"str=%s\\n\", s);\n  //printf(\"cnt=%d, y=%d, line_height=%d\\n\", cnt, y, line_height);\n  for( i = 0; i < cnt; i++ )\n  {\n    //printf(\"  i=%d, y=%d, line_height=%d\\n\", i, y, line_height);\n    u8g2_DrawUTF8Line(u8g2, x, y, w, u8x8_GetStringLineStart(i, s), 0, 0);\n    y+=line_height;\n    yy+=line_height;\n  }\n  return yy;\n}\n\n/*\n  selection list with string line\n  returns line height\n*/\nstatic u8g2_uint_t u8g2_draw_selection_list_line(u8g2_t *u8g2, u8sl_t *u8sl, u8g2_uint_t y, uint8_t idx, const char *s) U8G2_NOINLINE;\nstatic u8g2_uint_t u8g2_draw_selection_list_line(u8g2_t *u8g2, u8sl_t *u8sl, u8g2_uint_t y, uint8_t idx, const char *s)\n{\n  u8g2_uint_t yy;\n  uint8_t border_size = 0;\n  uint8_t is_invert = 0;\n\t\n  u8g2_uint_t line_height = u8g2_GetAscent(u8g2) - u8g2_GetDescent(u8g2)+MY_BORDER_SIZE;\n\n  /* calculate offset from display upper border */\n  yy = idx;\n  yy -= u8sl->first_pos;\n  yy *= line_height;\n  yy += y;\n\n  /* check whether this is the current cursor line */\n  if ( idx == u8sl->current_pos )\n  {\n    border_size = MY_BORDER_SIZE;\n    is_invert = 1;\n  }\n\n  /* get the line from the array */\n  s = u8x8_GetStringLineStart(idx, s);\n\n  /* draw the line */\n  if ( s == NULL )\n    s = \"\";\n  u8g2_DrawUTF8Line(u8g2, MY_BORDER_SIZE, y, u8g2_GetDisplayWidth(u8g2)-2*MY_BORDER_SIZE, s, border_size, is_invert);\n  return line_height;\n}\n\nvoid u8g2_DrawSelectionList(u8g2_t *u8g2, u8sl_t *u8sl, u8g2_uint_t y, const char *s)\n{\n  uint8_t i;\n  for( i = 0; i < u8sl->visible; i++ )\n  {\n    y += u8g2_draw_selection_list_line(u8g2, u8sl, y, i+u8sl->first_pos, s);\n  }\n}\n\n\n/*\n  title: \t\tNULL for no title, valid str for title line. Can contain mutliple lines, separated by '\\n'\n  start_pos: \tdefault position for the cursor, first line is 1.\n  sl:\t\t\tstring list (list of strings separated by \\n)\n  returns 0 if user has pressed the home key\n  returns the selected line if user has pressed the select key\n  side effects:\n    u8g2_SetFontDirection(u8g2, 0);\n    u8g2_SetFontPosBaseline(u8g2);\n\t\n*/\nuint8_t u8g2_UserInterfaceSelectionList(u8g2_t *u8g2, const char *title, uint8_t start_pos, const char *sl)\n{\n  u8sl_t u8sl;\n  u8g2_uint_t yy;\n\n  uint8_t event;\n\n  u8g2_uint_t line_height = u8g2_GetAscent(u8g2) - u8g2_GetDescent(u8g2)+MY_BORDER_SIZE;\n\n  uint8_t title_lines = u8x8_GetStringLineCnt(title);\n  uint8_t display_lines;\n\n  \n  if ( start_pos > 0 )\t/* issue 112 */\n    start_pos--;\t\t/* issue 112 */\n\n\n  if ( title_lines > 0 )\n  {\n\tdisplay_lines = (u8g2_GetDisplayHeight(u8g2)-3) / line_height;\n\tu8sl.visible = display_lines;\n\tu8sl.visible -= title_lines;\n  }\n  else\n  {\n\tdisplay_lines = u8g2_GetDisplayHeight(u8g2) / line_height;\n\tu8sl.visible = display_lines;\n  }\n\n  u8sl.total = u8x8_GetStringLineCnt(sl);\n  u8sl.first_pos = 0;\n  u8sl.current_pos = start_pos;\n\n  if ( u8sl.current_pos >= u8sl.total )\n    u8sl.current_pos = u8sl.total-1;\n  if ( u8sl.first_pos+u8sl.visible <= u8sl.current_pos )\n    u8sl.first_pos = u8sl.current_pos-u8sl.visible+1;\n\n  u8g2_SetFontPosBaseline(u8g2);\n  \n  for(;;)\n  {\n      u8g2_FirstPage(u8g2);\n      do\n      {\n        yy = u8g2_GetAscent(u8g2);\n        if ( title_lines > 0 )\n        {\n          yy += u8g2_DrawUTF8Lines(u8g2, 0, yy, u8g2_GetDisplayWidth(u8g2), line_height, title);\n\t\t\n\t  u8g2_DrawHLine(u8g2, 0, yy-line_height- u8g2_GetDescent(u8g2) + 1, u8g2_GetDisplayWidth(u8g2));\n\t\t\n\t  yy += 3;\n        }\n        u8g2_DrawSelectionList(u8g2, &u8sl, yy, sl);\n      } while( u8g2_NextPage(u8g2) );\n      \n#ifdef U8G2_REF_MAN_PIC\n      return 0;\n#endif\n\n\n      for(;;)\n      {\n        event = u8x8_GetMenuEvent(u8g2_GetU8x8(u8g2));\n        if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n          return u8sl.current_pos+1;\t\t/* +1, issue 112 */\n        else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n          return 0;\t\t\t\t/* issue 112: return 0 instead of start_pos */\n        else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_DOWN )\n        {\n          u8sl_Next(&u8sl);\n          break;\n        }\n        else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_UP )\n        {\n          u8sl_Prev(&u8sl);\n          break;\n        }\n      }\n  }\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_setup.c",
    "content": "/*\n\n  u8g2_setup.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n#include <string.h>\n#include <assert.h>\n\n\n/*============================================*/\n\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n\nvoid u8g2_SetMaxClipWindow(u8g2_t *u8g2)\n{\n  u8g2->clip_x0 = 0;\n  u8g2->clip_y0 = 0;\n  u8g2->clip_x1 = (u8g2_uint_t)~(u8g2_uint_t)0;\n  u8g2->clip_y1 = (u8g2_uint_t)~(u8g2_uint_t)0;\n  \n  u8g2->cb->update_page_win(u8g2);\n}\n\nvoid u8g2_SetClipWindow(u8g2_t *u8g2, u8g2_uint_t clip_x0, u8g2_uint_t clip_y0, u8g2_uint_t clip_x1, u8g2_uint_t clip_y1 )\n{\n  u8g2->clip_x0 = clip_x0;\n  u8g2->clip_y0 = clip_y0;\n  u8g2->clip_x1 = clip_x1;\n  u8g2->clip_y1 = clip_y1;\n  u8g2->cb->update_page_win(u8g2);\n}\n#endif\n\n/*============================================*/\n/*\n  This procedure is called after setting up the display (u8x8 structure).\n  --> This is the central init procedure for u8g2 object\n*/\nvoid u8g2_SetupBuffer(u8g2_t *u8g2, uint8_t *buf, uint8_t tile_buf_height, u8g2_draw_ll_hvline_cb ll_hvline_cb, const u8g2_cb_t *u8g2_cb)\n{\n  u8g2->font = NULL;\n  //u8g2->kerning = NULL;\n  //u8g2->get_kerning_cb = u8g2_GetNullKerning;\n  \n  //u8g2->ll_hvline = u8g2_ll_hvline_vertical_top_lsb;\n  u8g2->ll_hvline = ll_hvline_cb;\n  \n  u8g2->tile_buf_ptr = buf;\n  u8g2->tile_buf_height = tile_buf_height;\n  \n  u8g2->tile_curr_row = 0;\n  \n  u8g2->font_decode.is_transparent = 0; /* issue 443 */\n  u8g2->bitmap_transparency = 0;\n  \n  u8g2->draw_color = 1;\n  u8g2->is_auto_page_clear = 1;\n  \n  u8g2->cb = u8g2_cb;\n  u8g2->cb->update_dimension(u8g2);\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  u8g2_SetMaxClipWindow(u8g2);\t\t/* assign a clip window and call the update() procedure */\n#else\n  u8g2->cb->update_page_win(u8g2);\n#endif\n\n  u8g2_SetFontPosBaseline(u8g2);  /* issue 195 */\n  \n#ifdef U8G2_WITH_FONT_ROTATION  \n  u8g2->font_decode.dir = 0;\n#endif\n}\n\n/*\n  Usually the display rotation is set initially, but it could be done later also\n  u8g2_cb can be U8G2_R0..U8G2_R3\n*/\nvoid u8g2_SetDisplayRotation(u8g2_t *u8g2, const u8g2_cb_t *u8g2_cb)\n{\n  u8g2->cb = u8g2_cb;\n  u8g2->cb->update_dimension(u8g2);\n  u8g2->cb->update_page_win(u8g2);\n}\n\n/*============================================*/\n\nvoid u8g2_SendF(u8g2_t * u8g2, const char *fmt, ...)\n{\n  va_list va;\n  va_start(va, fmt);\n  u8x8_cad_vsendf(u8g2_GetU8x8(u8g2), fmt, va);\n  va_end(va);\n}\n\n\n/*============================================*/\n/* \n  update dimension: \n  calculate the following variables:\n    u8g2_uint_t buf_x0;\tleft corner of the buffer\n    u8g2_uint_t buf_x1;\tright corner of the buffer (excluded)\n    u8g2_uint_t buf_y0;\n    u8g2_uint_t buf_y1; \t\n*/\n\nstatic void u8g2_update_dimension_common(u8g2_t *u8g2)\n{\n  const u8x8_display_info_t *display_info = u8g2_GetU8x8(u8g2)->display_info;\n  u8g2_uint_t t;\n  \n  t = u8g2->tile_buf_height;\n  t *= 8;\n  u8g2->pixel_buf_height = t;\n  \n  t = display_info->tile_width;\n#ifndef U8G2_16BIT\n  if ( t >= 32 )\n    t = 31;\n#endif\n  t *= 8;\n  u8g2->pixel_buf_width = t;\n  \n  t = u8g2->tile_curr_row;\n  t *= 8;\n  u8g2->pixel_curr_row = t;\n  \n  t = u8g2->tile_buf_height;\n  /* handle the case, where the buffer is larger than the (remaining) part of the display */\n  if ( t + u8g2->tile_curr_row > display_info->tile_height )\n    t = display_info->tile_height - u8g2->tile_curr_row;\n  t *= 8;\n  \n  u8g2->buf_y0 = u8g2->pixel_curr_row;   \n  u8g2->buf_y1 = u8g2->buf_y0;\n  u8g2->buf_y1 += t;\n\n  \n#ifdef U8G2_16BIT\n  u8g2->width = display_info->pixel_width;\n  u8g2->height = display_info->pixel_height;\n#else\n  u8g2->width = 240;\n  if ( display_info->pixel_width <= 240 )\n    u8g2->width = display_info->pixel_width;\n  u8g2->height = display_info->pixel_height;\n#endif\n\n}\n\n/*==========================================================*/\n/* apply clip window */\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\nstatic void u8g2_apply_clip_window(u8g2_t *u8g2)\n{\n  /* check aganst the current user_??? window */\n  if ( u8g2_IsIntersection(u8g2, u8g2->clip_x0, u8g2->clip_y0, u8g2->clip_x1, u8g2->clip_y1) == 0 ) \n  {\n    u8g2->is_page_clip_window_intersection = 0;\n  }\n  else\n  {\n    u8g2->is_page_clip_window_intersection = 1;\n\n    if ( u8g2->user_x0 < u8g2->clip_x0 )\n      u8g2->user_x0 = u8g2->clip_x0;\n    if ( u8g2->user_x1 > u8g2->clip_x1 )\n      u8g2->user_x1 = u8g2->clip_x1;\n    if ( u8g2->user_y0 < u8g2->clip_y0 )\n      u8g2->user_y0 = u8g2->clip_y0;\n    if ( u8g2->user_y1 > u8g2->clip_y1 )\n      u8g2->user_y1 = u8g2->clip_y1;\n  }\n}\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n\n/*==========================================================*/\n\n\nvoid u8g2_update_dimension_r0(u8g2_t *u8g2)\n{\n  u8g2_update_dimension_common(u8g2);  \n}\n\nvoid u8g2_update_page_win_r0(u8g2_t *u8g2)\n{\n  u8g2->user_x0 = 0;\n  u8g2->user_x1 = u8g2->width;\t\t\t/* pixel_buf_width replaced with width */\n  \n  u8g2->user_y0 = u8g2->buf_y0;\n  u8g2->user_y1 = u8g2->buf_y1;\n  \n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  u8g2_apply_clip_window(u8g2);\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n}\n\n\nvoid u8g2_update_dimension_r1(u8g2_t *u8g2)\n{\n  u8g2_update_dimension_common(u8g2);\n  \n  u8g2->height = u8g2_GetU8x8(u8g2)->display_info->pixel_width;\n  u8g2->width = u8g2_GetU8x8(u8g2)->display_info->pixel_height;\n  \n}\n\nvoid u8g2_update_page_win_r1(u8g2_t *u8g2)\n{\n  u8g2->user_x0 = u8g2->buf_y0;\n  u8g2->user_x1 = u8g2->buf_y1;\n  \n  u8g2->user_y0 = 0;\n  u8g2->user_y1 = u8g2->height;\t/* pixel_buf_width replaced with height (which is the real pixel width) */\n  \n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  u8g2_apply_clip_window(u8g2);\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n}\n\nvoid u8g2_update_dimension_r2(u8g2_t *u8g2)\n{\n  u8g2_update_dimension_common(u8g2);\n}\n\nvoid u8g2_update_page_win_r2(u8g2_t *u8g2)\n{\n  u8g2->user_x0 = 0;\n  u8g2->user_x1 = u8g2->width;\t/* pixel_buf_width replaced with width */\n  \n  /* there are ases where the height is not a multiple of 8. */\n  /* in such a case u8g2->buf_y1 might be heigher than u8g2->height */\n  u8g2->user_y0 = 0;\n  if ( u8g2->height >= u8g2->buf_y1 )\n    u8g2->user_y0 = u8g2->height - u8g2->buf_y1;\n  u8g2->user_y1 = u8g2->height - u8g2->buf_y0;\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  u8g2_apply_clip_window(u8g2);\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n}\n\n\nvoid u8g2_update_dimension_r3(u8g2_t *u8g2)\n{\n  u8g2_update_dimension_common(u8g2);\n  \n  u8g2->height = u8g2_GetU8x8(u8g2)->display_info->pixel_width;\n  u8g2->width = u8g2_GetU8x8(u8g2)->display_info->pixel_height;\n\n}\n\nvoid u8g2_update_page_win_r3(u8g2_t *u8g2)\n{\n  /* there are ases where the height is not a multiple of 8. */\n  /* in such a case u8g2->buf_y1 might be heigher than u8g2->width */\n  u8g2->user_x0 = 0;\n  if ( u8g2->width >= u8g2->buf_y1 )\n    u8g2->user_x0 = u8g2->width - u8g2->buf_y1;\n  u8g2->user_x1 = u8g2->width - u8g2->buf_y0;\n  \n  u8g2->user_y0 = 0;\n  u8g2->user_y1 = u8g2->height;\t/* pixel_buf_width replaced with height (pixel_width) */\n\n#ifdef U8G2_WITH_CLIP_WINDOW_SUPPORT\n  u8g2_apply_clip_window(u8g2);\n#endif /* U8G2_WITH_CLIP_WINDOW_SUPPORT */\n}\n\n\n/*============================================*/\nextern void u8g2_draw_hv_line_2dir(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir);\n\n\nvoid u8g2_draw_l90_r0(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n#ifdef __unix\n  assert( dir <= 1 );\n#endif\n  u8g2_draw_hv_line_2dir(u8g2, x, y, len, dir);\n}\n\nvoid u8g2_draw_l90_mirrorr_r0(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  u8g2_uint_t xx;\n  xx = u8g2->width;\n  xx -= x;\n  if ( (dir & 1) == 0 )\n  {\n    xx -= len;\n  }\n  else\n  {\n    xx--;\n  }\n  u8g2_draw_hv_line_2dir(u8g2, xx, y, len, dir);\n}\n\nvoid u8g2_draw_mirror_vertical_r0(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  u8g2_uint_t yy;\n  yy = u8g2->height;\n  yy -= y;\n  if ( (dir & 1) == 1 )\n  {\n    yy -= len;\n  }\n  else\n  {\n    yy--;\n  }\n  u8g2_draw_hv_line_2dir(u8g2, x, yy, len, dir);\n}\n\n/* dir = 0 or 1 */\nvoid u8g2_draw_l90_r1(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  u8g2_uint_t xx, yy;\n\n#ifdef __unix\n  assert( dir <= 1 );\n#endif\n  \n  yy = x;\n  \n  xx = u8g2->height;\n  xx -= y;\n  xx--;\n  \n  dir ++;\n  if ( dir == 2 )\n  {\n    xx -= len;\n    xx++;\n    dir = 0;\n  }\n  \n  u8g2_draw_hv_line_2dir(u8g2, xx, yy, len, dir);\n}\n\nvoid u8g2_draw_l90_r2(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  u8g2_uint_t xx, yy;\n\n  /*\n  yy = u8g2->height;\n  yy -= y;\n  yy--;\n  \n  xx = u8g2->width;\n  xx -= x;\n  xx--;\n  \n  if ( dir == 0 )\n  {\n    xx -= len;\n    xx++;\n  }\n  else if ( dir == 1 )\n  {\n    yy -= len;\n    yy++;\n  }\n  */\n\n  yy = u8g2->height;\n  yy -= y;\n  \n  xx = u8g2->width;\n  xx -= x;\n  \n  if ( dir == 0 )\n  {\n    yy--;\n    xx -= len;\n  }\n  else if ( dir == 1 )\n  {\n    xx--;\n    yy -= len;\n  }\n\n  u8g2_draw_hv_line_2dir(u8g2, xx, yy, len, dir);\n}\n\nvoid u8g2_draw_l90_r3(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8g2_uint_t len, uint8_t dir)\n{\n  u8g2_uint_t xx, yy;\n\n  xx = y;\n  \n  yy = u8g2->width;\n  yy -= x;\n  \n  if ( dir == 0 )\n  {\n    yy--;\n    yy -= len;\n    yy++;\n    dir = 1;\n  }\n  else\n  {\n    yy--;\n    dir = 0;\n  }\n  \n  \n  u8g2_draw_hv_line_2dir(u8g2, xx, yy, len, dir);\n}\n\n\n\n/*============================================*/\nconst u8g2_cb_t u8g2_cb_r0 = { u8g2_update_dimension_r0, u8g2_update_page_win_r0, u8g2_draw_l90_r0 };\nconst u8g2_cb_t u8g2_cb_r1 = { u8g2_update_dimension_r1, u8g2_update_page_win_r1, u8g2_draw_l90_r1 };\nconst u8g2_cb_t u8g2_cb_r2 = { u8g2_update_dimension_r2, u8g2_update_page_win_r2, u8g2_draw_l90_r2 };\nconst u8g2_cb_t u8g2_cb_r3 = { u8g2_update_dimension_r3, u8g2_update_page_win_r3, u8g2_draw_l90_r3 };\n  \nconst u8g2_cb_t u8g2_cb_mirror = { u8g2_update_dimension_r0, u8g2_update_page_win_r0, u8g2_draw_l90_mirrorr_r0 };\nconst u8g2_cb_t u8g2_cb_mirror_vertical = { u8g2_update_dimension_r0, u8g2_update_page_win_r0, u8g2_draw_mirror_vertical_r0 };\n  \n/*============================================*/\n/* setup for the null device */\n\n/* setup for the null (empty) device */\nvoid u8g2_Setup_null(u8g2_t *u8g2, const u8g2_cb_t *rotation, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  static uint8_t buf[8];\n  u8g2_SetupDisplay(u8g2, u8x8_d_null_cb, u8x8_cad_empty, byte_cb, gpio_and_delay_cb);\n  u8g2_SetupBuffer(u8g2, buf, 1, u8g2_ll_hvline_vertical_top_lsb, rotation);\n}\n\n\n  \n  "
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8g2_stm32f4.c",
    "content": "#include <cmsis_os.h>\n#include \"stm32f4xx_hal.h\"\n#include \"u8g2.h\"\n#include \"soft_i2c.h\"\n\n#define DEVICE_ADDRESS    0x3C\n#define TX_TIMEOUT        100\n\n#define USE_I2C_INTERFACE\n//#define USE_SPI_INTERFACE\n\n\n/* SPI Interface */\nSPI_HandleTypeDef *U8G2_SPI_HANDLE;\n\n/* I2C Interface */\nI2C_HandleTypeDef *U8G2_I2C_HANDLE;\n\n\nuint8_t u8x8_stm32_gpio_and_delay(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    /* STM32 supports HW SPI, Remove unused cases like U8X8_MSG_DELAY_XXX & U8X8_MSG_GPIO_XXX */\n    switch (msg)\n    {\n        case U8X8_MSG_GPIO_AND_DELAY_INIT:\n            /* Insert codes for initialization */\n            break;\n        case U8X8_MSG_DELAY_MILLI:\n            /* ms Delay */\n            osDelay(arg_int);\n            break;\n\n#ifdef USE_SPI_INTERFACE\n            /* SPI Interface */\n        case U8X8_MSG_GPIO_CS:\n            /* Insert codes for SS pin control */\n            //HAL_GPIO_WritePin(OLED_CS_GPIO_Port, OLED_CS_Pin, arg_int);\n            break;\n        case U8X8_MSG_GPIO_DC:\n            /* Insert codes for DC pin control */\n            HAL_GPIO_WritePin(GPIOC, GPIO_PIN_4, arg_int);\n            break;\n        case U8X8_MSG_GPIO_RESET:\n            /* Insert codes for RST pin control */\n            HAL_GPIO_WritePin(GPIOB, GPIO_PIN_2, arg_int);\n            break;\n#endif\n    }\n    return 1;\n}\n\n#ifdef USE_SPI_INTERFACE\nuint8_t u8x8_byte_stm32_hw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    switch (msg)\n    {\n        case U8X8_MSG_BYTE_SEND:\n            /* Insert codes to transmit data */\n            if (HAL_SPI_Transmit(&SPI_HANDLE, arg_ptr, arg_int, TX_TIMEOUT) != HAL_OK) return 0;\n            break;\n        case U8X8_MSG_BYTE_INIT:\n            /* Insert codes to begin SPI transmission */\n            break;\n        case U8X8_MSG_BYTE_SET_DC:\n            /* Control DC pin, U8X8_MSG_GPIO_DC will be called */\n            u8x8_gpio_SetDC(u8x8, arg_int);\n            break;\n        case U8X8_MSG_BYTE_START_TRANSFER:\n            /* Select slave, U8X8_MSG_GPIO_CS will be called */\n            u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);\n            osDelay(1);\n            break;\n        case U8X8_MSG_BYTE_END_TRANSFER:\n            osDelay(1);\n            /* Insert codes to end SPI transmission */\n            u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n            break;\n        default:\n            return 0;\n    }\n    return 1;\n}\n#endif\n\n#ifdef USE_I2C_INTERFACE\n\nuint8_t u8x8_byte_stm32_hw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    /* u8g2/u8x8 will never send more than 32 bytes between START_TRANSFER and END_TRANSFER */\n    static uint8_t buffer[32];\n    static uint8_t buf_idx;\n    uint8_t *data;\n\n    switch (msg)\n    {\n        case U8X8_MSG_BYTE_SEND:\n            data = (uint8_t *) arg_ptr;\n            while (arg_int > 0)\n            {\n                buffer[buf_idx++] = *data;\n                data++;\n                arg_int--;\n            }\n            break;\n        case U8X8_MSG_BYTE_INIT:\n            /* add your custom code to init i2c subsystem */\n            break;\n        case U8X8_MSG_BYTE_SET_DC:\n            break;\n        case U8X8_MSG_BYTE_START_TRANSFER:\n            buf_idx = 0;\n            break;\n        case U8X8_MSG_BYTE_END_TRANSFER:\n            if (U8G2_I2C_HANDLE->Instance == I2C_SOFT)\n                SOFT_I2C_Master_Transmit((DEVICE_ADDRESS << 1), buffer, buf_idx);\n            else\n                HAL_I2C_Master_Transmit(U8G2_I2C_HANDLE, (DEVICE_ADDRESS << 1), buffer, buf_idx, TX_TIMEOUT);\n            break;\n        default:\n            return 0;\n    }\n    return 1;\n}\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8log.c",
    "content": "/*\n\n  u8log.c\n  \n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include <stdint.h>\n#include <string.h>\n#include \"u8x8.h\"\n\n\n/*\nstatic uint8_t u8log_is_on_screen(u8log_t *u8log, uint8_t x, uint8_t y)\n{\n  if ( x >= u8log->width )\n    return 0;\n  if ( y >= u8log->height )\n    return 0;\n  return 1;\n}\n*/\n\nstatic void u8log_clear_screen(u8log_t *u8log)\n{\n  uint8_t *dest = u8log->screen_buffer;\n  uint16_t cnt = u8log->height;\n  cnt *= u8log->width;\n  do\n  {\n    *dest++ = ' ';\n    cnt--;\n  } while( cnt > 0 );\n  \n}\n\n\n/* scroll the content of the complete buffer, set redraw_line to 255 */\nstatic void u8log_scroll_up(u8log_t *u8log)\n{\n  uint8_t *dest = u8log->screen_buffer;\n  uint8_t *src = dest+u8log->width;\n  uint16_t cnt = u8log->height;\n  cnt--;\n  cnt *= u8log->width;\n  do\n  {\n    *dest++ = *src++;\n    cnt--;\n  } while( cnt > 0 );\n  cnt = u8log->width;\n  do\n  {\n    *dest++ = ' ';\n    cnt--;\n  } while(cnt > 0);\n  \n  if ( u8log->is_redraw_line_for_each_char )\n    u8log->is_redraw_all = 1;\n  else\n    u8log->is_redraw_all_required_for_next_nl = 1;\n}\n\n/*\n  Place the cursor on the screen. This will also scroll, if required \n*/\nstatic void u8log_cursor_on_screen(u8log_t *u8log)\n{\n  //printf(\"u8log_cursor_on_screen, cursor_y=%d\\n\", u8log->cursor_y);\n  if ( u8log->cursor_x >= u8log->width )\n  {\n    u8log->cursor_x = 0;\n    u8log->cursor_y++;\n  }\n  while ( u8log->cursor_y >= u8log->height )\n  {\n    u8log_scroll_up(u8log);\n    u8log->cursor_y--;\n  }\n}\n\n/*\n  Write a printable, single char on the screen, do any kind of scrolling\n*/\nstatic void u8log_write_to_screen(u8log_t *u8log, uint8_t c)\n{\n  u8log_cursor_on_screen(u8log);\n  u8log->screen_buffer[u8log->cursor_y * u8log->width + u8log->cursor_x] = c;\n  u8log->cursor_x++;\n  \n  if ( u8log->is_redraw_line_for_each_char )\n  {\n    u8log->is_redraw_line = 1;\n    u8log->redraw_line = u8log->cursor_y;\n  }\n}\n\n/*\n  Handle control codes or write the char to the screen.\n  Supported control codes are:\n  \n    \\n\t\t10\t\tGoto first position of the next line. Line is marked for redraw.\n    \\r\t\t13\t\tGoto first position in the same line. Line is marked for redraw.\n    \\t\t\t9\t\tJump to the next tab position\n    \\f\t\t12\t\tClear the screen and mark redraw for whole screen\n    any other char\tWrite char to screen. Line redraw mark depends on \n\t\t\t\tis_redraw_line_for_each_char flag.\n*/\nvoid u8log_write_char(u8log_t *u8log, uint8_t c)\n{\n  switch(c)\n  {\n    case '\\n':\t// 10\n      u8log->is_redraw_line = 1;\n      u8log->redraw_line = u8log->cursor_y;\n      if ( u8log->is_redraw_all_required_for_next_nl )\n\tu8log->is_redraw_all = 1;\n      u8log->is_redraw_all_required_for_next_nl = 0;\n      u8log->cursor_y++;\n      u8log->cursor_x = 0;\n      break;\t\n    case '\\r':\t// 13\n      u8log->is_redraw_line = 1;\n      u8log->redraw_line = u8log->cursor_y;\n      u8log->cursor_x = 0;\n      break;\n    case '\\t':\t// 9\n      u8log->cursor_x = (u8log->cursor_x + 8) & 0xf8;\n      break;\n    case '\\f':\t// 12\n      u8log_clear_screen(u8log);\n      u8log->is_redraw_all = 1;\n      u8log->cursor_x = 0;\n      u8log->cursor_y = 0;\n      break;\n    default:\n      u8log_write_to_screen(u8log, c);\n      break;\n  }\n}\n\nvoid u8log_Init(u8log_t *u8log, uint8_t width, uint8_t height, uint8_t *buf)\n{\n  memset(u8log, 0, sizeof(u8log_t));\n  u8log->width = width;\n  u8log->height = height;\n  u8log->screen_buffer = buf;\n  u8log_clear_screen(u8log);\n}\n\nvoid u8log_SetCallback(u8log_t *u8log, u8log_cb cb, void *aux_data)\n{\n  u8log->cb = cb;\n  u8log->aux_data = aux_data;\n}\n\nvoid u8log_SetRedrawMode(u8log_t *u8log, uint8_t is_redraw_line_for_each_char)\n{\n  u8log->is_redraw_line_for_each_char = is_redraw_line_for_each_char;\n}\n\n/* offset can be negative or positive, it is 0 by default */\nvoid u8log_SetLineHeightOffset(u8log_t *u8log, int8_t line_height_offset)\n{\n  u8log->line_height_offset = line_height_offset;\n}\n\n\n\nvoid u8log_WriteChar(u8log_t *u8log, uint8_t c)\n{\n  u8log_write_char(u8log, c);\n  if ( u8log->is_redraw_line || u8log->is_redraw_all )\n  {\n    if ( u8log->cb != 0 )\n    {\n      u8log->cb(u8log);\n    }\n    u8log->is_redraw_line = 0;\n    u8log->is_redraw_all = 0;\n  }\n}\n\nvoid u8log_WriteString(u8log_t *u8log, const char *s)\n{\n  while( *s != '\\0' )\n  {\n    u8log_WriteChar(u8log, *s);\n    s++;\n  }\n}\n\nstatic void u8log_WriteHexHalfByte(u8log_t *u8log, uint8_t b) U8X8_NOINLINE;\nstatic void u8log_WriteHexHalfByte(u8log_t *u8log, uint8_t b)\n{\n  b &= 0x0f;\n  if ( b < 10 )\n    u8log_WriteChar(u8log, b+'0');\n  else\n    u8log_WriteChar(u8log, b+'a'-10);\n}\n\nvoid u8log_WriteHex8(u8log_t *u8log, uint8_t b)\n{\n  u8log_WriteHexHalfByte(u8log, b >> 4);\n  u8log_WriteHexHalfByte(u8log, b);\n}\n\nvoid u8log_WriteHex16(u8log_t *u8log, uint16_t v)\n{\n  u8log_WriteHex8(u8log, v>>8);\n  u8log_WriteHex8(u8log, v);\n}\n\nvoid u8log_WriteHex32(u8log_t *u8log, uint32_t v)\n{\n  u8log_WriteHex16(u8log, v>>16);\n  u8log_WriteHex16(u8log, v);\n}\n\n/* v = value, d = number of digits (1..3) */\nvoid u8log_WriteDec8(u8log_t *u8log, uint8_t v, uint8_t d)\n{\n  u8log_WriteString(u8log, u8x8_u8toa(v, d));\n}\n\n/* v = value, d = number of digits (1..5) */\nvoid u8log_WriteDec16(u8log_t *u8log, uint16_t v, uint8_t d)\n{\n  u8log_WriteString(u8log, u8x8_u16toa(v, d));\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8log_u8g2.c",
    "content": "/*\n\n  u8log_u8g2.c\n  \n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8g2.h\"\n/*\n  Draw the u8log text at the specified x/y position.\n  x/y position is the reference position of the first char of the first line.\n  the line height is \n    u8g2_GetAscent(u8g2) - u8g2_GetDescent(u8g2) + line_height_offset;\n  line_height_offset can be set with u8log_SetLineHeightOffset()\n  Use\n    u8g2_SetFontRefHeightText(u8g2_t *u8g2);\n    u8g2_SetFontRefHeightExtendedText(u8g2_t *u8g2);\n    u8g2_SetFontRefHeightAll(u8g2_t *u8g2);\n  to change the return values for u8g2_GetAscent and u8g2_GetDescent\n\n*/\nvoid u8g2_DrawLog(u8g2_t *u8g2, u8g2_uint_t x, u8g2_uint_t y, u8log_t *u8log)\n{\n  u8g2_uint_t disp_x, disp_y;\n  uint8_t buf_x, buf_y;\n  uint8_t c;\n  \n  disp_y = y;  \n  u8g2_SetFontDirection(u8g2, 0);\n  for( buf_y = 0; buf_y < u8log->height; buf_y++ )\n  {\n    disp_x = x;\n    for( buf_x = 0; buf_x < u8log->width; buf_x++ )\n    {\n      c = u8log->screen_buffer[buf_y * u8log->width + buf_x];\n      disp_x += u8g2_DrawGlyph(u8g2, disp_x, disp_y, c);\n    }\n    disp_y += u8g2_GetAscent(u8g2) - u8g2_GetDescent(u8g2);\n    disp_y += u8log->line_height_offset;\n  }\n}\n\n/*\n  u8lib callback for u8g2\n  \n  Only font direction 0 is supported: u8g2_SetFontDirection(u8g2, 0)\n  Use\n    u8g2_SetFontRefHeightText(u8g2_t *u8g2);\n    u8g2_SetFontRefHeightExtendedText(u8g2_t *u8g2);\n    u8g2_SetFontRefHeightAll(u8g2_t *u8g2);\n  to change the top offset and the line height and\n    u8log_SetLineHeightOffset(u8log_t *u8log, int8_t line_height_offset)\n  to change the line height.\n  \n*/\nvoid u8log_u8g2_cb(u8log_t * u8log)\n{\n  u8g2_t *u8g2 = (u8g2_t *)(u8log->aux_data);\n  if ( u8log->is_redraw_line || u8log->is_redraw_all )\n  {\n    u8g2_FirstPage(u8g2);\n    do\n    {\n      u8g2_DrawLog( u8g2, 0, u8g2_GetAscent(u8g2), u8log);\n    }\n    while( u8g2_NextPage(u8g2) );\n  }\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8log_u8x8.c",
    "content": "/*\n\n  u8log_u8x8.c\n  \n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8x8.h\"\n\nstatic void u8x8_DrawLogLine(u8x8_t *u8x8, uint8_t disp_x, uint8_t disp_y, uint8_t buf_y, u8log_t *u8log) U8X8_NOINLINE;\nstatic void u8x8_DrawLogLine(u8x8_t *u8x8, uint8_t disp_x, uint8_t disp_y, uint8_t buf_y, u8log_t *u8log)\n{\n  uint8_t buf_x;\n  uint8_t c;\n  for( buf_x = 0; buf_x < u8log->width; buf_x++ )\n  {\n    c = u8log->screen_buffer[buf_y * u8log->width + buf_x];\n    u8x8_DrawGlyph(u8x8, disp_x, disp_y, c);\n    disp_x++;\n  }\n}\n\nvoid u8x8_DrawLog(u8x8_t *u8x8, uint8_t x, uint8_t y, u8log_t *u8log)\n{\n  uint8_t buf_y;\n  for( buf_y = 0; buf_y < u8log->height; buf_y++ )\n  {\n    u8x8_DrawLogLine(u8x8, x, y, buf_y, u8log);\n    y++;\n  }\n}\n\n\nvoid u8log_u8x8_cb(u8log_t * u8log)\n{\n  u8x8_t *u8x8 = (u8x8_t *)(u8log->aux_data);\n  if ( u8log->is_redraw_all )\n  {\n    u8x8_DrawLog(u8x8, 0, 0, u8log);\n  }\n  else if ( u8log->is_redraw_line )\n  {\n    u8x8_DrawLogLine(u8x8, 0, u8log->redraw_line, u8log->redraw_line, u8log);\n  }\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8.h",
    "content": "/*\n\n  u8x8.h\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  \n  \n  U8glib has several layers. Each layer is implemented with a callback function. \n  This callback function handels the messages for the layer.\n\n  The topmost level is the display layer. It includes the following messages:\n  \n    U8X8_MSG_DISPLAY_SETUP_MEMORY\t\t\tno communicaation with the display, setup memory ony\n    U8X8_MSG_DISPLAY_INIT\n    U8X8_MSG_DISPLAY_SET_FLIP_MODE\n    U8X8_MSG_DISPLAY_SET_POWER_SAVE\n    U8X8_MSG_DISPLAY_SET_CONTRAST\n    U8X8_MSG_DISPLAY_DRAW_TILE\n\n  A display driver may decided to breakdown these messages to a lower level interface or\n  implement this functionality directly.\n  \n\n  One layer is the Command/Arg/Data interface. It can be used by the display layer\n  to communicate with the display hardware.\n  This layer only deals with data, commands and arguments. D/C line is unknown.\n    U8X8_MSG_CAD_INIT\n    U8X8_MSG_CAD_SET_I2C_ADR\t(obsolete)\n    U8X8_MSG_CAD_SET_DEVICE (obsolete)\n    U8X8_MSG_CAD_START_TRANSFER\n    U8X8_MSG_CAD_SEND_CMD\n    U8X8_MSG_CAD_SEND_ARG\n    U8X8_MSG_CAD_SEND_DATA\n    U8X8_MSG_CAD_END_TRANSFER\n    \n  The byte interface is there to send 1 byte (8 bits) to the display hardware.\n  This layer depends on the hardware of a microcontroller, if a specific hardware \n  should be used (I2C or SPI). \n  If this interface is implemented via software, it may use the GPIO level for sending\n  bytes.\n    U8X8_MSG_BYTE_INIT\n    U8X8_MSG_BYTE_SEND 30\n    U8X8_MSG_BYTE_SET_DC 31\n    U8X8_MSG_BYTE_START_TRANSFER\n    U8X8_MSG_BYTE_END_TRANSFER\n    U8X8_MSG_BYTE_SET_I2C_ADR (obsolete)\n    U8X8_MSG_BYTE_SET_DEVICE (obsolete)\n\n  GPIO and Delay\n    U8X8_MSG_GPIO_INIT\n    U8X8_MSG_DELAY_MILLI\n    U8X8_MSG_DELAY_10MICRO\n    U8X8_MSG_DELAY_100NANO\n    U8X8_MSG_DELAY_NANO\n*/\n\n#ifndef U8X8_H\n#define U8X8_H\n\n/*==========================================*/\n/* Global Defines */\n\n/* Undefine this to remove u8x8_SetContrast function */\n#define U8X8_WITH_SET_CONTRAST\n\n/* Define this for an additional user pointer inside the u8x8 data struct */\n//#define U8X8_WITH_USER_PTR\n\n\n/* Undefine this to remove u8x8_SetFlipMode function */\n/* 26 May 2016: Obsolete */\n//#define U8X8_WITH_SET_FLIP_MODE\n\n/* Select 0 or 1 for the default flip mode. This is not affected by U8X8_WITH_FLIP_MODE */\n/* Note: Not all display types support a mirror functon for the frame buffer */\n/* 26 May 2016: Obsolete */\n//#define U8X8_DEFAULT_FLIP_MODE 0\n\n/*==========================================*/\n/* Includes */\n\n\n#include <stdint.h>\n#include <stdarg.h>\n#include <stddef.h>\n#include <limits.h>\n\n#if defined(__GNUC__) && defined(__AVR__)\n#include <avr/pgmspace.h>\n#endif \n\n/*==========================================*/\n/* C++ compatible */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n/*==========================================*/\n/* U8G2 internal defines */\n\n/* the following macro returns the first value for the normal mode */\n/* or the second argument for the flip mode */\n\n/* 26 May 2016: Obsolete\n#if U8X8_DEFAULT_FLIP_MODE == 0\n#define U8X8_IF_DEFAULT_NORMAL_OR_FLIP(normal, flipmode) (normal)\n#else\n#define U8X8_IF_DEFAULT_NORMAL_OR_FLIP(normal, flipmode) (flipmode)\n#endif\n*/\n\n#ifdef __GNUC__\n#  define U8X8_NOINLINE __attribute__((noinline))\n#  define U8X8_SECTION(name) __attribute__ ((section (name)))\n#  define U8X8_UNUSED __attribute__((unused))\n#else\n#  define U8X8_SECTION(name)\n#  define U8X8_NOINLINE\n#  define U8X8_UNUSED\n#endif\n\n#if defined(__GNUC__) && defined(__AVR__)\n#  define U8X8_FONT_SECTION(name) U8X8_SECTION(\".progmem.\" name)\n#  define u8x8_pgm_read(adr) pgm_read_byte_near(adr)\n#  define U8X8_PROGMEM PROGMEM\n#endif\n\n#if defined(ESP8266)\nuint8_t u8x8_pgm_read_esp(const uint8_t * addr);   /* u8x8_8x8.c */\n#  define U8X8_FONT_SECTION(name) __attribute__((section(\".text.\" name)))\n#  define u8x8_pgm_read(adr) u8x8_pgm_read_esp(adr)\n#  define U8X8_PROGMEM\n#endif\n\n\n\n#ifndef U8X8_FONT_SECTION\n#  define U8X8_FONT_SECTION(name) \n#endif\n\n#ifndef u8x8_pgm_read\n#  ifndef CHAR_BIT\n#  \tdefine u8x8_pgm_read(adr) (*(const uint8_t *)(adr)) \n#  else\n#\tif CHAR_BIT > 8 \n#  \t  define u8x8_pgm_read(adr) ((*(const uint8_t *)(adr)) & 0x0ff)\n#     else\n#  \t  define u8x8_pgm_read(adr) (*(const uint8_t *)(adr)) \n#     endif \n#  endif\n#endif\n\n#ifndef U8X8_PROGMEM\n#  define U8X8_PROGMEM\n#endif\n\n#ifdef ARDUINO\n#define U8X8_USE_PINS\n#endif\n\n/*==========================================*/\n/* U8X8 typedefs and data structures */\n\n\ntypedef struct u8x8_struct u8x8_t;\ntypedef struct u8x8_display_info_struct u8x8_display_info_t;\ntypedef struct u8x8_tile_struct u8x8_tile_t;\n\ntypedef uint8_t (*u8x8_msg_cb)(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\ntypedef uint16_t (*u8x8_char_cb)(u8x8_t *u8x8, uint8_t b);\n\n\n\n\n//struct u8x8_mcd_struct\n//{\n//  u8x8_msg_cb cb;\t\t/* current callback function */\n//  u8x8_t *u8g2;\t\t/* pointer to the u8g2 parent to minimize the number of args */\n//  u8x8_mcd_t *next;\n//};\n\nstruct u8x8_tile_struct\n{\n  uint8_t *tile_ptr;\t/* pointer to one or more tiles... should be \"const\" */\n  uint8_t cnt;\t\t/* number of tiles */\n  uint8_t x_pos;\t/* tile x position */\n  uint8_t y_pos;\t/* tile y position */\n};\n\n\nstruct u8x8_display_info_struct\n{\n  /* == general == */\n\n  uint8_t chip_enable_level;\t\t\t/* UC1601: 0 */\n  uint8_t chip_disable_level;\t\t\t/* opposite of chip_enable_level */\n  \n  uint8_t post_chip_enable_wait_ns;\t\t/* UC1601: 5ns */\n  uint8_t pre_chip_disable_wait_ns;\t\t/* UC1601: 5ns */\n  uint8_t reset_pulse_width_ms;\t\t/* UC1601: 0.003ms --> 1ms */ \n  uint8_t post_reset_wait_ms;\t\t\t/* UC1601: 6ms  */ \n  \n  \n  /* == SPI interface == */\n  \n  /* after SDA has been applied, wait this much time for the SCK data takeover edge */\n  /* if this is smaller than sck_pulse_width_ns, then use the value from sck_pulse_width_ns */\n  uint8_t sda_setup_time_ns;\t\t/* UC1601: 12ns */\n  /* the pulse width of the the clock signal, cycle time is twice this value */\n  /* max freq is 1/(2*sck_pulse_width_ns) */\n  /* AVR: below 70: DIV2, 8 MHz, >= 70 --> 4MHz clock (DIV4) */\n  uint8_t sck_pulse_width_ns;\t\t/* UC1701: 50ns */\n  \n  /* until here we have 8 bytes (uint8_t). Newly introduced for SPI.beginTransaction */\n  uint32_t sck_clock_hz;\n  \n  /* previous name \"sck_takeover_edge\" renamed to \"spi_mode\" */\n  /* bit 0 of spi_mode is equal to the value of the previous variable sck_takeover_edge, 20 Aug 16: This is wrong the bit is actually inverted */ \n  /* SPI has four clock modes: */\n  /*   0: clock active high, data out on falling edge, clock default value is zero, takover on rising edge */\n  /*   1: clock active high, data out on rising edge, clock default value is zero, takover on falling edge */\n  /*   2: clock active low, data out on rising edge */\n  /*   3: clock active low, data out on falling edge */\n  /* most displays have clock mode 1 */\n  uint8_t spi_mode;\n  \n  /* == I2C == */\n  uint8_t i2c_bus_clock_100kHz;\t\t/* UC1601: 1000000000/275 = 37 *100k */\n\n  \n  /* == 8 bit interface == */\n  \n  /* how long to wait after all data line are set */\n  uint8_t data_setup_time_ns;\t\t/* UC1601: 30ns */\n  /* write enable pulse width */\n  uint8_t write_pulse_width_ns;\t\t/* UC1601: 40ns */\n  \n  /* == layout == */\n  uint8_t tile_width;\n  uint8_t tile_height;\n\n  uint8_t default_x_offset;\t\t/* default x offset for the display */\n  uint8_t flipmode_x_offset;\t/* x offset, if flip mode is enabled */\n \n /* pixel width is not used by the u8x8 procedures */\n /* instead it will be used by the u8g2 procedures, because the pixel dimension can */\n /* not always be calculated from the tile_width/_height */\n /* the following conditions must be true: */\n /* pixel_width <= tile_width*8 */\n /* pixel_height <= tile_height*8 */\n  uint16_t pixel_width;\n  uint16_t pixel_height;\n};\n\n\n\n/* list of U8x8 pins */\n#define U8X8_PIN_D0 0\n#define U8X8_PIN_SPI_CLOCK 0\n#define U8X8_PIN_D1 1\n#define U8X8_PIN_SPI_DATA 1\n#define U8X8_PIN_D2 2\n#define U8X8_PIN_D3 3\n#define U8X8_PIN_D4 4\n#define U8X8_PIN_D5 5\n#define U8X8_PIN_D6 6\n#define U8X8_PIN_D7 7\n\n#define U8X8_PIN_E 8\n#define U8X8_PIN_CS 9\t\t\t/* parallel, SPI */\n#define U8X8_PIN_DC 10\t\t\t/* parallel, SPI */\n#define U8X8_PIN_RESET 11\t\t/* parallel, SPI, I2C */\n\n#define U8X8_PIN_I2C_CLOCK 12\t/* 1 = Input/high impedance, 0 = drive low */\n#define U8X8_PIN_I2C_DATA 13\t/* 1 = Input/high impedance, 0 = drive low */\n\n#define U8X8_PIN_CS1 14\t\t\t/* KS0108 extra chip select */\n#define U8X8_PIN_CS2 15\t\t\t/* KS0108 extra chip select */\n\n#define U8X8_PIN_OUTPUT_CNT 16\n\n#define U8X8_PIN_MENU_SELECT 16\n#define U8X8_PIN_MENU_NEXT 17\n#define U8X8_PIN_MENU_PREV 18\n#define U8X8_PIN_MENU_HOME 19\n#define U8X8_PIN_MENU_UP 20\n#define U8X8_PIN_MENU_DOWN 21\n\n#define U8X8_PIN_INPUT_CNT 6\n\n#ifdef U8X8_USE_PINS \n#define U8X8_PIN_CNT (U8X8_PIN_OUTPUT_CNT+U8X8_PIN_INPUT_CNT)\n#define U8X8_PIN_NONE 255\n#endif\n\nstruct u8x8_struct\n{\n  const u8x8_display_info_t *display_info;\n  u8x8_char_cb next_cb; /*  procedure, which will be used to get the next char from the string */\n  u8x8_msg_cb display_cb;\n  u8x8_msg_cb cad_cb;\n  u8x8_msg_cb byte_cb;\n  u8x8_msg_cb gpio_and_delay_cb;\n  uint32_t bus_clock;\t/* can be used by the byte function to store the clock speed of the bus */\n  const uint8_t *font;\n  uint16_t encoding;\t\t/* encoding result for utf8 decoder in next_cb */\n  uint8_t x_offset;\t/* copied from info struct, can be modified in flip mode */\n  uint8_t is_font_inverse_mode; \t/* 0: normal, 1: font glyphs are inverted */\n  uint8_t i2c_address;\t/* a valid i2c adr. Initially this is 255, but this is set to something usefull during DISPLAY_INIT */\n\t\t\t\t\t/* i2c_address is the address for writing data to the display */\n\t\t\t\t\t/* usually, the lowest bit must be zero for a valid address */\n  uint8_t i2c_started;\t/* for i2c interface */\n  //uint8_t device_address;\t/* OBSOLETE???? - this is the device address, replacement for U8X8_MSG_CAD_SET_DEVICE */\n  uint8_t utf8_state;\t\t/* number of chars which are still to scan */\n  uint8_t gpio_result;\t/* return value from the gpio call (only for MENU keys at the moment) */ \n  uint8_t debounce_default_pin_state;\n  uint8_t debounce_last_pin_state;\n  uint8_t debounce_state;\n  uint8_t debounce_result_msg;\t/* result msg or event after debounce */\n#ifdef U8X8_WITH_USER_PTR\n  void *user_ptr;\n#endif\n#ifdef U8X8_USE_PINS \n  uint8_t pins[U8X8_PIN_CNT];\t/* defines a pinlist: Mainly a list of pins for the Arduino Envionment, use U8X8_PIN_xxx to access */\n#endif\n};\n\n#ifdef U8X8_WITH_USER_PTR\n#define u8x8_GetUserPtr(u8x8) ((u8x8)->user_ptr)\n#define u8x8_SetUserPtr(u8x8, p) ((u8x8)->user_ptr = (p))\n#endif\n\n\n#define u8x8_GetCols(u8x8) ((u8x8)->display_info->tile_width)\n#define u8x8_GetRows(u8x8) ((u8x8)->display_info->tile_height)\n#define u8x8_GetI2CAddress(u8x8) ((u8x8)->i2c_address)\n#define u8x8_SetI2CAddress(u8x8, address) ((u8x8)->i2c_address = (address))\n\n#define u8x8_SetGPIOResult(u8x8, val) ((u8x8)->gpio_result = (val))\n#define u8x8_GetSPIClockPhase(u8x8) ((u8x8)->display_info->spi_mode & 0x01)  /* 0 means rising edge */\n#define u8x8_GetSPIClockPolarity(u8x8) (((u8x8)->display_info->spi_mode & 0x02) >> 1)\n#define u8x8_GetSPIClockDefaultLevel(u8x8) (((u8x8)->display_info->spi_mode & 0x02) >> 1)\n\n#define u8x8_GetFontCharWidth(u8x8) u8x8_pgm_read( (u8x8)->font + 2 )\n#define u8x8_GetFontCharHeight(u8x8) u8x8_pgm_read( (u8x8)->font + 3 )\n\n#ifdef U8X8_USE_PINS \n#define u8x8_SetPin(u8x8,pin,val) (u8x8)->pins[pin] = (val)\n#define u8x8_SetMenuSelectPin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_SELECT,(val))\n#define u8x8_SetMenuNextPin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_NEXT,(val))\n#define u8x8_SetMenuPrevPin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_PREV,(val))\n#define u8x8_SetMenuHomePin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_HOME,(val))\n#define u8x8_SetMenuUpPin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_UP,(val))\n#define u8x8_SetMenuDownPin(u8x8, val) u8x8_SetPin((u8x8),U8X8_PIN_MENU_DOWN,(val))\n#endif\n\n\n/*==========================================*/\n/* u8log extension for u8x8 and u8g2 */\n\ntypedef struct u8log_struct u8log_t;\n\n\n/* redraw the specified line. */\ntypedef void (*u8log_cb)(u8log_t * u8log);\n\nstruct u8log_struct\n{\n  /* configuration */\n  void *aux_data;\t\t/* pointer to u8x8 or u8g2 */\n  uint8_t width, height;\t/* size of the terminal */\n  u8log_cb cb;\t\t\t/* callback redraw function */\n  uint8_t *screen_buffer;\t/* size must be width*heigh bytes */\n  uint8_t is_redraw_line_for_each_char;\n  int8_t line_height_offset;\t\t/* extra offset for the line height (u8g2 only) */\n  \n  /* internal data */\n  //uint8_t last_x, last_y;\t/* position of the last printed char */\n  uint8_t cursor_x, cursor_y;  /* position of the cursor, might be off screen */\n  uint8_t redraw_line;\t/* redraw specific line if is_redraw_line is not 0 */\n  uint8_t is_redraw_line;\n  uint8_t is_redraw_all;\n  uint8_t is_redraw_all_required_for_next_nl; /* in nl mode, redraw all instead of current line */\n};\n\n\n/*==========================================*/\n\n/* helper functions */\nvoid u8x8_d_helper_display_setup_memory(u8x8_t *u8x8, const u8x8_display_info_t *display_info);\nvoid u8x8_d_helper_display_init(u8x8_t *u8g2);\n\n/* Display Interface */\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_SETUP_MEMORY\n  Args:\tNone\n  Tasks:\n    1) setup u8g2->display_info\n      copy u8g2->display_info->default_x_offset to u8g2->x_offset\n      \n   usually calls u8x8_d_helper_display_setup_memory()\n*/\n#define U8X8_MSG_DISPLAY_SETUP_MEMORY 9\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_INIT\n  Args:\tNone\n  Tasks:\n\n    2) put interface into default state: \n\t  execute u8x8_gpio_Init for port directions\n\t  execute u8x8_cad_Init for default port levels\n    3) set CS status (not clear, may be done in cad/byte interface\n    4) execute display reset (gpio interface)\n    5) send setup sequence to display, do not activate display, disable \"power save\" will follow \n*/\n#define U8X8_MSG_DISPLAY_INIT 10\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_SET_POWER_SAVE\n  Args:\targ_int: 0: normal mode (RAM is visible on the display), 1: nothing is shown\n  Tasks:\n    Depending on arg_int, put the display into normal or power save mode.\n    Send the corresponding sequence to the display.\n    In power save mode, it must be possible to modify the RAM content.\n*/\n#define U8X8_MSG_DISPLAY_SET_POWER_SAVE 11\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_SET_FLIP_MODE\n  Args:\targ_int: 0: normal mode, 1: flipped HW screen (180 degree)\n  Tasks:\n    Reprogramms the display controller to rotate the display by \n    180 degree (arg_int = 1) or not (arg_int = 0)\n    This may change u8g2->x_offset if the display is smaller than the controller ram\n    This message should only be supported if U8X8_WITH_FLIP_MODE is defined.\n*/\n#define U8X8_MSG_DISPLAY_SET_FLIP_MODE 13\n\n/*  arg_int: 0..255 contrast value */\n#define U8X8_MSG_DISPLAY_SET_CONTRAST 14\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_DRAW_TILE\n  Args:\t\n    arg_int: How often to repeat this tile pattern\n    arg_ptr: pointer to u8x8_tile_t\n        uint8_t *tile_ptr;\tpointer to one or more tiles (number is \"cnt\")\n\tuint8_t cnt;\t\tnumber of tiles\n\tuint8_t x_pos;\t\tfirst tile x position\n\tuint8_t y_pos;\t\tfirst tile y position \n  Tasks:\n    One tile has exactly 8 bytes (8x8 pixel monochrome bitmap). \n    The lowest bit of the first byte is the upper left corner\n    The highest bit of the first byte is the lower left corner\n    The lowest bit of the last byte is the upper right corner\n    The highest bit of the last byte is the lower left corner\n    \"tile_ptr\" is the address of a memory area, which contains\n    one or more tiles. \"cnt\" will contain the exact number of\n    tiles in the memory areay. The size of the memory area is 8*cnt;\n    Multiple tiles in the memory area form a horizontal sequence, this \n    means the first tile is drawn at x_pos/y_pos, the second tile is drawn\n    at x_pos+1/y_pos, third at x_pos+2/y_pos.\n    \"arg_int\" tells how often the tile sequence should be repeated:\n    For example if \"cnt\" is two and tile_ptr points to tiles A and B,\n    then for arg_int = 3, the following tile sequence will be drawn:\n    ABABAB. Totally, cnt*arg_int tiles will be drawn. \n        \n*/\n#define U8X8_MSG_DISPLAY_DRAW_TILE 15\n\n\n/*\n  Name: \tU8X8_MSG_DISPLAY_REFRESH\n  Args:\t\n    arg_int: -\n    arg_ptr: -\n  \n  This was introduced for the SSD1606 eInk display.\n  The problem is, that all RAM access will not appear on the screen\n  unless a special command is executed. With this message, this command\n  sequence is executed.\n  Use\n    void u8x8_RefreshDisplay(u8x8_t *u8x8)\n  to send the message to the display handler.\n*/\n#define U8X8_MSG_DISPLAY_REFRESH 16\n\n/*==========================================*/\n/* u8x8_setup.c */\n\nuint8_t u8x8_dummy_cb(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\n/* \n  Setup u8x8 object itself. This should be the very first function \n  called on the new u8x8 object. After this call, assign the callback\n  functions. Optional: Set the pins \n*/\n\nvoid u8x8_SetupDefaults(u8x8_t *u8x8); /* do not use this, use u8x8_Setup() instead */\n\nvoid u8x8_Setup(u8x8_t *u8x8, u8x8_msg_cb display_cb, u8x8_msg_cb cad_cb, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb);\n\n/*==========================================*/\n/* u8x8_display.c */\nuint8_t u8x8_DrawTile(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t cnt, uint8_t *tile_ptr);\n\n/* \n  After a call to u8x8_SetupDefaults, \n  setup u8x8 memory structures & inform callbacks \n  This function is also called from u8x8_Setup(), so do not call u8x8_SetupMemory()\n  directly, but use u8x8_Setup() instead.\n*/\nvoid u8x8_SetupMemory(u8x8_t *u8x8);\n\n/*\n  After calling u8x8_SetupMemory()/u8x8_Setup(), init the display hardware itself.\n  This will will the first time, u8x8 talks to the display.\n  It will init the display, but keep display in power save mode. \n  Usually this command must be followed by u8x8_SetPowerSave() \n*/\nvoid u8x8_InitDisplay(u8x8_t *u8x8);\n/* wake up display from power save mode */\nvoid u8x8_SetPowerSave(u8x8_t *u8x8, uint8_t is_enable);\nvoid u8x8_SetFlipMode(u8x8_t *u8x8, uint8_t mode);\nvoid u8x8_SetContrast(u8x8_t *u8x8, uint8_t value);\nvoid u8x8_ClearDisplayWithTile(u8x8_t *u8x8, const uint8_t *buf)  U8X8_NOINLINE;\nvoid u8x8_ClearDisplay(u8x8_t *u8x8);\t// this does not work for u8g2 in some cases\nvoid u8x8_FillDisplay(u8x8_t *u8x8);\nvoid u8x8_RefreshDisplay(u8x8_t *u8x8);\t// make RAM content visible on the display (Dec 16: SSD1606 only)\nvoid u8x8_ClearLine(u8x8_t *u8x8, uint8_t line);\n\n\n\n/*==========================================*/\n/* Command Arg Data (CAD) Interface */\n\n/*\n  U8X8_MSG_CAD_INIT\n    no args\n    call U8X8_MSG_BYTE_INIT\n    setup default values for the I/O lines\n*/\n#define U8X8_MSG_CAD_INIT 20\n\n\n#define U8X8_MSG_CAD_SEND_CMD 21\n/*  arg_int: cmd byte */\n#define U8X8_MSG_CAD_SEND_ARG 22\n/*  arg_int: arg byte */\n#define U8X8_MSG_CAD_SEND_DATA 23\n/* arg_int: expected cs level after processing this msg */\n#define U8X8_MSG_CAD_START_TRANSFER 24\n/* arg_int: expected cs level after processing this msg */\n#define U8X8_MSG_CAD_END_TRANSFER 25\n/* arg_int = 0: disable chip, arg_int = 1: enable chip */\n//#define U8X8_MSG_CAD_SET_I2C_ADR 26\n//#define U8X8_MSG_CAD_SET_DEVICE 27\n\n\n\n/* u8g_cad.c */\n\n#define u8x8_cad_Init(u8x8) ((u8x8)->cad_cb((u8x8), U8X8_MSG_CAD_INIT, 0, NULL ))\n\nuint8_t u8x8_cad_SendCmd(u8x8_t *u8x8, uint8_t cmd) U8X8_NOINLINE;\nuint8_t u8x8_cad_SendArg(u8x8_t *u8x8, uint8_t arg) U8X8_NOINLINE;\nuint8_t u8x8_cad_SendMultipleArg(u8x8_t *u8x8, uint8_t cnt, uint8_t arg) U8X8_NOINLINE;\nuint8_t u8x8_cad_SendData(u8x8_t *u8x8, uint8_t cnt, uint8_t *data) U8X8_NOINLINE;\nuint8_t u8x8_cad_StartTransfer(u8x8_t *u8x8) U8X8_NOINLINE;\nuint8_t u8x8_cad_EndTransfer(u8x8_t *u8x8) U8X8_NOINLINE;\nvoid u8x8_cad_vsendf(u8x8_t * u8x8, const char *fmt, va_list va);\nvoid u8x8_SendF(u8x8_t * u8x8, const char *fmt, ...);\n\n/*\n#define U8X8_C(c0)\t\t\t\t(0x04), (c0)\n#define U8X8_CA(c0,a0)\t\t\t(0x05), (c0), (a0)\n#define U8X8_CAA(c0,a0,a1)\t\t(0x06), (c0), (a0), (a1)\n#define U8X8_DATA()\t\t\t(0x10)\n#define U8X8_D1(d0)\t\t\t(0x11), (d0)\n*/\n\n#define U8X8_C(c0)\t\t\t\t(U8X8_MSG_CAD_SEND_CMD), (c0)\n#define U8X8_A(a0)\t\t\t\t(U8X8_MSG_CAD_SEND_ARG), (a0)\n#define U8X8_CA(c0,a0)\t\t\t(U8X8_MSG_CAD_SEND_CMD), (c0), (U8X8_MSG_CAD_SEND_ARG), (a0)\n#define U8X8_CAA(c0,a0,a1)\t\t(U8X8_MSG_CAD_SEND_CMD), (c0), (U8X8_MSG_CAD_SEND_ARG), (a0), (U8X8_MSG_CAD_SEND_ARG), (a1)\n#define U8X8_CAAA(c0,a0,a1, a2)\t(U8X8_MSG_CAD_SEND_CMD), (c0), (U8X8_MSG_CAD_SEND_ARG), (a0), (U8X8_MSG_CAD_SEND_ARG), (a1), (U8X8_MSG_CAD_SEND_ARG), (a2)\n#define U8X8_CAAAA(c0,a0,a1,a2,a3)\t\t(U8X8_MSG_CAD_SEND_CMD), (c0), (U8X8_MSG_CAD_SEND_ARG), (a0), (U8X8_MSG_CAD_SEND_ARG), (a1), (U8X8_MSG_CAD_SEND_ARG), (a2), (U8X8_MSG_CAD_SEND_ARG), (a3)\n#define U8X8_AAC(a0,a1,c0)\t\t(U8X8_MSG_CAD_SEND_ARG), (a0), (U8X8_MSG_CAD_SEND_ARG), (a1), (U8X8_MSG_CAD_SEND_CMD), (c0)\n#define U8X8_D1(d0)\t\t\t(U8X8_MSG_CAD_SEND_DATA), (d0)\n\n#define U8X8_A4(a0,a1,a2,a3)\t\tU8X8_A(a0), U8X8_A(a1), U8X8_A(a2), U8X8_A(a3)\n#define U8X8_A8(a0,a1,a2,a3,a4,a5,a6,a7)\tU8X8_A4((a0), (a1), (a2), (a3)), U8X8_A4((a4), (a5), (a6), (a7))\n\n\n#define U8X8_START_TRANSFER()\t(U8X8_MSG_CAD_START_TRANSFER)\n#define U8X8_END_TRANSFER()\t(U8X8_MSG_CAD_END_TRANSFER)\n#define U8X8_DLY(m)\t\t\t(0xfe),(m)\t\t/* delay in milli seconds */\n#define U8X8_END()\t\t\t(0xff)\n\nvoid u8x8_cad_SendSequence(u8x8_t *u8x8, uint8_t const *data);\nuint8_t u8x8_cad_empty(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_110(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_001(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_011(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_st7920_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_ssd13xx_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_ssd13xx_fast_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_st75256_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_ld7032_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_cad_uc16xx_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\n\n/*==========================================*/\n/* Byte Interface */\n\n#define U8X8_MSG_BYTE_INIT U8X8_MSG_CAD_INIT\n#define U8X8_MSG_BYTE_SET_DC 32\n\n#define U8X8_MSG_BYTE_SEND U8X8_MSG_CAD_SEND_DATA\n\n#define U8X8_MSG_BYTE_START_TRANSFER U8X8_MSG_CAD_START_TRANSFER\n#define U8X8_MSG_BYTE_END_TRANSFER U8X8_MSG_CAD_END_TRANSFER\n\n//#define U8X8_MSG_BYTE_SET_I2C_ADR U8X8_MSG_CAD_SET_I2C_ADR\n//#define U8X8_MSG_BYTE_SET_DEVICE U8X8_MSG_CAD_SET_DEVICE\n\n\nuint8_t u8x8_byte_SetDC(u8x8_t *u8x8, uint8_t dc) U8X8_NOINLINE;\nuint8_t u8x8_byte_SendByte(u8x8_t *u8x8, uint8_t byte) U8X8_NOINLINE;\nuint8_t u8x8_byte_SendBytes(u8x8_t *u8x8, uint8_t cnt, uint8_t *data) U8X8_NOINLINE;\nuint8_t u8x8_byte_StartTransfer(u8x8_t *u8x8);\nuint8_t u8x8_byte_EndTransfer(u8x8_t *u8x8);\n\nuint8_t u8x8_byte_empty(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_8bit_6800mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n/* uint8_t u8x8_byte_st7920_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); */\nvoid u8x8_byte_set_ks0108_cs(u8x8_t *u8x8, uint8_t arg) U8X8_NOINLINE;\nuint8_t u8x8_byte_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_ssd13xx_sw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);  /* OBSOLETE! */\nuint8_t u8x8_byte_sw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_byte_sed1520(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\n\n/*==========================================*/\n/* GPIO Interface */\n\n\n/*\n  U8X8_MSG_GPIO_AND_DELAY_INIT\n  no args\n  setup port directions, do not set IO levels, this is done with BYTE/CAD_INIT\n*/\n#define U8X8_MSG_GPIO_AND_DELAY_INIT 40\n\n/* arg_int: milliseconds */\n#define U8X8_MSG_DELAY_MILLI\t\t41\n\n/* 10MICRO and 100NANO are not used at the moment */\n#define U8X8_MSG_DELAY_10MICRO\t\t42\n#define U8X8_MSG_DELAY_100NANO\t\t43\n\n\n#define U8X8_MSG_DELAY_NANO\t\t44\n/* delay of one i2c unit, should be 5us for 100K, and 1.25us for 400K */\n#define U8X8_MSG_DELAY_I2C\t\t45\n\n#define U8X8_MSG_GPIO(x) (64+(x))\n#ifdef U8X8_USE_PINS \n#define u8x8_GetPinIndex(u8x8, msg) ((msg)&0x3f)\n#define u8x8_GetPinValue(u8x8, msg) ((u8x8)->pins[(msg)&0x3f])\n#endif\n\n#define U8X8_MSG_GPIO_D0\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D0)\n#define U8X8_MSG_GPIO_SPI_CLOCK\tU8X8_MSG_GPIO(U8X8_PIN_SPI_CLOCK)\n#define U8X8_MSG_GPIO_D1\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D1)\n#define U8X8_MSG_GPIO_SPI_DATA\t\tU8X8_MSG_GPIO(U8X8_PIN_SPI_DATA)\n#define U8X8_MSG_GPIO_D2\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D2)\n#define U8X8_MSG_GPIO_D3\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D3)\n#define U8X8_MSG_GPIO_D4\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D4)\n#define U8X8_MSG_GPIO_D5\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D5)\n#define U8X8_MSG_GPIO_D6\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D6)\n#define U8X8_MSG_GPIO_D7\t\t\tU8X8_MSG_GPIO(U8X8_PIN_D7)\n#define U8X8_MSG_GPIO_E \t\t\tU8X8_MSG_GPIO(U8X8_PIN_E)\t\t\t// used as E1 for the SED1520\n#define U8X8_MSG_GPIO_CS\t\t\tU8X8_MSG_GPIO(U8X8_PIN_CS)\t\t// used as E2 for the SED1520\n#define U8X8_MSG_GPIO_DC\t\t\tU8X8_MSG_GPIO(U8X8_PIN_DC)\n#define U8X8_MSG_GPIO_RESET \t\tU8X8_MSG_GPIO(U8X8_PIN_RESET)\n#define U8X8_MSG_GPIO_I2C_CLOCK\tU8X8_MSG_GPIO(U8X8_PIN_I2C_CLOCK)\n#define U8X8_MSG_GPIO_I2C_DATA\t\tU8X8_MSG_GPIO(U8X8_PIN_I2C_DATA)\n\n\n#define U8X8_MSG_GPIO_CS1\t\t\tU8X8_MSG_GPIO(U8X8_PIN_CS1)\t/* KS0108 extra chip select */\n#define U8X8_MSG_GPIO_CS2\t\t\tU8X8_MSG_GPIO(U8X8_PIN_CS2)\t/* KS0108 extra chip select */\n\n\n/* these message expect the return value in u8x8->gpio_result */\n#define U8X8_MSG_GPIO_MENU_SELECT\tU8X8_MSG_GPIO(U8X8_PIN_MENU_SELECT)\n#define U8X8_MSG_GPIO_MENU_NEXT\tU8X8_MSG_GPIO(U8X8_PIN_MENU_NEXT)\n#define U8X8_MSG_GPIO_MENU_PREV\tU8X8_MSG_GPIO(U8X8_PIN_MENU_PREV)\n#define U8X8_MSG_GPIO_MENU_HOME\tU8X8_MSG_GPIO(U8X8_PIN_MENU_HOME)\n#define U8X8_MSG_GPIO_MENU_UP\t\tU8X8_MSG_GPIO(U8X8_PIN_MENU_UP)\n#define U8X8_MSG_GPIO_MENU_DOWN\tU8X8_MSG_GPIO(U8X8_PIN_MENU_DOWN)\n\n\n#define u8x8_gpio_Init(u8x8) ((u8x8)->gpio_and_delay_cb((u8x8), U8X8_MSG_GPIO_AND_DELAY_INIT, 0, NULL ))\n\n\n/*\n#define u8x8_gpio_SetDC(u8x8, v) ((u8x8)->gpio_and_delay_cb((u8x8), U8X8_MSG_GPIO_DC, (v), NULL ))\n#define u8x8_gpio_SetCS(u8x8, v) ((u8x8)->gpio_and_delay_cb((u8x8), U8X8_MSG_GPIO_CS, (v), NULL ))\n#define u8x8_gpio_SetReset(u8x8, v) ((u8x8)->gpio_and_delay_cb((u8x8), U8X8_MSG_GPIO_RESET, (v), NULL ))\n*/\n\n#define u8x8_gpio_SetDC(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_DC, (v))\n#define u8x8_gpio_SetCS(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_CS, (v))\n#define u8x8_gpio_SetReset(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_RESET, (v))\n#define u8x8_gpio_SetSPIClock(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_SPI_CLOCK, (v))\n#define u8x8_gpio_SetSPIData(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_SPI_DATA, (v))\n#define u8x8_gpio_SetI2CClock(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_I2C_CLOCK, (v))\n#define u8x8_gpio_SetI2CData(u8x8, v) u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_I2C_DATA, (v))\n\nvoid u8x8_gpio_call(u8x8_t *u8x8, uint8_t msg, uint8_t arg) U8X8_NOINLINE;\n\n#define u8x8_gpio_Delay(u8x8, msg, dly) u8x8_gpio_call((u8x8), (msg), (dly))\n//void u8x8_gpio_Delay(u8x8_t *u8x8, uint8_t msg, uint8_t dly) U8X8_NOINLINE;\n\n\n/*==========================================*/\n/* u8x8_debounce.c */\n/* return U8X8_MSG_GPIO_MENU_xxxxx messages */\nuint8_t u8x8_GetMenuEvent(u8x8_t *u8x8);\n\n/*==========================================*/\n/* u8x8_d_stdio.c */\nvoid u8x8_SetupStdio(u8x8_t *u8x8);\n\n/*==========================================*/\n/* u8x8_d_sdl_128x64.c */\nvoid u8x8_Setup_SDL_128x64(u8x8_t *u8x8);\nvoid u8x8_Setup_SDL_240x160(u8x8_t *u8x8);\nint u8g_sdl_get_key(void);\n\n/*==========================================*/\n/* u8x8_d_tga.c */\nvoid u8x8_Setup_TGA_DESC(u8x8_t *u8x8);\nvoid u8x8_Setup_TGA_LCD(u8x8_t *u8x8);\nvoid tga_save(const char *name);\n\n/*==========================================*/\n/* u8x8_d_bitmap.c */\nuint8_t u8x8_GetBitmapPixel(u8x8_t *u8x8, uint16_t x, uint16_t y);\nvoid u8x8_SaveBitmapTGA(u8x8_t *u8x8, const char *filename);\nvoid u8x8_SetupBitmap(u8x8_t *u8x8, uint16_t pixel_width, uint16_t pixel_height);\nuint8_t u8x8_ConnectBitmapToU8x8(u8x8_t *u8x8);\n\n/*==========================================*/\n/* u8x8_d_utf8.c */\nvoid u8x8_Setup_Utf8(u8x8_t *u8x8);\t/* stdout UTF-8 display */\nvoid utf8_show(void);\t\t/* show content of UTF-8 frame buffer */\n\n\n/*==========================================*/\n\n/* u8x8_setup.c */\nuint8_t u8x8_d_null_cb(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\n/* u8x8_d_XXX.c */\nuint8_t u8x8_d_uc1701_ea_dogs102(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1701_mini12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1305_128x32_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1305_128x32_adafruit(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1305_128x64_adafruit(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1305_128x64_raystar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x64_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x80_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x64_vcomh0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x64_alt0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1309_128x64_noname0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1309_128x64_noname2(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1106_128x64_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1106_128x64_vcomh0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1106_128x64_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1106_128x32_visionox(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); // located in ssd1306_128x32\nuint8_t u8x8_d_sh1106_72x40_wise(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1106_64x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1107_64x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1107_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1107_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1107_pimoroni_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1107_seeed_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1108_160x160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sh1122_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7920_192x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7920_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_2040x16(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x32_univision(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_128x32_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_64x48_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_48x64_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_64x32_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_64x32_1f(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_96x16_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1306_72x40_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ls013b7dh03_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ls027b7dh01_400x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ls027b7dh01_m0_400x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ls013b7dh05_144x168(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7511_avd_320x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7528_nhd_c160100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7528_erc16064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_ea_dogm128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_lm6063(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_64128n(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_ea_dogm132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_zolen_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_nhd_c12832(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_nhd_c12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_lm6059(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_ks0713(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_lx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_erc12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7565_erc12864_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);  /* issue #790 */\nuint8_t u8x8_d_st7567_pi_132x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_enh_dg128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_enh_dg128064i(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_64x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_hem6432(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7567_os12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7571_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7586s_s028hn118a(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7586s_erc240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7586s_ymc240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st7588_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx256128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_wo256x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx256160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx256160m(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx256160_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx25664(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx172104(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75256_jlx19296(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_st75320_jlx320240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\t/* https://github.com/olikraus/u8g2/issues/921 */\nuint8_t u8x8_d_nt7534_tg12864r(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); /* u8x8_d_st7565.c */\nuint8_t u8x8_d_ld7032_60x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ld7032_60x32_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_128x64_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_t6963_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1316_128x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1317_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1318_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1318_128x96_xcp(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1320_160x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1320_160x132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1322_nhd_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1322_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_a2printer_384x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sed1330_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ra8835_nhd_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ra8835_320x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1325_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd0323_os128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_ws_96x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_ea_w128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_midas_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_ws_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1327_visionox_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1326_er_256x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1329_128x96_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1601_128x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1604_jlx19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1608_erc24064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1608_dem240064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1608_erc240120(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1608_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1610_ea_dogxl160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1611_ea_dogm240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1611_ea_dogxl240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1611_ew50850(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);  /* 240x160 */\nuint8_t u8x8_d_uc1611_cg160160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); /* 160x160 */\nuint8_t u8x8_d_uc1617_jlx128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_uc1611_ids4073(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); /* 256x128 */\nuint8_t u8x8_d_uc1638_160x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ks0108_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ks0108_erm19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sbn1661_122x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_sed1520_122x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_pcd8544_84x48(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_pcf8812_96x65(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_hx1230_96x68(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1606_172x72(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1607_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1607_v2_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1607_gd_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ssd1607_ws_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); /* issue 637 */\nuint8_t u8x8_d_il3820_296x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_il3820_v2_296x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_lc7981_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_lc7981_160x160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_lc7981_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_lc7981_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ist3020_erc19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_ist7920_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_max7219_64x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_max7219_32x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_max7219_16x16(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_max7219_8x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_s1d15e06_160100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\nuint8_t u8x8_d_s1d15721_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);\n\n\n\n/*==========================================*/\n/* u8x8_8x8.c */\n\nuint16_t u8x8_upscale_byte(uint8_t x) U8X8_NOINLINE;\n\n\nvoid u8x8_utf8_init(u8x8_t *u8x8);\nuint16_t u8x8_ascii_next(u8x8_t *u8x8, uint8_t b);\nuint16_t u8x8_utf8_next(u8x8_t *u8x8, uint8_t b);\n// the following two functions are replaced by the init/next functions \n//uint16_t u8x8_get_encoding_from_utf8_string(const char **str);\n//uint16_t u8x8_get_char_from_string(const char **str);\n\nvoid u8x8_SetFont(u8x8_t *u8x8, const uint8_t *font_8x8);\nvoid u8x8_DrawGlyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding);\nvoid u8x8_Draw2x2Glyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding);\nvoid u8x8_Draw1x2Glyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding);\nuint8_t u8x8_DrawString(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\nuint8_t u8x8_DrawUTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\t/* return number of glyps */\nuint8_t u8x8_Draw2x2String(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\nuint8_t u8x8_Draw2x2UTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\nuint8_t u8x8_Draw1x2String(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\nuint8_t u8x8_Draw1x2UTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s);\nuint8_t u8x8_GetUTF8Len(u8x8_t *u8x8, const char *s);\n#define u8x8_SetInverseFont(u8x8, b) (u8x8)->is_font_inverse_mode = (b)\n\n/*==========================================*/\n/* itoa procedures */\nconst char *u8x8_u8toa(uint8_t v, uint8_t d);\nconst char *u8x8_u16toa(uint16_t v, uint8_t d);\nconst char *u8x8_utoa(uint16_t v);\n\n\n/*==========================================*/\n/* u8x8_string.c */\n\nuint8_t u8x8_GetStringLineCnt(const char *str);  /* return 0 for str==NULL */\nconst char *u8x8_GetStringLineStart(uint8_t line_idx, const char *str );\nvoid u8x8_CopyStringLine(char *dest, uint8_t line_idx, const char *str);\n/* draw one line, consider \\t for center */\nuint8_t u8x8_DrawUTF8Line(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t w, const char *s);\n/* draw multiple lines, handle \\t */\nuint8_t u8x8_DrawUTF8Lines(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t w, const char *s);\n\n/*==========================================*/\n\n/* u8x8_selection_list.c */\nstruct _u8sl_struct\n{\n  uint8_t visible;\t\t/* number of visible elements in the menu */\n  uint8_t total;\t\t\t/* total number of elements in the menu */\n  uint8_t first_pos;\t\t/* position of the first visible line */\n  uint8_t current_pos;\t/* current cursor position, starts at 0 */  \n  \n  uint8_t x;\t\t/* u8x8 only, not used in u8g2 */\n  uint8_t y;\t\t/* u8x8 only, not used in u8g2 */\n};\ntypedef struct _u8sl_struct u8sl_t;\n\ntypedef void (*u8x8_sl_cb)(u8x8_t *u8x8, u8sl_t *u8sl, uint8_t idx, const void *aux);\n\nvoid u8sl_Next(u8sl_t *u8sl);\nvoid u8sl_Prev(u8sl_t *u8sl);\n\nuint8_t u8x8_UserInterfaceSelectionList(u8x8_t *u8x8, const char *title, uint8_t start_pos, const char *sl);\n\n/*==========================================*/\n\n/* u8x8_message.c  */\nuint8_t u8x8_UserInterfaceMessage(u8x8_t *u8x8, const char *title1, const char *title2, const char *title3, const char *buttons);\n\n/*==========================================*/\n/* u8x8_capture.c */\n\n/* vertical_top memory architecture */\nuint8_t u8x8_capture_get_pixel_1(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width);\n\n/* horizontal right memory architecture */\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nuint8_t u8x8_capture_get_pixel_2(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width);\n\n\n\nvoid u8x8_capture_write_pbm_pre(uint8_t tile_width, uint8_t tile_height, void (*out)(const char *s));\nvoid u8x8_capture_write_pbm_buffer(uint8_t *buffer, uint8_t tile_width, uint8_t tile_height, uint8_t (*get_pixel)(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width), void (*out)(const char *s));\n\nvoid u8x8_capture_write_xbm_pre(uint8_t tile_width, uint8_t tile_height, void (*out)(const char *s));\nvoid u8x8_capture_write_xbm_buffer(uint8_t *buffer, uint8_t tile_width, uint8_t tile_height, uint8_t (*get_pixel)(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width), void (*out)(const char *s));\n\n\n\n/*==========================================*/\n\n/* u8x8_input_value.c  */\n\nuint8_t u8x8_UserInterfaceInputValue(u8x8_t *u8x8, const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits, const char *post);\n\n/*==========================================*/\n/* u8log.c */\nvoid u8log_Init(u8log_t *u8log, uint8_t width, uint8_t height, uint8_t *buf);\nvoid u8log_SetCallback(u8log_t *u8log, u8log_cb cb, void *aux_data);\nvoid u8log_SetRedrawMode(u8log_t *u8log, uint8_t is_redraw_line_for_each_char);\nvoid u8log_SetLineHeightOffset(u8log_t *u8log, int8_t line_height_offset);\nvoid u8log_WriteString(u8log_t *u8log, const char *s) U8X8_NOINLINE;\nvoid u8log_WriteChar(u8log_t *u8log, uint8_t c) U8X8_NOINLINE;\nvoid u8log_WriteHex8(u8log_t *u8log, uint8_t b) U8X8_NOINLINE;\nvoid u8log_WriteHex16(u8log_t *u8log, uint16_t v);\nvoid u8log_WriteHex32(u8log_t *u8log, uint32_t v);\nvoid u8log_WriteDec8(u8log_t *u8log, uint8_t v, uint8_t d);\nvoid u8log_WriteDec16(u8log_t *u8log, uint16_t v, uint8_t d);\n\n/*==========================================*/\n/* u8log_u8x8.c */\nvoid u8x8_DrawLog(u8x8_t *u8x8, uint8_t x, uint8_t y, u8log_t *u8log);\nvoid u8log_u8x8_cb(u8log_t * u8log);\n\n\n/*==========================================*/\n/* start font list */\nextern const uint8_t u8x8_font_amstrad_cpc_extended_f[] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_f\");\nextern const uint8_t u8x8_font_amstrad_cpc_extended_r[] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_r\");\nextern const uint8_t u8x8_font_amstrad_cpc_extended_n[] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_n\");\nextern const uint8_t u8x8_font_amstrad_cpc_extended_u[] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_u\");\nextern const uint8_t u8x8_font_5x7_f[] U8X8_FONT_SECTION(\"u8x8_font_5x7_f\");\nextern const uint8_t u8x8_font_5x7_r[] U8X8_FONT_SECTION(\"u8x8_font_5x7_r\");\nextern const uint8_t u8x8_font_5x7_n[] U8X8_FONT_SECTION(\"u8x8_font_5x7_n\");\nextern const uint8_t u8x8_font_5x8_f[] U8X8_FONT_SECTION(\"u8x8_font_5x8_f\");\nextern const uint8_t u8x8_font_5x8_r[] U8X8_FONT_SECTION(\"u8x8_font_5x8_r\");\nextern const uint8_t u8x8_font_5x8_n[] U8X8_FONT_SECTION(\"u8x8_font_5x8_n\");\nextern const uint8_t u8x8_font_8x13_1x2_f[] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_f\");\nextern const uint8_t u8x8_font_8x13_1x2_r[] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_r\");\nextern const uint8_t u8x8_font_8x13_1x2_n[] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_n\");\nextern const uint8_t u8x8_font_8x13B_1x2_f[] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_f\");\nextern const uint8_t u8x8_font_8x13B_1x2_r[] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_r\");\nextern const uint8_t u8x8_font_8x13B_1x2_n[] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_n\");\nextern const uint8_t u8x8_font_7x14_1x2_f[] U8X8_FONT_SECTION(\"u8x8_font_7x14_1x2_f\");\nextern const uint8_t u8x8_font_7x14_1x2_r[] U8X8_FONT_SECTION(\"u8x8_font_7x14_1x2_r\");\nextern const uint8_t u8x8_font_7x14_1x2_n[] U8X8_FONT_SECTION(\"u8x8_font_7x14_1x2_n\");\nextern const uint8_t u8x8_font_7x14B_1x2_f[] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_f\");\nextern const uint8_t u8x8_font_7x14B_1x2_r[] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_r\");\nextern const uint8_t u8x8_font_7x14B_1x2_n[] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_n\");\nextern const uint8_t u8x8_font_open_iconic_arrow_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_1x1\");\nextern const uint8_t u8x8_font_open_iconic_check_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_1x1\");\nextern const uint8_t u8x8_font_open_iconic_embedded_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_1x1\");\nextern const uint8_t u8x8_font_open_iconic_play_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_1x1\");\nextern const uint8_t u8x8_font_open_iconic_thing_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_1x1\");\nextern const uint8_t u8x8_font_open_iconic_weather_1x1[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_1x1\");\nextern const uint8_t u8x8_font_open_iconic_arrow_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_2x2\");\nextern const uint8_t u8x8_font_open_iconic_check_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_2x2\");\nextern const uint8_t u8x8_font_open_iconic_embedded_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_2x2\");\nextern const uint8_t u8x8_font_open_iconic_play_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_2x2\");\nextern const uint8_t u8x8_font_open_iconic_thing_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_2x2\");\nextern const uint8_t u8x8_font_open_iconic_weather_2x2[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_2x2\");\nextern const uint8_t u8x8_font_open_iconic_arrow_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_4x4\");\nextern const uint8_t u8x8_font_open_iconic_check_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_4x4\");\nextern const uint8_t u8x8_font_open_iconic_embedded_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_4x4\");\nextern const uint8_t u8x8_font_open_iconic_play_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_4x4\");\nextern const uint8_t u8x8_font_open_iconic_thing_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_4x4\");\nextern const uint8_t u8x8_font_open_iconic_weather_4x4[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_4x4\");\nextern const uint8_t u8x8_font_open_iconic_arrow_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_8x8\");\nextern const uint8_t u8x8_font_open_iconic_check_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_8x8\");\nextern const uint8_t u8x8_font_open_iconic_embedded_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_8x8\");\nextern const uint8_t u8x8_font_open_iconic_play_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_8x8\");\nextern const uint8_t u8x8_font_open_iconic_thing_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_8x8\");\nextern const uint8_t u8x8_font_open_iconic_weather_8x8[] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_8x8\");\nextern const uint8_t u8x8_font_profont29_2x3_f[] U8X8_FONT_SECTION(\"u8x8_font_profont29_2x3_f\");\nextern const uint8_t u8x8_font_profont29_2x3_r[] U8X8_FONT_SECTION(\"u8x8_font_profont29_2x3_r\");\nextern const uint8_t u8x8_font_profont29_2x3_n[] U8X8_FONT_SECTION(\"u8x8_font_profont29_2x3_n\");\nextern const uint8_t u8x8_font_artossans8_r[] U8X8_FONT_SECTION(\"u8x8_font_artossans8_r\");\nextern const uint8_t u8x8_font_artossans8_n[] U8X8_FONT_SECTION(\"u8x8_font_artossans8_n\");\nextern const uint8_t u8x8_font_artossans8_u[] U8X8_FONT_SECTION(\"u8x8_font_artossans8_u\");\nextern const uint8_t u8x8_font_artosserif8_r[] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_r\");\nextern const uint8_t u8x8_font_artosserif8_n[] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_n\");\nextern const uint8_t u8x8_font_artosserif8_u[] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_u\");\nextern const uint8_t u8x8_font_chroma48medium8_r[] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_r\");\nextern const uint8_t u8x8_font_chroma48medium8_n[] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_n\");\nextern const uint8_t u8x8_font_chroma48medium8_u[] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_u\");\nextern const uint8_t u8x8_font_saikyosansbold8_n[] U8X8_FONT_SECTION(\"u8x8_font_saikyosansbold8_n\");\nextern const uint8_t u8x8_font_saikyosansbold8_u[] U8X8_FONT_SECTION(\"u8x8_font_saikyosansbold8_u\");\nextern const uint8_t u8x8_font_torussansbold8_r[] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_r\");\nextern const uint8_t u8x8_font_torussansbold8_n[] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_n\");\nextern const uint8_t u8x8_font_torussansbold8_u[] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_u\");\nextern const uint8_t u8x8_font_victoriabold8_r[] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_r\");\nextern const uint8_t u8x8_font_victoriabold8_n[] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_n\");\nextern const uint8_t u8x8_font_victoriabold8_u[] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_u\");\nextern const uint8_t u8x8_font_victoriamedium8_r[] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_r\");\nextern const uint8_t u8x8_font_victoriamedium8_n[] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_n\");\nextern const uint8_t u8x8_font_victoriamedium8_u[] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_u\");\nextern const uint8_t u8x8_font_courB18_2x3_f[] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_f\");\nextern const uint8_t u8x8_font_courB18_2x3_r[] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_r\");\nextern const uint8_t u8x8_font_courB18_2x3_n[] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_n\");\nextern const uint8_t u8x8_font_courR18_2x3_f[] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_f\");\nextern const uint8_t u8x8_font_courR18_2x3_r[] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_r\");\nextern const uint8_t u8x8_font_courR18_2x3_n[] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_n\");\nextern const uint8_t u8x8_font_courB24_3x4_f[] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_f\");\nextern const uint8_t u8x8_font_courB24_3x4_r[] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_r\");\nextern const uint8_t u8x8_font_courB24_3x4_n[] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_n\");\nextern const uint8_t u8x8_font_courR24_3x4_f[] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_f\");\nextern const uint8_t u8x8_font_courR24_3x4_r[] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_r\");\nextern const uint8_t u8x8_font_courR24_3x4_n[] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_n\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_o_2x2_f[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_o_2x2_f\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_o_2x2_r[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_o_2x2_r\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_o_2x2_n[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_o_2x2_n\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_r_2x2_f[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_r_2x2_f\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_r_2x2_r[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_r_2x2_r\");\nextern const uint8_t u8x8_font_lucasarts_scumm_subtitle_r_2x2_n[] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_r_2x2_n\");\nextern const uint8_t u8x8_font_inr21_2x4_f[] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_f\");\nextern const uint8_t u8x8_font_inr21_2x4_r[] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_r\");\nextern const uint8_t u8x8_font_inr21_2x4_n[] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_n\");\nextern const uint8_t u8x8_font_inr33_3x6_f[] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_f\");\nextern const uint8_t u8x8_font_inr33_3x6_r[] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_r\");\nextern const uint8_t u8x8_font_inr33_3x6_n[] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_n\");\nextern const uint8_t u8x8_font_inr46_4x8_f[] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_f\");\nextern const uint8_t u8x8_font_inr46_4x8_r[] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_r\");\nextern const uint8_t u8x8_font_inr46_4x8_n[] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_n\");\nextern const uint8_t u8x8_font_inb21_2x4_f[] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_f\");\nextern const uint8_t u8x8_font_inb21_2x4_r[] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_r\");\nextern const uint8_t u8x8_font_inb21_2x4_n[] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_n\");\nextern const uint8_t u8x8_font_inb33_3x6_f[] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_f\");\nextern const uint8_t u8x8_font_inb33_3x6_r[] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_r\");\nextern const uint8_t u8x8_font_inb33_3x6_n[] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_n\");\nextern const uint8_t u8x8_font_inb46_4x8_f[] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_f\");\nextern const uint8_t u8x8_font_inb46_4x8_r[] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_r\");\nextern const uint8_t u8x8_font_inb46_4x8_n[] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_n\");\nextern const uint8_t u8x8_font_pressstart2p_f[] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_f\");\nextern const uint8_t u8x8_font_pressstart2p_r[] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_r\");\nextern const uint8_t u8x8_font_pressstart2p_n[] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_n\");\nextern const uint8_t u8x8_font_pressstart2p_u[] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_u\");\nextern const uint8_t u8x8_font_pcsenior_f[] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_f\");\nextern const uint8_t u8x8_font_pcsenior_r[] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_r\");\nextern const uint8_t u8x8_font_pcsenior_n[] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_n\");\nextern const uint8_t u8x8_font_pcsenior_u[] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_u\");\nextern const uint8_t u8x8_font_pxplusibmcgathin_f[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_f\");\nextern const uint8_t u8x8_font_pxplusibmcgathin_r[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_r\");\nextern const uint8_t u8x8_font_pxplusibmcgathin_n[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_n\");\nextern const uint8_t u8x8_font_pxplusibmcgathin_u[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_u\");\nextern const uint8_t u8x8_font_pxplusibmcga_f[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_f\");\nextern const uint8_t u8x8_font_pxplusibmcga_r[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_r\");\nextern const uint8_t u8x8_font_pxplusibmcga_n[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_n\");\nextern const uint8_t u8x8_font_pxplusibmcga_u[] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_u\");\nextern const uint8_t u8x8_font_pxplustandynewtv_f[] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_f\");\nextern const uint8_t u8x8_font_pxplustandynewtv_r[] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_r\");\nextern const uint8_t u8x8_font_pxplustandynewtv_n[] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_n\");\nextern const uint8_t u8x8_font_pxplustandynewtv_u[] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_u\");\nextern const uint8_t u8x8_font_px437wyse700a_2x2_f[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700a_2x2_f\");\nextern const uint8_t u8x8_font_px437wyse700a_2x2_r[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700a_2x2_r\");\nextern const uint8_t u8x8_font_px437wyse700a_2x2_n[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700a_2x2_n\");\nextern const uint8_t u8x8_font_px437wyse700b_2x2_f[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700b_2x2_f\");\nextern const uint8_t u8x8_font_px437wyse700b_2x2_r[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700b_2x2_r\");\nextern const uint8_t u8x8_font_px437wyse700b_2x2_n[] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700b_2x2_n\");\n\n/* end font list */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif  /* _U8X8_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_8x8.c",
    "content": "/*\n\n  u8x8_8x8.c\n  \n  font procedures, directly interfaces display procedures\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.    \n\n*/\n\n#include \"u8x8.h\"\n\n#if defined(ESP8266)\nuint8_t u8x8_pgm_read_esp(const uint8_t * addr) \n{\n    uint32_t bytes;\n    bytes = *(uint32_t*)((uint32_t)addr & ~3);\n    return ((uint8_t*)&bytes)[(uint32_t)addr & 3];\n}\n#endif\n\n\nvoid u8x8_SetFont(u8x8_t *u8x8, const uint8_t *font_8x8)\n{\n  u8x8->font = font_8x8;\n}\n\n/*\n Args:\n   u8x8: ptr to u8x8 structure\n   encoding: glyph for which the data is requested (must be between 0 and 255)\n   buf: pointer to 8 bytes\n*/\nstatic void u8x8_get_glyph_data(u8x8_t *u8x8, uint8_t encoding, uint8_t *buf, uint8_t tile_offset) U8X8_NOINLINE;\nstatic void u8x8_get_glyph_data(u8x8_t *u8x8, uint8_t encoding, uint8_t *buf, uint8_t tile_offset) \n{\n  uint8_t first, last, tiles, i;\n  uint16_t offset;\n  first = u8x8_pgm_read(u8x8->font+0);\n  last = u8x8_pgm_read(u8x8->font+1);\n  tiles = u8x8_pgm_read(u8x8->font+2);\t\t/* new 2019 format */\n  tiles *= u8x8_pgm_read(u8x8->font+3);\t/* new 2019 format */\n  \n  /* get the glyph bitmap from the font */\n  if ( first <= encoding && encoding <= last )\n  {\n    offset = encoding;\n    offset -= first;\n    offset *= tiles;\t\t/* new 2019 format */\n    offset += tile_offset;\t/* new 2019 format */\n    offset *= 8;\n    offset +=4;\t\t\t/* changed from 2 to 4, new 2019 format */\n    for( i = 0; i < 8; i++ )\n    {\n      buf[i] = u8x8_pgm_read(u8x8->font+offset);\n      offset++;\n    }\n  }\n  else\n  {\n    for( i = 0; i < 8; i++ )\n    {\n      buf[i] = 0;\n    }\n  }\n  \n  /* invert the bitmap if required */\n  if ( u8x8->is_font_inverse_mode )\n  {\n    for( i = 0; i < 8; i++ )\n    {\n      buf[i] ^= 255;\n    }\n  }\n  \n}\n\nvoid u8x8_DrawGlyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding)\n{\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t\t/* new 2019 format */\n  uint8_t tv = u8x8_pgm_read(u8x8->font+3);\t/* new 2019 format */\n  uint8_t xx, tile;\n  uint8_t buf[8];\n  th += x;\n  tv += y;\n  tile = 0;\n  do\n  {\n    xx = x;\n    do\n    {\n      u8x8_get_glyph_data(u8x8, encoding, buf, tile);\n      u8x8_DrawTile(u8x8, xx, y, 1, buf);\n      tile++;\n      xx++;\n    } while( xx < th );\n    y++;\n  } while( y < tv );\n}\n\n\n/*\n  Source: http://graphics.stanford.edu/~seander/bithacks.html\n\tSection: Interleave bits by Binary Magic Numbers \n   Original codes is here:\n\t\tstatic const unsigned int B[] = {0x55555555, 0x33333333, 0x0F0F0F0F, 0x00FF00FF};\n\t\tstatic const unsigned int S[] = {1, 2, 4, 8};\n\n\t\tunsigned int x; // Interleave lower 16 bits of x and y, so the bits of x\n\t\tunsigned int y; // are in the even positions and bits from y in the odd;\n\t\tunsigned int z; // z gets the resulting 32-bit Morton Number.  \n\t\t\t\t// x and y must initially be less than 65536.\n\n\t\tx = (x | (x << S[3])) & B[3];\n\t\tx = (x | (x << S[2])) & B[2];\n\t\tx = (x | (x << S[1])) & B[1];\n\t\tx = (x | (x << S[0])) & B[0];\n\n\t\ty = (y | (y << S[3])) & B[3];\n\t\ty = (y | (y << S[2])) & B[2];\n\t\ty = (y | (y << S[1])) & B[1];\n\t\ty = (y | (y << S[0])) & B[0];\n\n\t\tz = x | (y << 1);\n*/\nuint16_t u8x8_upscale_byte(uint8_t x) \n{\n\tuint16_t y = x;\n\ty |= (y << 4);\t\t// x = (x | (x << S[2])) & B[2];\n\ty &= 0x0f0f;\n\ty |= (y << 2);\t\t// x = (x | (x << S[1])) & B[1];\n\ty &= 0x3333;\n\ty |= (y << 1);\t\t// x = (x | (x << S[0])) & B[0];\n\ty &= 0x5555;\n  \n\ty |= (y << 1);\t\t// z = x | (y << 1);\n\treturn y;\n}\n\nstatic void u8x8_upscale_buf(uint8_t *src, uint8_t *dest) U8X8_NOINLINE;\nstatic void u8x8_upscale_buf(uint8_t *src, uint8_t *dest)\n{\n  uint8_t i = 4;  \n  do \n  {\n    *dest++ = *src;\n    *dest++ = *src++;\n    i--;\n  } while( i > 0 );\n}\n\nstatic void u8x8_draw_2x2_subglyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding, uint8_t tile)\n{\n  uint8_t i;\n  uint16_t t;\n  uint8_t buf[8];\n  uint8_t buf1[8];\n  uint8_t buf2[8];\n  u8x8_get_glyph_data(u8x8, encoding, buf, tile);\n  for( i = 0; i < 8; i ++ )\n  {\n      t = u8x8_upscale_byte(buf[i]);\n      buf1[i] = t >> 8;\n      buf2[i] = t & 255;\n  }\n  u8x8_upscale_buf(buf2, buf);\n  u8x8_DrawTile(u8x8, x, y, 1, buf);\n  \n  u8x8_upscale_buf(buf2+4, buf);\n  u8x8_DrawTile(u8x8, x+1, y, 1, buf);\n  \n  u8x8_upscale_buf(buf1, buf);\n  u8x8_DrawTile(u8x8, x, y+1, 1, buf);\n  \n  u8x8_upscale_buf(buf1+4, buf);\n  u8x8_DrawTile(u8x8, x+1, y+1, 1, buf);  \n}\n\n\nvoid u8x8_Draw2x2Glyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding)\n{\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t\t/* new 2019 format */\n  uint8_t tv = u8x8_pgm_read(u8x8->font+3);\t/* new 2019 format */\n  uint8_t xx, tile;\n  th *= 2;\n  th += x;\n  tv *= 2;\n  tv += y;\n  tile = 0;\n  do\n  {\n    xx = x;\n    do\n    {\n      u8x8_draw_2x2_subglyph(u8x8, xx, y, encoding, tile);\n      tile++;\n      xx+=2;\n    } while( xx < th );\n    y+=2;\n  } while( y < tv );  \n}\n\n/* https://github.com/olikraus/u8g2/issues/474 */\nstatic void u8x8_draw_1x2_subglyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding, uint8_t tile)\n{\n  uint8_t i;\n  uint16_t t;\n  uint8_t buf[8];\n  uint8_t buf1[8];\n  uint8_t buf2[8];\n  u8x8_get_glyph_data(u8x8, encoding, buf, tile);\n  for( i = 0; i < 8; i ++ )\n  {\n      t = u8x8_upscale_byte(buf[i]);\n      buf1[i] = t >> 8;\n      buf2[i] = t & 255;\n  }\n  u8x8_DrawTile(u8x8, x,   y, 1, buf2);\n  u8x8_DrawTile(u8x8, x, y+1, 1, buf1);\n}\n\nvoid u8x8_Draw1x2Glyph(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t encoding)\n{\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t\t/* new 2019 format */\n  uint8_t tv = u8x8_pgm_read(u8x8->font+3);\t/* new 2019 format */\n  uint8_t xx, tile;\n  th += x;\n  tv *= 2;\n  tv += y;\n  tile = 0;\n  do\n  {\n    xx = x;\n    do\n    {\n      u8x8_draw_1x2_subglyph(u8x8, xx, y, encoding, tile);\n      tile++;\n      xx++;\n    } while( xx < th );\n    y+=2;\n  } while( y < tv );  \n}\n\n/*\nsource: https://en.wikipedia.org/wiki/UTF-8\nBits\tfrom \t\tto\t\t\tbytes\tByte 1 \t\tByte 2 \t\tByte 3 \t\tByte 4 \t\tByte 5 \t\tByte 6\n  7 \tU+0000 \t\tU+007F \t\t1 \t\t0xxxxxxx\n11 \tU+0080 \t\tU+07FF \t\t2 \t\t110xxxxx \t10xxxxxx\n16 \tU+0800 \t\tU+FFFF \t\t3 \t\t1110xxxx \t10xxxxxx \t10xxxxxx\n21 \tU+10000 \tU+1FFFFF \t4 \t\t11110xxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n26 \tU+200000 \tU+3FFFFFF \t5 \t\t111110xx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx\n31 \tU+4000000 \tU+7FFFFFFF \t6 \t\t1111110x \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx \t10xxxxxx  \n\n\n*/\n\n/* reset the internal state machine */\nvoid u8x8_utf8_init(u8x8_t *u8x8)\n{\n  u8x8->utf8_state = 0;\t/* also reset during u8x8_SetupDefaults() */\n}\n\nuint16_t u8x8_ascii_next(U8X8_UNUSED u8x8_t *u8x8, uint8_t b)\n{\n  if ( b == 0 || b == '\\n' ) /* '\\n' terminates the string to support the string list procedures */\n    return 0x0ffff;\t/* end of string detected*/\n  return b;\n}\n\n/*\n  pass a byte from an utf8 encoded string to the utf8 decoder state machine\n  returns \n    0x0fffe: no glyph, just continue\n    0x0ffff: end of string\n    anything else: The decoded encoding\n*/\nuint16_t u8x8_utf8_next(u8x8_t *u8x8, uint8_t b)\n{\n  if ( b == 0 || b == '\\n' )\t/* '\\n' terminates the string to support the string list procedures */\n    return 0x0ffff;\t/* end of string detected, pending UTF8 is discarded */\n  if ( u8x8->utf8_state == 0 )\n  {\n    if ( b >= 0xfc )\t/* 6 byte sequence */\n    {\n      u8x8->utf8_state = 5;\n      b &= 1;\n    }\n    else if ( b >= 0xf8 )\n    {\n      u8x8->utf8_state = 4;\n      b &= 3;\n    }\n    else if ( b >= 0xf0 )\n    {\n      u8x8->utf8_state = 3;\n      b &= 7;      \n    }\n    else if ( b >= 0xe0 )\n    {\n      u8x8->utf8_state = 2;\n      b &= 15;\n    }\n    else if ( b >= 0xc0 )\n    {\n      u8x8->utf8_state = 1;\n      b &= 0x01f;\n    }\n    else\n    {\n      /* do nothing, just use the value as encoding */\n      return b;\n    }\n    u8x8->encoding = b;\n    return 0x0fffe;\n  }\n  else\n  {\n    u8x8->utf8_state--;\n    /* The case b < 0x080 (an illegal UTF8 encoding) is not checked here. */\n    u8x8->encoding<<=6;\n    b &= 0x03f;\n    u8x8->encoding |= b;\n    if ( u8x8->utf8_state != 0 )\n      return 0x0fffe;\t/* nothing to do yet */\n  }\n  return u8x8->encoding;\n}\n\n\n\nstatic uint8_t u8x8_draw_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s) U8X8_NOINLINE;\nstatic uint8_t u8x8_draw_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  uint16_t e;\n  uint8_t cnt = 0;\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t\t/* new 2019 format */\n\n  u8x8_utf8_init(u8x8);\n  for(;;)\n  {\n    e = u8x8->next_cb(u8x8, (uint8_t)*s);\n    if ( e == 0x0ffff )\n      break;\n    s++;\n    if ( e != 0x0fffe )\n    {\n      u8x8_DrawGlyph(u8x8, x, y, e);\n      x+=th;\n      cnt++;\n    }\n  }\n  return cnt;\n}\n\n\nuint8_t u8x8_DrawString(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_ascii_next;\n  return u8x8_draw_string(u8x8, x, y, s);\n}\n\nuint8_t u8x8_DrawUTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_utf8_next;\n  return u8x8_draw_string(u8x8, x, y, s);\n}\n\n\n\nstatic uint8_t u8x8_draw_2x2_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s) U8X8_NOINLINE;\nstatic uint8_t u8x8_draw_2x2_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  uint16_t e;\n  uint8_t cnt = 0;\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t/* new 2019 format */\n  \n  th <<= 1;\n  \n  u8x8_utf8_init(u8x8);\n  for(;;)\n  {\n    e = u8x8->next_cb(u8x8, (uint8_t)*s);\n    if ( e == 0x0ffff )\n      break;\n    s++;\n    if ( e != 0x0fffe )\n    {\n      u8x8_Draw2x2Glyph(u8x8, x, y, e);\n      x+=th;\n      cnt++;\n    }\n  }\n  return cnt;\n}\n\n\nuint8_t u8x8_Draw2x2String(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_ascii_next;\n  return u8x8_draw_2x2_string(u8x8, x, y, s);\n}\n\nuint8_t u8x8_Draw2x2UTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_utf8_next;\n  return u8x8_draw_2x2_string(u8x8, x, y, s);\n}\n\n\n\nstatic uint8_t u8x8_draw_1x2_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s) U8X8_NOINLINE;\nstatic uint8_t u8x8_draw_1x2_string(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{  \n  uint16_t e;\n  uint8_t cnt = 0;\n  uint8_t th = u8x8_pgm_read(u8x8->font+2);\t/* new 2019 format */\n  u8x8_utf8_init(u8x8);\n  for(;;)\n  {\n    e = u8x8->next_cb(u8x8, (uint8_t)*s);\n    if ( e == 0x0ffff )\n      break;\n    s++;\n    if ( e != 0x0fffe )\n    {\n      u8x8_Draw1x2Glyph(u8x8, x, y, e);\n      x+=th;\n      cnt++;\n    }\n  }\n  return cnt;\n}\n\n\nuint8_t u8x8_Draw1x2String(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_ascii_next;\n  return u8x8_draw_1x2_string(u8x8, x, y, s);\n}\n\nuint8_t u8x8_Draw1x2UTF8(u8x8_t *u8x8, uint8_t x, uint8_t y, const char *s)\n{\n  u8x8->next_cb = u8x8_utf8_next;\n  return u8x8_draw_1x2_string(u8x8, x, y, s);\n}\n\n\n\nuint8_t u8x8_GetUTF8Len(u8x8_t *u8x8, const char *s)\n{\n  uint16_t e;\n  uint8_t cnt = 0;\n  u8x8_utf8_init(u8x8);\n  for(;;)\n  {\n    e = u8x8_utf8_next(u8x8, *s);\n    if ( e == 0x0ffff )\n      break;\n    s++;\n    if ( e != 0x0fffe )\n      cnt++;\n  }\n  return cnt;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_byte.c",
    "content": "/*\n\n  u8x8_byte.c \n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  \n*/\n\n#include \"u8x8.h\"\n\nuint8_t u8x8_byte_SetDC(u8x8_t *u8x8, uint8_t dc)\n{\n  return u8x8->byte_cb(u8x8, U8X8_MSG_BYTE_SET_DC, dc, NULL);\n}\n\nuint8_t u8x8_byte_SendBytes(u8x8_t *u8x8, uint8_t cnt, uint8_t *data)\n{\n  return u8x8->byte_cb(u8x8, U8X8_MSG_BYTE_SEND, cnt, (void *)data);\n}\n\nuint8_t u8x8_byte_SendByte(u8x8_t *u8x8, uint8_t byte)\n{\n  return u8x8_byte_SendBytes(u8x8, 1, &byte);\n}\n\nuint8_t u8x8_byte_StartTransfer(u8x8_t *u8x8)\n{\n  return u8x8->byte_cb(u8x8, U8X8_MSG_BYTE_START_TRANSFER, 0, NULL);\n}\n\nuint8_t u8x8_byte_EndTransfer(u8x8_t *u8x8)\n{\n  return u8x8->byte_cb(u8x8, U8X8_MSG_BYTE_END_TRANSFER, 0, NULL);\n}\n\n/*=========================================*/\n\nuint8_t u8x8_byte_empty(U8X8_UNUSED u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n    case U8X8_MSG_BYTE_INIT:\n    case U8X8_MSG_BYTE_SET_DC:\n    case U8X8_MSG_BYTE_START_TRANSFER:\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      break;\t/* do nothing */\n  }\n  return 1;\t/* always succeed */\n}\n\n\n/*=========================================*/\n\n\n/*\n  Uses:\n    u8x8->display_info->sda_setup_time_ns\n    u8x8->display_info->sck_pulse_width_ns\n    u8x8->display_info->spi_mode\n    u8x8->display_info->chip_disable_level\n    u8x8->display_info->chip_enable_level\n    u8x8->display_info->post_chip_enable_wait_ns\n    u8x8->display_info->pre_chip_disable_wait_ns\n  Calls to GPIO and DELAY:\n    U8X8_MSG_DELAY_NANO\n    U8X8_MSG_GPIO_DC\n    U8X8_MSG_GPIO_CS\n    U8X8_MSG_GPIO_CLOCK\n    U8X8_MSG_GPIO_DATA\n  Handles:\n    U8X8_MSG_BYTE_INIT\n    U8X8_MSG_BYTE_SEND\n    U8X8_MSG_BYTE_SET_DC\n    U8X8_MSG_BYTE_START_TRANSFER\n    U8X8_MSG_BYTE_END_TRANSFER\n*/\n\nuint8_t u8x8_byte_4wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n  uint8_t takeover_edge = u8x8_GetSPIClockPhase(u8x8);\n  uint8_t not_takeover_edge = 1 - takeover_edge;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = 0; i < 8; i++ )\n\t{\n\t  if ( b & 128 )\n\t    u8x8_gpio_SetSPIData(u8x8, 1);\n\t  else\n\t    u8x8_gpio_SetSPIData(u8x8, 0);\n\t  b <<= 1;\n\t  \n\t  u8x8_gpio_SetSPIClock(u8x8, not_takeover_edge);\n\t  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sda_setup_time_ns);\n\t  u8x8_gpio_SetSPIClock(u8x8, takeover_edge);\n\t  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sck_pulse_width_ns);\n\t}    \n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      u8x8_gpio_SetSPIClock(u8x8, u8x8_GetSPIClockPhase(u8x8));\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================*/\n\nuint8_t u8x8_byte_8bit_6800mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = U8X8_MSG_GPIO_D0; i <= U8X8_MSG_GPIO_D7; i++ )\n\t{\n\t  u8x8_gpio_call(u8x8, i, b&1);\n\t  b >>= 1;\n\t}    \n\t\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 1);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);    \n      /* ensure that the enable signal is high */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_byte_8bit_8080mode(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = U8X8_MSG_GPIO_D0; i <= U8X8_MSG_GPIO_D7; i++ )\n\t{\n\t  u8x8_gpio_call(u8x8, i, b&1);\n\t  b >>= 1;\n\t}    \n\t\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 1);\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);    \n      /* ensure that the enable signal is high */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 1);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================*/\n\nuint8_t u8x8_byte_3wire_sw_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i;\n  uint8_t *data;\n  uint8_t takeover_edge = u8x8_GetSPIClockPhase(u8x8);\n  uint8_t not_takeover_edge = 1 - takeover_edge;\n  uint16_t b;\n  static uint8_t last_dc;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tif ( last_dc != 0 )\n\t  b |= 256;\n\tdata++;\n\targ_int--;\n\tfor( i = 0; i < 9; i++ )\n\t{\n\t  if ( b & 256 )\n\t    u8x8_gpio_SetSPIData(u8x8, 1);\n\t  else\n\t    u8x8_gpio_SetSPIData(u8x8, 0);\n\t  b <<= 1;\n\t  \n\t  u8x8_gpio_SetSPIClock(u8x8, not_takeover_edge);\n\t  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sda_setup_time_ns);\n\t  u8x8_gpio_SetSPIClock(u8x8, takeover_edge);\n\t  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->sck_pulse_width_ns);\n\t}    \n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      /* no wait required here */\n      \n      /* for SPI: setup correct level of the clock signal */\n      u8x8_gpio_SetSPIClock(u8x8, u8x8_GetSPIClockPhase(u8x8));\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      last_dc = arg_int;\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_enable_level);  \n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================*/\n\nvoid u8x8_byte_set_ks0108_cs(u8x8_t *u8x8, uint8_t arg)\n{\n  u8x8_gpio_SetCS(u8x8, arg&1);\n  arg = arg >> 1;\n  u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_CS1, arg&1);\n  arg = arg >> 1;\n  u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_CS2, arg&1);\n}\n\n/* 6800 mode */\nuint8_t u8x8_byte_ks0108(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = U8X8_MSG_GPIO_D0; i <= U8X8_MSG_GPIO_D7; i++ )\n\t{\n\t  u8x8_gpio_call(u8x8, i, b&1);\n\t  b >>= 1;\n\t}    \n\t\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 1);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);\n\tu8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);    \n      /* ensure that the enable signal is low */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      /* expects 3 bits in arg_int for the chip select lines */ \n      u8x8_byte_set_ks0108_cs(u8x8, arg_int);\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->post_chip_enable_wait_ns, NULL);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->pre_chip_disable_wait_ns, NULL);\n      u8x8_byte_set_ks0108_cs(u8x8, arg_int);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/* sed1520 or sbn1661 \n  U8X8_MSG_GPIO_E --> E1\n  U8X8_MSG_GPIO_CS --> E2\n*/\nuint8_t u8x8_byte_sed1520(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t i, b;\n  uint8_t *data;\n  static uint8_t enable_pin;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tdata++;\n\targ_int--;\n\tfor( i = U8X8_MSG_GPIO_D0; i <= U8X8_MSG_GPIO_D7; i++ )\n\t{\n\t  u8x8_gpio_call(u8x8, i, b&1);\n\t  b >>= 1;\n\t}    \n\t\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->data_setup_time_ns);\n\tu8x8_gpio_call(u8x8, enable_pin, 1);\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 200);\t\t/* KS0108 requires 450 ns, use 200 here */\n\tu8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, u8x8->display_info->write_pulse_width_ns);  /* expect 250 here */\n\tu8x8_gpio_call(u8x8, enable_pin, 0);\n      }\n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      /* disable chipselect */\n      u8x8_gpio_SetCS(u8x8, u8x8->display_info->chip_disable_level);    \n      /* ensure that the enable signals are low */\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_E, 0);\n      u8x8_gpio_call(u8x8, U8X8_MSG_GPIO_CS, 0);\n      enable_pin = U8X8_MSG_GPIO_E;\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      u8x8_gpio_SetDC(u8x8, arg_int);\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      /* cs lines are not supported for the SED1520/SBN1661 */\n      /* instead, this will select the E1 or E2 line */ \n      enable_pin = U8X8_MSG_GPIO_E;\n      if ( arg_int != 0 )\n\tenable_pin = U8X8_MSG_GPIO_CS;\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================*/\n\n\n/*\n  software i2c,\n  ignores ACK response (which is anyway not provided by some displays)\n  also does not allow reading from the device\n*/\nstatic void i2c_delay(u8x8_t *u8x8) U8X8_NOINLINE;\nstatic void i2c_delay(u8x8_t *u8x8)\n{\n  //u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_10MICRO, u8x8->display_info->i2c_bus_clock_100kHz);\n  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_I2C, u8x8->display_info->i2c_bus_clock_100kHz);\n}\n\nstatic void i2c_init(u8x8_t *u8x8)\n{\n  u8x8_gpio_SetI2CClock(u8x8, 1);\n  u8x8_gpio_SetI2CData(u8x8, 1);\n  \n  i2c_delay(u8x8);\n}\n\n/* actually, the scl line is not observed, so this procedure does not return a value */\n\nstatic void i2c_read_scl_and_delay(u8x8_t *u8x8)\n{\n  /* set as input (line will be high) */\n  u8x8_gpio_SetI2CClock(u8x8, 1);\n\n  i2c_delay(u8x8);\n}\n\nstatic void i2c_clear_scl(u8x8_t *u8x8)\n{\n  u8x8_gpio_SetI2CClock(u8x8, 0);\n}\n\nstatic void i2c_read_sda(u8x8_t *u8x8)\n{\n  /* set as input (line will be high) */\n  u8x8_gpio_SetI2CData(u8x8, 1);\n}\n\nstatic void i2c_clear_sda(u8x8_t *u8x8)\n{\n  /* set open collector and drive low */\n  u8x8_gpio_SetI2CData(u8x8, 0);\n}\n\nstatic void i2c_start(u8x8_t *u8x8)\n{\n  if ( u8x8->i2c_started != 0 )\n  {\n    /* if already started: do restart */\n    i2c_read_sda(u8x8);     /* SDA = 1 */\n    i2c_delay(u8x8);\n    i2c_read_scl_and_delay(u8x8);\n  }\n  i2c_read_sda(u8x8);\n  /* send the start condition, both lines go from 1 to 0 */\n  i2c_clear_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_clear_scl(u8x8);\n  u8x8->i2c_started = 1;\n}\n\n\nstatic void i2c_stop(u8x8_t *u8x8)\n{\n  /* set SDA to 0 */\n  i2c_clear_sda(u8x8);  \n  i2c_delay(u8x8);\n \n  /* now release all lines */\n  i2c_read_scl_and_delay(u8x8);\n \n  /* set SDA to 1 */\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  u8x8->i2c_started = 0;\n}\n\nstatic void i2c_write_bit(u8x8_t *u8x8, uint8_t val)\n{\n  if (val)\n    i2c_read_sda(u8x8);\n  else\n    i2c_clear_sda(u8x8);\n \n  i2c_delay(u8x8);\n  i2c_read_scl_and_delay(u8x8);\n  i2c_clear_scl(u8x8);\n}\n\nstatic void i2c_read_bit(u8x8_t *u8x8)\n{\n  //uint8_t val;\n  /* do not drive SDA */\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_read_scl_and_delay(u8x8);\n  i2c_read_sda(u8x8);\n  i2c_delay(u8x8);\n  i2c_clear_scl(u8x8);\n  //return val;\n}\n\nstatic void i2c_write_byte(u8x8_t *u8x8, uint8_t b)\n{\n  i2c_write_bit(u8x8, b & 128);\n  i2c_write_bit(u8x8, b & 64);\n  i2c_write_bit(u8x8, b & 32);\n  i2c_write_bit(u8x8, b & 16);\n  i2c_write_bit(u8x8, b & 8);\n  i2c_write_bit(u8x8, b & 4);\n  i2c_write_bit(u8x8, b & 2);\n  i2c_write_bit(u8x8, b & 1);\n    \n  /* read ack from client */\n  /* 0: ack was given by client */\n  /* 1: nothing happend during ack cycle */  \n  i2c_read_bit(u8x8);\n}\n\nuint8_t u8x8_byte_sw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t *data;\n\n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;\n    \n      while( arg_int > 0 )\n      {\n\ti2c_write_byte(u8x8, *data);\n\tdata++;\n\targ_int--;\n      }\n      \n      break;\n      \n    case U8X8_MSG_BYTE_INIT:\n      i2c_init(u8x8);\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      i2c_start(u8x8);\n      i2c_write_byte(u8x8, u8x8_GetI2CAddress(u8x8));\n      //i2c_write_byte(u8x8, 0x078);\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      i2c_stop(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================*/\n\n/* alternative i2c byte procedure */\n#ifdef ALTERNATIVE_I2C_BYTE_PROCEDURE\n\n\nvoid i2c_transfer(u8x8_t *u8x8, uint8_t adr, uint8_t cnt, uint8_t *data)\n{\n  uint8_t i;\n  i2c_start(u8x8);\n  i2c_write_byte(u8x8, adr);\n  for( i = 0; i < cnt; i++ )\n    i2c_write_byte(u8x8, data[i]);\n  i2c_stop(u8x8);  \n}\n\n\nuint8_t u8x8_byte_sw_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  static uint8_t buffer[32];\t\t/* u8g2/u8x8 will never send more than 32 bytes */\n  static uint8_t buf_idx;\n  uint8_t *data;\n \n  switch(msg)\n  {\n    case U8X8_MSG_BYTE_SEND:\n      data = (uint8_t *)arg_ptr;      \n      while( arg_int > 0 )\n      {\n\tbuffer[buf_idx++] = *data;\n\tdata++;\n\targ_int--;\n      }      \n      break;\n    case U8X8_MSG_BYTE_INIT:\n      i2c_init(u8x8);\t\t\t/* init i2c communication */\n      break;\n    case U8X8_MSG_BYTE_SET_DC:\n      /* ignored for i2c */\n      break;\n    case U8X8_MSG_BYTE_START_TRANSFER:\n      buf_idx = 0;\n      break;\n    case U8X8_MSG_BYTE_END_TRANSFER:\n      i2c_transfer(u8x8, u8x8_GetI2CAddress(u8x8), buf_idx, buffer);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_cad.c",
    "content": "/*\n  \n  u8x8_cad.c\n  \n  \"command arg data\" interface to the graphics controller\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  The following sequence must be used for any data, which is set to the display:\n  \n  \n  uint8_t u8x8_cad_StartTransfer(u8x8_t *u8x8)\n\n  any of the following calls\n    uint8_t u8x8_cad_SendCmd(u8x8_t *u8x8, uint8_t cmd)\n    uint8_t u8x8_cad_SendArg(u8x8_t *u8x8, uint8_t arg)\n    uint8_t u8x8_cad_SendData(u8x8_t *u8x8, uint8_t cnt, uint8_t *data)\n  \n  uint8_t u8x8_cad_EndTransfer(u8x8_t *u8x8)\n\n\n\n*/\n/*\nuint8_t u8x8_cad_template(u8x8_t *u8x8, uint8_t msg, uint16_t arg_int, void *arg_ptr)\n{\n  uint8_t i;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_mcd_byte_SetDC(mcd->next, 1);\n      u8x8_mcd_byte_Send(mcd->next, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_mcd_byte_SetDC(mcd->next, 1);\n      u8x8_mcd_byte_Send(mcd->next, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      u8x8_mcd_byte_SetDC(mcd->next, 0);\n      for( i = 0; i < 8; i++ )\n\tu8x8_mcd_byte_Send(mcd->next, ((uint8_t *)arg_ptr)[i]);\n      break;\n    case U8X8_MSG_CAD_RESET:\n      return mcd->next->cb(mcd->next, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n      return mcd->next->cb(mcd->next, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return mcd->next->cb(mcd->next, msg, arg_int, arg_ptr);\n    default:\n      break;\n  }\n  return 1;\n}\n\n*/\n\n#include \"u8x8.h\"\n\nuint8_t u8x8_cad_SendCmd(u8x8_t *u8x8, uint8_t cmd)\n{\n  return u8x8->cad_cb(u8x8, U8X8_MSG_CAD_SEND_CMD, cmd, NULL);\n}\n\nuint8_t u8x8_cad_SendArg(u8x8_t *u8x8, uint8_t arg)\n{\n  return u8x8->cad_cb(u8x8, U8X8_MSG_CAD_SEND_ARG, arg, NULL);\n}\n\nuint8_t u8x8_cad_SendMultipleArg(u8x8_t *u8x8, uint8_t cnt, uint8_t arg)\n{\n  while( cnt > 0 )\n  {\n    u8x8->cad_cb(u8x8, U8X8_MSG_CAD_SEND_ARG, arg, NULL);\n    cnt--;\n  }\n  return 1;\n}\n\nuint8_t u8x8_cad_SendData(u8x8_t *u8x8, uint8_t cnt, uint8_t *data)\n{\n  return u8x8->cad_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, cnt, data);\n}\n\nuint8_t u8x8_cad_StartTransfer(u8x8_t *u8x8)\n{\n  return u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 0, NULL);\n}\n\nuint8_t u8x8_cad_EndTransfer(u8x8_t *u8x8)\n{\n  return u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n}\n\nvoid u8x8_cad_vsendf(u8x8_t * u8x8, const char *fmt, va_list va)\n{\n  uint8_t d;\n  u8x8_cad_StartTransfer(u8x8);\n  while( *fmt != '\\0' )\n  {\n    d = (uint8_t)va_arg(va, int);\n    switch(*fmt)\n    {\n      case 'a':  u8x8_cad_SendArg(u8x8, d); break;\n      case 'c':  u8x8_cad_SendCmd(u8x8, d); break;\n      case 'd':  u8x8_cad_SendData(u8x8, 1, &d); break;\n    }\n    fmt++;\n  }\n  u8x8_cad_EndTransfer(u8x8);\n}\n\nvoid u8x8_SendF(u8x8_t * u8x8, const char *fmt, ...)\n{\n  va_list va;\n  va_start(va, fmt);\n  u8x8_cad_vsendf(u8x8, fmt, va);\n  va_end(va);\n}\n\n/*\n  21 c\t\tsend command c\n  22 a\t\tsend arg a\n  23 d\t\tsend data d\n  24\t\t\tCS on\n  25\t\t\tCS off\n  254 milli\tdelay by milliseconds\n  255\t\tend of sequence\n*/\n\nvoid u8x8_cad_SendSequence(u8x8_t *u8x8, uint8_t const *data)\n{\n  uint8_t cmd;\n  uint8_t v;\n\n  for(;;)\n  {\n    cmd = *data;\n    data++;\n    switch( cmd )\n    {\n      case U8X8_MSG_CAD_SEND_CMD:\n      case U8X8_MSG_CAD_SEND_ARG:\n\t  v = *data;\n\t  u8x8->cad_cb(u8x8, cmd, v, NULL);\n\t  data++;\n\t  break;\n      case U8X8_MSG_CAD_SEND_DATA:\n\t  v = *data;\n\t  u8x8_cad_SendData(u8x8, 1, &v);\n\t  data++;\n\t  break;\n      case U8X8_MSG_CAD_START_TRANSFER:\n      case U8X8_MSG_CAD_END_TRANSFER:\n\t  u8x8->cad_cb(u8x8, cmd, 0, NULL);\n\t  break;\n      case 0x0fe:\n\t  v = *data;\n\t  u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, v);\t    \n\t  data++;\n\t  break;\n      default:\n\treturn;\n    }\n  }\n}\n\n\nuint8_t u8x8_cad_empty(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*\n  convert to bytes by using \n    dc = 1 for commands and args and\n    dc = 0 for data\n*/\nuint8_t u8x8_cad_110(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SetDC(u8x8, 1);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SetDC(u8x8, 1);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      u8x8_byte_SetDC(u8x8, 0);\n      //u8x8_byte_SendBytes(u8x8, arg_int, arg_ptr);\n      //break;\n      /* fall through */\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*\n  convert to bytes by using \n    dc = 1 for commands and args and\n    dc = 0 for data\n    t6963\n*/\nuint8_t u8x8_cad_100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SetDC(u8x8, 1);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SetDC(u8x8, 0);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      u8x8_byte_SetDC(u8x8, 0);\n      //u8x8_byte_SendBytes(u8x8, arg_int, arg_ptr);\n      //break;\n      /* fall through */\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*\n  convert to bytes by using \n    dc = 0 for commands and args and\n    dc = 1 for data\n*/\nuint8_t u8x8_cad_001(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SetDC(u8x8, 0);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SetDC(u8x8, 0);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      u8x8_byte_SetDC(u8x8, 1);\n      //u8x8_byte_SendBytes(u8x8, arg_int, arg_ptr);\n      //break;\n      /* fall through */\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*\n  convert to bytes by using \n    dc = 0 for commands \n    dc = 1 for args and data\n*/\nuint8_t u8x8_cad_011(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SetDC(u8x8, 0);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SetDC(u8x8, 1);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      u8x8_byte_SetDC(u8x8, 1);\n      //u8x8_byte_SendBytes(u8x8, arg_int, arg_ptr);\n      //break;\n      /* fall through */\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* cad procedure for the ST7920 in SPI mode */\n/* u8x8_byte_SetDC is not used */\nuint8_t u8x8_cad_st7920_spi(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t *data;\n  uint8_t b;\n  uint8_t i;\n  static uint8_t buf[16];\n  uint8_t *ptr;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_SendByte(u8x8, 0x0f8);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 1);\n      u8x8_byte_SendByte(u8x8, arg_int & 0x0f0);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 1);\n      u8x8_byte_SendByte(u8x8, arg_int << 4);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 1);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SendByte(u8x8, 0x0f8);\n      u8x8_byte_SendByte(u8x8, arg_int & 0x0f0);\n      u8x8_byte_SendByte(u8x8, arg_int << 4);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n    \n      u8x8_byte_SendByte(u8x8, 0x0fa);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 1);\n\n      /* this loop should be optimized: multiple bytes should be sent */\n      /* u8x8_byte_SendBytes(u8x8, arg_int, arg_ptr); */\n      data = (uint8_t *)arg_ptr;\n    \n      /* the following loop increases speed by 20% */\n      while( arg_int >= 8 )\n      {\n\ti = 8;\n\tptr = buf;\n\tdo\n\t{\n\t  b = *data++;\n\t  *ptr++= b & 0x0f0;\n\t  b <<= 4;\n\t  *ptr++= b;\n\t  i--;\n\t} while( i > 0 );\n\targ_int -= 8;\n\tu8x8_byte_SendBytes(u8x8, 16, buf); \n      }\n      \n    \n      while( arg_int > 0 )\n      {\n\tb = *data;\n\tu8x8_byte_SendByte(u8x8, b & 0x0f0);\n\tu8x8_byte_SendByte(u8x8, b << 4);\n\tdata++;\n\targ_int--;\n      }\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_NANO, 1);\n      break;\n    case U8X8_MSG_CAD_INIT:\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/* cad procedure for the SSD13xx family in I2C mode */\n/* this procedure is also used by the ST7588 */\n/* u8x8_byte_SetDC is not used */\n/* U8X8_MSG_BYTE_START_TRANSFER starts i2c transfer, U8X8_MSG_BYTE_END_TRANSFER stops transfer */\n/* After transfer start, a full byte indicates command or data mode */\n\nstatic void u8x8_i2c_data_transfer(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr) U8X8_NOINLINE;\nstatic void u8x8_i2c_data_transfer(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr)\n{\n    u8x8_byte_StartTransfer(u8x8);    \n    u8x8_byte_SendByte(u8x8, 0x040);\n    u8x8->byte_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, arg_int, arg_ptr);\n    u8x8_byte_EndTransfer(u8x8);\n}\n\n/* classic version: will put a start/stop condition around each command and arg */\nuint8_t u8x8_cad_ssd13xx_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t *p;\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n    case U8X8_MSG_CAD_SEND_ARG:\n      /* 7 Nov 2016: Can this be improved?  */\n      //u8x8_byte_SetDC(u8x8, 0);\n      u8x8_byte_StartTransfer(u8x8);\n      //u8x8_byte_SendByte(u8x8, u8x8_GetI2CAddress(u8x8));\n      u8x8_byte_SendByte(u8x8, 0x000);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      u8x8_byte_EndTransfer(u8x8);      \n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      //u8x8_byte_SetDC(u8x8, 1);\n    \n      /* the FeatherWing OLED with the 32u4 transfer of long byte */\n      /* streams was not possible. This is broken down to */\n      /* smaller streams, 32 seems to be the limit... */\n      /* I guess this is related to the size of the Wire buffers in Arduino */\n      /* Unfortunately, this can not be handled in the byte level drivers, */\n      /* so this is done here. Even further, only 24 bytes will be sent, */\n      /* because there will be another byte (DC) required during the transfer */\n      p = arg_ptr;\n       while( arg_int > 24 )\n      {\n\tu8x8_i2c_data_transfer(u8x8, 24, p);\n\targ_int-=24;\n\tp+=24;\n      }\n      u8x8_i2c_data_transfer(u8x8, arg_int, p);\n      break;\n    case U8X8_MSG_CAD_INIT:\n      /* apply default i2c adr if required so that the start transfer msg can use this */\n      if ( u8x8->i2c_address == 255 )\n\tu8x8->i2c_address = 0x078;\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      /* cad transfer commands are ignored */\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/* fast version with reduced data start/stops, issue 735 */\nuint8_t u8x8_cad_ssd13xx_fast_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  static uint8_t in_transfer = 0;\n  uint8_t *p;\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      /* improved version, takeover from ld7032 */\n      /* assumes, that the args of a command is not longer than 31 bytes */\n      /* speed improvement is about 4% compared to the classic version */\n      if ( in_transfer != 0 )\n\t u8x8_byte_EndTransfer(u8x8); \n      \n      u8x8_byte_StartTransfer(u8x8);\n      u8x8_byte_SendByte(u8x8, 0x000);\t/* cmd byte for ssd13xx controller */\n      u8x8_byte_SendByte(u8x8, arg_int);\n      in_transfer = 1;\n      /* lightning version: can replace the improved version from above */\n      /* the drawback of the lightning version is this: The complete init sequence */\n      /* must fit into the 32 byte Arduino Wire buffer, which might not always be the case */\n      /* speed improvement is about 6% compared to the classic version */\n      // if ( in_transfer == 0 )\n\t// {\n\t//   u8x8_byte_StartTransfer(u8x8);\n\t//   u8x8_byte_SendByte(u8x8, 0x000);\t/* cmd byte for ssd13xx controller */\n\t//   in_transfer = 1;\n\t// }\n\t//u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;      \n    case U8X8_MSG_CAD_SEND_DATA:\n      if ( in_transfer != 0 )\n\tu8x8_byte_EndTransfer(u8x8); \n      \n    \n      /* the FeatherWing OLED with the 32u4 transfer of long byte */\n      /* streams was not possible. This is broken down to */\n      /* smaller streams, 32 seems to be the limit... */\n      /* I guess this is related to the size of the Wire buffers in Arduino */\n      /* Unfortunately, this can not be handled in the byte level drivers, */\n      /* so this is done here. Even further, only 24 bytes will be sent, */\n      /* because there will be another byte (DC) required during the transfer */\n      p = arg_ptr;\n       while( arg_int > 24 )\n      {\n\tu8x8_i2c_data_transfer(u8x8, 24, p);\n\targ_int-=24;\n\tp+=24;\n      }\n      u8x8_i2c_data_transfer(u8x8, arg_int, p);\n      in_transfer = 0;\n      break;\n    case U8X8_MSG_CAD_INIT:\n      /* apply default i2c adr if required so that the start transfer msg can use this */\n      if ( u8x8->i2c_address == 255 )\n\tu8x8->i2c_address = 0x078;\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n      in_transfer = 0;\n      break;\n    case U8X8_MSG_CAD_END_TRANSFER:\n      if ( in_transfer != 0 )\n\tu8x8_byte_EndTransfer(u8x8); \n      in_transfer = 0;\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n/* the st75256 i2c driver is a copy of the ssd13xx driver, but with arg=1 */\n/* modified from cad001 (ssd13xx) to cad011 */\nuint8_t u8x8_cad_st75256_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t *p;\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      u8x8_byte_StartTransfer(u8x8);\n      u8x8_byte_SendByte(u8x8, 0x000);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      u8x8_byte_EndTransfer(u8x8);      \n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_StartTransfer(u8x8);\n      u8x8_byte_SendByte(u8x8, 0x040);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      u8x8_byte_EndTransfer(u8x8);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      /* see ssd13xx driver */\n      p = arg_ptr;\n       while( arg_int > 24 )\n      {\n\tu8x8_i2c_data_transfer(u8x8, 24, p);\n\targ_int-=24;\n\tp+=24;\n      }\n      u8x8_i2c_data_transfer(u8x8, arg_int, p);\n      break;\n    case U8X8_MSG_CAD_INIT:\n      /* apply default i2c adr if required so that the start transfer msg can use this */\n      if ( u8x8->i2c_address == 255 )\n\tu8x8->i2c_address = 0x078;\t/* ST75256, often this is 0x07e */\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n    case U8X8_MSG_CAD_END_TRANSFER:\n      /* cad transfer commands are ignored */\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* cad i2c procedure for the ld7032 controller */\n/* Issue https://github.com/olikraus/u8g2/issues/865 mentiones, that I2C does not work */\n/* Workaround is to remove the while loop (or increase the value in the condition) */\nuint8_t u8x8_cad_ld7032_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  static uint8_t in_transfer = 0;\n  uint8_t *p;\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n      if ( in_transfer != 0 )\n\tu8x8_byte_EndTransfer(u8x8); \n      u8x8_byte_StartTransfer(u8x8);\n      u8x8_byte_SendByte(u8x8, arg_int);\n      in_transfer = 1;\n      break;\n    case U8X8_MSG_CAD_SEND_ARG:\n      u8x8_byte_SendByte(u8x8, arg_int);\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      //u8x8_byte_SetDC(u8x8, 1);\n    \n      /* the FeatherWing OLED with the 32u4 transfer of long byte */\n      /* streams was not possible. This is broken down to */\n      /* smaller streams, 32 seems to be the limit... */\n      /* I guess this is related to the size of the Wire buffers in Arduino */\n      /* Unfortunately, this can not be handled in the byte level drivers, */\n      /* so this is done here. Even further, only 24 bytes will be sent, */\n      /* because there will be another byte (DC) required during the transfer */\n      p = arg_ptr;\n       while( arg_int > 24 )\n      {\n\tu8x8->byte_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, 24, p);\n\targ_int-=24;\n\tp+=24;\n\tu8x8_byte_EndTransfer(u8x8); \n\tu8x8_byte_StartTransfer(u8x8);\n\tu8x8_byte_SendByte(u8x8, 0x08);\t/* data write for LD7032 */\n      }\n      u8x8->byte_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, arg_int, p);\n      break;\n    case U8X8_MSG_CAD_INIT:\n      /* apply default i2c adr if required so that the start transfer msg can use this */\n      if ( u8x8->i2c_address == 255 )\n\tu8x8->i2c_address = 0x060;\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n      in_transfer = 0;\n      break;\n    case U8X8_MSG_CAD_END_TRANSFER:\n      if ( in_transfer != 0 )\n\tu8x8_byte_EndTransfer(u8x8); \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* cad procedure for the UC16xx family in I2C mode */\n/* u8x8_byte_SetDC is not used */\n/* DC bit is encoded into the adr byte */\nuint8_t u8x8_cad_uc16xx_i2c(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  static uint8_t in_transfer = 0;\t\n  static uint8_t is_data = 0;\n  uint8_t *p;\n  switch(msg)\n  {\n    case U8X8_MSG_CAD_SEND_CMD:\n    case U8X8_MSG_CAD_SEND_ARG:\n      if ( in_transfer != 0 )\n      {\n\tif ( is_data != 0 )\n\t{\n\t  /* transfer mode is active, but data transfer */\n\t  u8x8_byte_EndTransfer(u8x8); \n\t  /* clear the lowest two bits of the adr */\n\t  u8x8_SetI2CAddress( u8x8, u8x8_GetI2CAddress(u8x8)&0x0fc );\n\t  u8x8_byte_StartTransfer(u8x8); \n\t}\n      }\n      else\n      {\n\t/* clear the lowest two bits of the adr */\n\tu8x8_SetI2CAddress( u8x8, u8x8_GetI2CAddress(u8x8)&0x0fc );\n\tu8x8_byte_StartTransfer(u8x8);\n      }\n      u8x8_byte_SendByte(u8x8, arg_int);\n      in_transfer = 1;\n      break;\n    case U8X8_MSG_CAD_SEND_DATA:\n      if ( in_transfer != 0 )\n      {\n\tif ( is_data == 0 )\n\t{\n\t  /* transfer mode is active, but data transfer */\n\t  u8x8_byte_EndTransfer(u8x8); \n\t  /* clear the lowest two bits of the adr */\n\t  u8x8_SetI2CAddress( u8x8, (u8x8_GetI2CAddress(u8x8)&0x0fc)|2 );\n\t  u8x8_byte_StartTransfer(u8x8); \n\t}\n      }\n      else\n      {\n\t/* clear the lowest two bits of the adr */\n\tu8x8_SetI2CAddress( u8x8, (u8x8_GetI2CAddress(u8x8)&0x0fc)|2 );\n\tu8x8_byte_StartTransfer(u8x8);\n      }\n      in_transfer = 1;\n      \n      p = arg_ptr;\n      while( arg_int > 24 )\n      {\n\tu8x8->byte_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, 24, p);\n\targ_int-=24;\n\tp+=24;\n\tu8x8_byte_EndTransfer(u8x8); \n\tu8x8_byte_StartTransfer(u8x8);\n      }\n      u8x8->byte_cb(u8x8, U8X8_MSG_CAD_SEND_DATA, arg_int, p);\n      \n      break;\n    case U8X8_MSG_CAD_INIT:\n      /* apply default i2c adr if required so that the start transfer msg can use this */\n      if ( u8x8->i2c_address == 255 )\n\tu8x8->i2c_address = 0x070;\n      return u8x8->byte_cb(u8x8, msg, arg_int, arg_ptr);\n    case U8X8_MSG_CAD_START_TRANSFER:\n      in_transfer = 0;    \n      /* actual start is delayed, because we do not whether this is data or cmd transfer */\n      break;\n    case U8X8_MSG_CAD_END_TRANSFER:\n      if ( in_transfer != 0 )\n\tu8x8_byte_EndTransfer(u8x8);\n      in_transfer = 0;\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_capture.c",
    "content": "/*\n\n  u8x8_capture.c\n  \n  Screen capture funcion\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n*/\n\n#include \"u8x8.h\"\n\n/*========================================================*/\n\n\n/* vertical top lsb memory architecture */\nuint8_t u8x8_capture_get_pixel_1(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width)\n{\n  //uint8_t *dest_ptr = capture->buffer;\n  //if ( dest_ptr == NULL )\n    //return 0;\n  //dest_ptr += (y/8)*capture->tile_width*8;\n  dest_ptr += (y/8)*tile_width*8;\n  y &= 7;\n  dest_ptr += x;\n  if ( (*dest_ptr & (1<<y)) == 0 )\n    return 0;\n  return 1;\n}\n\n/* horizontal right lsb memory architecture */\n/* SH1122, LD7032, ST7920, ST7986, LC7981, T6963, SED1330, RA8835, MAX7219, LS0 */ \nuint8_t u8x8_capture_get_pixel_2(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width)\n{\n  //uint8_t *dest_ptr = capture->buffer;\n  //if ( dest_ptr == NULL )\n  //  return 0;\n  //dest_ptr += y*capture->tile_width;\n  y *= tile_width;\n  dest_ptr += y;\n  dest_ptr += x>>3;\n  if ( (*dest_ptr & (128>>(x&7))) == 0 )\n    return 0;\n  return 1;\n}\n\nvoid u8x8_capture_write_pbm_pre(uint8_t tile_width, uint8_t tile_height, void (*out)(const char *s))\n{\n  out(\"P1\\n\");\n  out(u8x8_utoa((uint16_t)tile_width*8));\n  out(\"\\n\");\n  out(u8x8_utoa((uint16_t)tile_height*8));\n  out(\"\\n\");\n}\n\n\nvoid u8x8_capture_write_pbm_buffer(uint8_t *buffer, uint8_t tile_width, uint8_t tile_height, uint8_t (*get_pixel)(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width), void (*out)(const char *s))\n{\n  uint16_t x, y;\n  uint16_t w, h;\n\n  w = tile_width;\n  w *= 8;\n  h = tile_height;\n  h *= 8;\n    \n  for( y = 0; y < h; y++)\n  {\n    for( x = 0; x < w; x++)\n    {\n      if ( get_pixel(x, y, buffer, tile_width) )\n\tout(\"1\");\n      else\n\tout(\"0\"); \t  \n    }\n    out(\"\\n\");\n  }\n}\n\n\n\n\nvoid u8x8_capture_write_xbm_pre(uint8_t tile_width, uint8_t tile_height, void (*out)(const char *s))\n{\n  out(\"#define xbm_width \");\n  out(u8x8_utoa((uint16_t)tile_width*8));\n  out(\"\\n\");\n  out(\"#define xbm_height \");\n  out(u8x8_utoa((uint16_t)tile_height*8));\n  out(\"\\n\");  \n  out(\"static unsigned char xbm_bits[] = {\\n\");  \n}\n\nvoid u8x8_capture_write_xbm_buffer(uint8_t *buffer, uint8_t tile_width, uint8_t tile_height, uint8_t (*get_pixel)(uint16_t x, uint16_t y, uint8_t *dest_ptr, uint8_t tile_width), void (*out)(const char *s))\n{\n  uint16_t x, y;\n  uint16_t w, h;\n  uint8_t v, b;\n  char s[2];\n  s[1] = '\\0';\n\n  w = tile_width;\n  w *= 8;\n  h = tile_height;\n  h *= 8;\n\n  y = 0;\n  for(;;)\n  {\n    x = 0;\n    for(;;)\n    {\n      v = 0;\n      for( b = 0; b < 8; b++ )\n      {\n\tv <<= 1;\n\tif ( get_pixel(x+7-b, y, buffer, tile_width) )\n\t  v |= 1;\n      }\n      out(\"0x\");\n      s[0] = (v>>4);\n      if ( s[0] <= 9 )\n\ts[0] += '0';\n      else\n\ts[0] += 'a'-10;\n      out(s);\n      s[0] = (v&15);\n      if ( s[0] <= 9 )\n\ts[0] += '0';\n      else\n\ts[0] += 'a'-10;\n      out(s);\n      x += 8;\n      if ( x >= w )\n\tbreak;\n      out(\",\");\n    }\n    y++;\n    if ( y >= h )\n      break;\n    out(\",\");\n    out(\"\\n\");\n  }\n  out(\"};\\n\");\n  \n}\n\n\n\n/*========================================================*/\n\n#ifdef NOT_YET_IMPLEMENTED_U8X8_SCREEN_CAPTURE\n\nstruct _u8x8_capture_struct\n{\n  u8x8_msg_cb old_cb;\n  uint8_t *buffer;\t/* tile_width*tile_height*8 bytes */\n  uint8_t tile_width;\n  uint8_t tile_height;\n};\ntypedef struct _u8x8_capture_struct u8x8_capture_t;\n\n\nu8x8_capture_t u8x8_capture;\n\n\nstatic void u8x8_capture_memory_copy(uint8_t *dest, uint8_t *src, uint16_t cnt)\n{\n  while( cnt > 0 )\n  {\n    *dest++ = *src++;\n    cnt--;\n  }\n}\n\nstatic void u8x8_capture_DrawTiles(u8x8_capture_t *capture, uint8_t tx, uint8_t ty, uint8_t tile_cnt, uint8_t *tile_ptr)\n{\n  uint8_t *dest_ptr = capture->buffer;\n  //printf(\"tile pos: %d %d, cnt=%d\\n\", tx, ty, tile_cnt);\n  if ( dest_ptr == NULL )\n    return;\n  dest_ptr += (uint16_t)ty*capture->tile_width*8;\n  dest_ptr += (uint16_t)tx*8;\n  u8x8_capture_memory_copy(dest_ptr, tile_ptr, tile_cnt*8);\n}\n\nuint8_t u8x8_d_capture(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if (  msg ==  U8X8_MSG_DISPLAY_DRAW_TILE )\n  {\n    uint8_t x, y, c;\n    uint8_t *ptr;\n    x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n    y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n    c = ((u8x8_tile_t *)arg_ptr)->cnt;\n    ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n    do\n    {\n      u8x8_capture_DrawTiles(&u8x8_capture, x, y, c, ptr);\n      x += c;\n      arg_int--;\n    } while( arg_int > 0 );\n  }\n  return u8x8_capture.old_cb(u8x8, msg, arg_int, arg_ptr);\n}\n\nuint8_t u8x8_GetCaptureMemoryPixel(u8x8_t *u8x8, uint16_t x, uint16_t y)\n{\n  return u8x8_capture_GetPixel(&u8x8_capture, x, y);\n}\n\n/* memory: tile_width*tile_height*8 bytes */\nvoid u8x8_ConnectCapture(u8x8_t *u8x8, uint8_t tile_width, uint8_t tile_height, uint8_t *memory)\n{\n  if ( u8x8->display_cb == u8x8_d_capture )\n    return;\t/* do nothing, capture already installed */\n\n  u8x8_capture.buffer = memory;\t/* tile_width*tile_height*8 bytes */\n  u8x8_capture.tile_width = tile_width;\n  u8x8_capture.tile_height = tile_height;\n  u8x8_capture.old_cb = u8x8->display_cb;\n  u8x8->display_cb = u8x8_d_capture;\n  return;\n}\n\n#endif"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_a2printer.c",
    "content": "/*\n\n  u8x8_d_a2printer.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  Use DC2 bitmap command of the A2 Micro panel termal printer\n  double stroke\n  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n#define LINE_MIN_DELAY_MS 15\n/* higher values improve quality */\n/* however if the value is too high (>=5) then form feed does not work any more */\n#define LINE_EXTRA_8PIXEL_DELAY_MS 3\n/* this must be a power of two and between 1 and 8 */\n/* best quality only with 1 */\n#define NO_OF_LINES_TO_SEND_WITHOUT_DELAY 1\n\n/* calculates the delay, based on the number of black pixel */\n/* actually only \"none-zero\" bytes are calculated which is, of course not so accurate, but should be good enough */\nuint16_t get_delay_in_milliseconds(uint8_t cnt, uint8_t *data)\n{\n  uint8_t i;\n  uint16_t time = LINE_MIN_DELAY_MS;\n  for ( i = 0; i < cnt; i++ )\n    if ( data[i] != 0 )\n      time += LINE_EXTRA_8PIXEL_DELAY_MS;\n  return time;\n}\n\nuint8_t u8x8_d_a2printer_common(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t c, i, j;\n  uint8_t *ptr;\n  uint16_t delay_in_milliseconds;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      // no setup required\n      // u8x8_cad_SendSequence(u8x8, u8x8_d_a2printer_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      // no powersave \n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      \n      u8x8_cad_SendCmd(u8x8, 27);      /* ESC */\n      u8x8_cad_SendCmd(u8x8, 55 );      /* parameter command */\n      /* increasing the \"max printing dots\" requires a good power supply, but LINE_EXTRA_8PIXEL_DELAY_MS could be reduced then */\n      u8x8_cad_SendCmd(u8x8, 0);      /* Max printing dots,Unit(8dots),Default:7(64 dots) 8*(x+1) ... lower values improve, probably my current supply is not sufficient */\n      u8x8_cad_SendCmd(u8x8, 200);      /* 3-255 Heating time,Unit(10us),Default:80(800us) */\n      u8x8_cad_SendCmd(u8x8, 2);      /* 0-255 Heating interval,Unit(10us),Default:2(20us) ... does not have much influence */\n      \n      //c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      c = u8x8->display_info->tile_width;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n    \n      u8x8_cad_SendCmd(u8x8, 18);      /* DC2 */\n      u8x8_cad_SendCmd(u8x8, 42 );      /* *  */\n      u8x8_cad_SendCmd(u8x8, 8 ); \t/* height */\n      u8x8_cad_SendCmd(u8x8, c ); \t/* c, u8x8->display_info->tile_width */\n      \n      for( j = 0; j < 8 / NO_OF_LINES_TO_SEND_WITHOUT_DELAY; j ++ )\n      {\n\n\tdelay_in_milliseconds = 0;\n\tfor( i = 0; i < NO_OF_LINES_TO_SEND_WITHOUT_DELAY; i++ )\n\t{\n\t  u8x8_cad_SendData(u8x8, c, ptr);\t/* c, note: SendData can not handle more than 255 bytes, send one line of data */\n\t  delay_in_milliseconds += get_delay_in_milliseconds(c, ptr);\n\t  ptr += c;\n\t}\n\t\n\twhile( delay_in_milliseconds > 200 )\n\t{\n\t  u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_MILLI, 200, NULL);\t\n\t  delay_in_milliseconds -= 200;\n\t}\n\tu8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_MILLI, delay_in_milliseconds, NULL);\t\n      }\n\n      /* set parameters back to their default values */\n      u8x8_cad_SendCmd(u8x8, 27);      /* ESC */\n      u8x8_cad_SendCmd(u8x8, 55 );      /* parameter command */\n      u8x8_cad_SendCmd(u8x8, 7);      /* Max printing dots,Unit(8dots),Default:7(64 dots) 8*(x+1)*/\n      u8x8_cad_SendCmd(u8x8, 80);      /* 3-255 Heating time,Unit(10us),Default:80(800us) */\n      u8x8_cad_SendCmd(u8x8, 2);      /* 0-255 Heating interval,Unit(10us),Default:2(20us)*/\n\n      u8x8_cad_EndTransfer(u8x8);\n\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_a2printer_384x240_display_info =\n{\n  /* most of the settings are not required, because this is a serial RS232 printer */\n  \n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* old: sck_takeover_edge, new: active high (bit 1), rising edge (bit 0) */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 48,\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 384,\n  /* pixel_height = */ 240\n};\n\nuint8_t u8x8_d_a2printer_384x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_a2printer_384x240_display_info);\n      break;\n    default:\n      return u8x8_d_a2printer_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n\n  \n\n  "
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_il3820_296x128.c",
    "content": "/*\n\n  u8x8_d_il3820_296x128.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  il3820: 200x300x1\n  \n  command \n    0x22: assign actions\n    0x20: execute actions\n  \n  action for command 0x022 are (more or less guessed)\n    bit 7:\tEnable Clock\n    bit 6:\tEnable Charge Pump\n    bit 5:\tLoad Temparture Value (???)\n    bit 4:\tLoad LUT (???)\n    bit 3:\tInitial Display (???)\n    bit 2:\tPattern Display --> Requires about 945ms with the LUT from below\n    bit 1:\tDisable Charge Pump\n    bit 0:\tDisable Clock\n    \n    Disable Charge Pump and Clock require about 10ms\n    Enable Charge Pump and Clock require about 100 to 300ms\n\n  Notes:\n    - Introduced a refresh display message, which copies RAM to display\n    - Charge pump is always enabled. Charge pump can be enabled/disabled via power save message\n    - U8x8 will not really work because of the two buffers in the SSD1606, however U8g2 should be ok.\n\n  LUT for the 296x128 device (IL3820)\n  LUT (cmd: 0x032 has 30 bytes)\n  section 6.8 of the datasheet mentions 256 bits = 32 bytes for the LUT\n  chapter 7 tells 30 bytes\n\n  according to section 6.8:\n  20 bytes waveform\n  10 bytes timing\n  1 byte named as VSH/VSL\n  1 empty byte\n  according to the command table, the lut has 240 bits (=30 bytes * 8 bits)\n\n\n  LUT / Refresh time\n    total_refresh_time = (refresh_lines + dummy_lines*2)*TGate*TS_Sum/f_OSC\n\n    f_OSC=1MHz (according to the datasheets)\n    refreh_lines = 296 (for the waveshare display, 0x045 cmd)\n    dummy_lines = 22 (for the upcoming u8g2 code, 0x03a cmd)\n    TGate = 62 (POR default, 0x03b cmd)\n    TS_Sum: Sum of all TS entries of the second part of the LUT\n    f_OSC: 1MHz according to the datasheet.\n\n    so we have\n\n    total_refresh_time = 21080*TS_Sum/1000000 = 21ms * TS_Sum\n\n\n  This file includes two devices:\n    u8x8_d_il3820_296x128\t\t--> includes LUT which is probably from the WaveShare 2.9 Vendor\n    u8x8_d_il3820_v2_296x128\t\t--> includes LUT which was optimized for faster speed and lesser flicker\n\n*/\n  \n/* Waveform part of the LUT (20 bytes) */\n/* bit 7/6: 1 - 1 transition */\n/* bit 5/4: 1 - 0 transition */\n/* bit 3/2: 0 - 1 transition */\n/* bit 1/0: 0 - 0 transition */\n/* \t00 – VSS */\n/* \t01 – VSH */\n/* \t10 – VSL */\n/* \t11 – NA */\n  \n\n#include \"u8x8.h\"\n\n/*=================================================*/\n/* common code for all devices */\n\n\nstatic const uint8_t u8x8_d_il3820_296x128_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x22, 0xc0),\t\t\t/* enable clock and charge pump */\n  U8X8_C(0x20),\t\t\t\t/* execute sequence */  \n  U8X8_DLY(200),\t\t\t\t/* according to my measures it may take up to 150ms */\n  U8X8_DLY(100),\t\t\t\t/* but it might take longer */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_il3820_296x128_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  /* disable clock and charge pump only, deep sleep is not entered, because we will loose RAM content */\n  U8X8_CA(0x22, 0x02),\t\t\t/* only disable charge pump, HW reset seems to be required if the clock is disabled */\n  U8X8_C(0x20),\t\t\t\t/* execute sequence */  \n  U8X8_DLY(20),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n// static const uint8_t u8x8_d_il3820_296x128_flip0_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n// static const uint8_t u8x8_d_il3820_296x128_flip1_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n\nstatic const u8x8_display_info_t u8x8_il3820_296x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 120,\n  /* pre_chip_disable_wait_ns = */ 60,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 50,\t\t/* IL3820 */\n  /* sck_pulse_width_ns = */ 125,\t/* IL3820: 125ns, clock cycle = 250ns */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 37,\t\t/* 37*8 = 296 */\n  /* tile_hight = */ 16,\t\t/* 16*8 = 128 */\t\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 296,\n  /* pixel_height = */ 128\n};\n\n\nstatic uint8_t *u8x8_convert_tile_for_il3820(uint8_t *t)\n{\n  uint8_t i;\n  static uint8_t buf[8];\n  uint8_t *pbuf = buf;\n\n  for( i = 0; i < 8; i++ )\n  {\n    *pbuf++ = ~(*t++);\n  }\n  return buf;\n}\n\nstatic void u8x8_d_il3820_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr) U8X8_NOINLINE;\nstatic void u8x8_d_il3820_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr)\n{\n  uint16_t x;\n  uint8_t c, page;\n  uint8_t *ptr;\n  u8x8_cad_StartTransfer(u8x8);\n\n  page = u8x8->display_info->tile_height;\n  page --;\n  page -= (((u8x8_tile_t *)arg_ptr)->y_pos);\n  \n  x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n  x *= 8;\n  x += u8x8->x_offset;\n\n  //u8x8_cad_SendCmd(u8x8, 0x011 );\t/* cursor increment mode */\n  //u8x8_cad_SendArg(u8x8, 7);\n\n  u8x8_cad_SendCmd(u8x8, 0x04f );\t/* set cursor column */\n  u8x8_cad_SendArg(u8x8, x&255);\n  u8x8_cad_SendArg(u8x8, x>>8);\n\n  u8x8_cad_SendCmd(u8x8, 0x04e );\t/* set cursor row */\n  u8x8_cad_SendArg(u8x8, page);\n\n  u8x8_cad_SendCmd(u8x8, 0x024 );\n  \n  do\n  {\n    c = ((u8x8_tile_t *)arg_ptr)->cnt;\n    ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n    do\n    {\n      u8x8_cad_SendData(u8x8, 8, u8x8_convert_tile_for_il3820(ptr));\n      ptr += 8;\n      x += 8;\n      c--;\n    } while( c > 0 );\n    \n    arg_int--;\n  } while( arg_int > 0 );\n  \n  u8x8_cad_EndTransfer(u8x8);\n}\n\n\n\nstatic const uint8_t u8x8_d_il3820_exec_1000dly_seq[] = {\n  // assumes, that the start transfer has happend\n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic void u8x8_d_il3820_first_init(u8x8_t *u8x8)\n{\n      u8x8_ClearDisplay(u8x8);\n  \n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x032);\t\t// program update sequence\n      u8x8_cad_SendMultipleArg(u8x8, 8, 0x055);\t\t// all black\n      u8x8_cad_SendMultipleArg(u8x8, 12, 0x0aa);\t\t// all white\n      u8x8_cad_SendMultipleArg(u8x8, 10, 0x022);\t\t// 830ms\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_exec_1000dly_seq);\n  \n}\n\n#ifdef OBSOLETE\nstatic void u8x8_d_il3820_second_init(u8x8_t *u8x8)\n{\n      u8x8_ClearDisplay(u8x8);\n  \n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x032);\t\t// program update sequence\n      u8x8_cad_SendMultipleArg(u8x8, 20, 0x000);\t\t// do nothing\n      u8x8_cad_SendMultipleArg(u8x8, 10, 0x011);\t\t// 414ms dly\n      /* reuse sequence from above, ok some time is wasted here, */\n      /* delay could be lesser */\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_exec_1000dly_seq);  \n}\n#endif\n\n\n/*=================================================*/\n/* first version, LUT from WaveShare */\n\n\n/* http://www.waveshare.com/wiki/File:2.9inch_e-Paper_Module_code.7z */\nstatic const uint8_t u8x8_d_il3820_296x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x10, 0x00),\t/* Deep Sleep mode Control: Disable */\n  U8X8_C(0x01),\n  U8X8_A(295 % 256), U8X8_A(295/256), U8X8_A(0),\n  \n  \n  U8X8_CA(0x03, 0x00), \t/* Gate Driving voltage: 15V (lowest value)*/\n  U8X8_CA(0x04, 0x0a), \t/* Source Driving voltage: 15V (mid value and POR)*/\n  \n  //U8X8_CA(0x22, 0xc0),\t/* display update seq. option: enable clk, enable CP, .... todo: this is never activated */\n\n  //U8X8_CA(0x0b, 7),\t/* Set Delay of gate and source non overlap period, POR = 7 */\n  U8X8_CA(0x2c, 0xa8),\t/* write vcom value*/\n  U8X8_CA(0x3a, 0x16),\t/* dummy lines POR=22 (0x016) */\n  U8X8_CA(0x3b, 0x08),\t/* gate time POR=0x08*/\n  U8X8_CA(0x3c, 0x33),\t/* select boarder waveform */\n  //U8X8_CA(0x22, 0xc4),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n\n\n  U8X8_CA(0x11, 0x07),\t/* Define data entry mode, x&y inc, x first*/\n\n  U8X8_CAA(0x44, 0, 29),\t/* RAM x start & end, issue 920: end should be (128/8)-1=15. */\n  U8X8_CAAAA(0x45, 0, 0, 295&255, 295>>8),\t/* RAM y start & end */\n  \n  //U8X8_CA(0x4e, 0),\t/* set x pos, 0..29? */\n  //U8X8_CAA(0x4f, 0, 0),\t/* set y pos, 0...320??? */\n\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_il3820_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n/*\n0x50, 0xAA, 0x55, 0xAA, 0x11, \t0x00, 0x00, 0x00, 0x00, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \t0x00, 0x00, 0x00, 0x00, 0x00, \n0xFF, 0xFF, 0x1F, 0x00, 0x00, \t\t0x00, 0x00, 0x00, 0x00, 0x00\nmeasured 1582 ms\n*/\n  U8X8_C(0x32),\t/* write LUT register*/\n  /* original values */\n  U8X8_A(0x50),\n  U8X8_A(0xaa),\n  U8X8_A(0x55),\n  U8X8_A(0xaa),  \n  U8X8_A(0x11),\n  \n  U8X8_A(0x11),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),  \n  U8X8_A(0x00),\n  \n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  /* Timing part of the LUT, 20 Phases with 4 bit each: 10 bytes */\n  U8X8_A(0xff),\n  U8X8_A(0xff),\n  U8X8_A(0x3f),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n\n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: pattern display, assumes clk and charge pump are enabled  */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n  U8X8_DLY(250),\t/* delay for 1620ms. The current sequence takes 1582ms */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(120),\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_il3820_296x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_il3820_296x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_init_seq);    \n\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave0_seq);\n      u8x8_d_il3820_first_init(u8x8);\n\n      /* usually the DISPLAY_INIT message leaves the display in power save state */\n      /* however this is not done for e-paper devices, see: */\n      /* https://github.com/olikraus/u8g2/wiki/internal#powersave-mode */\n    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_il3820_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_to_display_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=================================================*/\n/* second version for the IL3820 display */\n\n\n/* http://www.waveshare.com/wiki/File:2.9inch_e-Paper_Module_code.7z */\nstatic const uint8_t u8x8_d_il3820_v2_296x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  // U8X8_CA(0x10, 0x00),\t/* Deep Sleep mode Control: POR: Normal mode */\n  U8X8_C(0x01),\n  U8X8_A(295 % 256), U8X8_A(295/256), U8X8_A(0),\n  \n  /* the driving voltagesmust not be that high, in order to aviod level change after */\n  /* some seconds (which happens with 0xea */\n  U8X8_CA(0x03, 0x75), \t/* Gate Driving voltage: +/-15V =0x00 POR (+22/-20V) = 0x0ea*/\n  U8X8_CA(0x04, 0x0a), \t/* Source Driving voltage:  (POR=0x0a=15V), max=0x0e*/\n  \n  U8X8_CA(0x0b, 7),\t/* Set Delay of gate and source non overlap period, POR = 7 */\n  U8X8_CA(0x2c, 0xa8),\t/* write vcom value*/\n  U8X8_CA(0x3a, 0x16),\t/* dummy lines POR=22 (0x016) */\n  U8X8_CA(0x3b, 0x08),\t/* gate time POR=0x08*/\n  U8X8_CA(0x3c, 0x33),\t/* select boarder waveform */\n\n  U8X8_CA(0x11, 0x07),\t/* Define data entry mode, x&y inc, x first*/\n  U8X8_CAA(0x44, 0, 29),\t/* RAM x start & end, 32*4=128 */\n  U8X8_CAAAA(0x45, 0, 0, 295&255, 295>>8),\t/* RAM y start & end, 0..295 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_il3820_v2_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n/*\n0xaa, 0x09, 0x09, 0x19, 0x19, \n0x11, 0x11, 0x11, 0x11, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n\n0x75, 0x77, 0x77, 0x77, 0x07, \n0x00, 0x00, 0x00, 0x00, 0x00\nmeasured 1240 ms\n*/\n  U8X8_C(0x32),\t/* write LUT register*/\n  /* https://github.com/olikraus/u8g2/issues/347 */\n  U8X8_A(0xaa),\n  U8X8_A(0x09),\n  U8X8_A(0x09),\n  U8X8_A(0x19),  \n  U8X8_A(0x19),\n  \n  U8X8_A(0x11),\n  U8X8_A(0x11),\n  U8X8_A(0x11),\n  U8X8_A(0x11),  \n  U8X8_A(0x00),\n  \n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  /* Timing part of the LUT, 20 Phases with 4 bit each: 10 bytes */\n  U8X8_A(0x75),\n  U8X8_A(0x77),\n  U8X8_A(0x77),\n  U8X8_A(0x77),\n  U8X8_A(0x07),\n  \n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n  U8X8_DLY(250),\t/* delay for 1400ms. The current sequence takes 1240ms, it was reported, that longer delays are better */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  U8X8_DLY(250),\n  U8X8_DLY(150),\t/* extended, #318 */\n \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_il3820_v2_296x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_il3820_296x128_display_info);\n      break;    \n    case U8X8_MSG_DISPLAY_INIT:\n\n      u8x8_d_helper_display_init(u8x8);\n    \n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_v2_296x128_init_seq);    \n\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave0_seq);\n      u8x8_d_il3820_first_init(u8x8);\n      /* u8x8_d_il3820_second_init(u8x8); */  /* not required, u8g2.begin() will also clear the display once more */\n          \n      /* usually the DISPLAY_INIT message leaves the display in power save state */\n      /* however this is not done for e-paper devices, see: */\n      /* https://github.com/olikraus/u8g2/wiki/internal#powersave-mode */\n    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_il3820_296x128_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_il3820_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_il3820_v2_to_display_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ist3020.c",
    "content": "/*\n\n  u8x8_d_ist3020.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ist3020_erc19264_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a4),\t\t                /* all pixel off, issue 142 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist3020_erc19264_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist3020_erc19264_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist3020_erc19264_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_ist3020_erc19264_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* IST3020 datasheet, page 56 */\n  /* pre_chip_disable_wait_ns = */ 150,\t/* IST3020 datasheet, page 56 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 100,\t\t/* IST3020 datasheet, page 56 */\n  /* sck_pulse_width_ns = */ 100,\t/* IST3020 datasheet, page 56 */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* IST3020 datasheet, page 54 */\n  /* write_pulse_width_ns = */ 60,\t/* IST3020 datasheet, page 54 */\n  /* tile_width = */ 24,\t\t/* width of 24*8=192 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 64,\n  /* pixel_width = */ 192,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_ist3020_erc19264_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ab),            \t\t\t/* build in osc on, used in ER code, but not mentioned in data sheet */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  \n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* FIX: LCD bias 1/7, old value was 1/9 (0x0a2) */\n  \n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x020),\t\t                /* v0 voltage resistor ratio */\n  U8X8_CA(0x081, 0x019),\t\t/* set contrast, contrast value (from ER code: 45) */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ist3020_erc19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ist3020_erc19264_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ist3020_erc19264_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist3020_erc19264_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist3020_erc19264_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist3020_erc19264_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist3020_erc19264_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ist7920.c",
    "content": "/*\n\n  u8x8_d_ist7920.c\n  \n  this is NOT ST7920!\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ist7920_128x128_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x03d),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist7920_128x128_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x03c),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist7920_128x128_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x064),\t\t\t\t/* Display Ctrl: Bit3: SHL 2:ADC 1:EON, 0:REV */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ist7920_128x128_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x068),\t\t\t\t/* Display Ctrl: Bit3: SHL 2:ADC 1:EON, 0:REV */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_ist7920_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 90,\t/* IST7920 datasheet, page 48 */\n  /* pre_chip_disable_wait_ns = */ 90,\t/* IST7920 datasheet, page 48 */\n  /* reset_pulse_width_ms = */ 10,\t\t \n  /* post_reset_wait_ms = */ 20, \t\t/* IST7920 Startup Seq.. */\n  /* sda_setup_time_ns = */ 45,\t\t/* IST7920 datasheet, page 48 */\n  /* sck_pulse_width_ns = */ 130,\t/* IST7920 datasheet, page 48 */\n  /* sck_clock_hz = */ 3000000UL,\t/* IST7920 datasheet: 260ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge (not verified) */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400kHz according to IST7920 datasheet */\n  /* data_setup_time_ns = */ 60,\t/* IST7920 datasheet, page 47 */\n  /* write_pulse_width_ns = */ 150,\t/* IST7920 datasheet, page 47 */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\n/* 1/128 Duty, 1/10 Bias, 128x128 round display */\nstatic const uint8_t u8x8_d_ist7920_128x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x076),\t\t\t\t/* Software Reset */\n  U8X8_DLY(50),\n  U8X8_C(0x03c),\t\t\t\t/* display off */\n  \n  \n  U8X8_CA(0x090, 128),\t\t\t/* Set Duty */\n  //U8X8_CAA(0x0b2, 0x011, 0x00),\t/* Set Frame Control */  \n\n  U8X8_CA(0x030, 16),\t\t\t/* Set Bias 0: 1/8, 8: 1/9, 16: 1/10, 24: 1/11, 48: 1/12 ... */  \n  U8X8_CA(0x031, 0x03f),\t\t/* Set voltage generate clock(31H/11H) */  \n  //U8X8_CA(0x032, 0x015),\t\t/* Temperature compensation */  \n  U8X8_CA(0x033, 0x020),\t\t/* Power Control */\n  U8X8_DLY(100),\n  U8X8_CA(0x033, 0x02c),\t\t/* Power Control */\n  U8X8_DLY(100),\n  U8X8_C(0xfd),\t\t\t\t/* set booster */\n  U8X8_DLY(100),\n  U8X8_CA(0x033, 0x02f),\t\t/* Power Control */\n  U8X8_DLY(200),\n  \n  U8X8_C(0x064),\t\t\t\t/* Display Ctrl: Bit3: SHL 2:ADC 1:EON, 0:REV */\n\n  U8X8_CAA(0x074, 0x000, 0x00f),\t/* AY Window */  \n  U8X8_CAA(0x075, 0x000, 0x07f),\t/* AX Window */  \n  \n  U8X8_CA(0x040, 64),\t\t\t/* Start line at 64 */\n\n  U8X8_CA(0x0b1, 100),\t\t\t/* electronic volume */  \n\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ist7920_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ist7920_128x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ist7920_128x128_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist7920_128x128_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist7920_128x128_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist7920_128x128_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ist7920_128x128_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x0b1 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* st7920 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x0c0 );\n      u8x8_cad_SendArg(u8x8, x );\n      u8x8_cad_SendCmd(u8x8, 0x001 );\n      u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos) );\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ks0108.c",
    "content": "/*\n\n  u8x8_d_ks0108.c \n  \n  The classic 5V LCD\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ks0108_init_seq[] = {\n  U8X8_C(0x0c0),\t\t                /* satart at the top  */  \n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ks0108_powersave0_seq[] = {\n  U8X8_C(0x03f),\t\t                /* display on */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ks0108_powersave1_seq[] = {\n  U8X8_C(0x03e),\t\t                /* display off */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstruct u8x8_ks0108_vars\n{\n  uint8_t *ptr;\n  uint8_t x;\n  uint8_t c;\n  uint8_t arg_int;\n};\n\nstatic void u8x8_ks0108_out(u8x8_t *u8x8, struct u8x8_ks0108_vars *v, void *arg_ptr)\n{\n  uint8_t cnt;\n  u8x8_cad_SendCmd(u8x8, 0x040 | ((v->x << 3) & 63) );\n  u8x8_cad_SendCmd(u8x8, 0x0b8 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n  \n  while( v->arg_int > 0 )\n  {\n      /* calculate tiles to next boundary (end or chip limit) */\n      cnt = v->x;\n      cnt += 8;\n      cnt &= 0x0f8;\n      cnt -= v->x;\n            \n      if ( cnt > v->c )\n\tcnt = v->c;\n    \n      /* of cours we still could use cnt=1 here... */\n      /* but setting cnt to 1 is not very efficient */\n      //cnt = 1;\n    \n      v->x +=cnt;\n      v->c-=cnt;\n      cnt<<=3;\n      u8x8_cad_SendData(u8x8, cnt, v->ptr);\t/* note: SendData can not handle more than 255 bytes */    \n      v->ptr += cnt;\n    \n      if ( v->c == 0 )\n      {\n\tv->ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tv->c = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tv->arg_int--;\n      }\n      if ( ((v->x) & 7) == 0 )\n\tbreak;       \n  } \n}\n\n\nstatic const u8x8_display_info_t u8x8_ks0108_128x64_display_info =\n{\n  /* chip_enable_level = */ 0,\t\t/* KS0108: Not used */\n  /* chip_disable_level = */ 1,\t\t/* KS0108: Not used */\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \t\t/* could be faster for the KS0108 */\n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* KS0108: Not used */\n  /* sck_clock_hz = */ 4000000UL,\t/* KS0108: Not used */\n  /* spi_mode = */ 0,\t\t\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* KS0108: Not used */\n  /* data_setup_time_ns = */ 200,\n  /* write_pulse_width_ns = */ 250,\t/* KS0108: actially 450 ns, but additional 200 ns are added by the byte transfer function */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ks0108_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  struct u8x8_ks0108_vars v;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ks0108_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 2, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      \n      if ( arg_int == 0 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 2, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\t\n      }\n      else\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\t\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 2, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\t\n      }\n      break;\n// The KS0108 can not mirror the cols and rows, use U8g2 for rotation\n//    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n//      break;\n// The KS0108 has no internal contrast command\n//    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n//      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n\n      v.ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      v.x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      v.c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      v.arg_int = arg_int;    \n      \n      \n      if ( v.x < 8 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n\tu8x8_ks0108_out(u8x8, &v, arg_ptr);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n      }\n      if ( v.x < 16 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 2, NULL);\n\tu8x8_ks0108_out(u8x8, &v, arg_ptr);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n      }\n      //if ( v.x < 24 )\n      //{\n\t//u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 4, NULL);\n\t//u8x8_ks0108_out(u8x8, &v, arg_ptr);\n\t//u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n      //}    \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_ks0108_192x64_display_info =\n{\n  /* chip_enable_level = */ 0,\t\t/* KS0108: Not used */\n  /* chip_disable_level = */ 1,\t\t/* KS0108: Not used */\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \t\t/* could be faster for the KS0108 */\n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* KS0108: Not used */\n  /* sck_clock_hz = */ 4000000UL,\t/* KS0108: Not used */\n  /* spi_mode = */ 0,\t\t\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* KS0108: Not used */\n  /* data_setup_time_ns = */ 200,\n  /* write_pulse_width_ns = */ 250,\t/* KS0108: actially 450 ns, but additional 200 ns are added by the byte transfer function */\n  /* tile_width = */ 24,\t\t/* width of 24*8=192 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 192,\n  /* pixel_height = */ 64\n};\n\n\n/* east rising (buydisplay.com) ERM19264 */\n/* left: 011, middle: 101, right: 110, no chip select: 111 */\nuint8_t u8x8_d_ks0108_erm19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  struct u8x8_ks0108_vars v;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ks0108_192x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 3, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 5, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 6, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      \n      if ( arg_int == 0 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 3, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 5, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 6, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\t\n      }\n      else\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 3, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 5, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 6, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ks0108_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n\t\n      }\n      break;\n// The KS0108 can not mirror the cols and rows, use U8g2 for rotation\n//    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n//      break;\n// The KS0108 has no internal contrast command\n//    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n//      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n\n      v.ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      v.x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      v.c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      v.arg_int = arg_int;    \n      \n/*\n    3-bit CS value:\n    In u8x8_byte_set_ks0108_cs(u8x8_t *u8x8, uint8_t arg) the lowest\n    bit is assigned to CS and highest bit if the 3-bit value to CS2\n    \n    CS: left part of the display  --> 6\n    CS1: middle part --> 5\n    CS2: right part of the display --> 3\n\n    Reference: https://github.com/olikraus/u8g2/issues/631\n*/\n      if ( v.x < 8 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 6, NULL);  // 3-->6, issue 631\n\tu8x8_ks0108_out(u8x8, &v, arg_ptr);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n      }\n      if ( v.x < 16 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 5, NULL);\n\tu8x8_ks0108_out(u8x8, &v, arg_ptr);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n      }\n      if ( v.x < 24 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 3, NULL); // 6-->3, // issue 631\n\tu8x8_ks0108_out(u8x8, &v, arg_ptr);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 7, NULL);\n      }    \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_lc7981.c",
    "content": "/*\n\n  u8x8_d_lc7981.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n/* no powersave mode for the LC7981 */\n// static const uint8_t u8x8_d_lc7981_powersave0_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n// static const uint8_t u8x8_d_lc7981_powersave1_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n/* no hardware flip for the LC7981 */\n// static const uint8_t u8x8_d_lc7981_flip0_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n// static const uint8_t u8x8_d_lc7981_flip1_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n\n/* http://graphics.stanford.edu/~seander/bithacks.html */\nstatic uint8_t reverse_byte(uint8_t v)\n{\n  // if ( v != 0 && v != 255 )  does not help much\n  {\n    // swap odd and even bits\n    v = ((v >> 1) & 0x055) | ((v & 0x055) << 1);\n    // swap consecutive pairs\n    v = ((v >> 2) & 0x033) | ((v & 0x033) << 2);\n    // swap nibbles ... \n    v = ((v >> 4) & 0x00F) | ((v & 0x00F) << 4);\n  }\n  return v;\n}\n\nstatic uint8_t u8x8_d_lc7981_common(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t c, i, j;\n  uint16_t y;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y*=8;\n      y*= u8x8->display_info->tile_width;\n      /* x = ((u8x8_tile_t *)arg_ptr)->x_pos; x is ignored... no u8x8 support */\n      u8x8_cad_StartTransfer(u8x8);\n      /* \n\tTile structure is reused here for the t6963, however u8x8 is not supported \n\ttile_ptr points to data which has cnt*8 bytes (same as SSD1306 tiles)\n\tBuffer is expected to have 8 lines of code fitting to the t6963 internal memory\n\t\"cnt\" includes the number of horizontal bytes. width is equal to cnt*8\n\t\n\tx is assumed to be zero\n    \n\tTODO: Consider arg_int, however arg_int is not used by u8g2\n      */\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      for( i = 0; i < 8; i++ )\n      {\n\tu8x8_cad_SendCmd(u8x8, 0x0a );\t/* display ram (cursor) address low byte */\n\tu8x8_cad_SendArg(u8x8, y&255);\n\tu8x8_cad_SendCmd(u8x8, 0x0b );\t/* display ram (cursor) address high byte */\n\tu8x8_cad_SendArg(u8x8, y>>8);\n\t\n\tu8x8_cad_SendCmd(u8x8, 0x0c );\t/* write start */\n\t/*\n\t  The LC7981 has the MSB at the right position, which is exactly the opposite to the T6963.\n\t  Instead of writing a third hvline procedure for this device, we just revert the bytes before \n\t  transmit. This is slow because:\n\t    - the bit reverse itself\n\t    - the single byte transfer \n\t   The one byte is transmitted via SendArg, which is ok, because CAD = 100\n\t*/\n\tfor( j = 0; j < c; j++ )\n\t  u8x8_cad_SendArg(u8x8, reverse_byte(*ptr++));\n\t\n\t//u8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes, send one line of data */\n\t//ptr += u8x8->display_info->tile_width;\n\t\n\ty += u8x8->display_info->tile_width;\n      }\n\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_lc7981_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    /* power save is not there... \n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_powersave1_seq);\n      break;\n    */\n    /* hardware flip not is not available\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n    */\n#ifdef U8X8_WITH_SET_CONTRAST\n    /* no contrast setting :-(\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n  */\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* LC7981 160x80 LCD*/\n\nstatic const u8x8_display_info_t u8x8_lc7981_160x80_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* LC7981 has a low active CS*/\n  /* chip_disable_level = */ 1,\n  \n  /* from here... */\n  /* post_chip_enable_wait_ns = */ 20,\t\n  /* pre_chip_disable_wait_ns = */ 20,\t\n  /* reset_pulse_width_ms = */ 1, \t\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* ... to here, values are ignored, because this is a parallel interface only */\n  \n  /* data_setup_time_ns = */ 220,\t\n  /* write_pulse_width_ns = */ 20,\t\n  /* tile_width = */ 20,\t\t/* width of 20*8=160 pixel */\n  /* tile_hight = */ 10,\n  /* default_x_offset = */ 0,\t\n  /* flipmode_x_offset = */ 0,\t\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 80\n};\n\nstatic const uint8_t u8x8_d_lc7981_160x80_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(50),\n\n  U8X8_CA(0x00, 0x32),\t\t\t/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1) */\n  U8X8_CA(0x01, 0x07),\t\t\t/* character/bits per pixel pitch */\n  U8X8_CA(0x02, 160/8-1),\t\t/* number of chars/byte width of the screen */\n  U8X8_CA(0x03, 0x50),\t\t\t/* time division:  50 (1/80 duty cycle) */\n  U8X8_CA(0x08, 0x00),\t\t\t/* display start low */\n  U8X8_CA(0x09, 0x00),\t\t\t/* display start high */\n\n  U8X8_DLY(10),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_lc7981_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_lc7981_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_lc7981_160x80_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_160x80_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* LC7981 160x160 LCD*/\n\nstatic const u8x8_display_info_t u8x8_lc7981_160x160_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* LC7981 has a low active CS*/\n  /* chip_disable_level = */ 1,\n  \n  /* from here... */\n  /* post_chip_enable_wait_ns = */ 20,\t\n  /* pre_chip_disable_wait_ns = */ 20,\t\n  /* reset_pulse_width_ms = */ 1, \t\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* ... to here, values are ignored, because this is a parallel interface only */\n  \n  /* data_setup_time_ns = */ 220,\t\n  /* write_pulse_width_ns = */ 20,\t\n  /* tile_width = */ 20,\t\t/* width of 20*8=160 pixel */\n  /* tile_hight = */ 20,\n  /* default_x_offset = */ 0,\t\n  /* flipmode_x_offset = */ 0,\t\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 160\n};\n\nstatic const uint8_t u8x8_d_lc7981_160x160_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(50),\n\n  U8X8_CA(0x00, 0x32),\t\t\t/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1) */\n  U8X8_CA(0x01, 0x07),\t\t\t/* character/bits per pixel pitch */\n  U8X8_CA(0x02, 160/8-1),\t\t/* number of chars/byte width of the screen */\n  U8X8_CA(0x03, 159),\t\t\t/* time division */\n  U8X8_CA(0x08, 0x00),\t\t\t/* display start low */\n  U8X8_CA(0x09, 0x00),\t\t\t/* display start high */\n\n  U8X8_DLY(10),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_lc7981_160x160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_lc7981_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_lc7981_160x160_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_160x160_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* LC7981 240x128 LCD*/\n\nstatic const u8x8_display_info_t u8x8_lc7981_240x128_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* LC7981 has a low active CS*/\n  /* chip_disable_level = */ 1,\n  \n  /* from here... */\n  /* post_chip_enable_wait_ns = */ 20,\t\n  /* pre_chip_disable_wait_ns = */ 20,\t\n  /* reset_pulse_width_ms = */ 1, \t\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* ... to here, values are ignored, because this is a parallel interface only */\n  \n  /* data_setup_time_ns = */ 220,\t\n  /* write_pulse_width_ns = */ 20,\t\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\t\n  /* flipmode_x_offset = */ 0,\t\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 128\n};\n\nstatic const uint8_t u8x8_d_lc7981_240x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(50),\n\n  U8X8_CA(0x00, 0x32),\t\t\t/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1) */\n  U8X8_CA(0x01, 0x07),\t\t\t/* character/bits per pixel pitch */\n  U8X8_CA(0x02, 240/8-1),\t\t/* number of chars/byte width of the screen */\n  U8X8_CA(0x03, 0x7f),\t\t\t/* time division */\n  U8X8_CA(0x08, 0x00),\t\t\t/* display start low */\n  U8X8_CA(0x09, 0x00),\t\t\t/* display start high */\n\n  U8X8_DLY(10),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_lc7981_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_lc7981_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_lc7981_240x128_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_240x128_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* LC7981 240x64 LCD*/\n/* https://github.com/olikraus/u8g2/issues/642 */\n\nstatic const u8x8_display_info_t u8x8_lc7981_240x64_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* LC7981 has a low active CS*/\n  /* chip_disable_level = */ 1,\n  \n  /* from here... */\n  /* post_chip_enable_wait_ns = */ 20,\t\n  /* pre_chip_disable_wait_ns = */ 20,\t\n  /* reset_pulse_width_ms = */ 1, \t\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* ... to here, values are ignored, because this is a parallel interface only */\n  \n  /* data_setup_time_ns = */ 220,\t\n  /* write_pulse_width_ns = */ 20,\t\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t\n  /* flipmode_x_offset = */ 0,\t\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_lc7981_240x64_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(50),\n\n  U8X8_CA(0x00, 0x32),\t\t\t/* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1) */\n  U8X8_CA(0x01, 0x07),\t\t\t/* character/bits per pixel pitch */\n  U8X8_CA(0x02, 240/8-1),\t\t/* number of chars/byte width of the screen */\n  U8X8_CA(0x03, 0x7f),\t\t\t/* time division */\n  U8X8_CA(0x08, 0x00),\t\t\t/* display start low */\n  U8X8_CA(0x09, 0x00),\t\t\t/* display start high */\n\n  U8X8_DLY(10),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_lc7981_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_lc7981_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_lc7981_240x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_lc7981_240x64_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ld7032_60x32.c",
    "content": "/*\n\n  u8x8_d_ld7032_60x32.c\n  Note: Flip Mode is NOT supported\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n/* testboard U8GLIB_LD7032_60x32 u8g(11, 12, 9, 10, 8);\t// SPI Com: SCK = 11, MOSI = 12, CS = 9, A0 = 10, RST = 8  (SW SPI Nano Board) */\n/* http://www.seeedstudio.com/document/pdf/0.5OLED%20SPEC.pdf */\n#ifdef OBSOLETE\nstatic const uint8_t u8x8_d_ld7032_60x32_init_seq_old[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  //U8X8_CA(0x002, 0x001),\t\t/* Dot Matrix Display ON */\n  U8X8_CA(0x014, 0x000),\t\t/* Stand-by OFF */\n  U8X8_CA(0x01a, 0x004),\t\t/* Dot Matrix Frame Rate,  special value for this OLED from manual*/\n  U8X8_CA(0x01d, 0x000),\t\t/* Graphics Memory Writing Direction: reset default (right down, horizontal) */\n  U8X8_CA(0x009, 0x000),\t\t/* Display Direction:  reset default (x,y: min --> max) */\n  U8X8_CAA(0x030, 0x000, 0x03b),\t/* Display Size X, Column Start - End*/\n  U8X8_CAA(0x032, 0x000, 0x01f),\t/* Display Size Y, Row Start - End*/\n  U8X8_CA(0x010, 0x000),\t\t/* Peak Pulse Width Set: 0 SCLK */\n  U8X8_CA(0x016, 0x000),\t\t/* Peak Pulse Delay Set: 0 SCLK */\n  U8X8_CA(0x012, 0x040),\t\t/* Dot Matrix Current Level Set: 0x050 * 1 uA = 80 uA */\n  U8X8_CA(0x018, 0x003),\t\t/* Pre-Charge Pulse Width: 3 SCLK */\n  U8X8_CA(0x044, 0x002),\t\t/* Pre-Charge Mode: Every Time */\n  U8X8_CA(0x048, 0x003),\t\t/* Row overlap timing: Pre-Charge + Peak Delay + Peak boot Timing */\n  U8X8_CA(0x03f, 0x011),\t\t/* VCC_R_SEL: ??? */\n  U8X8_CA(0x03d, 0x000),\t\t/* VSS selection: 2.8V */\n  //U8X8_CA(0x002, 0x001),\t\t/* Dot Matrix Display ON */\n  \n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n#endif\n\n/* new sequence https://github.com/olikraus/u8g2/issues/865 */\nstatic const uint8_t u8x8_d_ld7032_60x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x02, 0x00),\t\t  \t\t/* Dot Matrix Display OFF */\n  U8X8_CA(0x14, 0x00),\t\t  \t\t/* Stand-by OFF, OSCA Start */\n  U8X8_CA(0x1a, 0x04),\t\t  \t\t/* Dot Matrix Frame Rate,  special value for this OLED from manual 4 => 120Hz*/\n  U8X8_CA(0x1d, 0x00),\t\t  \t\t/* Graphics Memory Writing Direction: reset default (right down, horizontal) */\n  U8X8_CA(0x09, 0x00),\t      \t\t/* Display Direction:  reset default (x,y: min --> max) */\n  U8X8_CAA(0x30, 0x00, 0x3B),  \t\t/* Display Size X, Column Start - End 0-0x3b(59)*/\n  U8X8_CAA(0x32, 0x00, 0x1F),  \t\t/* Display Size Y, Row Start - End 0-0x1f(31)*/\n  U8X8_CA(0x34, 0x00),\t\t\t\t/* Data Reading/Writing Box X start */\n  U8X8_CA(0x35, 0x07),\t\t\t\t/* Data Reading/Writing Box X end */\n  U8X8_CA(0x36, 0x00),\t\t\t\t/* Data Reading/Writing Box Y start */\n  U8X8_CA(0x37, 0x1F),\t\t\t\t/* Data Reading/Writing Box Y end */\n  U8X8_CA(0x38, 0x00),        \t\t/* Display Start Address X */\n  U8X8_CA(0x39, 0x00),        \t\t/* Display Start Address Y */\n  U8X8_CA(0x10, 0x00),\t\t  \t\t/* Peak Pulse Width Set: 0 SCLK */\n  U8X8_CA(0x16, 0x00),\t\t  \t\t/* Peak Pulse Delay Set: 0 SCLK */\n  U8X8_CA(0x12, 0x40),\t\t  \t\t/* 0x32, 0x50 or 0x40 Dot Matrix Current Level Set: 0x050 * 1 uA = 80 uA */\n  U8X8_CA(0x18, 0x03),\t\t  \t\t/* Pre-Charge Pulse Width: 3 SCLK */\n  U8X8_CA(0x44, 0x02),\t\t  \t\t/* Pre-Charge Mode: Every Time */\n  U8X8_CA(0x48, 0x03),\t\t  \t\t/* Row overlap timing: Pre-Charge + Peak Delay + Peak boot Timing */\n  U8X8_CA(0x17, 0x00),          \t/* Row Scan */\n  U8X8_CA(0x13, 0x00),          \t/* Row Scan Sequence Setting */\n  U8X8_CA(0x1C, 0x00),          \t/* Data Reverse */\n  U8X8_CA(0x3f, 0x11),\t\t  \t\t/* VCC_R_SEL: Internal Regulator enabled(D4=1) and VCC_R=VCC_C*0.7(D0=1) */\n  U8X8_CA(0x3d, 0x00),\t\t  \t\t/* VSS selection: 2.8V */\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ld7032_60x32_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x002, 0x001),\t\t/* Dot Matrix Display ON */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ld7032_60x32_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x002, 0x000),\t\t/* Dot Matrix Display ON */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ld7032_60x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x009, 0x000),\t\t/* Display Direction:  reset default (x,y: min --> max) */  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ld7032_60x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  //U8X8_CA(0x009, 0x002),\t\t/* Display Direction:  reset default (x,y: min --> max) */  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ld7032_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ld7032_60x32_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x012 );\n      if ( arg_int > 0x07f )\t\t\t/* default is 0x040, limit to 0x07f to be on the safe side (hopefully) */\n\targ_int= 0x07f;\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* values from 0x00 to 0x0ff are allowed, bit will all values be safe??? */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x += u8x8->x_offset/8;\n      u8x8_cad_SendCmd(u8x8, 0x034 );\n      u8x8_cad_SendArg(u8x8, x );\n      u8x8_cad_SendCmd(u8x8, 0x035 );\n      u8x8_cad_SendArg(u8x8, 0x007 );\n      u8x8_cad_SendCmd(u8x8, 0x036 );\n      u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos)*8 );\n      u8x8_cad_SendCmd(u8x8, 0x037 );\n      u8x8_cad_SendArg(u8x8, 0x01f );\n      u8x8_cad_SendCmd(u8x8, 0x008 );\n    \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ld7032_60x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 15,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 30,\t\t/* 20ns, but cycle time is 60ns, so use 60/2 */\n  /* sck_pulse_width_ns = */ 30,\t/* 20ns, but cycle time is 60ns, so use 60/2  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 20,\n  /* write_pulse_width_ns = */ 40,\t\n  /* tile_width = */ 8,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 60,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_ld7032_60x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ld7032_60x32_display_info);\n      return 1;\n    }\n    return u8x8_d_ld7032_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n\n/* alternative version, issue #1189 */\n\n/* new sequence https://github.com/olikraus/u8g2/issues/1189 */\nstatic const uint8_t u8x8_d_ld7032_60x32_alt_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x02, 0x00),\t\t  \t\t\n  U8X8_CA(0x14, 0x00),\t\t  \t\t\n  U8X8_CA(0x1A, 0x05),\t\t  \t\t\n  U8X8_CA(0x1D, 0x00),\t\t  \t\n  U8X8_CA(0x09, 0x00),\t      \t\t\n  U8X8_CAA(0x30, 0x00, 0x3F),\n  U8X8_CAA(0x32, 0x08, 0x27),\n  U8X8_CA(0x34, 0x00),\t\t\t\t\n  U8X8_CA(0x35, 0x07),\t\t\n  U8X8_CA(0x36, 0x08),\t\n  U8X8_CA(0x37, 0x27),\t\t\t\n  U8X8_CA(0x38, 0x00),        \n  U8X8_CA(0x39, 0x20),       \n  U8X8_CA(0x10, 0x05),\t\t  \t\n  U8X8_CA(0x16, 0x00),\t\t  \t\n  U8X8_CA(0x18, 0x08),\t\t  \t\t\n  U8X8_CA(0x12, 0x2F),\t\t  \t\n  U8X8_CA(0x3D, 0x01),\t\t  \t\n  U8X8_CA(0x3F, 0x10),\t\t  \t\t\n  U8X8_CA(0x44, 0x02),\t\t  \t\t\n  U8X8_CA(0x48, 0x03),\t\t  \t\n  U8X8_CA(0x17, 0x00),         \n  U8X8_CA(0x13, 0x01),        \n  U8X8_CA(0x3F, 0x11),\n  U8X8_CA(0x3D, 0x00),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */};\n\nuint8_t u8x8_d_ld7032_60x32_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ld7032_60x32_display_info);\n      return 1;\n    }\n\n    if ( msg ==U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ld7032_60x32_alt_init_seq);    \n      return 1;\n    }\n    \n    return u8x8_d_ld7032_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ls013b7dh03.c",
    "content": "/*\n\n  u8x8_d_ls013b7dh03.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  The LS013B7DH02 is a simple display and controller\n  --> no support for contrast adjustment, flip and power down.\n*/\n\n#include \"u8x8.h\"\n\n#define SWAP8(a) ((((a) & 0x80) >> 7) | (((a) & 0x40) >> 5) | (((a) & 0x20) >> 3) | (((a) & 0x10) >> 1) | (((a) & 0x08) << 1) | (((a) & 0x04) << 3) | (((a) & 0x02) << 5) | (((a) & 0x01) << 7))\n\n#define LS013B7DH03_CMD_UPDATE     (0x01)\n#define LS013B7DH03_CMD_ALL_CLEAR  (0x04)\n#define LS013B7DH03_VAL_TRAILER    (0x00)\n\nstatic const u8x8_display_info_t u8x8_ls013b7dh03_128x128_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  /* post_chip_enable_wait_ns = */ 50,\n  /* pre_chip_disable_wait_ns = */ 50,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 227,\t/* 227 nsec according to the datasheet */\t\t\n  /* sck_pulse_width_ns = */  255,\t/* 450 nsec according to the datasheet */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 2,\t\t/* active low, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 100,\n  /* write_pulse_width_ns = */ 100,\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_ls013b7dh03_128x128(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t y, c, i;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ls013b7dh03_128x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n\n      /* clear screen */\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, SWAP8(LS013B7DH03_CMD_ALL_CLEAR) );\n      u8x8_cad_SendCmd(u8x8, LS013B7DH03_VAL_TRAILER);\n      u8x8_cad_EndTransfer(u8x8);\n\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      /* not available for the ls013b7dh03 */\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      /* each tile is 8 lines, with the data starting at the left edge */\n      y = ((((u8x8_tile_t *)arg_ptr)->y_pos) * 8) + 1;\n\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n      /* send data mode byte */\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, SWAP8(LS013B7DH03_CMD_UPDATE) );\n\n      /* send 8 lines of 16 bytes (=128 pixels) */\n      for( i = 0; i < 8; i++ )\n      {\n        u8x8_cad_SendCmd(u8x8, SWAP8(y + i) );\n        u8x8_cad_SendData(u8x8, c, ptr);\n        u8x8_cad_SendCmd(u8x8, LS013B7DH03_VAL_TRAILER);\n\n        ptr += c;\n      }\n\n      /* finish with a trailing byte */\n      u8x8_cad_SendCmd(u8x8, LS013B7DH03_VAL_TRAILER);\n      u8x8_cad_EndTransfer(u8x8);\n\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ls027b7dh01_400x240_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  /* post_chip_enable_wait_ns = */ 50,\n  /* pre_chip_disable_wait_ns = */ 50,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 227,\t/* 227 nsec according to the datasheet */\t\t\n  /* sck_pulse_width_ns = */  255,\t/* 450 nsec according to the datasheet */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 2,\t\t/* active low, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 100,\n  /* write_pulse_width_ns = */ 100,\n  /* tile_width = */ 50,\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 400,\n  /* pixel_height = */ 240\n};\n\nuint8_t u8x8_d_ls027b7dh01_400x240(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ls027b7dh01_400x240_display_info);\n      break;\n    default:\n      return u8x8_d_ls013b7dh03_128x128(u8x8, msg, arg_int, arg_ptr);\n  }    \n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_ls027b7dh01_m0_400x240_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  /* post_chip_enable_wait_ns = */ 50,\n  /* pre_chip_disable_wait_ns = */ 50,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 227,\t/* 227 nsec according to the datasheet */\t\t\n  /* sck_pulse_width_ns = */  255,\t/* 450 nsec according to the datasheet */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active low, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 100,\n  /* write_pulse_width_ns = */ 100,\n  /* tile_width = */ 50,\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 400,\n  /* pixel_height = */ 240\n};\n\nuint8_t u8x8_d_ls027b7dh01_m0_400x240(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ls027b7dh01_m0_400x240_display_info);\n      break;\n    default:\n      return u8x8_d_ls013b7dh03_128x128(u8x8, msg, arg_int, arg_ptr);\n  }    \n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ls013b7dh05_144x168_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  /* post_chip_enable_wait_ns = */ 50,\n  /* pre_chip_disable_wait_ns = */ 50,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 227,\t/* 227 nsec according to the datasheet */\t\t\n  /* sck_pulse_width_ns = */  255,\t/* 450 nsec according to the datasheet */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 2,\t\t/* active low, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 100,\n  /* write_pulse_width_ns = */ 100,\n  /* tile_width = */ 18,\n  /* tile_hight = */ 21,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 144,\n  /* pixel_height = */ 168\n};\n\nuint8_t u8x8_d_ls013b7dh05_144x168(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ls013b7dh05_144x168_display_info);\n      break;\n    default:\n      return u8x8_d_ls013b7dh03_128x128(u8x8, msg, arg_int, arg_ptr);\n  }    \n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_max7219.c",
    "content": "/*\n\n  u8x8_d_max7219.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_max7219_init_seq[] = {\n\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n\n\n  //U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n    \n  //U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_max7219_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_max7219_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_max7219_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t c, j, i;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_pcf8812_96x65_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_max7219_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave1_seq);\n      break;\n    */\n/*  not supported by MAX7219\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      break;\n*/\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      for( i = 0; i < u8x8->display_info->tile_width; i++ )\n      {\n\tu8x8_cad_SendCmd(u8x8, 10 );    /* brightness */\n\tu8x8_cad_SendArg(u8x8, (arg_int>>4) );\t/* 0..15 for contrast */\n      }\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      /* transfer always has to start at x pos 0 (u8x8 is not supported) */\n      /* also y pos has to be 0 */\n      /* arg_int is ignored */\n      //x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      for( i = 0; i < 8; i++ )\n      {\n\tu8x8_cad_StartTransfer(u8x8);\n\tfor( j = 0; j < c; j++ )\n\t{\n\t  u8x8_cad_SendCmd(u8x8, i+1);\t/* commands 1..8 select the byte */\n\t  u8x8_cad_SendArg(u8x8, *ptr );\n\t  ptr++;\n\t}\n\tu8x8_cad_EndTransfer(u8x8);\n      }\n      \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==============================*/\n\nstatic const u8x8_display_info_t u8x8_max7219_32x8_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 4,\n  /* tile_hight = */ 1,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 32,\n  /* pixel_height = */ 8\n};\n\nuint8_t u8x8_d_max7219_32x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY :\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_max7219_32x8_display_info);\n      return 1;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_max7219_init_seq);    \n      return 1;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave1_seq);\n      return 1;\n  }\n  return u8x8_d_max7219_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n/*==============================*/\n\nstatic const u8x8_display_info_t u8x8_max7219_16x16_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 2,\n  /* tile_hight = */ 2,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 16,\n  /* pixel_height = */ 16\n};\n\n/*\n  Multiple page rows are not supported, so 16x16 will not work.\n  Due to the hardware structure of such displays all tiles of the display\n  must be written at once. \n  This is not possible with the current u8g2 structure.\n  So u8x8_d_max7219_16x16 will not work.\n*/\n\nuint8_t u8x8_d_max7219_16x16(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY :\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_max7219_16x16_display_info);\n      return 1;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_max7219_init_seq);    \n      return 1;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave1_seq);\n      return 1;\n  }\n  return u8x8_d_max7219_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n/*==============================*/\n\nstatic const u8x8_display_info_t u8x8_max7219_8x8_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 1,\n  /* tile_hight = */ 1,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 8,\n  /* pixel_height = */ 8\n};\n\nuint8_t u8x8_d_max7219_8x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY :\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_max7219_8x8_display_info);\n      return 1;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_max7219_init_seq);    \n      return 1;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_powersave1_seq);\n      return 1;\n  }\n    return u8x8_d_max7219_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n/*==============================*/\n\nstatic const uint8_t u8x8_d_max7219_8_init_seq[] = {\n\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_CA(15, 0),\t\t\t\t/* test mode off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_CA(12, 0),\t\t\t\t/*  */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_CA(9, 0),\t\t\t\t/* decode mode: graphics */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_CA(10, 10),\t\t\t\t/* medium high intensity */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_CA(11, 7),\t\t\t\t/* scan limit: display all digits (assuming a 8x8 matrix) */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n\n\n  //U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n    \n  //U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_max7219_8_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_CA(12, 1),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_max7219_8_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_CA(12, 0),\t\t\t\t/* shutdown */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_max7219_64x8_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 8,\n  /* tile_hight = */ 1,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 8\n};\n\nuint8_t u8x8_d_max7219_64x8(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY :\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_max7219_64x8_display_info);\n      return 1;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_max7219_8_init_seq);    \n      return 1;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_8_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_max7219_8_powersave1_seq);\n      return 1;\n  }\n  return u8x8_d_max7219_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_pcd8544_84x48.c",
    "content": "/*\n\n  u8x8_d_pcd8544_84x48.c (so called \"Nokia 5110\" displays)\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_pcd8544_84x48_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x021),            \t\t\t/* activate chip (PD=0), horizontal increment (V=0), enter extended command set (H=1) */\n  U8X8_C(0x006),\t\t                /* temp. control: b10 = 2  */\n  U8X8_C(0x013),\t\t                /* bias system 1:48 */\n  U8X8_C(0x0c0),\t\t                /* medium Vop  */\n  \n  U8X8_C(0x020),\t\t                /* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n  U8X8_C(0x008),\t\t\t\t/* blank */\n  U8X8_C(0x024),\t\t                /* power down (PD=1), horizontal increment (V=0), enter normal command set (H=0) */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_pcd8544_84x48_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x020),\t\t                /* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n  U8X8_C(0x00c),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_pcd8544_84x48_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x020),\t\t                /* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n  U8X8_C(0x008),\t\t\t\t/* blank */\n  U8X8_C(0x024),\t\t                /* power down (PD=1), horizontal increment (V=0), enter normal command set (H=0) */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\nstatic const u8x8_display_info_t u8x8_pcd8544_84x48_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 2, \n  /* post_reset_wait_ms = */ 2, \n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 11,\t\t/* width of 11*8=88 pixel */\n  /* tile_hight = */ 6,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 84,\n  /* pixel_height = */ 48\n};\n\nuint8_t u8x8_d_pcd8544_84x48(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_pcd8544_84x48_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_pcd8544_84x48_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcd8544_84x48_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcd8544_84x48_powersave1_seq);\n      break;\n    // case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n    // \t  break; \tNOT SUPPORTED\n      \n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x021 ); /* command mode, extended function set */\n      u8x8_cad_SendCmd(u8x8, 0x080 | (arg_int >> 1) );\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x020 ); /* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n      u8x8_cad_SendCmd(u8x8, 0x080 | (x) );\t/* set X address */\n      u8x8_cad_SendCmd(u8x8, 0x040 | (((u8x8_tile_t *)arg_ptr)->y_pos) );\t/* set Y address */\n    \n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\t\n      do\n      {\n\tif ( c + x > 84u )\n\t{\n\t  if ( x >= 84u )\n\t    break;\n\t  c = 84u;\n\t  c -= x;\n\t}\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\tx += c;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_pcf8812.c",
    "content": "/*\n\n  u8x8_d_pcf8812.c\n  \n  pcf8812: 65x102\n  pcf8814: 65x96\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_pcf8812_96x65_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x020),\t\t                /* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n  U8X8_C(0x008),\t\t                /* blank display */\n  \n  U8X8_C(0x021),\t\t                /* activate chip (PD=0), horizontal increment (V=0), enter extended command set (H=1) */\n  U8X8_C(0x006),\t\t                /* temp. control: b10 = 2 */\n  U8X8_C(0x013),\t\t                /* bias system, 0x010..0x07 1:48 */\n  U8X8_C(0x09f),\t\t\t\t/* contrast setting, 0..127 */\n  //U8X8_CA(0x020 | 2, 0x080 | 0),\t\t\t\t/* contrast setting, pcf8814 */\n\n  U8X8_C(0x024),\t\t                /* deactivate chip (PD=1), horizontal increment (V=0), enter normal command set (H=0) */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_pcf8812_96x65_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x020),\t\t                /* power on */\n  U8X8_C(0x00c),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_pcf8812_96x65_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x020),\t\t                /* power on */\n  U8X8_C(0x008),\t\t                /* blank display */\n  U8X8_C(0x024),\t\t                /* power down */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_pcf8812_96x65_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_pcf8812_96x65_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_pcf8812_96x65_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcf8812_96x65_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcf8812_96x65_powersave1_seq);\n      break;\n/*\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcf8812_96x65_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_pcf8812_96x65_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n*/\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x021 );    /* command mode, extended function set */\n      u8x8_cad_SendArg(u8x8, (arg_int>>1)|0x80 );\t/* 0..127 for contrast */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, 0x020 );\t/* activate chip (PD=0), horizontal increment (V=0), enter normal command set (H=0) */\n      u8x8_cad_SendCmd(u8x8, 0x080 | x);\n      u8x8_cad_SendCmd(u8x8, 0x040 | ((u8x8_tile_t *)arg_ptr)->y_pos);\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_pcf8812_96x65_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 12,\n  /* tile_hight = */ 9,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 65\n};\n\nuint8_t u8x8_d_pcf8812_96x65(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_pcf8812_96x65_display_info);\n      return 1;\n    }\n    return u8x8_d_pcf8812_96x65_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_pcf8814_hx1230.c",
    "content": "/*\n\n  u8x8_d_pcf8814_hc1230.c\n  \n  pcf8814: 65x96\n  hx1230: 68x96\n  \n  pcf8814 and hc1230 are almost identical.\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_hx1230_96x68_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x020),\t\t                /* power off */\n  U8X8_C(0x080),\t\t\t\t/* contrast setting, 0..31, set to 0 */\n  U8X8_C(0x0a6),\t\t                /* not inverted display */\n  U8X8_C(0x0a4),\t\t                /* normal display mode */\n\n  U8X8_C(0x0a0),\t\t                /* */\n  U8X8_C(0x0c0),\t\t                /* */\n  \n  U8X8_C(0x040),\t\t                /* start at scanline 0 */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_hx1230_96x68_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x02f),\t\t                /* power on */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_hx1230_96x68_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),           \t\t/* display off */\n  U8X8_C(0x0a5),\t     \t\t/* All pixels on = powersave */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_hx1230_96x68_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t                /* */\n  U8X8_C(0x0c0),\t\t                /* */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_hx1230_96x68_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t                /* */\n  U8X8_C(0x0c8),\t\t                /* */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_hx1230_96x68_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_hx1230_96x68_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_hx1230_96x68_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_hx1230_96x68_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_hx1230_96x68_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_hx1230_96x68_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_hx1230_96x68_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, (arg_int>>3)|0x80 );\t/* 0..31 for contrast */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, x&15);\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | ((u8x8_tile_t *)arg_ptr)->y_pos);\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_hx1230_96x68_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 100,\n  /* reset_pulse_width_ms = */ 100, \n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 100,\t\n  /* sck_pulse_width_ns = */ 100,\t\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 12,\n  /* tile_hight = */ 9,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 68\n};\n\nuint8_t u8x8_d_hx1230_96x68(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_hx1230_96x68_display_info);\n      return 1;\n    }\n    return u8x8_d_hx1230_96x68_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_s1d15721.c",
    "content": "/*\n\n  u8x8_d_s1d15721.c\n\n  240x64 display\n  https://github.com/olikraus/u8g2/issues/1473  \n  http://datasheet.datasheetarchive.com/originals/library/Datasheets-ISS16/DSAIH000309343.pdf\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n  \n  Copyright (c) 2020, olikraus@gmail.com\n  \n  All rights reserved.\n  \n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n    \n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_s1d15721_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA8),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15721_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA8|1),\t\t                /* display off, enter sleep mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15721_flip0_seq[] = {\n  U8X8_START_TRANSFER(),            /* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA6),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15721_flip1_seq[] = {\n  U8X8_START_TRANSFER(),            /* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA7),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_s1d15721_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x += u8x8->x_offset;\n      x *= 8;\n\n\t  u8x8_cad_SendCmd(u8x8, 0xB1);\t//Page Address - Row\n\t  u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n\n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n\n      u8x8_cad_SendCmd(u8x8, 0x13);\t/* col */\n      u8x8_cad_SendArg(u8x8, x);\n\n\t  u8x8_cad_SendCmd(u8x8, 0x1D );\t//Data Write\n\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\t\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\t\targ_int--;\n      } while( arg_int > 0 );\n\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* s1d15721 240x64 */\n\n\nstatic const u8x8_display_info_t u8x8_s1d15721_240x64_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* low active CS */\n  /* chip_disable_level = */ 1,\n\n  /* post_chip_enable_wait_ns = */ 10,\t/* */\n  /* pre_chip_disable_wait_ns = */ 20,\t        /* */\n  /* reset_pulse_width_ms = */ 1, \t        /* */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/*  */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t         /*  */\n  /* write_pulse_width_ns = */ 65,\t/* */\n  /* tile_width = */ 30,\t\t                /* width of 20*8=160 pixel (30*8 = 240) */\n  /* tile_hight = */ 8,                 /* height 8*8 = 64*/\n  /* default_x_offset = */ 1,\t\n  /* flipmode_x_offset = */ 1,\t\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_s1d15721_240x64_init_seq[] = {\n  U8X8_START_TRANSFER(),           \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0xC4|1),       \t    \t        /* (5) Common Output Status (Reverse) */\n  U8X8_CA(0xA6, 0x01),            \t/* (3) Display Normal Reverse (Normal) */\n  U8X8_CA(0xA4, 0x00), \t           \t/* (4) Display All Light (Normal) */\n  U8X8_CAA(0x6D,0x10,0x02), \t\t/* (18) Duty Set Command */\n  U8X8_CA(0x66, 0x01),           \t/* (15) Display Mode, Parameter 0 (0 = Gray Scale 1 = Binary */\n  U8X8_CA(0x39, 0x36),            \t/* (16) Gray Scale Pattern Set, Pattern */\n  U8X8_CA(0x2B, 0x07),\t\t\t/* (27) LCD Drive Mode Voltage Select, Parameter */\n  U8X8_CA(0x81, 0x0a),\t\t        /* (28) Electronic Volume, Parameter */\n  U8X8_CA(0x5F, 0x00),\t\t        /* (24) Built-in Oscillator Frequency, Parameter  */\n  U8X8_C(0xAA|1),\t\t\t        /* (23) Built-in OSC On */  \n  U8X8_CA(0x25, 0x1f),\t\t        /* (25) Power Control Set, Parameter  */\n  U8X8_CA(0x8A, 0x00),\t\t        /* (6) Start Line Setup, Parameter  */\n  U8X8_CA(0xB1, 0x00),\t\t        /* (7) Page Address Set, Parameter  */\n  U8X8_CA(0x13, 0x00),\t\t        /* (8) Column Address Set  */\n  U8X8_C(0xAE|1),\t\t\t        /* (1) Display ON/OFF */  \n  U8X8_END_TRANSFER(),           /* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_s1d15721_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n\n  /* checking for the flip mode cmd first */\n  if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      return 1;\n  }\n  /* call the common procedure, this now leads to the effect, that the flip code is executed again */\n  /* maybe we should paste the common code here to avoid this */\n\n\n  if ( u8x8_d_s1d15721_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_s1d15721_240x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15721_240x64_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_s1d15e06.c",
    "content": "/*\n\n  u8x8_d_s1d15e06.c\n  \n  https://github.com/olikraus/u8g2/pull/1190\n  https://github.com/olikraus/u8g2/issues/1172\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n  \n  Copyright (c) 2020, olikraus@gmail.com\n  \n  All rights reserved.\n  \n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n    \n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_s1d15e06_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA8),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15e06_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA8|1),\t\t                /* display off, enter sleep mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15e06_flip0_seq[] = {\n  U8X8_START_TRANSFER(),            /* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA6),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_s1d15e06_flip1_seq[] = {\n  U8X8_START_TRANSFER(),            /* enable chip, delay is part of the transfer start */\n  U8X8_C(0xA7),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_s1d15e06_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n\n\t  u8x8_cad_SendCmd(u8x8, 0xB1);\t//Page Address - Row\n\t  u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n\n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y += u8x8->x_offset;\n\n      u8x8_cad_SendCmd(u8x8, 0x13);\t/* col */\n      u8x8_cad_SendArg(u8x8, x);\n\n\t  u8x8_cad_SendCmd(u8x8, 0x1D );\t//Data Write\n\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\t\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\t\targ_int--;\n      } while( arg_int > 0 );\n\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* s1d15e06 160x100 */\n\n\nstatic const u8x8_display_info_t u8x8_s1d15e06_160100_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* s1d15e06 has low active CS */\n  /* chip_disable_level = */ 1,\n\n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1608 datasheet, page 39, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* uc1608 datasheet, page 39 */\n  /* reset_pulse_width_ms = */ 1, \t/* uc1608 datasheet, page 42 */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* uc1608 datasheet, page 41 */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1608 datasheet, page 39 */\n  /* write_pulse_width_ns = */ 65,\t/* uc1608 datasheet, page 39 */\n  /* tile_width = */ 20,\t\t/* width of 20*8=160 pixel */\n  /* tile_hight = */ 13,\n  /* default_x_offset = */ 0,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 0,\t/* reused as y page offset */\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 100\n};\n\nstatic const uint8_t u8x8_d_s1d15e06_160100_init_seq[] = {\n\n  U8X8_START_TRANSFER(),           \t/* enable chip, delay is part of the transfer start */\n\n\t\t\t\t\t\t\t\t\t/* (Command no in datasheet) Description */\n  U8X8_C(0xA0|1),           \t\t/* (12) Column Address Direction (Reverse) */\n\n  U8X8_C(0xC4|1),       \t    \t/* (5) Common Output Status (Reverse) */\n  U8X8_C(0x84),            \t\t\t/* (11) Display Data In. Direction (Normal) */\n\n  U8X8_C(0xA6),            \t\t\t/* (3) Display Normal Reverse (Normal) */\n  U8X8_C(0xA4), \t           \t\t/* (4) Display All Light (Normal) */\n\n\n  U8X8_CAA(0x6D,0x18,0x04), \t\t/* (18) Duty Set Command, \n\t\t\t\t\t\t\t\t\t\tParameter \"Duty Set\" 1/96 ,\n\t\t\t\t\t\t\t\t\t\tParameter \"Start Point Set\" */\n\n  U8X8_CA(0x66, 0x01),           \t/* (15) Display Mode, Parameter 0 (4 Gray Scale) 1 (Binary) */\n  U8X8_CA(0x39, 0x43),            \t/* (16) Gray Scale Pattern Set, Pattern */\n  U8X8_C(0xBE|1),          \t  \t\t/* (2) Display Off Mode (0 VSS / 1 Vcc) */\n\n  U8X8_CA(0x2B, 0x03),\t\t\t\t/* (27) LCD Drive Mode Voltage Select, Parameter */\n\n  U8X8_CA(0x81, 0x32),\t\t        /* (28) Electronic Volume, Parameter */\n  U8X8_C(0xE4|1),\t\t\t        /* (14) N-Line On Off (On) */  \n  U8X8_CA(0x36, 0x05),\t\t        /* (13) N-Line Inversion Drive, Parameter (6x4)  */\n\n  U8X8_CA(0x41, 0x03),\t\t        /* (13) (26) Step-up CK Frequency Select, fosc/8  */\n  U8X8_CA(0x5F, 0x04),\t\t        /* (24) Built-in Oscillator Frequency, Parameter  */\n  U8X8_C(0xAA|1),\t\t\t        /* (23) Built-in OSC On */  \n\n  U8X8_CA(0x25, 0x1F),\t\t        /* (25) Power Control Set, Parameter  */\n\n  U8X8_CA(0x8A, 0x00),\t\t        /* (6) Start Line Setup, Parameter  */\n  U8X8_CA(0xB1, 0x00),\t\t        /* (7) Page Address Set, Parameter  */\n  U8X8_CA(0x13, 0x00),\t\t        /* (8) Column Address Set  */\n\n  U8X8_C(0xAE|1),\t\t\t        /* (1) Display ON/OFF */  \n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_s1d15e06_160100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n\n  /* checking for the flip mode cmd first */\n  if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      return 1;\n  }\n  /* call the common procedure, this now leads to the effect, that the flip code is executed again */\n  /* maybe we should paste the common code here to avoid this */\n\n\n  if ( u8x8_d_s1d15e06_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_s1d15e06_160100_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_s1d15e06_160100_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sbn1661.c",
    "content": "/*\n\n  u8x8_d_sbn1661.c \n  \n  SED1520 / SBN1661 122x32 5V LCD\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_sbn1661_init_seq[] = {\n  U8X8_C(0x0c0),\t\t                /* display start at line 0  */  \n  U8X8_C(0x0a0),\t\t                /* a0: ADC forward, a1: ADC reverse */  \n  U8X8_C(0x0a4),\t\t                /* a4: normal driving, a5: power save */  \n  U8X8_C(0x0a9),\t\t                /* a8: 1/16, a9: 1/32 duty */  \n\n  //U8X8_C(0x0af),\t\t\t\t/* display on */\n  \n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sbn1661_powersave0_seq[] = {\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sbn1661_powersave1_seq[] = {\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstruct u8x8_sbn1661_vars\n{\n  uint8_t *ptr;\n  uint8_t x;\n  uint8_t c;\n  uint8_t arg_int;\n};\n\n#ifdef NOT_USED\nstatic void u8x8_sbn1661_out(u8x8_t *u8x8, struct u8x8_sbn1661_vars *v, void *arg_ptr)\n{\n  uint8_t cnt;\n  u8x8_cad_SendCmd(u8x8, 0x000 | ((v->x << 3) & 63) );\n  u8x8_cad_SendCmd(u8x8, 0x0b8 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n  \n  while( v->arg_int > 0 )\n  {\n      /* calculate tiles to next boundary (end or chip limit) */\n      cnt = v->x;\n      cnt += 8;\n      cnt &= 0x0f8;\n      cnt -= v->x;\n            \n      if ( cnt > v->c )\n\tcnt = v->c;\n    \n      /* of course we still could use cnt=1 here... */\n      /* but setting cnt to 1 is not very efficient */\n      //cnt = 1;\n    \n      v->x +=cnt;\n      v->c-=cnt;\n      cnt<<=3;\n      u8x8_cad_SendData(u8x8, cnt, v->ptr);\t/* note: SendData can not handle more than 255 bytes */    \n      v->ptr += cnt;\n    \n      if ( v->c == 0 )\n      {\n\tv->ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tv->c = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tv->arg_int--;\n      }\n      if ( ((v->x) & 7) == 0 )\n\tbreak;       \n  } \n}\n#endif /* NOT_USED */\n\n\nstatic const u8x8_display_info_t u8x8_sbn1661_122x32_display_info =\n{\n  /* chip_enable_level = */ 0,\t\t/* sbn1661: Not used */\n  /* chip_disable_level = */ 1,\t\t/* sbn1661: Not used */\n  \n  /* post_chip_enable_wait_ns = */ 100,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \t\t/*  */\n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* sbn1661: Not used */\n  /* sck_clock_hz = */ 4000000UL,\t/* sbn1661: Not used */\n  /* spi_mode = */ 0,\t\t\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* sbn1661: Not used */\n  /* data_setup_time_ns = */ 200,\n  /* write_pulse_width_ns = */ 200,\t/*  */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 122,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_sbn1661_122x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t *ptr;\n  //uint8_t x;\n  //uint8_t c;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sbn1661_122x32_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 0, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_init_seq);\n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 1, NULL);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      \n      if ( arg_int == 0 )\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 0, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_powersave0_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 1, NULL);\t\n      }\n      else\n      {\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 0, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\t\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sbn1661_powersave1_seq);\n\tu8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 1, NULL);\n\t\n      }\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      // x and c are ignored (u8g2 only)\n      //x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      //c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 0, NULL);\n      u8x8_cad_SendCmd(u8x8, 0x000 | 0);\t\t// column 0\n      u8x8_cad_SendCmd(u8x8, 0x0b8 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      u8x8_cad_SendData(u8x8, 61, ptr);\t/* note: SendData can not handle more than 255 bytes */    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 0, NULL);\n\n      ptr += 61;\n      \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_START_TRANSFER, 1, NULL);\n      u8x8_cad_SendCmd(u8x8, 0x000 | 0);\t\t// column 0\n      u8x8_cad_SendCmd(u8x8, 0x0b8 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      u8x8_cad_SendData(u8x8, 61, ptr);\t/* note: SendData can not handle more than 255 bytes */    \n      u8x8->cad_cb(u8x8, U8X8_MSG_CAD_END_TRANSFER, 1, NULL);\n    \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_sed1520_122x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_d_sbn1661_122x32(u8x8, msg, arg_int, arg_ptr);\n\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sed1330.c",
    "content": "/*\n\n  u8x8_d_sed1330.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  The device might also work with the RA8835, SED1335 and SED1336 controller.\n  The following devices might be compatible:\n    RA8835\n    SED1330\n    SED1335\n    S1D13700\n\n\n*/\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_sed1330_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x040, 0x030),\t\t/* sys init (0x040) with one arg, where 0x030 is a wild guess */\n  U8X8_CA(0x059, 0x004),               /* send display on command (hex 0x059, see p37 ) */\n\t\t\t\t\t\t\t/* display cmd has one arg: 01010100 should enable all three blocks, but disable the cursor*/\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sed1330_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x058, 0x000),               /* send display off command (hex 0x059, see p37) and turn of all banks */\n  /* maybe send a sleep in cmd */\n  //U8X8_C(0x053)\t\t\t\t/* sleep in: 0x053 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_sed1330_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t c, i;\n  uint16_t y;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sed1330_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sed1330_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y*=8;\n      y*= u8x8->display_info->tile_width;\n    \n      u8x8_cad_StartTransfer(u8x8);\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      for( i = 0; i < 8; i++ )\n      {\n\tu8x8_cad_SendCmd(u8x8, 0x046 );\t/* CSRW command*/\n\tu8x8_cad_SendArg(u8x8, y&255);\t\t/* CSRW low adr byte */\n\tu8x8_cad_SendArg(u8x8, y>>8);\t\t/* CSRW high adr byte */\n\tu8x8_cad_SendCmd(u8x8, 0x042 );\t/* MWRITE */\n\t\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes, send one line of data */\n\t\n\tptr += u8x8->display_info->tile_width;\n\ty += u8x8->display_info->tile_width;\n      }\n\n      /* sometimes the display switches off... so just sent a display on command */\n      u8x8_cad_SendCmd(u8x8, 0x059 );\t/* display on */\n      u8x8_cad_SendArg(u8x8, 0x004);\t/* arg for display on */\n\n      u8x8_cad_EndTransfer(u8x8);\n      //u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=============================================*/\n\n\nstatic const u8x8_display_info_t u8x8_sed1330_240x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 30,\t/* G242CX Datasheet p5 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* G242CX Datasheet p5 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 120,\t\t/* G242CX Datasheet p5 */\n  /* write_pulse_width_ns = */ 220,\t\t/* G242CX Datasheet p5 */\n  /* tile_width = */ 0x01e,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 128\n};\n\n/* 240x128 Seiko G242C */\nstatic const uint8_t u8x8_d_sed1330_240x128_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n\n  /* system init command, see also u8x8_d_sed1330_powersave0_seq */\n  U8X8_CA(0x040, 0x030),\t\t/* sys init (0x040) with one arg, where 0x030 is a wild guess */\n  /* system init has total 8 parameters, so 7 more are here */\n  U8X8_A(0x087),\t\t\t\t/* no idea here... WF (topmost bit) is set to one because it is suggested in the datasheet, lowest 3 bits refer to text mode only */\n  U8X8_A(0x007),\t\t\t\t/* FY: height of a char+1, does not matter here (hopefully), because we use graphics mode only */\n  U8X8_A(0x01d),\t\t\t\t/* C/R: this could be the number of horizontal bytes - 1 (Value confirmed with app notes p41) */\n  U8X8_A(0x050),\t\t\t\t\t/* TC/R: According to app notes fOSC=6Mhz fFF=70Hz --> TC/R = 74d*/\n  U8X8_A(0x080),\t\t\t\t/* L/F: Lines per frame - 1, probably this is the height of the display - 1 (value confirmed with app notes p41)*/\n  U8X8_A(0x01e),\t\t\t\t/* Low byte of the virtual screen size. (Value confirmed with app notes p41)   */\n  U8X8_A(0),\t\t\t\t\t/* High byte of the virtual screen size, see also section 9.1.2 */\n\t\n  U8X8_C(0x044),\t\t\t\t/* SCROLL */\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x080),\n  U8X8_A(0x000),\n  U8X8_A(0x040),\n  U8X8_A(0x080),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n\t\n  U8X8_CA(0x05a, 0),\t\t\t/* HDOT SCR: Horizontal dotwise scroll... set to 0 */\n\t\n  U8X8_CA(0x05b, 0x0c),\t\t\t/* OVLAY: 2-layer, all graphics, OR between layer 1 and 2 */\n\n\n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\n/* RA8835 NHD-240128BZ */\nstatic const uint8_t u8x8_d_rh8835_nhd_240128_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n\n  /* system init command, see also u8x8_d_sed1330_powersave0_seq */\n  U8X8_CA(0x040, 0x030),\t\t/* sys init (0x040) with one arg, where 0x030 is a wild guess */\n  /* system init has total 8 parameters, so 7 more are here */\n  U8X8_A(0x087),\t\t\t\t/* no idea here... WF (topmost bit) is set to one because it is suggested in the datasheet, lowest 3 bits refer to text mode only */\n  U8X8_A(0x007),\t\t\t\t/* FY: height of a char+1, does not matter here (hopefully), because we use graphics mode only */\n  U8X8_A(0x01d),\t\t\t\t/* C/R: this could be the number of horizontal bytes - 1 (Value confirmed with app notes p41) */\n  U8X8_A(0x050),\t\t\t\t\t/* TC/R: According to app notes fOSC=6Mhz fFF=70Hz --> TC/R = 74d*/\n  U8X8_A(0x080),\t\t\t\t/* L/F: Lines per frame - 1, probably this is the height of the display - 1 (value confirmed with app notes p41)*/\n  U8X8_A(0x01e),\t\t\t\t/* Low byte of the virtual screen size. (Value confirmed with app notes p41)   */\n  U8X8_A(0),\t\t\t\t\t/* High byte of the virtual screen size, see also section 9.1.2 */\n\n  U8X8_C(0x044),\t\t\t\t/* SCROLL */\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x080),\n  U8X8_A(0x000),\n  U8X8_A(0x040),\n  U8X8_A(0x080),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n\t\n  //U8X8_CA(0x05a, 0),\t\t\t/* HDOT SCR: Horizontal dotwise scroll... set to 0 */\n\t\n  U8X8_CA(0x05b, 0x0c),\t\t\t/* OVLAY: 2-layer, all graphics, OR between layer 1 and 2 */\n\n  //U8X8_CA(0x059, 0x04),               /* send display on command (hex 0x059, see p37 ) */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n  \n};\n\n\nuint8_t u8x8_d_sed1330_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sed1330_240x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sed1330_240x128_init_seq);\n      break;\n    default:\n      return u8x8_d_sed1330_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\nuint8_t u8x8_d_ra8835_nhd_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sed1330_240x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_rh8835_nhd_240128_init_seq);\n      break;\n    default:\n      return u8x8_d_sed1330_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n\n/*=============================================*/\n\n\nstatic const u8x8_display_info_t u8x8_sed1330_320x240_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 30,\t/* G242CX Datasheet p5 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* G242CX Datasheet p5 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 120,\t\t/* G242CX Datasheet p5 */\n  /* write_pulse_width_ns = */ 220,\t\t/* G242CX Datasheet p5 */\n  /* tile_width = */ 40,\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 320,\n  /* pixel_height = */ 240\n};\n\nstatic const uint8_t u8x8_d_sed1330_320x240_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n\n  /* system init command, see also u8x8_d_sed1330_powersave0_seq */\n  U8X8_CA(0x040, 0x030),\t\t/* sys init (0x040) with one arg, where 0x030 is a wild guess */\n  /* system init has total 8 parameters, so 7 more are here */\n  U8X8_A(0x087),\t\t\t\t/* no idea here... WF (topmost bit) is set to one because it is suggested in the datasheet, lowest 3 bits refer to text mode only */\n  U8X8_A(0x007),\t\t\t\t/* FY: height of a char+1, does not matter here (hopefully), because we use graphics mode only */\n  U8X8_A(0x027),\t/* 40-1 */\t\t/* C/R: this could be the number of horizontal bytes - 1 (Value confirmed with app notes p41) */\n  U8X8_A(0x039),\t\t\t\t\t/* TC/R: According to app notes fOSC=6Mhz fFF=70Hz --> TC/R = 74d*/\n  U8X8_A(0x0ef),\t\t\t\t/* L/F: Lines per frame - 1, probably this is the height of the display - 1 (value confirmed with app notes p41)*/\n  U8X8_A(0x028),\t\t\t\t/* Low byte of the virtual screen size. (Value confirmed with app notes p41)   */\n  U8X8_A(0),\t\t\t\t\t/* High byte of the virtual screen size, see also section 9.1.2 */\n\t\n  U8X8_C(0x044),\t\t\t\t/* SCROLL */\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x000),\t\t\t\t\n  U8X8_A(0x0ef),\n  U8X8_A(0x0b0),\n  U8X8_A(0x004),\n  U8X8_A(0x0ef),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n\t\n  U8X8_CA(0x05a, 0),\t\t\t/* HDOT SCR: Horizontal dotwise scroll... set to 0 */\n\t\n  U8X8_CA(0x05b, 0x0c),\t\t\t/* OVLAY: 2-layer, all graphics, OR between layer 1 and 2 */\n\n\n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\n\n\nuint8_t u8x8_d_ra8835_320x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sed1330_320x240_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sed1330_320x240_init_seq);\n      break;\n    default:\n      return u8x8_d_sed1330_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sh1106_64x32.c",
    "content": "/*\n\n  u8x8_d_sh1106_64x32.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* issue 568 */\nstatic const uint8_t u8x8_d_sh1106_64x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x01f),\t\t/* multiplex ratio, 0.42 OLED */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset, 0.42 OLED  */\n  U8X8_C(0x040),\t\t                /* set display start line to 0, 0.42 OLED */\n  U8X8_CA(0xad, 0x8b),      \t \t/* DC-DC ON/OFF Mode Set: Built-in DC-DC is used, Normal Display (POR = 0x8b) */\n  U8X8_C(0x33),\t\t\t\t/* set charge pump voltage 0x30 (POR) .. 0x33 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1, 0.66 OLED  */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse, 0.66 OLED  */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.66 OLED */\n  U8X8_CA(0x081, 0x080),\t\t/* [2] set contrast control, 0.42 OLED datasheet: 0xcf */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1, 0.42 OLED datasheet: 0x22 */\n  U8X8_CA(0x0db, 0x028),\t\t/* vcomh deselect level, 0.42 OLED datasheet: 0x00 */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_64x32_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_64x32_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_64x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_CA(0x0d3, 0),\t\t\t/* display offset, 0.42 OLED  */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_64x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_CA(0x0d3, 0),\t\t/* What is the correct offset in flip 1 mode?  --> Issue 547 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_sh1106_64x32_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_64x32_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n        u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_powersave0_seq);\n      else\n        u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_flip0_seq);\n        u8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_flip1_seq);\n        u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* copied from SSD1306 */\nstatic const u8x8_display_info_t u8x8_sh1106_64x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 8,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 32,\n  /* flipmode_x_offset = */ 36,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_sh1106_64x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_64x32_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_64x32_init_seq);    \n      return 1;\n    }\n    return u8x8_d_sh1106_64x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sh1106_72x40.c",
    "content": "/*\n\n  u8x8_d_sh1106_72x40.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* WiseChip 0.42 OLED, issue 547 */\nstatic const uint8_t u8x8_d_sh1106_72x40_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x027),\t\t/* multiplex ratio, 0.42 OLED */\n  U8X8_CA(0x0d3, 0x00c),\t\t/* display offset, 0.42 OLED  */\n  U8X8_C(0x040),\t\t                /* set display start line to 0, 0.42 OLED */\n  U8X8_CA(0xad, 0x8b),      \t \t/* DC-DC ON/OFF Mode Set: Built-in DC-DC is used, Normal Display (POR = 0x8b) */\n  U8X8_C(0x33),\t\t\t\t/* set charge pump voltage 0x30 (POR) .. 0x33 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1, 0.66 OLED  */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse, 0.66 OLED  */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.66 OLED */\n  U8X8_CA(0x081, 0x080),\t\t/* [2] set contrast control, 0.42 OLED datasheet: 0xcf */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1, 0.42 OLED datasheet: 0x22 */\n  U8X8_CA(0x0db, 0x028),\t\t/* vcomh deselect level, 0.42 OLED datasheet: 0x00 */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_72x40_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_72x40_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_72x40_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_CA(0x0d3, 12),\t\t\t/* display offset, 0.42 OLED  */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1106_72x40_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_CA(0x0d3, 52),\t\t/* What is the correct offset in flip 1 mode?  --> Issue 547 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_sh1106_72x40_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_72x40_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* copied from SSD1306 */\nstatic const u8x8_display_info_t u8x8_sh1106_72x40_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 9,\n  /* tile_hight = */ 5,\n  /* default_x_offset = */ 30,\n  /* flipmode_x_offset = */ 30,\n  /* pixel_width = */ 72,\n  /* pixel_height = */ 40\n};\n\n/* WiseChip 0.42\" OLED */\nuint8_t u8x8_d_sh1106_72x40_wise(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_72x40_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_72x40_init_seq);    \n      return 1;\n    }\n    return u8x8_d_sh1106_72x40_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sh1107.c",
    "content": "/*\n\n  u8x8_d_sh1107.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n/* code copyied from SSD1306 */\n\n\n\nstatic const uint8_t u8x8_d_sh1107_64x128_noname_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1107_64x128_noname_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1107_64x128_noname_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1107_64x128_noname_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_sh1107_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1107_64x128_noname_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* sh1107 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n\n      //u8x8_cad_SendCmd(u8x8, 0x040 ); /* set line offset to 0 */\n\n      // set column address\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4));\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x & 15))); /* probably wrong, should be SendCmd */\n      \n      // set page address\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos)); /* probably wrong, should be SendCmd */\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n\n/* QG-6428TSWKG01 */\nstatic const uint8_t u8x8_d_sh1107_64x128_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0dc, 0x000),\t\t/* start line */\n  U8X8_CA(0x081, 0x02f), \t\t/* [2] set contrast control */\n  U8X8_C(0x020),\t\t                /* addressing mode */\n\n  // U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0a8, 0x7f),\t\t/* 0x03f) multiplex ratio */\n  U8X8_CA(0x0d3, 0x060),\t\t/* display offset */\n  U8X8_CA(0x0d5, 0x051),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0d9, 0x022), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x035), \t\t/* vcomh deselect level */  \n  \n  U8X8_C(0x0b0), /* set page address */\n  U8X8_CA(0x0da, 0x012), /* set com pins */\n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_sh1107_64x128_noname_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* sh1107: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* sh1107: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* sh1107: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1107: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 8,\n  /* tile_height = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_sh1107_64x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1107_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_64x128_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1107_64x128_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n\n/* init sequence from Grove OLED 96x96 */\nstatic const uint8_t u8x8_d_sh1107_seeed_96x96_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x050),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x5) */\n  U8X8_C(0x020),\t\t                /* use page addressing mode */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_CA(0x0dc, 0x000),\t\t/* start line */\n  //U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  //U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x080), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0ad, 0x080), \t\t/* */  \n  U8X8_CA(0x0d9, 0x01f), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x027), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  //U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_sh1107_seeed_96x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 100,\t\t/* cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 100,\t/* cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1107: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 12,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 96\n};\n\nuint8_t u8x8_d_sh1107_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1107_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_seeed_96x96_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1107_seeed_96x96_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*==================================================*/\n/* 128x128 OLED: this display has a very strange x offset */\n\n/* sequence taken over from 64x128 sequence, because it seems to work mostly */\nstatic const uint8_t u8x8_d_sh1107_128x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0dc, 0x000),\t\t/* start line */\n  U8X8_CA(0x081, 0x02f), \t\t/* [2] set contrast control */\n  U8X8_C(0x020),\t\t                /* use page addressing mode */\n\n  // U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0a8, 0x7f),\t\t/* 0x03f multiplex ratio */\n  //U8X8_CA(0x0d3, 0x060),\t\t/* display offset (removed, not in datasheet ) */\n  U8X8_CA(0x0d5, 0x050),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8), changed to 0x051, issue 501 */\n  U8X8_CA(0x0d9, 0x022), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x035), \t\t/* vcomh deselect level */  \n  \n  U8X8_C(0x0b0), /* set page address */\n  U8X8_CA(0x0da, 0x012), /* set com pins */\n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_sh1107_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 100,\t\t/* cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 100,\t/* cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1107: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 96,\n  /* flipmode_x_offset = */ 96,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_sh1107_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1107_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_128x128_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1107_128x128_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n/* pimoroni_128x128_display */\n\nstatic const u8x8_display_info_t u8x8_sh1107_pimoroni_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 100,\t\t/* cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 100,\t/* cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1107: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_sh1107_pimoroni_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1107_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_128x128_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1107_pimoroni_128x128_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n/*\nName: \tSH1107_seeed_128x128\nURL: \thttps://www.seeedstudio.com/Grove-OLED-Display-1-12-V2.html \nDisplay is there in my lab. Backside PCB label: \"OLED Display 1.12 inch v1.0\"\nTookover code from SSD1327_SEEED_96X96 because none of the other displays did work\nand at least the 96x96 driver did show something.\n*/\n\nstatic const u8x8_display_info_t u8x8_seeed_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 100,\t\t/* cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 100,\t/* cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 2,\t\t// 400kHz does not work, but 200kHz seems to be ok\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1107: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_sh1107_seeed_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1107_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1107_128x128_init_seq); \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_seeed_128x128_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sh1108.c",
    "content": "/*\n\n  u8x8_d_sh1108.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n/* \n  code copyied from sh1107\n  SH1108: 160x160 controller from Sino Wealth\n*/\n\n\n\nstatic const uint8_t u8x8_d_sh1108_noname_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1108_noname_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1108_160x160_noname_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1108_160x160_noname_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_sh1108_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1108_64x128_noname_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_64x128_noname_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_noname_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_noname_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_160x160_noname_powersave0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_160x160_noname_powersave1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* sh1108 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n\n      //u8x8_cad_SendCmd(u8x8, 0x040 ); /* set line offset to 0 */\n\n      // set column address\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4));\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x & 15))); \n      \n      // set page address\n      u8x8_cad_SendCmd(u8x8, 0x0b0 ); \t\t// page cmd is a two byte command\n      u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos)); \n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n\n/* issue #619, 160x160 OLED */\nstatic const uint8_t u8x8_d_sh1108_160x160_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n    \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x060),\t\t/* clock divide ratio and oscillator frequency */\n  U8X8_CA(0x0a9, 0x003), \t\t/* set display resolution, 0=64x160, 1=96x160, 2=128x160, 3=160x160 */\n  U8X8_C(0x020),\t\t                /* addressing mode */\n  U8X8_CA(0x081, 0x01f), \t\t/* set contrast control */\n  U8X8_CA(0x0ad, 0x80),\t\t\t/* DC/DC control 80=Use external Vpp, 89=Use internal DC/DC*/\n  U8X8_C(0x030),\t\t\t\t/* set discharge VSL level, 0x030..0x03f */\n  U8X8_CA(0x0d9, 0x028), \t\t/* pre-charge period */\n  U8X8_CA(0x0db, 0x035), \t\t/* vcomh deselect level */    \n  U8X8_CA(0x0dc, 0x035),\t\t/* VSEGM Deselect Level */\n\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_sh1108_160x160_noname_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 60,\n  /* pre_chip_disable_wait_ns = */ 120,\n  /* reset_pulse_width_ms = */ 100, \t/* sh1108: 3 us */\n  /* post_reset_wait_ms = */ 100, /* sometimes OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 100,\t\t/* sh1108: 100ns */\n  /* sck_pulse_width_ns = */ 100,\t/* sh1108: 100ns */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* sh1108: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 20,\n  /* tile_height = */ 20,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 160\n};\n\nuint8_t u8x8_d_sh1108_160x160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_sh1108_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1108_160x160_noname_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1108_160x160_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*==================================================*/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_sh1122.c",
    "content": "/*\n\n  u8x8_d_sh1122.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  Copied from sh1122 mostly because of the similar RAM architecture.\n  However: Commands are very different!\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_sh1122_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* sh1122: display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1122_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* sh1122: display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for SH1122 (32 Bytes)\n*/\n\n/*\nstatic uint8_t u8x8_sh1122_to32_dest_buf[32];\n\nstatic uint8_t *u8x8_sh1122_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_sh1122_to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_sh1122_to32_dest_buf;\n}\n*/\n\n\nstatic uint8_t u8x8_write_byte_to_16gr_device(u8x8_t *u8x8, uint8_t b)\n{\n  static uint8_t buf[4];\n  static uint8_t map[4] = { 0, 0x00f, 0x0f0, 0x0ff };\n  buf [3] = map[b & 3];\n  b>>=2;\n  buf [2] = map[b & 3];\n  b>>=2;\n  buf [1] = map[b & 3];\n  b>>=2;\n  buf [0] = map[b & 3];\n  return u8x8_cad_SendData(u8x8, 4, buf);\n}\n\nuint8_t u8x8_d_sh1122_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x; \n  uint8_t y, c, i;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_256x64_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* sh1122 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 2;\t\t// only every 4th col can be addressed\n      x += u8x8->x_offset;\t\t\n    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y *= 8;\n          \n      \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      for( i = 0; i < 8; i++ )\n      {\n\tu8x8_cad_SendCmd(u8x8, 0x0b0 );\t/* set row address */\n\tu8x8_cad_SendArg(u8x8, y);\n\tu8x8_cad_SendCmd(u8x8, x & 15 );\t/* lower 4 bit*/\n\tu8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4) );\t/* higher 3 bit */\t  \n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n\n\twhile (  c > 0 )\n\t{\n\t  u8x8_write_byte_to_16gr_device(u8x8, *ptr);\n\t  c--;\n\t  ptr++;\n\t}\n\ty++;\n      }\n\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================================*/\n\nstatic const uint8_t u8x8_d_sh1122_256x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t/* remap */\n  U8X8_C(0x0c8),\t\t/* remap */\n  U8X8_C(0x060),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_sh1122_256x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t/* remap */\n  U8X8_C(0x0c0),\t\t/* remap */\n  U8X8_C(0x040),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_sh1122_256x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 10, \t/* sh1122: 10 us */\n  /* post_reset_wait_ms = */ 20, \t/* */\n  /* sda_setup_time_ns = */ 125,\t\t/* sh1122: cycle time is 250ns, so use 250/2 */\n  /* sck_pulse_width_ns = */ 125,\t/* sh1122: cycle time is 250ns, so use 250/2 */\n  /* sck_clock_hz = */ 40000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns  */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 10,\n  /* write_pulse_width_ns = */ 150,\t/* sh1122: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 32,\t\t/* 256 pixel, so we require 32 bytes for this */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t/* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_sh1122_256x64_init_seq[] = {\n    \n  U8X8_DLY(1),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(1),\n  \n  U8X8_C(0xae),\t\t                /* display off */\n  U8X8_C(0x40),\t\t\t\t/* display start line */  \n  U8X8_C(0x0a0),\t\t/* remap */\n  U8X8_C(0x0c0),\t\t/* remap */\n  U8X8_CA(0x81, 0x80),\t\t\t/* set display contrast  */  \n  U8X8_CA(0xa8, 0x3f),\t\t\t/* multiplex ratio 1/64 Duty (0x0F~0x3F) */  \n  U8X8_CA(0xad, 0x81),\t\t\t/* use buildin DC-DC with 0.6 * 500 kHz */  \n  \n  U8X8_CA(0xd5, 0x50),\t\t\t/* set display clock divide ratio (lower 4 bit)/oscillator frequency (upper 4 bit)  */  \n  U8X8_CA(0xd3, 0x00),\t\t\t/* display offset, shift mapping ram counter */  \n  U8X8_CA(0xd9, 0x22),\t\t\t/* pre charge (lower 4 bit) and discharge(higher 4 bit) period */  \n  U8X8_CA(0xdb, 0x35),\t\t\t/* VCOM deselect level */  \n  U8X8_CA(0xdc, 0x35),\t\t\t/* Pre Charge output voltage */  \n  U8X8_C(0x030),\t\t\t\t/* discharge level */\n\n  U8X8_DLY(1),\t\t\t\t\t/* delay  */\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_sh1122_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1122_256x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_256x64_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_256x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_sh1122_256x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    \n    default:\n      return u8x8_d_sh1122_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1305.c",
    "content": "/*\n\n  u8x8_d_ssd1305.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ssd1305_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1305_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1305_128x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0d3, 32),\t\t\t/* display offset to 32 */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1305_128x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0d3, 0),\t\t\t/* display offset to  */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\nstatic uint8_t u8x8_d_ssd1305_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, 0x040 );\t/* set line offset to 0 */\n    \n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendArg(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendArg(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos)   );\n\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1305 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/* timing from SSD1306 */\nstatic const u8x8_display_info_t u8x8_ssd1305_128x32_noname_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 2,\n  /* flipmode_x_offset = */ 2,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\n\nstatic const uint8_t u8x8_d_ssd1305_128x32_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 32),\t\t\t/* display offset to 32 */\n  U8X8_C(0x040),\t\t        \t/* set display start line to 0 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x0cf), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0f1), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x040), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1305_128x32_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1305_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1305_128x32_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* adafruit 128x32 SSD1305 OLED, https://www.adafruit.com/product/2675 */\n/* issue 724 */\n\n/* timing from SSD1306 */\nstatic const u8x8_display_info_t u8x8_ssd1305_128x32_adafruit_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\n\nuint8_t u8x8_d_ssd1305_128x32_adafruit(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1305_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1305_128x32_adafruit_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n\n/*================================================*/\n/* adafruit SSD1305 OLED */\n\n/* timing from SSD1306 */\nstatic const u8x8_display_info_t u8x8_ssd1305_128x64_adafruit_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 2,\n  /* flipmode_x_offset = */ 2,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_ssd1305_128x64_adafruit_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x0f0),\t\t/* clock divide ratio (0x00=1) and oscillator frequency */\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x040),\t\t/* display offset to 32 */\n  U8X8_C(0x040),\t\t        \t/* set display start line to 0 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x032), \t\t/* [2] set contrast control */\n  U8X8_CA(0x082, 0x080), \t\t/* set area brightness (reset=0x080) */\n  U8X8_CA(0x0d9, 0x0f1), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x040), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1305_128x64_adafruit(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1305_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x64_adafruit_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1305_128x64_adafruit_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* Raystar RET012864 OLED, issue https://github.com/olikraus/u8g2/issues/1111 */\n\nstatic const u8x8_display_info_t u8x8_ssd1305_128x64_raystar_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ssd1305_128x64_raystar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1305_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1305_128x64_adafruit_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1305_128x64_raystar_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_128x32.c",
    "content": "/*\n\n  u8x8_d_ssd1306_128x32.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* UG-2832HSWEG02 Datasheet, Section 4.4 */\nstatic const uint8_t u8x8_d_ssd1306_128x32_univision_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x01f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x002),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n  U8X8_CA(0x081, 0x08f),\t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0f1),\t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x040),\t\t/* vcomh deselect level */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x32_univision_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x32_univision_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x32_univision_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x32_univision_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_128x32_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x32_univision_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x32_univision_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x32_univision_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x32_univision_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x32_univision_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x32_univision_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_128x32_univision_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_ssd1306_128x32_univision(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x32_univision_display_info);\n      return 1;\n    }\n    return u8x8_d_ssd1306_128x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n/*=============================================*/\n/* issue 756 */\n\n#define\t    ADDR_MODE\t0 //0:horizontal, 1:vertical, 2:page\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_128x32_winstar_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 125,\n  /* flipmode_x_offset = */ 125,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_ssd1306_128x32_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x32_winstar_display_info);\n      return 1;\n    }\n    return u8x8_d_ssd1306_128x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n/*=============================================*/\n/* visionox 132x32 OLED, https://github.com/olikraus/u8g2/issues/1250 */\n\n\nstatic const uint8_t u8x8_d_sh1106_128x32_visionox_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0xAE),\n  U8X8_CA(0xD5, 0x91),\n  U8X8_CA(0xA8, 0x1F),\n  U8X8_CA(0xD3, 0x10),\n  U8X8_C(0x40),\n  U8X8_CA(0xAD, 0x8B),\n  U8X8_C(0x33),\n  U8X8_C(0xA1),\n  U8X8_C(0xC8),\n  U8X8_CA(0xDA, 0x12),\n  U8X8_CA(0x81, 0xAF),\n  U8X8_CA(0xD9, 0x1F),\n  U8X8_CA(0xDB, 0x25),\n  U8X8_C(0xA4),\n  U8X8_C(0xA6),\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_d_sh1106_128x32_visionox_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 2,\n  /* flipmode_x_offset = */ 2,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\n\nuint8_t u8x8_d_sh1106_128x32_visionox(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_d_sh1106_128x32_visionox_display_info);\n      return 1;\n    }\n\n    if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_128x32_visionox_init_seq);    \n    }\n    \n    return u8x8_d_ssd1306_128x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_128x64_noname.c",
    "content": "/*\n\n  u8x8_d_ssd1306_128x64_noname.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* more or less generic setup of all these small OLEDs */\nstatic const uint8_t u8x8_d_ssd1306_128x64_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, SSD1306 only, should be removed for SH1106 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x0cf), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0f1), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x040), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* this setup maximizes the brightness range, that can be set with setContrast() */\n/* Drawback: VCOMH deselect level is set to 0, which das not work so good with all OLEDs, issue #116 */\nstatic const uint8_t u8x8_d_ssd1306_128x64_vcomh0_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n  U8X8_CA(0x081, 0x0ef),\t\t/* [2] set contrast control,  */\n  U8X8_CA(0x0d9, 0x0a1),\t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x000),\t\t/* vcomh deselect level 0x000 .. 0x070, low nibble always 0 */\n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/* same as u8x8_d_ssd1306_128x64_noname_init_seq, but 0x0da bit 4 is set to 0 */\n/* this will disable the alternative COM configuration */\nstatic const uint8_t u8x8_d_ssd1306_128x64_alt0_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, SSD1306 only, should be removed for SH1106 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x002),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x0cf), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0f1), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x040), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n/* issue 316: a special sh1106 setup, https://www.mikrocontroller.net/topic/431371?goto=5087807#5087807 */\nstatic const uint8_t u8x8_d_sh1106_128x64_winstar_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0xae),                 // Display OFF/ON: off (POR = 0xae)\n  U8X8_C(0xa4),                 // Set Entire Display OFF/ON: off (POR = 0xa4)\n  U8X8_CA(0xd5, 0x50),       // Divide Ratio/Oscillator FrequencyData Set: divide ratio = 1 (POR = 1), Oscillator Frequency = +/- 0% (POR = +/- 0%)\n  U8X8_CA(0xa8, 0x3f),       // Multiplex Ratio Data Set: 64 (POR = 0x3f, 64)\n  U8X8_CA(0xd3, 0x00),       // Display OffsetData Set: 0 (POR = 0x00)\n  U8X8_C(0x40),                 // Set Display Start Line: 0  \n  U8X8_CA(0xad, 0x8b),       // DC-DC ON/OFF Mode Set: Built-in DC-DC is used, Normal Display (POR = 0x8b)\n  U8X8_CA(0xd9, 0x22),       // Dis-charge/Pre-charge PeriodData Set: pre-charge 2 DCLKs, dis-charge 2 DCLKs (POR = 0x22, pre-charge 2 DCLKs, dis-charge 2 DCLKs)\n  U8X8_CA(0xdb, 0x35),       // VCOM Deselect LevelData Set: 0,770V (POR = 0x35, 0,770 V)\n  U8X8_C(0x32), // Set Pump voltage value: 8,0 V (POR = 0x32, 8,0 V)\n  U8X8_CA(0x81, 0xff),       // Contrast Data Register Set: 255 (large) (POR = 0x80)\n  U8X8_C(0x0a6),\t\t\t// Set Normal/Reverse Display: normal (POR = 0xa6)\n  U8X8_CA(0x0da, 0x012),\t\t// com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) \n      \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1306_128x64_noname_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x64_noname_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x64_noname_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x64_noname_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_sh1106_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x64_noname_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, 0x040 );\t/* set line offset to 0 */\n    \n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendArg(u8x8, 0x000 | ((x&15)));\t\t\t\t\t/* probably wrong, should be SendCmd */\n      u8x8_cad_SendArg(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\t/* probably wrong, should be SendCmd */\n\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_128x64_noname_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ssd1306_128x64_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_ssd1306_128x64_vcomh0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_vcomh0_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_ssd1306_128x64_alt0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  \n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_alt0_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_sh1106_128x64_noname_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 3,\t\t/* active low (clock is high by default), rising edge, this seems to be a difference to the ssd1306 */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 2,\n  /* flipmode_x_offset = */ 2,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_sh1106_128x64_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      /* maybe use a better init sequence */\n      /* https://www.mikrocontroller.net/topic/431371 */\n      /* the new sequence is added in the winstar constructor (see below), this is kept untouched */\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n    \n}\n\nuint8_t u8x8_d_sh1106_128x64_vcomh0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x64_vcomh0_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n    \n}\n\nuint8_t u8x8_d_sh1106_128x64_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_sh1106_128x64_winstar_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_sh1106_128x64_noname_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n    \n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_128x80_noname.c",
    "content": "/*\n\n  u8x8_d_ssd1306_128x80_noname.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n/* more or less generic setup of all these small OLEDs */\nstatic const uint8_t u8x8_d_ssd1306_128x80_noname_init_seq[] = {\n\n    U8X8_START_TRANSFER(),                /* enable chip, delay is part of the transfer start */\n\n    U8X8_C(0xAE), /*display off*/\n    U8X8_C(0x00), /*set lower column address*/\n    U8X8_C(0x10), /*set higher column address*/\n    U8X8_C(0x20), /* Set Memory addressing mode (0x20/0x21) */\n    U8X8_C(0x81), /*contract control*/\n    U8X8_C(0x6f), /*b0*/\n    U8X8_C(0xA0), /*set segment remap*/\n    U8X8_C(0xC0), /*Com scan direction*/\n    U8X8_C(0xA4), /*Disable Entire Display On (0xA4/0xA5)*/\n    U8X8_C(0xA6), /*normal / reverse*/\n    U8X8_C(0xD5), /*set osc division*/\n    U8X8_C(0x91),\n    U8X8_C(0xD9), /*set pre-charge period*/\n    U8X8_C(0x22),\n    U8X8_C(0xdb), /*set vcomh*/\n    U8X8_C(0x3f),\n    U8X8_C(0xA8), /*multiplex ratio*/\n    U8X8_C(0x4F), /*duty = 1/80*/\n    U8X8_C(0xD3), /*set display offset*/\n    U8X8_C(0x68), /*18*/\n    U8X8_C(0xdc), /*Set Display Start Line*/\n    U8X8_C(0x00),\n    U8X8_C(0xad), /*set charge pump enable*/\n    U8X8_C(0x8a), /*Set DC-DC enable (a=0:disable; a=1:enable) */\n\n\n    U8X8_END_TRANSFER(),                /* disable chip */\n    U8X8_END()                        /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x80_noname_powersave0_seq[] = {\n    U8X8_START_TRANSFER(),                /* enable chip, delay is part of the transfer start */\n    U8X8_C(0x0af),                        /* display on */\n    U8X8_END_TRANSFER(),                /* disable chip */\n    U8X8_END()                        /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x80_noname_powersave1_seq[] = {\n    U8X8_START_TRANSFER(),                /* enable chip, delay is part of the transfer start */\n    U8X8_C(0x0ae),                        /* display off */\n    U8X8_END_TRANSFER(),                /* disable chip */\n    U8X8_END()                        /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x80_noname_flip0_seq[] = {\n    U8X8_START_TRANSFER(),                /* enable chip, delay is part of the transfer start */\n    U8X8_C(0x0a1),                /* segment remap a0/a1*/\n    U8X8_C(0x0c8),                /* c0: scan dir normal, c8: reverse */\n    U8X8_END_TRANSFER(),                /* disable chip */\n    U8X8_END()                        /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_128x80_noname_flip1_seq[] = {\n    U8X8_START_TRANSFER(),                /* enable chip, delay is part of the transfer start */\n    U8X8_C(0x0a0),                /* segment remap a0/a1*/\n    U8X8_C(0x0c0),                /* c0: scan dir normal, c8: reverse */\n    U8X8_END_TRANSFER(),                /* disable chip */\n    U8X8_END()                        /* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_sh1106_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    uint8_t x, c;\n    uint8_t *ptr;\n    switch (msg)\n    {\n        /* handled by the calling function\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n          u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x80_noname_display_info);\n          break;\n        */\n        /* handled by the calling function\n        case U8X8_MSG_DISPLAY_INIT:\n          u8x8_d_helper_display_init(u8x8);\n          u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_init_seq);\n          break;\n        */\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n            if (arg_int == 0)\n                u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_powersave0_seq);\n            else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_powersave1_seq);\n            break;\n        case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n            if (arg_int == 0)\n            {\n                u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_flip0_seq);\n                u8x8->x_offset = u8x8->display_info->default_x_offset;\n            } else\n            {\n                u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_flip1_seq);\n                u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n            }\n            break;\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n            u8x8_cad_StartTransfer(u8x8);\n            u8x8_cad_SendCmd(u8x8, 0x081);\n            u8x8_cad_SendArg(u8x8, arg_int);    /* ssd1306 has range from 0 to 255 */\n            u8x8_cad_EndTransfer(u8x8);\n            break;\n#endif\n        case U8X8_MSG_DISPLAY_DRAW_TILE:\n            u8x8_cad_StartTransfer(u8x8);\n            x = ((u8x8_tile_t *) arg_ptr)->x_pos;\n            x *= 8;\n            x += u8x8->x_offset;\n\n            u8x8_cad_SendCmd(u8x8, 0x040);    /* set line offset to 0 */\n\n            u8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4));\n            u8x8_cad_SendArg(u8x8, 0x000 | ((x & 15)));                    /* probably wrong, should be SendCmd */\n            u8x8_cad_SendArg(u8x8,\n                             0x0b0 | (((u8x8_tile_t *) arg_ptr)->y_pos));    /* probably wrong, should be SendCmd */\n\n\n            do\n            {\n                c = ((u8x8_tile_t *) arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;\n                u8x8_cad_SendData(u8x8, c * 8, ptr);    /* note: SendData can not handle more than 255 bytes */\n                /*\n                do\n                {\n                  u8x8_cad_SendData(u8x8, 8, ptr);\n                  ptr += 8;\n                  c--;\n                } while( c > 0 );\n                */\n                arg_int--;\n            } while (arg_int > 0);\n\n            u8x8_cad_EndTransfer(u8x8);\n            break;\n        default:\n            return 0;\n    }\n    return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_128x80_noname_display_info =\n    {\n        /* chip_enable_level = */ 0,\n        /* chip_disable_level = */ 1,\n\n        /* post_chip_enable_wait_ns = */ 20,\n        /* pre_chip_disable_wait_ns = */ 10,\n        /* reset_pulse_width_ms = */ 100,    /* SSD1306: 3 us */\n        /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n        /* sda_setup_time_ns = */ 50,        /* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n        /* sck_pulse_width_ns = */\n                                  50,    /* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n        /* sck_clock_hz = */\n                                  8000000UL,    /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n        /* spi_mode = */ 0,        /* active high, rising edge */\n        /* i2c_bus_clock_100kHz = */ 4,\n        /* data_setup_time_ns = */ 40,\n        /* write_pulse_width_ns = */ 150,    /* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n        /* tile_width = */ 10,\n        /* tile_hight = */ 16,\n        /* default_x_offset = */ 0,\n        /* flipmode_x_offset = */ 0,\n        /* pixel_width = */ 80,\n        /* pixel_height = */ 128\n    };\n\nuint8_t u8x8_d_ssd1306_128x80_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n\n    if (u8x8_d_ssd1306_sh1106_generic(u8x8, msg, arg_int, arg_ptr) != 0)\n        return 1;\n\n    switch (msg)\n    {\n        case U8X8_MSG_DISPLAY_INIT:\n            u8x8_d_helper_display_init(u8x8);\n            u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_128x80_noname_init_seq);\n            break;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_128x80_noname_display_info);\n            break;\n        default:\n            return 0;\n    }\n    return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_2040x16.c",
    "content": "/*\n\n u8x8_d_ssd1306_2040x16.c\n\n Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n Copyright (c) 2016, olikraus@gmail.com\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n\n * Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or other\n materials provided with the distribution.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR\n CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n */\n#include \"u8x8.h\"\n\n/* virtual device, issue 1291 */\nstatic const uint8_t u8x8_d_ssd1306_2040x16_init_seq[] =\n{\n\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\n\n    U8X8_C(0x0ae), /* display off */\n    U8X8_CA(0x0d5, 0x080), /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n    U8X8_CA(0x0a8, 0x03f), /* multiplex ratio, 0.71 OLED: changed from 0x2f to 0x3f */\n    U8X8_CA(0x0d3, 0x000), /* display offset, 0.71 OLED  */\n    U8X8_C(0x040), /* set display start line to 0, 0.71 OLED */\n    U8X8_CA(0x08d, 0x014), /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, 0.71 OLED  0x14*/\n\n    /// according to the datasheet, 0x00 is NOT page addressing mode, but horizontal addressing mode;\n    /// so it looks like u8g2 expects horizontal addressing (and the inline comment is wrong) while the Winstar example\n    /// actually uses page addressing (which is the reset default)\n    U8X8_CA(0x020, 0x000), /* horizontal addressing mode */\n\n    U8X8_C(0x0a1), /* segment remap a0/a1, 0.71 OLED  */\n    U8X8_C(0x0c8), /* c0: scan dir normal, c8: reverse, 0.71 OLED  */\n    // Flipmode\n    // U8X8_C(0x0a0),       /* segment remap a0/a1*/\n    // U8X8_C(0x0c0),       /* c0: scan dir normal, c8: reverse */\n\n    U8X8_CA(0x0da, 0x012), /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.71 OLED */\n    U8X8_CA(0x081, 0x07f), /* [2] set contrast control, 0.71 OLED datasheet: 0x7f */\n    U8X8_CA(0x0d9, 0x022), /* [2] pre-charge period 0x022/f1, 0.71 OLED datasheet: 0x22 */\n    U8X8_CA(0x0db, 0x040), /* vcomh deselect level, 0.71 OLED datasheet: 0x40 */\n\n    // U8X8_C(0x02e),        /* Deactivate scroll */\n    U8X8_C(0x0a4), /* output ram to display */\n    U8X8_C(0x0a6), /* none inverted normal display mode */\n\n    U8X8_END_TRANSFER(), /* disable chip */\n    U8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_2040x16_powersave0_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0af), /* display on */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_2040x16_powersave1_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0ae), /* display off */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_2040x16_flip0_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0a1), /* segment remap a0/a1*/\nU8X8_C(0x0c8), /* c0: scan dir normal, c8: reverse */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_2040x16_flip1_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0a0), /* segment remap a0/a1*/\nU8X8_C(0x0c0), /* c0: scan dir normal, c8: reverse */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic uint8_t u8x8_d_ssd1306_2040x16_generic(u8x8_t *u8x8, uint8_t msg,\n    uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch (msg)\n  {\n    /* handled by the calling function\n     case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n     u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_2040x16_display_info);\n     break;\n     case U8X8_MSG_DISPLAY_INIT:\n     u8x8_d_helper_display_init(u8x8);\n     u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_init_seq);\n     break;\n     */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if (arg_int == 0)\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_powersave0_seq);\n      else\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if (arg_int == 0)\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_flip0_seq);\n        u8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_flip1_seq);\n        u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081);\n      u8x8_cad_SendArg(u8x8, arg_int); /* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *) arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4));\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x & 15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *) arg_ptr)->y_pos));\n\n      do\n      {\n        c = ((u8x8_tile_t *) arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;\n        u8x8_cad_SendData(u8x8, c * 8, ptr); /* note: SendData can not handle more than 255 bytes */\n        arg_int--;\n      } while (arg_int > 0);\n\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_ssd1306_2040x16_display_info =\n{\n/* chip_enable_level = */0,\n/* chip_disable_level = */1,\n\n/* post_chip_enable_wait_ns = */20,\n/* pre_chip_disable_wait_ns = */10,\n/* reset_pulse_width_ms = */100, /* SSD1306: 3 us */\n/* post_reset_wait_ms = */100, /* far east OLEDs need much longer setup time */\n/* sda_setup_time_ns = */50, /* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n/* sck_pulse_width_ns = */50, /* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n/* sck_clock_hz = */8000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n/* spi_mode = */0, /* active high, rising edge */\n/* i2c_bus_clock_100kHz = */4,\n/* data_setup_time_ns = */40,\n/* write_pulse_width_ns = */150, /* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n/* tile_width = */255,\n/* tile_height = */2,\n/* default_x_offset = */0,\n/* flipmode_x_offset = */0,\n/* pixel_width = */2040,\n/* pixel_height = */16 };\n\nuint8_t u8x8_d_ssd1306_2040x16(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if (msg == U8X8_MSG_DISPLAY_SETUP_MEMORY)\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_2040x16_display_info);\n    return 1;\n  }\n  else if (msg == U8X8_MSG_DISPLAY_INIT)\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_2040x16_init_seq);\n    return 1;\n  }\n  return u8x8_d_ssd1306_2040x16_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_48x64.c",
    "content": "/*\n\n u8x8_d_ssd1306_48x64_winstar.c\n\n Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n Copyright (c) 2016, olikraus@gmail.com\n All rights reserved.\n\n Redistribution and use in source and binary forms, with or without modification,\n are permitted provided that the following conditions are met:\n\n * Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n\n * Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or other\n materials provided with the distribution.\n\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND\n CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES,\n INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR\n CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\n SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\n NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,\n STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\n ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n\n */\n#include \"u8x8.h\"\n\n/* Winstar 0.71 OLED */\nstatic const uint8_t u8x8_d_ssd1306_48x64_winstar_init_seq[] =\n{\n\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\n\n    U8X8_C(0x0ae), /* display off */\n    U8X8_CA(0x0d5, 0x080), /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n    U8X8_CA(0x0a8, 0x03f), /* multiplex ratio, 0.71 OLED: changed from 0x2f to 0x3f */\n    U8X8_CA(0x0d3, 0x000), /* display offset, 0.71 OLED  */\n    U8X8_C(0x040), /* set display start line to 0, 0.71 OLED */\n    U8X8_CA(0x08d, 0x014), /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, 0.71 OLED  0x14*/\n\n    /// according to the datasheet, 0x00 is NOT page addressing mode, but horizontal addressing mode;\n    /// so it looks like u8g2 expects horizontal addressing (and the inline comment is wrong) while the Winstar example\n    /// actually uses page addressing (which is the reset default)\n    U8X8_CA(0x020, 0x000), /* horizontal addressing mode */\n\n    U8X8_C(0x0a1), /* segment remap a0/a1, 0.71 OLED  */\n    U8X8_C(0x0c8), /* c0: scan dir normal, c8: reverse, 0.71 OLED  */\n    // Flipmode\n    // U8X8_C(0x0a0),       /* segment remap a0/a1*/\n    // U8X8_C(0x0c0),       /* c0: scan dir normal, c8: reverse */\n\n    U8X8_CA(0x0da, 0x012), /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.71 OLED */\n    U8X8_CA(0x081, 0x07f), /* [2] set contrast control, 0.71 OLED datasheet: 0x7f */\n    U8X8_CA(0x0d9, 0x022), /* [2] pre-charge period 0x022/f1, 0.71 OLED datasheet: 0x22 */\n    U8X8_CA(0x0db, 0x040), /* vcomh deselect level, 0.71 OLED datasheet: 0x40 */\n\n    // U8X8_C(0x02e),        /* Deactivate scroll */\n    U8X8_C(0x0a4), /* output ram to display */\n    U8X8_C(0x0a6), /* none inverted normal display mode */\n\n    U8X8_END_TRANSFER(), /* disable chip */\n    U8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_48x64_powersave0_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0af), /* display on */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_48x64_powersave1_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0ae), /* display off */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_48x64_flip0_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0a1), /* segment remap a0/a1*/\nU8X8_C(0x0c8), /* c0: scan dir normal, c8: reverse */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_48x64_flip1_seq[] =\n{\nU8X8_START_TRANSFER(), /* enable chip, delay is part of the transfer start */\nU8X8_C(0x0a0), /* segment remap a0/a1*/\nU8X8_C(0x0c0), /* c0: scan dir normal, c8: reverse */\nU8X8_END_TRANSFER(), /* disable chip */\nU8X8_END() /* end of sequence */\n};\n\nstatic uint8_t u8x8_d_ssd1306_48x64_generic(u8x8_t *u8x8, uint8_t msg,\n    uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch (msg)\n  {\n    /* handled by the calling function\n     case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n     u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_48x64_display_info);\n     break;\n     case U8X8_MSG_DISPLAY_INIT:\n     u8x8_d_helper_display_init(u8x8);\n     u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_winstar_init_seq);\n     break;\n     */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if (arg_int == 0)\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_powersave0_seq);\n      else\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if (arg_int == 0)\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_flip0_seq);\n        u8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_flip1_seq);\n        u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081);\n      u8x8_cad_SendArg(u8x8, arg_int); /* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *) arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x >> 4));\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x & 15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *) arg_ptr)->y_pos));\n\n      do\n      {\n        c = ((u8x8_tile_t *) arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;\n        u8x8_cad_SendData(u8x8, c * 8, ptr); /* note: SendData can not handle more than 255 bytes */\n        arg_int--;\n      } while (arg_int > 0);\n\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_ssd1306_48x64_display_info =\n{\n/* chip_enable_level = */0,\n/* chip_disable_level = */1,\n\n/* post_chip_enable_wait_ns = */20,\n/* pre_chip_disable_wait_ns = */10,\n/* reset_pulse_width_ms = */100, /* SSD1306: 3 us */\n/* post_reset_wait_ms = */100, /* far east OLEDs need much longer setup time */\n/* sda_setup_time_ns = */50, /* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n/* sck_pulse_width_ns = */50, /* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n/* sck_clock_hz = */8000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n/* spi_mode = */0, /* active high, rising edge */\n/* i2c_bus_clock_100kHz = */4,\n/* data_setup_time_ns = */40,\n/* write_pulse_width_ns = */150, /* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n/* tile_width = */6,\n/* tile_height = */8,\n/* default_x_offset = */40,\n/* flipmode_x_offset = */40,\n/* pixel_width = */48,\n/* pixel_height = */64 };\n\n/* Winstar 0.71\" OLED */\nuint8_t u8x8_d_ssd1306_48x64_winstar(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int,\n    void *arg_ptr)\n{\n  if (msg == U8X8_MSG_DISPLAY_SETUP_MEMORY)\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_48x64_display_info);\n    return 1;\n  }\n  else if (msg == U8X8_MSG_DISPLAY_INIT)\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_48x64_winstar_init_seq);\n    return 1;\n  }\n  return u8x8_d_ssd1306_48x64_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_64x32.c",
    "content": "/*\n\n  u8x8_d_ssd1306_64x32.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_64x32_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x32_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_noname_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*======================================================*/\n\nstatic const u8x8_display_info_t u8x8_ssd1306_64x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 8,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 32,\n  /* flipmode_x_offset = */ 32,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 32\n};\n\n\n/*======================================================*/\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_noname_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x02f),\t\t/* multiplex ratio: changed from 0x1f to 0x2f */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1 */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n  U8X8_CA(0x081, 0x0cf),\t\t/* [2] set contrast control datasheet: 0xcf */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1 */\n  U8X8_CA(0x0db, 0x000),\t\t/* vcomh deselect level */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1306_64x32_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x32_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_noname_init_seq);    \n      return 1;\n    }\n    return u8x8_d_ssd1306_64x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n/*======================================================*/\n\nstatic const uint8_t u8x8_d_ssd1306_64x32_1f_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n    \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x01f),\t\t/* multiplex ratio: changed from 0x1f to 0x2f, 23 Sep 17: changed back to 1f */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1 */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n  U8X8_CA(0x081, 0x0cf),\t\t/* [2] set contrast control datasheet: 0xcf */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1 */\n  U8X8_CA(0x0db, 0x000),\t\t/* vcomh deselect level */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1306_64x32_1f(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x32_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x32_1f_init_seq);    \n      return 1;\n    }\n    return u8x8_d_ssd1306_64x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_64x48.c",
    "content": "/*\n\n  u8x8_d_ssd1306_64x48.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* EastRising 0.66 OLED */\nstatic const uint8_t u8x8_d_ssd1306_64x48_er_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x02f),\t\t/* multiplex ratio, 0.66 OLED: changed from 0x1f to 0x2f */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset, 0.66 OLED  */\n  U8X8_C(0x040),\t\t                /* set display start line to 0, 0.66 OLED */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, 0.66 OLED  0x14*/\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1, 0.66 OLED  */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse, 0.66 OLED  */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.66 OLED */\n  U8X8_CA(0x081, 0x0cf),\t\t/* [2] set contrast control, 0.66 OLED datasheet: 0xcf */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1, 0.66 OLED datasheet: 0x22 */\n  U8X8_CA(0x0db, 0x000),\t\t/* vcomh deselect level, 0.66 OLED datasheet: 0x00 */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x48_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x48_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x48_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_64x48_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_64x48_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x48_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_er_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_64x48_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 8,\n  /* tile_hight = */ 6,\n  /* default_x_offset = */ 32,\n  /* flipmode_x_offset = */ 32,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 48\n};\n\n/* East Rising 0.66\" OLED */\nuint8_t u8x8_d_ssd1306_64x48_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_64x48_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_64x48_er_init_seq);    \n      return 1;\n    }\n    return u8x8_d_ssd1306_64x48_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_72x40.c",
    "content": "/*\n\n  u8x8_d_ssd1306_72x40.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* \nEastRising 0.41 OLED \nhttps://www.buydisplay.com/default/white-0-42-inch-oled-display-panel-72x40-iic-i2c-serial-spi-ssd1306\n\n\n    command(0xae);//--turn off oled panel\n\t\n    command(0xd5);//--set display clock divide ratio/oscillator frequency\n    command(0x80);//--set divide ratio\n\n    command(0xa8);//--set multiplex ratio\n    command(0x27);//--1/40 duty\n\n    command(0xd3);//-set display offset\n    command(0x00);//-not offset\n\n    command(0xad);//--Internal IREF Setting\t\n    command(0x30);//--\n\n    command(0x8d);//--set Charge Pump enable/disable\n    command(0x14);//--set(0x10) disable\n\n    command(0x40);//--set start line address\n\n    command(0xa6);//--set normal display\n\n    command(0xa4);//Disable Entire Display On\n\n    command(0xa1);//--set segment re-map 128 to 0\n\n    command(0xC8);//--Set COM Output Scan Direction 64 to 0\n\n    command(0xda);//--set com pins hardware configuration\n    command(0x12);\n\n    command(0x81);//--set contrast control register\n    command(0xaf);\n\n    command(0xd9);//--set pre-charge period\n    command(0x22);\n\n    command(0xdb);//--set vcomh\n    command(0x20);\n\n    command(0xaf);//--turn on oled panel\n\n\n*/\nstatic const uint8_t u8x8_d_ssd1306_72x40_er_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x027),\t\t/* multiplex ratio, 0.42 OLED: 0x27*/\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset, 0.42 OLED  */\n  U8X8_CA(0x0ad, 0x030),\t\t/* Internal IREF Setting for the 0.42 OLED, see also issue https://github.com/olikraus/u8g2/issues/1047 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, 0.66 OLED  0x14*/\n\n  U8X8_C(0x040),\t\t                /* set display start line to 0, 0.66 OLED */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  \n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1, 0.66 OLED  */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse, 0.66 OLED  */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.66 OLED */\n  U8X8_CA(0x081, 0x0af),\t\t/* [2] set contrast control, 0.42 OLED */\n  U8X8_CA(0x0d9, 0x022),\t\t/* [2] pre-charge period 0x022/f1, 0.42 OLED datasheet: 0x22 */\n  U8X8_CA(0x0db, 0x020),\t\t/* vcomh deselect level, 0.42 OLED datasheet: 0x20 */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_72x40_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_72x40_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_72x40_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_72x40_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_72x40_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_72x40_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_er_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_72x40_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 9,\n  /* tile_hight = */ 5,\n  /* default_x_offset = */ 28,\n  /* flipmode_x_offset = */ 28,\n  /* pixel_width = */ 72,\n  /* pixel_height = */ 40\n};\n\n/* \nEastRising 0.41 OLED \nhttps://www.buydisplay.com/default/white-0-42-inch-oled-display-panel-72x40-iic-i2c-serial-spi-ssd1306\n*/\nuint8_t u8x8_d_ssd1306_72x40_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_72x40_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_72x40_er_init_seq);    \n      return 1;\n    }\n    return u8x8_d_ssd1306_72x40_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1306_96x16.c",
    "content": "/*\n\n  u8x8_d_ssd1306_96x16.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* EastRising 0.69 OLED */\nstatic const uint8_t u8x8_d_ssd1306_96x16_er_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x00f),\t\t/* multiplex ratio, 0.69 OLED: 0x0f */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset, 0.69 OLED  */\n  U8X8_C(0x040),\t\t                /* set display start line to 0, 0.69 OLED */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, 0.66 OLED  0x14*/\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1, 0.66 OLED  */\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse, 0.66 OLED  */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x002),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), 0.66 OLED */\n  U8X8_CA(0x081, 0x0af),\t\t/* [2] set contrast control, 0.69 OLED datasheet: 0xaf */\n  U8X8_CA(0x0d9, 0x0f1),\t\t/* [2] pre-charge period 0x0f1, 0.69 OLED datasheet: 0xf1 */\n  U8X8_CA(0x0db, 0x020),\t\t/* vcomh deselect level, 0.69 OLED datasheet: 0x20 */\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_96x16_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_96x16_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_96x16_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1306_96x16_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1306_96x16_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_96x16_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_er_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1306_96x16_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, \t/* OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 12,\n  /* tile_hight = */ 2,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 32,\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 16\n};\n\n/* East Rising 0.69\" OLED */\nuint8_t u8x8_d_ssd1306_96x16_er(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1306_96x16_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1306_96x16_er_init_seq);    \n      return 1;\n    }\n    return u8x8_d_ssd1306_96x16_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1309.c",
    "content": "/*\n\n  u8x8_d_ssd1309.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ssd1309_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1309_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1309_128x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1309_128x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\nstatic uint8_t u8x8_d_ssd1309_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos)   );\n\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1309 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=================================================*/\n/* offset 2 version */\n\n/* timing from SSD1306 */\nstatic const u8x8_display_info_t u8x8_ssd1309_128x64_noname2_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 2,\n  /* flipmode_x_offset = */ 2,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_ssd1309_128x64_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0d5, 0x0a0),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio */\n  U8X8_C(0x040),\t\t        \t/* set display start line to 0 */\n  U8X8_CA(0x020, 0x002),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x06f), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0d3), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x020), \t\t/* vcomh deselect level */  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n  \n  //U8X8_C(0x0af),\t\t                /* display on */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1309_128x64_noname2(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1309_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1309_128x64_noname2_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=================================================*/\n/* offset 0 version */\n\n/* timing from SSD1306 */\nstatic const u8x8_display_info_t u8x8_ssd1309_128x64_noname0_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ssd1309_128x64_noname0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1309_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1309_128x64_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1309_128x64_noname0_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1316.c",
    "content": "/*\n\n  u8x8_d_ssd1316.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  SSD1316: 128x39 OLED\n  \n  https://github.com/olikraus/u8g2/issues/919\n\n*/\n\n\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_ssd1316_128x32_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1316_128x32_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1316_128x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1316_128x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\n/*===================================================*/\n\nstatic uint8_t u8x8_d_ssd1316_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1316_128x32_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n\n      u8x8_cad_StartTransfer(u8x8);\n    \n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\t/* probably wrong, should be SendCmd */\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos)); /* probably wrong, should be SendCmd */\n\n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*===================================================*/\n\n\n/* QT-2832TSWUG02/ZJY-2832TSWZG02 */\nstatic const uint8_t u8x8_d_ssd1316_128x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t        /* display off */\n  U8X8_C(0x040),\t\t        /* start line */\n  U8X8_CA(0x081, 0x045), \t\t/* QG-2832TSWZG02 datasheet */\n\n  U8X8_C(0x0a6),\t\t\t/* none inverted normal display mode */\n  U8X8_CA(0x0a8, 0x01f),\t\t/* multiplex ratio, duty = 1/32 */\n\n  U8X8_C(0x0a1),\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t/* c0: scan dir normal, c8: reverse */\n\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_CA(0x0d5, 0x080),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0d9, 0x022), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n  U8X8_CA(0x0db, 0x020), \t\t/* vcomh deselect level */  \n  U8X8_CA(0x08d, 0x015),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, */\n  \n  //U8X8_CA(0x0a2, 0x000),\t\t/* set display start line to 0 */\n  //U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  \n  // Flipmode\n  //U8X8_C(0x0a1),\t\t\t/* segment remap a0/a1*/\n  //U8X8_C(0x0c0),\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_C(0x02e),\t\t\t/* Deactivate scroll */ \n  //U8X8_C(0x0a4),\t\t\t/* output ram to display */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()           \t\t\t/* end of sequence */\n};\n\n\n\n\nstatic const u8x8_display_info_t u8x8_ssd1316_128x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* reset time */\n  /* post_reset_wait_ms = */ 100, /* reset delay */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_ssd1316_128x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1316_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1316_128x32_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1316_128x32_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1317.c",
    "content": "/*\n\n  u8x8_d_ssd1317.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  SSD1317: 128x96 OLED\n  \n  https://github.com/olikraus/u8g2/issues/663\n\n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* more or less generic setup of all these small OLEDs */\nstatic const uint8_t u8x8_d_ssd1317_96x96_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t        /* display off */\n  U8X8_CA(0x0d5, 0x0d1),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8) */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_CA(0x0a2, 0x000),\t\t/* set display start line to 0 */\n  U8X8_CA(0x08d, 0x014),\t\t/* [2] charge pump setting (p62): 0x014 enable, 0x010 disable, SSD1306 only, should be removed for SH1106 */\n  U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  \n  U8X8_C(0x0a0),\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  // Flipmode\n  //U8X8_C(0x0a1),\t\t\t/* segment remap a0/a1*/\n  //U8X8_C(0x0c0),\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x09f), \t\t/* [2] set contrast control */\n  U8X8_CA(0x0d9, 0x0f1), \t\t/* [2] pre-charge period 0x022/f1*/\n  U8X8_CA(0x0db, 0x0ff), \t\t/* vcomh deselect level */  \n  \n  // if vcomh is 0, then this will give the biggest range for contrast control issue #98\n  // restored the old values for the noname constructor, because vcomh=0 will not work for all OLEDs, #116\n  \n  U8X8_C(0x02e),\t\t\t/* Deactivate scroll */ \n  U8X8_C(0x0a4),\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()           \t\t\t/* end of sequence */\n};\n\n\n\nstatic const uint8_t u8x8_d_ssd1317_96x96_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1317_96x96_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1317_96x96_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1317_96x96_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1317_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1317_96x96_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1306 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n  case U8X8_MSG_DISPLAY_DRAW_TILE:\n   u8x8_cad_StartTransfer(u8x8);\n   x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n   x *= 8;\n   x += u8x8->x_offset;\n  \n   u8x8_cad_SendCmd(u8x8, 0x040 );\t/* set line offset to 0 */\n   \n   u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n   u8x8_cad_SendArg(u8x8, 0x000 | ((x&15)));\t/* probably wrong, should be SendCmd */\n   u8x8_cad_SendArg(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos)); /* probably wrong, should be SendCmd */\n\n    \n   do\n   {\n    c = ((u8x8_tile_t *)arg_ptr)->cnt;\n    ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n    u8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n    /*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1317_96x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 12,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 16,\n  /* flipmode_x_offset = */ 16,\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 96\n};\n\nuint8_t u8x8_d_ssd1317_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1317_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1317_96x96_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1317_96x96_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1318.c",
    "content": "/*\n\n  u8x8_d_ssd1318.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  SSD1318: 128x96 OLED\n  \n  https://github.com/olikraus/u8g2/issues/784\n\n*/\n\n\n#include \"u8x8.h\"\n\n\n\n/* with internal charge pump (icp) */\nstatic const uint8_t u8x8_d_ssd1318_128x96_icp_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0ad, 0x0d0),\t\t/* external or internal IREF selection */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio, 96 duty */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_CA(0x0a2, 0x000),\t\t/* start line */\n  \n  \n  // four possible charge pump setting from as per sec 6.8.2 of the ssd1318 datasheet\n  // uncomment only one of the below for lines  \n  // default: \n  // U8X8_CA(0x08d, 0x004, 0x0ac, 0x001),\t\t/* Charge pump setting from sec 6.8.2 of SSD1318 datasheet */\n  // U8X8_CA(0x08d, 0x044, 0x0ac, 0x001),\t\t/* Charge pump setting from sec 6.8.2 of SSD1318 datasheet */\n  // U8X8_CA(0x08d, 0x084, 0x0ac, 0x001),\t\t/* Charge pump setting from sec 6.8.2 of SSD1318 datasheet */\n  U8X8_CAAA(0x08d, 0x0c4, 0x0ac, 0x001),\t\t/* Charge pump setting from sec 6.8.2 of SSD1318 datasheet */\n  \n\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x00f), \t\t/* value from issue 784, seems to be a little bit low... */\n  \n  \n  U8X8_CA(0x0d5, 0x0d1),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8), value from issue 784 example code */\n  U8X8_CA(0x0d9, 0x022), \t\t/* [2] pre-charge period 0x022/f1, value from issue 784 example code */\n  U8X8_CA(0x0db, 0x030), \t\t/* vcomh deselect level, value from issue 784 example code  */  \n  \n  \n  //U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  //U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/* with external charge pump */\nstatic const uint8_t u8x8_d_ssd1318_128x96_xcp_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0ad, 0x0d0),\t\t/* external or internal IREF selection */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio, 96 duty */\n  U8X8_CA(0x0d3, 0x000),\t\t/* display offset */\n  U8X8_CA(0x0a2, 0x000),\t\t/* start line */\n  \n  \n  // not sure if we have to set something for external charge pump\n  // ...\n  \n\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  // U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  \n  U8X8_CA(0x0da, 0x012),\t\t/* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */\n\n  U8X8_CA(0x081, 0x00f), \t\t/* value from issue 784, seems to be a little bit low... */\n  \n  \n  U8X8_CA(0x0d5, 0x0d1),\t\t/* clock divide ratio (0x00=1) and oscillator frequency (0x8), value from issue 784 example code */\n  U8X8_CA(0x0d9, 0x022), \t\t/* [2] pre-charge period 0x022/f1, value from issue 784 example code */\n  U8X8_CA(0x0db, 0x030), \t\t/* vcomh deselect level, value from issue 784 example code  */  \n  \n  \n  //U8X8_CA(0x020, 0x000),\t\t/* horizontal addressing mode */\n  //U8X8_C(0x02e),\t\t\t\t/* Deactivate scroll */ \n  \n  U8X8_C(0x0a4),\t\t\t\t/* output ram to display */\n  U8X8_C(0x0a6),\t\t\t\t/* none inverted normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1318_128x96_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1318_128x96_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1318_128x96_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1318_128x96_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_ssd1318_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1318_128x96_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1318 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n    \n      u8x8_cad_SendCmd(u8x8, 0x040 );\t/* set line offset to 0 */\n    \n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendArg(u8x8, 0x000 | ((x&15)));\t\t\t\t\t/* probably wrong, should be SendCmd */\n      u8x8_cad_SendArg(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\t/* probably wrong, should be SendCmd */\n\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\t/*\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, ptr);\n\t  ptr += 8;\n\t  c--;\n\t} while( c > 0 );\n\t*/\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1318_128x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1306: 3 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1306: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1306: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1306: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 96\n};\n\nuint8_t u8x8_d_ssd1318_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1318_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_icp_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1318_128x96_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_ssd1318_128x96_xcp(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_ssd1318_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1318_128x96_xcp_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1318_128x96_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1320.c",
    "content": "/*\n\n  u8x8_d_ssd1320.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2020, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  https://github.com/olikraus/u8g2/issues/1351\n  SSD1320: \n    160 x 160 dot matrix\n    16 gray scale\n  \n  Adapted from u8x8_d_ssd1322.c with the command set of the SSD1320 controller\n  \"official\" procedure is described here: https://github.com/olikraus/u8g2/wiki/internal\n  \n  NOTE: U8x8 does NOT work!\n  \n*/\n\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x132_nhd_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* ssd1320: display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x132_nhd_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* ssd1320: display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/*\n  input:32\n    one tile (8 Bytes; 1 byte per column)\n  output:\n    Tile for SSD1320 (32 Bytes)\n\n  The origin of the display seems to be in the upper right-hand corner. Therefore\n  compared to SSD1322, the order inside each byte is swapped.\n*/\n\nstatic uint8_t u8x8_ssd1320_to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1320_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1320_to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0x0f;\n      if ( b&1 ) v |= 0xf0;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1320_to32_dest_buf;\n}\n\n\nuint8_t u8x8_d_ssd1320_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x; \n  uint8_t y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_256x64_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_nhd_powersave0_seq);\n      else\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_nhd_powersave1_seq);\n      break;\n\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1320 has range from 1 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      x += u8x8->x_offset;\t\t\n    \n      y *= 8;\n    \n      \n      u8x8_cad_SendCmd(u8x8, 0x022 );\t/* set row address, moved out of the loop (issue 302) */\n      u8x8_cad_SendArg(u8x8, y);\n      u8x8_cad_SendArg(u8x8, y+7);\n      \n      do {\n\t      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n\t      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n        do {\n          u8x8_cad_SendCmd(u8x8, 0x021 );\t/* set column address */\n          u8x8_cad_SendArg(u8x8, x );\t/* start */\n          u8x8_cad_SendArg(u8x8, x+3 );\t/* end */\n          \n          u8x8_cad_SendData(u8x8, 32, u8x8_ssd1320_8to32(u8x8, ptr));\n          \n          ptr += 8;\n          x += 4;\n          c--;\n        } while( c > 0 );\n      \n      //x += 2;\n      arg_int--;\n    } while( arg_int > 0 );\n    \n    u8x8_cad_EndTransfer(u8x8);\n    break;\n\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================================*/\n/* 160x32 */\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x32_nhd_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x32_nhd_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_d_ssd1320_cs1_160x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* ssd1320: 2 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* ssd1320: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* ssd1320: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 10000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 10,\n  /* write_pulse_width_ns = */ 150,\t/* ssd1320: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 20,\t\t/* 160 pixel, so we require 20 bytes for this */\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\t/* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 32\n};\n\n// initialisation sequence from the Arduino Library\n// (see https://github.com/sparkfun/SparkFun_SSD1320_OLED_Arduino_Library)\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x32_init_seq[] = {\n    \n    U8X8_DLY(1),\n    U8X8_START_TRANSFER(),    /* enable chip, delay is part of the transfer start */\n    U8X8_DLY(1),\n    \n    U8X8_C(0xae),\t\t          /* display off */\n    U8X8_CA(0xd5, 0xC2),\t\t\t/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec)  */  \n    U8X8_CA(0xa8, 0x1f),\t\t\t/* multiplex ratio 1/64 Duty (0x0F~0x3F) */  \n    U8X8_CA(0xa2, 0x00),\t\t\t/* display start line */  \n\n    U8X8_C(0xa0),\t                /* Set Segment Re-Map: column address 0 mapped to SEG0  CS1 */ \n    // U8X8_C(0xa1),\t                /* Set Segment Re-Map: column address 0 mapped to SEG0  CS2 */ \n\n    U8X8_C(0xc8),\t             /* Set COM Output Scan Direction: normal mode CS1 */\n    // U8X8_C(0xc0),\t\t\t        /* Set COM Output Scan Direction: normal mode CS2 */\n    \n    U8X8_CA(0xd3, 0x72),        /* CS1 */\n    // U8X8_CA(0xd3, 0x92),        /* CS2 */\n    \n    U8X8_CA(0xda, 0x12),\t    /* Set SEG Pins Hardware Configuration:  */  \n    U8X8_CA(0x81, 0x5a),\t\t\t/* contrast */  \n    U8X8_CA(0xd9, 0x22),\t\t\t/* Set Phase Length */  \n    U8X8_CA(0xdb, 0x30),\t\t  /* VCOMH Deselect Level */\n    U8X8_CA(0xad, 0x10),\t\t\t/* Internal IREF Enable */  \n    U8X8_CA(0x20, 0x00),\t    /* Memory Addressing Mode: Horizontal */  \n    U8X8_CA(0x8d, 0x01),\t\t\t/* disable internal charge pump 1 */  \n    U8X8_CA(0xac, 0x00),\t\t\t/* disable internal charge pump 2 */  \n    U8X8_C(0xa4),\t\t        \t/* display on */  \n    U8X8_C(0xa6),\t\t          /* normal display */\n\n    U8X8_DLY(1),\t\t\t\t\t/* delay 2ms */\n\n    U8X8_END_TRANSFER(),             \t/* disable chip */\n    U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1320_160x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n        u8x8_d_helper_display_setup_memory(u8x8, &u8x8_d_ssd1320_cs1_160x32_display_info);\n      break;\n\n    case U8X8_MSG_DISPLAY_INIT:\n        u8x8_d_helper_display_init(u8x8);\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x32_init_seq);\n      break;\n\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 ){\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x32_nhd_flip0_seq);\n        u8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else{\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x32_nhd_flip1_seq);\n        u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    \n    default:\n      return u8x8_d_ssd1320_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n/*=========================================================*/\n/* 160x132 (actually 320x132) */\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x132_nhd_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t/* remap */\n  U8X8_C(0xc8),\t             /* Set COM Output Scan Direction: normal mode CS1 */\n  U8X8_CA(0xd3, 0x0e),        /* CS1 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x132_nhd_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t/* remap */\n  U8X8_C(0xc0),\t             /* Set COM Output Scan Direction: normal mode CS1 */\n  U8X8_CA(0xd3, 0x92),        /* CS1 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_d_ssd1320_cs1_160x132_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* ssd1320: 2 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* ssd1320: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* ssd1320: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 10000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 10,\n  /* write_pulse_width_ns = */ 150,\t/* ssd1320: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 20,\t\t/* 160 pixel, so we require 20 bytes for this */\n  /* tile_hight = */ 17,\n  /* default_x_offset = */ 0,\t/* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 132\n};\n\n\n/* the following sequence will work, but requires contrast to be very high */\nstatic const uint8_t u8x8_d_ssd1320_cs1_160x132_init_seq[] = {\n    \n    U8X8_DLY(1),\n    U8X8_START_TRANSFER(),    /* enable chip, delay is part of the transfer start */\n    U8X8_DLY(1),\n    \n    U8X8_C(0xae),\t\t          /* display off */\n    U8X8_CA(0xd5, 0xC2),\t\t\t/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec)  */  \n    U8X8_CA(0xa8, 0x83),\t\t\t/* multiplex ratio 1/132 Duty  */  \n    U8X8_CA(0xa2, 0x00),\t\t\t/* display start line */  \n\n    U8X8_C(0xa0),\t                /* Set Segment Re-Map: column address 0 mapped to SEG0  CS1 */ \n    // U8X8_C(0xa1),\t                /* Set Segment Re-Map: column address 0 mapped to SEG0  CS2 */ \n\n    U8X8_C(0xc8),\t             /* Set COM Output Scan Direction: normal mode CS1 */\n    // U8X8_C(0xc0),\t\t\t        /* Set COM Output Scan Direction: normal mode CS2 */\n  \n    U8X8_CA(0xd3, 0x0e),        /* CS1 */\n    // U8X8_CA(0xd3, 0x92),        /* CS2 */\n    \n    U8X8_CA(0xda, 0x12),\t    /* Set SEG Pins Hardware Configuration:  */  \n    U8X8_CA(0x81, 0x5a),\t\t\t/* contrast */  \n    U8X8_CA(0xd9, 0x22),\t\t\t/* Set Phase Length */  \n    U8X8_CA(0xdb, 0x30),\t\t  /* VCOMH Deselect Level */\n    U8X8_CA(0xad, 0x10),\t\t\t/* Internal IREF Enable */  \n    U8X8_CA(0x20, 0x00),\t    /* Memory Addressing Mode: Horizontal */  \n    U8X8_CA(0x8d, 0x01),\t\t\t/* disable internal charge pump 1 */  \n    U8X8_CA(0xac, 0x00),\t\t\t/* disable internal charge pump 2 */  \n    U8X8_C(0xa4),\t\t        \t/* display on */  \n    U8X8_C(0xa6),\t\t          /* normal display */\n\n    U8X8_DLY(1),\t\t\t\t\t/* delay 2ms */\n\n    U8X8_END_TRANSFER(),             \t/* disable chip */\n    U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/*\nOLED_WR_Byte(0xae,OLED_CMD);//Display OFF\nOLED_WR_Byte(0xfd,OLED_CMD);//Set Command Lock\nOLED_WR_Byte(0x12,OLED_CMD);\nOLED_WR_Byte(0x20,OLED_CMD);//Set Memory Addressing Mode\nOLED_WR_Byte(0x00,OLED_CMD);\nOLED_WR_Byte(0x25,OLED_CMD);//Set Portrait Addressing Mode\nOLED_WR_Byte(0x00,OLED_CMD);//Normal Addressing Mode\nOLED_WR_Byte(0x81,OLED_CMD);//Set Contrast Control\nOLED_WR_Byte(0x6b,OLED_CMD);\nOLED_WR_Byte1(0xa0,OLED_CMD,1);//Set Seg Remap LEFT DISPLAY\nOLED_WR_Byte1(0xa1,OLED_CMD,2);//Set Seg Remap RIGHT DISPLAY\nOLED_WR_Byte(0xa2,OLED_CMD);//Set Display Start Line\nOLED_WR_Byte(0x00,OLED_CMD);\nOLED_WR_Byte(0xa4,OLED_CMD);//Resume to RAM content display\nOLED_WR_Byte(0xa6,OLED_CMD);//Set Normal Display\n\nOLED_WR_Byte(0xa8,OLED_CMD);//Set MUX Ratio\nOLED_WR_Byte(0x83,OLED_CMD);//1/132 duty\n\nOLED_WR_Byte(0xad,OLED_CMD);//Select external or internal IREF\nOLED_WR_Byte(0x10,OLED_CMD);\nOLED_WR_Byte(0xbc,OLED_CMD);//Set Pre-charge voltage\nOLED_WR_Byte(0x1e,OLED_CMD);//\nOLED_WR_Byte(0xbf,OLED_CMD);//Linear LUT\nOLED_WR_Byte1(0xc8,OLED_CMD,1);//Set COM Output Scan Direction LEFT DISPLAY\nOLED_WR_Byte1(0xc0,OLED_CMD,2);//Set COM Output Scan Direction RIGHT DISPLAY\nOLED_WR_Byte(0xd3,OLED_CMD);//Set Display Offset\nOLED_WR_Byte1(0x0e,OLED_CMD,1); //LEFT DISPLAY\nOLED_WR_Byte1(0x92,OLED_CMD,2); // RIGHT DISPLAY\nOLED_WR_Byte(0xd5,OLED_CMD);//Set Display Clock Divide Ratio/Oscillator Frequency\nOLED_WR_Byte(0xc2,OLED_CMD);//85Hz\nOLED_WR_Byte(0xd9,OLED_CMD);//Set Pre-charge Period\nOLED_WR_Byte(0x72,OLED_CMD);//\nOLED_WR_Byte(0xda,OLED_CMD);//Set SEG Pins Hardware Configuration\nOLED_WR_Byte(0x32,OLED_CMD);\nOLED_WR_Byte(0xbd,OLED_CMD);//Set VP\nOLED_WR_Byte(0x03,OLED_CMD);\nOLED_WR_Byte(0xdb,OLED_CMD);//Set VCOMH\nOLED_WR_Byte(0x30,OLED_CMD);\nOLED_WR_Byte(0xaf,OLED_CMD);//Display on\n*/\nstatic const uint8_t u8x8_d_ssd1320_160x132_init_seq[] = {\n    U8X8_DLY(1),\n    U8X8_START_TRANSFER(),    /* enable chip, delay is part of the transfer start */\n    U8X8_DLY(1),\n    \n    U8X8_C(0xae),\t\t          /* display off */\n    U8X8_CA(0xd5, 0xC2),\t/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec)  */  \n    U8X8_CA(0xa8, 0x83),\t/* multiplex ratio 1/132 Duty  */  \n    U8X8_CA(0xa2, 0x00),\t/* display start line */  \n\n    U8X8_C(0xa0),\t                /* Set Segment Re-Map: column address 0 mapped to SEG0  CS1 */ \n    // U8X8_C(0xa1),\t      \t/* Set Segment Re-Map: column address 0 mapped to SEG0  CS2 */ \n\n    U8X8_C(0xc8),\t             \t/* Set COM Output Scan Direction: normal mode CS1 */\n    // U8X8_C(0xc0),\t\t/* Set COM Output Scan Direction: normal mode CS2 */\n\n    U8X8_CA(0xad, 0x10), \t\t/* select Iref: 0x00 external (reset default), 0x10 internal */\n    U8X8_CA(0xbc, 0x1e), \t\t/* pre-charge voltage level 0x00..0x1f, reset default: 0x1e */\n    U8X8_C(0xbf),\t\t        \t/* select linear LUT */  \n    U8X8_CA(0xd5, 0xc2), \t\t/* Bit 0..3: clock ratio 1, 2, 4, 8, ...256, reset=0x1, Bit 4..7: F_osc 0..15 */\n    U8X8_CA(0xd9, 0x72),\t\t/* Set Phase 1&2 Length, Bit 0..3: Phase 1, Bit 4..7: Phase 2, reset default 0x72 */  \n    U8X8_CA(0xbd, 0x03), \t\t/* from the vendor init sequence */\n    U8X8_CA(0xdb, 0x30),\t\t  /* VCOMH Deselect Level */\n\n  \n    U8X8_CA(0xd3, 0x0e),        /* CS1 */\n    // U8X8_CA(0xd3, 0x92),        /* CS2 */\n    \n    U8X8_CA(0xda, 0x12),\t/* Set SEG Pins Hardware Configuration:  */  \n    U8X8_CA(0x81, 0x6b),\t\t\t/* contrast */  \n    //U8X8_CA(0xd9, 0x22),\t\t\t/* Set Phase Length */  \n    //U8X8_CA(0xdb, 0x30),\t\t  /* VCOMH Deselect Level */\n    //U8X8_CA(0xad, 0x10),\t\t\t/* Internal IREF Enable */  \n    U8X8_CA(0x20, 0x00),\t    /* Memory Addressing Mode: Horizontal */  \n    //U8X8_CA(0x8d, 0x01),\t\t\t/* unknown in SSD1320 datasheet, disable internal charge pump 1 */  \n    //U8X8_CA(0xac, 0x00),\t\t\t/* unknown in SSD1320 datasheet, disable internal charge pump 2 */  \n    U8X8_C(0xa4),\t\t        \t/* display RAM on */  \n    U8X8_C(0xa6),\t\t          /* normal display */\n\n    U8X8_DLY(1),\t\t\t\t\t/* delay 2ms */\n\n    U8X8_END_TRANSFER(),             \t/* disable chip */\n    U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1320_160x132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n        u8x8_d_helper_display_setup_memory(u8x8, &u8x8_d_ssd1320_cs1_160x132_display_info);\n    \n      break;\n\n    case U8X8_MSG_DISPLAY_INIT:\n        u8x8_d_helper_display_init(u8x8);\n       // u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_init_seq);\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_160x132_init_seq);\n      break;\n\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 ){\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_nhd_flip0_seq);\n        u8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else{\n        u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1320_cs1_160x132_nhd_flip1_seq);\n        u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    \n    default:\n      return u8x8_d_ssd1320_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1322.c",
    "content": "/*\n\n  u8x8_d_ssd1322.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  SSD1322: \n    480 x 128 dot matrix\n    16 gray scale\n  \n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_ssd1322_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* ssd1322: display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1322_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* ssd1322: display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n/* interpret b as a monochrome bit pattern, write value 15 for high bit and value 0 for a low bit */\n/* topbit (msb) is sent last */\n/* example: b = 0x083 will send 0xff, 0x00, 0x00, 0xf0 */\n\n/* 4 Jan 2017: I think this procedure not required any more. Delete? */\n/*\nstatic uint8_t u8x8_write_byte_to_16gr_device(u8x8_t *u8x8, uint8_t b)\n{\n  static uint8_t buf[4];\n  static uint8_t map[4] = { 0, 0x00f, 0x0f0, 0x0ff };\n  buf [3] = map[b & 3];\n  b>>=2;\n  buf [2] = map[b & 3];\n  b>>=2;\n  buf [1] = map[b & 3];\n  b>>=2;\n  buf [0] = map[b & 3];\n  return u8x8_cad_SendData(u8x8, 4, buf);\n}\n*/\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for SSD1325 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_ssd1322_to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1322_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1322_to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1322_to32_dest_buf;\n}\n\nstatic uint8_t *u8x8_ssd1322_4to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1322_to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v = 0xff;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1322_to32_dest_buf;\n}\n\n\nuint8_t u8x8_d_ssd1322_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x; \n  uint8_t y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_256x64_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x0C1 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1322 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 2;\t\t// only every 4th col can be addressed\n      x += u8x8->x_offset;\t\t\n    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y *= 8;\n    \n      \n      u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address, moved out of the loop (issue 302) */\n      u8x8_cad_SendArg(u8x8, y);\n      u8x8_cad_SendArg(u8x8, y+7);\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n\t  u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t  u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t  u8x8_cad_SendArg(u8x8, x+1 );\t/* end */\n\n\t  u8x8_cad_SendCmd(u8x8, 0x05c );\t/* write to ram */\n\t  \n\t  u8x8_cad_SendData(u8x8, 32, u8x8_ssd1322_8to32(u8x8, ptr));\n\t  \n\t  ptr += 8;\n\t  x += 2;\n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 2;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=========================================================*/\n\nstatic const uint8_t u8x8_d_ssd1322_256x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAA(0x0a0, 0x006, 0x011),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1322_256x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAA(0x0a0, 0x014, 0x011),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_ssd1322_256x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1322: 2 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1322: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1322: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 10000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 10,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1322: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 32,\t\t/* 256 pixel, so we require 32 bytes for this */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0x01c,\t/* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */\n  /* flipmode_x_offset = */ 0x01c,\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_ssd1322_256x64_init_seq[] = {\n    \n  U8X8_DLY(1),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(1),\n  \n  U8X8_CA(0xfd, 0x12),            \t/* unlock */\n  U8X8_C(0xae),\t\t                /* display off */\n  U8X8_CA(0xb3, 0x91),\t\t\t/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec)  */  \n  U8X8_CA(0xca, 0x3f),\t\t\t/* multiplex ratio 1/64 Duty (0x0F~0x3F) */  \n  U8X8_CA(0xa2, 0x00),\t\t\t/* display offset, shift mapping ram counter */  \n  U8X8_CA(0xa1, 0x00),\t\t\t/* display start line */  \n  //U8X8_CAA(0xa0, 0x14, 0x11),\t/* Set Re-Map / Dual COM Line Mode */  \n  U8X8_CAA(0xa0, 0x06, 0x011),\t/* Set Re-Map / Dual COM Line Mode */  \n  U8X8_CA(0xab, 0x01),\t\t\t/* Enable Internal VDD Regulator */  \n  U8X8_CAA(0xb4, 0xa0, 0x005|0x0fd),\t/* Display Enhancement A */  \n  U8X8_CA(0xc1, 0x9f),\t\t\t/* contrast */  \n  U8X8_CA(0xc7, 0x0f),\t\t\t/* Set Scale Factor of Segment Output Current Control */  \n  U8X8_C(0xb9),\t\t                /* linear grayscale */\n  U8X8_CA(0xb1, 0xe2),\t\t\t/* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */  \n  U8X8_CAA(0xd1, 0x082|0x020, 0x020),\t/* Display Enhancement B */  \n  U8X8_CA(0xbb, 0x1f),\t\t\t/* precharge  voltage */  \n  U8X8_CA(0xb6, 0x08),\t\t\t/* precharge  period */  \n  U8X8_CA(0xbe, 0x07),\t\t\t/* vcomh */  \n  U8X8_C(0xa6),\t\t                /* normal display */\n  U8X8_C(0xa9),\t\t                /* exit partial display */\n\n\n  U8X8_DLY(1),\t\t\t\t\t/* delay 2ms */\n\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1322_nhd_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1322_256x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_256x64_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_256x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_256x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    \n    default:\n      return u8x8_d_ssd1322_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n/*=========================================================*/\n/* \n  NHD-2.7-12864WDW3-M \n  http://www.newhavendisplay.com/nhd2712864wdw3m-p-9546.html\n  http://www.newhavendisplay.com/specs/NHD-2.7-12864WDW3-M.pdf\n\n  It looks like that only every second pixel is connected to the OLED\n*/\n\nuint8_t u8x8_d_ssd1322_common2(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x; \n  uint8_t y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_256x64_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x0C1 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1322 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 2;\t\t// only every 4th col can be addressed\n      x *= 2;\t\t// only every second pixel is used in the 128x64 NHD OLED \n    \n      x += u8x8->x_offset;\n    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y *= 8;\n          \n      u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address, moved out of the loop (issue 302) */\n      u8x8_cad_SendArg(u8x8, y);\n      u8x8_cad_SendArg(u8x8, y+7);\n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n\t  u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t  u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t  u8x8_cad_SendArg(u8x8, x+1 );\t/* end */\n\t  u8x8_cad_SendCmd(u8x8, 0x05c );\t/* write to ram */\t  \n\t  u8x8_cad_SendData(u8x8, 32, u8x8_ssd1322_4to32(u8x8, ptr));\t  \n\t  ptr += 4;\n\t  x += 2;\n\t  \n\t  u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t  u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t  u8x8_cad_SendArg(u8x8, x+1 );\t/* end */\n\t  u8x8_cad_SendCmd(u8x8, 0x05c );\t/* write to ram */\t  \n\t  u8x8_cad_SendData(u8x8, 32, u8x8_ssd1322_4to32(u8x8, ptr));\t  \n\t  ptr += 4;\n\t  x += 2;\n\t  \n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 2;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const uint8_t u8x8_d_ssd1322_128x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAA(0x0a0, 0x016, 0x011),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1322_128x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAA(0x0a0, 0x004, 0x011),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_ssd1322_128x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t/* SSD1322: 2 us */\n  /* post_reset_wait_ms = */ 100, /* far east OLEDs need much longer setup time */\n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1322: 15ns, but cycle time is 100ns, so use 100/2 */\n  /* sck_pulse_width_ns = */ 50,\t/* SSD1322: 20ns, but cycle time is 100ns, so use 100/2, AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 10000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns, increased to 8MHz (issue 215), 10 MHz (issue 301) */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 10,\n  /* write_pulse_width_ns = */ 150,\t/* SSD1322: cycle time is 300ns, so use 300/2 = 150 */\n  /* tile_width = */ 16,\t\t/* 128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 28,\t/* this is the byte offset (there are two pixel per byte with 4 bit per pixel) */\n  /* flipmode_x_offset = */ 28,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_ssd1322_128x64_init_seq[] = {\n    \n  U8X8_DLY(1),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(1),\n  \n  U8X8_CA(0xfd, 0x12),            \t/* unlock */\n  U8X8_C(0xae),\t\t                /* display off */\n  U8X8_CA(0xb3, 0x91),\t\t\t/* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec)  */  \n  U8X8_CA(0xca, 0x3f),\t\t\t/* multiplex ratio 1/64 Duty (0x0F~0x3F) */  \n  U8X8_CA(0xa2, 0x00),\t\t\t/* display offset, shift mapping ram counter */  \n\n  U8X8_CA(0xa1, 0x00),\t\t\t/* display start line */  \n  U8X8_CA(0xab, 0x01),\t\t\t/* Enable Internal VDD Regulator */  \n  //U8X8_CAA(0xa0, 0x14, 0x11),\t/* Set Re-Map / Dual COM Line Mode */  \n  //U8X8_CAA(0xa0, 0x06, 0x011),\t/* Set Re-Map / Dual COM Line Mode */  \n  U8X8_CAA(0xa0, 0x16, 0x011),\t/* Set Re-Map / Dual COM Line Mode (NHD-2.7-12864WDW3-M datasheet) */  \n  U8X8_CA(0xc7, 0x0f),\t\t\t/* Set Scale Factor of Segment Output Current Control */  \n  U8X8_CA(0xc1, 0x9f),\t\t\t/* contrast */  \n  //U8X8_CA(0xb1, 0xe2),\t\t\t/* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */  \n  U8X8_CA(0xb1, 0xf2),\t\t\t/* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment (NHD-2.7-12864WDW3-M datasheet) */  \n  U8X8_CA(0xbb, 0x1f),\t\t\t/* precharge  voltage */    \n  //U8X8_CAA(0xb4, 0xa0, 0x005|0x0fd),\t/* Display Enhancement A */  \n  U8X8_CAA(0xb4, 0xa0, 0x0fd),\t/* Display Enhancement A (NHD-2.7-12864WDW3-M datasheet) */  \n  U8X8_CA(0xbe, 0x04),\t\t\t/* vcomh (NHD-2.7-12864WDW3-M datasheet) */  \n  U8X8_C(0xb9),\t\t                /* linear grayscale */\n  //U8X8_CAA(0xd1, 0x082|0x020, 0x020),\t/* Display Enhancement B */  \n  //U8X8_CA(0xb6, 0x08),\t\t\t/* precharge  period */  \n  U8X8_C(0xa6),\t\t                /* normal display */\n  U8X8_C(0xa9),\t\t                /* exit partial display */\n\n\n  U8X8_DLY(1),\t\t\t\t\t/* delay 2ms */\n\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1322_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1322_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_128x64_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_128x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1322_128x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n    \n    default:\n      return u8x8_d_ssd1322_common2(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1325.c",
    "content": "/*\n\n  u8x8_d_ssd1325.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  SSD1325:\n    128 x 80, 16 Gray Scale Dot Matrix\n    \n  SSD0323: Identical to SSD1325, issue 720\n    \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_ssd1325_128x64_nhd_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1325_128x64_nhd_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1325_128x64_nhd_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x052),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1325_128x64_nhd_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x041),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for SSD1325 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_ssd1325_8to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1325_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1325_8to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1325_8to32_dest_buf;\n}\n\n\n/*===================================================================*/\n\nstatic uint8_t u8x8_d_ssd1325_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1325_128x64_nhd_display_info);\n      break;\n    */\n    \n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_powersave1_seq);\n      break;\n      \n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n      */\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1325 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 4;\n    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y *= 8;\n      y += u8x8->x_offset;\t\t/* x_offset is used as y offset for the SSD1325 */\n    \n\n      u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address */\n      u8x8_cad_SendArg(u8x8, y);\n      u8x8_cad_SendArg(u8x8, y+7);\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n\t  if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] )\n\t  {\n\t    /* draw the tile if pattern is not zero for all bytes */\n\t    u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t    u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t    u8x8_cad_SendArg(u8x8, x+3 );\t/* end */\n\n\t    \n\t    \n\t    u8x8_cad_SendData(u8x8, 32, u8x8_ssd1325_8to32(u8x8, ptr));\n\t  }\n\t  else\n\t  {\n\t    /* tile is empty, use the graphics acceleration command */\n\t    u8x8_cad_SendCmd(u8x8, 0x024 );\t// draw rectangle\n\t    u8x8_cad_SendArg(u8x8, x );\t\n\t    u8x8_cad_SendArg(u8x8, y );\t\n\t    u8x8_cad_SendArg(u8x8, x+3 );\t\n\t    u8x8_cad_SendArg(u8x8, y+7 );\t\n\t    u8x8_cad_SendArg(u8x8, 0 );\t// clear\t    \n\t  }\n\t  ptr += 8;\n\t  x += 4;\n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 4;\n\targ_int--;\n      } while( arg_int > 0 );\n\n      u8x8_cad_SendCmd(u8x8, 0xe3); // no-op needs to be sent after last byte before cs is toggled.\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*===================================================================*/\n\n/* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */\nstatic const uint8_t u8x8_d_ssd1325_128x64_nhd_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0b3, 0x091),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio: 0x03f * 1/64 duty */\n  U8X8_CA(0x0a2, 0x04c),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  U8X8_CA(0x0a0, 0x052),\t\t/* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */\n  U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n  U8X8_C(0x0b8),\t\t\t\t/* set gray scale table */\n    U8X8_A(0x001),\t\t\t\t/* */\n    U8X8_A(0x011),\t\t\t\t/* */\n    U8X8_A(0x022),\t\t\t\t/* */\n    U8X8_A(0x032),\t\t\t\t/* */\n    U8X8_A(0x043),\t\t\t\t/* */\n    U8X8_A(0x054),\t\t\t\t/* */\n    U8X8_A(0x065),\t\t\t\t/* */\n    U8X8_A(0x076),\t\t\t\t/* */\n    \n  U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128, Newhaven: 0x040 */\n  U8X8_CA(0x0b2, 0x051),\t\t/* frame frequency (row period) */\n  U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0b4, 0x002),                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0b0, 0x028),                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0bf, 0x002|0x00d),           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_CA(0x023, 0x003),\t\t/* graphics accelleration: fill pixel */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_nhd_ssd1325_128x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* SSD1325  */\n  /* sck_pulse_width_ns = */ 100,\t/* SSD1325  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t/* SSD1325 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the SSD1325 */\n  /* flipmode_x_offset = */ 8,\t\t/* x_offset is used as y offset for the SSD1325 */\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ssd1325_nhd_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_nhd_ssd1325_128x64_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_init_seq);    \n      return 1;\n    }    \n    else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n    {\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1325_128x64_nhd_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      return 1;\n    }\n    return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n/*===================================================================*/\n/* OSRAM Pictiva 128x64 OLED */\n/* https://github.com/olikraus/u8g2/issues/720 */\n\nstatic const uint8_t u8x8_d_ssd0323_os128064_init_seq[] = {\n\n  U8X8_START_TRANSFER(),                     /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),                                /* display off */\n  U8X8_CA(0x0b3, 0x091),                /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\n  U8X8_CA(0x0a8, 0x03f),                /* multiplex ratio: 0x03f * 1/64 duty */\n  U8X8_CA(0x0a2, 0x040),                /* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a1, 0x000),                /* display start line */\n  U8X8_CA(0x0ad, 0x002),                /* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  U8X8_CA(0x0a0, 0x052),                /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */\n  U8X8_C(0x086),                                /* full current range (0x084, 0x085, 0x086) */\n  U8X8_C(0x0b8),                                /* set gray scale table */\n    U8X8_A(0x001),                                /* */\n    U8X8_A(0x011),                                /* */\n    U8X8_A(0x022),                                /* */\n    U8X8_A(0x032),                                /* */\n    U8X8_A(0x043),                                /* */\n    U8X8_A(0x054),                                /* */\n    U8X8_A(0x065),                                /* */\n    U8X8_A(0x076),                                /* */\n\n  U8X8_CA(0x081, 0x070),                /* contrast, brightness, 0..128, Newhaven: 0x040 */\n  U8X8_CA(0x0b2, 0x051),                /* frame frequency (row period) */\n  U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0b4, 0x002),                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0b0, 0x028),                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0bf, 0x002|0x00d),           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_C(0x0a4),                                /* normal display mode */\n\n  U8X8_CA(0x023, 0x003),                /* graphics accelleration: fill pixel */\n\n  U8X8_END_TRANSFER(),                     /* disable chip */\n  U8X8_END()                                     /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd0323_os128064_flip0_seq[] = {\n  U8X8_START_TRANSFER(),                     /* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x052),                /* remap */\n  U8X8_CA(0x0a2, 0x040),                /* display offset, shift mapping ram counter */\n  U8X8_END_TRANSFER(),                     /* disable chip */\n  U8X8_END()                                     /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd0323_os128064_flip1_seq[] = {\n  U8X8_START_TRANSFER(),                     /* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x041),                /* remap */\n  U8X8_CA(0x0a2, 0x050),                /* display offset, shift mapping ram counter */\n  U8X8_END_TRANSFER(),                     /* disable chip */\n  U8X8_END()                                     /* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_ssd0323_os128064_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* SSD1325  */\n  /* sck_pulse_width_ns = */ 100,\t/* SSD1325  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t/* SSD1325 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the SSD1325 */\n  /* flipmode_x_offset = */ 0,\t\t/* x_offset is used as y offset for the SSD1325 */\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_ssd0323_os128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd0323_os128064_display_info);\n      return 1;\n    }\n    else if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_init_seq);\n      return 1;\n    }    \n    else if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n    {\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd0323_os128064_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      return 1;\n    }\n    return u8x8_d_ssd1325_128x64_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1326.c",
    "content": "/*\n\n  u8x8_d_ssd1326.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n/* ER OLED */\nstatic const uint8_t u8x8_d_ssd1326_er_256x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock (not required, this is default by reset) */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0a8, 0x01f),\t\t/* multiplex ratio: 0x03f * 1/64 duty - changed by CREESOO, acc. to datasheet, 100317*/ \n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  /*\n    a0 command: 0x0a0 ***abcde\n      a: 1: mono mode\n      b: 0: horizontal (1: vertical) address increment\n      c: 1: enable bit remap\n      d: 1: COM remap\n      e: 1: Column remap\n  */\n  U8X8_CA(0x0a0, 0x006),\t\t/* remap configuration, see above */\n  U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n\n  U8X8_C(0x0b7),\t\t\t\t/* set default gray scale table */\n    \n  U8X8_CA(0x081, 0x027),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x0b1, 0x071),                    /* phase length */\n  //U8X8_CA(0x0b2, 0x051),\t\t/* frame frequency (row period) */\n  U8X8_CA(0x0b3, 0x0f0),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  //U8X8_CA(0x0b4, 0x002),                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  //U8X8_CA(0x0b0, 0x028),                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CAA(0x0bb, 0x035, 0x0ff),                     /* set precharge */\n  U8X8_CA(0x0bc, 0x01f),                    /* pre-charge voltage level */\n  U8X8_CA(0x0be, 0x00f),                     /* VCOMH voltage */\n  U8X8_CA(0x0bf, 0x002|0x00d),           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  //U8X8_CA(0x023, 0x003),\t\t/* graphics accelleration: fill pixel */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1326_256x32_nhd_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1326_256x32_nhd_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1326_256x32_nhd_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x006),\t\t/* remap 00110 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1326_256x32_nhd_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  //U8X8_CA(0x0a0, 0x005),\t\t/* remap 00101 */\n  U8X8_CA(0x0a0, 0x001),\t\t/* remap 00001 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for ssd1326 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_ssd1326_8to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1326_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1326_8to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1326_8to32_dest_buf;\n}\n\n\n\n\nstatic uint8_t u8x8_d_ssd1326_256x32_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1326_256x32_nhd_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_er_256x32_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1326_256x32_nhd_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1326 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 4;\n      \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      \n      y *= 8;\n      y += u8x8->x_offset;\t\t/* x_offset is used as y offset for the ssd1326 */\n    \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n          u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n          u8x8_cad_SendArg(u8x8, x );\t/* start */\n          u8x8_cad_SendArg(u8x8, x+3 );\t/* end */\n\n          u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address */\n          u8x8_cad_SendArg(u8x8, y);\n          u8x8_cad_SendArg(u8x8, y+7);\n          \n          u8x8_cad_SendData(u8x8, 32, u8x8_ssd1326_8to32(u8x8, ptr));\n          \n\t  ptr += 8;\n\t  x += 4;\n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 4;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1326_256x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 15,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* ssd1326  */\n  /* sck_pulse_width_ns = */ 100,\t/* ssd1326  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t/* ssd1326 */\n  /* tile_width = */ 32,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* flipmode_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 32\n};\n\nuint8_t u8x8_d_ssd1326_er_256x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1326_256x32_display_info);\n      return 1;\n    }\n    return u8x8_d_ssd1326_256x32_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1327.c",
    "content": "/*\n\n  u8x8_d_ssd1327.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\nstatic const uint8_t u8x8_d_ssd1327_96x96_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_96x96_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1327_seeed_96x96_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x020),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_seeed_96x96_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x060),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1327_winstar_96x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_winstar_96x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  U8X8_CA(0x0a2, 0x040),\t\t/* display offset, shift mapping ram counter */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for ssd1327 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_ssd1327_8to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1327_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1327_8to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1327_8to32_dest_buf;\n}\n\n\n\n\nstatic uint8_t u8x8_d_ssd1327_96x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_96x96_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1327 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 4;\n      x+=u8x8->x_offset/2;\n    \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y *= 8;\n    \n      u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address, moved out of the loop (issue 302) */\n      u8x8_cad_SendArg(u8x8, y);\n      u8x8_cad_SendArg(u8x8, y+7);\n\t  \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n\t  u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t  u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t  u8x8_cad_SendArg(u8x8, x+3 );\t/* end */\n\n\t  \n\t  u8x8_cad_SendData(u8x8, 32, u8x8_ssd1327_8to32(u8x8, ptr));\n\t  ptr += 8;\n\t  x += 4;\n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 4;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=============================================*/\n/*\n  Winstar WEA009664B 96x64 OLED Display, 1.1 inch OLED\n  https://www.winstar.com.tw/products/oled-module/graphic-oled-display/96x64-oled.html\n\n  https://github.com/olikraus/u8g2/issues/1050\n*/\n\nstatic const u8x8_display_info_t u8x8_ssd1327_winstar_96x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* */\n  /* sck_pulse_width_ns = */ 100,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\t/* use 1 instead of 4, because the SSD1327 seems to be very slow */\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t\n  /* tile_width = */ 12,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 16,\t\t/* changed to 16, issue 1050 */\n  /* flipmode_x_offset = */ 16,\t\t/* changed to 16, issue 1050 */\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 64\n};\n\n/*\n\tWrite_Cmd(0xAE);\t//Set Display Off     OK\n\tWrite_Cmd(0x81);\t//Contrast Level  OK\n  \tWrite_Cmd(0xdF);\t//\t\t\tVALUE WRONG????\n\tWrite_Cmd(0xD9);\t//Pre-charge Period\n  \tWrite_Cmd(0x00);\n\tWrite_Cmd(0xA0);\t//Set Re-map\t\tOK\n\tWrite_Cmd(0x42);\t//Default Setting\tOK\n\tWrite_Cmd(0xA1);\t//Set Display Start Line\tOK\n\tWrite_Cmd(0x00);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xA2);\t//Set Display Offset\t\tOK\n\tWrite_Cmd(0x00);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xA4);\t//Set Display Mode\t\tOK\n\tWrite_Cmd(0xA8);\t//Set Multiplex Ratio     \tOK\n\tWrite_Cmd(0x63);\t//Multiplex\t\t\tOK\n\tWrite_Cmd(0xAB);\t//Set Function SelectionA OK\n\tWrite_Cmd(0x01);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xB1);\t//Set Phase Length\t\tOK\n\tWrite_Cmd(0x47);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xB3);\t//Set Display Clock Divide Ratio/Oscillator Frequency\tOK\n\tWrite_Cmd(0x00);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xBC);\t//Set Prechange Voltage\tOK\n\tWrite_Cmd(0x07);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xBE);\t//Set VCOMH Voltage\tOK\n\tWrite_Cmd(0x07);\t\t\t\t\t\tOK\n\tWrite_Cmd(0xB6);\t//Set Second Pre-charge period\tOK\n\tWrite_Cmd(0x04);\t\t\t\t\t\t\t\tOK\n\tWrite_Cmd(0xD5);\t//Set Function selection B\t\tOK\n\tWrite_Cmd(0x62);\t\t\t\t\t\t\t\tOK\n\tWrite_Cmd(0xAF);\t//Set Display On\n\n*/\n\nstatic const uint8_t u8x8_d_ssd1327_winstar_96x64_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock display, usually not required because the display is unlocked after reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  \n  U8X8_CA(0x0d9, 0x000),\t\t/* Pre-charge Period ??? */\n  \n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */  \n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  \n  U8X8_CA(0x0a8, 0x063),\t\t/* multiplex ratio: 63* 1/64 duty */ /* changed to hex, issue 1050 */\n  \n  U8X8_CA(0x0ab, 0x001),\t\t/* Enable internal VDD regulator (RESET) */\n  U8X8_CA(0x081, 0x053),\t\t/* contrast, brightness, 0..128 */\n  \n  U8X8_CA(0x0b1, 0x047),                    /* phase length */  \n  //U8X8_CA(0x0b3, 0x001),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  U8X8_CA(0x0b3, 0x000),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  \n  U8X8_C(0x0b9),\t\t\t\t/* use linear lookup table */\n\n  U8X8_CA(0x0bc, 0x007),                    /* pre-charge voltage level */\n  U8X8_CA(0x0be, 0x007),                     /* VCOMH voltage */\n  U8X8_CA(0x0b6, 0x004),\t\t/* second precharge */\n  U8X8_CA(0x0d5, 0x062),\t\t/* enable second precharge, internal vsl (bit0 = 0) */\n  \n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1327_ws_96x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_winstar_96x64_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_winstar_96x64_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n/*=============================================*/\n/*  Seeedstudio Grove OLED 96x96 */\n\nstatic const u8x8_display_info_t u8x8_ssd1327_96x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* */\n  /* sck_pulse_width_ns = */ 100,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\t/* use 1 instead of 4, because the SSD1327 seems to be very slow */\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t\n  /* tile_width = */ 12,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 16,\n  /* flipmode_x_offset = */ 16,\t\t\n  /* pixel_width = */ 96,\n  /* pixel_height = */ 96\n};\n\n/*  https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */\n/*  http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */\n/* values from u8glib */\n/*\n  Re-map setting in Graphic Display Data RAM, command 0x0a0\n    Bit 0: Column Address Re-map\n    Bit 1: Nibble Re-map\n    Bit 2: Horizontal/Vertical Address Increment\n    Bit 3: Not used, must be 0\n    \n    Bit 4: COM Re-map\n    Bit 5: Not used, must be 0\n    Bit 6: COM Split Odd Even\n    Bit 7: Not used, must be 0\n*/\n\n\nstatic const uint8_t u8x8_d_ssd1327_96x96_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock display, usually not required because the display is unlocked after reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio: 0x03f * 1/64 duty */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio: 0x05f * 1/64 duty */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  //U8X8_CA(0x0a2, 0x04c),\t\t/* display offset, shift mapping ram counter */\n  \n  U8X8_CA(0x0a2, 0x020),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  \n  \n  U8X8_CA(0x0ab, 0x001),\t\t/* Enable internal VDD regulator (RESET) */\n  //U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x081, 0x053),\t\t/* contrast, brightness, 0..128 */\n  //U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0b1, 0x051),                    /* phase length */  \n  //U8X8_CA(0x0b3, 0x091),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  U8X8_CA(0x0b3, 0x001),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  \n  //? U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  //? U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n  \n  U8X8_C(0x0b9),\t\t\t\t/* use linear lookup table */\n\n  //U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0bc, 0x008),                    /* pre-charge voltage level */\n  //U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0be, 0x007),                     /* VCOMH voltage */\n  U8X8_CA(0x0b6, 0x001),\t\t/* second precharge */\n  U8X8_CA(0x0d5, 0x062),\t\t/* enable second precharge, internal vsl (bit0 = 0) */\n\n\n  \n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\nuint8_t u8x8_d_ssd1327_seeed_96x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_96x96_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_96x96_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_seeed_96x96_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_seeed_96x96_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n/*=============================================*/\n/*  EA W128128 round OLED 128x128 */\n/* issue #641 */\n/* https://www.lcd-module.de/fileadmin/eng/pdf/grafik/W128128-XR.pdf */\n\nstatic const u8x8_display_info_t u8x8_ssd1327_ea_w128128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* */\n  /* sck_pulse_width_ns = */ 100,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\t/* use 1 instead of 4, because the SSD1327 seems to be very slow */\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\t\t\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\n/* this is a copy of the init sequence for the seeed 96x96 oled */\nstatic const uint8_t u8x8_d_ssd1327_ea_w128128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock display, usually not required because the display is unlocked after reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio: 0x03f * 1/64 duty */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio: 0x05f * 1/64 duty */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  //U8X8_CA(0x0a2, 0x04c),\t\t/* display offset, shift mapping ram counter */\n  \n  U8X8_CA(0x0a2, 0x010),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  \n  \n  U8X8_CA(0x0ab, 0x001),\t\t/* Enable internal VDD regulator (RESET) */\n  //U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x081, 0x053),\t\t/* contrast, brightness, 0..128 */\n  //U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0b1, 0x051),                    /* phase length */  \n  //U8X8_CA(0x0b3, 0x091),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  U8X8_CA(0x0b3, 0x001),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  \n  //? U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  //? U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n  \n  U8X8_C(0x0b9),\t\t\t\t/* use linear lookup table */\n\n  //U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0bc, 0x008),                    /* pre-charge voltage level */\n  //U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0be, 0x007),                     /* VCOMH voltage */\n  U8X8_CA(0x0b6, 0x001),\t\t/* second precharge */\n  U8X8_CA(0x0d5, 0x062),\t\t/* enable second precharge, internal vsl (bit0 = 0) */\n  \n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\nstatic const uint8_t u8x8_d_ssd1327_ea_w128128_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_ea_w128128_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1327_ea_w128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_ea_w128128_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n/*=============================================*/\n/*  MIDAS MCOT128128C1V-YM 128x128 Module */\n\n\nstatic const u8x8_display_info_t u8x8_ssd1327_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* */\n  /* sck_pulse_width_ns = */ 100,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\t/* use 1 instead of 4, because the SSD1327 seems to be very slow, Update 9 Aug 2019: The OLED from aliexpress supports 400kHz */\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\t\t\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\n/*  https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */\n/*  http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */\n/* values from u8glib */\n/*\n  Re-map setting in Graphic Display Data RAM, command 0x0a0\n    Bit 0: Column Address Re-map\n    Bit 1: Nibble Re-map\n    Bit 2: Horizontal/Vertical Address Increment\n    Bit 3: Not used, must be 0\n    \n    Bit 4: COM Re-map\n    Bit 5: Not used, must be 0\n    Bit 6: COM Split Odd Even\n    Bit 7: Not used, must be 0\n*/\n\n\nstatic const uint8_t u8x8_d_ssd1327_128x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n\t\n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock display, usually not required because the display is unlocked after reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio: 0x03f * 1/64 duty */\n  //U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio: 0x05f * 1/64 duty */\n  U8X8_CA(0x0a8, 0x07f),       \t\t /* multiplex ratio: 0x05f * 1/128duty */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  //U8X8_CA(0x0a2, 0x04c),\t\t/* display offset, shift mapping ram counter */\n  \n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  \n  \n  U8X8_CA(0x0ab, 0x001),\t\t/* Enable internal VDD regulator (RESET) */\n  //U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x081, 0x053),\t\t/* contrast, brightness, 0..128 */\n  //U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0b1, 0x051),                    /* phase length */  \n  //U8X8_CA(0x0b3, 0x091),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  U8X8_CA(0x0b3, 0x001),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  \n  //? U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  //? U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n  \n  U8X8_C(0x0b9),\t\t\t\t/* use linear lookup table */\n\n  //U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0bc, 0x008),                    /* pre-charge voltage level */\n  //U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0be, 0x007),                     /* VCOMH voltage */\n  U8X8_CA(0x0b6, 0x001),\t\t/* second precharge */\n  U8X8_CA(0x0d5, 0x062),\t\t/* enable second precharge, internal vsl (bit0 = 0) */\n\n\n  \n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1327_128x128_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_128x128_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1327_midas_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call the 96x96 procedure at the moment */\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x128_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_init_seq); \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x128_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n/*=============================================*/\n/*  \n  Waveshare 128x128 Module \n  https://www.waveshare.com/w/upload/8/80/1.5inch_OLED_Module_User_Manual_EN.pdf\n  https://github.com/olikraus/u8g2/issues/880\n\n  This is mostly a takeover of the EA display.\n*/\n\n/*  https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */\n/*  http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */\n/* values from u8glib */\n/*\n  Re-map setting in Graphic Display Data RAM, command 0x0a0\n    Bit 0: Column Address Re-map\n    Bit 1: Nibble Re-map\n    Bit 2: Horizontal/Vertical Address Increment\n    Bit 3: Not used, must be 0\n    \n    Bit 4: COM Re-map\n    Bit 5: Not used, must be 0\n    Bit 6: COM Split Odd Even\n    Bit 7: Not used, must be 0\n*/\n\n/* takeover from https://github.com/olikraus/u8g2/issues/880 */\nstatic const uint8_t u8x8_d_ssd1327_ws_128x128_init_seq[] = {\n    \n    U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n    U8X8_C(0x0ae), //--turn off oled panel\n    U8X8_CAA(0x015, 0x000, 0x07f),    //set column address, start column 0, end column 127\n    U8X8_CAA(0x075, 0x000, 0x07f),    //set row address, start row 0, end row 127\n    U8X8_CA(0x081, 0x080),    //set contrast control\n    U8X8_CA(0x0a0, 0x051),    //gment remap, 51\n    U8X8_CA(0x0a1, 0x000),    //start line\n    U8X8_CA(0x0a2, 0x000),    //display offset\n    U8X8_CAA(0x0a4, 0x0a8, 0x07f),    //rmal display, set multiplex ratio\n    U8X8_CA(0x0b1, 0x0f1),    //set phase leghth\n    U8X8_CA(0x0b3, 0x000),    //set dclk, 80Hz:0xc1 90Hz:0xe1   100Hz:0x00   110Hz:0x30 120Hz:0x50   130Hz:0x70     01\n    U8X8_CA(0x0ab, 0x001),    //\n    U8X8_CA(0x0b6, 0x00f),    //set phase leghth\n    U8X8_CA(0x0be, 0x00f),\n    U8X8_CA(0x0bc, 0x008),\n    U8X8_CA(0x0d5, 0x062),\n    U8X8_CA(0x0fd, 0x012),\n\n    U8X8_END_TRANSFER(),             \t/* disable chip */\n    U8X8_END()             \t\t\t/* end of sequence */\n  };\n\n\nuint8_t u8x8_d_ssd1327_ws_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call the 96x96 procedure at the moment */\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_ea_w128128_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ws_128x128_init_seq); \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_ea_w128128_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n\n\n/*=============================================*/\n/*  \nVisonox VGM128096A4W10 128x96 COB \nhttps://github.com/olikraus/u8g2/files/4052919/M02289_VGM128096A4W10_Y02.pdf\nhttps://github.com/olikraus/u8g2/issues/1090\n*/\n\n\nstatic const u8x8_display_info_t u8x8_ssd1327_128x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 10,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* */\n  /* sck_pulse_width_ns = */ 100,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\t/* use 1 instead of 4, because the SSD1327 seems to be very slow, Update 9 Aug 2019: The OLED from aliexpress supports 400kHz */\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t\n  /* tile_width = */ 16,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\t\t\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 96\n};\n\n/*  https://github.com/SeeedDocument/Grove_OLED_1.12/raw/master/resources/LY120-096096.pdf */\n/*  http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96 */\n/* values from u8glib */\n/*\n  Re-map setting in Graphic Display Data RAM, command 0x0a0\n    Bit 0: Column Address Re-map\n    Bit 1: Nibble Re-map\n    Bit 2: Horizontal/Vertical Address Increment\n    Bit 3: Not used, must be 0\n    \n    Bit 4: COM Re-map\n    Bit 5: Not used, must be 0\n    Bit 6: COM Split Odd Even\n    Bit 7: Not used, must be 0\n*/\n\n/* init values from the Visionox datasheeet section 10.4 */\n\nstatic const uint8_t u8x8_d_ssd1327_128x96_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n\t\n  U8X8_CA(0x0fd, 0x012),\t\t/* unlock display, usually not required because the display is unlocked after reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  //U8X8_CA(0x0a8, 0x03f),\t\t/* multiplex ratio: 0x03f * 1/64 duty */\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio: 0x05f * 1/64 duty */\n  //U8X8_CA(0x0a8, 0x07f),       \t\t /* multiplex ratio: 0x05f * 1/128duty */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  //U8X8_CA(0x0a2, 0x04c),\t\t/* display offset, shift mapping ram counter */\n  \n  U8X8_CA(0x0a2, 0x020),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  \n  \n  U8X8_CA(0x0ab, 0x001),\t\t/* Enable internal VDD regulator (RESET) */\n  //U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x081, 0x0df),\t\t/* contrast, brightness, 0..128 (0xdf as per datasheet) */\n  U8X8_CA(0x0b1, 0x022),                    /* phase length */  \n  U8X8_CA(0x0b3, 0x050),\t\t/* set display clock divide ratio/oscillator frequency  */\t\t\t\n  \n  //? U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  //? U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n  \n  U8X8_C(0x0b9),\t\t\t\t/* use linear lookup table */\n\n  U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0be, 0x005),                     /* VCOMH voltage */\n  U8X8_CA(0x0b6, 0x00a),\t\t/* second precharge */\n  U8X8_CA(0x0d5, 0x062),\t\t/* enable second precharge, internal vsl (bit0 = 0) */\n\n\n  \n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1327_128x96_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x020),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x051),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1327_128x96_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a2, 0x060),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a0, 0x042),\t\t/* remap configuration */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1327_visionox_128x96(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call the 96x96 procedure at the moment */\n  if ( u8x8_d_ssd1327_96x96_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1327_128x96_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_init_seq); \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1327_128x96_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1329.c",
    "content": "/*\n\n  u8x8_d_ssd1329.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_ssd1329_128x96_noname_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_CA(0x0b3, 0x091),\t\t/* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */\t\t\t\n  U8X8_CA(0x0a8, 0x05f),\t\t/* multiplex ratio: 0x03f * 1/64 duty - changed by CREESOO, acc. to datasheet, 100317*/ \n  U8X8_CA(0x0a2, 0x000),\t\t/* display offset, shift mapping ram counter */\n  U8X8_CA(0x0a1, 0x000),\t\t/* display start line */\n  U8X8_CA(0x0ad, 0x002),\t\t/* master configuration: disable embedded DC-DC, enable internal VCOMH */\n  U8X8_CA(0x0a0, 0x052),\t\t/* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */\n  U8X8_C(0x086),\t\t\t\t/* full current range (0x084, 0x085, 0x086) */\n#ifdef removed\n  U8X8_C(0x0b8),\t\t\t\t/* set gray scale table */\n    U8X8_A(1),\t\t\t\t/* */\n    U8X8_A(5),\t\t\t\t/* */\n    U8X8_A(10),\t\t\t\t/* */\n    U8X8_A(14),\t\t\t\t/* */\n    U8X8_A(19),\t\t\t\t/* */\n    U8X8_A(23),\t\t\t\t/* */\n    U8X8_A(28),\t\t\t\t/* */\n    U8X8_A(32),\t\t\t\t/* */\n    U8X8_A(37),\t\t\t\t/* */\n    U8X8_A(41),\t\t\t\t/* */\n    U8X8_A(46),\t\t\t\t/* */\n    U8X8_A(50),\t\t\t\t/* */\n    U8X8_A(55),\t\t\t\t/* */\n    U8X8_A(59),\t\t\t\t/* */\n    U8X8_A(63),\t\t\t\t/* */\n#endif \n\n  U8X8_C(0x0b7),\t\t\t\t/* set default gray scale table */\n    \n  U8X8_CA(0x081, 0x070),\t\t/* contrast, brightness, 0..128 */\n  U8X8_CA(0x0b2, 0x051),\t\t/* frame frequency (row period) */\n  U8X8_CA(0x0b1, 0x055),                    /* phase length */\n  U8X8_CA(0x0bc, 0x010),                    /* pre-charge voltage level */\n  U8X8_CA(0x0b4, 0x002),                    /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0b0, 0x028),                    /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_CA(0x0be, 0x01c),                     /* VCOMH voltage */\n  U8X8_CA(0x0bf, 0x002|0x00d),           /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */\n  U8X8_C(0x0a4),\t\t\t\t/* normal display mode */\n    \n  U8X8_CA(0x023, 0x003),\t\t/* graphics accelleration: fill pixel */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1329_128x96_nhd_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1329_128x96_nhd_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x052),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1329_128x96_nhd_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0a0, 0x041),\t\t/* remap */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for ssd1329 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_ssd1329_8to32_dest_buf[32];\n\nstatic uint8_t *u8x8_ssd1329_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t v;\n  uint8_t a,b;\n  uint8_t i, j;\n  uint8_t *dest;\n  \n  for( j = 0; j < 4; j++ )\n  {\n    dest = u8x8_ssd1329_8to32_dest_buf;\n    dest += j;\n    a =*ptr;\n    ptr++;\n    b = *ptr;\n    ptr++;\n    for( i = 0; i < 8; i++ )\n    {\n      v = 0;\n      if ( a&1 ) v |= 0xf0;\n      if ( b&1 ) v |= 0x0f;\n      *dest = v;\n      dest+=4;\n      a >>= 1;\n      b >>= 1;\n    }\n  }\n  \n  return u8x8_ssd1329_8to32_dest_buf;\n}\n\n\n\n\nstatic uint8_t u8x8_d_ssd1329_128x96_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_nhd_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_noname_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1329_128x96_nhd_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1329 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 4;\n      \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      \n      y *= 8;\n      y += u8x8->x_offset;\t\t/* x_offset is used as y offset for the ssd1329 */\n    \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n\t  if ( ptr[0] | ptr[1] | ptr[2] | ptr[3] | ptr[4] | ptr[5] | ptr[6] | ptr[7] )\n\t  {\n\t    /* draw the tile if pattern is not zero for all bytes */\n\t    u8x8_cad_SendCmd(u8x8, 0x015 );\t/* set column address */\n\t    u8x8_cad_SendArg(u8x8, x );\t/* start */\n\t    u8x8_cad_SendArg(u8x8, x+3 );\t/* end */\n\n\t    u8x8_cad_SendCmd(u8x8, 0x075 );\t/* set row address */\n\t    u8x8_cad_SendArg(u8x8, y);\n\t    u8x8_cad_SendArg(u8x8, y+7);\n\t    \n\t    \n\t    u8x8_cad_SendData(u8x8, 32, u8x8_ssd1329_8to32(u8x8, ptr));\n\t  }\n\t  else\n\t  {\n\t    /* tile is empty, use the graphics acceleration command */\n\t    /* are this really available on the SSD1329??? */\n\t    u8x8_cad_SendCmd(u8x8, 0x024 );\t// draw rectangle\n\t    u8x8_cad_SendArg(u8x8, x );\t\n\t    u8x8_cad_SendArg(u8x8, y );\t\n\t    u8x8_cad_SendArg(u8x8, x+3 );\t\n\t    u8x8_cad_SendArg(u8x8, y+7 );\t\n\t    u8x8_cad_SendArg(u8x8, 0 );\t// clear\t    \n\t  }\n\t  ptr += 8;\n\t  x += 4;\n\t  c--;\n\t} while( c > 0 );\n\t\n\t//x += 4;\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1329_128x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 15,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \t\t/**/\n  /* sda_setup_time_ns = */ 100,\t\t/* ssd1329  */\n  /* sck_pulse_width_ns = */ 100,\t/* ssd1329  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 60,\t/* ssd1329 */\n  /* tile_width = */ 16,\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1329 */\n  /* flipmode_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1329 */\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 96\n};\n\nuint8_t u8x8_d_ssd1329_128x96_noname(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1329_128x96_display_info);\n      return 1;\n    }\n    return u8x8_d_ssd1329_128x96_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1606_172x72.c",
    "content": "/*\n\n  u8x8_d_ssd1606_172x72.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  SSD1606: 128x180x2 \n  two-bit, four graylevels\n  command \n    0x22: assign actions\n    0x20: execute actions\n  \n  action for command 0x022 are (more or less guessed)\n    bit 7:\tEnable Clock\n    bit 6:\tEnable Charge Pump\n    bit 5:\tLoad Temparture Value (???)\n    bit 4:\tLoad LUT (???)\n    bit 3:\tInitial Display (???)\n    bit 2:\tPattern Display --> Requires about 945ms with the LUT from below\n    bit 1:\tDisable Charge Pump\n    bit 0:\tDisable Clock\n    \n    Disable Charge Pump and Clock require about 267ms\n    Enable Charge Pump and Clock require about 10ms\n\n  Notes:\n    - Introduced a refresh display message, which copies RAM to display\n    - Charge pump and clock are only enabled for the transfer RAM to display\n    - U8x8 will not really work because of the two buffers in the SSD1606, however U8g2 should be ok.\n\n*/\n\n\n#include \"u8x8.h\"\n\n\n#define L(a,b,c,d) (((a)<<6)|((b)<<4)|((c)<<2)|(d))\n\n\n/* GDE021A1, 2.1\" EPD */\nstatic const uint8_t u8x8_d_ssd1606_172x72_gde021a1_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x10, 0x00),\t/* Deep Sleep mode Control: Disable */\n  U8X8_CA(0x11, 0x03),\t/* Define data entry mode, x&y inc, x first */\n  U8X8_CAA(0x44, 0, 31),\t/* RAM x start & end, each byte has 4 pixel, 32*4=128 */\n  U8X8_CAA(0x45, 0, 179),\t/* RAM y start & end, 179 MAX */\n  \n  U8X8_CA(0x4e, 0),\t/* set x pos, 0..31 */\n  U8X8_CA(0x4f, 0),\t/* set y pos, 0...179 */\n\n  U8X8_CA(0xf0, 0x1f),\t/* set booster feedback to internal */\n  U8X8_CA(0x22, 0xc0),\t/* display update seq. option: enable clk, enable CP, .... todo: this is never activated */\n  \n  U8X8_C(0x32),\t/* write LUT register*/\n\n#ifdef ORIGINAL_LUT\n  \n  /* wavefrom part of the LUT: absolute LUT... this will always force the destination color */\n  U8X8_A4(0x00,0x00,0x00,0x55),  /* step 0 */\n  U8X8_A4(0x00,0x00,0x55,0x55),\t/* step 1 */\n  U8X8_A4(0x00,0x55,0x55,0x55),\n  U8X8_A4(0xAA,0xAA,0xAA,0xAA),\n  U8X8_A4(0x15,0x15,0x15,0x15),\n  U8X8_A4(0x05,0x05,0x05,0x05),\n  U8X8_A4(0x01,0x01,0x01,0x01),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\t/* step 19 */\n  \n  /* timing part of the LUT */\n  U8X8_A8(0x22,0xFB,0x22,0x1B,0x00,0x00,0x00,0x00),\n  U8X8_A(0x00),U8X8_A(0x00),\n\n#else\n\n  /* the following LUT will not change anything if the old and the new values are the same */\n  /* 03 02 01 00\t13 12 11 10 \t23 22 21 20\t33 32 31 30 \t\t\t\toriginal */\n  U8X8_A4(L(0, 0, 0, 0), \tL(0, 0, 0, 0), \tL(0, 0, 0, 0), \tL(0, 1, 1, 1)),\t\t// 0x00,0x00,0x00,0x55,\tstep 0\n  U8X8_A4(L(0, 0, 0, 0), \tL(0, 0, 0, 0), \tL(1, 0, 1, 1), \tL(0, 1, 1, 1)),\t\t// 0x00,0x00,0x55,0x55,\tstep 1\n  U8X8_A4(L(0, 0, 0, 0), \tL(1, 1, 0, 1), \tL(1, 0, 1, 1), \tL(0, 1, 1, 1)),\t\t// 0x00,0x55,0x55,0x55,\tstep 2\n  U8X8_A4(L(2, 2, 2, 0), \tL(2, 2, 0, 2), \tL(2, 0, 2, 2), \tL(0, 2, 2, 2)),\t\t// 0xAA,0xAA,0xAA,0xAA,\tstep 3\n  U8X8_A4(L(0, 1, 1, 0), \tL(0, 1, 0, 1), \tL(0, 0, 1, 1), \tL(0, 1, 1, 1)),\t\t// 0x15,0x15,0x15,0x15,\tstep 4\n  U8X8_A4(L(0, 0, 1, 0), \tL(0, 0, 0, 1), \tL(0, 0, 1, 1), \tL(0, 0, 1, 1)),\t\t// 0x05,0x05,0x05,0x05,\tstep 5\n  U8X8_A4(L(0, 0, 0, 0), \tL(0, 0, 0, 1), \tL(0, 0, 0, 1), \tL(0, 0, 0, 1)),\t\t// 0x01,0x01,0x01,0x01,\tstep 6\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\n  U8X8_A4(0x00,0x00,0x00,0x00),\t/* step 19 */\n  \n  /* timing part of the LUT */\n  U8X8_A8(0x22,0xFB,0x22,0x1B,0x00,0x00,0x00,0x00),\n  U8X8_A(0x00),U8X8_A(0x00),\n\n#endif\n  \n  U8X8_CA(0x2c, 0xa0),\t/* write vcom value*/\n  U8X8_CA(0x3c, 0x63),\t/* select boarder waveform */\n  U8X8_CA(0x22, 0xc4),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n    /* 0x0c4 is mentioned in chapter 9.2 of the GDE021A1 data sheet */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1606_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  \n  //U8X8_CA(0x22, 0xc0),\t/* display update seq. option: Enable clock and charge pump */\n  //U8X8_C(0x20),\t/* execute sequence */\n  //U8X8_DLY(10),\n  /* strange, splitting 0x0c0 does not work reliable */\n  \n  U8X8_CA(0x22, 0xc4),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  U8X8_DLY(250),\t/* the sequence above requires about 970ms */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(230),\n  \n  U8X8_CA(0x22, 0x03),\t/* disable clock and charge pump */\n  U8X8_DLY(200),\t\t/* this requres about 270ms */\n  U8X8_DLY(90),  \n  \n  //U8X8_CA(0x10, 0x01), /* deep sleep mode */\n  //U8X8_C(0x20), \t\t/* execute sequence */\n  U8X8_DLY(50),  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n// static const uint8_t u8x8_d_ssd1606_172x72_powersave0_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n\n// static const uint8_t u8x8_d_ssd1606_172x72_powersave1_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n// static const uint8_t u8x8_d_ssd1606_172x72_flip0_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n// static const uint8_t u8x8_d_ssd1606_172x72_flip1_seq[] = {\n//   U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n//   U8X8_END_TRANSFER(),             \t/* disable chip */\n//   U8X8_END()             \t\t\t/* end of sequence */\n// };\n\n\nstatic uint8_t *u8x8_convert_tile_for_ssd1606(uint8_t *t)\n{\n  uint8_t i;\n  uint16_t r;\n  static uint8_t buf[16];\n  uint8_t *pbuf = buf;\n\n  for( i = 0; i < 8; i++ )\n  {\n    r = u8x8_upscale_byte(~(*t++));\n    *pbuf++ = (r>>8) & 255;\n    *pbuf++ = r & 255;\n  }\n  return buf;\n}\n\nstatic void u8x8_d_ssd1606_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr) U8X8_NOINLINE;\nstatic void u8x8_d_ssd1606_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c, page;\n  uint8_t *ptr;\n  u8x8_cad_StartTransfer(u8x8);\n\n  page = u8x8->display_info->tile_height;\n  page --;\n  page -= (((u8x8_tile_t *)arg_ptr)->y_pos);\n  page *= 2;\n\n\n  x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n  x *= 8;\n  x += u8x8->x_offset;\n\n  u8x8_cad_SendCmd(u8x8, 0x00f );\t/* scan start */\n  u8x8_cad_SendArg(u8x8, 0);\n\n  u8x8_cad_SendCmd(u8x8, 0x011 );\t/* cursor increment mode */\n  u8x8_cad_SendArg(u8x8, 3);\n\n  u8x8_cad_SendCmd(u8x8, 0x045 );\t/* window start column */\n  u8x8_cad_SendArg(u8x8, 0);\n  u8x8_cad_SendArg(u8x8, 179);\t\t/* end of display */\n\n  u8x8_cad_SendCmd(u8x8, 0x044 );\t/* window end page */\n  u8x8_cad_SendArg(u8x8, page);\n  u8x8_cad_SendArg(u8x8, page+1);\n\n  u8x8_cad_SendCmd(u8x8, 0x04f );\t/* window column */\n  u8x8_cad_SendArg(u8x8, x);\n\n  u8x8_cad_SendCmd(u8x8, 0x04e );\t/* window row */\n  u8x8_cad_SendArg(u8x8, page);\n\n  u8x8_cad_SendCmd(u8x8, 0x024 );\n  \n  do\n  {\n    c = ((u8x8_tile_t *)arg_ptr)->cnt;\n    ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n    do\n    {\n      u8x8_cad_SendData(u8x8, 16, u8x8_convert_tile_for_ssd1606(ptr));\n      ptr += 8;\n      x += 8;\n      c--;\n    } while( c > 0 );\n    \n    arg_int--;\n  } while( arg_int > 0 );\n  \n  u8x8_cad_EndTransfer(u8x8);\n}\n\n\nstatic uint8_t u8x8_d_ssd1606_172x72_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1606_172x72_display_info);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_172x72_gde021a1_init_seq);    \n    \n      /* special code for the SSD1606... */\n      /* ensure that the initial buffer is clear and all eInk is set to white */\n      /* this is done here, because the LUT will be of that kind, that it uses the previous color */\n      /* make everything black */\n      u8x8_FillDisplay(u8x8);\t\t\n      /* write content to the display */\n      u8x8_RefreshDisplay(u8x8);\n      /* now make everything clear */\n      u8x8_FillDisplay(u8x8);\t\t\n      /* write content to the display */\n      u8x8_RefreshDisplay(u8x8);\n      /* now make everything clear */\n      u8x8_ClearDisplay(u8x8);\t\t\n      /* write content to the display */\n      u8x8_RefreshDisplay(u8x8);\n\n      u8x8_ClearDisplay(u8x8);\t\t\n      /* write content to the display */\n      u8x8_RefreshDisplay(u8x8);\n    \n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n/*\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_172x72_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_172x72_powersave1_seq);\n*/\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n/*\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_172x72_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_172x72_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n*/\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n/*\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_EndTransfer(u8x8);\n*/\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_ssd1606_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1606_to_display_seq);    \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic const u8x8_display_info_t u8x8_ssd1606_172x72_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 120,\n  /* pre_chip_disable_wait_ns = */ 60,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1606: */\n  /* sck_pulse_width_ns = */ 100,\t/* SSD1606: 100ns */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 22,\t\t/* 22*8 = 176 */\n  /* tile_hight = */ 9,\t\t/* 9*8 = 72 */\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 172,\n  /* pixel_height = */ 72\t\t\n};\n\nuint8_t u8x8_d_ssd1606_172x72(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1606_172x72_display_info);\n      return 1;\n    }\n    return u8x8_d_ssd1606_172x72_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_ssd1607_200x200.c",
    "content": "/*\n\n  u8x8_d_ssd1607_200x200.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  SSD1607: 200x300x1\n  \n  command \n    0x22: assign actions\n    0x20: execute actions\n  \n  action for command 0x022 are (more or less guessed)\n    bit 7:\tEnable Clock\n    bit 6:\tEnable Charge Pump\n    bit 5:\tLoad Temparture Value (???)\n    bit 4:\tLoad LUT (???)\n    bit 3:\tInitial Display (???)\n    bit 2:\tPattern Display --> Requires about 945ms with the LUT from below\n    bit 1:\tDisable Charge Pump\n    bit 0:\tDisable Clock\n    \n    Disable Charge Pump and Clock require about 267ms\n    Enable Charge Pump and Clock require about 10ms\n\n  Notes:\n    - Introduced a refresh display message, which copies RAM to display\n    - Charge pump and clock are only enabled for the transfer RAM to display\n    - U8x8 will not really work because of the two buffers in the SSD1606, however U8g2 should be ok.\n\n*/\n\n\n#include \"u8x8.h\"\n\n/*=================================================*/\n\nstatic const u8x8_display_info_t u8x8_ssd1607_200x200_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* values from SSD1606 */\n  /* post_chip_enable_wait_ns = */ 120,\n  /* pre_chip_disable_wait_ns = */ 60,\n  /* reset_pulse_width_ms = */ 100, \t\n  /* post_reset_wait_ms = */ 100, \n  /* sda_setup_time_ns = */ 50,\t\t/* SSD1606: */\n  /* sck_pulse_width_ns = */ 100,\t/* SSD1606: 100ns */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 150,\t\n  /* tile_width = */ 25,\t\t/* 25*8 = 200 */\n  /* tile_hight = */ 25,\t\t\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 200,\n  /* pixel_height = */ 200\t\t\n};\n\n\nstatic const uint8_t u8x8_d_ssd1607_200x200_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x22, 0xc0),\t\t\t/* enable clock and charge pump */\n  U8X8_C(0x20),\t\t\t\t/* execute sequence */  \n  U8X8_DLY(200),\t\t\t\t/* according to my measures it may take up to 150ms */\n  U8X8_DLY(100),\t\t\t\t/* but it might take longer */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1607_200x200_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */  \n  /* disable clock and charge pump only, deep sleep is not entered, because we will loose RAM content */\n  U8X8_CA(0x22, 0x02),\t\t\t/* only disable charge pump, HW reset seems to be required if the clock is disabled */\n  U8X8_C(0x20),\t\t\t\t/* execute sequence */  \n  U8X8_DLY(20),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1607_200x200_exec_1000dly_seq[] = {\n  // assumes, that the start transfer has happend\n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic void u8x8_d_ssd1607_200x200_first_init(u8x8_t *u8x8)\n{\n      u8x8_ClearDisplay(u8x8);\n  \n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x032);\t\t// program update sequence\n      u8x8_cad_SendMultipleArg(u8x8, 8, 0x055);\t\t// all black\n      u8x8_cad_SendMultipleArg(u8x8, 12, 0x0aa);\t\t// all white\n      u8x8_cad_SendMultipleArg(u8x8, 10, 0x022);\t\t// 830ms\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_exec_1000dly_seq);\n  \n}\n\nstatic uint8_t *u8x8_convert_tile_for_ssd1607(uint8_t *t)\n{\n  uint8_t i;\n  static uint8_t buf[8];\n  uint8_t *pbuf = buf;\n\n  for( i = 0; i < 8; i++ )\n  {\n    *pbuf++ = ~(*t++);\n  }\n  return buf;\n}\n\nstatic void u8x8_d_ssd1607_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr) U8X8_NOINLINE;\nstatic void u8x8_d_ssd1607_draw_tile(u8x8_t *u8x8, uint8_t arg_int, void *arg_ptr)\n{\n  uint16_t x;\n  uint8_t c, page;\n  uint8_t *ptr;\n  u8x8_cad_StartTransfer(u8x8);\n\n  page = u8x8->display_info->tile_height;\n  page --;\n  page -= (((u8x8_tile_t *)arg_ptr)->y_pos);\n  \n  x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n  x *= 8;\n  x += u8x8->x_offset;\n  \n  \n\n  u8x8_cad_SendCmd(u8x8, 0x045 );\t/* window start column */\n  u8x8_cad_SendArg(u8x8, x&255);\n  u8x8_cad_SendArg(u8x8, x>>8);\n  u8x8_cad_SendArg(u8x8, 199);\t\t/* end of display */\n  u8x8_cad_SendArg(u8x8, 0);\n\n  u8x8_cad_SendCmd(u8x8, 0x044 );\t/* window end page */\n  u8x8_cad_SendArg(u8x8, page);\n  u8x8_cad_SendArg(u8x8, page);\n\n  u8x8_cad_SendCmd(u8x8, 0x04f );\t/* window column */\n  u8x8_cad_SendArg(u8x8, x&255);\n  u8x8_cad_SendArg(u8x8, x>>8);\n\n  u8x8_cad_SendCmd(u8x8, 0x04e );\t/* window row */\n  u8x8_cad_SendArg(u8x8, page);\n\n  u8x8_cad_SendCmd(u8x8, 0x024 );\n  \n  do\n  {\n    c = ((u8x8_tile_t *)arg_ptr)->cnt;\n    ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n    do\n    {\n      u8x8_cad_SendData(u8x8, 8, u8x8_convert_tile_for_ssd1607(ptr));\n      ptr += 8;\n      x += 8;\n      c--;\n    } while( c > 0 );\n    \n    arg_int--;\n  } while( arg_int > 0 );\n  \n  u8x8_cad_EndTransfer(u8x8);\n}\n\n\n\n/*=================================================*/\n\n\n#define L(a,b,c,d) (((a)<<6)|((b)<<4)|((c)<<2)|(d))\n\n\n/* https://github.com/embeddedadventures/SSD1607/blob/master/SSD1607.cpp */\nstatic const uint8_t u8x8_d_ssd1607_200x200_init_seq[] = {    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  //U8X8_CA(0x10, 0x00),\t/* Deep Sleep mode Control: Disable */\n  U8X8_C(0x01),\n  U8X8_A(199),U8X8_A(0),U8X8_A(0),\n  \n  \n  U8X8_CA(0x03, 0x00), \t/* Gate Driving voltage: 15V (lowest value)*/\n  U8X8_CA(0x04, 0x0a), \t/* Source Driving voltage: 15V (mid value and POR)*/\n  \n  U8X8_CA(0x0f, 0x00),\t\t/* scan start ? */\n  \n  U8X8_CA(0xf0, 0x1f),\t/* set booster feedback to internal */\n\n  U8X8_CA(0x2c, 0xa8),\t/* write vcom value*/\n  U8X8_CA(0x3a, 0x1a),\t/* dummy lines */\n  U8X8_CA(0x3b, 0x08),\t/* gate time */\n  U8X8_CA(0x3c, 0x33),\t/* select boarder waveform */\n  \n  U8X8_CA(0x11, 0x03),\t\t/* cursor increment mode */\n  U8X8_CAA(0x44, 0, 24),\t/* RAM x start & end, each byte has 8 pixel, 25*4=200 */\n  U8X8_CAAAA(0x45, 0, 0, 299&255, 299>>8),\t/* RAM y start & end, 0..299 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_ssd1607_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x32),\t/* write LUT register*/\n\n  \n  /* according to the command table, the lut has 240 bits (=30 bytes * 8 bits) */\n  \n  /* Waveform part of the LUT (20 bytes) */\n  /* bit 7/6: 1 - 1 transition */\n  /* bit 5/4: 1 - 0 transition */\n  /* bit 3/2: 0 - 1 transition */\n  /* bit 1/0: 0 - 0 transition */\n  /* \t00 – VSS */\n  /* \t01 – VSH */\n  /* \t10 – VSL */\n  /* \t11 – NA */\n  \n  /* original values */\n  /*\n  U8X8_A(0x02),\n  U8X8_A(0x02),\n  U8X8_A(0x01),\n  U8X8_A(0x11),\n  U8X8_A(0x12),\n  U8X8_A(0x12),\n  U8X8_A(0x22),\n  U8X8_A(0x22),\n  U8X8_A(0x66),\n  U8X8_A(0x69),\n  U8X8_A(0x69),\n  U8X8_A(0x59),\n  U8X8_A(0x58),\n  U8X8_A(0x99),\n  U8X8_A(0x99),\n  U8X8_A(0x88),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  */\n  \n  /* original values, L-macro */\n  U8X8_A(L(0,0,0,2)), // 0x02\n  U8X8_A(L(0,0,0,2)), // 0x02\n  U8X8_A(L(0,0,0,1)), // 0x01\n  U8X8_A(L(0,1,0,1)), // 0x11\n  U8X8_A(L(0,1,0,2)), // 0x12\n  U8X8_A(L(0,1,0,2)), // 0x12\n  U8X8_A(L(0,2,0,2)), // 0x22\n  U8X8_A(L(0,2,0,2)), // 0x22\n  U8X8_A(L(1,2,1,2)), // 0x66\n  U8X8_A(L(1,2,2,1)), // 0x69\n  U8X8_A(L(1,2,2,1)), // 0x69\n  U8X8_A(L(1,1,2,1)), // 0x59\n  U8X8_A(L(1,1,2,0)), // 0x58\n  U8X8_A(L(2,1,2,1)), // 0x99\n  U8X8_A(L(2,1,2,1)), // 0x99\n  U8X8_A(L(2,0,2,0)), // 0x88\n  U8X8_A(L(0,0,0,0)), // 0x00\n  U8X8_A(L(0,0,0,0)), // 0x00\n  U8X8_A(L(0,0,0,0)), // 0x00\n  U8X8_A(L(0,0,0,0)), // 0x00\n\n\n  /* orginal values without 0-0 and 1-1 transition */\n  /*\n  U8X8_A(L(3,0,0,3)), // 0x02\n  U8X8_A(L(3,0,0,3)), // 0x02\n  U8X8_A(L(3,0,0,3)), // 0x01\n  U8X8_A(L(3,1,0,3)), // 0x11\n  U8X8_A(L(3,1,0,3)), // 0x12\n  U8X8_A(L(3,1,0,3)), // 0x12\n  U8X8_A(L(3,2,0,3)), // 0x22\n  U8X8_A(L(3,2,0,3)), // 0x22\n  U8X8_A(L(3,2,1,3)), // 0x66\n  U8X8_A(L(3,2,2,3)), // 0x69\n  U8X8_A(L(3,2,2,3)), // 0x69\n  U8X8_A(L(3,1,2,3)), // 0x59\n  U8X8_A(L(3,1,2,3)), // 0x58\n  U8X8_A(L(3,1,2,3)), // 0x99\n  U8X8_A(L(3,1,2,3)), // 0x99\n  U8X8_A(L(3,0,2,3)), // 0x88\n  U8X8_A(L(3,0,0,3)), // 0x00\n  U8X8_A(L(3,0,0,3)), // 0x00\n  U8X8_A(L(3,0,0,3)), // 0x00\n  U8X8_A(L(3,0,0,3)), // 0x00\n  */\n  \n  \n  /* Timing part of the LUT, 20 Phases with 4 bit each: 10 bytes */\n  U8X8_A(0xF8),\n  U8X8_A(0xB4),\n  U8X8_A(0x13),\n  U8X8_A(0x51),\n  U8X8_A(0x35),\n  U8X8_A(0x51),\n  U8X8_A(0x51),\n  U8X8_A(0x19),\n  U8X8_A(0x01),\n  U8X8_A(0x00),\n  \n  \n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  U8X8_DLY(250),\t/* the sequence above requires about 1200ms for the 200x200 display*/\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1607_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1607_200x200_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_init_seq);    \n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      u8x8_d_ssd1607_200x200_first_init(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_ssd1607_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_to_display_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=================================================*/\n/* there is no improvement possible... so i consider the v2 version as obsolete */\n\n\nstatic const uint8_t u8x8_d_ssd1607_v2_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  /*\n0xaa, 0x09, 0x09, 0x19, 0x19, \n0x11, 0x11, 0x11, 0x11, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n\n0x75, 0x77, 0x77, 0x77, 0x07, \n0x00, 0x00, 0x00, 0x00, 0x00\nmeasured 1240 ms with IL3830 196x128\n  \n  \n0x02, 0x02, 0x01, 0x11, 0x12, \n0x12, 0x12, 0x22, 0x22, 0x66, \n0x69, 0x59, 0x58, 0x99, 0x99, \n0x88, 0x00, 0x00, 0x00, 0x00, \n\n0xf8, 0xb4, 0x13, 0x51, 0x35, \n0x51, 0x51, 0xe9, 0x04, 0x00\n  \n*/\n\n  U8X8_C(0x32),\t/* write LUT register*/\n\n  /* https://github.com/olikraus/u8g2/issues/347 */\n  U8X8_A(0x02),\n  U8X8_A(0x02),\n  U8X8_A(0x01),\n  U8X8_A(0x11),\n  U8X8_A(0x12),\n  U8X8_A(0x12),\n  U8X8_A(0x22),\n  U8X8_A(0x22),\n  U8X8_A(0x66),\n  U8X8_A(0x69),\n  U8X8_A(0x69),\n  U8X8_A(0x59),\n  U8X8_A(0x58),\n  U8X8_A(0x99),\n  U8X8_A(0x99),\n  \n  U8X8_A(0x88),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  U8X8_A(0x00),\n  \n  /* Timing part of the LUT, 20 Phases with 4 bit each: 10 bytes */\n  U8X8_A(0xF8),\n  U8X8_A(0xB4),\n  U8X8_A(0x13),\n  U8X8_A(0x51),\n  U8X8_A(0x35),\n  \n  U8X8_A(0x51),\n  U8X8_A(0x51),\n  U8X8_A(0xe9),\n  U8X8_A(0x04),\n  U8X8_A(0x00),\n  \n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n  U8X8_DLY(250),\t/* delay for 1500ms. The current sequence takes 1300ms */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_ssd1607_v2_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1607_200x200_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_init_seq);    \n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      u8x8_d_ssd1607_200x200_first_init(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_ssd1607_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_v2_to_display_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=================================================*/\n/* GDEP015OC1 */\n/* https://github.com/olikraus/u8g2/issues/454 */\n\n\nstatic const uint8_t u8x8_d_ssd1607_gd_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  /*\n0xaa, 0x09, 0x09, 0x19, 0x19, \n0x11, 0x11, 0x11, 0x11, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n0x00, 0x00, 0x00, 0x00, 0x00, \n\n0x75, 0x77, 0x77, 0x77, 0x07, \n0x00, 0x00, 0x00, 0x00, 0x00\nmeasured 1240 ms with IL3830 196x128\n  \n  \n0x02, 0x02, 0x01, 0x11, 0x12, \n0x12, 0x12, 0x22, 0x22, 0x66, \n0x69, 0x59, 0x58, 0x99, 0x99, \n0x88, 0x00, 0x00, 0x00, 0x00, \n\n0xf8, 0xb4, 0x13, 0x51, 0x35, \n0x51, 0x51, 0xe9, 0x04, 0x00\n  \n*/\n\n  U8X8_C(0x32),\t/* write LUT register*/\n\n/*\n  U8X8_A(0x50), U8X8_A(0xAA), U8X8_A(0x55), U8X8_A(0xAA), U8X8_A(0x11), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  \n  U8X8_A(0xFF), U8X8_A(0xFF), U8X8_A(0x1F), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n*/\n  U8X8_A(0x10), U8X8_A(0x18), U8X8_A(0x18), U8X8_A(0x08), U8X8_A(0x18),   // numbers based on Waveshare demo code\n  U8X8_A(0x18), U8X8_A(0x08), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  \n  U8X8_A(0x13), U8X8_A(0x14), U8X8_A(0x44), U8X8_A(0x12), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00),\n\n  U8X8_CA(0x22, 0xc4),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n  U8X8_DLY(250),\t/* delay for 1500ms. The current sequence takes 1300ms */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n//  U8X8_DLY(250),\n  \n//  U8X8_DLY(250),\n//  U8X8_DLY(250),\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_ssd1607_gd_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1607_200x200_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_init_seq);    \n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      u8x8_d_ssd1607_200x200_first_init(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_ssd1607_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_gd_to_display_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n/*=================================================*/\n\nstatic const uint8_t u8x8_d_ssd1607_ws_to_display_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n\n  U8X8_C(0x32),\t/* write LUT register*/\n\n  U8X8_A(0x10), U8X8_A(0x18), U8X8_A(0x18), U8X8_A(0x08), U8X8_A(0x18),   // numbers based on Waveshare demo code\n  U8X8_A(0x18), U8X8_A(0x08), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), \n  \n  U8X8_A(0x13), U8X8_A(0x14), U8X8_A(0x44), U8X8_A(0x12), U8X8_A(0x00), \n  U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00), U8X8_A(0x00),\n\n  U8X8_CA(0x22, 0xc4),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n  U8X8_DLY(250),\t/* delay for 1250ms.  */\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  U8X8_DLY(250),\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_ssd1607_ws_to_refresh_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n\n  U8X8_CA(0x22, 0x04),\t/* display update seq. option: clk -> CP -> LUT -> initial display -> pattern display */\n  U8X8_C(0x20),\t/* execute sequence */\n  \n//  U8X8_DLY(250),\n//  U8X8_DLY(250),\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/* waveshare 200x200 */\nstatic const uint8_t u8x8_d_ssd1607_ws_200x200_init_seq[] = {    \n  // suggested code from https://github.com/olikraus/u8g2/issues/637\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n \n  U8X8_C(0x01), /* DRIVER_OUTPUT_CONTROL: LO(EPD_HEIGHT-1), HI(EPD_HEIGHT-1). GD = 0; SM = 0; TB = 0; */\n  U8X8_A(199),U8X8_A(0),U8X8_A(0),\n  \n  U8X8_C(0x0C), /* BOOSTER_SOFT_START_CONTROL */\n  U8X8_A(0xd7),U8X8_A(0xd6),U8X8_A(0x9d),\n  \n  U8X8_CA(0x2c, 0xa8), /* WRITE_VCOM_REGISTER: VCOM 7C */\n  U8X8_CA(0x3a, 0x1a), /* SET_DUMMY_LINE_PERIOD: 4 dummy lines per gate */\n  U8X8_CA(0x3b, 0x08), /* SET_GATE_TIME: 2us per line */\n  U8X8_CA(0x11, 0x03), /* DATA_ENTRY_MODE_SETTING: X increment; Y increment */\n  U8X8_CAA(0x44, 0, 24), /* SET_RAM_X_ADDRESS_START_END_POSITION: LO(x >> 3), LO((w-1) >> 3) */\n  U8X8_CAAAA(0x45, 0, 0, 199&255, 199>>8), /* SET_RAM_Y_ADDRESS_START_END_POSITION: LO(y), HI(y), LO(h - 1), HI(h - 1) */\n  U8X8_CA(0x4e, 0), /* LO(x >> 3) */\n  U8X8_CAA(0x4f, 0, 0), /* LO(y), HI(y >> 8) */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */  \n  \n};\n\n\nuint8_t u8x8_d_ssd1607_ws_200x200(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_ssd1607_200x200_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_ws_200x200_init_seq);    \n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      u8x8_d_ssd1607_200x200_first_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_ws_to_display_seq);; // to setup LUT\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_200x200_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_d_ssd1607_draw_tile(u8x8, arg_int, arg_ptr);\n      break;\n    case U8X8_MSG_DISPLAY_REFRESH:\n      u8x8_cad_SendSequence(u8x8, u8x8_d_ssd1607_ws_to_refresh_seq);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7511.c",
    "content": "/*\n\n  u8x8_d_st7511.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  20 May 2019:\n  https://github.com/olikraus/u8g2/issues/876\n  Probably HW Flip does not work \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_st7511_320x240_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x015, 0x0a5),\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7511_320x240_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x014, 0x0a5),\t\t/* display off */\n  // maybe use sleep mode here, but it not clear whether sleep mode will reset all the settings\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7511_320x240_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAAAA(0x24, 0x01, 0xa5, 0xa5, 0xa5),\t\t/* memory control directions */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7511_320x240_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CAAAA(0x24, 0x02, 0xa5, 0xa5, 0xa5),\t\t/* memory control directions */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n/*=====================================================*/\n/* AV-Display: AVD-TM57QV-NW-001-B, issue 876 */\n\nstatic const u8x8_display_info_t u8x8_st7511_320x240_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* ST7511 Datasheet */\n  /* pre_chip_disable_wait_ns = */ 150,\t/* ST7511 Datasheet */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 120,\t\t/* ST7511 Datasheet */\n  /* sck_pulse_width_ns = */ 150,\t/* ST7511 Datasheet */\n  /* sck_clock_hz = */ 3300000UL,\t/* ST7511 Datasheet: 300ns cycle */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 200,\t/* */\n  /* write_pulse_width_ns = */ 250,\t/* ST7511 Datasheet: 500ns */\n  /* tile_width = */ 40,\t\t/* width of 17*8=136 pixel */\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 160,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 320,\n  /* pixel_height = */ 240\n};\n\nstatic const uint8_t u8x8_d_st7511_320x240_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_CA(0xae, 0xa5),\t\t\t\t\t\t/* SW Reset */\n  U8X8_CAAAA(0x61, 0x0f, 0x04, 0x02, 0xa5),\t/* all power on */\n  U8X8_CAAAA(0x62, 0x0a, 0x06, 0x0f, 0xa5),\t/* electronic volumne set 1 */\n  U8X8_CAAAA(0x63, 0x0f, 0x0f, 0xa5, 0xa5),\t\t/* electronic volumne set 2 */\n  U8X8_CAAAA(0x66, 0x00, 0xa5, 0xa5, 0xa5),\t\t/* electronic volumne set 2 */\n  U8X8_CA(0x12, 0xa5),\t\t\t\t\t\t/* SLeeP OUT */\n  U8X8_DLY(50),\n  // skiping display on here, deviation from https://github.com/olikraus/u8g2/issues/876\n  // will be called later in u8x8_d_st7511_320x240_powersave0_seq\n  U8X8_CAAAA(0x22, 0x00, 0xa5, 0xa5, 0xa5),\t\t/* monochrome display */\n  U8X8_CAAAA(0x24, 0x01, 0xa5, 0xa5, 0xa5),\t\t/* memory control directions */\n\n  U8X8_DLY(50),\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7511_avd_320x240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint16_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7511_320x240_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7511_320x240_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7511_320x240_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7511_320x240_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7511_320x240_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7511_320x240_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      // not sure how to implement this....\n      // u8x8_cad_StartTransfer(u8x8);\n      // u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n\n      // set page\n      u8x8_cad_SendCmd(u8x8, 0x025);\n      u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n      u8x8_cad_SendArg(u8x8, 0x09f);\t\t// end page\n      u8x8_cad_SendArg(u8x8, 0x000);\t\t// frame 0\n      u8x8_cad_SendArg(u8x8, 0x0a5);\t\t\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n    \n      // set column\n      u8x8_cad_SendCmd(u8x8, 0x026);\n      u8x8_cad_SendArg(u8x8, (x>>8) );\n      u8x8_cad_SendArg(u8x8, (x&255) );\n      u8x8_cad_SendArg(u8x8, 0x002);\n      u8x8_cad_SendArg(u8x8, 0x07f);\n\n      // start data transfer\n      u8x8_cad_SendCmd(u8x8, 0x02c);\n      u8x8_cad_SendArg(u8x8, 0x0a5 );\n\n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tc *= 8;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\t\n\twhile ( c > 128 )\n\t{\n\t  u8x8_cad_SendData(u8x8, 128, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\t  c -= 128;\n\t  ptr += 128;\n\t}\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st75256.c",
    "content": "/*\n\n  u8x8_d_st75256.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  0x030\text 00\n  0x031\text 01\n  0x038\text 10\n  0x039\text 11\n  \n  cad 011\n  \n  \n  code examples:\n  http://www.it610.com/article/2601023.htm\n  \n  normal mode:\n\t0x00c\tbit format\n  U8X8_CA( 0xbc, 0x00 ),\tdata scan dir \n  U8X8_A( 0xa6 ),\t\t\t\t\n  y: 0 offset\n  \n  flip mode:\n\t0x008\tbit format\n  U8X8_CA( 0xbc, 0x03 ),\tdata scan dir \n  U8X8_A( 0xa6 ),\t\t\t\t\n  y: 5 offset\n\t\n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n/* not a real power down for the st75256... just a display off */\nstatic const uint8_t u8x8_d_st75256_256x128_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */  \n  U8X8_C( 0x94 ),\t\t\t\t/* sleep out */\n  U8X8_DLY(10),\n  U8X8_C( 0xaf ),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_256x128_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0xae ),\t\t\t\t/* display off */\n  U8X8_C( 0x95 ),\t\t\t\t/* sleep in */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx256128_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx256128_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x03 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x008 ),\t\t\t\t/* data format MSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx172104_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x02 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx172104_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x01 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x008 ),\t\t\t\t/* data format MSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx256160_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx256160_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x03 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x008 ),\t\t\t\t/* data format MSB top */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic uint8_t u8x8_d_st75256_256x128_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x128_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n        u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n      else\n        u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n      u8x8_cad_StartTransfer(u8x8);\n      \n      u8x8_cad_SendCmd(u8x8, 0x030 );\n      u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n      u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n      u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      \n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      \n      u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n      u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n      u8x8_cad_SendArg(u8x8, u8x8->x_offset + (((u8x8_tile_t *)arg_ptr)->y_pos));\t/* x offset is used as y offset */\n      u8x8_cad_SendArg(u8x8, 0x04f);\n      //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n      u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n      u8x8_cad_SendArg(u8x8, x);\n      u8x8_cad_SendArg(u8x8, 255);\n      u8x8_cad_SendCmd(u8x8, 0x05c );\t\n          \n      do\n      {\n        c = ((u8x8_tile_t *)arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n        /* SendData can not handle more than 255 bytes, treat c > 31 correctly  */\n        if ( c > 31 )\n        {\n          u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n          ptr+=248;\n          c -= 31;\n        }\n        \n        u8x8_cad_SendData(u8x8, c*8, ptr); \t\n        arg_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=============================================*/\n/* JLX256128 */\n\nstatic const u8x8_display_info_t u8x8_st75256_256x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 32,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\t/* must be 0, because this is checked also for normal mode */\n  /* flipmode_x_offset = */ 5,\t\t/* used as y offset */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 128\n};\n\n\nstatic const uint8_t u8x8_d_st75256_256x128_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 0x7f ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x36, 0x05 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_jlx256128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_st75256_256x128_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x128_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256128_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256128_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n\n/*=============================================*/\n/* WO256X128, https://github.com/olikraus/u8g2/issues/891  */\n\nstatic const u8x8_display_info_t u8x8_st75256_wo256x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 32,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 5,\t/* must be 0, because this is checked also for normal mode */\n  /* flipmode_x_offset = */ 0,\t\t/* used as y offset */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 128\n};\n\n\nstatic const uint8_t u8x8_d_st75256_wo256x128_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x01 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x008 ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 0x7f ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x36, 0x05 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_wo256x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_st75256_256x128_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_wo256x128_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_wo256x128_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq);\t// this matches the init sequence\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n/*=============================================*/\n/* JLX25664 */\n\nstatic const u8x8_display_info_t u8x8_st75256_256x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 32,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t/* must be 0, because this is checked also for normal mode */\n  /* flipmode_x_offset = */ 13,\t\t/* used as y offset */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_st75256_256x64_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x005 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x1f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 0x3f ),\t\t\t\t/* 64 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 012, 0x02 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_jlx25664(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_st75256_256x128_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x64_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x64_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256128_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256128_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n/*=============================================*/\n/* JLX172104 LCD */\n\nstatic const u8x8_display_info_t u8x8_st75256_172x104_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 22,\t\t\t/* 22=176 */\n  /* tile_hight = */ 13,\n  /* default_x_offset = */ 84,\t/*  */\n  /* flipmode_x_offset = */ 0,\t\t\n  /* pixel_width = */ 172,\n  /* pixel_height = */ 104\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx172104_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x003 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x02 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 0x9f ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x08, 0x04 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};    \n\n\nuint8_t u8x8_d_st75256_jlx172104(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 0 )\t\t/* 0 means flip mode 1, then adjust y value */\n\t\tu8x8_cad_SendArg(u8x8, 8+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              /* this procedure assumes, that the overall width is 172 */\n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n                c *= 8;\n\n                if ( c + x > 172u )\n                {\n                        c = 172u;\n                        c -= x;\n                }\n                      \n                u8x8_cad_SendData(u8x8, c, ptr); \t\n                x += c;\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n            u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_172x104_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n            u8x8_d_helper_display_init(u8x8);\n            u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_init_seq);\n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq); \n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n}\n\n/*=============================================*/\n/* JLX240160 */\n\nstatic const u8x8_display_info_t u8x8_st75256_240x160_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 30,\n  /* tile_hight = */ 20,\n  /* default_x_offset = */ 16,\t/*  x offset in flipmode 0 */\n  /* flipmode_x_offset = */ 0,\t\t/* */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 160\n};\n\n\nstatic const uint8_t u8x8_d_st75256_240x160_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 239),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x02 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 159 ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x18, 0x04 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_jlx240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 0 )\t\t/* 0 means flip mode 1 */\n\t\tu8x8_cad_SendArg(u8x8, 1+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n                c *= 8;\n\n                if ( c + x > 240u )\n                {\n                        c = 240u;\n                        c -= x;\n                }\n                      \n                u8x8_cad_SendData(u8x8, c, ptr); \t\n                x += c;\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n\t    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_240x160_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n\t    u8x8_d_helper_display_init(u8x8);\n\t    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_240x160_init_seq);    \n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq);\n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n  \n  \n  \n}\n\n\n/*=============================================*/\n/* JLX256160 */\n\nstatic const u8x8_display_info_t u8x8_st75256_256x160_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 32,\n  /* tile_hight = */ 20,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 1,\t/* x offset is used as y offset in flipmode */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 160\n};\n\n\nstatic const uint8_t u8x8_d_st75256_256x160_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x28),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 0xFF),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 159 ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x18, 0x05 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_jlx256160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 1 )\t\t/* 1 means flip mode 1 */\n\t\tu8x8_cad_SendArg(u8x8, 1+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->display_info->default_x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\t\t/* SendData can not handle more than 255 bytes, treat c > 31 correctly  */\n\t\tif ( c > 31 )\n\t\t{\n\t\t  u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n\t\t  ptr+=248;\n\t\t  c -= 31;\n\t\t}\n\t\t\n\t\tu8x8_cad_SendData(u8x8, c*8, ptr); \t\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n\t    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x160_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n\t    u8x8_d_helper_display_init(u8x8);\n\t    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x160_init_seq);    \n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256160_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256160_flip1_seq);\n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n}\n\n\n/*=============================================*/\n/* JLX256160 mirror version #930 */\n\n\nstatic const uint8_t u8x8_d_st75256_256x160m_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x28),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 0xFF),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x02 ),\t\t\t/* data scan dir  ( CHANGED FOR MIRROR VERSION ) */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 159 ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x18, 0x05 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st75256_jlx256160m(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 1 )\t\t/* 1 means flip mode 1 */\n\t\tu8x8_cad_SendArg(u8x8, 1+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->display_info->default_x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\t\t/* SendData can not handle more than 255 bytes, treat c > 31 correctly  */\n\t\tif ( c > 31 )\n\t\t{\n\t\t  u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n\t\t  ptr+=248;\n\t\t  c -= 31;\n\t\t}\n\t\t\n\t\tu8x8_cad_SendData(u8x8, c*8, ptr); \t\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n\t    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x160_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n\t    u8x8_d_helper_display_init(u8x8);\n\t    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x160m_init_seq);    \n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq);\n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n}\n\n\n\n\n/*=============================================*/\n/* JLX256160 alternative version from issue #561 */\n\nstatic const u8x8_display_info_t u8x8_st75256_256x160_alt_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 32,\n  /* tile_hight = */ 20,\n  /* default_x_offset = */ 0,\t/*  x offset in flipmode 0 */\n  /* flipmode_x_offset = */ 0,\t\t/* */\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 160\n};\n\n\nstatic const uint8_t u8x8_d_st75256_256x160_alt_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x000 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x02 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 159 ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x18, 0x05 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st75256_jlx256160_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 0 )\t\t/* 0 means flip mode 1 */\n\t\tu8x8_cad_SendArg(u8x8, 1+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\t\t/* SendData can not handle more than 255 bytes, treat c > 31 correctly  */\n\t\tif ( c > 31 )\n\t\t{\n\t\t  u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n\t\t  ptr+=248;\n\t\t  c -= 31;\n\t\t}\n\t\t\n\t\tu8x8_cad_SendData(u8x8, c*8, ptr); \t\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n\t    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_256x160_alt_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n\t    u8x8_d_helper_display_init(u8x8);\n\t    u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x160_alt_init_seq);    \n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq);\n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n\n} \n\n\n/*=============================================*/\n/* JLX19296 LCD */\n\nstatic const u8x8_display_info_t u8x8_st75256_192x96_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 24,\t\n  /* tile_hight = */ 12,\n  /* default_x_offset = */ 0,\t/*  */\n  /* flipmode_x_offset = */ 64,\n  /* pixel_width = */ 192,\n  /* pixel_height = */ 96\n};\n\nstatic const uint8_t u8x8_d_st75256_jlx19296_init_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_DLY(20),\n\n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x094 ),\t\t\t\t/* sleep out */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x0ae ),\t\t\t\t/* display off */\n\n  U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_CA( 0x0d7, 0x09f ),\t\t/* disable auto read */  \n\n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x032 ),\t\t\t\t/* analog circuit set */\n  U8X8_A( 0x000 ),\t\t\t\t/* code example: OSC Frequency adjustment */\n  U8X8_A( 0x001 ),\t\t\t\t/* Frequency on booster capacitors 1 = 6KHz? */\n  U8X8_A( 0x003 ),\t\t\t\t/* Bias: 1: 1/13, 2: 1/12, 3: 1/11, 4:1/10, 5:1/9 */\n    \n  //U8X8_C( 0x031 ),\t\t\t\t/* select 01 commands */\n  U8X8_C( 0x020 ),\t\t\t\t/* gray levels */\n  U8X8_A( 0x01 ),\n  U8X8_A( 0x03 ),\n  U8X8_A( 0x05 ),\n  U8X8_A( 0x07 ),\n  U8X8_A( 0x09),\n  U8X8_A( 0x0b ),\n  U8X8_A( 0x0d ),\n  U8X8_A( 0x10 ),\n  U8X8_A( 0x11 ),\n  U8X8_A( 0x13 ),\n  U8X8_A( 0x15 ),\n  U8X8_A( 0x17 ),\n  U8X8_A( 0x19 ),\n  U8X8_A( 0x1b ),\n  U8X8_A( 0x1d ),\n  U8X8_A( 0x1f ),\n \n  \n  U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA(0x75, 0, 0x4f),\t\t/* row range */\n  U8X8_CAA(0x15, 0, 255),\t\t/* col range */\n  \n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0xbc, 0x00 ),\t\t\t/* data scan dir */\n  U8X8_A( 0xa6 ),\t\t\t\t/* ??? */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_C( 0x00c ),\t\t\t\t/* data format LSB top */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_C( 0xca ),\t\t\t\t/* display control, 3 args follow  */\n  U8X8_A( 0x00 ),\t\t\t\t/* 0x00: no clock division, 0x04: devide clock */\n  U8X8_A( 0x9f ),\t\t\t\t/* 1/160 duty value from the DS example code */\n  U8X8_A( 0x20 ),\t\t\t\t/* nline off */ \n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */ \n  U8X8_CA( 0x0f0, 0x010 ),\t\t/* monochrome mode  = 0x010*/\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CAA( 0x81, 0x2e, 0x03 ),\t/* Volume control */\n\n  //U8X8_C( 0x030 ),\t\t\t\t/* select 00 commands */\n  U8X8_CA( 0x020, 0x00b ),\t\t/* Power control: Regulator, follower & booster on */\n  U8X8_DLY(100),\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};    \n\n\nuint8_t u8x8_d_st75256_jlx19296(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n\n  switch(msg)\n  {\n            case U8X8_MSG_DISPLAY_DRAW_TILE:\n              \n              u8x8_cad_StartTransfer(u8x8);\n              x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n              x *= 8;\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\t/* select command set */\n              u8x8_cad_SendCmd(u8x8, 0x075 );\t/* row */\n\t      if ( u8x8->x_offset == 0 )\t\t/* 0 means flip mode 1, then adjust y value */\n\t\tu8x8_cad_SendArg(u8x8, 8+(((u8x8_tile_t *)arg_ptr)->y_pos));\n\t      else\n\t\tu8x8_cad_SendArg(u8x8, 1+(((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendArg(u8x8, 0x04f);\n              //u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos));\n              u8x8_cad_SendCmd(u8x8, 0x015 );\t/* col */\n              u8x8_cad_SendArg(u8x8, x+u8x8->x_offset);\n              u8x8_cad_SendArg(u8x8, 255);\n              u8x8_cad_SendCmd(u8x8, 0x05c );\t\n            \n              \n              do\n              {\n                c = ((u8x8_tile_t *)arg_ptr)->cnt;\n                ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n                c *= 8;\n\n                if ( c + x > 192u )\n                {\n                        c = 192u;\n                        c -= x;\n                }\n                      \n                u8x8_cad_SendData(u8x8, c, ptr); \t\n                x += c;\n                arg_int--;\n              } while( arg_int > 0 );\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n        case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n            //u8x8_SetI2CAddress(u8x8, 0x078);\t\t/* lowest I2C adr of the ST75256 */\n            u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75256_192x96_display_info);\n            return 1;\n        case U8X8_MSG_DISPLAY_INIT:\n            u8x8_d_helper_display_init(u8x8);\n            u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx19296_init_seq);\n            return 1;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n              if ( arg_int == 0 )\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave0_seq);\n              else\n                u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_256x128_powersave1_seq);\n\n              return 1;\n\tcase U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256160_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx256160_flip1_seq);\n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t    /*\n\t    if ( arg_int == 0 )\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip0_seq);\n\t      u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t    }\n\t    else\n\t    {\n\t      u8x8_cad_SendSequence(u8x8, u8x8_d_st75256_jlx172104_flip1_seq); \n\t      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t    }\n\t    return 1;\n\t    */\n\t\t\n#ifdef U8X8_WITH_SET_CONTRAST\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n              u8x8_cad_StartTransfer(u8x8);\n              \n              u8x8_cad_SendCmd(u8x8, 0x030 );\n              u8x8_cad_SendCmd(u8x8, 0x081 );  /* there are 9 bit for the volume control */\n              u8x8_cad_SendArg(u8x8, (arg_int & 0x1f)<<1 );\t/* lower 6 bit */\n              u8x8_cad_SendArg(u8x8, (arg_int>>5));\t\t/* upper 3 bit */\n              \n              u8x8_cad_EndTransfer(u8x8);\n              return 1;\n#endif\n  }\n  return 0;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7528.c",
    "content": "/*\n\n  u8x8_d_st7528.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  ST7528: 16 Graylevel Controller\n  https://github.com/olikraus/u8g2/issues/986\n  I2C Address: 0x03f (0x7e)\n  \n  \n  ERC16004\n  https://www.buydisplay.com/default/2-inch-lcd-160x64-graphic-module-serial-spi-display-st7528-black-on-white\n  \n*/\n\n\n#include \"u8x8.h\"\n\n\nstatic const uint8_t u8x8_d_st7528_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x038, 0x074),\t\t/* ext mode 0*/\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7528_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x038, 0x074),\t\t/* ext mode 0*/\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7528_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t                /* ADC */\n  U8X8_C(0x0c8),\t\t                /* SHL */  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7528_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t                /* ADC */\n  U8X8_C(0x0c0),\t\t                /* SHL */  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/*\n  input:\n    one tile (8 Bytes)\n  output:\n    Tile for st7528 (32 Bytes)\n*/\n\nstatic uint8_t u8x8_st7528_8to32_dest_buf[32];\n\nstatic uint8_t *u8x8_st7528_8to32(U8X8_UNUSED u8x8_t *u8x8, uint8_t *ptr)\n{\n  uint8_t j;\n  uint8_t *dest;\n  \n  dest = u8x8_st7528_8to32_dest_buf;\n  for( j = 0; j < 8; j++ )\n  {\n    *dest++ =*ptr;\n    *dest++ =*ptr;\n    *dest++ =*ptr;\n    *dest++ =*ptr;\n    ptr++;\n  }\n  return u8x8_st7528_8to32_dest_buf;\n}\n\n\n\nstatic uint8_t u8x8_d_st7528_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x;\n  uint8_t y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7528_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7528_nhd_c160100_init_seq);    \n    */\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7528_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7528_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7528_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7528_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* ssd1326 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;  // not clear\n      \n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      \n    \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\n\tdo\n\t{\n          u8x8_cad_SendCmd(u8x8, 0xb0 | y );\t/* set page address */\n          u8x8_cad_SendCmd(u8x8, 0x10| (x>>4) );\t/* set col msb*/\n          u8x8_cad_SendCmd(u8x8, 0x00| (x&15) );\t/* set col lsb*/\n          \n          u8x8_cad_SendData(u8x8, 32, u8x8_st7528_8to32(u8x8, ptr));\n          \n\t  ptr += 8;\n\t  x += 8;\n\t  c--;\n\t} while( c > 0 );\t\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\nstatic void u8x8_d_st7528_graylevel_init(u8x8_t *u8x8, uint8_t mode0)\n{\n  uint8_t i;\n  \n  u8x8_cad_StartTransfer(u8x8);\n  u8x8_cad_SendCmd(u8x8, 0x38 );\n  u8x8_cad_SendArg(u8x8, mode0+1 );\n  for( i = 0; i < 64; i++ )\n  {\n          u8x8_cad_SendCmd(u8x8, i+0x080 );\n          u8x8_cad_SendArg(u8x8, i & 0xfc);\n  }\n  u8x8_cad_SendCmd(u8x8, 0x38 );\n  u8x8_cad_SendArg(u8x8, mode0 );\n  u8x8_cad_EndTransfer(u8x8);\n}\n\n/*===============================================================*/\n/* NHD C160100 */\nstatic const uint8_t u8x8_d_st7528_nhd_c160100_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  \n/*\n    I2C_out(0x48);//partial display duty ratio\n    I2C_out(0x64);// 1/100 duty\n    I2C_out(0xA0);//ADC select\n    I2C_out(0xC8);//SHL select\n    I2C_out(0x44);//initial Com0 register\n    I2C_out(0x00);//scan from Com0\n    I2C_out(0xAB);//OSC on\n    I2C_out(0x26);//\n    I2C_out(0x81);\t//set electronic volume\n    I2C_out(0x15);//vopcode=0x1C\n    I2C_out(0x56);//set 1/11 bias\n    I2C_out(0x64);//3x\n    delay(2);\n    I2C_out(0x2C);//\n    I2C_out(0x66);//5x\n    delay(2);\n    I2C_out(0x2E);//\n    delay(2);\n    I2C_out(0x2F);//power control\n    I2C_out(0xF3);//bias save circuit\n    I2C_out(0x00);//\n    I2C_out(0x96);//frc and pwm\n    I2C_out(0x38);//external mode\n    I2C_out(0x75);//\n    I2C_out(0x97);//3frc, 45 pwm\t\t\tTHIS IS A MODE0 CMD, IT IS USELESS HERE\n    I2C_out(0x80);//start 16-level grayscale settings\n*/\n  U8X8_CA(0x038, 0x064),\t\t/* ext mode 0*/\n  U8X8_CA(0x048, 0x064),\t\t/* partial display duty ratio, 1/100 duty*/\n  U8X8_C(0x0a0),\t\t                /* ADC */\n  U8X8_C(0x0c8),\t\t                /* SHL */\n  U8X8_CA(0x044, 0x000),\t\t/* initial Com0 */\n  U8X8_C(0x0ab),\t\t                /* start oscillator */\n  U8X8_C(0x026),\t\t                /* Select the internal resistance ratio of the regulator resistor */\n  U8X8_CA(0x081, 0x015),\t\t/* volumn */\n  U8X8_C(0x056),\t\t                /* LCD Bias */\n  U8X8_C(0x064),\t\t                /* DC DC step up */\n  U8X8_DLY(2),\n  U8X8_C(0x02c),\t\t                /* Power Control */\n  U8X8_C(0x066),\t\t                /* DC DC step up */\n  U8X8_DLY(2),\n  U8X8_C(0x02e),\t\t                /* Power Control */\n  U8X8_DLY(2),\n  U8X8_C(0x02f),\t\t                /* Power Control */\n  U8X8_CA(0x0f3, 0x000),\t\t/* bias power save */\n  U8X8_C(0x096),\t\t                /* frc and pwm */\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\nstatic const u8x8_display_info_t u8x8_st7528_160x100_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* st7528  */\n  /* sck_pulse_width_ns = */ 25,\t/* st7528 */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n      /* st7528 actually allows 20MHz according to the datasheet */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 80,\t/* st7528 */\n  /* tile_width = */ 20,\n  /* tile_hight = */ 13,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* flipmode_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 100\n};\n\nuint8_t u8x8_d_st7528_nhd_c160100(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7528_160x100_display_info);\n      return 1;\n    }\n    if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7528_nhd_c160100_init_seq);    \n      u8x8_d_st7528_graylevel_init(u8x8, 0x074);\n      return 1;\n    }    \n    return u8x8_d_st7528_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n/*===============================================================*/\n/* ERC16064, https://www.buydisplay.com/2-inch-lcd-160x64-graphic-module-serial-spi-display-st7528-black-on-white */\n\n/*\n\n#define\tModeSet\t\t\t\t0x38\n#define\tModeSetP1\t\t\t0x64\t//EXT=0\n#define\tModeSetP2\t\t\t0x65\t//EXT=1\n\n#define Display_on \t\t\t0xaf\n#define Display_off \t\t0xae\n\n#define Regulator\t\t\t0x26\n#define Contrast_level\t\t0x81\n#define PowerControll_on1\t0x2c\n#define PowerControll_on2\t0x2e\n#define PowerControll_on3\t0x2f\n\n#define\tLcdBias_9\t\t\t0x54\n#define\tInterOsc_on\t\t\t0xab\n#define\tEntireDisp_on\t\t0xa5\n#define\tEntireDisp_off\t\t0xa4\n#define BoostLevel_5\t\t0x66\n#define\tDuty_set\t\t\t0x48\n#define\tDuty_setP\t\t\t0x40\n#define Start_columnlsb\t\t0x00\n#define Start_columnmsb\t\t0x10\n#define Start_page\t\t\t0xb0\n#define\tStartLine_set\t\t0x40\n//#define\tStartLine_setP\t\t0x00\n#define Set_Initial_COM0\t0x44\n#define Set_Initial_COM0P\t0x12\n\n\n#define Entire_Displa_ON\t0xA5\n#define Entire_Displa_OFF\t0xA4\n\n#define FrcPwm_set\t\t\t0x92\n#define NLineInversion_on\t0x4c\n#define NLineInversion_onP\t0x1f\n#define NLineInversion_off\t0xe4\t\n#define ReverseDisp_on\t\t0xa7\n#define ReverseDisp_off\t\t0xa6\n#define AdcSelect\t\t\t0xa0\n#define ComScanDirection\t0xc8\n\n\tWrite_command(ModeSet);\t\t0x38, 0x64\n\tWrite_command(ModeSetP1);\t\n\tWrite_command(InterOsc_on);\t0xab\n\tWrite_command(Set_Initial_COM0);\t0x44, 0x12\n\tWrite_command(Set_Initial_COM0P);\n\n\tWrite_command(AdcSelect);\t\t0xa0\n\tWrite_command(ComScanDirection);\t0xc8\n\tWrite_command(BoostLevel_5);\t\t0x66\n\tDelay(1000);\n\tWrite_command(LcdBias_9);\t0x54\n\tWrite_command(Duty_set);\t\t0x48, 0x40\n\tWrite_command(Duty_setP);\n\tWrite_command(Regulator);\t0x26\n\tWrite_command(Contrast_level);\t\t0x81, 0x0b\n\tWrite_command(Contrast_levelP);\n\tWrite_command(PowerControll_on1);\t0x2c\n\tDelay(10000);\n\tWrite_command(PowerControll_on2);\t0x2e\n\tDelay(1000);\n\tWrite_command(PowerControll_on3);\t0x2f\n\tDelay(1000);\t\n\tWrite_command(FrcPwm_set);\t0x92\n\n\tWrite_command(ModeSet);\n\tWrite_command(ModeSetP2);\n\tfor(i=0;i<64;i++)\n\t\t{\n\t\tWrite_command(0x80+i);\n\t\tWrite_command(Gray_Parameters[i]);\n\t\t}\n\tWrite_command(ModeSet);\n\tWrite_command(ModeSetP1);\n*/\n\nstatic const uint8_t u8x8_d_st7528_erc16064_init_seq[] = {    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x038, 0x064),\t\t/* ext mode 0*/\n  U8X8_C(0x0ab),\t\t                /* start oscillator */\n  U8X8_CA(0x044, 0x012),\t\t/* initial Com0 */\n  U8X8_C(0x0a0),\t\t                /* ADC */\n  U8X8_C(0x0c8),\t\t                /* SHL */  \n  U8X8_C(0x066),\t\t                /* boost level, ERC16064: 0x066 */\n  U8X8_DLY(1),\n  U8X8_C(0x054),\t\t                /* LCD Bias, ERC16064: 0x054 */\n  U8X8_CA(0x048, 0x040),\t\t/* partial display duty ratio */  \n  U8X8_C(0x026),\t\t                /* Select the internal resistance ratio of the regulator resistor */  \n  U8X8_CA(0x081, 0x00b),\t\t/* contrast,  ERC16064: 0x00b */\n  \n  U8X8_C(0x02c),\t\t                /* Power Control */\n  U8X8_DLY(2),\n  U8X8_C(0x02e),\t\t                /* Power Control */\n  U8X8_DLY(2),\n  U8X8_C(0x02f),\t\t                /* Power Control */\n  U8X8_DLY(2),\n  U8X8_C(0x092),\t\t                /* frc and pwm, ERC160624: 0x092 */\n\n  \n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_st7528_erc16064_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* st7528  */\n  /* sck_pulse_width_ns = */ 25,\t/* st7528 */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n      /* st7528 actually allows 20MHz according to the datasheet */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\n  /* write_pulse_width_ns = */ 80,\t/* st7528 */\n  /* tile_width = */ 20,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* flipmode_x_offset = */ 0,\t\t/* x_offset is used as y offset for the ssd1326 */\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 64\n};\n\n\nuint8_t u8x8_d_st7528_erc16064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n    {\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7528_erc16064_display_info);\n      return 1;\n    }\n    if ( msg == U8X8_MSG_DISPLAY_INIT )\n    {\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7528_erc16064_init_seq);    \n      u8x8_d_st7528_graylevel_init(u8x8, 0x064);\n      return 1;\n    }    \n    return u8x8_d_st7528_generic(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st75320.c",
    "content": "/*\n\n  u8x8_d_st75320.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2019, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  ST75320: 320x240 monochrome LCD\n  \n  https://github.com/olikraus/u8g2/issues/921\n\n*/\n\n\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_st75320_jlx320240_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75320_jlx320240_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75320_jlx320240_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0xC4, 0x02), \t\t\t/* COM Output Status, Bits 0 & 1 */\n  U8X8_C(0xA1), \t\t\t\t/* Column Address Direction: Bit 0 */\n  //U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  //U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st75320_jlx320240_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  //U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  //U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_CA(0xC4, 0x03), \t\t\t/* COM Output Status, Bits 0 & 1 */\n  U8X8_C(0xA0), \t\t\t\t/* Column Address Direction: Bit 0 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\n/*===================================================*/\n\nstatic uint8_t u8x8_d_st75320_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint16_t x;\n  uint8_t c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75320_jlx320240_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int<<2 );\t\n      u8x8_cad_SendArg(u8x8, arg_int>>6 );\t\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n\n      u8x8_cad_StartTransfer(u8x8);\n    \n      u8x8_cad_SendCmd(u8x8, 0x013);\n      u8x8_cad_SendArg(u8x8, (x>>8) );\n      u8x8_cad_SendArg(u8x8, (x&255) );\n      u8x8_cad_SendCmd(u8x8, 0x0b1 ); \n      u8x8_cad_SendArg(u8x8, (((u8x8_tile_t *)arg_ptr)->y_pos)); \n\n\n      u8x8_cad_SendCmd(u8x8, 0x01d );\t\t// write data \n    \n      do\n      {\n        c = ((u8x8_tile_t *)arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n        /* SendData can not handle more than 255 bytes */\n        if ( c > 31 )\n        {\n          u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n          ptr+=248;\n          c -= 31;\n        }\n        \n        u8x8_cad_SendData(u8x8, c*8, ptr); \t\n        arg_int--;\n      } while( arg_int > 0 );\n\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*===================================================*/\n\n\n/* QT-2832TSWUG02/ZJY-2832TSWZG02 */\nstatic const uint8_t u8x8_d_st75320_jlx320240_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0xAE), \t\t\t\t// Display OFF\n  U8X8_CA(0xEA, 0x00), \t\t\t// Power Discharge Control, Discharge OFF\n  U8X8_C(0xA8), \t\t\t\t// sleep out\n  U8X8_C(0xAB), \t\t\t\t// OSC ON\n  U8X8_C(0x69), \t\t\t\t// Temperature Detection ON\n  U8X8_C(0x4E), \t\t\t\t// TC Setting\n  U8X8_A8(0xff, 0x44, 0x12, 0x11,  0x11, 0x11, 0x22, 0x23),\n  U8X8_CAA(0x39, 0x00, 0x00), \t//TC Flag\n  \n  \n  U8X8_CA(0x2B, 0x00), \t\t\t// Frame Rate Level\n  U8X8_CAA(0x5F, 0x66, 0x66), \t// Set Frame Frequency, fFR=80Hz in all temperature range\n  U8X8_CAAA(0xEC, 0x19, 0x64, 0x6e), // FR Compensation Temp. Range, TA = -15 degree, TB = 60 degree, TC = 70 degree\n  U8X8_CAA(0xED, 0x04, 0x04), \t// Temp. Hysteresis Value (thermal sensitivity)\n  U8X8_C(0xA6), \t\t\t\t// Display Inverse OFF\n  U8X8_C(0xA4), \t\t\t\t// Disable Display All Pixel ON\n\n  U8X8_CA(0xC4, 0x02), \t\t\t// COM Output Status  \n  U8X8_C(0xA1), \t\t\t\t// Column Address Direction: MX=0\n  \n  U8X8_CAA(0x6D, 0x07, 0x00), \t// Display Area, Duty = 1/240 duty, Start Group = 1\n  U8X8_C(0x84), \t\t\t\t// Display Data Input Direction: Column\n  U8X8_CA(0x36, 0x1e), \t\t\t// Set N-Line\n  U8X8_C(0xE4), \t\t\t\t// N-Line On\n  U8X8_CA(0xE7, 0x19), \t\t\t// LCD Drive Method //NLFR=1//\n\n  U8X8_CAA(0x81, 0x4f, 0x01), \t// OX81: Set EV=64h, 0..255, 0..3\n  U8X8_CA(0xA2, 0x0a), \t\t\t// BIAS //1/16 BIAS\n  U8X8_CA(0x25, 0x020), \t\t// Power Control //AVDD ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x60), \t\t\t// Power Control//AVDD, MV3 & NAVDD ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x70), \t\t\t// Power Control //AVDD, MV3, NAVDD & V3 ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x78), \t\t\t// Power Control//AVDD, MV3, NAVDD, V3 & VPF ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x7c), \t\t\t// Power Control//AVDD, MV3, NAVDD, V3, VPF & VNF ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x7e), \t\t\t// Power Control//VOUT, AVDD, MV3, NAVDD, V3, VPF & VNF ON\n  U8X8_DLY(10),\n  U8X8_CA(0x25, 0x7f), \t\t\t// Power Control/VOUT, AVDD, MV3, NAVDD, V3, VPF & VNF ON\n  U8X8_DLY(10),\n  //U8X8_C(0xaf); //Display ON  \n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()           \t\t\t/* end of sequence */\n};\n\n\n\n\nstatic const u8x8_display_info_t u8x8_st75320_jlx320240_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 40,\n  /* tile_hight = */ 30,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 320,\n  /* pixel_height = */ 240\n};\n\nuint8_t u8x8_d_st75320_jlx320240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_st75320_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st75320_jlx320240_init_seq);    \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st75320_jlx320240_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7565.c",
    "content": "/*\n\n  u8x8_d_st7565.c\n  also includes support for nt7534 \n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_st7565_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a4),\t\t                /* all pixel off, issue 142 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7565_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7565_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7565_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7565_zflip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7565_zflip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7565_128x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 4,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7565_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7565 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7565 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* DOGM128 */\n\nstatic const uint8_t u8x8_d_st7565_dogm128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x018),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_ea_dogm128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_128x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_dogm128_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n\n/*================================================*/\n/* LM6063 https://github.com/olikraus/u8g2/issues/893 */\n\nstatic const uint8_t u8x8_d_st7565_lm6063_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 50/4),\t\t/* set contrast, contrast value, 40..60 seems to be good */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_lm6063(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_128x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_lm6063_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* Displaytech 64128n */\n\nstatic const uint8_t u8x8_d_st7565_64128n_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  #ifdef NOT_WORKING\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  //U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  //U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n\n  U8X8_C(0x010),                   \t\t/* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */\n  \n  \n  U8X8_CA(0x081, 0x01e),\t\t/* set contrast, contrast value */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n#else\n\n\n  U8X8_C(0x0e2),            \t   /* soft reset */\n  U8X8_C(0x0A2),   \t\t\t\t   /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  //U8X8_C(0x0A0),  \t\t\t\t   /* Normal ADC Select (according to Displaytech 64128N datasheet) */\n  //U8X8_C(0x0c8),                   /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */\n  \n  U8X8_C(0x040),\t\t           /* Display start line for Displaytech 64128N */\n  U8X8_C(0x028 | 0x04),            /* power control: turn on voltage converter */\n  U8X8_C(0x028 | 0x06),            /* power control: turn on voltage regulator */\n  U8X8_C(0x028 | 0x07),            /* power control: turn on voltage follower */\n  U8X8_C(0x010),                   /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */\n\t\t\t\t\t      /* 19 Jul 17: Not sure if this is true, cmd 0x1? is used to set the column */\n  U8X8_C(0x0a6),                   /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x081),      \t           /* set contrast */\n  U8X8_C(0x01e),        \t       /* Contrast value. Setting for controlling brightness of Displaytech 64128N */\n  //U8X8_C(0x0af),\t\t           /* display on */\n  //U8X8_C(0x0a5),\t\t           /* display all points, ST7565 */\n  //U8X8_C(0x0a4),\t\t           /* normal display */\n\n  U8X8_C(0x0ae),\t\t                /* display off */\n\n\n#endif\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7565_64128n_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7565_64128n(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_64128n_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_64128n_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* ZOLEN 128x64  */\n\nstatic const uint8_t u8x8_d_st7565_zolen_128x64_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c0),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x007),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_zolen_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_128x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_zolen_128x64_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_zflip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_zflip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n\n/*================================================*/\n/* NHD-C12832 */\n\nstatic const u8x8_display_info_t u8x8_st7565_128x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\n\nstatic const uint8_t u8x8_d_st7565_nhd_c12832_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x023),\t\t                /* set V0 voltage resistor ratio to large*/\n  U8X8_CA(0x081, 0x00a),\t\t/* set contrast, contrast value NHD C12832 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_nhd_c12832(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_128x32_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_nhd_c12832_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* NHD-C12864 */\n\nstatic const u8x8_display_info_t u8x8_st7565_nhd_c12864_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n\nstatic const uint8_t u8x8_d_st7565_nhd_c12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x023),\t\t                /* set V0 voltage resistor ratio to large*/\n  U8X8_CA(0x081, 180),\t\t\t/* set contrast, contrast value NHD C12864, see issue 186, increased contrast to 180 (issue 219) */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_nhd_c12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_nhd_c12864_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_nhd_c12864_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n/*================================================*/\n/* JLX12864 */\n\nuint8_t u8x8_d_st7565_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  return u8x8_d_st7565_nhd_c12864(u8x8, msg, arg_int, arg_ptr);\n}\n\n\n/*================================================*/\n/* LM6059 (Adafruit)... probably this is a ST7567 display */\n\nstatic const uint8_t u8x8_d_st7565_lm6059_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x060),\t\t                /* set display start line to ... */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  //U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature) */\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x018),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7565_lm6059_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 1,\t/* not sure... */\n  /* flipmode_x_offset = */ 3,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7565_lm6059(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_lm6059_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_lm6059_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* https://github.com/olikraus/u8g2/issues/1314 */\n/* KS0713 controller, takeover from LM6059 */\n\nstatic const uint8_t u8x8_d_st7565_ks0713_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0e2),            \t\t\t /* soft reset */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_C(0x026),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_CA(0x081, 0x010),\t\t       /* set contrast, contrast value, EA default: 0x016 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_ks0713(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_lm6059_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_ks0713_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* LX12864 issue 576 */\n\nstatic const uint8_t u8x8_d_st7565_lx12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x060),\t\t                /* set display start line to ... */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  //U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature) */\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x008),\t\t/* set contrast, contrast value */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7565_lx12864_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 1,\t/* not sure... */\n  /* flipmode_x_offset = */ 3,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7565_lx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_lx12864_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_lx12864_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* ERC12864-1 (buydisplay.com) */\n\nstatic const uint8_t u8x8_d_st7565_erc12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to ... */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  //U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature)*/\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x018),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7565_erc12864_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 4,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7565_erc12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_erc12864_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_erc12864_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n\n\n/*================================================*/\n/* ERC12864-1 alternative version, suggested in issue 790 */\n\nstatic const uint8_t u8x8_d_st7565_erc12864_alt_init_seq[] = {\n\n\n  // original sequence \n  \n  // U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  // U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  // U8X8_C(0x0ae),\t\t                /* display off */\n  // U8X8_C(0x040),\t\t                /* set display start line to ... */\n  \n  // U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  // U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  // U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  // U8X8_C(0x0a3),\t\t                /* LCD bias 1/9 */\n  // U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  // U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature)*/\n  // U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  // U8X8_CA(0x081, 0x018),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  // U8X8_C(0x0ae),\t\t                /* display off */\n  // U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  // U8X8_END_TRANSFER(),             \t/* disable chip */\n  // U8X8_END()             \t\t\t/* end of sequence */\n  \n\n\n  // suggested in https://github.com/olikraus/u8g2/issues/790\n  \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to ... */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 - *** Changed by Ismail - was 0xa3 - 1/7 bias we were getting dark pixel off */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature)*/\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x05),\t\t       /* set contrast, contrast value, EA default: 0x016 - *** Changed by Ismail to 0x05 */ \n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n  \n};\n\n\nuint8_t u8x8_d_st7565_erc12864_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_erc12864_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_erc12864_alt_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n\n\n/*================================================*/\n/* NT7534, TG12864R */\n/* The NT7534 has an extended command set for the ST7565, however this is not used. */\n/* The TG12864R display is also shifted in lines, like the LM6059/Adafruit display */\n/* However contrast seems to be different */\n\nstatic const uint8_t u8x8_d_nt7534_tg12864r_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x060),\t\t                /* set display start line to ... */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c0),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on (regulator, booster and follower) */\n  //U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x (ST7567 feature)*/\n  U8X8_C(0x027),\t\t                /* set V0 voltage resistor ratio to max  */\n  U8X8_CA(0x081, 0x009),\t\t/* set contrast, contrast value, EA default: 0x016 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_nt7534_tg12864r(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\t/* reuse the LM6059 data structure... this display seems to have similar shifts and offsets */\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_lm6059_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n      \n\t//u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_lm6059_init_seq);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_nt7534_tg12864r_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* EA DOGM132 */\n\nstatic const u8x8_display_info_t u8x8_st7565_dogm132_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* st7565 datasheet, table 26, tcsh */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* st7565 datasheet, table 26, tcss */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* st7565 datasheet, table 26, tsds */\n  /* sck_pulse_width_ns = */ 120,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* st7565 datasheet, table 24, tds8 */\n  /* write_pulse_width_ns = */ 80,\t/* st7565 datasheet, table 24, tcclw */\n  /* tile_width = */ 17,\t\t/* width of 16*8=136 pixel */\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 132,\n  /* pixel_height = */ 32\n};\n\n\nstatic const uint8_t u8x8_d_st7565_dogm132_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  U8X8_CA(0x0f8, 0x000),\t\t/* set booster ratio to 4x */\n  U8X8_C(0x023),\t\t                /* set V0 voltage resistor ratio to large*/\n  U8X8_CA(0x081, 0x01f),\t\t/* set contrast, contrast value EA DOGM132 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_st7565_ea_dogm132(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_st7565_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7565_dogm132_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7565_dogm132_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_st7565_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7567.c",
    "content": "/*\n\n  u8x8_d_st7567.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_st7567_132x64_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a4),\t\t                /* all pixel off, issue 142 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7567_132x64_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7567_132x64_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7567_132x64_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7567_n_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7567_n_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n/*=====================================================*/\n\n\nstatic const u8x8_display_info_t u8x8_st7567_132x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 17,\t\t/* width of 17*8=136 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 132,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_st7567_132x64_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/7 */\n  /* power on sequence from paxinstruments */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x026),\t\t                /* v0 voltage resistor ratio */\n  U8X8_CA(0x081, 0x027),\t\t/* set contrast, contrast value*/\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* pax instruments 132x64 display */\nuint8_t u8x8_d_st7567_pi_132x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_132x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n\n\n/*=====================================================*/\n\n\n\n\n\nstatic const u8x8_display_info_t u8x8_st7567_jlx12864_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_st7567_jlx12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/7 */\n  /* power on sequence from paxinstruments */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x023),\t\t                /* v0 voltage resistor ratio */\n  U8X8_CA(0x081, 42>>2),\t\t/* set contrast, contrast value*/\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* JLX12864 display */\nuint8_t u8x8_d_st7567_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_jlx12864_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_st7567_jlx12864_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=====================================================*/\n\n\n\nstatic const u8x8_display_info_t u8x8_st7567_enh_dg128064_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 4,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nstatic const u8x8_display_info_t u8x8_st7567_enh_dg128064i_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_st7567_enh_dg128064_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  /* power on sequence from paxinstruments */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x023),\t\t                /* v0 voltage resistor ratio */\n  U8X8_CA(0x081, 200>>2),\t\t/* set contrast, contrast value*/\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* ENH-DG128064 transparent display */\nstatic uint8_t u8x8_d_st7567_enh_dg128064_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_enh_dg128064_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_st7567_enh_dg128064_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_st7567_enh_dg128064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_enh_dg128064_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_n_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_n_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n    default:\n      return u8x8_d_st7567_enh_dg128064_generic(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_st7567_enh_dg128064i(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_enh_dg128064i_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n    default:\n      return u8x8_d_st7567_enh_dg128064_generic(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n/*=====================================================*/\n/* issue 657 */\n\nstatic const u8x8_display_info_t u8x8_st7567_64x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 8,\t\t\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 32,\n  /* flipmode_x_offset = */ 32,\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 32\n};\n\nstatic const uint8_t u8x8_st7567_64x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC  */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x024),\t\t                /* v0 voltage resistor ratio, taken from issue 657 */\n  U8X8_CA(0x081, 0x020),\t\t/* set contrast, contrast value*/\n  /* 18 Apr 2020: the value 0x080 does not make sense, only 6 bit are supported\n  for contrast, changed to 0x040 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st7567_64x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_64x32_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_st7567_64x32_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=====================================================*/\n/* issue 1159, Lummax HEM6432-03 */\n\n\nstatic const u8x8_display_info_t u8x8_st7567_hem6432_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 8,\t\t\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 36,\t\t/* issue 1159 */\n  /* flipmode_x_offset = */ 32,\t\t/* issue 1159 */\n  /* pixel_width = */ 64,\n  /* pixel_height = */ 32\n};\n\nstatic const uint8_t u8x8_st7567_hem6432_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC  */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x024),\t\t                /* v0 voltage resistor ratio, taken from issue 657 */\n  U8X8_CA(0x081, 225/4),\t\t/* set contrast, contrast value as suggested inissue 1159 */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st7567_hem6432(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_hem6432_display_info);\n      u8x8->i2c_address = 0x07e;  /* issue 1159, use different i2c address */\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_st7567_hem6432_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*=====================================================*/\n/*\n  https://github.com/olikraus/u8g2/issues/1088 \n  https://www.dx.com/p/opensmart-33v-26-inch-128x64-serial-spi-monochrome-lcd-breakout-board-module-with-backlight-for-arduino-nano-pro-mini-2710499.html\n*/\n\n\n\n\n\nstatic const u8x8_display_info_t u8x8_st7567_os12864_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\t/* */\n  /* pre_chip_disable_wait_ns = */ 50,\t/* */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 1, \n  /* sda_setup_time_ns = */ 50,\t\t/* */\n  /* sck_pulse_width_ns = */ 120,\t/* */\n  /* sck_clock_hz = */ 4000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 40,\t/* */\n  /* write_pulse_width_ns = */ 80,\t/* */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 4,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_st7567_os12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a3),\t\t                /* LCD bias 1/7 */\n  /* power on sequence from paxinstruments */\n  U8X8_C(0x028|4),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|6),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  U8X8_C(0x028|7),\t\t                /* all power  control circuits on */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x026),\t\t                /* v0 voltage resistor ratio */\n  U8X8_CA(0x081, 50>>2),\t\t/* set contrast, contrast value*/\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* open-smart 12864 display */\nuint8_t u8x8_d_st7567_os12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7567_os12864_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_st7567_os12864_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7567_132x64_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* st7567 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the st7567 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7571.c",
    "content": "/*\n\n  u8x8_d_st7571.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2020, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  ST7571: 128x129 2-bit graylevel LCD\n  \n  https://github.com/olikraus/u8g2/issues/921\n\n*/\n\n\n#include \"u8x8.h\"\n\nstatic const uint8_t u8x8_d_st7571_128x128_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x071),\t\t                /* exit power save mode */\n  U8X8_C(0x0a8),\t\t                /* disable powersave mode */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7571_128x128_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */  \n  U8X8_C(0x0a9),\t\t                /* enter powersave mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7571_128x128_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7571_128x128_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\n/*===================================================*/\n\nstatic uint8_t u8x8_d_st7571_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint16_t x;\n  uint8_t c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7571_128x128_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int>>2);\t\t\t// 6 bit for the ST7571\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n\n\n      do\n      {\n        c = ((u8x8_tile_t *)arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n        /* SendData can not handle more than 255 bytes */\n\t/*\n        if ( c > 31 )\n        {\n          u8x8_cad_SendData(u8x8, 31*8, ptr); \n          ptr+=31*8;\n          c -= 31;\n        }\n\t*/\n        \n        u8x8_cad_SendData(u8x8, c*8, ptr); \t\n        arg_int--;\n      } while( arg_int > 0 );\n\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*===================================================*/\n\n\n/* QT-2832TSWUG02/ZJY-2832TSWZG02 */\nstatic const uint8_t u8x8_d_st7571_128x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  \n  U8X8_C(0xAE), \t\t\t\t// Display OFF\n  U8X8_C(0x38), \t\t\t\t// Mode Set  \n  U8X8_C(0xB8), \t\t\t\t// FR=1011 (85Hz), BE[1:0]=10, level 3 booster\n  \n  \n  U8X8_C(0xA0), \t\t\t\t// ADC select\n  U8X8_C(0xC8), \t\t\t\t// SHL select\n  U8X8_CA(0x44, 0x00), \t\t// COM0 register  \n  U8X8_CA(0x40, 0x7f), \t\t// initial display line  (0x7f... strange but ok... maybe specific for the JLX128128)\n  \n  U8X8_C(0xAB), \t\t\t\t// OSC ON  \n  U8X8_C(0x25), \t\t\t\t// Voltage regulator\n  U8X8_CA(0x81, 0x33), \t\t// Volume\n  U8X8_C(0x54), \t\t\t\t// LCD Bias: 0x056=1/11 (1/11 according to JLX128128 datasheet), 0x054=1/9\n  U8X8_CA(0x44, 0x7f), \t\t// Duty 1/128\n  \n  U8X8_C(0x2C), \t\t\t\t// Power Control, VC: ON, VR: OFF, VF: OFF\n  U8X8_DLY(200),\n  U8X8_C(0x2E), \t\t\t\t// Power Control, VC: ON, VR: ON, VF: OFF\n  U8X8_DLY(200),\n  U8X8_C(0x2F), \t\t\t\t// Power Control, VC: ON, VR: ON, VF: ON\n  U8X8_DLY(10),\n\n  U8X8_C(0x7B), \t\t\t\t// command set 3\n  U8X8_C(0x11), \t\t\t\t// black white mode\n  U8X8_C(0x00), \t\t\t\t// exit command set 3\n\n\n  U8X8_C(0xA6), \t\t\t\t// Display Inverse OFF\n  U8X8_C(0xA4), \t\t\t\t// Disable Display All Pixel ON\n\n  //U8X8_C(0xAF), \t\t\t\t// Display on\n\n\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()           \t\t\t/* end of sequence */\n};\n\n\n\n\nstatic const u8x8_display_info_t u8x8_st7571_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\n  /* pre_chip_disable_wait_ns = */ 20,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 20,\t\t/* */\n  /* sck_pulse_width_ns = */ 40,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 15,\n  /* write_pulse_width_ns = */ 70,\t\n  /* tile_width = */ 16,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_st7571_128x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    \n  if ( u8x8_d_st7571_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  \n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7571_128x128_init_seq); \n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7571_128x128_display_info);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7586s_erc240160.c",
    "content": "/*\n  u8x8_d_st7586s_erc240160.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n  \n  Copyright (c) 2018, olikraus@gmail.com\n  \n  All rights reserved.\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n\nstatic const uint8_t u8x8_d_st7586s_sleep_on[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x010), /* set power save mode */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_sleep_off[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x011), //Sleep out\n  U8X8_DLY(50), /* delay 50 ms */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_erc240160_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),  /* Scan Direction Setting */\n  U8X8_A(0x0C8),\t/* COM159 -> COM0 SEG383 -> SEG0 */\n  U8X8_C(0x037),\t/* Start line 0 */\n  U8X8_A(0x000),\n  U8X8_C(0x02A), /* Column Address Setting */\n  U8X8_A(0x000),  /* COL8 -> COL127 */\n  U8X8_A(0x008),  \n  U8X8_A(0x000), \n  U8X8_A(0x07F),  /* 120*3=240 pixels + 120 unused */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()           \t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_erc240160_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),  /* Scan Direction Setting */\n  U8X8_A(0x000),  /* COM0 -> COM159 SEG0 -> SEG383 */\n  U8X8_C(0x037),  /* Start line 0 */\n  U8X8_A(0x000),\n  U8X8_C(0x02A),  /* Column Address Setting */\n  U8X8_A(0x000),  /* COL0 -> COL119 */\n  U8X8_A(0x000),\n  U8X8_A(0x000),\n  U8X8_A(0x077),  /* 120*3=240 pixels + 120 unused */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()            /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_erc240160_init_seq[] = {\n  U8X8_END_TRANSFER(),/* disable chip */\n // U8G_ESC_RST(1), /* hardware reset */\n  U8X8_DLY(60),   /* Delay 60 ms */\n  U8X8_START_TRANSFER(),/* enable chip */\n\n  U8X8_C(0x001), // Soft reset\n  U8X8_DLY(60), // Delay 120 ms\n\n  U8X8_C(0x011), // Sleep Out\n  U8X8_C(0x028), // Display OFF\n  U8X8_DLY(25), // Delay 50 ms\n\n  U8X8_CAA(0x0C0,0x036,0x01),// Vop = 136h data sheet suggested 0x0145 but this caused streaks\n\n  U8X8_CA(0x0C3,0x000), // BIAS = 1/14\n\n  U8X8_CA(0x0C4,0x007), // Booster = x8\n\n  U8X8_CA(0x0D0,0x01D), // Enable Analog Circuit\n\n  U8X8_CA(0x0B3,0x000), // Set FOSC divider\n\n  U8X8_CA(0x0B5,0x000), // N-Line = 0\n\n  U8X8_C(0x039), // 0x39 Monochrome mode. 0x38 - gray Mode\n\n  U8X8_C(0x03A), // Enable DDRAM Interface\n  U8X8_A(0x002), // monochrome and 4-level\n\n  U8X8_C(0x036), // Scan Direction Setting\n  U8X8_A(0x0C8), // COM:C159->C0   SEG: SEG383->SEG0\n\n  U8X8_C(0x0B1), // First output COM\n  U8X8_A(0x000), // \n  \n  U8X8_C(0x0B0), // Duty Setting (num rows - 1)\n  U8X8_A(0x09F), \n\n  U8X8_C(0x020), // Display inversion off\n\n  U8X8_C(0x02A), // Column Address Setting\n  U8X8_A(0x000), // COL0 -> COL127\n  U8X8_A(0x008), // \n  U8X8_A(0x000), //\n  U8X8_A(0x07F), // 80*3=240 pixels\n\n  U8X8_C(0x02B), // Row Address Setting\n  U8X8_A(0x000), // ROW0 -> ROW159\n  U8X8_A(0x000), //\n  U8X8_A(0x000), //\n  U8X8_A(0x09F), // 160 pixels\n\n  U8X8_C(0x029), // Display ON\n  U8X8_END()  /* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7586s_erc240160_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n\n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 20,\n  /* sck_pulse_width_ns = */  100,  /* datasheet ST7586S */\n  /* sck_clock_hz = */ 8000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* ST7586+Atmega128RFA1 works with 8MHz */\n  /* spi_mode = */ 3,   /* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 20, /* datasheet suggests min 20 */\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 30,\n  /* tile_height = */ 20,\n  /* default_x_offset = */ 0,  /* abused as flag to know if we are flipped */\n  /* flipmode_x_offset = */ 1, /* as pixel order different for normal/flipped  */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 160\n};\n\n/*******************************************************************************\n * st7586s_erc240160 driver. ST7586 based display from buydisplay.com\n ******************************************************************************/\nuint8_t u8x8_d_st7586s_erc240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) {\n  \n  uint8_t c;\n  uint8_t *ptr;\n  uint8_t i, byte;\n  uint32_t input;\n  uint8_t output[4];\n  switch (msg) {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n    u8x8_cad_StartTransfer(u8x8); // OK Start transfer\n    u8x8_cad_SendCmd(u8x8, 0x02B);  /* Row Address Setting */\n    u8x8_cad_SendArg(u8x8, 0x000);\n    u8x8_cad_SendArg(u8x8, 0x008 * ((u8x8_tile_t *)arg_ptr)->y_pos);\n    u8x8_cad_SendArg(u8x8, 0x000);\n    u8x8_cad_SendArg(u8x8, 0x09F); // should set end row based on display dimensions\n    u8x8_cad_SendCmd(u8x8, 0x02C);  /* cmd write display data to ram */\n    c = ((u8x8_tile_t *) arg_ptr)->cnt; //\n    c *= 8;\n    ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;  //\n\n// The ST7586S has an unusual 3 pixels per byte format the ERC240160 is even more annoying\n// as it has every 3rd COM line disconnected for extra oddness so here we read in a byte \n// (8 pixels) and pack that into 4 bytes of 2 pixels + 1 unused each. This has to be done\n// in a different order for flipped, normal UUx11x22 flipped 11x22xUU\n\twhile (c > 0) {\n      input = ((uint8_t)ptr[0]);\n      \n      for (i=0; i<4; i++)\n      {\n        byte = 0;\n        if (u8x8->x_offset ==0){\n          if (input & 0x80)          // if bit 7\n            byte = byte | 0x18;  //set pixel 1\n          if (input & 0x40)          // if bit 6\n            byte = byte | 0x3;  //set pixel 2\n        }\n        if (u8x8->x_offset ==1){\n          if (input & 0x80)          // if bit 7\n            byte = byte | 0xC0;  //set pixel 1\n          if (input & 0x40)          // if bit 6\n            byte = byte | 0x18;  //set pixel 2\n        }\n        output[i] = byte;\n        input <<= 2;\n      }\n      \n      u8x8_cad_SendData(u8x8, 4, output);\n      ptr += 1;\n      c -= 1;\n    }\n    u8x8_cad_EndTransfer(u8x8); \n    break;\n  case U8X8_MSG_DISPLAY_INIT:\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_erc240160_init_seq);\n    break;\n  case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7586s_erc240160_display_info);\n    break;\n  case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n  \tif ( arg_int == 0 )\n    {\n       u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_erc240160_flip0_seq);\n       u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_erc240160_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\t\n    break;\n  case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n    if (arg_int == 0)\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_off);\n    else\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_on);\n    break;\n#ifdef U8X8_WITH_SET_CONTRAST\n  case U8X8_MSG_DISPLAY_SET_CONTRAST:\n    u8x8_cad_StartTransfer(u8x8);\n    u8x8_cad_SendCmd(u8x8, 0x0C0);\n    u8x8_cad_SendArg(u8x8, arg_int);\n    u8x8_cad_SendArg(u8x8, 1);\n    u8x8_cad_EndTransfer(u8x8);\n    break;\n#endif\n  default:\n    return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7586s_s028hn118a.c",
    "content": "/*\n  u8x8_d_st7586s_s028hn118a.c\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n  Copyright (c) 2018, olikraus@gmail.com\n  All rights reserved.\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n\nstatic const uint8_t u8x8_d_st7586s_sleep_on[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x010), /* set power save mode */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_sleep_off[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x011), //Sleep out\n  U8X8_DLY(50), /* delay 50 ms */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_s028hn118a_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),\t\t\t\t/* Scan Direction Setting */\n  U8X8_A(0x000),\t\t\t\t/* COM0 -> COM159 SEG0 -> SEG384 */\n  U8X8_C(0x037),\t\t\t\t/* Start line 0 */\n  U8X8_A(0x000),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_s028hn118a_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),\t\t\t\t/* Scan Direction Setting */\n  U8X8_A(0x0C8),\t\t\t\t/* COM159 -> COM0 SEG384 -> SEG0 */\n  U8X8_C(0x037),\t\t\t\t/* Start line 24 */\n  U8X8_A(0x018),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic uint8_t u8x8_d_st7586s_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) {\n  uint8_t c;\n  uint8_t *ptr;\n  uint8_t i, byte;\n  uint32_t input;\n  uint8_t output[8];\n  switch (msg) {\n  case U8X8_MSG_DISPLAY_DRAW_TILE:\n    u8x8_cad_StartTransfer(u8x8); // OK Start transfer\n    u8x8_cad_SendCmd(u8x8, 0x02B);  /* Row Address Setting */\n    u8x8_cad_SendArg(u8x8, 0x000);\n    u8x8_cad_SendArg(u8x8, 0x008 * ((u8x8_tile_t *)arg_ptr)->y_pos);\n    u8x8_cad_SendArg(u8x8, 0x000);\n    u8x8_cad_SendArg(u8x8, u8x8->display_info->pixel_height - 1);  /* should this be u8x8->display_info->pixel_height - 1 */\n    u8x8_cad_SendCmd(u8x8, 0x02C);  /* cmd write display data to ram */\n    c = ((u8x8_tile_t *) arg_ptr)->cnt; //\n    c *= 8;\n    ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;  //\n\n// The ST7586S has an unusual 3 pixels per byte format so here we read in 3 bytes (24 pixels) and\n// pack that into 8 bytes of 3 pixels each \t\n\twhile (c > 0) {\n      input = (((uint32_t)ptr[0] << 16) | ((uint32_t)ptr[1] << 8) | (uint32_t)ptr[2]);\n      for (i=0; i<8; i++)\n      {\n        byte = 0;\n        if (input & 0x800000)          // if bit 23\n            byte = byte | 0xC0;  //set pixel 1\n        if (input & 0x400000)          // if bit 22\n            byte = byte | 0x18;  //set pixel 2\n\t\tif (input & 0x200000)          // if bit 22\n\t\t\tbyte = byte | 0x3;  //set pixel 3\n\t\toutput[i] = byte;\n        input <<= 3;\n      }\n      u8x8_cad_SendData(u8x8, 8, output);\n      ptr += 3;\n      c -= 3;\n    }\n    u8x8_cad_EndTransfer(u8x8);\n    break;\n  case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n    if (arg_int == 0)\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_off);\n    else\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_on);\n    break;\n#ifdef U8X8_WITH_SET_CONTRAST\n  case U8X8_MSG_DISPLAY_SET_CONTRAST:\n    u8x8_cad_StartTransfer(u8x8);\n    u8x8_cad_SendCmd(u8x8, 0x0C0);\n    u8x8_cad_SendArg(u8x8, arg_int);\n    u8x8_cad_SendArg(u8x8, 0);\n    u8x8_cad_EndTransfer(u8x8);\n    break;\n#endif\n  default:\n    return 0;\n  }\n  return 1;\n}\n\nstatic const uint8_t u8x8_d_st7586s_s028hn118a_init_seq[] = {\n  U8X8_END_TRANSFER(),/* disable chip */\n//  U8G_ESC_RST(15), /* hardware reset */\n  U8X8_DLY(60),   /* Delay 60 ms */\n  U8X8_START_TRANSFER(),/* enable chip */\n\n  U8X8_C(0x001), // Soft reset\n  U8X8_DLY(60), // Delay 120 ms\n\n  U8X8_C(0x011), // Sleep Out\n  U8X8_C(0x028), // Display OFF\n  U8X8_DLY(25), // Delay 50 ms\n\n  U8X8_CAA(0x0C0,0x0E5,0x00),// Vop = F0h in trace a bit too dark\n\n  U8X8_CA(0x0C3,0x004), // BIAS = 1/10 0x04 in trace\n\n  U8X8_CA(0x0C4,0x005), // Booster = x6 0x05 in trace\n\n  U8X8_CA(0x0D0,0x01D), // Enable Analog Circuit\n\n  U8X8_CA(0x0B3,0x000), // Set FOSC divider\n\n  U8X8_CA(0x0B5,0x08B), // N-Line = 0\n\n  U8X8_C(0x039), // 0x39 Monochrome mode. 0x38 - gray Mode\n\n  U8X8_C(0x03A), // Enable DDRAM Interface\n  U8X8_A(0x002), // monochrome and 4-level\n\n  U8X8_C(0x036), // Scan Direction Setting\n  U8X8_A(0x000), // COM0 -> COM159 SEG0 -> SEG384\n\n  U8X8_C(0x0B0), // Duty Setting (num rows - 1)\n  U8X8_A(0x087), // should be 0x87 but caused flicker 0x9F\n\n  U8X8_C(0x020), // Display inversion off\n\n  U8X8_C(0x02A), // Column Address Setting\n  U8X8_A(0x000), // COL0 -> COL127\n  U8X8_A(0x000), // \n  U8X8_A(0x000), //\n  U8X8_A(0x07f), // 128*3=384 pixels\n\n  U8X8_C(0x02B), // Row Address Setting\n  U8X8_A(0x000), // ROW0 -> ROW135\n  U8X8_A(0x000), //\n  U8X8_A(0x000), //\n  U8X8_A(0x087), // 136 pixels\n\n  U8X8_C(0x0F1), // Frame rate monochrome\n  U8X8_A(0x00C), // The factory firmware set this to 49.0 Hz 0x07\n  U8X8_A(0x00C), // This caused a shimmer under 50Hz LED lights\n  U8X8_A(0x00C), // 69.0 Hz (0x0C) fixes this and should avoid the\n  U8X8_A(0x00C), // issue in the US too\n  \n  U8X8_C(0x029), // Display ON\n  U8X8_END()  /* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7586s_s028hn118a_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n\n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 20,\n  /* sck_pulse_width_ns = */  100,  /* datasheet ST7586S */\n  /* sck_clock_hz = */ 8000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* ST7586+Atmega128RFA1 works with 8MHz */\n  /* spi_mode = */ 3,   /* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 20, /* datasheet suggests min 20 */\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 48,\n  /* tile_height = */ 17,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 384,\n  /* pixel_height = */ 136\n};\n\n/*******************************************************************************\n * st7586s_s028hn118a driver. This is the display in the SMART Response XE. This requires 16 bit mode.\n ******************************************************************************/\nuint8_t u8x8_d_st7586s_s028hn118a(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) {\n  if (u8x8_d_st7586s_common(u8x8, msg, arg_int, arg_ptr) != 0)\n    return 1;\n  \n  switch (msg) {\n  case U8X8_MSG_DISPLAY_INIT:\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_s028hn118a_init_seq);\n    break;\n  case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7586s_s028hn118a_display_info);\n    break;\n  case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n  \tif ( arg_int == 0 )\n    {\n       u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_s028hn118a_flip0_seq);\n       u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_s028hn118a_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\t\n    break;\n  default:\n    return 0;\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7586s_ymc240160.c",
    "content": "/*\n  u8x8_d_st7586s_ymc240160.c\n  \n  takeover from https://github.com/olikraus/u8g2/issues/1183\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n  \n  Copyright (c) 2020, olikraus@gmail.com\n  \n  All rights reserved.\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8g2.h\"\n\n\nstatic const uint8_t u8x8_d_st7586s_sleep_on[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x010), /* set power save mode */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_sleep_off[] = {\n  U8X8_START_TRANSFER(),  /* enable chip, delay is part of the transfer start */\n  U8X8_C(0x011), //Sleep out\n  U8X8_DLY(50), /* delay 50 ms */\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()                  /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_ymc240160_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),  /* Scan Direction Setting */\n  U8X8_A(0x080),\t/* COM159 -> COM0 SEG383 -> SEG0 */\n  U8X8_C(0x037),\t/* Start line 0 */\n  U8X8_A(0x000),\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()           \t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_ymc240160_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x036),  /* Scan Direction Setting */\n  U8X8_A(0x000),  /* COM0 -> COM159 SEG0 -> SEG383 */\n  U8X8_C(0x037),  /* Start line 0 */\n  U8X8_A(0x000),\n  U8X8_END_TRANSFER(),  /* disable chip */\n  U8X8_END()            /* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7586s_ymc240160_init_seq[] = {\n  U8X8_END_TRANSFER(),/* disable chip */\n // U8G_ESC_RST(1), /* hardware reset */\n  U8X8_DLY(60),   /* Delay 60 ms */\n  U8X8_START_TRANSFER(),/* enable chip */\n\n  U8X8_C(0x001), // Soft reset\n  U8X8_DLY(60), // Delay 120 ms\n\n  U8X8_C(0x011), // Sleep Out\n  U8X8_C(0x028), // Display OFF\n  U8X8_DLY(25), // Delay 50 ms\n\n  U8X8_CAA(0x0C0,0x036,0x01),// Vop = 136h data sheet suggested 0x0145 but this caused streaks\n\n  U8X8_CA(0x0C3,0x000), // BIAS = 1/14\n\n  U8X8_CA(0x0C4,0x007), // Booster = x8\n\n  U8X8_CA(0x0D0,0x01D), // Enable Analog Circuit\n\n  U8X8_CA(0x0B3,0x000), // Set FOSC divider\n\n  U8X8_CA(0x0B5,0x000), // N-Line = 0\n\n  U8X8_C(0x039), // 0x39 Monochrome mode. 0x38 - gray Mode\n\n  U8X8_C(0x03A), // Enable DDRAM Interface\n  U8X8_A(0x002), // monochrome and 4-level\n\n  U8X8_C(0x036), // Scan Direction Setting\n  U8X8_A(0x080), // COM:C159->C0   SEG: SEG383->SEG0\n\n  U8X8_C(0x0B1), // First output COM\n  U8X8_A(0x000), // \n  \n  U8X8_C(0x0B0), // Duty Setting (num rows - 1)\n  U8X8_A(0x09F), \n\n  U8X8_C(0x020), // Display inversion off\n\n  U8X8_C(0x02A), // Column Address Setting\n  U8X8_A(0x000), // COL0 -> COL127\n  U8X8_A(0x000), // \n  U8X8_A(0x000), //\n  U8X8_A(0x04F), // 80*3=240 pixels\n\n  U8X8_C(0x02B), // Row Address Setting\n  U8X8_A(0x000), // ROW0 -> ROW159\n  U8X8_A(0x000), //\n  U8X8_A(0x000), //\n  U8X8_A(0x09F), // 160 pixels\n\n  U8X8_C(0x029), // Display ON\n  U8X8_END()  /* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_st7586s_ymc240160_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n\n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1,\n  /* post_reset_wait_ms = */ 6,\n  /* sda_setup_time_ns = */ 20,\n  /* sck_pulse_width_ns = */  100,  /* datasheet ST7586S */\n  /* sck_clock_hz = */ 8000000UL, /* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* ST7586+Atmega128RFA1 works with 8MHz */\n  /* spi_mode = */ 3,   /* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 20, /* datasheet suggests min 20 */\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 30,\n  /* tile_height = */ 20,\n  /* default_x_offset = */ 0,  /* abused as flag to know if we are flipped */\n  /* flipmode_x_offset = */ 1, /* as pixel order different for normal/flipped  */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 160\n};\n\n/*  takeover from https://github.com/olikraus/u8g2/issues/1183 */\nuint8_t u8x8_d_st7586s_ymc240160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr) \n{  \n  uint8_t c;\n  uint8_t *ptr;\n  uint8_t i, byte;\n  uint32_t input;\n  uint8_t output[8];\n//  uint8_t output[4];\n  switch (msg) {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n    u8x8_cad_StartTransfer(u8x8); // OK Start transfer\n    u8x8_cad_SendCmd(u8x8, 0x02B);  /* Row Address Setting */\n    u8x8_cad_SendArg(u8x8, 0x000);\n    u8x8_cad_SendArg(u8x8, 0x008 * ((u8x8_tile_t *)arg_ptr)->y_pos);\n    u8x8_cad_SendArg(u8x8, 0x000);\n//    u8x8_cad_SendArg(u8x8, 0x09F); // should set end row based on display dimensions\n    u8x8_cad_SendArg(u8x8, u8x8->display_info->pixel_height - 1);  /* should this be u8x8->display_info->pixel_height - 1 */\n    u8x8_cad_SendCmd(u8x8, 0x02C);  /* cmd write display data to ram */\n    c = ((u8x8_tile_t *) arg_ptr)->cnt; //\n    c *= 8;\n    ptr = ((u8x8_tile_t *) arg_ptr)->tile_ptr;  //\n\n    while (c > 0) \n    {\n      input = (((uint32_t)ptr[0] << 16) | ((uint32_t)ptr[1] << 8) | (uint32_t)ptr[2]);\n      for (i=0; i<8; i++)\n      {\n        byte = 0;\n        if (input & 0x800000)          // if bit 23\n            byte = byte | 0xC0;  //set pixel 1\n        if (input & 0x400000)          // if bit 22\n            byte = byte | 0x18;  //set pixel 2\n        if (input & 0x200000)          // if bit 22\n            byte = byte | 0x3;  //set pixel 3\n        output[i] = byte;\n        input <<= 3;\n      }\n      u8x8_cad_SendData(u8x8, 8, output);\n      ptr += 3;\n      c -= 3;\n    }\n    u8x8_cad_EndTransfer(u8x8); \n    break;\n  case U8X8_MSG_DISPLAY_INIT:\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_ymc240160_init_seq);\n    break;\n  case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7586s_ymc240160_display_info);\n    break;\n  case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n  \tif ( arg_int == 0 )\n    {\n       u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_ymc240160_flip0_seq);\n       u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_ymc240160_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\t\n    break;\n  case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n    if (arg_int == 0)\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_off);\n    else\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7586s_sleep_on);\n    break;\n#ifdef U8X8_WITH_SET_CONTRAST\n  case U8X8_MSG_DISPLAY_SET_CONTRAST:\n    u8x8_cad_StartTransfer(u8x8);\n    u8x8_cad_SendCmd(u8x8, 0x0C0);\n    u8x8_cad_SendArg(u8x8, arg_int);\n    u8x8_cad_SendArg(u8x8, 1);\n    u8x8_cad_EndTransfer(u8x8);\n    break;\n#endif\n  default:\n    return 0;\n  }\n  return 1;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7588.c",
    "content": "/*\n\n  u8x8_d_st7588.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  ST7588\n    - has 4 different I2C addresses \n    - I2C protocol is identical to SSD13xx\n  \n*/\n\n\n#include \"u8x8.h\"\n\n/* function set, bit 2: power down, bit 3: MY, bit 4: MX, bit 5: must be 1 */\n#define FS (0x020)\n\n/* not a real power down for the ST7588... just a display off */\nstatic const uint8_t u8x8_d_st7588_128x64_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( FS | 0x00 ),\t\t\t/* select 00 commands */\n  //U8X8_C( 0x08 ),\t\t\t\t/* display off */\n  U8X8_C( 0x0c ),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7588_128x64_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( FS | 0x00 ),\t\t\t/* select 00 commands */\n  U8X8_C( 0x08 ),\t\t\t\t/* display off */\n  //U8X8_C( 0x0c ),\t\t\t\t/* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n\n\nstatic uint8_t u8x8_d_st7588_128x64_generic(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7588_128x64_display_info);\n      break;\n    */\n    /* handled by the calling function\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7588_128x64_init_seq);    \n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7588_128x64_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7588_128x64_powersave1_seq);\n\n      /* restore orientation */\n      if ( u8x8->x_offset == 0 )\n\tu8x8_cad_SendCmd(u8x8, FS );\t/* select 00 commands */\n      else\n\tu8x8_cad_SendCmd(u8x8, FS ^ 0x018 );\t/* select 00 commands */\n      \n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n\n      u8x8_cad_StartTransfer(u8x8);\n      \n      u8x8_cad_SendCmd(u8x8, FS );\n      u8x8_cad_SendArg(u8x8, 4 | (arg_int>>7) );\n      u8x8_cad_SendCmd(u8x8, FS | 1);\n      u8x8_cad_SendArg(u8x8, 0x080 | arg_int );\n      \n      /* restore orientation */\n      if ( u8x8->x_offset == 0 )\n\tu8x8_cad_SendCmd(u8x8, FS );\t/* select 00 commands */\n      else\n\tu8x8_cad_SendCmd(u8x8, FS ^ 0x018 );\t/* select 00 commands */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      \n      u8x8_cad_StartTransfer(u8x8);\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;    \n      x *= 8;\n      \n      x += u8x8->x_offset;\n    \n      if ( u8x8->x_offset == 0 )\n\tu8x8_cad_SendCmd(u8x8, FS );\t/* select 00 commands */\n      else\n\tu8x8_cad_SendCmd(u8x8, FS ^ 0x018 );\t/* select 00 commands */\n\t\n      u8x8_cad_SendCmd(u8x8, 0x040 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n      u8x8_cad_SendCmd(u8x8, 0x0e0 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0f0 | (x>>4) );\n    \n      \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tu8x8_cad_SendData(u8x8, c*8, ptr); \t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=============================================*/\n\nstatic const u8x8_display_info_t u8x8_st7588_128x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 150,\n  /* pre_chip_disable_wait_ns = */ 30,\n  /* reset_pulse_width_ms = */ 5, \t\n  /* post_reset_wait_ms = */ 5, \t\t/**/\n  /* sda_setup_time_ns = */ 60,\t\t/* */\n  /* sck_pulse_width_ns = */ 60,\t/*  */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\t/* 400KHz */\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 50,\t\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t/* must be 0, because this is checked also for normal mode */\n  /* flipmode_x_offset = */ 4,\t\t\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n\n\nstatic const uint8_t u8x8_d_st7588_128x64_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C( FS | 0x03 ),\t\t\t/* select 11 commands */\n  U8X8_C( 0x03 ),\t\t\t\t/* software reset */\n\n  U8X8_C( FS | 0x00 ),\t\t\t/* select 00 commands */\n  U8X8_C( 0x08 ),\t\t\t\t/* display off */\n  //U8X8_C( 0x0c ),\t\t\t\t/* display on */\n  \n  U8X8_C( FS | 0x01 ),\t\t\t/* select 01 commands */\n  U8X8_C( 0x08 ),\t\t\t\t/* display confguration */\n  U8X8_C( 0x12 ),\t\t\t\t/* bias 1/9 */\n  U8X8_C( 0x8f ),\t\t\t\t/* Vop, lower 7 bits */\n  \n  U8X8_C( FS | 0x00 ),\t\t\t/* select 00 commands */\n  U8X8_C( 0x05),\t\t\t\t/* Bit 0 contains high/low range for Vop */\n  \n  \n  U8X8_C( FS | 0x03 ),\t\t\t/* select 11 commands */\n  U8X8_C( 0x0b),\t\t\t\t/* Frame Rate: 73 Hz */\n  \n  \n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const uint8_t u8x8_d_st7588_jlx12864_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( FS ),\t\t\t\t\t/* normal mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7588_jlx12864_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C( FS ^ 0x018 ),\t\t\t\t\t/* normal mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st7588_jlx12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  if ( u8x8_d_st7588_128x64_generic(u8x8, msg, arg_int, arg_ptr) != 0 )\n    return 1;\n  if ( msg == U8X8_MSG_DISPLAY_SETUP_MEMORY )\n  {\n    u8x8_SetI2CAddress(u8x8, 0x07e);\t\t/* the JLX12864 has 0x07e as a default address for I2C */\n    u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7588_128x64_display_info);\n    return 1;\n  }\n  else if ( msg == U8X8_MSG_DISPLAY_INIT )\n  {\n    u8x8_d_helper_display_init(u8x8);\n    u8x8_cad_SendSequence(u8x8, u8x8_d_st7588_128x64_init_seq);    \n    return 1;\n  }\n  else if  ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n    if ( arg_int == 0 )\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7588_jlx12864_flip0_seq);\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n    }\n    else\n    {\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7588_jlx12864_flip1_seq);\n      u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n    }\n    return 1;\n  }\n  return 0;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_st7920.c",
    "content": "/*\n\n  u8x8_d_st7920.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  The ST7920 controller does not support hardware graphics flip.\n  Contrast adjustment is done by an external resistor --> no support for contrast adjustment\n  \n  \n*/\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_st7920_init_seq[] = {\n    \n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(10),\n  \n  U8X8_C(0x038),            \t\t\t/* 8 Bit interface (DL=1), basic instruction set (RE=0) */\n  U8X8_C(0x008),\t\t                /* display on, cursor & blink off; 0x08: all off */\n  U8X8_C(0x006),\t\t                /* Entry mode: Cursor move to right ,DDRAM address counter (AC) plus 1, no shift  */  \n  U8X8_C(0x002),\t\t                /* disable scroll, enable CGRAM adress  */\n  U8X8_C(0x001),\t\t                /* clear RAM, needs 1.6 ms */\n  U8X8_DLY(4),\t\t\t\t\t/* delay 2ms */\n\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7920_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x038),            \t\t\t/* 8 Bit interface (DL=1), basic instruction set (RE=0) */\n  U8X8_C(0x00c),\t\t                /* display on, cursor & blink off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_st7920_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x038),            \t\t\t/* 8 Bit interface (DL=1), basic instruction set (RE=0) */\n  U8X8_C(0x008),\t\t                /* display off */\n  U8X8_C(0x034), /* 8 Bit interface (DL=1), extended instruction set (RE=1) */\n  U8X8_C(0x001), /* Standby mode */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_st7920_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c, i;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    */\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_st7920_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7920_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_st7920_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y*=8;\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x /= 2;\t\t/* not sure whether this is a clever idea, problem is, the ST7920 can address only every second tile */\n    \n      if ( y >= 32 )\t/* this is the adjustment for 128x64 displays */\n      {\n\ty-=32;\n\tx+=8;\n      }\n    \n      u8x8_cad_StartTransfer(u8x8);\n        \n\n      /* \n\tTile structure is reused here for the ST7920, however u8x8 is not supported \n\ttile_ptr points to data which has cnt*8 bytes (same as SSD1306 tiles)\n\tBuffer is expected to have 8 lines of code fitting to the ST7920 internal memory\n\t\"cnt\" includes the number of horizontal bytes. width is equal to cnt*8\n\tAlso important: Width must be a multiple of 16 (ST7920 requirement), so cnt must be even.\n\t\n\tTODO: Consider arg_int, however arg_int is not used by u8g2\n      */\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      /* The following byte is sent to allow the ST7920 to sync up with the data */\n      /* it solves some issues with garbage data */\n      u8x8_cad_SendCmd(u8x8, 0x03e );\t/* enable extended mode */\n      u8x8_cad_SendCmd(u8x8, 0x03e );\t/* enable extended mode, issue 487 */\n      for( i = 0; i < 8; i++ )\n      {\n\t//u8x8_cad_SendCmd(u8x8, 0x03e );\t/* enable extended mode */\n\tu8x8_cad_SendCmd(u8x8, 0x080 | (y+i) );      /* y pos  */\n\tu8x8_cad_SendCmd(u8x8, 0x080 | x );      /* set x pos */\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n\n\t//u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes, send one line of data */\n\tptr += c;\n\t//u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n      }\n\n      u8x8_cad_EndTransfer(u8x8);\n\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\nstatic const u8x8_display_info_t u8x8_st7920_192x32_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t/* datasheet ST7920 */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 3,\t\t/* old: sck_takeover_edge, new: active high (bit 1), rising edge (bit 0), 18 Aug 16: changed from 1 to 3 which works for 101 */\n\t/* Arduino mode 3: aktive low clock, but use rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 24,\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 192,\n  /* pixel_height = */ 32\n};\n\nstatic const u8x8_display_info_t u8x8_st7920_128x64_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t/* datasheet ST7920 */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* ST7920+Due work with 1MHz but not with 2MHz, ST7920+Uno works with 2MHz */\n  /* spi_mode = */ 3,\t\t/* active high, rising edge, 18 Aug 16: changed from 1 to 3 which works for 101  */\n  /* in theory mode 3 should be correct  */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_st7920_192x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7920_192x32_display_info);\n      break;\n    default:\n      return u8x8_d_st7920_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\nuint8_t u8x8_d_st7920_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_st7920_128x64_display_info);\n      break;\n    default:\n      return u8x8_d_st7920_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n\n  \n\n  "
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_stdio.c",
    "content": "/*\n\n  u8x8_d_stdio.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n#include \"u8x8.h\"\n\n#include <stdio.h>\n\n#define W 8\n#define H 2\n\nuint8_t bitmap[W * H * 8];\n\nvoid bitmap_place_tile(uint8_t x, uint8_t y, uint8_t *tile)\n{\n    uint8_t i;\n    for (i = 0; i < 8; i++)\n        bitmap[x * 8 + y * W * 8 + i] = tile[i];\n}\n\nvoid bitmap_show(void)\n{\n    int x, y;\n    for (y = 0; y < H * 8; y++)\n    {\n        for (x = 0; x < W * 8; x++)\n        {\n            if ((bitmap[x + (y / 8) * W * 8] & (1 << ((y & 7)))) != 0)\n            {\n                printf(\"*\");\n            } else\n            {\n                printf(\".\");\n            }\n        }\n        printf(\"\\n\");\n    }\n}\n\n\nuint8_t u8x8_d_stdio(U8X8_UNUSED u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n    switch (msg)\n    {\n        case U8X8_MSG_DISPLAY_INIT:\n            break;\n        case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n            if (arg_int == 0)\n                bitmap_show();\n            break;\n        case U8X8_MSG_DISPLAY_SET_CONTRAST:\n            break;\n        case U8X8_MSG_DISPLAY_DRAW_TILE:\n            bitmap_place_tile(((u8x8_tile_t *) arg_ptr)->x_pos, ((u8x8_tile_t *) arg_ptr)->y_pos,\n                              ((u8x8_tile_t *) arg_ptr)->tile_ptr);\n            break;\n        default:\n            break;\n    }\n    return 1;\n}\n\n\nvoid u8x8_SetupStdio(u8x8_t *u8x8)\n{\n    u8x8_SetupDefaults(u8x8);\n    u8x8->display_cb = u8x8_d_stdio;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_t6963.c",
    "content": "/*\n\n  u8x8_d_t6963.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  The t6963 controller does not support hardware graphics flip.\n  Contrast adjustment is done by an external resistor --> no support for contrast adjustment\n  \n  \n*/\n#include \"u8x8.h\"\n\n\n\nstatic const uint8_t u8x8_d_t6963_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x098),                            /* mode register: Display Mode, Graphics on, Text off, Cursor off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_t6963_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_t6963_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t c, i;\n  uint16_t y;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    /* U8X8_MSG_DISPLAY_SETUP_MEMORY is handled by the calling function */\n    /*\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_t6963_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_t6963_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      y = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      y*=8;\n      y*= u8x8->display_info->tile_width;\n      /* x = ((u8x8_tile_t *)arg_ptr)->x_pos; x is ignored... no u8x8 support */\n      //u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n      u8x8_cad_StartTransfer(u8x8);\n      //u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n      /* \n\tTile structure is reused here for the t6963, however u8x8 is not supported \n\ttile_ptr points to data which has cnt*8 bytes (same as SSD1306 tiles)\n\tBuffer is expected to have 8 lines of code fitting to the t6963 internal memory\n\t\"cnt\" includes the number of horizontal bytes. width is equal to cnt*8\n\t\n\tTODO: Consider arg_int, however arg_int is not used by u8g2\n      */\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\t/* data ptr to the tiles */\n      for( i = 0; i < 8; i++ )\n      {\n\tu8x8_cad_SendArg(u8x8, y&255);\n\tu8x8_cad_SendArg(u8x8, y>>8);\n\tu8x8_cad_SendCmd(u8x8, 0x024 );\t/* set adr */\n\tu8x8_cad_SendCmd(u8x8, 0x0b0 );\t/* auto write start */\n\t\n\t\n\t//c = ((u8x8_tile_t *)arg_ptr)->cnt;\t/* number of tiles */\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes, send one line of data */\n\t\n\tu8x8_cad_SendCmd(u8x8, 0x0b2 );\t/* auto write reset */\n\tptr += u8x8->display_info->tile_width;\n\ty += u8x8->display_info->tile_width;\n      }\n\n      u8x8_cad_EndTransfer(u8x8);\n      //u8x8->gpio_and_delay_cb(u8x8, U8X8_MSG_DELAY_NANO, 200, NULL);\t/* extra dely required */\n\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*=============================================*/\n\n\nstatic const u8x8_display_info_t u8x8_t6963_240x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 110,\t/* T6963 Datasheet p30 */\n  /* pre_chip_disable_wait_ns = */ 100,\t/* T6963 Datasheet p30 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 80,\n  /* tile_width = */ 30,\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 128\n};\n\n/* 240x128 */\nstatic const uint8_t u8x8_d_t6963_240x128_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n  \n  U8X8_AAC(0x00,0x00,0x021),\t/* low, high, set cursor pos */\n  U8X8_AAC(0x00,0x00,0x022),\t/* low, high, set offset */\n  U8X8_AAC(0x00,0x00,0x040),\t/* low, high, set text home */\n  U8X8_AAC(240/8,0x00,0x041),\t/* low, high, set text columns */\n  U8X8_AAC(0x00,0x00,0x042),\t/* low, high, graphics home */  \n  U8X8_AAC(240/8,0x00,0x043),\t/* low, high, graphics columns */\n  U8X8_DLY(2),\t\t\t\t\t/* delay 2ms */\n  // mode set\n  // 0x080: Internal CG, OR Mode\n  // 0x081: Internal CG, EXOR Mode\n  // 0x083: Internal CG, AND Mode\n  // 0x088: External CG, OR Mode\n  // 0x089: External CG, EXOR Mode\n  // 0x08B: External CG, AND Mode\n  U8X8_C(0x080),            \t\t\t/* mode register: OR Mode, Internal Character Mode */\n  // display mode\n  // 0x090: Display off\n  // 0x094: Graphic off, text on, cursor off, blink off\n  // 0x096: Graphic off, text on, cursor on, blink off\n  // 0x097: Graphic off, text on, cursor on, blink on\n  // 0x098: Graphic on, text off, cursor off, blink off\n  // 0x09a: Graphic on, text off, cursor on, blink off\n  // ...\n  // 0x09c: Graphic on, text on, cursor off, blink off\n  // 0x09f: Graphic on, text on, cursor on, blink on\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_AAC(0x00,0x00,0x024),\t/* low, high, set adr pointer */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\nuint8_t u8x8_d_t6963_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_240x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_240x128_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n\n/*=============================================*/\n\nstatic const u8x8_display_info_t u8x8_t6963_240x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 110,\t/* T6963 Datasheet p30 */\n  /* pre_chip_disable_wait_ns = */ 100,\t/* T6963 Datasheet p30 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 80,\n  /* tile_width = */ 30,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\n\n/* 240x64 */\nstatic const uint8_t u8x8_d_t6963_240x64_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n  \n  U8X8_AAC(0x00,0x00,0x021),\t/* low, high, set cursor pos */\n  U8X8_AAC(0x00,0x00,0x022),\t/* low, high, set offset */\n  U8X8_AAC(0x00,0x00,0x040),\t/* low, high, set text home */\n  U8X8_AAC(240/8,0x00,0x041),\t/* low, high, set text columns */\n  U8X8_AAC(0x00,0x00,0x042),\t/* low, high, graphics home */  \n  U8X8_AAC(240/8,0x00,0x043),\t/* low, high, graphics columns */\n  U8X8_DLY(2),\t\t\t\t\t/* delay 2ms */\n  // mode set\n  // 0x080: Internal CG, OR Mode\n  // 0x081: Internal CG, EXOR Mode\n  // 0x083: Internal CG, AND Mode\n  // 0x088: External CG, OR Mode\n  // 0x089: External CG, EXOR Mode\n  // 0x08B: External CG, AND Mode\n  U8X8_C(0x080),            \t\t\t/* mode register: OR Mode, Internal Character Mode */\n  // display mode\n  // 0x090: Display off\n  // 0x094: Graphic off, text on, cursor off, blink off\n  // 0x096: Graphic off, text on, cursor on, blink off\n  // 0x097: Graphic off, text on, cursor on, blink on\n  // 0x098: Graphic on, text off, cursor off, blink off\n  // 0x09a: Graphic on, text off, cursor on, blink off\n  // ...\n  // 0x09c: Graphic on, text on, cursor off, blink off\n  // 0x09f: Graphic on, text on, cursor on, blink on\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_AAC(0x00,0x00,0x024),\t/* low, high, set adr pointer */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\nuint8_t u8x8_d_t6963_240x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_240x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_240x64_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n\n/*=============================================*/\n\n\n\nstatic const u8x8_display_info_t u8x8_t6963_256x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 110,\t/* T6963 Datasheet p30 */\n  /* pre_chip_disable_wait_ns = */ 100,\t/* T6963 Datasheet p30 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 80,\n  /* tile_width = */ 32,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 64\n};\n\n/* 256x64 */\nstatic const uint8_t u8x8_d_t6963_256x64_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n  \n  U8X8_AAC(0x00,0x00,0x021),\t/* low, high, set cursor pos */\n  U8X8_AAC(0x00,0x00,0x022),\t/* low, high, set offset */\n  U8X8_AAC(0x00,0x00,0x040),\t/* low, high, set text home */\n  U8X8_AAC(256/8,0x00,0x041),\t/* low, high, set text columns */\n  U8X8_AAC(0x00,0x00,0x042),\t/* low, high, graphics home */  \n  U8X8_AAC(256/8,0x00,0x043),\t/* low, high, graphics columns */\n  U8X8_DLY(2),\t\t\t\t\t/* delay 2ms */\n  // mode set\n  // 0x080: Internal CG, OR Mode\n  // 0x081: Internal CG, EXOR Mode\n  // 0x083: Internal CG, AND Mode\n  // 0x088: External CG, OR Mode\n  // 0x089: External CG, EXOR Mode\n  // 0x08B: External CG, AND Mode\n  U8X8_C(0x080),            \t\t\t/* mode register: OR Mode, Internal Character Mode */\n  // display mode\n  // 0x090: Display off\n  // 0x094: Graphic off, text on, cursor off, blink off\n  // 0x096: Graphic off, text on, cursor on, blink off\n  // 0x097: Graphic off, text on, cursor on, blink on\n  // 0x098: Graphic on, text off, cursor off, blink off\n  // 0x09a: Graphic on, text off, cursor on, blink off\n  // ...\n  // 0x09c: Graphic on, text on, cursor off, blink off\n  // 0x09f: Graphic on, text on, cursor on, blink on\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_AAC(0x00,0x00,0x024),\t/* low, high, set adr pointer */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\nuint8_t u8x8_d_t6963_256x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_256x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_256x64_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n/*=============================================*/\n\nstatic const u8x8_display_info_t u8x8_t6963_128x64_display_info =\n{\n  /* chip_enable_level = */ 1,\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* T6963 Datasheet p30 */\n  /* pre_chip_disable_wait_ns = */ 100,\t/* T6963 Datasheet p30 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 80,\n  /* tile_width = */ 16,\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\n/* 128x64 */\nstatic const uint8_t u8x8_d_t6963_128x64_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n  \n  U8X8_AAC(0x00,0x00,0x021),\t/* low, high, set cursor pos */\n  U8X8_AAC(0x00,0x00,0x022),\t/* low, high, set offset */\n  U8X8_AAC(0x00,0x00,0x040),\t/* low, high, set text home */\n  U8X8_AAC(128/8,0x00,0x041),\t/* low, high, set text columns */\n  U8X8_AAC(0x00,0x00,0x042),\t/* low, high, graphics home */  \n  U8X8_AAC(128/8,0x00,0x043),\t/* low, high, graphics columns */\n  U8X8_DLY(2),\t\t\t\t\t/* delay 2ms */\n  // mode set\n  // 0x080: Internal CG, OR Mode\n  // 0x081: Internal CG, EXOR Mode\n  // 0x083: Internal CG, AND Mode\n  // 0x088: External CG, OR Mode\n  // 0x089: External CG, EXOR Mode\n  // 0x08B: External CG, AND Mode\n  U8X8_C(0x080),            \t\t\t/* mode register: OR Mode, Internal Character Mode */\n  // display mode\n  // 0x090: Display off\n  // 0x094: Graphic off, text on, cursor off, blink off\n  // 0x096: Graphic off, text on, cursor on, blink off\n  // 0x097: Graphic off, text on, cursor on, blink on\n  // 0x098: Graphic on, text off, cursor off, blink off\n  // 0x09a: Graphic on, text off, cursor on, blink off\n  // ...\n  // 0x09c: Graphic on, text on, cursor off, blink off\n  // 0x09f: Graphic on, text on, cursor on, blink on\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_AAC(0x00,0x00,0x024),\t/* low, high, set adr pointer */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\nuint8_t u8x8_d_t6963_128x64(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_128x64_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n/*=============================================*/\n\nstatic const u8x8_display_info_t u8x8_t6963_160x80_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* T6963 Datasheet p30 */\n  /* pre_chip_disable_wait_ns = */ 100,\t/* T6963 Datasheet p30 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 20,\t\t\n  /* sck_pulse_width_ns = */  140,\t\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 80,\n  /* write_pulse_width_ns = */ 80,\n  /* tile_width = */ 20,\n  /* tile_hight = */ 10,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 80\n};\n\n/* 128x64 */\nstatic const uint8_t u8x8_d_t6963_160x80_init_seq[] = {\n  U8X8_DLY(100),\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(100),\n  \n  U8X8_AAC(0x00,0x00,0x021),\t/* low, high, set cursor pos */\n  U8X8_AAC(0x00,0x00,0x022),\t/* low, high, set offset */\n  U8X8_AAC(0x00,0x00,0x040),\t/* low, high, set text home */\n  U8X8_AAC(160/8,0x00,0x041),\t/* low, high, set text columns */\n  U8X8_AAC(0x00,0x00,0x042),\t/* low, high, graphics home */  \n  U8X8_AAC(160/8,0x00,0x043),\t/* low, high, graphics columns */\n  U8X8_DLY(2),\t\t\t\t\t/* delay 2ms */\n  // mode set\n  // 0x080: Internal CG, OR Mode\n  // 0x081: Internal CG, EXOR Mode\n  // 0x083: Internal CG, AND Mode\n  // 0x088: External CG, OR Mode\n  // 0x089: External CG, EXOR Mode\n  // 0x08B: External CG, AND Mode\n  U8X8_C(0x080),            \t\t\t/* mode register: OR Mode, Internal Character Mode */\n  // display mode\n  // 0x090: Display off\n  // 0x094: Graphic off, text on, cursor off, blink off\n  // 0x096: Graphic off, text on, cursor on, blink off\n  // 0x097: Graphic off, text on, cursor on, blink on\n  // 0x098: Graphic on, text off, cursor off, blink off\n  // 0x09a: Graphic on, text off, cursor on, blink off\n  // ...\n  // 0x09c: Graphic on, text on, cursor off, blink off\n  // 0x09f: Graphic on, text on, cursor on, blink on\n  U8X8_C(0x090),                             /* All Off */\n  U8X8_AAC(0x00,0x00,0x024),\t/* low, high, set adr pointer */\n  \n  U8X8_DLY(100),\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_DLY(100),\n};\n\nuint8_t u8x8_d_t6963_160x80(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_160x80_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_160x80_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n/* alternative version for the 128x64 t6963 display: use the 160x80 init sequence */\nuint8_t u8x8_d_t6963_128x64_alt(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_t6963_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_t6963_160x80_init_seq);\n      break;\n    default:\n      return u8x8_d_t6963_common(u8x8, msg, arg_int, arg_ptr);\n  }\n  return 1;\n}\n\n\n  \n\n  "
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1601.c",
    "content": "/*\n\n  u8x8_d_uc1601.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  This is for the uc1601s controller\n  \n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_uc1601_128x32_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1601_128x32_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1601_128x32_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c4),\t\t\t\t/* bit 1: MX, bit 2: MY */\n  U8X8_C(0x060),\t\t                /* set display start line to 32 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1601_128x32_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c2),\t\t\t\t/* bit 1: MX, bit 2: MY */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_uc1601_128x32_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 1,\t/* uc1601 datasheet, page 46 */\n  /* pre_chip_disable_wait_ns = */ 5,\t/* uc1601 datasheet, page 46 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 12,\t\t/* uc1601 datasheet, page 44 */\n  /* sck_pulse_width_ns = */ 15,\t/* uc1601 datasheet, page 44 */\n  /* sck_clock_hz = */ 2000000UL,\t/* */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 1,\n  /* data_setup_time_ns = */ 60,\t/* uc1601 datasheet, page 43 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1601 datasheet, page 43 */\n  /* tile_width = */ 16,\t\t\n  /* tile_hight = */ 4,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 4,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 32\n};\n\nstatic const uint8_t u8x8_d_uc1601_128x32_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0eb),            \t\t\t/* LCD Bias: 0xe8: 6, 0xe9: 7, 0xea: 8, 0xeb: 9 */\n  //U8X8_C(0x023),            \t\t\t/* 0x020...0x023 only for UC1601, not for UC1601s */\n\t\n\n  //U8X8_C(0x02e),            \t\t\t/* LCD Load + Internal Charge Pump (default: 0x2e) */\n  U8X8_C(0x024),\t\t                /* Temperature Compenstation, default: 0x24 */\n  U8X8_C(0x089),\t\t                /* RAM address ctrl, default: 0x89 */\n  U8X8_C(0x0c4),\t\t                /* RAM mapping ctrl */\n  U8X8_C(0x0a0),\t\t                /* Frame Rate, 0x0a0 or 0x0a1 */\n  U8X8_CA(0x081, 0x0df),\t\t/* set contrast */\n  U8X8_C(0x02e),            \t\t\t/* LCD Load + Internal Charge Pump (default: 0x2e) */\t\n  U8X8_C(0x060),\t\t                /* set display start line to 32 */\n  \n  U8X8_C(0x0a6),\t\t                /* normal display */\n   \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1601_128x32(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1601_128x32_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1601_128x32_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1601_128x32_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1601_128x32_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1601_128x32_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1601_128x32_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int );\t/* uc1601 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1604.c",
    "content": "/*\n\n  u8x8_d_uc1604.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_uc1604_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_DLY(20),\t\t\t\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_DLY(20),\t\t\t\t/* during setup, it seems that the startup is more reliable when sending this cmd twice */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_DLY(50),\t\t\t\t/* startup takes some time */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1604_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off, enter sleep mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1604_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c4),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1604_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c2),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_uc1604_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n   \n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n    \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (y&15));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1604_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1604_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1604_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1604_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1604_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1604 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* JLX19264 */\n\n/* \n  timings from uc1608 \n\n  UC1604 has two chip select inputs (CS0 and CS1).\n  CS0 is low active, CS1 is high active. It will depend on the display\n  module whether the display has a is low or high active chip select.\n\n*/\nstatic const u8x8_display_info_t u8x8_uc1604_192x64_display_info =\n{\n  /* chip_enable_level = */ 0,\t/* JLX19264G uses CS0, which is low active CS*/\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 20,\t\n  /* pre_chip_disable_wait_ns = */ 20,\t\n  /* reset_pulse_width_ms = */ 1, \t\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t\n  /* write_pulse_width_ns = */ 35,\t\n  /* tile_width = */ 24,\t\t/* width of 24*8=192 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 0,\t/* reused as y page offset */\n  /* pixel_width = */ 192,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_uc1604_jlx19264_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_DLY(200),\n  U8X8_DLY(200),\n\n  U8X8_C(0x02f),            \t\t\t/* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */\n  U8X8_DLY(200),\n  U8X8_DLY(200),\n  \n  U8X8_CA(0x081, 0x052),\t\t/* set contrast, JLX19264G suggestion: 0x045 */\n  U8X8_C(0x0eb),            \t\t\t/* LCD bias Bits 0/1: 00=6 01=7, 10=8, 11=9 */\n\n  \n  //U8X8_C(0x023),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n  //U8X8_C(0x027),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n\n  U8X8_C(0x0c4),            \t\t\t/* Map control, Bit 2: MY=1, Bit 1: MX=0 */\n  U8X8_C(0x0a0),            \t\t\t/* 0xa0: 76Hz FPS, controller default: 0x0a1: 95Hz FPS */\n  \n  \n  U8X8_C(0x040),            \t\t\t/* set scroll line to 0 */\n  U8X8_C(0x089),            \t\t\t/* RAM access control (controller default: 0x089)*/\n  \n  \n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x0b0),\t\t                /* page adr  */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1604_jlx19264(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1604_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1604_192x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1604_jlx19264_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1608.c",
    "content": "/*\n\n  u8x8_d_uc1608.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_uc1608_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1608_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off, enter sleep mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1608_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c8),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1608_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c4),            \t\t\t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_uc1608_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n   \n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n    \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (y&15));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1608 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* ERC24064-1 */\n\n/*\n  The UC1608 has only one high active chip select input.\n  UC1604, UC1610 and UC1611 have two chip select inputs.\n*/\n\nstatic const u8x8_display_info_t u8x8_uc1608_240x64_display_info =\n{\n  /* chip_enable_level = */ 1,\t/* uc1608 has high active CS */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1608 datasheet, page 39, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* uc1608 datasheet, page 39 */\n  /* reset_pulse_width_ms = */ 1, \t/* uc1608 datasheet, page 42 */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* uc1608 datasheet, page 41 */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1608 datasheet, page 39 */\n  /* write_pulse_width_ns = */ 35,\t/* uc1608 datasheet, page 39 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 4,\t/* reused as y page offset */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_uc1608_erc24064_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_DLY(200),\n\n  U8X8_C(0x023),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n  //U8X8_C(0x027),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n\n  U8X8_C(0x0c8),            \t\t\t/* Map control, Bit 3: MY=1, Bit 2: MX=0, Bit 0: MSF =0 */\n  U8X8_C(0x0e8),            \t\t\t/* LCD bias Bits 0/1: 00=10.7 01=10.3, 10=12.0, 11=12.7 */\n  \n  U8X8_C(0x02f),            \t\t\t/* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x040),            \t\t\t/* set display start line to 0 */\n  U8X8_C(0x090),            \t\t\t/* no fixed lines */\n  U8X8_C(0x089),            \t\t\t/* RAM access control */\n  \n  U8X8_CA(0x081, 0x014),\t\t/* set contrast, ERC24064-1 default: 0x040 */\n  \n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x0b0),\t\t                /* page adr  */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1608_erc24064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1608_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_240x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_erc24064_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* experimental implementation for the uc1608 240x128, not referenced in codebuild */\n\nstatic const u8x8_display_info_t u8x8_uc1608_240x128_display_info =\n{\n  /* chip_enable_level = */ 1,\t/* uc1608 has high active CS */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1608 datasheet, page 39, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* uc1608 datasheet, page 39 */\n  /* reset_pulse_width_ms = */ 1, \t/* uc1608 datasheet, page 42 */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* uc1608 datasheet, page 41 */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1608 datasheet, page 39 */\n  /* write_pulse_width_ns = */ 35,\t/* uc1608 datasheet, page 39 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 0,\t/* reused as y page offset */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 128\n};\n\nstatic const uint8_t u8x8_d_uc1608_240x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_DLY(200),\n\n  //U8X8_C(0x023),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n  U8X8_C(0x026),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n\n  U8X8_C(0x0c8),            \t\t\t/* Map control, Bit 3: MY=1, Bit 2: MX=0, Bit 0: MSF =0 */\n  U8X8_C(0x0ea),            \t\t\t/* LCD bias Bits 0/1: 00=10.7 01=10.3, 10=12.0, 11=12.7 */\n\t\t\t\t\t\t\t/* maybe 0x0eb??? */\n  \n  U8X8_C(0x02f),            \t\t\t/* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x040),            \t\t\t/* set display start line to 0 */\n  U8X8_C(0x090),            \t\t\t/* no fixed lines */\n  U8X8_C(0x089),            \t\t\t/* RAM access control */\n  \n  U8X8_CA(0x081, 0x072),\t\t/* set contrast  */\n  \n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x0b0),\t\t                /* page adr  */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1608_240x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1608_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_240x128_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_240x128_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* experimental implementation for the uc1608 erc240x120 */\n\nstatic const u8x8_display_info_t u8x8_uc1608_erc240120_display_info =\n{\n  /* chip_enable_level = */ 1,\t/* uc1608 has high active CS */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1608 datasheet, page 39, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* uc1608 datasheet, page 39 */\n  /* reset_pulse_width_ms = */ 1, \t/* uc1608 datasheet, page 42 */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* uc1608 datasheet, page 41 */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1608 datasheet, page 39 */\n  /* write_pulse_width_ns = */ 35,\t/* uc1608 datasheet, page 39 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 15,\n  /* default_x_offset = */ 1,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 0,\t/* reused as y page offset */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 120\n};\n\n/* http://www.buydisplay.com/download/democode/ERC240120-1_DemoCode.txt */\nstatic const uint8_t u8x8_d_uc1608_erc240120_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_DLY(200),\n\n  //U8X8_C(0x023),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n  U8X8_C(0x026),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n\n  U8X8_C(0x0c8),            \t\t\t/* Map control, Bit 3: MY=1, Bit 2: MX=0, Bit 0: MSF =0 */\n  U8X8_C(0x0ea),            \t\t\t/* LCD bias Bits 0/1: 00=10.7 01=10.3, 10=12.0, 11=12.7 */\n\t\t\t\t\t\t\t/* according to DemoCode.txt */\n  \n  U8X8_C(0x02f),            \t\t\t/* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x040),            \t\t\t/* set display start line to 0 */\n  U8X8_C(0x090),            \t\t\t/* no fixed lines */\n  U8X8_C(0x089),            \t\t\t/* RAM access control */\n  \n  //U8X8_CA(0x081, 46),\t\t\t/* set contrast, 46 according to  DemoCode.txt */\n  U8X8_CA(0x081, 80),\t\t\t/* */\n  \n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x0b0),\t\t                /* page adr  */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1608_erc240120(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1608_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_erc240120_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_erc240120_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* DEM 240064, issue 1164 */\n\n\nstatic const u8x8_display_info_t u8x8_uc1608_dem240064_display_info =\n{\n  /* chip_enable_level = */ 1,\t/* uc1608 has high active CS */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1608 datasheet, page 39, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* uc1608 datasheet, page 39 */\n  /* reset_pulse_width_ms = */ 1, \t/* uc1608 datasheet, page 42 */\n  /* post_reset_wait_ms = */ 10, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* uc1608 datasheet, page 41 */\n  /* sck_pulse_width_ns = */ 65,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1608 datasheet, page 39 */\n  /* write_pulse_width_ns = */ 35,\t/* uc1608 datasheet, page 39 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 1,\t/* reused as y page offset */\n  /* flipmode_x_offset = */ 0,\t/* reused as y page offset */\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\n/* http://www.buydisplay.com/download/democode/ERC240120-1_DemoCode.txt */\nstatic const uint8_t u8x8_d_uc1608_dem240064_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_DLY(200),\n\n  //U8X8_C(0x023),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n  U8X8_C(0x026),            \t\t\t/* Bit 0/1: Temp compenstation, Bit 2: Multiplex Rate 0=96, 1=128 */\n\n  U8X8_C(0x0c8),            \t\t\t/* Map control, Bit 3: MY=1, Bit 2: MX=0, Bit 0: MSF =0 */\n  U8X8_C(0x0ea),            \t\t\t/* LCD bias Bits 0/1: 00=10.7 01=10.3, 10=12.0, 11=12.7 */\n\t\t\t\t\t\t\t/* according to DemoCode.txt */\n  \n  U8X8_C(0x02f),            \t\t\t/* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */\n  U8X8_DLY(50),\n  \n  U8X8_C(0x07f),            \t\t\t/* set display start line*/\n  U8X8_C(0x094),            \t\t\t/* fixed lines */\n  U8X8_C(0x089),            \t\t\t/* RAM access control */\n  \n  U8X8_CA(0x081, 160),\t\t\t/* issue 1164 */\n  \n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x0b0),\t\t                /* page adr  */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1608_dem240064_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c8),            \t\t\t/* LCD Mapping */\n  U8X8_C(0x07f),            \t\t\t/* set display start line*/\n  U8X8_C(0x094),            \t\t\t/* fixed lines */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1608_dem240064_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c4),            \t\t\t/* LCD Mapping */\n  U8X8_C(0x040),            \t\t\t/* set display start line*/\n  U8X8_C(0x090),            \t\t\t/* fixed lines */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_uc1608_dem240064(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  \n  /* checking for the flip mode cmd first */\n  if ( msg == U8X8_MSG_DISPLAY_SET_FLIP_MODE )\n  {\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_dem240064_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_dem240064_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      return 1;\n  }\n  /* call the common procedure, this now leads to the effect, that the flip code is executed again */\n  /* maybe we should paste the common code here to avoid this */\n  \n  \n  if ( u8x8_d_uc1608_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1608_dem240064_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1608_dem240064_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1610.c",
    "content": "/*\n\n  u8x8_d_uc1610.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n  cad001\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_uc1610_dogxl160_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x0f1, 0x067),\t\t/* set COM end (display height-1) */\n  U8X8_C(0x0c0),            \t\t\t/* SEG & COM normal */\n  U8X8_C(0x040),            \t\t\t/* set scroll line lsb to zero */\n  U8X8_C(0x050),            \t\t\t/* set scroll line msb to zero */\n  U8X8_C(0x02b),            \t\t\t/* set panelloading */\n  U8X8_C(0x0eb),            \t\t\t/* set bias 1/2 */  \n  U8X8_CA(0x081, 0x05f),            \t/* set contrast */\n  \n  /*\n    AC0:\t0: stop at boundary, 1: increment by one\n    AC1: \t0: first column then page, 1: first page, then column increment\n    AC2:\t0: increment page adr, 1: decrement page adr.\n  */\n  U8X8_C(0x08b),            \t\t\t/* set auto increment, low bits are AC2 AC1 AC0 */\n  \n  /*\n    LC0:\t0\n    MX:\tMirror X\n    MY:\tMirror Y\n  */  \n  U8X8_C(0x0c0),            \t\t\t/* low bits are MY, MX, LC0 */\n  \n  U8X8_C(0x0f8),            \t\t\t// window mode off\n  U8X8_C(0x010),\t\t                // col high\n  U8X8_C(0x000),\t\t                // col low\n  U8X8_C(0x0b0),\t\t                // page\n  \n  U8X8_C(0x0a6),            \t\t\t/* set normal pixel mode (not inverse) */\n  U8X8_C(0x0a4),            \t\t\t/* set normal pixel mode (not all on) */\n\n  /* test code \n  U8X8_C(0x0af),\t\t                // display on \n  U8X8_C(0x0f8),            \t\t\t// window mode off\n  U8X8_CA(0x0f4, 0),\t\t\t// set window\n  U8X8_CA(0x0f5, 0),\n  U8X8_CA(0x0f6, 4),\n  U8X8_CA(0x0f7, 1),\n  U8X8_C(0x0f9),            \t\t\t// window mode on\n  U8X8_D1(0x03),\n  U8X8_D1(0x0c0),\n  U8X8_D1(0x0ff),\n  U8X8_D1(0x0ff),\n  U8X8_D1(0x0ff),\n  U8X8_D1(0x0ff),\n  U8X8_D1(0x0ff),\n  U8X8_D1(0x0ff),\n  */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1610_dogxl160_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on, UC1610 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1610_dogxl160_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off,  UC1610 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1610_dogxl160_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  /*\n    LC0:\t0\n    MX:\tMirror X\n    MY:\tMirror Y\n  */  \n  U8X8_C(0x0c0),            \t\t\t/* low bits are MY, MX, LC0 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1610_dogxl160_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  /*\n    LC0:\t0\n    MX:\tMirror X\n    MY:\tMirror Y\n  */  \n  U8X8_C(0x0c6),            \t\t\t/* low bits are MY, MX, LC0 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/* \n  UC1610 has two chip select inputs (CS0 and CS1).\n  CS0 is low active, CS1 is high active. It will depend on the display\n  module whether the display has a is low or high active chip select.\n*/\n\nstatic const u8x8_display_info_t u8x8_uc1610_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 15,\n  /* pre_chip_disable_wait_ns = */ 15,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 30,\t\n  /* sck_pulse_width_ns = */ 63,\t/* half of cycle time (125ns cycle time according to datasheet) --> 8MHz clock */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 20,\t\t\n  /* tile_hight = */ 13,\t\t/* height of 13*8=104 pixel */\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 104\n};\n\n\n/*\n  RAM Organization:\n  D0  Pix0\n  D1\n  D2  Pix1\n  D3\n  D4  Pix2\n  D5\n  D6  Pix3\n  D7    \n  D0  Pix4\n  D1\n  D2  Pix5\n  D3\n  D4  Pix6\n  D5\n  D6  Pix7\n  D7    \n\n\n*/\nstatic uint8_t *u8x8_convert_tile_for_uc1610(uint8_t *t)\n{\n  uint8_t i;\n  uint16_t r;\n  static uint8_t buf[16];\n  uint8_t *pbuf = buf;\n\n  for( i = 0; i < 8; i++ )\n  {\n    r = u8x8_upscale_byte(*t++);\n    *pbuf++ = r & 255;\n    r >>= 8;\n    *pbuf++ = r;\n  }\n  return buf;\n}\n\nuint8_t u8x8_d_uc1610_ea_dogxl160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c, page;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1610_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1610_dogxl160_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1610_dogxl160_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1610_dogxl160_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1610_dogxl160_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1610_dogxl160_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1610 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n    \n      page = (((u8x8_tile_t *)arg_ptr)->y_pos);\n      page *= 2;\n\n      u8x8_cad_SendCmd(u8x8, 0x0f8 );\t/* window disable */\n      \n      //u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      //u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      //u8x8_cad_SendCmd(u8x8, 0x0b0 | page);\n\n      u8x8_cad_SendCmd(u8x8, 0x0f4 );\t/* window start column */\n      u8x8_cad_SendArg(u8x8, x);\n      u8x8_cad_SendCmd(u8x8, 0x0f5 );\t/* window start page */\n      u8x8_cad_SendArg(u8x8, page);\n      u8x8_cad_SendCmd(u8x8, 0x0f6 );\t/* window end column */\n      u8x8_cad_SendArg(u8x8, 159);\t\t/* end of display */\n      u8x8_cad_SendCmd(u8x8, 0x0f7 );\t/* window end page */\n      u8x8_cad_SendArg(u8x8, page+1);\n      u8x8_cad_SendCmd(u8x8, 0x0f9 );\t/* window enable */\n    \n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 16, u8x8_convert_tile_for_uc1610(ptr));\n\t  ptr += 8;\n\t  x += 8;\n\t  c--;\n\t} while( c > 0 );\n\t\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n\n    \n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1611.c",
    "content": "/*\n\n  u8x8_d_uc1611.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  6 Nov 2016: Not yet finished\n  \n  There are two controller:\n  UC1611s\t\t160x256\n  UC1611\t\t\t160x240\n  \n  Differences:\n  UC1611\t\t0xa8 cmd: enables 80 display rows\n  UC1611s\t0xa8 cmd: controlls graylevels\n  \n  UC1611\t\t0xc0 cmd: single byte command for LCD mapping control\n  UC1611s\t0xc0 cmd: double byte command for LCD mapping control\n  \n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_uc1611s_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a9),\t\t                /* display on, UC1611s */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611s_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a8),\t\t                /* display off, enter sleep mode, UC1611s */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611s_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0c0, 0x004),            \t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611s_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0c0, 0x002),            \t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1611_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n   \n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n    \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      u8x8_cad_SendCmd(u8x8, 0x060 | (y&15));\n      u8x8_cad_SendCmd(u8x8, 0x070 | (y>>4));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1611 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* EA DOGM240 */\n\n\n/*\n  UC1611 has two chip select inputs (CS0 and CS1).\n  CS0 is low active, CS1 is high active. It will depend on the display\n  module whether the display has a is low or high active chip select.\n*/\n\nstatic const u8x8_display_info_t u8x8_uc1611_240x64_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 10, \t/* uc1611 datasheet, page 67 */\n  /* sda_setup_time_ns = */ 10,\t\t/* uc1611 datasheet, page 64, actually 0 */\n  /* sck_pulse_width_ns = */ 60,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1611 datasheet, page 60 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1611 datasheet, page 60 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 64\n};\n\nstatic const uint8_t u8x8_d_uc1611_ea_dogm240_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_CA(0x0f1, 63),\t\t\t/* set COM end */\n  U8X8_CA(0x0f2, 0x000),\t\t/* display line start */\n  U8X8_CA(0x0f3, 63),\t\t\t/* display line end */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */\n  U8X8_CA(0x081, 0x0a4),\t\t/* set contrast, EA default: 0x0b7 */\n  \n  //U8X8_C(0x0a9),            \t\t\t/* display enable */\n\n  U8X8_C(0x0d1),            \t\t\t/* display pattern */  \n  U8X8_C(0x089),            \t\t\t/* auto increment */\n  U8X8_CA(0x0c0, 0x004),            \t/* LCD Mapping */\n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x060),\t\t                /* page adr low */\n  U8X8_C(0x070),\t\t                /* page adr high */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* UC1611s 240x64 display */\nuint8_t u8x8_d_uc1611_ea_dogm240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1611_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_240x64_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_ea_dogm240_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n\tif ( arg_int == 0 )\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave0_seq);\n\telse\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave1_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* EA DOGXL240 */\n\nstatic const uint8_t u8x8_d_uc1611_ea_dogxl240_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_CA(0x0f1, 0x07f),\t\t\t/* set COM end */\n  U8X8_CA(0x0f2, 0x000),\t\t/* display line start */\n  U8X8_CA(0x0f3, 127),\t\t/* display line end */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */\n  U8X8_CA(0x081, 0x08f),\t\t/* set contrast */\n  \n  //U8X8_C(0x0a9),            \t\t\t/* display enable */\n\n  U8X8_C(0x0d1),            \t\t\t/* display pattern */  \n  U8X8_C(0x089),            \t\t\t/* auto increment */\n  U8X8_CA(0x0c0, 0x004),            \t/* LCD Mapping */\n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x060),\t\t                /* page adr low */\n  U8X8_C(0x070),\t\t                /* page adr high */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_uc1611_240x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 10, \t/* uc1611 datasheet, page 67 */\n  /* sda_setup_time_ns = */ 10,\t\t/* uc1611 datasheet, page 64, actually 0 */\n  /* sck_pulse_width_ns = */ 60,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1611 datasheet, page 60 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1611 datasheet, page 60 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 128\n};\n\n/* UC1611s 240x128 display */\nuint8_t u8x8_d_uc1611_ea_dogxl240(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1611_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_240x128_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_ea_dogxl240_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n\tif ( arg_int == 0 )\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave0_seq);\n\telse\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave1_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n/*================================================*/\n/* EMERGING DISPLAY, EW50850FLWP 240x160 */\n/* active high CS (CS1), UC1611 display  */\n\nstatic const uint8_t u8x8_d_uc1611_ew50850_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_CA(0x0f1, 159),\t\t\t/* set COM end */\n  U8X8_CA(0x0f2, 0),\t\t\t/* display line start */\n  U8X8_CA(0x0f3, 159),\t\t\t/* display line end */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */\n  U8X8_CA(0x081, 75),\t\t\t/* set contrast */\n  \n  //U8X8_C(0x0a9),            \t\t\t/* display enable */\n\n  U8X8_C(0x0d2),            \t\t\t/* gray level mode: 16 gray shades */  \n  U8X8_C(0x089),            \t\t\t/* auto increment */\n  U8X8_C(0x0c0),            \t\t\t/* LCD Mapping Bit 0: MSF, Bit 1: MX, Bit 2: MY */\n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x060),\t\t                /* page adr low */\n  U8X8_C(0x070),\t\t                /* page adr high */\n    \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_uc1611_ew50850_display_info =\n{\n  /* chip_enable_level = */ 1,\t\t/* active high */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 10, \t/* uc1611 datasheet, page 67 */\n  /* sda_setup_time_ns = */ 10,\t\t/* uc1611 datasheet, page 64, actually 0 */\n  /* sck_pulse_width_ns = */ 60,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1611 datasheet, page 60 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1611 datasheet, page 60 */\n  /* tile_width = */ 30,\t\t/* width of 30*8=240 pixel */\n  /* tile_hight = */ 20,\t\t/* height: 160 pixel */\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 240,\n  /* pixel_height = */ 160\n};\n\nstatic const uint8_t u8x8_d_uc1611_alt_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c0),\t\t\t\t/* LCD Mapping Bit 0: MSF, Bit 1: MX, Bit 2: MY */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611_alt_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c6),\t\t\t\t/* LCD Mapping Bit 0: MSF, Bit 1: MX, Bit 2: MY */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0af),\t\t                /* display on, UC1611 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1611_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a8),\t\t                /* display off, enter sleep mode, UC1611 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n/* EW50850, 240x160 */\nuint8_t u8x8_d_uc1611_ew50850(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c, i, v, m0, m1, ai;\n  uint8_t *ptr;\n  /* msg not handled, then try here */\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n   \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y*=4;\n      m0 = 1;\n      m1 = 2;\n      for( i = 0; i < 4; i++ )\n      {\n        u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n        u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n    \n\tu8x8_cad_SendCmd(u8x8, 0x060 | (y&15));\n\tu8x8_cad_SendCmd(u8x8, 0x070 | (y>>4));\n      \n\tai = arg_int;\n\tdo\n\t{\n\t  c = ((u8x8_tile_t *)arg_ptr)->cnt;\n\t  c *= 8;\n\t  ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\t  while( c > 0 )\n\t  {\n\t    v = 0;\n\t    if ( *ptr & m0 )\n\t      v|= 0x0f;\n\t    if ( *ptr & m1 )\n\t      v|= 0xf0;\n\t    u8x8_cad_SendData(u8x8, 1, &v);\t/* note: SendData can not handle more than 255 bytes */\n\t    c--;\n            ptr++;\n\t  }\n\t  ai--;\n\t} while( ai > 0 );\n\t\n\tm0 <<= 2;\n\tm1 <<= 2;\n\ty++;\n      }\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_ew50850_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_ew50850_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_alt_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_alt_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n  case U8X8_MSG_DISPLAY_SET_CONTRAST:\n    u8x8_cad_StartTransfer(u8x8);\n    u8x8_cad_SendCmd(u8x8, 0x081 );\n    u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1611 has range from 0 to 255 */\n    u8x8_cad_EndTransfer(u8x8);\n    break;\n#endif\n    default:\n      return 0;\t\t/* msg unknown */\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* CG160160D, http://www.cloverdisplay.com/pdf/CG160160D.pdf  */\n\n/*\n  UC1611 has two chip select inputs (CS0 and CS1).\n  CS0 is low active, CS1 is high active. It will depend on the display\n  module whether the display has a is low or high active chip select.\n\n  Connect CS1 to 3.3V and CS0 to GPIO\n*/\n\nstatic const u8x8_display_info_t u8x8_uc1611_cg160160_display_info =\n{\n  /* chip_enable_level = */ 0,\t\t\t/* use CS0 of the UC1611 */\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 10, \t/* uc1611 datasheet, page 67 */\n  /* sda_setup_time_ns = */ 10,\t\t/* uc1611 datasheet, page 64, actually 0 */\n  /* sck_pulse_width_ns = */ 60,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1611 datasheet, page 60 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1611 datasheet, page 60 */\n  /* tile_width = */ 20,\t\t/* width of 20*8=160 pixel */\n  /* tile_hight = */ 20,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 160\n};\n\n/*\nSystem Reset: E2H \t--> DONE\nSet Temp. Compensation: 24H --> DONE\nSet up LCD format specific parameters MX,MY,etc(double-byte command): C0H,04H  --> FLIP0\nSet line rate: A3H --> DONE\nSet Pump Control (internal Vlcd): 2FH --> DONE\nSet Isolation Clock Front (3 bytes command): 82H, 13H, 01H  --> DONE\nSet Isolation Clock Back (3 bytes command): 82H, 14H, 00H  --> DONE\nSet LCD Bias Ratio: EAH \nLCD Specific Operation Voltage Setting (double-byte command): 81H, 90H --> DONE\nSet RAM Address Control: 80H --> DOES NOT MAKE SENSE\nSet Page Addr. MSB: 72H \t\t--> DONE\nSet Page Addr. LSB : 60H \t\t--> DONE\nSet Column Addr. LSB: 00H \t\t--> DONE\nSet Column Addr.MSB: 10H \t\t--> DONE\nWindow Program Enable : F8H \t\t--> NOT REQURED\nWindow Starting Column (double-byte command): F4H , 00H --> NOT REQURED\nWindow Ending Column (double-byte command): F6H, 9FH --> NOT REQURED\nSet one bit for one pixel: D1H \t\t--> DONE\nSet Display Enable: A9H \n*/\n\nstatic const uint8_t u8x8_d_uc1611_cg160160_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0e2),\t\t\t\t/* system reset */\n  U8X8_DLY(2),\n  U8X8_C(0x024),            \t\t\t/* Temp. Compensation to 0 = -0.05%/ Grad C */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */  \n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_CAA(0x082, 0x013, 0x001), /* Isolation front clock, \"1\" is the default value */\n  U8X8_CAA(0x082, 0x014, 0x000), /* Isolation back clock, \"0\" is the default value */\n  U8X8_C(0x0ea),            \t\t\t/* bias ratio, default: 0x0ea */\n  U8X8_CA(0x081, 0x090),\t\t/* set contrast, CG160160: 0x090 */\n  \n  //U8X8_CA(0x0f1, 159),\t\t\t/* set COM end */\n  //U8X8_CA(0x0f2, 0),\t\t\t/* display line start */\n  //U8X8_CA(0x0f3, 159),\t\t\t/* display line end */\n  \n  //U8X8_C(0x0a9),            \t\t\t/* display enable */\n\n  U8X8_C(0x089),            \t\t\t/* RAM Address Control: auto increment */\n  U8X8_C(0x0d1),            \t\t\t/* display pattern */  \n  U8X8_CA(0x0c0, 0x004),            \t/* LCD Mapping */\n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x060),\t\t                /* page adr low */\n  U8X8_C(0x070),\t\t                /* page adr high */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n/* cg160160 display */\nuint8_t u8x8_d_uc1611_cg160160(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1611_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_cg160160_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_cg160160_init_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n\tif ( arg_int == 0 )\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave0_seq);\n\telse\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave1_seq);\n\tbreak;\n      case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n\tif ( arg_int == 0 )\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip0_seq);\n\t  u8x8->x_offset = u8x8->display_info->default_x_offset;\n\t}\n\telse\n\t{\n\t  u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip1_seq);\n\t  u8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n\t}\t\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* CI064-4073-06 (Intelligent Display Solutions), IDS4073*/\n/* https://docs.rs-online.com/7e6e/0900766b8156b018.pdf */\n\nstatic const uint8_t u8x8_d_uc1611_ids4073_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_CA(0x0f1, 0x07f),\t\t\t/* set COM end */\n  U8X8_CA(0x0f2, 0x000),\t\t/* display line start */\n  U8X8_CA(0x0f3, 127),\t\t/* display line end */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */\n  U8X8_CA(0x081, 0x08f),\t\t/* set contrast */\n  \n  //U8X8_C(0x0a9),            \t\t\t/* display enable */\n\n  U8X8_C(0x0d1),            \t\t\t/* display pattern */  \n  U8X8_C(0x089),            \t\t\t/* auto increment */\n  U8X8_CA(0x0c0, 0x004),            \t/* LCD Mapping */\n  U8X8_C(0x000),\t\t                /* column low nibble */\n  U8X8_C(0x010),\t\t                /* column high nibble */  \n  U8X8_C(0x060),\t\t                /* page adr low */\n  U8X8_C(0x070),\t\t                /* page adr high */\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_uc1611_256x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1611 datasheet, page 60, actually 0 */\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 10, \t/* uc1611 datasheet, page 67 */\n  /* sda_setup_time_ns = */ 10,\t\t/* uc1611 datasheet, page 64, actually 0 */\n  /* sck_pulse_width_ns = */ 60,\t/* half of cycle time  */\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1611 datasheet, page 60 */\n  /* write_pulse_width_ns = */ 80,\t/* uc1611 datasheet, page 60 */\n  /* tile_width = */ 32,\t\t/* width of 32*8=256 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 256,\n  /* pixel_height = */ 128\n};\n\n/* UC1611s 256x128 display */\nuint8_t u8x8_d_uc1611_ids4073(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n   \n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n    \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      u8x8_cad_SendCmd(u8x8, 0x060 | (y&15));\n      u8x8_cad_SendCmd(u8x8, 0x070 | (y>>4));\n    \n      do\n      {\n        c = ((u8x8_tile_t *)arg_ptr)->cnt;\n        ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n        /* SendData can not handle more than 255 bytes */\n        if ( c > 31 )\n        {\n          u8x8_cad_SendData(u8x8, 248, ptr); \t/* 31*8=248 */\n          ptr+=248;\n          c -= 31;\n        }\n        \n        u8x8_cad_SendData(u8x8, c*8, ptr); \t\n        arg_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1611 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1611_256x128_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1611_ids4073_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1611s_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n    default:\n      return 0;\t\t/* msg unknown */\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1617.c",
    "content": "/*\n\n  u8x8_d_uc1617.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2017, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_uc1617_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  //U8X8_C(0x0ad),            \t\t\t/* display enable BW Mode*/\n  U8X8_C(0x0af),            \t\t\t/* display enable GS Mode*/\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1617_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ac),\t\t                /* display off, enter sleep mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1617_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c0),            \t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1617_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c6),            \t/* LCD Mapping */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\n//static uint8_t u8x8_upscale_4bit(uint8_t x) U8X8_NOINLINE;\nstatic uint8_t u8x8_upscale_4bit(uint8_t x) \n{\n\tuint8_t y = x;\n\ty |= (y << 4);\t\t// x = (x | (x << S[2])) & B[2];\n\ty &= 0x0f;\n\ty |= (y << 2);\t\t// x = (x | (x << S[1])) & B[1];\n\ty &= 0x33;\n\ty |= (y << 1);\t\t// x = (x | (x << S[0])) & B[0];\n\ty &= 0x55;\n  \n\ty |= (y << 1);\t\t// z = x | (y << 1);\n\treturn y;\n}\n\nstatic uint8_t u8x8_uc1617_tile_half_buffer[8];\n\nstatic uint8_t *u8x8_convert_tile_for_uc1617_lower4bit(uint8_t *t)\n{\n  uint8_t i;\n  uint8_t *pbuf = u8x8_uc1617_tile_half_buffer;\n\n  for( i = 0; i < 8; i++ )\n  {\n    *pbuf++ = u8x8_upscale_4bit(*t++);\n  }\n  return u8x8_uc1617_tile_half_buffer;\n}\n\nstatic uint8_t *u8x8_convert_tile_for_uc1617_upper4bit(uint8_t *t)\n{\n  uint8_t i;\n  uint8_t *pbuf = u8x8_uc1617_tile_half_buffer;\n\n  for( i = 0; i < 8; i++ )\n  {\n    *pbuf++ = u8x8_upscale_4bit((*t++)>>4);\n  }\n  return u8x8_uc1617_tile_half_buffer;\n}\n\n#ifdef NOT_USED\nstatic uint8_t *u8x8_convert_tile_for_uc1617(uint8_t *t)\n{\n  uint8_t i;\n  uint16_t r;\n  static uint8_t buf[16];\n  uint8_t *pbuf = buf;\n\n  for( i = 0; i < 8; i++ )\n  {\n    r = u8x8_upscale_byte(*t++);\n    *pbuf = r & 255;\n    r >>= 8;\n    pbuf+=8;\n    *pbuf = r;\n    pbuf-=7;\n  }\n  return buf;\n}\n#endif\n\n\nuint8_t u8x8_d_uc1617_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c, a;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n\n\n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y*=2;\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x060 | (x&15));\n      u8x8_cad_SendCmd(u8x8, 0x070 | (x>>4)); \n      u8x8_cad_SendCmd(u8x8, 0x00 | (y));\n\n#ifdef NOT_REQUIRED\n      u8x8_cad_SendCmd(u8x8, 0xf8 );\t/* disable window */\n      u8x8_cad_SendCmd(u8x8, 0xf4 );\t/* page start */\n      u8x8_cad_SendCmd(u8x8, y );\t\n      u8x8_cad_SendCmd(u8x8, 0xf5 );\t/* x start */\n      u8x8_cad_SendCmd(u8x8, x );\t\n      u8x8_cad_SendCmd(u8x8, 0xf6 );\t/* page end */\n      u8x8_cad_SendCmd(u8x8, y );\t\n      u8x8_cad_SendCmd(u8x8, 0xf7 );\t/* x end */\n      u8x8_cad_SendCmd(u8x8, 127 );\t\n      u8x8_cad_SendCmd(u8x8, 0xf9 );\t/* enable window  */\n#endif\n\n      a = arg_int;\n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, u8x8_convert_tile_for_uc1617_lower4bit(ptr));\n\t  ptr += 8;\n\t  x += 8;\n\t  c--;\n\t} while( c > 0 );\t\n\ta--;\n      } while( a > 0 );\n\n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x060 | (x&15));\n      u8x8_cad_SendCmd(u8x8, 0x070 | (x>>4));    \n      u8x8_cad_SendCmd(u8x8, 0x00 | (y+1));\n      a = arg_int;\n      do\n      {\n\tc = ((u8x8_tile_t *)arg_ptr)->cnt;\n\tptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n\tdo\n\t{\n\t  u8x8_cad_SendData(u8x8, 8, u8x8_convert_tile_for_uc1617_upper4bit(ptr));\n\t  ptr += 8;\n\t  x += 8;\n\t  c--;\n\t} while( c > 0 );\t\n\ta--;\n      } while( a > 0 );\n          \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1617_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1617_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1617_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1617_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1617 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n/*================================================*/\n/* JLX128128 */\n\nstatic const uint8_t u8x8_d_uc1617_jlx128128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* reset */\n  U8X8_DLY(10),\n  \n  //U8X8_D1(0x0ff),\n  U8X8_C(0x027),            \t\t\t/* temperature compensation */\n  U8X8_C(0x02b),            \t\t\t/* panel loading: 13-18nF */\n  \n  U8X8_C(0x02f),            \t\t\t/* internal pump control */\n  U8X8_C(0x0eb),            \t\t\t/* bias=1/11 */\n  U8X8_CA(0x081, 0x028),\t\t/* set contrast */\n  //U8X8_C(0x0a9),            \t\t\t/* used in display datasheet, but cmd not described in controller datasheet */\n  \n  U8X8_CA(0x0f1, 0x07f),\t\t\t/* set COM end */\n  U8X8_CA(0x0f2, 0x000),\t\t/* display line start */\n  U8X8_CA(0x0f3, 127),\t\t\t/* display line end */\n  U8X8_C(0x0a3),            \t\t\t/* line rate */\n  \n  U8X8_C(0x0d3),            \t\t\t/* */\n  U8X8_C(0x0d7),            \t\t\t/* */\n  \n\n  //U8X8_C(0x0a5),            \t\t\t/* all pixel on */\n\n  //U8X8_C(0x0d1),            \t\t\t/* display pattern */  \n  U8X8_C(0x08b),            \t\t\t/* auto increment */\n  U8X8_C(0x0c0),            \t/* LCD Mapping */\n\n  //U8X8_C(0x0ad),            \t\t\t/* display enable BW Mode*/\n  //U8X8_C(0x0af),            \t\t\t/* display enable GS Mode*/\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const u8x8_display_info_t u8x8_uc1617_128x128_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* uc1617 datasheet, page 54, actually 5 */\n  /* pre_chip_disable_wait_ns = */ 10,\t/* uc1617 datasheet, page 54, actually 5 */\n  /* reset_pulse_width_ms = */ 10, \n  /* post_reset_wait_ms = */ 20, \t/* uc1617 datasheet, page 56 */\n  /* sda_setup_time_ns = */ 24,\t\t/* uc1617 datasheet, page 54 */\n  /* sck_pulse_width_ns = */ 45,\t/* half of cycle time  uc1617 datasheet, page 54*/\n  /* sck_clock_hz = */ 8000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/* uc1617 datasheet, page 52 */\n  /* write_pulse_width_ns = */ 65,\t/* uc1617 datasheet, page 52 */\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 128\n};\n\nuint8_t u8x8_d_uc1617_jlx128128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1617_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1617_128x128_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1617_jlx128128_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1638.c",
    "content": "/*\n\n  u8x8_d_uc1638.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\n\nstatic const uint8_t u8x8_d_uc1638_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0c9, 0x0ad),\t\t                /* display on */   /* UC1638 B/W mode */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1638_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_CA(0x0c9, 0x0ac),\t\t                /* display off */   /* UC1638 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1638_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c4),            \t/* LCD Mapping */    /* UC1638*/\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1638_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0c2),            \t/* LCD Mapping */    /* UC1638*/\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nuint8_t u8x8_d_uc1638_common(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, y, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n\n      u8x8_cad_SendCmd(u8x8, 0x004);  /* UC1638 */\n      u8x8_cad_SendArg(u8x8, x);\n    \n      y = ((u8x8_tile_t *)arg_ptr)->y_pos;\n      y += u8x8->x_offset;\n      y *= 2;\t\t/* for B/W mode, use only every second page */\n\n      u8x8_cad_SendCmd(u8x8, 0x060 | (y&15));  /* UC1638 */\n      u8x8_cad_SendCmd(u8x8, 0x070 | (y>>4));  /* UC1638 */\n    \n    \n      u8x8_cad_SendCmd(u8x8, 0x001); /* UC1638 */\n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    /*\thandled in the calling procedure \n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1638_128x64_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    */\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1638_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1638_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1638_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1638_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int  );\t/* uc1638 has range from 0 to 255 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n/*================================================*/\n/* uc1638 160x128 */\n\n/* values taken from uc1608 */\nstatic const u8x8_display_info_t u8x8_uc1638_160x128_display_info =\n{\n  /* chip_enable_level = */ 1,\t/* uc1638 has high active CS */\n  /* chip_disable_level = */ 0,\n  \n  /* post_chip_enable_wait_ns = */ 10,\t/* */\n  /* pre_chip_disable_wait_ns = */ 20,\t/* */\n  /* reset_pulse_width_ms = */ 5, \t/* */\n  /* post_reset_wait_ms = */ 150, \t\n  /* sda_setup_time_ns = */ 30,\t\t/* */\n  /* sck_pulse_width_ns = */ 65,\t/* */\n  /* sck_clock_hz = */ 1000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 3,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\t/*  */\n  /* write_pulse_width_ns = */ 35,\t/*  */\n  /* tile_width = */ 20,\t\t/* width of 20*8=160 pixel */\n  /* tile_hight = */ 16,\n  /* default_x_offset = */ 0,\t/*  */\n  /* flipmode_x_offset = */ 0,\t/* */\n  /* pixel_width = */ 160,\n  /* pixel_height = */ 128\n};\n\nstatic const uint8_t u8x8_d_uc1638_160x128_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n\n  U8X8_CA(0x0e1, 0x0e2),\t\t/* software reset */    /* UC1638*/\n  U8X8_DLY(5),\t\t\t\t\t/* 5 ms */\t\n\n  U8X8_C(0x024),            \t\t/*\t set temp comp*/\n  U8X8_C(0x0c0),            \t\t/*\tmirror y and mirror x */  /* WAS: c2 */\n  U8X8_C(0x0a2),            \t\t/*\tline rate */\n  U8X8_C(0x0d6),            \t\t/*\tgray scale 2 */\n  U8X8_C(0x0eb),            \t\t/*\t set bias*/\n  U8X8_C(0x095),            \t\t/*\t set 1 bit per pixel, pattern 0*/\n  U8X8_C(0x089),            \t\t/*\t set auto increment, low bits are AC2 AC1 AC0 */  /* WAS 89 */\n\n\n  U8X8_CA(0x081, 0x0a0),\t\t/* set contrast */    /* UC1638*/\n  \n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nuint8_t u8x8_d_uc1638_160x128(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  /* call common procedure first and handle messages there */\n  if ( u8x8_d_uc1638_common(u8x8, msg, arg_int, arg_ptr) == 0 )\n  {\n    /* msg not handled, then try here */\n    switch(msg)\n    {\n      case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n\tu8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1638_160x128_display_info);\n\tbreak;\n      case U8X8_MSG_DISPLAY_INIT:\n\tu8x8_d_helper_display_init(u8x8);\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1638_160x128_init_seq);\n\tbreak;\n      default:\n\treturn 0;\t\t/* msg unknown */\n    }\n  }\n  return 1;\n}\n\n\n/*================================================*/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1701_dogs102.c",
    "content": "/*\n\n  u8x8_d_uc1701_dogs102.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_uc1701_dogs102_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a1),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c0),\t\t                /* common output mode */\n  // Flipmode\n  //U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  //U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  U8X8_C(0x027),\t\t                /* regulator, booster and follower */\n  U8X8_CA(0x081, 0x00e),\t\t/* set contrast, contrast value, EA default: 0x010, previous value for S102: 0x0e */\n  U8X8_C(0x0fa),\t\t                /* Set Temp compensation */ \n  U8X8_C(0x090),\t\t                /* 0.11 deg/c WP Off WC Off*/\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_dogs102_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a4),\t\t                /* all pixel off, issue 142 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_dogs102_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_dogs102_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_dogs102_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_uc1701_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 13,\t\t/* width of 13*8=104 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 30,\n  /* pixel_width = */ 102,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_uc1701_ea_dogs102(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1701_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_dogs102_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* uc1701 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the uc1701 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_d_uc1701_mini12864.c",
    "content": "/*\n\n  u8x8_d_uc1701_mini12864.c (dealextreme, displays from ebay MP3 players)\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n#include \"u8x8.h\"\n\n\n\n\nstatic const uint8_t u8x8_d_uc1701_mini12864_init_seq[] = {\n    \n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  \n  U8X8_C(0x0e2),            \t\t\t/* soft reset */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x040),\t\t                /* set display start line to 0 */\n  \n  U8X8_C(0x0a0),\t\t                /* ADC set to reverse */\n  U8X8_C(0x0c8),\t\t                /* common output mode */\n  \n  U8X8_C(0x0a6),\t\t                /* display normal, bit val 0: LCD pixel off. */\n  U8X8_C(0x0a2),\t\t                /* LCD bias 1/9 */\n  U8X8_C(0x02f),\t\t                /* all power  control circuits on */\n  U8X8_C(0x0f8),\t\t/* set booster ratio to */\n  U8X8_C(0x000),\t\t/* 4x */\n  U8X8_C(0x023),\t\t/* set V0 voltage resistor ratio to large */\n  U8X8_C(0x081),\t\t/* set contrast */\n  U8X8_C(0x027),\t\t/* contrast value */\n  U8X8_C(0x0ac),\t\t/* indicator */\n  //  0x000,\t\t/* disable */\n  \n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  \n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_mini12864_powersave0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a4),\t\t                /* all pixel off, issue 142 */\n  U8X8_C(0x0af),\t\t                /* display on */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_mini12864_powersave1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0ae),\t\t                /* display off */\n  U8X8_C(0x0a5),\t\t                /* enter powersafe: all pixel on, issue 142 */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_mini12864_flip0_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a0),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c8),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\nstatic const uint8_t u8x8_d_uc1701_mini12864_flip1_seq[] = {\n  U8X8_START_TRANSFER(),             \t/* enable chip, delay is part of the transfer start */\n  U8X8_C(0x0a1),\t\t\t\t/* segment remap a0/a1*/\n  U8X8_C(0x0c0),\t\t\t\t/* c0: scan dir normal, c8: reverse */\n  U8X8_END_TRANSFER(),             \t/* disable chip */\n  U8X8_END()             \t\t\t/* end of sequence */\n};\n\n\nstatic const u8x8_display_info_t u8x8_uc1701_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 5,\n  /* pre_chip_disable_wait_ns = */ 5,\n  /* reset_pulse_width_ms = */ 1, \n  /* post_reset_wait_ms = */ 6, \n  /* sda_setup_time_ns = */ 12,\t\t\n  /* sck_pulse_width_ns = */ 75,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 30,\n  /* write_pulse_width_ns = */ 40,\n  /* tile_width = */ 16,\t\t/* width of 16*8=128 pixel */\n  /* tile_hight = */ 8,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 4,\n  /* pixel_width = */ 128,\n  /* pixel_height = */ 64\n};\n\nuint8_t u8x8_d_uc1701_mini12864(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr)\n{\n  uint8_t x, c;\n  uint8_t *ptr;\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_uc1701_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      u8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_mini12864_init_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_POWER_SAVE:\n      if ( arg_int == 0 )\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_mini12864_powersave0_seq);\n      else\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_mini12864_powersave1_seq);\n      break;\n    case U8X8_MSG_DISPLAY_SET_FLIP_MODE:\n      if ( arg_int == 0 )\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_mini12864_flip0_seq);\n\tu8x8->x_offset = u8x8->display_info->default_x_offset;\n      }\n      else\n      {\n\tu8x8_cad_SendSequence(u8x8, u8x8_d_uc1701_mini12864_flip1_seq);\n\tu8x8->x_offset = u8x8->display_info->flipmode_x_offset;\n      }\t\n      break;\n#ifdef U8X8_WITH_SET_CONTRAST\n    case U8X8_MSG_DISPLAY_SET_CONTRAST:\n      u8x8_cad_StartTransfer(u8x8);\n      u8x8_cad_SendCmd(u8x8, 0x081 );\n      u8x8_cad_SendArg(u8x8, arg_int >> 2 );\t/* uc1701 has range from 0 to 63 */\n      u8x8_cad_EndTransfer(u8x8);\n      break;\n#endif\n    case U8X8_MSG_DISPLAY_DRAW_TILE:\n      u8x8_cad_StartTransfer(u8x8);\n    \n      x = ((u8x8_tile_t *)arg_ptr)->x_pos;\n      x *= 8;\n      x += u8x8->x_offset;\n      u8x8_cad_SendCmd(u8x8, 0x010 | (x>>4) );\n      u8x8_cad_SendCmd(u8x8, 0x000 | ((x&15)));\n      u8x8_cad_SendCmd(u8x8, 0x0b0 | (((u8x8_tile_t *)arg_ptr)->y_pos));\n    \n      c = ((u8x8_tile_t *)arg_ptr)->cnt;\n      c *= 8;\n      ptr = ((u8x8_tile_t *)arg_ptr)->tile_ptr;\n      /* \n\tThe following if condition checks the hardware limits of the uc1701 \n\tcontroller: It is not allowed to write beyond the display limits.\n\tThis is in fact an issue within flip mode.\n    \n\tbug: this check should be inside the while loop, see u8x8_d_pcd8544_84x48.c \n      */\n      if ( c + x > 132u )\n      {\n\tc = 132u;\n\tc -= x;\n      }\n      do\n      {\n\tu8x8_cad_SendData(u8x8, c, ptr);\t/* note: SendData can not handle more than 255 bytes */\n\targ_int--;\n      } while( arg_int > 0 );\n      \n      u8x8_cad_EndTransfer(u8x8);\n      break;\n    default:\n      return 0;\n  }\n  return 1;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_debounce.c",
    "content": "/*\n\n  u8x8_debounce.c\n  \n  Key/button simple debounce algorithm (Addon for u8x8)\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8x8.h\"\n\nstatic uint8_t u8x8_read_pin_state(u8x8_t *u8x8)\n{\n  uint8_t i;\n  uint8_t pin_state;\n  \n  pin_state = 255;\t/* be compatible with the setup of the default pin setup, which is 255 */\n  for( i = 0; i < U8X8_PIN_INPUT_CNT; i++ )\n  {\n    pin_state <<= 1;\n    \n    /* the callback function should put the return value into this variable */\n    u8x8->gpio_result = 1;\n    u8x8_gpio_call(u8x8, U8X8_MSG_GPIO(i+U8X8_PIN_OUTPUT_CNT), 0);\n    pin_state |= u8x8->gpio_result & 1;\n  }\n  \n  return pin_state;\n}\n\n/*\n  return 0 to U8X8_PIN_INPUT_CNT-1 if there is a difference\n  return U8X8_PIN_INPUT_CNT if there is no difference\n*/\nstatic uint8_t u8x8_find_first_diff(uint8_t a, uint8_t b)\n{\n  uint8_t mask;\n  uint8_t i;\n  mask = 1;\n  i = U8X8_PIN_INPUT_CNT;\n  do\n  {\n    i--;\n    if ( (a & mask) != (b & mask) )\n      return i;\n    mask <<= 1;\n  } while( i > 0 );\n  return U8X8_PIN_INPUT_CNT;\n}\n\n/*\n  State A:\n    u8x8->debounce_last_pin_state == current_state \n      --> State A\n    u8x8->debounce_last_pin_state != current_state \n      --> u8x8->debounce_last_pin_state = current_state \n      --> State B + cnt\n\n  State B + cnt\n    --> state--\n\n  State B\n    u8x8->debounce_last_pin_state == current_state \n      --> keypress detected\n      --> State C\n    u8x8->debounce_last_pin_state != current_state \n      --> State A\n\n  State C\n    u8x8->debounce_last_pin_state == current_state \n      --> State C\n    u8x8->debounce_last_pin_state != current_state \n      --> State A\n\n*/\n\n#ifdef __unix__xxxxxx_THIS_IS_DISABLED\n\n#include <stdio.h>\n#include <stdlib.h>\nuint8_t u8x8_GetMenuEvent(u8x8_t *u8x8)\n{\n    int c;\n    c = getc(stdin);\n    switch(c)\n    {\n        case 'n':\n            return  U8X8_MSG_GPIO_MENU_NEXT;\n        case 'p':\n            return  U8X8_MSG_GPIO_MENU_PREV;\n        case 's':\n            return  U8X8_MSG_GPIO_MENU_SELECT;\n        case 'h':\n            return  U8X8_MSG_GPIO_MENU_HOME;\n        case 'x':\n            exit(0);\n        default:\n            puts(\"press n, p, s, h or x\");\n            break;\n    }\n    return 0;\n}\n\n\n#else  /* __unix__ */\n\n\n#define U8X8_DEBOUNCE_WAIT 2\n/* do debounce and return a GPIO msg which indicates the event */\n/* returns 0, if there is no event */\n#if defined(__GNUC__) && !defined(__CYGWIN__)\n# pragma weak  u8x8_GetMenuEvent\n#endif\nuint8_t u8x8_GetMenuEvent(u8x8_t *u8x8)\n{\n  uint8_t pin_state;\n  uint8_t result_msg = 0;\t/* invalid message, no event */\n  \n  pin_state = u8x8_read_pin_state(u8x8);\n  \n  /* States A, B, C & D are encoded in the upper 4 bit*/\n  switch(u8x8->debounce_state)\n  {\n    case 0x00:\t/* State A, default state */\n      if ( u8x8->debounce_default_pin_state != pin_state )\n      {\n\t//u8x8->debounce_last_pin_state = pin_state;\n\tu8x8->debounce_state = 0x010 + U8X8_DEBOUNCE_WAIT;\n      }\n      break;\n    case 0x10:\t/* State B */\n      //if ( u8x8->debounce_last_pin_state != pin_state )\n      if ( u8x8->debounce_default_pin_state == pin_state )\n      {\n\tu8x8->debounce_state = 0x00;\t/* back to state A */\n      }\n      else\n      {\n\t/* keypress detected */\n\tu8x8->debounce_last_pin_state = pin_state;\n\t//result_msg = U8X8_MSG_GPIO_MENU_NEXT;\n\tu8x8->debounce_state = 0x020 + U8X8_DEBOUNCE_WAIT;\t/* got to state C */\t\n      }\n      break;\n      \n    case 0x20:\t/* State C */\n      if ( u8x8->debounce_last_pin_state != pin_state )\n      {\n\tu8x8->debounce_state = 0x00;\t/* back to state A */\n      }\n      else\n      {\n\tu8x8->debounce_state = 0x030;\t/* got to state D */\t\n      }\n      break;\n      \n    case 0x30:\t/* State D */\n      /* wait until key release */\n      if ( u8x8->debounce_default_pin_state == pin_state )\n      {\n\tu8x8->debounce_state = 0x00;\t/* back to state A */\n\tresult_msg = U8X8_MSG_GPIO(u8x8_find_first_diff(u8x8->debounce_default_pin_state, u8x8->debounce_last_pin_state)+U8X8_PIN_OUTPUT_CNT);\n      }\n      else\n      {\n\t//result_msg = U8X8_MSG_GPIO_MENU_NEXT;\n\t// maybe implement autorepeat here \n      }\n      break;\n    default:\n      u8x8->debounce_state--;\t/* count down, until there is a valid state */\n      break;\n  }\n  return result_msg;\n}\n\n#endif /* __unix__ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_display.c",
    "content": "/*\n  \n  u8x8_display.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n  \n  Abstraction layer for the graphics controller.\n  Main goal is the placement of a 8x8 pixel block (tile) on the display.\n  \n*/\n\n\n#include \"u8x8.h\"\n\n\n/*==========================================*/\n/* internal library function */\n\n/*\n  this is a helper function for the U8X8_MSG_DISPLAY_SETUP_MEMORY function.\n  It can be called within the display callback function to carry out the usual standard tasks.\n  \n*/\nvoid u8x8_d_helper_display_setup_memory(u8x8_t *u8x8, const u8x8_display_info_t *display_info)\n{\n      /* 1) set display info struct */\n      u8x8->display_info = display_info;\n      u8x8->x_offset = u8x8->display_info->default_x_offset;\n}\n\n/*\n  this is a helper function for the U8X8_MSG_DISPLAY_INIT function.\n  It can be called within the display callback function to carry out the usual standard tasks.\n  \n*/\nvoid u8x8_d_helper_display_init(u8x8_t *u8x8)\n{\n      /* 2) apply port directions to the GPIO lines and apply default values for the IO lines*/\n      u8x8_gpio_Init(u8x8);\n      u8x8_cad_Init(u8x8);\n\n      /* 3) do reset */\n      u8x8_gpio_SetReset(u8x8, 1);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->reset_pulse_width_ms);\n      u8x8_gpio_SetReset(u8x8, 0);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->reset_pulse_width_ms);\n      u8x8_gpio_SetReset(u8x8, 1);\n      u8x8_gpio_Delay(u8x8, U8X8_MSG_DELAY_MILLI, u8x8->display_info->post_reset_wait_ms);\n}    \n\n/*==========================================*/\n/* official functions */\n\nuint8_t u8x8_DrawTile(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t cnt, uint8_t *tile_ptr)\n{\n  u8x8_tile_t tile;\n  tile.x_pos = x;\n  tile.y_pos = y;\n  tile.cnt = cnt;\n  tile.tile_ptr = tile_ptr;\n  return u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_DRAW_TILE, 1, (void *)&tile);\n}\n\n/* should be implemented as macro */\nvoid u8x8_SetupMemory(u8x8_t *u8x8)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SETUP_MEMORY, 0, NULL);  \n}\n\nvoid u8x8_InitDisplay(u8x8_t *u8x8)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_INIT, 0, NULL);  \n}\n\nvoid u8x8_SetPowerSave(u8x8_t *u8x8, uint8_t is_enable)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SET_POWER_SAVE, is_enable, NULL);  \n}\n\nvoid u8x8_SetFlipMode(u8x8_t *u8x8, uint8_t mode)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SET_FLIP_MODE, mode, NULL);  \n}\n\nvoid u8x8_SetContrast(u8x8_t *u8x8, uint8_t value)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_SET_CONTRAST, value, NULL);  \n}\n\nvoid u8x8_RefreshDisplay(u8x8_t *u8x8)\n{\n  u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_REFRESH, 0, NULL);  \n}\n\nvoid u8x8_ClearDisplayWithTile(u8x8_t *u8x8, const uint8_t *buf)\n{\n  u8x8_tile_t tile;\n  uint8_t h;\n\n  tile.x_pos = 0;\n  tile.cnt = 1;\n  tile.tile_ptr = (uint8_t *)buf;\t\t/* tile_ptr should be const, but isn't */\n  \n  h = u8x8->display_info->tile_height;\n  tile.y_pos = 0;\n  do\n  {\n    u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_DRAW_TILE, u8x8->display_info->tile_width, (void *)&tile);\n    tile.y_pos++;\n  } while( tile.y_pos < h );\n}\n\nvoid u8x8_ClearDisplay(u8x8_t *u8x8)\n{\n  uint8_t buf[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };\n  u8x8_ClearDisplayWithTile(u8x8, buf);\n}\n\nvoid u8x8_FillDisplay(u8x8_t *u8x8)\n{\n  uint8_t buf[8] = { 255, 255, 255, 255, 255, 255, 255, 255 };\n  u8x8_ClearDisplayWithTile(u8x8, buf);\n}\n\nvoid u8x8_ClearLine(u8x8_t *u8x8, uint8_t line)\n{\n  uint8_t buf[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };\n  u8x8_tile_t tile;\n  if ( line < u8x8->display_info->tile_height )\n  {\n    tile.x_pos = 0;\n    tile.y_pos = line;\n    tile.cnt = 1;\n    tile.tile_ptr = (uint8_t *)buf;\t\t/* tile_ptr should be const, but isn't */\n    u8x8->display_cb(u8x8, U8X8_MSG_DISPLAY_DRAW_TILE, u8x8->display_info->tile_width, (void *)&tile);\n  }  \n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_fonts.c",
    "content": "/*\n  u8x8_fonts.c\n*/\n#include \"u8x8.h\"\n\n/*\n  Fontname: -FreeType-Amstrad CPC extended-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Copyright ruboku 2008\n  Glyphs: 222/228\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_amstrad_cpc_extended_f[1796] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\34\"\n  \"\\177\\177\\24\\0\\0$*\\177\\177*\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177QIE\\177>\\0\\0@B\\177\\177@@\\0\\0r{IIof\\0\\0\\42aI\"\n  \"I\\177\\66\\0\\30\\24R\\177\\177P\\20\\0\\0'oIIy\\63\\0\\0>\\177II{\\62\\0\\0\\3\\1q\"\n  \"}\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\200\\354\"\n  \"l\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0Ac\\66\\34\\10\\0\\0\\0\\2\\3Q\"\n  \"Y\\17\\6\\0>\\177A]]_\\36\\0\\0|~\\23\\23~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0<~CA\"\n  \"Qsr\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\7\\6\\0<~CQ\\63n\\134\\0A\\177\\177\\11\\31\\77f\\0\\0&oI\"\n  \"I{\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\77\\177@@\\177\\77\\0\\0\\37\\77``\\77\\37\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0as\\36\\14\\36sa\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\2\\6\\14\\10\\0\\0 tTT<x@\\0C\\77\\177DD|\\70\\0\\0\\70|D\"\n  \"Dl(\\0\\70|DE\\77\\177@\\0\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\"\n  \"\\244\\374|\\0A\\177\\177\\10\\4|x\\0\\0\\0D}}@\\0\\0\\0`\\340\\200\\204\\374}\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0A\\177\\177@\\0\\0x|\\14\\70\\14|x\\0\\4|x\\4\\4xx\\0\\0\\70|D\"\n  \"D|\\70\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xD\\14\\10\\0\\0\\0H\\134T\"\n  \"Tt \\0\\0\\4\\77\\177Dd \\0\\0<|@@||\\0\\0\\34<``<\\34\\0<|`\\70\"\n  \"`|<\\0Dl\\70\\20\\70lD\\0\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134LD\\0\\0AAw\"\n  \">\\10\\10\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0\\10\\10>wAA\\0\\2\\3\\1\\3\\2\\1\\1\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\30\\30\\30\\30\\30\\30\\30\\30\\0\\0\\0\\37\\37\\30\\30\\30\\0\\0\\0\\370\"\n  \"\\370\\30\\30\\30\\30\\30\\30\\370\\370\\0\\0\\0\\30\\30\\30\\37\\37\\0\\0\\0\\30\\30\\30\\37\\37\\30\\30\\30\\0\\0\\0\\377\"\n  \"\\377\\30\\30\\30\\30\\30\\30\\370\\370\\30\\30\\30\\30\\30\\30\\377\\377\\0\\0\\0\\30\\30\\30\\377\\377\\30\\30\\30\\0\\10\\34>\"\n  \"\\10\\10\\10\\0\\0\\10\\14>\\14\\10\\0\\0\\0\\10\\10\\10>\\34\\10\\0\\0\\10\\30>\\30\\10\\0\\0\\0\\0\\0\\0\"\n  \"\\360\\360\\360\\360\\360\\360\\360\\360\\0\\0\\0\\0\\360\\360\\360\\360\\360\\360\\360\\360\\0\\0\\0\\0\\17\\17\\17\\17\\0\\0\\0\\0\"\n  \"\\377\\377\\377\\377\\360\\360\\360\\360\\17\\17\\17\\17\\360\\360\\360\\360\\377\\377\\377\\377\\17\\17\\17\\17\\0\\0\\0\\0\\17\\17\\17\\17\"\n  \"\\360\\360\\360\\360\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\\360\\360\\360\\360\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\377\\377\\377\\377\\377\\377\\377\\377\\17\\17\\17\\17\\377\\377\\377\\377\\377\\377\\377\\377\\300\\300\\300\\300\\300\\300\\300\\300\\374\\374\\374\\374\"\n  \"\\374\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0}}\\0\\0\\0\\70|D\\376Dl(\\0H~\\177I\"\n  \"Icb\\0\\0Z<$$<Z\\0\\0\\25W~~W\\25\\0\\0\\0\\0ww\\0\\0\\0@H~w\"\n  \"\\35\\11\\1\\0\\0\\3\\3\\0\\0\\3\\3\\0\\34\\42]UU\\42\\34\\0H]UO^P\\0\\0\\10\\34\\66*\"\n  \"\\34\\66\\42\\0\\0\\10\\10\\10\\10\\10\\30\\0\\0\\0\\20\\20\\20\\0\\0\\0\\34\\42]MU\\42\\34\\0\\0\\0\\1\\1\"\n  \"\\1\\1\\0\\0\\0\\16\\33\\21\\33\\16\\0\\0\\0HH~~HH\\0\\0\\31\\35\\25\\27\\22\\0\\0\\0\\21\\25\\25\"\n  \"\\37\\12\\0\\0\\0\\0\\4\\7\\3\\0\\0\\0\\0\\370\\370@@x\\70\\0\\2\\17\\177\\177\\1\\177\\1\\0\\0\\0\\0\\30\"\n  \"\\30\\0\\0\\0\\0\\0@@`\\0\\0\\0\\0\\0\\21\\37\\37\\20\\0\\0\\0N[Q[N\\0\\0\\42\\66\\34*\"\n  \"\\66\\34\\10\\0\\2\\37\\0\\60(| \\0\\2\\37\\0HdTH\\0\\21\\25\\25\\12\\60(| \\0\\60xM\"\n  \"Ep\\60\\0\\0x}\\25\\24|x\\0\\0x|\\24\\25}x\\0\\0x|\\25\\25|x\\0\\0x}\\25\"\n  \"\\25}x\\0\\0y}\\24\\24}y\\0\\0x~\\25\\25~x\\0x|\\22\\177\\177Ik\\0\\14\\236\\263\\341\"\n  \"\\341\\63\\22\\0D}}TTTD\\0D||UUTD\\0D|}UUUD\\0D}}T\"\n  \"UUD\\0\\0DE}|DD\\0\\0DD|}ED\\0\\0DE}}ED\\0\\0EE|\"\n  \"|EE\\0I\\177\\177Ic>\\34\\0\\0zy\\21\\42zy\\0\\70|EED|\\70\\0\\70|DD\"\n  \"E}\\70\\0\\70|EEE|\\70\\0\\70}EEE}\\70\\0\\70}EDE}\\70\\0Bf<\\30\"\n  \"<fB\\0\\134>s]g>\\35\\1\\0<}A@|<\\0\\0<|@A}<\\0\\0<}A\"\n  \"A}<\\0\\0=}@@}=\\0\\0\\14]qp\\134\\14\\0\\177\\177\\42\\42\\42\\34\\0\\0~\\177II\"\n  \"I>\\66\\0 uUT<x@\\0 tTU=x@\\0 tUU=x@\\0 uUU\"\n  \"=y@\\0 uUT=y@\\0 vUU>x@\\0 tT|\\64TX\\0\\0\\30<\\244\"\n  \"\\344$(\\0\\0\\70}UT\\134\\30\\0\\0\\70|TU]\\30\\0\\0\\70}UU]\\30\\0\\0\\71}T\"\n  \"T]\\31\\0\\0\\0I{z@\\0\\0\\0\\0Hz{A\\0\\0\\0\\0JyyB\\0\\0\\0\\2Jx\"\n  \"xB\\2\\0\\0\\65uKN}\\61\\0\\10zq\\11\\12zq\\0\\0\\60yKJx\\60\\0\\0\\60xJ\"\n  \"Ky\\60\\0\\0\\60zIIz\\60\\0\\0\\62yIJz\\61\\0\\0\\62zHHz\\62\\0\\0\\10\\10k\"\n  \"k\\10\\10\\0\\200\\260xhXx\\64\\4\\0\\70yCBxx\\0\\0\\70xBCyx\\0\\0\\70zA\"\n  \"Azx\\0\\0:z@@zz\\0\\0\\230\\270\\242\\243\\371x\\0\\0~$$$\\30\\0\\0\\0\\232\\272\\240\"\n  \"\\240\\372z\";\n/*\n  Fontname: -FreeType-Amstrad CPC extended-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Copyright ruboku 2008\n  Glyphs: 95/228\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_amstrad_cpc_extended_r[764] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_r\") = \n  \" ~\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\34\"\n  \"\\177\\177\\24\\0\\0$*\\177\\177*\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177QIE\\177>\\0\\0@B\\177\\177@@\\0\\0r{IIof\\0\\0\\42aI\"\n  \"I\\177\\66\\0\\30\\24R\\177\\177P\\20\\0\\0'oIIy\\63\\0\\0>\\177II{\\62\\0\\0\\3\\1q\"\n  \"}\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\200\\354\"\n  \"l\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0Ac\\66\\34\\10\\0\\0\\0\\2\\3Q\"\n  \"Y\\17\\6\\0>\\177A]]_\\36\\0\\0|~\\23\\23~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0<~CA\"\n  \"Qsr\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\7\\6\\0<~CQ\\63n\\134\\0A\\177\\177\\11\\31\\77f\\0\\0&oI\"\n  \"I{\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\77\\177@@\\177\\77\\0\\0\\37\\77``\\77\\37\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0as\\36\\14\\36sa\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\2\\6\\14\\10\\0\\0 tTT<x@\\0C\\77\\177DD|\\70\\0\\0\\70|D\"\n  \"Dl(\\0\\70|DE\\77\\177@\\0\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\"\n  \"\\244\\374|\\0A\\177\\177\\10\\4|x\\0\\0\\0D}}@\\0\\0\\0`\\340\\200\\204\\374}\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0A\\177\\177@\\0\\0x|\\14\\70\\14|x\\0\\4|x\\4\\4xx\\0\\0\\70|D\"\n  \"D|\\70\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xD\\14\\10\\0\\0\\0H\\134T\"\n  \"Tt \\0\\0\\4\\77\\177Dd \\0\\0<|@@||\\0\\0\\34<``<\\34\\0<|`\\70\"\n  \"`|<\\0Dl\\70\\20\\70lD\\0\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134LD\\0\\0AAw\"\n  \">\\10\\10\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0\\10\\10>wAA\\0\\2\\3\\1\\3\\2\\1\\1\";\n/*\n  Fontname: -FreeType-Amstrad CPC extended-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Copyright ruboku 2008\n  Glyphs: 18/228\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_amstrad_cpc_extended_n[220] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177QIE\\177>\\0\\0@B\\177\\177@@\\0\\0r{IIof\\0\\0\\42aI\"\n  \"I\\177\\66\\0\\30\\24R\\177\\177P\\20\\0\\0'oIIy\\63\\0\\0>\\177II{\\62\\0\\0\\3\\1q\"\n  \"}\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0ll\\0\\0\";\n/*\n  Fontname: -FreeType-Amstrad CPC extended-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Copyright ruboku 2008\n  Glyphs: 64/228\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_amstrad_cpc_extended_u[517] U8X8_FONT_SECTION(\"u8x8_font_amstrad_cpc_extended_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\34\"\n  \"\\177\\177\\24\\0\\0$*\\177\\177*\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177QIE\\177>\\0\\0@B\\177\\177@@\\0\\0r{IIof\\0\\0\\42aI\"\n  \"I\\177\\66\\0\\30\\24R\\177\\177P\\20\\0\\0'oIIy\\63\\0\\0>\\177II{\\62\\0\\0\\3\\1q\"\n  \"}\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\200\\354\"\n  \"l\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0Ac\\66\\34\\10\\0\\0\\0\\2\\3Q\"\n  \"Y\\17\\6\\0>\\177A]]_\\36\\0\\0|~\\23\\23~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0<~CA\"\n  \"Qsr\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\7\\6\\0<~CQ\\63n\\134\\0A\\177\\177\\11\\31\\77f\\0\\0&oI\"\n  \"I{\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\77\\177@@\\177\\77\\0\\0\\37\\77``\\77\\37\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0as\\36\\14\\36sa\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--7-70-75-75-C-50-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/1848\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x7_f[1796] U8X8_FONT_SECTION(\"u8x8_font_5x7_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\16\\0\\16\\0\\0\\0\\0(|(|\"\n  \"(\\0\\0\\0\\10T|T \\0\\0\\0&\\20\\10d\\0\\0\\0\\0(T(@\\0\\0\\0\\0\\0\\0\\16\\0\"\n  \"\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0\\0\\0T\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0``\\0\\0\\0\\0\\0 \\20\\10\\4\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0DbRL\\0\\0\\0\\0\\42JJ\\66\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\200l,\\0\"\n  \"\\0\\0\\0\\0\\0\\20(D\\0\\0\\0\\0((((\\0\\0\\0\\0\\0D(\\20\\0\\0\\0\\0\\0\\4R\\14\"\n  \"\\0\\0\\0\\0<BZ\\34\\0\\0\\0\\0|\\22\\22|\\0\\0\\0\\0~JJ\\64\\0\\0\\0\\0<BB$\"\n  \"\\0\\0\\0\\0~BB<\\0\\0\\0\\0~JJB\\0\\0\\0\\0~\\12\\12\\2\\0\\0\\0\\0<BRt\"\n  \"\\0\\0\\0\\0~\\10\\10~\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0 @@>\\0\\0\\0\\0~\\30$B\"\n  \"\\0\\0\\0\\0~@@@\\0\\0\\0\\0~\\14\\14~\\0\\0\\0\\0~\\14\\60~\\0\\0\\0\\0<BB<\"\n  \"\\0\\0\\0\\0~\\22\\22\\14\\0\\0\\0\\0<bB\\274\\0\\0\\0\\0~\\22\\62L\\0\\0\\0\\0$JR$\"\n  \"\\0\\0\\0\\0\\0\\2~\\2\\0\\0\\0\\0>@@>\\0\\0\\0\\0\\36``\\36\\0\\0\\0\\0~\\60\\60~\"\n  \"\\0\\0\\0\\0f\\30\\30f\\0\\0\\0\\0\\0\\16p\\16\\0\\0\\0\\0bRJF\\0\\0\\0\\0\\0~BB\"\n  \"\\0\\0\\0\\0\\4\\10\\20 \\0\\0\\0\\0\\0BB~\\0\\0\\0\\0\\0\\4\\2\\4\\0\\0\\0\\0@@@@\"\n  \"\\0\\0\\0\\0\\0\\2\\4\\0\\0\\0\\0\\0\\60H(x\\0\\0\\0\\0~HH\\60\\0\\0\\0\\0\\60HH\\0\"\n  \"\\0\\0\\0\\0\\60HH~\\0\\0\\0\\0\\60hX\\20\\0\\0\\0\\0\\20|\\22\\4\\0\\0\\0\\0P\\250\\250\\230\"\n  \"\\0\\0\\0\\0~\\10\\10p\\0\\0\\0\\0\\0Hz@\\0\\0\\0\\0\\0@\\200z\\0\\0\\0\\0~\\20(@\"\n  \"\\0\\0\\0\\0\\0B~@\\0\\0\\0\\0x\\20\\30p\\0\\0\\0\\0x\\10\\10p\\0\\0\\0\\0\\60HH\\60\"\n  \"\\0\\0\\0\\0\\370HH\\60\\0\\0\\0\\0\\60HH\\370\\0\\0\\0\\0x\\10\\10\\20\\0\\0\\0\\0PXh(\"\n  \"\\0\\0\\0\\0\\10>H@\\0\\0\\0\\0\\70@@x\\0\\0\\0\\0\\0\\70@\\70\\0\\0\\0\\0x``x\"\n  \"\\0\\0\\0\\0H\\60\\60H\\0\\0\\0\\0\\30\\240@\\70\\0\\0\\0\\0HhXH\\0\\0\\0\\0\\0\\10<B\"\n  \"\\0\\0\\0\\0\\0\\0~\\0\\0\\0\\0\\0\\0B<\\10\\0\\0\\0\\0\\4\\2\\4\\2\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0z\\0\\0\\0\\0\\0\\60H\\374H\\0\\0\\0\\0P\\70TD\"\n  \"\\0\\0\\0\\0D\\70(\\70D\\0\\0\\0\\0\\26x\\26\\0\\0\\0\\0\\0\\0l\\0\\0\\0\\0\\0\\0\\234\\252r\"\n  \"\\0\\0\\0\\0\\0\\2\\0\\2\\0\\0\\0\\0|\\222\\252\\202|\\0\\0\\0\\4\\12\\16\\0\\0\\0\\0\\0\\20(\\0\\20\"\n  \"(\\0\\0\\0\\20\\20\\20\\60\\0\\0\\0\\0\\0\\20\\20\\20\\0\\0\\0\\0|\\272\\212\\202|\\0\\0\\0\\2\\2\\2\\2\"\n  \"\\0\\0\\0\\0\\0\\4\\12\\4\\0\\0\\0\\0HH~HH\\0\\0\\0\\0\\32\\26\\0\\0\\0\\0\\0\\0\\26\\36\\0\"\n  \"\\0\\0\\0\\0\\0\\4\\2\\0\\0\\0\\0\\0\\370@@\\70\\0\\0\\0\\0\\14~\\2~\\0\\0\\0\\0\\0\\30\\30\\0\"\n  \"\\0\\0\\0\\0\\0\\200@\\0\\0\\0\\0\\0\\0\\24\\36\\20\\0\\0\\0\\0\\4\\12\\4\\0\\0\\0\\0\\0(\\20\\0(\"\n  \"\\20\\0\\0\\0\\36@`\\360\\0\\0\\0\\0\\36\\0\\320\\260\\0\\0\\0\\0\\26^`\\360\\0\\0\\0\\0\\0\\60J \"\n  \"\\0\\0\\0\\0|\\22\\22|\\0\\0\\0\\0|\\22\\22|\\0\\0\\0\\0|\\22\\22|\\0\\0\\0\\0|\\22\\22|\"\n  \"\\0\\0\\0\\0z\\24\\24z\\0\\0\\0\\0x\\26\\26x\\0\\0\\0\\0|\\22~J\\0\\0\\0\\0<\\302B$\"\n  \"\\0\\0\\0\\0~JJB\\0\\0\\0\\0~JJB\\0\\0\\0\\0~JJB\\0\\0\\0\\0~JJB\"\n  \"\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0\\0B~B\"\n  \"\\0\\0\\0\\0J~B<\\0\\0\\0\\0~\\10\\62~\\0\\0\\0\\0<BB<\\0\\0\\0\\0<BB<\"\n  \"\\0\\0\\0\\0<BB<\\0\\0\\0\\0<BB<\\0\\0\\0\\0:DD:\\0\\0\\0\\0H\\60\\60H\"\n  \"\\0\\0\\0\\0|rN>\\0\\0\\0\\0>@@>\\0\\0\\0\\0>@@>\\0\\0\\0\\0>@@>\"\n  \"\\0\\0\\0\\0:@@:\\0\\0\\0\\0\\0\\16p\\16\\0\\0\\0\\0~\\24\\24\\10\\0\\0\\0\\0|\\2J\\64\"\n  \"\\0\\0\\0\\0\\60J,x\\0\\0\\0\\0\\60L*x\\0\\0\\0\\0\\60L*|\\0\\0\\0\\0\\64J,z\"\n  \"\\0\\0\\0\\0\\60J(z\\0\\0\\0\\0\\60N.x\\0\\0\\0\\0\\60HxX\\0\\0\\0\\0\\0\\60\\310H\"\n  \"\\0\\0\\0\\0\\60j\\134\\20\\0\\0\\0\\0\\60lZ\\20\\0\\0\\0\\0\\64j\\134\\20\\0\\0\\0\\0\\62hZ\\20\"\n  \"\\0\\0\\0\\0\\0J|@\\0\\0\\0\\0\\0Lz@\\0\\0\\0\\0\\0LzD\\0\\0\\0\\0\\0JxB\"\n  \"\\0\\0\\0\\0\\60JL\\64\\0\\0\\0\\0|\\12\\14r\\0\\0\\0\\0\\60JL\\60\\0\\0\\0\\0\\60LJ\\60\"\n  \"\\0\\0\\0\\0\\60JJ\\60\\0\\0\\0\\0\\64JL\\62\\0\\0\\0\\0\\60JH\\62\\0\\0\\0\\0\\20TT\\20\"\n  \"\\0\\0\\0\\0phX\\70\\0\\0\\0\\0\\70BDx\\0\\0\\0\\0\\70DBx\\0\\0\\0\\0\\70BBx\"\n  \"\\0\\0\\0\\0\\70B@z\\0\\0\\0\\0\\30\\244B\\70\\0\\0\\0\\0\\374HH\\60\\0\\0\\0\\0\\30\\242@:\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--7-70-75-75-C-50-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 95/1848\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x7_r[764] U8X8_FONT_SECTION(\"u8x8_font_5x7_r\") = \n  \" ~\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\16\\0\\16\\0\\0\\0\\0(|(|\"\n  \"(\\0\\0\\0\\10T|T \\0\\0\\0&\\20\\10d\\0\\0\\0\\0(T(@\\0\\0\\0\\0\\0\\0\\16\\0\"\n  \"\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0\\0\\0T\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0``\\0\\0\\0\\0\\0 \\20\\10\\4\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0DbRL\\0\\0\\0\\0\\42JJ\\66\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\200l,\\0\"\n  \"\\0\\0\\0\\0\\0\\20(D\\0\\0\\0\\0((((\\0\\0\\0\\0\\0D(\\20\\0\\0\\0\\0\\0\\4R\\14\"\n  \"\\0\\0\\0\\0<BZ\\34\\0\\0\\0\\0|\\22\\22|\\0\\0\\0\\0~JJ\\64\\0\\0\\0\\0<BB$\"\n  \"\\0\\0\\0\\0~BB<\\0\\0\\0\\0~JJB\\0\\0\\0\\0~\\12\\12\\2\\0\\0\\0\\0<BRt\"\n  \"\\0\\0\\0\\0~\\10\\10~\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0 @@>\\0\\0\\0\\0~\\30$B\"\n  \"\\0\\0\\0\\0~@@@\\0\\0\\0\\0~\\14\\14~\\0\\0\\0\\0~\\14\\60~\\0\\0\\0\\0<BB<\"\n  \"\\0\\0\\0\\0~\\22\\22\\14\\0\\0\\0\\0<bB\\274\\0\\0\\0\\0~\\22\\62L\\0\\0\\0\\0$JR$\"\n  \"\\0\\0\\0\\0\\0\\2~\\2\\0\\0\\0\\0>@@>\\0\\0\\0\\0\\36``\\36\\0\\0\\0\\0~\\60\\60~\"\n  \"\\0\\0\\0\\0f\\30\\30f\\0\\0\\0\\0\\0\\16p\\16\\0\\0\\0\\0bRJF\\0\\0\\0\\0\\0~BB\"\n  \"\\0\\0\\0\\0\\4\\10\\20 \\0\\0\\0\\0\\0BB~\\0\\0\\0\\0\\0\\4\\2\\4\\0\\0\\0\\0@@@@\"\n  \"\\0\\0\\0\\0\\0\\2\\4\\0\\0\\0\\0\\0\\60H(x\\0\\0\\0\\0~HH\\60\\0\\0\\0\\0\\60HH\\0\"\n  \"\\0\\0\\0\\0\\60HH~\\0\\0\\0\\0\\60hX\\20\\0\\0\\0\\0\\20|\\22\\4\\0\\0\\0\\0P\\250\\250\\230\"\n  \"\\0\\0\\0\\0~\\10\\10p\\0\\0\\0\\0\\0Hz@\\0\\0\\0\\0\\0@\\200z\\0\\0\\0\\0~\\20(@\"\n  \"\\0\\0\\0\\0\\0B~@\\0\\0\\0\\0x\\20\\30p\\0\\0\\0\\0x\\10\\10p\\0\\0\\0\\0\\60HH\\60\"\n  \"\\0\\0\\0\\0\\370HH\\60\\0\\0\\0\\0\\60HH\\370\\0\\0\\0\\0x\\10\\10\\20\\0\\0\\0\\0PXh(\"\n  \"\\0\\0\\0\\0\\10>H@\\0\\0\\0\\0\\70@@x\\0\\0\\0\\0\\0\\70@\\70\\0\\0\\0\\0x``x\"\n  \"\\0\\0\\0\\0H\\60\\60H\\0\\0\\0\\0\\30\\240@\\70\\0\\0\\0\\0HhXH\\0\\0\\0\\0\\0\\10<B\"\n  \"\\0\\0\\0\\0\\0\\0~\\0\\0\\0\\0\\0\\0B<\\10\\0\\0\\0\\0\\4\\2\\4\\2\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--7-70-75-75-C-50-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 18/1848\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x7_n[220] U8X8_FONT_SECTION(\"u8x8_font_5x7_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0T\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0``\\0\\0\\0\\0\\0 \\20\\10\\4\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0DbRL\\0\\0\\0\\0\\42JJ\\66\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--8-80-75-75-C-50-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/1426\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x8_f[1796] U8X8_FONT_SECTION(\"u8x8_font_5x8_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\16\\0\\16\\0\\0\\0\\0\\24\\177\\24\\177\"\n  \"\\24\\0\\0\\0\\4*\\177*\\20\\0\\0\\0\\0\\26\\10\\64\\0\\0\\0\\0\\66I\\66@\\0\\0\\0\\0\\0\\0\\16\\0\"\n  \"\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0\\0T\\70\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0@\\340@\\0\\0\\0\\0`\\20\\10\\6\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0dRRL\\0\\0\\0\\0\\42JN\\62\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\0\\200l,\"\n  \"\\0\\0\\0\\0\\0\\30$B\\0\\0\\0\\0((((\\0\\0\\0\\0\\0B$\\30\\0\\0\\0\\0\\0\\4R\\14\"\n  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Share and enjoy.\n  Glyphs: 95/1426\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x8_r[764] U8X8_FONT_SECTION(\"u8x8_font_5x8_r\") = \n  \" ~\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\16\\0\\16\\0\\0\\0\\0\\24\\177\\24\\177\"\n  \"\\24\\0\\0\\0\\4*\\177*\\20\\0\\0\\0\\0\\26\\10\\64\\0\\0\\0\\0\\66I\\66@\\0\\0\\0\\0\\0\\0\\16\\0\"\n  \"\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0\\0T\\70\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0@\\340@\\0\\0\\0\\0`\\20\\10\\6\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0dRRL\\0\\0\\0\\0\\42JN\\62\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\\0\\0\\200l,\"\n  \"\\0\\0\\0\\0\\0\\30$B\\0\\0\\0\\0((((\\0\\0\\0\\0\\0B$\\30\\0\\0\\0\\0\\0\\4R\\14\"\n  \"\\0\\0\\0\\0<B\\231\\245\\36\\0\\0\\0|\\22\\22|\\0\\0\\0\\0~JJ\\64\\0\\0\\0\\0<BB$\"\n  \"\\0\\0\\0\\0~BB<\\0\\0\\0\\0~JJB\\0\\0\\0\\0~\\12\\12\\2\\0\\0\\0\\0<BR\\64\"\n  \"\\0\\0\\0\\0~\\10\\10~\\0\\0\\0\\0\\0B~B\\0\\0\\0\\0 B>\\2\\0\\0\\0\\0~\\10\\64B\"\n  \"\\0\\0\\0\\0~@@@\\0\\0\\0\\0~\\14\\14~\\0\\0\\0\\0~\\14\\70~\\0\\0\\0\\0<BB<\"\n  \"\\0\\0\\0\\0~\\22\\22\\14\\0\\0\\0\\0<Rb\\274\\0\\0\\0\\0~\\22\\22l\\0\\0\\0\\0$JR$\"\n  \"\\0\\0\\0\\0\\0\\2~\\2\\0\\0\\0\\0>@@>\\0\\0\\0\\0\\36``\\36\\0\\0\\0\\0~\\60\\60~\"\n  \"\\0\\0\\0\\0f\\30\\30f\\0\\0\\0\\0\\6\\10p\\10\\6\\0\\0\\0bRJF\\0\\0\\0\\0\\0~BB\"\n  \"\\0\\0\\0\\0\\6\\10\\20`\\0\\0\\0\\0\\0BB~\\0\\0\\0\\0\\0\\4\\2\\4\\0\\0\\0\\0\\200\\200\\200\\200\"\n  \"\\0\\0\\0\\0\\0\\2\\4\\0\\0\\0\\0\\0\\60HHx\\0\\0\\0\\0~HH\\60\\0\\0\\0\\0\\0\\60HH\"\n  \"\\0\\0\\0\\0\\60HH~\\0\\0\\0\\0\\60hX\\20\\0\\0\\0\\0\\20|\\22\\4\\0\\0\\0\\0\\20\\250\\250p\"\n  \"\\0\\0\\0\\0~\\10\\10p\\0\\0\\0\\0\\0Hz@\\0\\0\\0\\0\\0@\\200z\\0\\0\\0\\0~\\20\\20h\"\n  \"\\0\\0\\0\\0\\0B~@\\0\\0\\0\\0x\\10p\\10p\\0\\0\\0x\\10\\10p\\0\\0\\0\\0\\60HH\\60\"\n  \"\\0\\0\\0\\0\\370((\\20\\0\\0\\0\\0\\20((\\370\\0\\0\\0\\0x\\20\\10\\20\\0\\0\\0\\0\\0PX(\"\n  \"\\0\\0\\0\\0\\10>H \\0\\0\\0\\0\\70@@x\\0\\0\\0\\0\\0\\70@\\70\\0\\0\\0\\0\\70@\\60@\"\n  \"\\70\\0\\0\\0H\\60\\60H\\0\\0\\0\\0X\\240\\240x\\0\\0\\0\\0HhXH\\0\\0\\0\\0\\10*UA\"\n  \"\\0\\0\\0\\0\\0\\0~\\0\\0\\0\\0\\0AU*\\10\\0\\0\\0\\0\\4\\2\\4\\2\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--8-80-75-75-C-50-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 18/1426\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_5x8_n[220] U8X8_FONT_SECTION(\"u8x8_font_5x8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0T\\70\\70T\\0\\0\\0\\0\\20\\20|\\20\"\n  \"\\20\\0\\0\\0\\0\\200` \\0\\0\\0\\0\\20\\20\\20\\20\\0\\0\\0\\0\\0@\\340@\\0\\0\\0\\0`\\20\\10\\6\"\n  \"\\0\\0\\0\\0\\0<B<\\0\\0\\0\\0\\0D~@\\0\\0\\0\\0dRRL\\0\\0\\0\\0\\42JN\\62\"\n  \"\\0\\0\\0\\0\\30\\24~\\20\\0\\0\\0\\0.JJ\\62\\0\\0\\0\\0<JJ\\60\\0\\0\\0\\0\\2b\\32\\6\"\n  \"\\0\\0\\0\\0\\64JJ\\64\\0\\0\\0\\0\\14RR<\\0\\0\\0\\0\\0ll\\0\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/3703\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13_1x2_f[3588] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_f\") = \n  \" \\377\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\0\\0\\0\\0\\0\\0\\0\\13\"\n  \"\\0\\0\\0\\0\\0\\0\\70\\0\\0\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\360@@\\360@\\0\\0\\1\\7\\1\"\n  \"\\1\\7\\1\\0\\0`\\220\\370\\220\\20\\0\\0\\0\\4\\4\\17\\4\\3\\0\\0\\0\\20(\\20\\300 \\30\\0\\0\\10\\6\\1\"\n  \"\\4\\12\\4\\0\\0\\300  \\300\\0\\0\\0\\0\\6\\11\\11\\12\\4\\12\\0\\0\\0\\0\\70\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\300\\60\\10\\0\\0\\0\\0\\0\\1\\6\\10\\0\\0\\0\\0\\10\\60\\300\\0\\0\\0\\0\\0\\10\\6\"\n  \"\\1\\0\\0\\0\\0 \\250pp\\250 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\340\\200\\200\\0\\0\\0\\0\\0\\3\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\14\\14\\4\\0\\0\\0\\0\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\"\n  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@\\200\\0\\370\\0\\0\\17\\0\\0\\0\\1\\17\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\370\\210\\210\\210\\210p\\0\\0\\17\\0\\0\\0\\0\\0\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\7\\10\\12\"\n  \"\\14\\10\\27\\0\\0\\370\\210\\210\\210\\210p\\0\\0\\17\\0\\1\\2\\4\\10\\0\\0p\\210\\210\\210\\210\\20\\0\\0\\4\\10\\10\"\n  \"\\10\\10\\7\\0\\10\\10\\10\\370\\10\\10\\10\\0\\0\\0\\0\\17\\0\\0\\0\\0\\0\\370\\0\\0\\0\\0\\370\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\30\\340\\0\\0\\0\\340\\30\\0\\0\\0\\7\\10\\7\\0\\0\\0\\370\\0\\0\\200\\0\\0\\370\\0\\7\\10\\4\\3\"\n  \"\\4\\10\\7\\0\\30 @\\200@ \\30\\0\\14\\2\\1\\0\\1\\2\\14\\0\\30 @\\200@ \\30\\0\\0\\0\\0\\17\"\n  \"\\0\\0\\0\\0\\0\\10\\10\\210H(\\30\\0\\0\\16\\11\\10\\10\\10\\10\\0\\0\\0\\370\\10\\10\\10\\0\\0\\0\\0\\17\\10\"\n  \"\\10\\10\\0\\0\\30 @\\200\\0\\0\\0\\0\\0\\0\\0\\0\\1\\2\\14\\0\\0\\10\\10\\10\\370\\0\\0\\0\\0\\10\\10\\10\"\n  \"\\17\\0\\0\\0\\0 \\20\\10\\20 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\"\\30\\10\\4\\0\\0\\340 $(  \\0\\0\\17\\11\\11\\11\\10\\10\\0\\0\\340 ($  \\0\\0\\17\\11\\11\"\n  \"\\11\\10\\10\\0\\0\\340($$( \\0\\0\\17\\11\\11\\11\\10\\10\\0\\0\\340,  , \\0\\0\\17\\11\\11\"\n  \"\\11\\10\\10\\0\\0 $\\350  \\0\\0\\0\\10\\10\\17\\10\\10\\0\\0\\0  \\350$ \\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\0 (\\344$(\\0\\0\\0\\10\\10\\17\\10\\10\\0\\0\\0, \\340 ,\\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\200\\370\\210\\10\\10\\20\\340\\0\\0\\17\\10\\10\\10\\4\\3\\0\\350D\\204\\10\\10\\4\\340\\0\\17\\0\\0\\1\"\n  \"\\2\\4\\17\\0\\300 $(  \\300\\0\\7\\10\\10\\10\\10\\10\\7\\0\\300  ($ \\300\\0\\7\\10\\10\\10\"\n  \"\\10\\10\\7\\0\\300 ($$(\\300\\0\\7\\10\\10\\10\\10\\10\\7\\0\\310$$(($\\300\\0\\7\\10\\10\\10\"\n  \"\\10\\10\\7\\0\\300,   ,\\300\\0\\7\\10\\10\\10\\10\\10\\7\\0\\0 @\\200\\200@ \\0\\0\\4\\2\\1\"\n  \"\\1\\2\\4\\0\\0\\360\\10\\210h\\30\\364\\0\\0\\27\\14\\13\\10\\10\\7\\0\\0\\340\\4\\10\\0\\0\\340\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\340\\0\\10\\4\\0\\340\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0\\340\\10\\4\\4\\10\\340\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\340\\14\\0\\0\\14\\340\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0`\\200\\10\\204`\\0\\0\\0\\0\\0\\17\"\n  \"\\0\\0\\0\\0\\0\\370\\20\\20\\20\\20\\340\\0\\0\\17\\1\\1\\1\\1\\0\\0\\0\\360\\10\\210H\\60\\0\\0\\0\\17\\0\\10\"\n  \"\\11\\11\\6\\0\\0\\0@HP@\\200\\0\\0\\6\\11\\11\\11\\5\\17\\0\\0\\0@@PH\\200\\0\\0\\6\\11\\11\"\n  \"\\11\\5\\17\\0\\0\\0PHHP\\200\\0\\0\\6\\11\\11\\11\\5\\17\\0\\0\\20HHPP\\210\\0\\0\\6\\11\\11\"\n  \"\\11\\5\\17\\0\\0\\0X@@X\\200\\0\\0\\6\\11\\11\\11\\5\\17\\0\\0\\0HTTH\\200\\0\\0\\6\\11\\11\"\n  \"\\11\\5\\17\\0\\0@@\\200@@\\200\\0\\6\\11\\11\\7\\11\\11\\4\\0\\0\\200@@@@\\200\\0\\0\\7\\10(\"\n  \"\\30\\10\\4\\0\\0\\200@HP@\\200\\0\\0\\7\\11\\11\\11\\11\\5\\0\\0\\200@PH@\\200\\0\\0\\7\\11\\11\"\n  \"\\11\\11\\5\\0\\0\\200PHHP\\200\\0\\0\\7\\11\\11\\11\\11\\5\\0\\0\\200X@@X\\200\\0\\0\\7\\11\\11\"\n  \"\\11\\11\\5\\0\\0\\0H\\320\\0\\0\\0\\0\\0\\10\\10\\17\\10\\10\\0\\0\\0\\0P\\310\\0\\0\\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\0\\20H\\310\\20\\0\\0\\0\\0\\10\\10\\17\\10\\10\\0\\0\\0\\30@\\300\\30\\0\\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\0\\200THXd\\200\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0\\320\\210HPP\\210\\0\\0\\17\\0\\0\"\n  \"\\0\\0\\17\\0\\0\\200HP@@\\200\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0\\200@PH@\\200\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\200PHHP\\200\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0\\220HHPP\\210\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\200X@@X\\200\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0\\200\\200\\260\\200\\200\\0\\0\\0\\0\\0\\6\"\n  \"\\0\\0\\0\\0\\0\\200@@@\\300\\240\\0\\0\\27\\14\\12\\11\\10\\7\\0\\0\\300\\10\\20\\0\\300\\0\\0\\0\\7\\10\\10\"\n  \"\\10\\7\\10\\0\\0\\300\\0\\20\\10\\300\\0\\0\\0\\7\\10\\10\\10\\7\\10\\0\\0\\300\\20\\10\\10\\320\\0\\0\\0\\7\\10\\10\"\n  \"\\10\\7\\10\\0\\0\\300\\30\\0\\30\\300\\0\\0\\0\\7\\10\\10\\10\\7\\10\\0\\0\\300\\0\\20\\10\\0\\300\\0\\0\\23$$\"\n  \"$\\42\\37\\0\\0\\360\\200@@@\\200\\0\\0\\77\\4\\10\\10\\10\\7\\0\\0\\300\\30\\0\\0\\30\\300\\0\\0\\23$$\"\n  \"$\\42\\37\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 95/3703\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13_1x2_r[1524] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_r\") = \n  \" ~\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\0\\0\\0\\0\\0\\0\\0\\13\"\n  \"\\0\\0\\0\\0\\0\\0\\70\\0\\0\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\360@@\\360@\\0\\0\\1\\7\\1\"\n  \"\\1\\7\\1\\0\\0`\\220\\370\\220\\20\\0\\0\\0\\4\\4\\17\\4\\3\\0\\0\\0\\20(\\20\\300 \\30\\0\\0\\10\\6\\1\"\n  \"\\4\\12\\4\\0\\0\\300  \\300\\0\\0\\0\\0\\6\\11\\11\\12\\4\\12\\0\\0\\0\\0\\70\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\300\\60\\10\\0\\0\\0\\0\\0\\1\\6\\10\\0\\0\\0\\0\\10\\60\\300\\0\\0\\0\\0\\0\\10\\6\"\n  \"\\1\\0\\0\\0\\0 \\250pp\\250 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\340\\200\\200\\0\\0\\0\\0\\0\\3\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\14\\14\\4\\0\\0\\0\\0\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10\\34\\10\\0\\0\\0\\0\\0\\0\\200@ \\30\\0\\14\\2\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\340\\20\\10\\10\\20\\340\\0\\0\\3\\4\\10\\10\\4\\3\\0\\0 \\20\\370\\0\\0\\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\0\\60\\10\\10\\10\\210p\\0\\0\\14\\12\\11\\11\\10\\10\\0\\0\\10\\10\\210\\310\\250\\30\\0\\0\\4\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\200@ \\20\\370\\0\\0\\0\\3\\2\\2\\2\\17\\2\\0\\0\\370\\210HHH\\210\\0\\0\\4\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\340\\20\\210\\210\\210\\0\\0\\0\\7\\11\\10\\10\\10\\7\\0\\0\\10\\10\\10\\310(\\30\\0\\0\\0\\14\\3\"\n  \"\\0\\0\\0\\0\\0p\\210\\210\\210\\210p\\0\\0\\7\\10\\10\\10\\10\\7\\0\\0p\\210\\210\\210H\\360\\0\\0\\0\\10\\10\"\n  \"\\10\\4\\3\\0\\0\\0@\\340@\\0\\0\\0\\0\\0\\10\\34\\10\\0\\0\\0\\0\\0@\\340@\\0\\0\\0\\0\\20\\14\\14\"\n  \"\\4\\0\\0\\0\\0\\0\\200@ \\20\\10\\0\\0\\0\\0\\1\\2\\4\\10\\0\\0@@@@@@\\0\\0\\2\\2\\2\"\n  \"\\2\\2\\2\\0\\0\\10\\20 @\\200\\0\\0\\0\\10\\4\\2\\1\\0\\0\\0\\0\\60\\10\\10\\10\\210p\\0\\0\\0\\0\\0\"\n  \"\\13\\0\\0\\0\\0\\360\\10\\210HH\\360\\0\\0\\7\\10\\11\\12\\11\\3\\0\\0\\340\\20\\10\\10\\20\\340\\0\\0\\17\\1\\1\"\n  \"\\1\\1\\17\\0\\0\\370\\210\\210\\210P \\0\\0\\17\\10\\10\\10\\5\\2\\0\\0\\360\\10\\10\\10\\10\\20\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\4\\0\\0\\370\\10\\10\\10\\20\\340\\0\\0\\17\\10\\10\\10\\4\\3\\0\\0\\370\\210\\210\\210\\10\\10\\0\\0\\17\\10\\10\"\n  \"\\10\\10\\10\\0\\0\\370\\210\\210\\210\\10\\10\\0\\0\\17\\0\\0\\0\\0\\0\\0\\0\\360\\10\\10\\10\\10\\20\\0\\0\\7\\10\\10\"\n  \"\\11\\5\\17\\0\\0\\370\\200\\200\\200\\200\\370\\0\\0\\17\\0\\0\\0\\0\\17\\0\\0\\10\\10\\370\\10\\10\\0\\0\\0\\10\\10\\17\"\n  \"\\10\\10\\0\\0\\0\\0\\0\\10\\10\\370\\10\\10\\0\\4\\10\\10\\10\\7\\0\\0\\0\\370\\200@ \\20\\10\\0\\0\\17\\0\\1\"\n  \"\\2\\4\\10\\0\\0\\370\\0\\0\\0\\0\\0\\0\\0\\17\\10\\10\\10\\10\\10\\0\\370 @\\200@ \\370\\0\\17\\0\\0\\1\"\n  \"\\0\\0\\17\\0\\0\\370 @\\200\\0\\370\\0\\0\\17\\0\\0\\0\\1\\17\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\0\\370\\210\\210\\210\\210p\\0\\0\\17\\0\\0\\0\\0\\0\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\7\\10\\12\"\n  \"\\14\\10\\27\\0\\0\\370\\210\\210\\210\\210p\\0\\0\\17\\0\\1\\2\\4\\10\\0\\0p\\210\\210\\210\\210\\20\\0\\0\\4\\10\\10\"\n  \"\\10\\10\\7\\0\\10\\10\\10\\370\\10\\10\\10\\0\\0\\0\\0\\17\\0\\0\\0\\0\\0\\370\\0\\0\\0\\0\\370\\0\\0\\7\\10\\10\"\n  \"\\10\\10\\7\\0\\30\\340\\0\\0\\0\\340\\30\\0\\0\\0\\7\\10\\7\\0\\0\\0\\370\\0\\0\\200\\0\\0\\370\\0\\7\\10\\4\\3\"\n  \"\\4\\10\\7\\0\\30 @\\200@ \\30\\0\\14\\2\\1\\0\\1\\2\\14\\0\\30 @\\200@ \\30\\0\\0\\0\\0\\17\"\n  \"\\0\\0\\0\\0\\0\\10\\10\\210H(\\30\\0\\0\\16\\11\\10\\10\\10\\10\\0\\0\\0\\370\\10\\10\\10\\0\\0\\0\\0\\17\\10\"\n  \"\\10\\10\\0\\0\\30 @\\200\\0\\0\\0\\0\\0\\0\\0\\0\\1\\2\\14\\0\\0\\10\\10\\10\\370\\0\\0\\0\\0\\10\\10\\10\"\n  \"\\17\\0\\0\\0\\0 \\20\\10\\20 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\"\\10\\10\\7\\0\\0\\300\\200@@@\\200\\0\\0\\77\\2\\4\\4\\4\\3\\0\\0\\200@@@\\200\\300\\0\\0\\3\\4\\4\"\n  \"\\4\\2\\77\\0\\0@\\200@@@\\200\\0\\0\\0\\17\\0\\0\\0\\0\\0\\0\\200@@@@\\200\\0\\0\\4\\11\\11\"\n  \"\\12\\12\\4\\0\\0@\\360@@@\\0\\0\\0\\0\\7\\10\\10\\10\\4\\0\\0\\300\\0\\0\\0\\300\\0\\0\\0\\7\\10\\10\"\n  \"\\10\\7\\10\\0\\0\\300\\0\\0\\0\\300\\0\\0\\0\\1\\6\\10\\6\\1\\0\\0\\300\\0\\0\\0\\0\\0\\300\\0\\7\\10\\4\\3\"\n  \"\\4\\10\\7\\0\\0@\\200\\0\\0\\200@\\0\\0\\10\\4\\3\\3\\4\\10\\0\\0\\300\\0\\0\\0\\0\\300\\0\\0\\23$$\"\n  \"$\\42\\37\\0\\0@@@@\\300@\\0\\0\\10\\14\\12\\11\\10\\10\\0\\0\\0\\200\\260H\\10\\10\\0\\0\\0\\0\\6\"\n  \"\\11\\10\\10\\0\\0\\0\\0\\370\\0\\0\\0\\0\\0\\0\\0\\17\\0\\0\\0\\0\\0\\10\\10H\\260\\200\\0\\0\\0\\10\\10\\11\"\n  \"\\6\\0\\0\\0\\0\\60\\10\\20 \\30\\0\\0\\0\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 18/3703\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13_1x2_n[436] U8X8_FONT_SECTION(\"u8x8_font_8x13_1x2_n\") = \n  \" :\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0@P\\340\\340P@\\0\\0\\0\\1\\0\\0\\1\\0\\0\\0\\0\\0\\300\\0\\0\\0\\0\\0\\1\\1\\7\"\n  \"\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0 \\30\\30\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\"\n  \"\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\70\\20\\0\\0\\0\\0\\0\\0\\0\\200@\\60\\0\\30\\4\\2\\1\"\n  \"\\0\\0\\0\\0\\0\\300 \\20\\20 \\300\\0\\0\\7\\10\\20\\20\\10\\7\\0\\0@ \\360\\0\\0\\0\\0\\0\\20\\20\\37\"\n  \"\\20\\20\\0\\0\\0`\\20\\20\\20\\20\\340\\0\\0\\30\\24\\22\\22\\21\\20\\0\\0\\20\\20\\20\\220P\\60\\0\\0\\10\\20\\21\"\n  \"\\21\\21\\16\\0\\0\\0\\200@ \\360\\0\\0\\0\\7\\4\\4\\4\\37\\4\\0\\0\\360\\20\\220\\220\\220\\20\\0\\0\\11\\21\\20\"\n  \"\\20\\20\\17\\0\\0\\300 \\20\\20\\20\\0\\0\\0\\17\\22\\21\\21\\21\\16\\0\\0\\20\\20\\20\\220P\\60\\0\\0\\0\\30\\6\"\n  \"\\1\\0\\0\\0\\0\\340\\20\\20\\20\\20\\340\\0\\0\\16\\21\\21\\21\\21\\16\\0\\0\\340\\20\\20\\20\\220\\340\\0\\0\\0\\21\\21\"\n  \"\\21\\10\\7\\0\\0\\0\\200\\300\\200\\0\\0\\0\\0\\0\\20\\71\\20\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/1141\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13B_1x2_f[3588] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_f\") = \n  \" \\377\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\\0\\0\\15\"\n  \"\\15\\0\\0\\0\\0<<\\0<<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0`\\370\\370`\\370\\370`\\0\\3\\17\\17\\3\"\n  \"\\17\\17\\3\\0p\\370\\310\\374\\210\\230\\20\\0\\4\\14\\10\\37\\11\\17\\7\\0\\34\\24\\234\\340p\\34\\14\\0\\14\\16\\3\\1\"\n  \"\\16\\12\\16\\0\\300\\340  \\340\\300\\0\\0\\6\\17\\11\\11\\17\\16\\12\\0\\0\\0\\0<<\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\300\\360\\70\\14\\4\\0\\0\\0\\1\\7\\16\\30\\20\\0\\0\\0\\4\\14\\70\\360\\300\\0\\0\\0\\20\\30\\16\"\n  \"\\7\\1\\0\\0@@\\300\\360\\300@@\\0\\0\\6\\3\\1\\3\\6\\0\\0\\0\\300\\300\\360\\360\\300\\300\\0\\0\\0\\0\\3\"\n  \"\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\21\\37\\17\\7\\0\\0\\0\\200\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\4\\16\\16\\4\\0\\0\\0\\0\\200\\300`\\70\\34\\0\\16\\7\\1\\0\"\n  \"\\0\\0\\0\\0\\360\\370\\14\\4\\14\\370\\360\\0\\3\\7\\14\\10\\14\\7\\3\\0\\0\\20\\30\\374\\374\\0\\0\\0\\0\\10\\10\\17\"\n  \"\\17\\10\\10\\0\\30\\34\\4\\204\\304|\\70\\0\\14\\16\\13\\11\\10\\10\\10\\0\\4\\4Ddt\\334\\214\\0\\4\\14\\10\\10\"\n  \"\\10\\17\\7\\0\\300\\340\\60\\30\\374\\374\\0\\0\\1\\1\\1\\1\\17\\17\\1\\0||d$$\\344\\304\\0\\4\\14\\10\\10\"\n  \"\\10\\17\\7\\0\\360\\370\\314DD\\304\\200\\0\\7\\17\\14\\10\\10\\17\\7\\0\\4\\4\\4\\304\\344<\\34\\0\\0\\0\\17\\17\"\n  \"\\0\\0\\0\\0\\270\\374DDD\\374\\270\\0\\7\\17\\10\\10\\10\\17\\7\\0x\\374\\204\\204\\314\\374\\370\\0\\0\\10\\10\\10\"\n  \"\\14\\7\\3\\0\\0\\0 pp \\0\\0\\0\\0\\4\\16\\16\\4\\0\\0\\0\\0 pp \\0\\0\\0\\0\\21\\37\"\n  \"\\17\\7\\0\\0\\0\\200\\300`\\60\\30\\10\\0\\0\\0\\1\\3\\6\\14\\10\\0\\0@@@@@@\\0\\0\\2\\2\\2\"\n  \"\\2\\2\\2\\0\\0\\10\\30\\60`\\300\\200\\0\\0\\10\\14\\6\\3\\1\\0\\0\\30\\34\\4\\204\\304|\\70\\0\\0\\0\\0\\15\"\n  \"\\15\\0\\0\\0\\360\\370\\30\\330xx\\360\\0\\7\\17\\14\\13\\12\\12\\13\\0\\360\\370\\214\\214\\214\\370\\360\\0\\17\\17\\0\\0\"\n  \"\\0\\17\\17\\0\\4\\374\\374DD\\374\\270\\0\\10\\17\\17\\10\\10\\17\\7\\0\\370\\374\\14\\4\\4\\34\\30\\0\\7\\17\\14\\10\"\n  \"\\10\\16\\6\\0\\4\\374\\374\\4\\4\\374\\370\\0\\10\\17\\17\\10\\10\\17\\7\\0\\374\\374DDD\\4\\4\\0\\17\\17\\10\\10\"\n  \"\\10\\10\\10\\0\\374\\374DDD\\4\\4\\0\\17\\17\\0\\0\\0\\0\\0\\0\\370\\374\\4\\4\\4\\34\\30\\0\\7\\17\\10\\10\"\n  \"\\11\\17\\7\\0\\374\\374@@@\\374\\374\\0\\17\\17\\0\\0\\0\\17\\17\\0\\0\\0\\4\\374\\374\\4\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\0\\0\\0\\4\\374\\374\\0\\6\\16\\10\\10\\10\\17\\7\\0\\374\\374\\300\\340\\60\\34\\14\\0\\17\\17\\0\\1\"\n  \"\\3\\16\\14\\0\\374\\374\\0\\0\\0\\0\\0\\0\\17\\17\\10\\10\\10\\10\\14\\0\\374\\374\\60`\\60\\374\\374\\0\\17\\17\\0\\0\"\n  \"\\0\\17\\17\\0\\374\\374p\\300\\200\\374\\374\\0\\17\\17\\0\\0\\3\\17\\17\\0\\370\\374\\4\\4\\4\\374\\370\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\374\\374\\204\\204\\204\\374x\\0\\17\\17\\0\\0\\0\\0\\0\\0\\370\\374\\4\\4\\4\\374\\370\\0\\7\\17\\10\\14\"\n  \"\\14\\37\\27\\0\\374\\374\\304\\304\\304|\\70\\0\\17\\17\\0\\0\\3\\17\\14\\0\\70|DDD\\334\\230\\0\\6\\16\\10\\10\"\n  \"\\10\\17\\7\\0\\0\\4\\4\\374\\374\\4\\4\\0\\0\\0\\0\\17\\17\\0\\0\\0\\374\\374\\0\\0\\0\\374\\374\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0<\\374\\200\\0\\200\\374<\\0\\0\\1\\7\\16\\7\\1\\0\\0\\374\\374\\0\\0\\0\\374\\374\\0\\7\\17\\14\\7\"\n  \"\\14\\17\\7\\0\\14<\\360\\300\\360<\\14\\0\\14\\17\\3\\0\\3\\17\\14\\0\\0\\34|\\340\\340|\\34\\0\\0\\0\\0\\17\"\n  \"\\17\\0\\0\\0\\4\\4\\204\\304d<\\34\\0\\16\\17\\11\\10\\10\\10\\10\\0\\0\\374\\374\\4\\4\\4\\0\\0\\0\\37\\37\\20\"\n  \"\\20\\20\\0\\0\\34\\70`\\300\\200\\0\\0\\0\\0\\0\\0\\0\\1\\7\\16\\0\\0\\4\\4\\4\\374\\374\\0\\0\\0\\20\\20\\20\"\n  \"\\37\\37\\0\\0 \\60\\30\\14\\30\\60 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\20\\20\\20\"\n  \"\\20\\20\\20\\0\\0\\0\\4\\14\\30\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\240\\240\\240\\240\\340\\300\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\374\\374@  \\340\\300\\0\\17\\17\\4\\10\\10\\17\\7\\0\\300\\340`  `@\\0\\7\\17\\14\\10\"\n  \"\\10\\14\\4\\0\\300\\340  @\\374\\374\\0\\7\\17\\10\\10\\4\\17\\17\\0\\300\\340   \\340\\300\\0\\7\\17\\11\\11\"\n  \"\\11\\15\\5\\0\\200\\370\\374\\204\\204\\214\\10\\0\\0\\17\\17\\0\\0\\0\\0\\0\\300\\340  \\340\\340 \\0\\25\\77..\"\n  \"+\\71\\20\\0\\374\\374@  \\340\\300\\0\\17\\17\\0\\0\\0\\17\\17\\0\\0\\0@\\330\\330\\0\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\0\\0\\0@\\330\\330\\0\\30\\70   \\77\\37\\0\\374\\374\\200\\300` \\0\\0\\17\\17\\1\\3\"\n  \"\\6\\14\\10\\0\\0\\0\\4\\374\\374\\0\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\300\\340`\\300`\\340\\300\\0\\17\\17\\0\\1\"\n  \"\\0\\17\\17\\0\\340\\340@  \\340\\300\\0\\17\\17\\0\\0\\0\\17\\17\\0\\300\\340   \\340\\300\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\340@  \\340\\300\\0\\77\\77\\4\\10\\10\\17\\7\\0\\300\\340  @\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\77\\77\\0\\340\\340@  `@\\0\\17\\17\\0\\0\\0\\0\\0\\0@\\340\\240  `@\\0\\4\\14\\11\\11\"\n  \"\\13\\16\\4\\0@\\374\\374@@@\\0\\0\\0\\7\\17\\10\\10\\14\\4\\0\\340\\340\\0\\0\\0\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\340\\340\\0\\0\\0\\340\\340\\0\\1\\7\\16\\10\\16\\7\\1\\0\\340\\340\\0\\0\\0\\340\\340\\0\\7\\17\\14\\7\"\n  \"\\14\\17\\7\\0`\\340\\200\\0\\200\\340`\\0\\14\\16\\3\\1\\3\\16\\14\\0\\340\\340\\0\\0\\0\\340\\340\\0\\23\\67$$\"\n  \"\\42\\77\\37\\0   \\240\\340` \\0\\14\\16\\13\\11\\10\\10\\10\\0\\0\\200\\270\\374D\\4\\4\\0\\0\\0\\16\\37\"\n  \"\\21\\20\\20\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\\0\\0\\17\\17\\0\\0\\0\\0\\4\\4D\\374\\270\\200\\0\\0\\20\\20\\21\"\n  \"\\37\\16\\0\\0\\60\\30\\30\\70\\60\\60\\30\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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`\\360\\60\\0\\6\\7\\3\\2\\3\\7\\6\\0\\0\\234\\374\\340\\340\\374\\234\\0\\0\\2\\2\\17\"\n  \"\\17\\2\\2\\0\\0\\0\\0<<\\0\\0\\0\\0\\0\\0\\17\\17\\0\\0\\0\\0\\330\\374$$\\354\\310\\0\\0\\4\\15\\11\"\n  \"\\11\\17\\6\\0\\0\\14\\14\\0\\14\\14\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\354\\364\\24\\264\\14\\370\\0\\3\\6\\5\\5\"\n  \"\\5\\6\\3\\0\\0tTT|x\\0\\0\\0\\1\\1\\1\\1\\1\\0\\0\\300`\\260\\320`\\60\\20\\0\\1\\3\\6\\5\"\n  \"\\3\\6\\4\\0\\300\\300\\300\\300\\300\\300\\0\\0\\0\\0\\0\\0\\0\\7\\0\\0\\0\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\370\\14\\364\\324t\\14\\370\\0\\3\\6\\5\\4\\5\\6\\3\\0\\0\\2\\2\\2\\2\\2\\2\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\30<$$<\\30\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@@\\360\\360@@\\0\\0\\4\\4\\5\"\n  \"\\5\\4\\4\\0\\0\\314\\344\\274\\230\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\314\\224\\374h\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\30\\14\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\340\\0\\0\\0\\340\\340\\0\\77\\77\\14\\10\"\n  \"\\14\\17\\7\\0p\\370\\214\\214\\374\\4\\374\\0\\0\\0\\1\\1\\37\\20\\37\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20 (\\30\\0\\0\\0\\0\\210\\374\\374\\200\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\70lll\\70\\0\\0\\0\\1\\1\\1\\1\\1\\0\\0\\20\\60`\\320\\260`\\300\\0\\4\\6\\3\\5\"\n  \"\\6\\3\\1\\0\\210\\374\\374\\200\\0\\200\\300\\0\\0\\0\\0\\6\\7\\15\\17\\0\\210\\374\\374\\300@\\300\\200\\0\\0\\0\\0\\14\"\n  \"\\16\\13\\11\\0\\314\\224\\374h\\0\\200\\300\\0\\0\\0\\0\\6\\7\\15\\17\\0\\0\\0\\200\\354l\\0\\0\\0\\0\\7\\17\\10\"\n  \"\\10\\16\\6\\0\\200\\300dlh\\300\\200\\0\\17\\17\\2\\2\\2\\17\\17\\0\\200\\300hld\\300\\200\\0\\17\\17\\2\\2\"\n  \"\\2\\17\\17\\0\\200\\310ldl\\310\\200\\0\\17\\17\\2\\2\\2\\17\\17\\0\\200\\310dlh\\304\\200\\0\\17\\17\\2\\2\"\n  \"\\2\\17\\17\\0\\200\\314l`l\\314\\200\\0\\17\\17\\2\\2\\2\\17\\17\\0\\200\\300djj\\304\\200\\0\\17\\17\\2\\2\"\n  \"\\2\\17\\17\\0\\370\\374\\214\\374\\374\\204\\4\\0\\17\\17\\0\\17\\17\\10\\10\\0\\370\\374\\14\\4\\4\\14\\10\\0\\3\\27&,\"\n  \"\\34\\6\\2\\0\\340\\340$,(  \\0\\17\\17\\11\\11\\11\\10\\10\\0\\340\\340(,$  \\0\\17\\17\\11\\11\"\n  \"\\11\\10\\10\\0\\340\\350,$,( \\0\\17\\17\\11\\11\\11\\10\\10\\0\\340\\354, ,, \\0\\17\\17\\11\\11\"\n  \"\\11\\10\\10\\0\\0\\0$\\354\\350 \\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\0\\0 \\350\\354$\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\0(\\354\\344,\\10\\0\\0\\0\\10\\17\\17\\10\\0\\0\\0\\0,\\354\\340,\\14\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\220\\360\\360\\220\\20\\360\\340\\0\\10\\17\\17\\10\\10\\17\\7\\0\\340\\350\\304\\214\\10\\344\\340\\0\\17\\17\\0\\3\"\n  \"\\6\\17\\17\\0\\340\\360\\22\\26\\24\\360\\340\\0\\7\\17\\10\\10\\10\\17\\7\\0\\340\\360\\24\\26\\22\\360\\340\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\364\\26\\22\\26\\364\\340\\0\\7\\17\\10\\10\\10\\17\\7\\0\\340\\364\\22\\26\\24\\362\\340\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\366\\26\\20\\26\\366\\340\\0\\7\\17\\10\\10\\10\\17\\7\\0`\\340\\200\\200\\200\\340`\\0\\14\\16\\3\\3\"\n  \"\\3\\16\\14\\0\\340\\360\\20\\320\\60\\360\\350\\0\\27\\17\\14\\13\\10\\17\\7\\0\\340\\340\\4\\14\\10\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\340\\10\\14\\4\\340\\340\\0\\7\\17\\10\\10\\10\\17\\7\\0\\340\\350\\14\\4\\14\\350\\340\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\354\\14\\0\\14\\354\\340\\0\\7\\17\\10\\10\\10\\17\\7\\0\\0 \\340\\210\\214\\344 \\0\\0\\0\\0\\17\"\n  \"\\17\\0\\0\\0\\370\\370\\20\\20\\20\\360\\340\\0\\17\\17\\1\\1\\1\\1\\0\\0@\\370\\374\\4\\344\\374\\30\\0\\0\\17\\17\\0\"\n  \"\\10\\17\\7\\0\\0\\240\\244\\254\\250\\340\\300\\0\\7\\17\\10\\10\\4\\17\\17\\0\\0\\240\\250\\254\\244\\340\\300\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\0\\250\\254\\244\\254\\350\\300\\0\\7\\17\\10\\10\\4\\17\\17\\0\\0\\250\\244\\254\\250\\344\\300\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\0\\254\\254\\240\\254\\354\\300\\0\\7\\17\\10\\10\\4\\17\\17\\0\\0\\240\\244\\252\\252\\344\\300\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0@` \\300\\340 \\300\\0\\6\\17\\11\\7\\17\\11\\4\\0\\340\\360\\60\\20\\20\\60 \\0\\3\\27&,\"\n  \"\\34\\6\\2\\0\\300\\340$,(\\340\\300\\0\\7\\17\\11\\11\\11\\15\\5\\0\\300\\340(,$\\340\\300\\0\\7\\17\\11\\11\"\n  \"\\11\\15\\5\\0\\300\\350,$,\\350\\300\\0\\7\\17\\11\\11\\11\\15\\5\\0\\300\\354, ,\\354\\300\\0\\7\\17\\11\\11\"\n  \"\\11\\15\\5\\0\\0\\0$\\354\\350\\0\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\0\\0(\\354\\344\\0\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\10,\\344\\354\\10\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\0\\14,\\340\\354\\14\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\200\\324\\134X|\\344\\300\\0\\7\\17\\10\\10\\10\\17\\7\\0\\340\\350D,(\\344\\300\\0\\17\\17\\0\\0\"\n  \"\\0\\17\\17\\0\\300\\340$,(\\340\\300\\0\\7\\17\\10\\10\\10\\17\\7\\0\\300\\340(,$\\340\\300\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\300\\350,$,\\350\\300\\0\\7\\17\\10\\10\\10\\17\\7\\0\\300\\350$,(\\344\\300\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\300\\354, ,\\354\\300\\0\\7\\17\\10\\10\\10\\17\\7\\0\\0\\200\\200\\260\\260\\200\\200\\0\\0\\0\\0\\6\"\n  \"\\6\\0\\0\\0\\300\\340 \\240`\\340\\320\\0\\27\\17\\14\\13\\10\\17\\7\\0\\340\\340\\4\\14\\10\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\340\\340\\10\\14\\4\\340\\340\\0\\7\\17\\10\\10\\4\\17\\17\\0\\340\\350\\14\\4\\14\\350\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\340\\354\\14\\0\\14\\354\\340\\0\\7\\17\\10\\10\\4\\17\\17\\0\\340\\340\\10\\14\\4\\340\\340\\0\\23\\67$$\"\n  \"\\42\\77\\37\\0\\370\\370@  \\340\\300\\0\\77\\77\\4\\10\\10\\17\\7\\0\\340\\354\\14\\0\\14\\354\\340\\0\\23\\67$$\"\n  \"\\42\\77\\37\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 95/1141\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13B_1x2_r[1524] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_r\") = \n  \" ~\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\\0\\0\\15\"\n  \"\\15\\0\\0\\0\\0<<\\0<<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0`\\370\\370`\\370\\370`\\0\\3\\17\\17\\3\"\n  \"\\17\\17\\3\\0p\\370\\310\\374\\210\\230\\20\\0\\4\\14\\10\\37\\11\\17\\7\\0\\34\\24\\234\\340p\\34\\14\\0\\14\\16\\3\\1\"\n  \"\\16\\12\\16\\0\\300\\340  \\340\\300\\0\\0\\6\\17\\11\\11\\17\\16\\12\\0\\0\\0\\0<<\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\300\\360\\70\\14\\4\\0\\0\\0\\1\\7\\16\\30\\20\\0\\0\\0\\4\\14\\70\\360\\300\\0\\0\\0\\20\\30\\16\"\n  \"\\7\\1\\0\\0@@\\300\\360\\300@@\\0\\0\\6\\3\\1\\3\\6\\0\\0\\0\\300\\300\\360\\360\\300\\300\\0\\0\\0\\0\\3\"\n  \"\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\21\\37\\17\\7\\0\\0\\0\\200\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\4\\16\\16\\4\\0\\0\\0\\0\\200\\300`\\70\\34\\0\\16\\7\\1\\0\"\n  \"\\0\\0\\0\\0\\360\\370\\14\\4\\14\\370\\360\\0\\3\\7\\14\\10\\14\\7\\3\\0\\0\\20\\30\\374\\374\\0\\0\\0\\0\\10\\10\\17\"\n  \"\\17\\10\\10\\0\\30\\34\\4\\204\\304|\\70\\0\\14\\16\\13\\11\\10\\10\\10\\0\\4\\4Ddt\\334\\214\\0\\4\\14\\10\\10\"\n  \"\\10\\17\\7\\0\\300\\340\\60\\30\\374\\374\\0\\0\\1\\1\\1\\1\\17\\17\\1\\0||d$$\\344\\304\\0\\4\\14\\10\\10\"\n  \"\\10\\17\\7\\0\\360\\370\\314DD\\304\\200\\0\\7\\17\\14\\10\\10\\17\\7\\0\\4\\4\\4\\304\\344<\\34\\0\\0\\0\\17\\17\"\n  \"\\0\\0\\0\\0\\270\\374DDD\\374\\270\\0\\7\\17\\10\\10\\10\\17\\7\\0x\\374\\204\\204\\314\\374\\370\\0\\0\\10\\10\\10\"\n  \"\\14\\7\\3\\0\\0\\0 pp \\0\\0\\0\\0\\4\\16\\16\\4\\0\\0\\0\\0 pp \\0\\0\\0\\0\\21\\37\"\n  \"\\17\\7\\0\\0\\0\\200\\300`\\60\\30\\10\\0\\0\\0\\1\\3\\6\\14\\10\\0\\0@@@@@@\\0\\0\\2\\2\\2\"\n  \"\\2\\2\\2\\0\\0\\10\\30\\60`\\300\\200\\0\\0\\10\\14\\6\\3\\1\\0\\0\\30\\34\\4\\204\\304|\\70\\0\\0\\0\\0\\15\"\n  \"\\15\\0\\0\\0\\360\\370\\30\\330xx\\360\\0\\7\\17\\14\\13\\12\\12\\13\\0\\360\\370\\214\\214\\214\\370\\360\\0\\17\\17\\0\\0\"\n  \"\\0\\17\\17\\0\\4\\374\\374DD\\374\\270\\0\\10\\17\\17\\10\\10\\17\\7\\0\\370\\374\\14\\4\\4\\34\\30\\0\\7\\17\\14\\10\"\n  \"\\10\\16\\6\\0\\4\\374\\374\\4\\4\\374\\370\\0\\10\\17\\17\\10\\10\\17\\7\\0\\374\\374DDD\\4\\4\\0\\17\\17\\10\\10\"\n  \"\\10\\10\\10\\0\\374\\374DDD\\4\\4\\0\\17\\17\\0\\0\\0\\0\\0\\0\\370\\374\\4\\4\\4\\34\\30\\0\\7\\17\\10\\10\"\n  \"\\11\\17\\7\\0\\374\\374@@@\\374\\374\\0\\17\\17\\0\\0\\0\\17\\17\\0\\0\\0\\4\\374\\374\\4\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\0\\0\\0\\4\\374\\374\\0\\6\\16\\10\\10\\10\\17\\7\\0\\374\\374\\300\\340\\60\\34\\14\\0\\17\\17\\0\\1\"\n  \"\\3\\16\\14\\0\\374\\374\\0\\0\\0\\0\\0\\0\\17\\17\\10\\10\\10\\10\\14\\0\\374\\374\\60`\\60\\374\\374\\0\\17\\17\\0\\0\"\n  \"\\0\\17\\17\\0\\374\\374p\\300\\200\\374\\374\\0\\17\\17\\0\\0\\3\\17\\17\\0\\370\\374\\4\\4\\4\\374\\370\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\374\\374\\204\\204\\204\\374x\\0\\17\\17\\0\\0\\0\\0\\0\\0\\370\\374\\4\\4\\4\\374\\370\\0\\7\\17\\10\\14\"\n  \"\\14\\37\\27\\0\\374\\374\\304\\304\\304|\\70\\0\\17\\17\\0\\0\\3\\17\\14\\0\\70|DDD\\334\\230\\0\\6\\16\\10\\10\"\n  \"\\10\\17\\7\\0\\0\\4\\4\\374\\374\\4\\4\\0\\0\\0\\0\\17\\17\\0\\0\\0\\374\\374\\0\\0\\0\\374\\374\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0<\\374\\200\\0\\200\\374<\\0\\0\\1\\7\\16\\7\\1\\0\\0\\374\\374\\0\\0\\0\\374\\374\\0\\7\\17\\14\\7\"\n  \"\\14\\17\\7\\0\\14<\\360\\300\\360<\\14\\0\\14\\17\\3\\0\\3\\17\\14\\0\\0\\34|\\340\\340|\\34\\0\\0\\0\\0\\17\"\n  \"\\17\\0\\0\\0\\4\\4\\204\\304d<\\34\\0\\16\\17\\11\\10\\10\\10\\10\\0\\0\\374\\374\\4\\4\\4\\0\\0\\0\\37\\37\\20\"\n  \"\\20\\20\\0\\0\\34\\70`\\300\\200\\0\\0\\0\\0\\0\\0\\0\\1\\7\\16\\0\\0\\4\\4\\4\\374\\374\\0\\0\\0\\20\\20\\20\"\n  \"\\37\\37\\0\\0 \\60\\30\\14\\30\\60 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\20\\20\\20\"\n  \"\\20\\20\\20\\0\\0\\0\\4\\14\\30\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\240\\240\\240\\240\\340\\300\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\374\\374@  \\340\\300\\0\\17\\17\\4\\10\\10\\17\\7\\0\\300\\340`  `@\\0\\7\\17\\14\\10\"\n  \"\\10\\14\\4\\0\\300\\340  @\\374\\374\\0\\7\\17\\10\\10\\4\\17\\17\\0\\300\\340   \\340\\300\\0\\7\\17\\11\\11\"\n  \"\\11\\15\\5\\0\\200\\370\\374\\204\\204\\214\\10\\0\\0\\17\\17\\0\\0\\0\\0\\0\\300\\340  \\340\\340 \\0\\25\\77..\"\n  \"+\\71\\20\\0\\374\\374@  \\340\\300\\0\\17\\17\\0\\0\\0\\17\\17\\0\\0\\0@\\330\\330\\0\\0\\0\\0\\0\\10\\17\"\n  \"\\17\\10\\0\\0\\0\\0\\0\\0@\\330\\330\\0\\30\\70   \\77\\37\\0\\374\\374\\200\\300` \\0\\0\\17\\17\\1\\3\"\n  \"\\6\\14\\10\\0\\0\\0\\4\\374\\374\\0\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\300\\340`\\300`\\340\\300\\0\\17\\17\\0\\1\"\n  \"\\0\\17\\17\\0\\340\\340@  \\340\\300\\0\\17\\17\\0\\0\\0\\17\\17\\0\\300\\340   \\340\\300\\0\\7\\17\\10\\10\"\n  \"\\10\\17\\7\\0\\340\\340@  \\340\\300\\0\\77\\77\\4\\10\\10\\17\\7\\0\\300\\340  @\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\77\\77\\0\\340\\340@  `@\\0\\17\\17\\0\\0\\0\\0\\0\\0@\\340\\240  `@\\0\\4\\14\\11\\11\"\n  \"\\13\\16\\4\\0@\\374\\374@@@\\0\\0\\0\\7\\17\\10\\10\\14\\4\\0\\340\\340\\0\\0\\0\\340\\340\\0\\7\\17\\10\\10\"\n  \"\\4\\17\\17\\0\\340\\340\\0\\0\\0\\340\\340\\0\\1\\7\\16\\10\\16\\7\\1\\0\\340\\340\\0\\0\\0\\340\\340\\0\\7\\17\\14\\7\"\n  \"\\14\\17\\7\\0`\\340\\200\\0\\200\\340`\\0\\14\\16\\3\\1\\3\\16\\14\\0\\340\\340\\0\\0\\0\\340\\340\\0\\23\\67$$\"\n  \"\\42\\77\\37\\0   \\240\\340` \\0\\14\\16\\13\\11\\10\\10\\10\\0\\0\\200\\270\\374D\\4\\4\\0\\0\\0\\16\\37\"\n  \"\\21\\20\\20\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\\0\\0\\17\\17\\0\\0\\0\\0\\4\\4D\\374\\270\\200\\0\\0\\20\\20\\21\"\n  \"\\37\\16\\0\\0\\60\\30\\30\\70\\60\\60\\30\\0\\0\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--13-120-75-75-C-80-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 18/1141\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_8x13B_1x2_n[436] U8X8_FONT_SECTION(\"u8x8_font_8x13B_1x2_n\") = \n  \" :\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\200\\200\\200\\340\\200\\200\\200\\0\\0\\14\\7\\3\\7\\14\\0\\0\\0\\200\\200\\340\\340\\200\\200\\0\\0\\1\\1\\7\"\n  \"\\7\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\42>\\36\\16\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\"\n  \"\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10\\34\\34\\10\\0\\0\\0\\0\\0\\200\\300p\\70\\0\\34\\16\\3\\1\"\n  \"\\0\\0\\0\\0\\340\\360\\30\\10\\30\\360\\340\\0\\7\\17\\30\\20\\30\\17\\7\\0\\0 \\60\\370\\370\\0\\0\\0\\0\\20\\20\\37\"\n  \"\\37\\20\\20\\0\\60\\70\\10\\10\\210\\370p\\0\\30\\34\\26\\23\\21\\20\\20\\0\\10\\10\\210\\310\\350\\270\\30\\0\\10\\30\\20\\20\"\n  \"\\20\\37\\17\\0\\200\\300`\\60\\370\\370\\0\\0\\3\\3\\2\\2\\37\\37\\2\\0\\370\\370\\310HH\\310\\210\\0\\10\\30\\20\\20\"\n  \"\\20\\37\\17\\0\\340\\360\\230\\210\\210\\210\\0\\0\\17\\37\\31\\20\\20\\37\\17\\0\\10\\10\\10\\210\\310x\\70\\0\\0\\0\\36\\37\"\n  \"\\1\\0\\0\\0p\\370\\210\\210\\210\\370p\\0\\17\\37\\20\\20\\20\\37\\17\\0\\360\\370\\10\\10\\230\\370\\360\\0\\0\\21\\21\\21\"\n  \"\\31\\17\\7\\0\\0\\0@\\340\\340@\\0\\0\\0\\0\\10\\34\\34\\10\\0\";\n/*\n  Fontname: -Misc-Fixed-Medium-R-Normal--14-130-75-75-C-70-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/2576\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_7x14_1x2_f[3588] U8X8_FONT_SECTION(\"u8x8_font_7x14_1x2_f\") = \n  \" \\377\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\33\\0\\0\\0\\0\\0\\0<\\0<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\370@\\370@\\0\\0\\0\\2\\37\"\n  \"\\2\\37\\2\\0\\0`\\220\\20\\370\\20`\\0\\0\\14\\20\\21\\77\\21\\16\\0\\0\\60HH\\360 \\30\\0\\0\\30\\4\\17\"\n  \"\\22\\22\\14\\0\\0\\0p\\210\\210p\\0\\0\\0\\16\\21\\21\\12\\14\\23\\0\\0\\0\\0\\0<\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\300\\60\\10\\4\\0\\0\\0\\0\\7\\30 @\\0\\0\\0\\4\\10\\60\\300\\0\\0\\0\\0@ \"\n  \"\\30\\7\\0\\0\\0\\0@\\200\\340\\200@\\0\\0\\0\\4\\2\\17\\2\\4\\0\\0\\0\\0\\0\\340\\0\\0\\0\\0\\0\\1\\1\"\n  \"\\17\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0H\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\"\n  \"\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\70\\20\\0\\0\\0\\0\\0\\0\\300\\60\\14\\0\\0`\\30\\6\"\n  \"\\1\\0\\0\\0\\0\\340\\20\\10\\10\\20\\340\\0\\0\\7\\10\\20\\20\\10\\7\\0\\0\\0 \\20\\370\\0\\0\\0\\0\\0\\20\\20\"\n  \"\\37\\20\\20\\0\\0\\60\\10\\10\\10\\210p\\0\\0\\20\\30\\24\\22\\21\\20\\0\\0\\10\\10\\210\\310\\250\\30\\0\\0\\14\\20\\20\"\n  \"\\20\\20\\17\\0\\0\\0\\200`\\20\\370\\0\\0\\0\\6\\5\\4\\4\\37\\4\\0\\0\\370HHHH\\210\\0\\0\\14\\20\\20\"\n  \"\\20\\20\\17\\0\\0\\340\\20\\210\\210\\210\\0\\0\\0\\17\\21\\20\\20\\20\\17\\0\\0\\10\\10\\10\\210h\\30\\0\\0\\0\\30\\6\"\n  \"\\1\\0\\0\\0\\0\\60H\\210\\210H\\60\\0\\0\\16\\21\\20\\20\\21\\16\\0\\0\\360\\10\\10\\10\\210\\360\\0\\0\\14\\21\\21\"\n  \"\\21\\10\\7\\0\\0\\0\\0@\\340@\\0\\0\\0\\0\\0\\10\\34\\10\\0\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\0\\0$\"\n  \"\\34\\0\\0\\0\\0\\0\\0\\200@ \\20\\0\\0\\0\\1\\2\\4\\10\\20\\0\\0@@@@@@\\0\\0\\2\\2\\2\"\n  \"\\2\\2\\2\\0\\0\\0\\20 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\"\\0\\0\\37\\0\\0\\370`\\200\\0\\0\\370\\0\\0\\37\\0\\0\\1\\6\\37\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\17\\20\\20\"\n  \"\\20\\20\\17\\0\\0\\370\\10\\10\\10\\10\\360\\0\\0\\37\\1\\1\\1\\1\\0\\0\\0\\360\\10\\10\\10\\10\\360\\0\\0\\17\\22\\22\"\n  \"\\24\\70O\\0\\0\\370\\10\\10\\10\\10\\360\\0\\0\\37\\1\\1\\3\\5\\30\\0\\0p\\210\\210\\10\\10\\60\\0\\0\\14\\20\\20\"\n  \"\\21\\21\\16\\0\\0\\10\\10\\10\\370\\10\\10\\10\\0\\0\\0\\0\\37\\0\\0\\0\\0\\370\\0\\0\\0\\0\\370\\0\\0\\17\\20\\20\"\n  \"\\20\\20\\17\\0\\0x\\200\\0\\0\\200x\\0\\0\\0\\3\\34\\34\\3\\0\\0\\0\\0\\370\\0\\0\\0\\370\\0\\0\\0\\17\\20\"\n  \"\\16\\20\\17\\0\\0\\30`\\200\\200`\\30\\0\\0\\30\\6\\1\\1\\6\\30\\0\\0\\0\\70\\300\\0\\300\\70\\0\\0\\0\\0\\0\"\n  \"\\37\\0\\0\\0\\0\\10\\10\\10\\310(\\30\\0\\0\\30\\26\\21\\20\\20\\20\\0\\0\\0\\0\\374\\4\\4\\4\\0\\0\\0\\0\\177\"\n  \"@@@\\0\\0\\14\\60\\300\\0\\0\\0\\0\\0\\0\\0\\1\\6\\30`\\0\\0\\0\\4\\4\\4\\374\\0\\0\\0\\0@@\"\n  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Share and enjoy.\n  Glyphs: 18/2576\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_7x14_1x2_n[436] U8X8_FONT_SECTION(\"u8x8_font_7x14_1x2_n\") = \n  \" :\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0@\\200\\340\\200@\\0\\0\\0\\4\\2\\17\\2\\4\\0\\0\\0\\0\\0\\340\\0\\0\\0\\0\\0\\1\\1\"\n  \"\\17\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0H\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\"\n  \"\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\70\\20\\0\\0\\0\\0\\0\\0\\300\\60\\14\\0\\0`\\30\\6\"\n  \"\\1\\0\\0\\0\\0\\340\\20\\10\\10\\20\\340\\0\\0\\7\\10\\20\\20\\10\\7\\0\\0\\0 \\20\\370\\0\\0\\0\\0\\0\\20\\20\"\n  \"\\37\\20\\20\\0\\0\\60\\10\\10\\10\\210p\\0\\0\\20\\30\\24\\22\\21\\20\\0\\0\\10\\10\\210\\310\\250\\30\\0\\0\\14\\20\\20\"\n  \"\\20\\20\\17\\0\\0\\0\\200`\\20\\370\\0\\0\\0\\6\\5\\4\\4\\37\\4\\0\\0\\370HHHH\\210\\0\\0\\14\\20\\20\"\n  \"\\20\\20\\17\\0\\0\\340\\20\\210\\210\\210\\0\\0\\0\\17\\21\\20\\20\\20\\17\\0\\0\\10\\10\\10\\210h\\30\\0\\0\\0\\30\\6\"\n  \"\\1\\0\\0\\0\\0\\60H\\210\\210H\\60\\0\\0\\16\\21\\20\\20\\21\\16\\0\\0\\360\\10\\10\\10\\210\\360\\0\\0\\14\\21\\21\"\n  \"\\21\\10\\7\\0\\0\\0\\0@\\340@\\0\\0\\0\\0\\0\\10\\34\\10\\0\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--14-130-75-75-C-70-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 191/1009\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_7x14B_1x2_f[3588] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_f\") = \n  \" \\377\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\370\\0\\0\\0\\0\\0\\0\\33\"\n  \"\\33\\0\\0\\0\\0\\0<<\\0<<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\370\\370\\370\\370@\\0\\0\\2\\37\\37\"\n  \"\\37\\37\\2\\0\\0`\\220\\370\\370\\20`\\0\\0\\14\\20\\77\\77\\21\\16\\0\\0\\60xH\\360\\70\\30\\0\\0\\30\\34\\17\"\n  \"\\22\\36\\14\\0\\0\\0p\\370\\210\\370p\\0\\0\\16\\37\\21\\16\\37\\23\\0\\0\\0\\0<<\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\360\\70\\14\\4\\0\\0\\0\\7\\37\\70`@\\0\\0\\0\\4\\14\\70\\360\\300\\0\\0\\0@`\"\n  \"\\70\\37\\7\\0\\0\\30\\240\\370\\370\\240\\30\\0\\0\\3\\0\\3\\3\\0\\3\\0\\0\\0\\0\\340\\340\\0\\0\\0\\0\\1\\1\\17\"\n  \"\\17\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0Hx\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\"\n  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\"\\22\\33\\13\\0\\0\\200\\320XX\\320\\200\\0\\0\\17\\37\\22\\22\\33\\13\\0\\0\\230\\330@@\\330\\230\\0\\0\\17\\37\\22\"\n  \"\\22\\33\\13\\0\\0\\0\\0\\10\\330\\320\\0\\0\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\0\\320\\330\\10\\0\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0\\0\\20\\330\\330\\20\\0\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\30\\30\\300\\300\\30\\30\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0\\64\\234\\230\\274\\344\\300\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\320\\310XP\\310\\200\\0\\0\\37\\37\\0\"\n  \"\\0\\37\\37\\0\\0\\200\\310XP\\300\\200\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\200\\300PX\\310\\200\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\17\\0\\0\\200\\320XX\\320\\200\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\220\\310XP\\310\\200\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\17\\0\\0\\230\\330@@\\330\\230\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\0\\0``\\0\\0\\0\\0\\3\\3\\33\"\n  \"\\33\\3\\3\\0\\0\\200\\300@\\300\\340\\220\\0\\0o\\37\\26\\21\\37\\17\\0\\0\\300\\310\\30\\20\\300\\300\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\37\\0\\0\\300\\300\\20\\30\\310\\300\\0\\0\\17\\37\\20\\20\\37\\37\\0\\0\\300\\320\\30\\30\\320\\300\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\37\\0\\0\\330\\330\\0\\0\\330\\330\\0\\0\\17\\37\\20\\20\\37\\37\\0\\0\\300\\300\\20\\30\\310\\300\\0\\0!c~\"\n  \">\\17\\1\\0\\0\\370\\370@@\\300\\200\\0\\0\\177\\177\\20\\20\\37\\17\\0\\0\\330\\330\\0\\0\\330\\330\\0\\0!c~\"\n  \">\\17\\1\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--14-130-75-75-C-70-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 95/1009\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_7x14B_1x2_r[1524] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_r\") = \n  \" ~\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\370\\0\\0\\0\\0\\0\\0\\33\"\n  \"\\33\\0\\0\\0\\0\\0<<\\0<<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\370\\370\\370\\370@\\0\\0\\2\\37\\37\"\n  \"\\37\\37\\2\\0\\0`\\220\\370\\370\\20`\\0\\0\\14\\20\\77\\77\\21\\16\\0\\0\\60xH\\360\\70\\30\\0\\0\\30\\34\\17\"\n  \"\\22\\36\\14\\0\\0\\0p\\370\\210\\370p\\0\\0\\16\\37\\21\\16\\37\\23\\0\\0\\0\\0<<\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\360\\70\\14\\4\\0\\0\\0\\7\\37\\70`@\\0\\0\\0\\4\\14\\70\\360\\300\\0\\0\\0@`\"\n  \"\\70\\37\\7\\0\\0\\30\\240\\370\\370\\240\\30\\0\\0\\3\\0\\3\\3\\0\\3\\0\\0\\0\\0\\340\\340\\0\\0\\0\\0\\1\\1\\17\"\n  \"\\17\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0Hx\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\"\n  \"\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\30\\30\\0\\0\\0\\0\\0\\0\\200\\340|\\34\\0\\0p|\\17\"\n  \"\\3\\0\\0\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0 \\60\\370\\370\\0\\0\\0\\0\\20\\20\\37\"\n  \"\\37\\20\\20\\0\\0\\60\\70\\10\\210\\370p\\0\\0\\30\\34\\26\\23\\21\\20\\0\\0\\60\\70\\210\\210\\370p\\0\\0\\14\\34\\20\"\n  \"\\20\\37\\17\\0\\0\\0\\200\\300\\360\\370\\0\\0\\0\\7\\7\\4\\37\\37\\4\\0\\0\\370\\370HH\\310\\210\\0\\0\\14\\34\\20\"\n  \"\\20\\37\\17\\0\\0\\340\\360\\230\\210\\270\\60\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\70\\70\\210\\350x\\30\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0p\\370\\210\\210\\370p\\0\\0\\16\\37\\21\\21\\37\\16\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\14\\35\\21\"\n  \"\\31\\17\\7\\0\\0\\0\\0``\\0\\0\\0\\0\\0\\0\\14\\14\\0\\0\\0\\0\\0\\0\\0``\\0\\0\\0\\0\\0$\"\n  \"<\\34\\0\\0\\0\\0\\200\\300`\\60\\20\\0\\0\\1\\3\\6\\14\\30\\20\\0\\0\\200\\200\\200\\200\\200\\200\\0\\0\\4\\4\\4\"\n  \"\\4\\4\\4\\0\\0\\20\\60`\\300\\200\\0\\0\\0\\20\\30\\14\\6\\3\\1\\0\\0\\60\\70\\210\\310x\\60\\0\\0\\0\\0\\33\"\n  \"\\33\\0\\0\\0\\0\\340\\360\\330\\350\\70\\360\\0\\0\\7\\17\\33\\27\\24\\27\\0\\0\\360\\370\\30\\30\\370\\360\\0\\0\\37\\37\\2\"\n  \"\\2\\37\\37\\0\\0\\370\\370\\210\\210\\370\\60\\0\\0\\37\\37\\20\\20\\37\\17\\0\\0\\360\\370\\10\\10\\70\\60\\0\\0\\17\\37\\20\"\n  \"\\20\\34\\14\\0\\0\\370\\370\\10\\30\\360\\340\\0\\0\\37\\37\\20\\30\\17\\7\\0\\0\\370\\370\\210\\210\\210\\10\\0\\0\\37\\37\\20\"\n  \"\\20\\20\\20\\0\\0\\370\\370\\210\\210\\210\\10\\0\\0\\37\\37\\0\\0\\0\\0\\0\\0\\360\\370\\10\\10\\70\\60\\0\\0\\17\\37\\20\"\n  \"\\21\\37\\17\\0\\0\\370\\370\\200\\200\\370\\370\\0\\0\\37\\37\\0\\0\\37\\37\\0\\0\\10\\10\\370\\370\\10\\10\\0\\0\\20\\20\\37\"\n  \"\\37\\20\\20\\0\\0\\0\\0\\0\\0\\370\\370\\0\\0\\14\\34\\20\\30\\17\\7\\0\\0\\370\\370\\340\\60\\30\\10\\0\\0\\37\\37\\3\"\n  \"\\7\\34\\30\\0\\0\\370\\370\\0\\0\\0\\0\\0\\0\\37\\37\\20\\20\\20\\20\\0\\0\\370\\360\\300\\300\\360\\370\\0\\0\\37\\37\\0\"\n  \"\\0\\37\\37\\0\\0\\370\\370\\340\\0\\370\\370\\0\\0\\37\\37\\0\\7\\37\\37\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\17\\0\\0\\370\\370\\10\\10\\370\\360\\0\\0\\37\\37\\1\\1\\1\\0\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\17\\37\\22\"\n  \"\\24\\77o\\0\\0\\370\\370\\210\\210\\370p\\0\\0\\37\\37\\0\\1\\37\\36\\0\\0\\60x\\310\\210\\70\\60\\0\\0\\14\\34\\21\"\n  \"\\23\\36\\14\\0\\0\\10\\10\\370\\370\\10\\10\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\370\\370\\0\\0\\370\\370\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\17\\0\\0\\370\\370\\0\\0\\370\\370\\0\\0\\3\\17\\34\\34\\17\\3\\0\\0\\370\\370\\0\\0\\370\\370\\0\\0\\17\\37\\17\"\n  \"\\17\\37\\17\\0\\0\\30x\\340\\340x\\30\\0\\0\\30\\36\\7\\7\\36\\30\\0\\0\\70\\370\\300\\300\\370\\70\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0\\10\\10\\210\\350x\\30\\0\\0\\30\\36\\27\\21\\20\\20\\0\\0\\0\\374\\374\\4\\4\\4\\0\\0\\0\\177\\177\"\n  \"@@@\\0\\0\\34|\\340\\200\\0\\0\\0\\0\\0\\0\\3\\17|p\\0\\0\\0\\4\\4\\4\\374\\374\\0\\0\\0@@\"\n  \"@\\177\\177\\0\\0\\10\\14\\6\\6\\14\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0```\"\n  \"```\\0\\0\\0\\4\\14\\30\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300@@\\300\\200\\0\\0\\14\\36\\22\"\n  \"\\21\\37\\37\\0\\0\\370\\370@@\\300\\200\\0\\0\\37\\37\\20\\20\\37\\17\\0\\0\\200\\300@@\\300\\200\\0\\0\\17\\37\\20\"\n  \"\\20\\30\\10\\0\\0\\200\\300@@\\370\\370\\0\\0\\17\\37\\20\\20\\37\\37\\0\\0\\200\\300@@\\300\\200\\0\\0\\17\\37\\22\"\n  \"\\22\\33\\13\\0\\0\\200\\200\\360\\370\\230\\220\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\200\\300@\\300\\200\\300\\0\\0\\63\\177T\"\n  \"Ws \\0\\0\\370\\370@@\\300\\200\\0\\0\\37\\37\\0\\0\\37\\37\\0\\0\\0\\0\\330\\330\\0\\0\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0\\0\\0\\0\\0\\330\\330\\0\\0\\0 `@\\177\\77\\0\\0\\370\\370\\0\\200\\300\\0\\0\\0\\37\\37\\3\"\n  \"\\7\\14\\30\\0\\0\\0\\0\\370\\370\\0\\0\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\300\\300\\200\\300\\300\\200\\0\\0\\37\\37\\17\"\n  \"\\17\\37\\37\\0\\0\\300\\300@@\\300\\200\\0\\0\\37\\37\\0\\0\\37\\37\\0\\0\\200\\300@@\\300\\200\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\17\\0\\0\\300\\300@@\\300\\200\\0\\0\\177\\177\\20\\20\\37\\17\\0\\0\\200\\300@@\\300\\300\\0\\0\\17\\37\\20\"\n  \"\\20\\177\\177\\0\\0\\300\\300@@\\300\\200\\0\\0\\37\\37\\0\\0\\1\\1\\0\\0\\200\\300@@\\300\\200\\0\\0\\10\\31\\23\"\n  \"\\26\\34\\10\\0\\0@@\\370\\370@@\\0\\0\\0\\0\\17\\37\\20\\20\\0\\0\\300\\300\\0\\0\\300\\300\\0\\0\\17\\37\\20\"\n  \"\\20\\37\\37\\0\\0\\300\\300\\0\\0\\300\\300\\0\\0\\1\\7\\36\\36\\7\\1\\0\\0\\300\\300\\0\\0\\300\\300\\0\\0\\17\\37\\17\"\n  \"\\17\\37\\17\\0\\0\\300\\300\\0\\0\\300\\300\\0\\0\\30\\35\\7\\7\\35\\30\\0\\0\\300\\300\\0\\0\\300\\300\\0\\0 cO\"\n  \"|\\77\\3\\0\\0@@@@\\300\\300\\0\\0\\30\\34\\26\\23\\21\\20\\0\\0\\0\\0\\370\\374\\4\\4\\0\\0\\0\\1\\77\"\n  \"~@@\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0\\0\\4\\4\\374\\370\\0\\0\\0\\0@@\"\n  \"~\\77\\1\\0\\0\\70\\14\\30\\30\\60\\34\\0\\0\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -Misc-Fixed-Bold-R-Normal--14-130-75-75-C-70-ISO10646-1\n  Copyright: Public domain font.  Share and enjoy.\n  Glyphs: 18/1009\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_7x14B_1x2_n[436] U8X8_FONT_SECTION(\"u8x8_font_7x14B_1x2_n\") = \n  \" :\\1\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\30\\240\\370\\370\\240\\30\\0\\0\\3\\0\\3\\3\\0\\3\\0\\0\\0\\0\\340\\340\\0\\0\\0\\0\\1\\1\\17\"\n  \"\\17\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0Hx\\70\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\"\n  \"\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\30\\30\\0\\0\\0\\0\\0\\0\\200\\340|\\34\\0\\0p|\\17\"\n  \"\\3\\0\\0\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0 \\60\\370\\370\\0\\0\\0\\0\\20\\20\\37\"\n  \"\\37\\20\\20\\0\\0\\60\\70\\10\\210\\370p\\0\\0\\30\\34\\26\\23\\21\\20\\0\\0\\60\\70\\210\\210\\370p\\0\\0\\14\\34\\20\"\n  \"\\20\\37\\17\\0\\0\\0\\200\\300\\360\\370\\0\\0\\0\\7\\7\\4\\37\\37\\4\\0\\0\\370\\370HH\\310\\210\\0\\0\\14\\34\\20\"\n  \"\\20\\37\\17\\0\\0\\340\\360\\230\\210\\270\\60\\0\\0\\17\\37\\20\\20\\37\\17\\0\\0\\70\\70\\210\\350x\\30\\0\\0\\0\\0\\37\"\n  \"\\37\\0\\0\\0\\0p\\370\\210\\210\\370p\\0\\0\\16\\37\\21\\21\\37\\16\\0\\0\\360\\370\\10\\10\\370\\360\\0\\0\\14\\35\\21\"\n  \"\\31\\17\\7\\0\\0\\0\\0``\\0\\0\\0\\0\\0\\0\\14\\14\\0\\0\";\n/*\n  Fontname: open_iconic_arrow_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 28/28\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_arrow_1x1[229] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_1x1\") = \n  \"@[\\1\\1\\0 `\\377` \\0\\0\\10\\34>\\10\\10\\10\\10\\10\\10\\10\\10\\10\\10>\\34\\10\\0\\4\\6\\377\"\n  \"\\6\\4\\0\\0<n\\317\\201\\201\\317n<<f\\303\\201\\347\\347f<<f\\347\\347\\201\\303f<<v\\363\\201\"\n  \"\\201\\363v<\\0\\0 \\177\\377 \\0\\0\\20\\30<\\30\\30\\30\\30\\30\\30\\30\\30\\30\\30<\\34\\10\\0\\0\\6\\377\"\n  \"\\376\\4\\0\\0\\0\\4\\14\\34\\34\\14\\4\\0\\0\\0\\0\\30<~\\0\\0\\0\\0~<\\30\\0\\0\\0\\0 \\60\\70\"\n  \"\\70\\60 \\0\\4\\16\\34\\70\\70\\34\\16\\4\\0\\0\\30<fB\\0\\0\\0B\\347~<\\30\\0\\0\\0\\60\\30\\14\"\n  \"\\14\\30\\60\\0\\200\\200\\210\\237\\237\\210\\200\\200\\1\\1\\21\\371\\371\\21\\1\\1&r\\42\\42\\42\\42'\\62\\20<\\26\\2\"\n  \"@h<\\10\\20\\373\\221\\201\\201\\211\\337\\10Bf<\\30$B\\347B\\60\\30\\14\\14\\14\\37\\16\\4\\177AAD\"\n  \"Ff\\6\\2\";\n/*\n  Fontname: open_iconic_check_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 5/5\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_check_1x1[45] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_1x1\") = \n  \"@D\\1\\1\\20\\70pp\\70\\34\\16\\4<~\\357\\357\\347\\363~<<~\\333\\347\\347\\333~<\\177AAI\"\n  \"IDr\\0B\\347~<<~\\347B\";\n/*\n  Fontname: open_iconic_embedded_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 17/17\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_embedded_1x1[140] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_1x1\") = \n  \"@P\\1\\1~BBBBB~\\30 \\60>\\277\\277>\\60 \\30~~\\347\\347~~\\30\\0\\0dg\"\n  \"=\\4\\0\\0\\0|~\\37\\37~|\\0\\300\\340p\\70\\30\\0\\2\\0\\20\\60<\\16\\70\\30\\20\\20\\300\\370\\376\\247\"\n  \"\\376\\360\\300\\0\\300\\340p>\\37\\30\\30\\10~~~~~~~\\30\\0$<\\333Z$\\0\\0<~\\377\\377\"\n  \"\\201\\201B<\\357\\357\\357\\357\\357\\257\\357\\0\\0\\12*\\277\\65\\24\\0\\0\\70D\\200\\217\\200D\\70\\0<B\\201\\201\"\n  \"\\201\\205\\6\\6\\2\\1\\11\\311\\311\\1\\2\";\n/*\n  Fontname: open_iconic_play_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 18/18\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_play_1x1[148] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_1x1\") = \n  \"@Q\\1\\1\\30\\0~\\0\\377\\0<\\0\\14\\34|\\36\\36\\0\\77\\0\\320\\330\\334\\336\\336\\334\\330\\320p~\\3\\1\"\n  \"\\1\\3~p\\0~~\\0\\0~~\\0\\0~<<\\30\\30\\0\\0\\0<~~~~<\\0\\0\\30<~\"\n  \"\\0\\30<~~<\\30\\0~<\\30\\0~~\\0\\30\\30<~\\0~<\\30\\30\\0~~\\0\\0~~~\"\n  \"~~~\\0\\0\\34\\260\\257\\357\\260\\34\\0\\340\\340\\376\\3\\3ss\\177<~\\377\\303\\347\\377~<<<~\\377\"\n  \"\\0Zf<\\0<<~\\377\\0\\30\\0\\0\\0<<~\\377\\0\";\n/*\n  Fontname: open_iconic_thing_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 19/19\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_thing_1x1[156] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_1x1\") = \n  \"@R\\1\\1\\10\\370\\234\\373\\373\\234\\370\\10\\334\\334\\337\\335\\335\\337\\334\\334zZzZzzzz\\300\\360\\370>\"\n  \"\\77\\31\\31\\16\\0\\360\\362\\361\\361\\376\\360\\0p\\310\\264\\242Q\\11\\6\\0\\374\\374\\77\\77\\374\\374\\60\\60\\200\\340\\360p\"\n  \"\\14\\16\\6\\1\\0x\\334\\276\\376\\374x\\0`~bBBb~`\\34\\42AAAb\\374\\300\\0\\377\\301\\301\"\n  \"\\301\\377\\0\\0\\0\\6\\6\\377\\14\\14\\0\\0T|~\\17~|T\\0p\\374\\77\\216\\340\\370\\360\\0\\0x~y\"\n  \"y~x\\0\\77\\241\\241\\341\\341\\241\\241\\77\\10\\11\\17\\177\\17\\11\\10\\0\\377\\301\\301\\301\\301\\301\\377\";\n/*\n  Fontname: open_iconic_weather_1x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 6/6\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_weather_1x1[52] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_1x1\") = \n  \"@E\\1\\1\\60x|~~~|pf\\367\\373\\375\\374\\374\\370\\340<~~\\360\\340``\\0\\30\\334\\16\\357\"\n  \"\\17\\337\\36\\70\\0\\10x<<x\\10\\0\\0B\\30<<\\30B\";\n/*\n  Fontname: open_iconic_arrow_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 28/28\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_arrow_2x2[900] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_2x2\") = \n  \"@[\\2\\2\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\4\\14\\34<\\177\\177<\\34\\14\\4\"\n  \"\\0\\0\\0\\0\\0\\300\\340\\360\\370\\374\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\0\\0\\1\\3\\7\\17\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\374\\370\\360\\340\\300\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0 \\60\\70<\\376\\376<\\70\\60 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\340\\370\\374\\376\\376\\377\\3\\3\\3\\3\\377\\376\\376\\374\\370\\340\\7\\37>|x\\360\\340\\300\\300\\340\\360x\"\n  \"|>\\37\\7\\340\\370|>\\36\\17\\7\\3\\77\\77\\77>><\\370\\340\\7\\37>|x\\360\\340\\300\\374\\374\\374|\"\n  \"|<\\37\\7\\340\\370<>>\\77\\77\\77\\3\\7\\17\\36>|\\370\\340\\7\\37<||\\374\\374\\374\\300\\340\\360x\"\n  \"|>\\37\\7\\340\\370|>\\36\\17\\7\\3\\3\\7\\17\\36>|\\370\\340\\7\\37\\77\\177\\177\\377\\300\\300\\300\\300\\377\\177\"\n  \"\\177\\77\\37\\7\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\4\\14\\34\\77\\177\\377\\177<\\34\"\n  \"\\14\\0\\0\\0\\0\\200\\300\\340\\360\\370\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\1\\3\\7\\17\\37\\37\\3\\3\\3\\3\\3\\3\"\n  \"\\3\\3\\3\\3\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\370\\370\\360\\340\\300\\200\\3\\3\\3\\3\\3\\3\\3\\3\\3\\3\\37\\17\"\n  \"\\7\\3\\1\\0\\0\\0\\0\\60\\70<\\376\\377\\376\\374\\70\\60 \\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\20\\60p\\360\\360\\360\\360\\360\\360\\360\\360p\\60\\20\\0\\0\\0\\0\\0\\0\\1\\3\\7\\7\\3\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\376\\374\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\177\\77\\37\\17\\7\\3\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\340\\300\\200\\0\\0\\0\\0\\0\\0\\10\\14\\16\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\16\\14\\10\\0\\0\\60x\\370\\360\\340\\300\\200\\200\\300\\340\\360\\370x\\60\\0\\0\\0\\0\\0\\1\\3\\7\\17\\17\\7\\3\\1\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370|>\\36\\14\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37>|x\\60\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\14\\36>|\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\\0\\0\\60x|>\\37\\17\\7\\3\\1\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\370\\360\\340\\300\\200\\0\\0\\0\\0\\6\\17\\17\\7\\3\\1\\0\\0\\1\\3\\7\"\n  \"\\17\\17\\6\\0\\0\\0\\0@\\300\\300\\377\\377\\377\\377\\300\\300@\\0\\0\\0\\300\\300\\300\\300\\300\\301\\303\\307\\307\\303\\301\\300\"\n  \"\\300\\300\\300\\300\\3\\3\\3\\3\\3\\203\\303\\343\\343\\303\\203\\3\\3\\3\\3\\3\\0\\0\\0\\2\\3\\3\\377\\377\\377\\377\\3\\3\"\n  \"\\2\\0\\0\\0\\70<\\14\\14\\14\\14\\14\\14\\14\\14\\14\\14\\77\\36\\14\\0\\0\\14\\36\\77\\14\\14\\14\\14\\14\\14\\14\\14\"\n  \"\\14\\14\\17\\7\\0\\0\\300\\360\\70\\30\\14\\14\\0\\0\\200\\300\\340\\340\\300\\200\\1\\3\\7\\7\\3\\1\\0\\0\\60\\60\\30\\34\"\n  \"\\17\\3\\0\\0\\0\\0\\317\\317\\3\\3\\3\\3\\3\\3C\\303\\377\\377\\300@\\2\\3\\377\\377\\303\\302\\300\\300\\300\\300\\300\\300\"\n  \"\\363\\363\\0\\0\\14\\14\\34\\70p\\340\\300\\340p\\70\\34\\14\\77\\36\\14\\0\\60\\60\\70\\34\\16\\7\\3\\3\\17\\34\\70\\60\"\n  \"\\374x\\60\\0\\0\\200\\300\\300\\340\\340\\360\\360\\360\\360\\377\\376\\374\\370p \\14\\7\\3\\1\\1\\0\\0\\0\\0\\0\\7\\3\"\n  \"\\1\\0\\0\\0\\377\\377\\3\\3\\3c\\60\\70\\70<<<~<\\34\\10\\77\\77\\60\\60\\60\\60\\60\\60\\60\\60<<\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: open_iconic_check_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 5/5\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_check_2x2[164] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_2x2\") = \n  \"@D\\2\\2\\0\\200\\300\\200\\0\\0\\0\\200\\300\\340\\360\\370\\374x\\60\\0\\1\\3\\7\\17\\37>\\77\\37\\17\\7\\3\\1\"\n  \"\\0\\0\\0\\0\\340\\370\\374\\376~\\177\\377\\377\\177\\77\\37\\216\\316\\374\\370\\340\\7\\37\\77\\177~\\374\\370\\370\\374\\376\\377\\177\"\n  \"\\177\\77\\37\\7\\340\\370\\374\\376\\316\\217\\37\\77\\77\\37\\217\\316\\376\\374\\370\\340\\7\\37\\77\\177s\\361\\370\\374\\374\\370\\361s\"\n  \"\\177\\77\\37\\7\\377\\377\\3\\3\\3c\\343\\303\\303\\343q\\70\\34\\216\\6\\0\\77\\77\\60\\60\\60\\60\\60\\61\\61\\60\\60\\60\"\n  \"\\77\\77\\0\\0\\4\\16\\37>|\\370\\360\\340\\360\\370\\374~\\77\\36\\14\\0\\20\\70|~\\77\\37\\17\\7\\7\\17\\37>\"\n  \"|x\\60\";\n/*\n  Fontname: open_iconic_embedded_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 17/17\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_embedded_2x2[548] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_2x2\") = \n  \"@P\\2\\2\\374\\374\\14\\14\\14\\14\\14\\14\\14\\14\\14\\14\\374\\374\\300\\300\\77\\77\\60\\60\\60\\60\\60\\60\\60\\60\\60\\60\"\n  \"\\77\\77\\3\\3\\0\\0\\0\\300\\374\\376\\377\\377\\377\\377\\376\\374\\300\\0\\0\\0\\14\\16\\17\\17\\17\\17O\\317\\317O\\17\\17\"\n  \"\\17\\17\\16\\14\\200\\300\\334\\374\\374\\70\\36\\37\\37\\36\\70\\374\\374\\334\\300\\200\\1\\3;\\77\\77\\34x\\370\\370x\\34\\77\"\n  \"\\77;\\3\\1\\0\\0\\0\\0 \\70>\\77\\367\\361p\\20\\0\\0\\0\\0\\0\\0\\0\\0\\14||\\77\\37\\15\\4\\0\"\n  \"\\0\\0\\0\\0\\0 \\360\\370\\370\\374\\376\\377\\377\\376\\374\\370\\370\\360 \\0\\0\\0\\77\\77\\77\\77\\3\\3\\3\\3\\77\\77\"\n  \"\\77\\77\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\340\\300\\200\\6\\16\\34\\30\\0\\360\\370\\374\\376\\177\\77\\37\\17\\7\\3\\1\\0\"\n  \"\\0\\0\\0\\0\\200\\200\\200\\200\\200\\370~\\370\\300\\200\\340\\340\\200\\200\\200\\200\\1\\1\\3\\37\\37\\3\\0\\3\\37\\37\\3\\1\"\n  \"\\1\\1\\1\\1\\0\\0\\0\\300\\370\\376\\77\\77\\376\\360\\300\\0\\0\\0\\0\\0\\340\\374\\377\\377\\377\\377\\314\\314\\377\\377\\377\\377\"\n  \"\\370\\340\\0\\0\\0\\0\\0\\0\\0\\0\\370\\376\\376\\377\\303\\300\\300\\300\\300``\\220\\230|>\\37\\17\\7\\3\\3\\3\\3\"\n  \"\\3\\1\\1\\0\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\300\\300\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\"\n  \"\\77\\77\\3\\3\\0\\0\\0\\60`\\377\\377\\206\\314xx\\60\\0\\0\\0\\0\\0\\0\\0\\14\\6\\377\\377a\\63\\36\\36\\14\"\n  \"\\0\\0\\0\\0\\340\\370\\374\\376\\376\\377\\377\\377\\3\\3\\7\\6\\16<\\370\\340\\7\\37\\77\\177\\177\\377\\377\\377\\300\\300\\340`\"\n  \"p<\\37\\7\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\314\\314\"\n  \"\\374\\374\\0\\0\\0\\0\\230\\230\\314\\314ff\\63\\63\\230\\230\\0\\0\\0\\0\\0\\0\\1\\1\\14\\314\\316\\316\\317\\17\\1\\1\"\n  \"\\0\\0\\0\\0\\300\\340p\\30\\0\\0\\377\\377\\0\\0\\30p\\340\\300\\0\\0\\17\\37\\70`\\340\\300\\300\\300\\300\\340`\\70\"\n  \"\\37\\17\\0\\0\\340\\370<\\16\\6\\7\\3\\3\\3\\3'\\66><>>\\7\\37<p`\\340\\300\\300\\300\\300\\340`\"\n  \"`\\0\\0\\0\\4\\16\\6\\206\\203\\303\\303\\303\\303\\303\\203\\206\\6\\6\\4\\0\\0\\0\\0\\0\\1\\0\\360\\360\\360\\0\\1\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: open_iconic_play_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 18/18\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_play_2x2[580] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_2x2\") = \n  \"@Q\\2\\2\\300\\300\\0\\0\\374\\374\\0\\0\\377\\377\\0\\0\\360\\360\\0\\0\\3\\3\\0\\0\\77\\77\\0\\0\\377\\377\\0\\0\"\n  \"\\17\\17\\0\\0\\360\\360\\360\\360\\360\\370\\370\\374\\374\\376\\0\\0\\377\\377\\0\\0\\0\\0\\1\\17\\77\\61\\1\\3\\3\\7\\0\\0\"\n  \"\\17\\17\\0\\0\\0\\0\\200\\300\\360\\370\\374\\376\\376\\374\\370\\360\\300\\200\\0\\0\\362\\363\\363\\363\\363\\363\\363\\363\\363\\363\\363\\363\"\n  \"\\363\\363\\363\\362\\0\\0\\360\\374\\16\\6\\3\\3\\3\\3\\6\\16\\374\\360\\0\\0\\77\\77\\77\\77\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\77\\77\\77\\77\\0\\0\\374\\374\\374\\374\\0\\0\\0\\0\\374\\374\\374\\374\\0\\0\\0\\0\\77\\77\\77\\77\\0\\0\\0\\0\\77\\77\"\n  \"\\77\\77\\0\\0\\0\\0\\374\\370\\370\\360\\360\\340\\340\\300\\300\\200\\200\\0\\0\\0\\0\\0\\77\\37\\37\\17\\17\\7\\7\\3\\3\\1\"\n  \"\\1\\0\\0\\0\\0\\0\\300\\360\\370\\370\\374\\374\\374\\374\\370\\370\\360\\300\\0\\0\\0\\0\\3\\17\\37\\37\\77\\77\\77\\77\\37\\37\"\n  \"\\17\\3\\0\\0\\0\\200\\300\\340\\340\\360\\370\\374\\0\\200\\300\\340\\340\\360\\370\\374\\0\\1\\3\\7\\7\\17\\37\\77\\0\\1\\3\\7\"\n  \"\\7\\17\\37\\77\\374\\370\\360\\340\\340\\300\\200\\0\\374\\370\\360\\340\\340\\300\\200\\0\\77\\37\\17\\7\\7\\3\\1\\0\\77\\37\\17\\7\"\n  \"\\7\\3\\1\\0\\374\\374\\374\\374\\0\\200\\200\\300\\340\\340\\360\\360\\370\\374\\0\\0\\77\\77\\77\\77\\0\\1\\1\\3\\7\\7\\17\\17\"\n  \"\\37\\77\\0\\0\\374\\370\\360\\360\\340\\340\\300\\200\\200\\0\\374\\374\\374\\374\\0\\0\\77\\37\\17\\17\\7\\7\\3\\1\\1\\0\\77\\77\"\n  \"\\77\\77\\0\\0\\0\\0\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\374\\0\\0\\0\\0\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\"\n  \"\\77\\77\\0\\0\\0\\0\\360\\360\\0\\0~\\377\\377~\\0\\0\\360\\360\\0\\0\\0\\0\\0\\3\\207\\306\\314\\374\\374\\314\\306\\207\"\n  \"\\3\\0\\0\\0\\0\\0\\0\\0\\374\\376\\36\\36\\16\\17\\17\\17\\17\\17\\377\\377x\\374\\374\\374\\377\\177\\0\\0\\0\\0\\36\\77\"\n  \"\\77\\77\\77\\37\\340\\370\\374\\376\\376\\377\\17\\37\\77\\77\\177\\376\\376\\374\\370\\340\\7\\37\\77\\177\\177\\377\\360\\370\\374\\374\\376\\177\"\n  \"\\177\\77\\37\\7\\360\\360\\360\\360\\370\\374\\377\\377\\0\\0\\314\\214\\30\\70\\360\\300\\17\\17\\17\\17\\37\\77\\377\\377\\0\\0\\63\\61\"\n  \"\\30\\34\\17\\3\\0\\0\\360\\360\\360\\360\\370\\374\\377\\377\\0\\0\\300\\200\\0\\0\\0\\0\\17\\17\\17\\17\\37\\77\\377\\377\\0\\0\"\n  \"\\3\\1\\0\\0\\0\\0\\0\\0\\360\\360\\360\\360\\370\\374\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\17\\17\\17\\17\\37\\77\\377\\377\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: open_iconic_thing_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 19/19\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_thing_2x2[612] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_thing_2x2\") = \n  \"@R\\2\\2\\300\\300\\300\\340\\360\\374\\316\\307\\307\\316\\374\\360\\340\\300\\300\\300\\0\\0\\377\\377\\303\\303\\377\\377\\377\\377\\303\\303\"\n  \"\\377\\377\\0\\0\\360\\360\\360\\360\\376\\377\\363\\363\\363\\363\\377\\376\\360\\360\\360\\360\\363\\363\\363\\363\\363\\363\\363\\363\\363\\363\\363\\363\"\n  \"\\363\\363\\363\\363\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\314\\77\\77\\63\\63\\77\\77\\63\\63\\77\\77\\77\\77\"\n  \"\\77\\77\\77\\77\\0\\0\\0\\0\\200\\300\\370\\376\\376\\377\\347\\303\\303\\346\\376x\\360\\370\\374\\377\\377\\377\\17\\17\\17\\17\\3\\3\"\n  \"\\3\\1\\1\\0\\0\\0\\0\\0\\14\\16\\7\\3\\3\\7\\376\\374\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\0\\0\\0\\200\\300\\340p\\270\\234\\16\\7\\203\\303\\347~<\\0\\0\\37\\77q\\340\\317\\317\\315\\356w;\\31\\0\"\n  \"\\0\\0\\0\\0\\360\\360\\360\\360\\366\\377\\377\\366\\360\\360\\360\\360\\0\\0\\0\\0\\377\\377\\377\\377\\237\\17\\17\\237\\377\\377\\377\\377\"\n  \"\\6\\17\\17\\6\\0\\0\\0\\0\\0\\0\\0``\\360\\370|<\\36\\7\\2\\0\\300\\360\\376\\377\\177\\77\\36\\0\\1\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\300\\360\\370\\374\\377\\376\\374\\370\\360\\300\\0\\0\\0\\0\\0\\37\\77s\\303\\317\\317\\337\\377\\377\\177\"\n  \"\\77\\37\\0\\0\\0\\0\\374\\374\\14\\14\\14\\14\\14\\14\\14\\14\\374\\374\\0\\0<<\\77\\77<<\\60\\60\\60\\60<<\"\n  \"\\77\\77<<\\360\\370\\34\\6\\7\\3\\3\\3\\3\\7\\6\\34\\370\\360\\0\\0\\3\\7\\16\\30\\70\\60\\60\\60\\60\\70\\30>\"\n  \"\\177\\371\\360`\\0\\0\\377\\377\\3\\3\\3\\3\\3\\3\\377\\377\\0\\0\\0\\0\\0\\0\\377\\377\\360\\360\\220\\220\\360\\360\\377\\377\"\n  \"\\0\\0\\0\\0\\0\\30<<<<\\377\\377\\360\\360\\360\\360`\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\60\\60`\\340\\374\\376\\377\\377\\377\\374\\340`\\60\\60\\0\\0\\63\\63\\37\\77\\177\\177\\0\\0\\177\\177\\77\\37\"\n  \"\\63\\63\\0\\0\\0\\200\\340\\360\\377\\376\\374\\360\\0\\0\\300\\200\\0\\0\\0\\0\\17\\77\\177\\377\\17\\7\\301\\340\\370\\374\\377\\377\"\n  \"\\377|\\0\\0\\0\\0\\300\\300\\374\\376\\307\\303\\303\\307\\376\\374\\300\\300\\0\\0\\0\\0\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\"\n  \"\\77\\77\\0\\0\\377\\377\\3\\3\\3\\3\\3\\3\\3\\3\\3\\3\\3\\3\\377\\377\\17\\17\\214\\314\\314\\314\\374\\374\\374\\374\\314\\314\"\n  \"\\314\\214\\17\\17\\200\\300\\303\\303\\377\\377\\377\\377\\377\\377\\303\\303\\300\\200\\0\\0\\0\\0\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\377\\377\\3\\3\\3\\3\\3\\3\\3\\3\\3\\3\\377\\377\\0\\0\\377\\377\\360\\360\\360\\360\\220\\220\\360\\360\\360\\360\"\n  \"\\377\\377\\0\";\n/*\n  Fontname: open_iconic_weather_2x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 6/6\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_weather_2x2[197] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_2x2\") = \n  \"@E\\2\\2\\0\\200\\300\\300\\340\\370\\370\\374\\374\\374\\374\\370\\370\\340\\0\\0\\17\\37\\77\\77\\77\\77\\77\\77\\77\\77\\77\\77\"\n  \"\\77\\77\\77\\36x~>\\37\\217\\347\\343\\362\\362\\360\\360\\340\\340\\200\\0\\0<~\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\374x\\340\\370\\374\\376\\377\\340\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\17\\37\\77\\177\\177\\177\\377\\376|||\"\n  \"\\70\\30\\14\\0\\300\\340\\360\\360\\370\\376\\376\\377\\377\\377\\377\\376\\376\\370\\300\\200\\3\\3\\363\\363\\1\\0\\374\\374\\0\\1\\363\\363\"\n  \"\\3\\7\\17\\7\\0@\\300\\300\\300\\300\\340\\374\\374\\340\\300\\300\\300\\300@\\0\\0\\0\\0\\1s\\77\\37\\17\\17\\37\\77s\"\n  \"\\1\\0\\0\\0\\200\\200\\14\\14\\300\\340\\360\\363\\363\\360\\340\\300\\14\\14\\200\\200\\1\\1\\60\\60\\3\\7\\17\\317\\317\\17\\7\\3\"\n  \"\\60\\60\\1\\1\";\n/*\n  Fontname: open_iconic_arrow_4x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 28/28\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_arrow_4x4[3588] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_4x4\") = \n  \"@[\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\20\\60p\\360\\360\\360\\360\\360\\377\\377\\377\\377\\360\\360\\360\\360\\360p\\60\\20\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\7\\17\\37\\77\\177\\377\\77\\37\\17\\7\\1\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0@`\\360\\370\\374\\376\\376\\377\\377\\377\\377\\377\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\"\n  \"\\360\\360\\360\\360\\0\\0\\0\\1\\3\\7\\7\\17\\37\\77\\177\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\360\\340\\300\\200\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\377\\377\\377\\377\\377\\376\\376\\374\"\n  \"\\370\\360` \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\177\\77\\37\\17\\7\\7\\3\"\n  \"\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\340\\360\\370\\374\\377\\376\\374\\370\\360\\340\\200\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\10\\14\\16\\17\\17\\17\\17\\17\\377\\377\\377\\377\\17\\17\\17\\17\\17\\16\\14\\10\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\17\\17\\17\\17\\17\\17\\17\\17\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\376\\374\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\376\\374\\370\\360\\360\\370\\374\\376\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\177\\77\\37\\17\\377\\377\\377\\377\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\177\\77\\37\\17\\7\\3\\1\\0\\0\\0\\0\\0\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\376\\374\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\376\\374\\370\\360\\377\\377\\377\\377\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\377\\377\\377\\377\\17\\37\\77\\177\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\377\\377\\377\\377\\360\\370\\374\\376\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\177\\77\\37\\17\\17\\37\\77\\177\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\177\\77\\37\\17\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\360\\360\\360\\360\\360\\360\\360\\360\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\60p\\360\\360\\360\\360\\377\\377\\377\\377\\377\\377\\377\\377\\360\\360\\360\\360\\360p\\60\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\\377\\177\\77\\37\\17\\7\\3\\1\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\377\\377\\377\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\"\n  \"\\360\\360\\360\\360\\1\\3\\7\\17\\37\\77\\177\\377\\377\\377\\377\\377\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\17\\17\\17\\17\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\340\\300\\200\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\377\\377\\377\\377\\377\\376\\374\\370\"\n  \"\\360\\340\\300\\200\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\377\\377\\377\\377\\177\\77\\37\\17\"\n  \"\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\3\\1\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\376\\374\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\14\\16\\17\\17\\17\\17\\17\\377\\377\\377\\377\\377\\377\\377\\377\\17\\17\\17\\17\\16\\14\\10\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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\"\\370\\360`\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\376\\370\\360\\360\\370\\374~\\77\\17\\7\\3\\1\\0\\0\\17\\7\\3\\1\"\n  \"\\1\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\374~\\77\\37\\17\\7\\17\\37\\177\\374\\370\\360\\340\\300\\200\\0\\360\\340\\300\\200\"\n  \"\\200\\0\\0\\0\\17\\17\\17\\17\\17\\17\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\17\\17\\377\\177\\77\\37\"\n  \"\\37\\17\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\376\\374\\370\\360\\340\\300\\200\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\300\\340\\360\\370\\370\\374\\374\\376\\376\\376\\376\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\177>\\34\\10\\300\\374\\77\\37\\17\\7\\7\\3\\1\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\177\\77\\37\\17\\7\\3\\1\\0\"\n  \"\\0\\0\\0\\0\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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\"\\200\\0\\0\\0\\0\\0\\200\\300\\340\\360\\340\\300\\200\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\377\\377\\377\\377\\177\\77\"\n  \"\\37\\17\\6\\0\\2\\7\\17\\37\\77\\177\\377\\377\\377\\377\\376\\374\\376\\377\\377\\377\\377\\377\\177\\77\\37\\17\\7\\3\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\37\\17\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\377\\377\\377\\377\\377\\377\\377\\377\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\377\\377\\377\\377\\177\\77\\77\\177\\377\\377\\377\\377\\177\\77\\37\\17\\7\\203\\301\\340\\360\\371\\377\\377\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\377\\377\\377\\377\\376\\374\\370\\360\\340\\301\\301\\340\\360\\370\\374\\376\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\377\\377\\377\\377\\377\\377\\377\\377\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\374\\376\\376\\376\\377\\377\\377\\377\\377\\377\\377\\377\\376\\376\\376\\374\\374\\370\\360\\340\"\n  \"\\300\\200\\0\\0\\360\\376\\377\\377\\377\\377\\377\\377\\371\\360\\340\\301\\203\\7\\17\\37\\37\\17\\7\\203\\301\\340\\360\\371\\377\\377\\377\\377\"\n  \"\\377\\377\\376\\360\\17\\177\\377\\377\\377\\377\\377\\377\\237\\17\\7\\203\\301\\340\\360\\370\\370\\360\\340\\301\\203\\7\\17\\237\\377\\377\\377\\377\"\n  \"\\377\\377\\177\\17\\0\\0\\1\\3\\7\\17\\37\\77\\77\\177\\177\\177\\377\\377\\377\\377\\377\\377\\377\\377\\177\\177\\177\\77\\77\\37\\17\\7\"\n  \"\\3\\1\\0\\0\\377\\377\\377\\377\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\7\\3\\201\\300\\340\\360\\370\\374\\376\"\n  \"~<\\30\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\30<~\\376\\374\\370\\360\\360\\370\\374\\376\\177\\77\\37\\17\\7\\3\\201\\300\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\7\\3\\1\\0\\0\\0\\0\\0\\376\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\0\\0\\0\\0 p\\370\\374\\376\\377\\376\\374\\370\\360\\340\\300\\200\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\376\\374\"\n  \"\\370\\360`\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\\377\\377\\377\\377\\376\\374\\376\\377\\377\\377\\377\\377\\177\\77\\37\\17\\7\\3\"\n  \"\\1\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\377\\377\\377\\377\\177\\77\\77\\177\\377\\377\\377\\377\\376\\374\\370\\360\\340\\300\"\n  \"\\200\\0\\0\\0\\2\\7\\17\\37\\77\\177\\177\\77\\37\\17\\7\\3\\1\\0\\0\\0\\0\\0\\0\\1\\3\\7\\17\\37\\77\\177\\177\\77\"\n  \"\\37\\17\\6\";\n/*\n  Fontname: open_iconic_embedded_4x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 17/17\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_embedded_4x4[2180] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_embedded_4x4\") = \n  \"@P\\4\\4\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\\360\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\360\\360\\360\\360\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\370\\374\\376\\376\\377\\377\\377\\377\\377\\377\\376\\376\\374\\370\\340\\0\\0\\0\\0\"\n  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https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 18/18\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_play_4x4[2308] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_play_4x4\") = \n  \"@Q\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\17\\17\\17\\17\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\17\\17\\17\\17\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\300\\300\\340\\340\\360\\360\\370\\370\\374\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\\377\\377\\377\\377\"\n  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\"\\377\\377~<\\377\\377\\377\\377\\377\\377\\377\\377\\303\\1\\0\\0\\0\\0\\1\\303\\377\\377\\377\\377\\377\\377\\377\\377\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\300\\340\\340\\360\\370\\374\\374\"\n  \"~\\77\\16\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\30\\34>~\\377\\377\\377\\377\\177\\77\\37\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\360\\374\\376\\377\\377\\377\\377\\377\\376\\374\\370\\0\\0\\0\\3\\3\\1\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0@@\\340\\370\\374\\377\\377\\377\\177\\177\\177\\77\\37\\17\\7\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\340\\360\\370\\376\\376\\376\\374\\370\\360\\340\\300\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\360\\370\\376\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\376\\370\\360\\300\\0\"\n  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\"\\0\\0\\0\\0\\300\\340\\360\\360\\360\\360\\360\\360\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\360\\360\\360\\360\\360\\360\\340\\300\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\177\\177\\37\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\347\\303\\303\\347\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\177\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: open_iconic_weather_4x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 6/6\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_weather_4x4[772] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_weather_4x4\") = \n  \"@E\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\300\\340\\340\\360\\360\\360\\360\\360\\360\\340\\340\\300\\300\\200\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\200\\300\\340\\340\\360\\360\\360\\374\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\376\\370\"\n  \"\\0\\0\\0\\0~\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\"\n  \"\\377\\376\\374\\360\\0\\1\\3\\7\\7\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\"\n  \"\\7\\7\\3\\0\\200\\340\\370\\374\\374\\376\\376\\377\\377\\177\\77\\77\\37\\36\\16\\14\\14\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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U8X8_FONT_SECTION(\"u8x8_font_open_iconic_arrow_8x8\") = \n  \"@[\\10\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\"\n  \"\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Fontname: open_iconic_check_8x\n  Copyright: https://github.com/iconic/open-iconic, SIL OPEN FONT LICENSE\n  Glyphs: 5/5\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_open_iconic_check_8x8[2564] U8X8_FONT_SECTION(\"u8x8_font_open_iconic_check_8x8\") = \n  \"@D\\10\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\376\\374\\370\\360\\340\\300\\200\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340\\360\\370\\374\\376\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\377\\177\"\n  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\"\\1\\0\\0\\0\\6\\7\\7\\7\\7\\7\\7\\7\\7\\7\\7\\7\\7\\7\\0\\0\\60<>\\16\\7\\7\\7\\7\\7\\207\\216\\376\"\n  \"\\374p\\0\\0`\\340\\340\\200\\0\\0\\7\\7\\7\\17\\217\\375\\370p\\0\\0\\0\\1\\3\\3\\7\\7\\7\\7\\7\\7\\3\\3\"\n  \"\\1\\0\\0\\0\\0\\200\\300\\340\\360x<\\36\\377\\377\\377\\0\\0\\0\\0\\0\\37\\37\\37\\35\\34\\34\\34\\34\\377\\377\\377\\34\"\n  \"\\34\\34\\0\\0\\0\\0\\0\\0\\0\\7\\7\\7\\7\\7\\7\\7\\7\\7\\0\\0\\377\\377\\377\\347\\347\\347\\347\\347\\347\\347\\307\\307\"\n  \"\\207\\7\\0\\0`\\340\\340\\200\\0\\0\\0\\0\\0\\0\\201\\377\\377~\\0\\0\\0\\1\\3\\3\\7\\7\\7\\7\\7\\7\\3\\3\"\n  \"\\1\\0\\0\\0\\360\\374\\376\\356\\347\\347\\347\\347\\347\\347\\307\\300\\200\\0\\0\\0\\177\\377\\377\\200\\0\\0\\0\\0\\0\\0\\201\\377\"\n  \"\\377~\\0\\0\\0\\1\\3\\3\\7\\7\\7\\7\\7\\7\\3\\3\\1\\0\\0\\0\\7\\7\\7\\7\\7\\7\\7\\7\\7\\207\\307\\377\"\n  \"\\377\\177\\0\\0\\0\\0\\0\\0\\0\\370\\374\\376\\17\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\7\\7\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0p\\374\\376\\216\\207\\7\\7\\7\\7\\207\\216\\376\\374p\\0\\0p\\370\\375\\217\\17\\7\\7\\7\\7\\17\\217\\375\"\n  \"\\370p\\0\\0\\0\\1\\3\\3\\7\\7\\7\\7\\7\\7\\3\\3\\1\\0\\0\\0\\360\\374\\376\\16\\7\\7\\7\\7\\7\\7\\16\\376\"\n  \"\\374\\360\\0\\0\\3\\17\\37\\34\\70\\70\\70\\70\\70\\70\\270\\377\\377\\177\\0\\0\\0\\0\\0\\7\\7\\7\\7\\7\\7\\7\\3\\3\"\n  \"\\1\\0\\0\\0\\0\\0\\0\\0\\300\\340\\340\\340\\300\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\301\\343\\343\\343\\301\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\3\\3\\1\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Artos Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 96/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artossans8_r[772] U8X8_FONT_SECTION(\"u8x8_font_artossans8_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\3\\0\\0\\0\\3\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0B%\\22\\10$R!\\0\\0 VIIU\\42P\\0\\0\\0\\0\"\n  \"\\3\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\0>AAA>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22\\21\\177\\20\\0\\0\\0'EEE\\71\\0\\0\\0>III\\62\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0&III>\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0\\0 \"\n  \"\\22\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34`\\30\\26\\21\\26\\30`\\0\\177IIIII\\66\\0>AAA\"\n  \"AA\\42\\0\\177AAAAA>\\0\\177IIIIAA\\0\\177\\11\\11\\11\\11\\1\\1\\0>AAA\"\n  \"II:\\0\\177\\10\\10\\10\\10\\10\\177\\0\\0AA\\177AA\\0\\0 @@@@@\\77\\0\\177\\10\\10\\10\"\n  \"\\24\\42A\\0\\177@@@@@@\\0\\177\\2\\4\\10\\4\\2\\177\\0\\177\\2\\4\\10\\20 \\177\\0>AAA\"\n  \"AA>\\0\\177\\21\\21\\21\\21\\21\\16\\0>AAAaA\\276\\0\\177\\11\\11\\11\\11\\31f\\0&III\"\n  \"II\\62\\0\\1\\1\\1\\177\\1\\1\\1\\0\\77@@@@@\\77\\0\\17\\20 @ \\20\\17\\0\\37` \\34\"\n  \" `\\37\\0A\\42\\24\\10\\24\\42A\\0\\3\\4\\10p\\10\\4\\3\\0AaQIECA\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\4\\2\\1\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\1\\2\\0\\0\\0\\0 TTTTx\\0\\0\\177DDDD\\70\\0\\0\\70DD\"\n  \"DD(\\0\\0\\70DDDD\\177\\0\\0\\70TTTTH\\0\\0\\0\\4~\\5\\1\\0\\0\\0\\30\\244\\244\"\n  \"\\244\\244|\\0\\0\\177\\4\\4\\4\\4x\\0\\0\\0D}@\\0\\0\\0\\0@\\200\\200\\204}\\0\\0\\0\\177\\20\\20\"\n  \"\\20(D\\0\\0\\0\\1\\177\\0\\0\\0\\0|\\4\\4|\\4\\4x\\0\\0|\\4\\4\\4\\4x\\0\\0\\70DD\"\n  \"DD\\70\\0\\0\\374DDDD\\70\\0\\0\\70DDDD\\374\\0\\0|\\10\\4\\4\\4\\4\\0\\0HTT\"\n  \"TT$\\0\\0\\0\\4\\77D@\\0\\0\\0<@@@@|\\0\\0\\34 @@ \\34\\0\\0<@@\"\n  \"\\70@@<\\0D(\\20(D\\0\\0\\0\\34\\240\\240\\240\\240|\\0\\0DdTLD\\0\\0\\0\\0\\10\\66\"\n  \"A\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0\\0A\\66\\10\\0\\0\\10\\4\\4\\10\\20\\20\\10\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Artos Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artossans8_n[220] U8X8_FONT_SECTION(\"u8x8_font_artossans8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\24\\10>\\10\\24\\0\\0\\20\\20|\"\n  \"\\20\\20\\0\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\200\\0\\0\\0\\0\\200@ \\20\"\n  \"\\10\\4\\2\\0\\0|\\202\\202\\202|\\0\\0\\0\\200\\204\\376\\200\\200\\0\\0\\0\\304\\242\\222\\222\\214\\0\\0\\0D\\202\\222\"\n  \"\\222l\\0\\0\\0\\70$\\42\\376 \\0\\0\\0N\\212\\212\\212r\\0\\0\\0|\\222\\222\\222d\\0\\0\\0\\2\\2\\362\"\n  \"\\12\\6\\0\\0\\0l\\222\\222\\222l\\0\\0\\0L\\222\\222\\222|\\0\\0\\0\\0\\0$\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Artos Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artossans8_u[517] U8X8_FONT_SECTION(\"u8x8_font_artossans8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\3\\0\\0\\0\\3\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0B%\\22\\10$R!\\0\\0 VIIU\\42P\\0\\0\\0\\0\"\n  \"\\3\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\0>AAA>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22\\21\\177\\20\\0\\0\\0'EEE\\71\\0\\0\\0>III\\62\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0&III>\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0\\0 \"\n  \"\\22\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34`\\30\\26\\21\\26\\30`\\0\\177IIIII\\66\\0>AAA\"\n  \"AA\\42\\0\\177AAAAA>\\0\\177IIIIAA\\0\\177\\11\\11\\11\\11\\1\\1\\0>AAA\"\n  \"II:\\0\\177\\10\\10\\10\\10\\10\\177\\0\\0AA\\177AA\\0\\0 @@@@@\\77\\0\\177\\10\\10\\10\"\n  \"\\24\\42A\\0\\177@@@@@@\\0\\177\\2\\4\\10\\4\\2\\177\\0\\177\\2\\4\\10\\20 \\177\\0>AAA\"\n  \"AA>\\0\\177\\21\\21\\21\\21\\21\\16\\0>AAAaA\\276\\0\\177\\11\\11\\11\\11\\31f\\0&III\"\n  \"II\\62\\0\\1\\1\\1\\177\\1\\1\\1\\0\\77@@@@@\\77\\0\\17\\20 @ \\20\\17\\0\\37` \\34\"\n  \" `\\37\\0A\\42\\24\\10\\24\\42A\\0\\3\\4\\10p\\10\\4\\3\\0AaQIECA\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\4\\2\\1\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Artos Serif-Medium-R-Normal--8-80-75-75-M-80-ISO8859-1\n  Copyright: (null)\n  Glyphs: 95/95\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artosserif8_r[764] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_r\") = \n  \" ~\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\3\\0\\0\\0\\3\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0B%\\22\\10$R!\\0\\0 VIIU\\42P\\0\\0\\0\\0\"\n  \"\\3\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\0>AAA>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22Q\\177P\\0\\0\\0'EEE\\71\\0\\0\\0>III\\62\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0&III>\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0\\0 \"\n  \"\\22\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34@xV\\21Vx@\\0A\\177IIII\\66\\0\\34\\42AA\"\n  \"AA\\42\\0A\\177AAAA>\\0A\\177IIIAc\\0A\\177I\\11\\11\\1\\3\\0\\34\\42AA\"\n  \"II:\\0A\\177I\\10I\\177A\\0\\0\\0A\\177A\\0\\0\\0 @@@A\\77\\1\\0A\\177I\\10\"\n  \"UcA\\0A\\177A@@@`\\0A\\177E\\10E\\177A\\0A\\177E\\10Q\\177A\\0\\0>AA\"\n  \"AA>\\0A\\177Q\\21\\21\\21\\16\\0\\0>AAaA\\276\\0A\\177I\\11\\11Iv@&III\"\n  \"II\\62\\0\\3\\1A\\177A\\1\\3\\0\\1\\77A@A\\77\\1\\0\\1\\17\\61@\\61\\17\\1\\0\\1\\177!\\34\"\n  \"!\\177\\1\\0AcU\\10UcA\\0\\1\\7IpI\\7\\1\\0CaQIECa\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\4\\2\\1\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\1\\2\\0\\0\\0\\0 TTTx\\0\\0\\0\\177DDD\\70\\0\\0\\0\\70DD\"\n  \"D(\\0\\0\\0\\70DDD\\177\\0\\0\\0\\70TTTH\\0\\0\\0\\0\\4~\\5\\1\\0\\0\\0\\30\\244\\244\"\n  \"\\244|\\0\\0\\0\\177\\4\\4\\4x\\0\\0\\0\\0D}@\\0\\0\\0\\0@\\200\\200\\204}\\0\\0\\0\\177\\20\\20\"\n  \"(D\\0\\0\\0\\0A\\177@\\0\\0\\0\\0|\\4x\\4x\\0\\0\\0|\\10\\4\\4x\\0\\0\\0\\70DD\"\n  \"D\\70\\0\\0\\0\\374DDD\\70\\0\\0\\0\\70DDD\\374\\0\\0\\0|\\10\\4\\4\\4\\0\\0\\0HTT\"\n  \"T$\\0\\0\\0\\0\\4\\77D@\\0\\0\\0<@@@|\\0\\0\\0\\34 @ \\34\\0\\0\\0<@\\60\"\n  \"@<\\0\\0\\0D(\\20(D\\0\\0\\0\\34\\240\\240\\240|\\0\\0\\0DdTLD\\0\\0\\0\\0\\10\\66\"\n  \"A\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0\\0A\\66\\10\\0\\0\\10\\4\\4\\10\\20\\20\\10\";\n/*\n  Fontname: -FontForge-Artos Serif-Medium-R-Normal--8-80-75-75-M-80-ISO8859-1\n  Copyright: (null)\n  Glyphs: 18/95\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artosserif8_n[220] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\24\\10>\\10\\24\\0\\0\\20\\20|\"\n  \"\\20\\20\\0\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\200\\0\\0\\0\\0\\200@ \\20\"\n  \"\\10\\4\\2\\0\\0|\\202\\202\\202|\\0\\0\\0\\200\\204\\376\\200\\200\\0\\0\\0\\304\\242\\222\\222\\214\\0\\0\\0D\\202\\222\"\n  \"\\222l\\0\\0\\0\\70$\\242\\376\\240\\0\\0\\0N\\212\\212\\212r\\0\\0\\0|\\222\\222\\222d\\0\\0\\0\\2\\2\\362\"\n  \"\\12\\6\\0\\0\\0l\\222\\222\\222l\\0\\0\\0L\\222\\222\\222|\\0\\0\\0\\0\\0$\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Artos Serif-Medium-R-Normal--8-80-75-75-M-80-ISO8859-1\n  Copyright: (null)\n  Glyphs: 64/95\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_artosserif8_u[517] U8X8_FONT_SECTION(\"u8x8_font_artosserif8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\3\\0\\0\\0\\3\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0B%\\22\\10$R!\\0\\0 VIIU\\42P\\0\\0\\0\\0\"\n  \"\\3\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\0>AAA>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22Q\\177P\\0\\0\\0'EEE\\71\\0\\0\\0>III\\62\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0&III>\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0\\0 \"\n  \"\\22\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34@xV\\21Vx@\\0A\\177IIII\\66\\0\\34\\42AA\"\n  \"AA\\42\\0A\\177AAAA>\\0A\\177IIIAc\\0A\\177I\\11\\11\\1\\3\\0\\34\\42AA\"\n  \"II:\\0A\\177I\\10I\\177A\\0\\0\\0A\\177A\\0\\0\\0 @@@A\\77\\1\\0A\\177I\\10\"\n  \"UcA\\0A\\177A@@@`\\0A\\177E\\10E\\177A\\0A\\177E\\10Q\\177A\\0\\0>AA\"\n  \"AA>\\0A\\177Q\\21\\21\\21\\16\\0\\0>AAaA\\276\\0A\\177I\\11\\11Iv@&III\"\n  \"II\\62\\0\\3\\1A\\177A\\1\\3\\0\\1\\77A@A\\77\\1\\0\\1\\17\\61@\\61\\17\\1\\0\\1\\177!\\34\"\n  \"!\\177\\1\\0AcU\\10UcA\\0\\1\\7IpI\\7\\1\\0CaQIECa\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\4\\2\\1\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Chroma 48-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 96/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_chroma48medium8_r[772] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\6\\0\\0\\6\\0\\0\\0$~$\"\n  \"$~$\\0\\0$k**k\\22\\0\\0F&\\20\\10db\\0\\0\\64JJT P\\0\\0\\0\\0\\0\"\n  \"\\6\\0\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0*\\34>\\34*\\0\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0<bRJF<\\0\\0@D~@@\\0\\0\\0dRRRRL\\0\\0$BJ\"\n  \"JJ\\64\\0\\0\\70$\\42\\42~ \\0\\0.JJJJ\\62\\0\\0<JJJJ\\60\\0\\0\\2\\2b\"\n  \"\\22\\12\\6\\0\\0\\64JJJJ\\64\\0\\0\\14RRRR<\\0\\0\\0\\0$\\0\\0\\0\\0\\0\\0@$\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\24\\42\\0\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0\\42\\24\\10\\0\\0\\0\\4\\2R\"\n  \"\\12\\4\\0\\0\\0\\30$ZZ$\\30\\0\\0|\\22\\22\\22\\22|\\0\\0~JJJJ\\64\\0\\0<BB\"\n  \"BB$\\0\\0~BBBB<\\0\\0~JJJBB\\0\\0~\\12\\12\\12\\2\\2\\0\\0<BB\"\n  \"RR\\64\\0\\0~\\10\\10\\10\\10~\\0\\0\\0B~B\\0\\0\\0\\0 @@@@>\\0\\0~\\10\\10\"\n  \"\\10\\24b\\0\\0~@@@@@\\0\\0~\\4\\10\\10\\4~\\0\\0~\\4\\10\\20 ~\\0\\0<BB\"\n  \"BB<\\0\\0~\\22\\22\\22\\22\\14\\0\\0<BRbB<\\0\\0~\\22\\22\\22\\62L\\0\\0$JJ\"\n  \"JJ\\60\\0\\0\\2\\2~\\2\\2\\0\\0\\0>@@@@>\\0\\0\\36 @@ \\36\\0\\0~ \\20\"\n  \"\\20 ~\\0\\0B$\\30\\30$B\\0\\0\\2\\4x\\4\\2\\0\\0\\0BbRJFB\\0\\0\\0~B\"\n  \"B\\0\\0\\0\\0\\2\\4\\10\\20 @\\0\\0\\0\\0BB~\\0\\0\\0\\0\\0\\4\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\2\\4\\0\\0\\0\\0 TTTx\\0\\0\\0~HHH\\60\\0\\0\\0\\70DD\"\n  \"D(\\0\\0\\0\\60HHH~\\0\\0\\0\\70TTTH\\0\\0\\0\\0\\10|\\12\\2\\0\\0\\0\\30\\244\\244\"\n  \"\\244|\\0\\0\\0~\\10\\10\\10p\\0\\0\\0\\0Hz@\\0\\0\\0\\0@\\200\\200\\210z\\0\\0\\0~\\20\\20\"\n  \"(D\\0\\0\\0\\0B~@\\0\\0\\0\\0|\\4x\\4x\\0\\0\\0|\\4\\4\\4x\\0\\0\\0\\70DD\"\n  \"D\\70\\0\\0\\0\\374DDD\\70\\0\\0\\0\\70DDD\\374\\0\\0\\0|\\10\\4\\4\\4\\0\\0\\0HTT\"\n  \"T$\\0\\0\\0\\0\\4>D\\0\\0\\0\\0<@@ |\\0\\0\\0\\34 @ \\34\\0\\0\\0\\34`\\34\"\n  \"`\\34\\0\\0\\0D(\\20(D\\0\\0\\0\\34\\240\\240\\240|\\0\\0\\0DdTLD\\0\\0\\0\\0\\10\\66\"\n  \"A\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0A\\66\\10\\0\\0\\0\\10\\4\\4\\10\\20\\20\\10\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Chroma 48-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_chroma48medium8_n[220] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0T\\70|\\70T\\0\\0\\0\\20\\20|\"\n  \"\\20\\20\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\200\\0\\0\\0\\0\\0\\200@ \"\n  \"\\20\\10\\4\\0\\0x\\304\\244\\224\\214x\\0\\0\\200\\210\\374\\200\\200\\0\\0\\0\\310\\244\\244\\244\\244\\230\\0\\0H\\204\\224\"\n  \"\\224\\224h\\0\\0pHDD\\374@\\0\\0\\134\\224\\224\\224\\224d\\0\\0x\\224\\224\\224\\224`\\0\\0\\4\\4\\304\"\n  \"$\\24\\14\\0\\0h\\224\\224\\224\\224h\\0\\0\\30\\244\\244\\244\\244x\\0\\0\\0\\0H\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Chroma 48-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_chroma48medium8_u[517] U8X8_FONT_SECTION(\"u8x8_font_chroma48medium8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0^\\0\\0\\0\\0\\0\\0\\6\\0\\0\\6\\0\\0\\0$~$\"\n  \"$~$\\0\\0$k**k\\22\\0\\0F&\\20\\10db\\0\\0\\64JJT P\\0\\0\\0\\0\\0\"\n  \"\\6\\0\\0\\0\\0\\0\\0<B\\0\\0\\0\\0\\0\\0B<\\0\\0\\0\\0*\\34>\\34*\\0\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0@\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0<bRJF<\\0\\0@D~@@\\0\\0\\0dRRRRL\\0\\0$BJ\"\n  \"JJ\\64\\0\\0\\70$\\42\\42~ \\0\\0.JJJJ\\62\\0\\0<JJJJ\\60\\0\\0\\2\\2b\"\n  \"\\22\\12\\6\\0\\0\\64JJJJ\\64\\0\\0\\14RRRR<\\0\\0\\0\\0$\\0\\0\\0\\0\\0\\0@$\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\24\\42\\0\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0\\0\\42\\24\\10\\0\\0\\0\\4\\2R\"\n  \"\\12\\4\\0\\0\\0\\30$ZZ$\\30\\0\\0|\\22\\22\\22\\22|\\0\\0~JJJJ\\64\\0\\0<BB\"\n  \"BB$\\0\\0~BBBB<\\0\\0~JJJBB\\0\\0~\\12\\12\\12\\2\\2\\0\\0<BB\"\n  \"RR\\64\\0\\0~\\10\\10\\10\\10~\\0\\0\\0B~B\\0\\0\\0\\0 @@@@>\\0\\0~\\10\\10\"\n  \"\\10\\24b\\0\\0~@@@@@\\0\\0~\\4\\10\\10\\4~\\0\\0~\\4\\10\\20 ~\\0\\0<BB\"\n  \"BB<\\0\\0~\\22\\22\\22\\22\\14\\0\\0<BRbB<\\0\\0~\\22\\22\\22\\62L\\0\\0$JJ\"\n  \"JJ\\60\\0\\0\\2\\2~\\2\\2\\0\\0\\0>@@@@>\\0\\0\\36 @@ \\36\\0\\0~ \\20\"\n  \"\\20 ~\\0\\0B$\\30\\30$B\\0\\0\\2\\4x\\4\\2\\0\\0\\0BbRJFB\\0\\0\\0~B\"\n  \"B\\0\\0\\0\\0\\2\\4\\10\\20 @\\0\\0\\0\\0BB~\\0\\0\\0\\0\\0\\4\\2\\4\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Saikyo Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/72\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_saikyosansbold8_n[220] U8X8_FONT_SECTION(\"u8x8_font_saikyosansbold8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\20\\20|\"\n  \"|\\20\\20\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\300`\\60\"\n  \"\\30\\14\\6\\0|\\376\\202\\202\\202\\376|\\0\\0\\200\\204\\376\\376\\200\\200\\0\\304\\346\\262\\222\\222\\236\\214\\0D\\306\\222\\222\"\n  \"\\222\\376l\\0\\70<&\\42\\376\\376 \\0N\\316\\212\\212\\212\\372r\\0|\\376\\222\\222\\222\\366d\\0\\6\\6\\2\\362\"\n  \"\\372\\16\\6\\0l\\376\\222\\222\\222\\376l\\0L\\336\\222\\222\\222\\376|\\0\\0\\0\\0ll\\0\\0\";\n/*\n  Fontname: -FontForge-Saikyo Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/72\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_saikyosansbold8_u[517] U8X8_FONT_SECTION(\"u8x8_font_saikyosansbold8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\0\\7\\7\\0\\0\\42\\177\\177\"\n  \"\\42\\177\\177\\42$.*k*:\\22\\0Ff\\60\\30\\14fb\\0 v_I\\77vP\\0\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\4\\25\\37\\16\\37\\25\\4\\0\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0@p\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\"\n  \"\\14\\6\\3\\0>\\177AAA\\177>\\0\\0@B\\177\\177@@\\0bsYIIOF\\0\\42cII\"\n  \"I\\177\\66\\0\\34\\36\\23\\21\\177\\177\\20\\0'gEEE}\\71\\0>\\177III{\\62\\0\\3\\3\\1y\"\n  \"}\\7\\3\\0\\66\\177III\\177\\66\\0&oIII\\177>\\0\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0@v\"\n  \"\\66\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\1Y\"\n  \"Y\\17\\6\\0<B\\231\\245\\245\\271\\42\\34~\\177\\21\\21\\21\\177~\\0\\177\\177III\\177\\66\\0>\\177AA\"\n  \"Ac\\42\\0\\177\\177AAA\\177>\\0\\177\\177IIIIA\\0\\177\\177\\11\\11\\11\\1\\1\\0>\\177AA\"\n  \"I{:\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0\\0\\0\\177\\177\\0\\0\\0 `@@@\\177\\77\\0\\177\\177\\10\\34\"\n  \"\\66cA\\0\\177\\177@@@@@\\0\\177\\177\\6\\14\\6\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0\\177\\177\\21\\21\\21\\37\\16\\0>\\177AAA\\377\\276\\0\\177\\177\\21\\21\\21\\177n\\0&oII\"\n  \"I{\\62\\0\\0\\1\\1\\177\\177\\1\\1\\0\\77\\177@@@\\177\\77\\0\\17\\37\\60`\\60\\37\\17\\0\\177\\177\\60\\34\"\n  \"\\60\\177\\177\\0cw\\34\\10\\34wc\\0\\0\\7\\17xx\\17\\7\\0aqy]OGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\0\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\0\\0\\14\\6\\3\\6\\14\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Torus Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 96/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_torussansbold8_r[772] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\3\\7\\0\\0\\7\\3\\0\\0\\42\\177\\177\"\n  \"\\42\\177\\177\\42\\0$.kk:\\22\\0\\0c\\63\\30\\14fc\\0\\0 vOY\\67fP\\0\\0\\0\\7\"\n  \"\\3\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\0\\10\\10\"\n  \">\\10\\10\\0\\0\\0\\0p\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\"\n  \"\\14\\6\\3\\0\\0>\\177AA\\177>\\0\\0@B\\177\\177@@\\0\\0bqYIOF\\0\\0\\42AI\"\n  \"I\\177\\66\\0\\0\\34\\36Q\\177\\177P\\0\\0'GEE}\\71\\0\\0>\\177IIy\\62\\0\\0\\1\\1y\"\n  \"}\\7\\3\\0\\0\\66\\177II\\177\\66\\0\\0&OII\\177>\\0\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0\\0v\"\n  \"\\66\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\1Y\"\n  \"Y\\17\\6\\0<B\\231\\245\\245\\271\\42\\34\\0~\\177\\11\\11\\177~\\0\\0\\177\\177II\\177\\66\\0\\0>\\177A\"\n  \"AA\\42\\0\\0\\177\\177AA\\177>\\0\\0\\177\\177IIAA\\0\\0\\177\\177\\11\\11\\1\\1\\0\\0>\\177A\"\n  \"Iy:\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0 @@@\\177\\77\\0\\0\\177\\177\\10\"\n  \"\\34wc\\0\\0\\177\\177@@@@\\0\\177\\6\\14\\30\\14\\6\\177\\177\\177\\7\\16\\34\\70p\\177\\0\\0>\\177A\"\n  \"A\\177>\\0\\0\\177\\177\\21\\21\\37\\16\\0\\0>\\177AA\\377\\276\\0\\0\\177\\177\\11\\11\\177v\\0\\0&OI\"\n  \"Iy\\62\\0\\0\\1\\1\\177\\177\\1\\1\\0\\0\\77\\177@@\\177\\77\\0\\0\\177\\177@@\\77\\37\\0\\177\\177@\\177\"\n  \"@\\77\\37\\0\\0w\\177\\10\\10\\177w\\0\\0\\7\\17xx\\17\\7\\0\\0aqYMGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\0\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\0\\0\\14\\6\\3\\6\\14\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\1\\3\\2\\0\\0\\0 tTT|x\\0\\0\\177\\177DD|\\70\\0\\0\\70|D\"\n  \"DD(\\0\\0\\70|DD\\177\\177\\0\\0\\70|TT\\134H\\0\\0\\0\\4~\\177\\5\\1\\0\\0\\30\\274\\244\"\n  \"\\244\\374|\\0\\0\\177\\177\\4\\4|x\\0\\0\\0D}}@\\0\\0\\0\\0@\\200\\204\\375}\\0\\0\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0\\0\\1\\177\\177\\0\\0||\\4|\\4|x\\0\\0||\\4\\4|x\\0\\0\\70|D\"\n  \"D|\\70\\0\\0\\374\\374DD|\\70\\0\\0\\70|DD\\374\\374\\0\\0||\\10\\4\\4\\4\\0\\0H\\134T\"\n  \"Tt$\\0\\0\\0\\4\\77\\177D\\0\\0\\0<|@@||\\0\\0||@@<\\34\\0||@|\"\n  \"@<\\34\\0\\0l|\\20\\20|l\\0\\0\\34\\274\\240\\240\\374|\\0\\0Ddt\\134LD\\0\\0\\0\\10>\"\n  \"wA\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\\0Aw>\\10\\0\\0\\0\\10\\14\\4\\10\\20\\30\\10\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Torus Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_torussansbold8_n[220] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\24\\10>\\10\\24\\0\\0\\0\\20\\20\"\n  \"|\\20\\20\\0\\0\\0\\0\\340`\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\300`\\60\"\n  \"\\30\\14\\6\\0\\0|\\376\\202\\202\\376|\\0\\0\\200\\204\\376\\376\\200\\200\\0\\0\\304\\342\\262\\222\\236\\214\\0\\0D\\202\\222\"\n  \"\\222\\376l\\0\\0\\70<\\242\\376\\376\\240\\0\\0N\\216\\212\\212\\372r\\0\\0|\\376\\222\\222\\362d\\0\\0\\2\\2\\362\"\n  \"\\372\\16\\6\\0\\0l\\376\\222\\222\\376l\\0\\0L\\236\\222\\222\\376|\\0\\0\\0\\0ll\\0\\0\";\n/*\n  Fontname: -FontForge-Torus Sans-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/170\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_torussansbold8_u[517] U8X8_FONT_SECTION(\"u8x8_font_torussansbold8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\3\\7\\0\\0\\7\\3\\0\\0\\42\\177\\177\"\n  \"\\42\\177\\177\\42\\0$.kk:\\22\\0\\0c\\63\\30\\14fc\\0\\0 vOY\\67fP\\0\\0\\0\\7\"\n  \"\\3\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\0\\12\\4\\37\\4\\12\\0\\0\\0\\10\\10\"\n  \">\\10\\10\\0\\0\\0\\0p\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\"\n  \"\\14\\6\\3\\0\\0>\\177AA\\177>\\0\\0@B\\177\\177@@\\0\\0bqYIOF\\0\\0\\42AI\"\n  \"I\\177\\66\\0\\0\\34\\36Q\\177\\177P\\0\\0'GEE}\\71\\0\\0>\\177IIy\\62\\0\\0\\1\\1y\"\n  \"}\\7\\3\\0\\0\\66\\177II\\177\\66\\0\\0&OII\\177>\\0\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0\\0v\"\n  \"\\66\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\1Y\"\n  \"Y\\17\\6\\0<B\\231\\245\\245\\271\\42\\34\\0~\\177\\11\\11\\177~\\0\\0\\177\\177II\\177\\66\\0\\0>\\177A\"\n  \"AA\\42\\0\\0\\177\\177AA\\177>\\0\\0\\177\\177IIAA\\0\\0\\177\\177\\11\\11\\1\\1\\0\\0>\\177A\"\n  \"Iy:\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0 @@@\\177\\77\\0\\0\\177\\177\\10\"\n  \"\\34wc\\0\\0\\177\\177@@@@\\0\\177\\6\\14\\30\\14\\6\\177\\177\\177\\7\\16\\34\\70p\\177\\0\\0>\\177A\"\n  \"A\\177>\\0\\0\\177\\177\\21\\21\\37\\16\\0\\0>\\177AA\\377\\276\\0\\0\\177\\177\\11\\11\\177v\\0\\0&OI\"\n  \"Iy\\62\\0\\0\\1\\1\\177\\177\\1\\1\\0\\0\\77\\177@@\\177\\77\\0\\0\\177\\177@@\\77\\37\\0\\177\\177@\\177\"\n  \"@\\77\\37\\0\\0w\\177\\10\\10\\177w\\0\\0\\7\\17xx\\17\\7\\0\\0aqYMGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\0\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\0\\0\\14\\6\\3\\6\\14\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Victoria-Bold-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 96/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriabold8_r[772] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\0\\7\\7\\0\\0\\42\\177\\177\"\n  \"\\42\\177\\177\\42\\0$.kk:\\22\\0\\0c\\63\\30\\14fc\\0\\0 v_I\\177vP\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\4\\25\\37\\16\\37\\25\\4\\0\\0\\0\\10\\10\"\n  \">\\10\\10\\0\\0\\0@p\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\"\n  \"\\14\\6\\3\\0\\0>\\177AA\\177>\\0\\0@B\\177\\177@@\\0\\0bsYIOF\\0\\0\\42cI\"\n  \"I\\177\\66\\0\\0\\34\\36S\\177\\177P\\0\\0'gEE}\\71\\0\\0>\\177II{\\62\\0\\0\\1\\1y\"\n  \"}\\7\\3\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0\\0v\"\n  \"\\66\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\1Y\"\n  \"Y\\17\\6\\0<B\\231\\245\\245\\271\\42\\34\\0~\\177\\11\\11\\177~\\0\\0\\177\\177II\\177\\66\\0\\0>\\177A\"\n  \"Ac\\42\\0\\0\\177\\177AA\\177>\\0\\0\\177\\177IIAA\\0\\0\\177\\177\\11\\11\\1\\1\\0\\0>\\177A\"\n  \"I{:\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0 `@@\\177\\77\\0\\0\\177\\177\\34\"\n  \"\\66cA\\0\\0\\177\\177@@@@\\0\\177\\177\\6\\14\\6\\177\\177\\0\\0\\177\\177\\14\\30\\177\\177\\0\\0>\\177A\"\n  \"A\\177>\\0\\0\\177\\177\\11\\11\\17\\6\\0\\0>\\177AA\\377\\276\\0\\0\\177\\177\\31\\71oF\\0\\0&oI\"\n  \"I{\\62\\0\\0\\1\\1\\177\\177\\1\\1\\0\\0\\77\\177@@\\177\\77\\0\\0\\37\\77``\\77\\37\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0\\0cw\\34\\34wc\\0\\0\\7\\17xx\\17\\7\\0\\0aqYMGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\0\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\0\\0\\14\\6\\3\\6\\14\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\1\\3\\2\\0\\0\\0 tTT|x\\0\\0\\177\\177DD|\\70\\0\\0\\70|D\"\n  \"Dl(\\0\\0\\70|DD\\177\\177\\0\\0\\70|TT\\134H\\0\\0\\0\\4~\\177\\5\\1\\0\\0\\30\\274\\244\"\n  \"\\244\\374|\\0\\0\\177\\177\\4\\4|x\\0\\0\\0D}}@\\0\\0\\0@\\300\\200\\204\\375}\\0\\0\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0\\0A\\177\\177@\\0||\\14x\\14|x\\0\\0||\\4\\4|x\\0\\0\\70|D\"\n  \"D|\\70\\0\\0\\374\\374DD|\\70\\0\\0\\70|DD\\374\\374\\0\\0||\\10\\4\\4\\4\\0\\0H\\134T\"\n  \"Tt$\\0\\0\\0\\4\\77\\177D\\0\\0\\0<|@@||\\0\\0\\34<``<\\34\\0\\34|p<\"\n  \"p|\\34\\0\\0Dl\\70\\70lD\\0\\0\\34\\274\\240\\240\\374|\\0\\0Ddt\\134LD\\0\\0\\0\\10>\"\n  \"wA\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\\0Aw>\\10\\0\\0\\0\\10\\14\\4\\10\\20\\30\\10\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Victoria-Bold-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriabold8_n[220] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\0\\20\\20\"\n  \"|\\20\\20\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\300`\\60\"\n  \"\\30\\14\\6\\0\\0|\\376\\202\\202\\376|\\0\\0\\200\\204\\376\\376\\200\\200\\0\\0\\304\\346\\262\\222\\236\\214\\0\\0D\\306\\222\"\n  \"\\222\\376l\\0\\0\\70<\\246\\376\\376\\240\\0\\0N\\316\\212\\212\\372r\\0\\0|\\376\\222\\222\\366d\\0\\0\\2\\2\\362\"\n  \"\\372\\16\\6\\0\\0l\\376\\222\\222\\376l\\0\\0L\\336\\222\\222\\376|\\0\\0\\0\\0ll\\0\\0\";\n/*\n  Fontname: -FontForge-Victoria-Bold-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriabold8_u[517] U8X8_FONT_SECTION(\"u8x8_font_victoriabold8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\0\\0\\0\\0\\7\\7\\0\\0\\7\\7\\0\\0\\42\\177\\177\"\n  \"\\42\\177\\177\\42\\0$.kk:\\22\\0\\0c\\63\\30\\14fc\\0\\0 v_I\\177vP\\0\\0\\0\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\4\\25\\37\\16\\37\\25\\4\\0\\0\\0\\10\\10\"\n  \">\\10\\10\\0\\0\\0@p\\60\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\"\n  \"\\14\\6\\3\\0\\0>\\177AA\\177>\\0\\0@B\\177\\177@@\\0\\0bsYIOF\\0\\0\\42cI\"\n  \"I\\177\\66\\0\\0\\34\\36S\\177\\177P\\0\\0'gEE}\\71\\0\\0>\\177II{\\62\\0\\0\\1\\1y\"\n  \"}\\7\\3\\0\\0\\66\\177II\\177\\66\\0\\0&oII\\177>\\0\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0\\0v\"\n  \"\\66\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\1Y\"\n  \"Y\\17\\6\\0<B\\231\\245\\245\\271\\42\\34\\0~\\177\\11\\11\\177~\\0\\0\\177\\177II\\177\\66\\0\\0>\\177A\"\n  \"Ac\\42\\0\\0\\177\\177AA\\177>\\0\\0\\177\\177IIAA\\0\\0\\177\\177\\11\\11\\1\\1\\0\\0>\\177A\"\n  \"I{:\\0\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0 `@@\\177\\77\\0\\0\\177\\177\\34\"\n  \"\\66cA\\0\\0\\177\\177@@@@\\0\\177\\177\\6\\14\\6\\177\\177\\0\\0\\177\\177\\14\\30\\177\\177\\0\\0>\\177A\"\n  \"A\\177>\\0\\0\\177\\177\\11\\11\\17\\6\\0\\0>\\177AA\\377\\276\\0\\0\\177\\177\\31\\71oF\\0\\0&oI\"\n  \"I{\\62\\0\\0\\1\\1\\177\\177\\1\\1\\0\\0\\77\\177@@\\177\\77\\0\\0\\37\\77``\\77\\37\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0\\0cw\\34\\34wc\\0\\0\\7\\17xx\\17\\7\\0\\0aqYMGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\0\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\0\\0\\14\\6\\3\\6\\14\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FontForge-Victoria-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 96/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriamedium8_r[772] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\7\\0\\0\\0\\7\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0\\0\\42\\20\\10\\4\\42\\0\\0 VIIV P\\0\\0\\0\\0\\7\"\n  \"\\0\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0*\\34\\177\\34*\\0\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>QIE>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22Q\\177P\\0\\0\\0'EEE\\71\\0\\0\\0<JII\\60\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0\\6II)\\36\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0@\\62\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0A\\42\\24\\10\\0\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34\\0~\\11\\11\\11~\\0\\0\\0\\177III\\66\\0\\0\\0>AA\"\n  \"A\\42\\0\\0\\0\\177AAA>\\0\\0\\0\\177IIAA\\0\\0\\0\\177\\11\\11\\11\\1\\0\\0\\0>AA\"\n  \"I:\\0\\0\\0\\177\\10\\10\\10\\177\\0\\0\\0\\0A\\177A\\0\\0\\0\\0 @@@\\77\\0\\0\\0\\177\\10\\24\"\n  \"\\42A\\0\\0\\0\\177@@@@\\0\\0\\0\\177\\2\\4\\2\\177\\0\\0\\0\\177\\4\\10\\20\\177\\0\\0\\0>AA\"\n  \"A>\\0\\0\\0\\177\\11\\11\\11\\6\\0\\0\\0>AaA\\276\\0\\0\\0\\177\\11\\31)F\\0\\0\\0&II\"\n  \"I\\62\\0\\0\\0\\1\\1\\177\\1\\1\\0\\0\\0\\77@@@\\77\\0\\0\\0\\37 @ \\37\\0\\0\\0\\177 \\20\"\n  \" \\177\\0\\0\\0c\\24\\10\\24c\\0\\0\\0\\7\\10p\\10\\7\\0\\0\\0aQIEC\\0\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\0\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\0\\4\\2\\1\\2\\4\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\1\\2\\0\\0\\0\\0 TTTx\\0\\0\\0\\177DDD\\70\\0\\0\\0\\70DD\"\n  \"D(\\0\\0\\0\\70DDD\\177\\0\\0\\0\\70TTTH\\0\\0\\0\\0\\4~\\5\\5\\0\\0\\0\\30\\244\\244\"\n  \"\\244|\\0\\0\\0\\177\\4\\4\\4x\\0\\0\\0\\0D}@\\0\\0\\0\\0@\\200\\200\\204}\\0\\0\\0\\177\\20\\20\"\n  \"(D\\0\\0\\0\\0A\\177@\\0\\0\\0\\0|\\4x\\4x\\0\\0\\0|\\4\\4\\4x\\0\\0\\0\\70DD\"\n  \"D\\70\\0\\0\\0\\374DDD\\70\\0\\0\\0\\70DDD\\374\\0\\0\\0|\\10\\4\\4\\4\\0\\0\\0HTT\"\n  \"T$\\0\\0\\0\\0\\4\\77D\\0\\0\\0\\0<@@ |\\0\\0\\0\\34 @ \\34\\0\\0\\0\\34`\\34\"\n  \"`\\34\\0\\0\\0D(\\20(D\\0\\0\\0\\34\\240\\240\\240|\\0\\0\\0DdTLD\\0\\0\\0\\0\\10\\66\"\n  \"A\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0A\\66\\10\\0\\0\\0\\10\\4\\4\\10\\20\\20\\10\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Victoria-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 18/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriamedium8_n[220] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0T\\70\\376\\70T\\0\\0\\0\\20\\20|\"\n  \"\\20\\20\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\300\\300\\0\\0\\0\\0\\200@ \"\n  \"\\20\\10\\4\\0\\0|\\242\\222\\212|\\0\\0\\0\\200\\204\\376\\200\\200\\0\\0\\0\\304\\242\\222\\222\\214\\0\\0\\0D\\202\\222\"\n  \"\\222l\\0\\0\\0\\70$\\242\\376\\240\\0\\0\\0N\\212\\212\\212r\\0\\0\\0x\\224\\222\\222`\\0\\0\\0\\2\\2\\362\"\n  \"\\12\\6\\0\\0\\0l\\222\\222\\222l\\0\\0\\0\\14\\222\\222R<\\0\\0\\0\\0\\0$\\0\\0\\0\";\n/*\n  Fontname: -FontForge-Victoria-Medium-R-Normal-Sans-8-80-75-75-P-50-ISO10646-1\n  Copyright: (null)\n  Glyphs: 64/98\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_victoriamedium8_u[517] U8X8_FONT_SECTION(\"u8x8_font_victoriamedium8_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0_\\0\\0\\0\\0\\0\\7\\0\\0\\0\\7\\0\\0\\0\\42\\177\\42\"\n  \"\\42\\177\\42\\0\\0$*k*\\22\\0\\0\\0\\42\\20\\10\\4\\42\\0\\0 VIIV P\\0\\0\\0\\0\\7\"\n  \"\\0\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\0*\\34\\177\\34*\\0\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0@\\60\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>QIE>\\0\\0\\0@B\\177@@\\0\\0\\0bQIIF\\0\\0\\0\\42AI\"\n  \"I\\66\\0\\0\\0\\34\\22Q\\177P\\0\\0\\0'EEE\\71\\0\\0\\0<JII\\60\\0\\0\\0\\1\\1y\"\n  \"\\5\\3\\0\\0\\0\\66III\\66\\0\\0\\0\\6II)\\36\\0\\0\\0\\0\\0\\22\\0\\0\\0\\0\\0\\0@\\62\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\24\\24\\24\\24\\24\\24\\0\\0\\0A\\42\\24\\10\\0\\0\\0\\2\\1Y\"\n  \"\\11\\6\\0\\0<B\\231\\245\\245\\271\\42\\34\\0~\\11\\11\\11~\\0\\0\\0\\177III\\66\\0\\0\\0>AA\"\n  \"A\\42\\0\\0\\0\\177AAA>\\0\\0\\0\\177IIAA\\0\\0\\0\\177\\11\\11\\11\\1\\0\\0\\0>AA\"\n  \"I:\\0\\0\\0\\177\\10\\10\\10\\177\\0\\0\\0\\0A\\177A\\0\\0\\0\\0 @@@\\77\\0\\0\\0\\177\\10\\24\"\n  \"\\42A\\0\\0\\0\\177@@@@\\0\\0\\0\\177\\2\\4\\2\\177\\0\\0\\0\\177\\4\\10\\20\\177\\0\\0\\0>AA\"\n  \"A>\\0\\0\\0\\177\\11\\11\\11\\6\\0\\0\\0>AaA\\276\\0\\0\\0\\177\\11\\31)F\\0\\0\\0&II\"\n  \"I\\62\\0\\0\\0\\1\\1\\177\\1\\1\\0\\0\\0\\77@@@\\77\\0\\0\\0\\37 @ \\37\\0\\0\\0\\177 \\20\"\n  \" \\177\\0\\0\\0c\\24\\10\\24c\\0\\0\\0\\7\\10p\\10\\7\\0\\0\\0aQIEC\\0\\0\\0\\0\\177A\"\n  \"A\\0\\0\\0\\0\\2\\4\\10\\20 @\\0\\0\\0\\0AA\\177\\0\\0\\0\\0\\4\\2\\1\\2\\4\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -Adobe-Courier-Bold-R-Normal--25-180-100-100-M-150-ISO10646-1\n  Copyright: Copyright (c) 1984, 1987 Adobe Systems Incorporated. All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 191/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB18_2x3_f[10756] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_f\") = \n  \" \\377\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\370\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\277\\277\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0<\\374<\\0<\\374<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\0\\0\\0\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\200\\376\\376\\200\\200\\376\\376\\200\"\n  \"\\200\\0\\0\\0\\0\\60\\61\\361\\377\\77\\61\\361\\377\\77\\61\\61\\1\\0\\0\\0\\0\\0\\0\\17\\17\\0\\0\\17\\17\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\340\\360\\30\\30\\36\\36\\60xx\\0\\0\\0\\0\\0\\0\\0\\341\\343\\303\\206\\206\\206\\206\\314\\374x\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 95/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB18_2x3_r[4564] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_r\") = \n  \" ~\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\370\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\277\\277\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0<\\374<\\0<\\374<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\0\\0\\0\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\200\\376\\376\\200\\200\\376\\376\\200\"\n  \"\\200\\0\\0\\0\\0\\60\\61\\361\\377\\77\\61\\361\\377\\77\\61\\61\\1\\0\\0\\0\\0\\0\\0\\17\\17\\0\\0\\17\\17\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\340\\360\\30\\30\\36\\36\\60xx\\0\\0\\0\\0\\0\\0\\0\\341\\343\\303\\206\\206\\206\\206\\314\\374x\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 18/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB18_2x3_n[1300] U8X8_FONT_SECTION(\"u8x8_font_courB18_2x3_n\") = \n  \" :\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200\\0\\0\\360\\360\\0\\0\\200\\200\\0\\0\\0\\0\\0\\0\\1a{;\\17\\17;{a\\1\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\60\\60\\60\\60\\60\\377\\377\\60\\60\\60\\60\\60\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\7\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0`\\70\\36\\16\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\60\\60\\60\\60\\60\\60\\60\\60\\60\\60\\60\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\340x\"\n  \"\\30\\0\\0\\0\\0\\0\\0\\0\\0\\200\\340x\\36\\7\\1\\0\\0\\0\\0\\0\\0\\0`x\\36\\7\\1\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\340`\\60\\60\\60\\60`\\340\\200\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\\0\\0\\377\\377\"\n  \"\\0\\0\\0\\0\\0\\0\\1\\7\\6\\14\\14\\14\\14\\6\\7\\1\\0\\0\\0\\0\\0\\0```p\\360\\360\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\14\\14\\14\\14\\17\\17\\14\\14\\14\\14\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\340p\\60\\60\\60\\60p\\340\\300\\0\\0\\0\\0\\0\\0\\1\\1\\200\\300\\340p\\70\\34\\17\\7\"\n  \"\\0\\0\\0\\0\\0\\14\\16\\17\\17\\15\\14\\14\\14\\14\\14\\14\\0\\0\\0\\0\\0\\0\\300\\340p\\60\\60\\60\\60p\\340\\300\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\30\\30\\30\\34>\\367\\343\\0\\0\\0\\0\\0\\3\\7\\16\\14\\14\\14\\14\\14\\16\\7\\3\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\340p\\360\\360\\0\\0\\0\\0\\0\\0\\0\\300\\360\\374\\317\\303\\300\\300\\377\\377\\300\\300\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\14\\14\\14\\17\\17\\14\\14\\0\\0\\0\\0\\0\\0\\0\\360\\360\\60\\60\\60\\60\\60\\60\\60\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\17\\17\\14\\6\\6\\6\\16\\34\\374\\360\\0\\0\\0\\0\\0\\3\\7\\16\\14\\14\\14\\14\\16\\7\\7\"\n  \"\\1\\0\\0\\0\\0\\0\\0\\200\\300\\340`p\\60\\60\\60\\60\\0\\0\\0\\0\\0\\0\\376\\377\\33\\14\\14\\14\\14\\34\\370\\360\"\n  \"\\0\\0\\0\\0\\0\\0\\1\\7\\7\\16\\14\\14\\14\\16\\7\\3\\0\\0\\0\\0\\0\\0pp\\60\\60\\60\\60\\60\\60\\360\\360\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\370\\77\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\17\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\340`\\60\\60\\60\\60`\\340\\300\\0\\0\\0\\0\\0\\0\\343\\367<\\30\\30\\30\\30<\\367\\343\"\n  \"\\0\\0\\0\\0\\0\\0\\3\\7\\16\\14\\14\\14\\14\\16\\7\\3\\0\\0\\0\\0\\0\\0\\0\\200\\340`\\60\\60\\60\\60`\\340\"\n  \"\\200\\0\\0\\0\\0\\0\\0\\37\\77p```\\60\\30\\377\\377\\0\\0\\0\\0\\0\\0\\14\\14\\14\\14\\14\\14\\6\\7\\3\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -Adobe-Courier-Medium-R-Normal--25-180-100-100-M-150-ISO10646-1\n  Copyright: Copyright (c) 1984, 1987 Adobe Systems Incorporated. All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 191/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR18_2x3_f[10756] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_f\") = \n  \" \\377\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0<\\374<\\0\\0<\\374<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\0\\0\\0\\0\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\0\\0\\374\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\21\\21\\377\\21\\21\\377\\21\\21\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\0\\0\\7\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\300 \\20\\36\\20\\20 p\\0\\0\\0\\0\\0\\0\\0\\300\\201\\2\\4\\4\\4\\4\\210p\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\1\\0\\1\\1\\37\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0p\\210\\4\\4\\4\\210p\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\10\\10\\10\\5\\5\\345\\22\\12\\12\\11\\21\\341\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\2\\2\\2\\1\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\300  `@ \\0\\0\\0\\0\\0\\0\\0\\0\\360\\10\\5\\6\\30 \\340\\230\\10\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\1\\2\\2\\2\\1\\0\\1\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\370\\370\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\30\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\177\\200\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\14\\20\\0\\0\\0\\0\\0\\0\\0\\0\\4\\30\\340\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\177\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\14\\3\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0 `@\\300\\374\\300@` \\0\\0\\0\\0\\0\\0\\0\\4\\6\\3\\1\\0\\1\\3\\6\\4\"\n  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\"\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\2\\2\\2\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\20\\20\\20\\10\\370\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\2\\2\\2\\2\\3\\2\\2\\2\\2\"\n  \"\\0\\0\\0\\0\\0\\0`\\20\\20\\10\\10\\10\\10\\20\\340\\0\\0\\0\\0\\0\\0\\0\\0\\200@ \\20\\10\\4\\2\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\3\\2\\2\\2\\2\\2\\2\\2\\2\\3\\0\\0\\0\\0\\0\\0\\0\\20\\10\\10\\10\\10\\10\\20\\360\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\0\\0\\2\\2\\2\\2\\5\\4\\370\\0\\0\\0\\0\\0\\0\\0\\1\\1\\2\\2\\2\\2\\1\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200`\\20\\10\\370\\0\\0\\0\\0\\0\\0\\0\\0\\60,#    \\377  \"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\2\\2\\2\\3\\2\\2\\0\\0\\0\\0\\0\\0\\0\\370\\10\\10\\10\\10\\10\\10\\10\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\3\\2\\1\\1\\1\\1\\2\\206x\\0\\0\\0\\0\\0\\0\\1\\1\\2\\2\\2\\2\\2\\1\\1\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200`\\60\\20\\10\\10\\10\\10\\0\\0\\0\\0\\0\\0\\0\\0\\177\\204\\2\\1\\1\\1\\1\\2\\374\"\n  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\"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\22\\22\\22\\22\\22\\22\\22\\22\\22\\22\\22\\22\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0  @@\\200\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200@@  \\21\\21\\12\\16\"\n  \"\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0`\\20\\20\\20\\20\\20 \\300\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\60\\10\\10\\4\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\340\\30\\10\\4\\4\\4\\204\\210\\360\\0\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\36!@@\\177@\"\n  \"\\0\\0\\0\\0\\0\\0\\1\\6\\4\\10\\10\\10\\10\\14\\4\\0\\0\\0\\0\\0\\0\\0\\0\\20\\20\\320\\60\\20\\60\\300\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200p\\36\\21\\20\\20\\20\\21\\36p\\200\\0\\0\\0\\0\\2\\3\\2\\2\\0\\0\\0\\0\\0\\2\\2\"\n  \"\\3\\2\\0\\0\\0\\20\\20\\360\\20\\20\\20\\20\\20\\20\\20 \\300\\0\\0\\0\\0\\0\\0\\377\\4\\4\\4\\4\\4\\4\\4\\12\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 95/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR18_2x3_r[4564] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_r\") = \n  \" ~\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0<\\374<\\0\\0<\\374<\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\0\\0\\0\\0\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\0\\0\\374\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\21\\21\\377\\21\\21\\377\\21\\21\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\0\\0\\7\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\300 \\20\\36\\20\\20 p\\0\\0\\0\\0\\0\\0\\0\\300\\201\\2\\4\\4\\4\\4\\210p\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 18/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR18_2x3_n[1300] U8X8_FONT_SECTION(\"u8x8_font_courR18_2x3_n\") = \n  \" :\\2\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200\\200\\0\\0\\360\\0\\0\\200\\200\\0\\0\\0\\0\\0\\0\\0\\20\\31\\15\\7\\3\\7\\15\\31\\20\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\20\\20\\20\\20\\377\\20\\20\\20\\20\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0`\\70\\36\\16\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\20\\20\\20\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\60\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\60\\14\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\60\\14\\3\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\300@   @\\300\\0\\0\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0\\0\\377\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\1\\6\\4\\10\\10\\10\\4\\6\\1\\0\\0\\0\\0\\0\\0\\0@@@ \\340\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10\\10\\10\\10\\17\\10\\10\\10\\10\"\n  \"\\0\\0\\0\\0\\0\\0\\200@@    @\\200\\0\\0\\0\\0\\0\\0\\0\\1\\0\\0\\200@ \\20\\10\\7\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\14\\12\\11\\10\\10\\10\\10\\10\\10\\14\\0\\0\\0\\0\\0\\0\\0@     @\\300\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10\\10\\10\\10\\24\\23\\340\\0\\0\\0\\0\\0\\0\\2\\4\\4\\10\\10\\10\\10\\4\\4\\3\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200@ \\340\\0\\0\\0\\0\\0\\0\\0\\0\\300\\260\\214\\202\\201\\200\\200\\377\\200\\200\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10\\10\\10\\17\\10\\10\\0\\0\\0\\0\\0\\0\\0\\340       \\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\17\\10\\4\\4\\4\\4\\10\\30\\340\\0\\0\\0\\0\\0\\0\\4\\4\\10\\10\\10\\10\\10\\4\\6\\1\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300@    \\0\\0\\0\\0\\0\\0\\0\\0\\376\\21\\10\\4\\4\\4\\4\\10\\360\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\1\\6\\4\\10\\10\\10\\10\\4\\3\\0\\0\\0\\0\\0\\0\\340      \\240`\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300<\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\1\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200@    @\\200\\0\\0\\0\\0\\0\\0\\0\\300'\\30\\20\\20\\20\\20\\30'\\300\"\n  \"\\0\\0\\0\\0\\0\\0\\1\\6\\4\\10\\10\\10\\10\\4\\6\\1\\0\\0\\0\\0\\0\\0\\0\\200\\300@   @\\300\\200\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\7\\30\\20   \\20\\10\\377\\0\\0\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\4\\4\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\16\\16\\0\\0\\0\\0\\0\\0\";\n/*\n  Fontname: -Adobe-Courier-Bold-R-Normal--34-240-100-100-M-200-ISO10646-1\n  Copyright: Copyright (c) 1984, 1987 Adobe Systems Incorporated. All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 191/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB24_3x4_f[21508] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_f\") = \n  \" \\377\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0 qsq \"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\370\\370\\0\\0\\0\\370\\370\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 95/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB24_3x4_r[9124] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_r\") = \n  \" ~\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0 qsq \"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\370\\370\\370\\0\\0\\0\\370\\370\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 18/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courB24_3x4_n[2596] U8X8_FONT_SECTION(\"u8x8_font_courB24_3x4_n\") = \n  \" :\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 191/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR24_3x4_f[21508] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_f\") = \n  \" \\377\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\360\\370\\360\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\1\\377\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\340\\341\\340\"\n  \"@\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 95/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR24_3x4_r[9124] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_r\") = \n  \" ~\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\360\\370\\360\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\1\\377\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@\\340\\341\\340\"\n  \"@\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\360\\360\\360\\360\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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All Rights Reserved. Copyright (c) 1988, 1991 Digital Equipment Corporation. All Rights Reserved.\n  Glyphs: 18/873\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_courR24_3x4_n[2596] U8X8_FONT_SECTION(\"u8x8_font_courR24_3x4_n\") = \n  \" :\\3\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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 \u001cLucasArts SCUMM - Subtitle - Roman\n  Glyphs: 16/95\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_lucasarts_scumm_subtitle_o_2x2_n[868] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_o_2x2_n\") = \n  \" :\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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\\340\\300\\0\\0\\0\\0\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\17\\17\\10\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\200\\300`   `\\300\\200\\0\\0\\0\\0\\0\\0\\0\\3\\7\\14\\10\\10\\10\\14\\7\\3\\0\\0\"\n  \"\\0\\0\\0\\0\\0 \\340\\340@  `\\300\\200\\0\\0\\0\\0\\0\\0\\0\\200\\377\\377\\204\\10\\10\\14\\7\\3\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\200\\300`  @\\340\\340\\0\\0\\0\\0\\0\\0\\0\\0\\3\\7\\14\\10\\10\\204\\377\\377\\200\\0\\0\"\n  \"\\0\\0\\0\\0\\0 \\340\\340\\300`  \\340\\300\\0\\0\\0\\0\\0\\0\\0\\10\\17\\17\\10\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\300\\340\\240  @\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\16\\5\\11\\11\\13\\17\\6\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0 \\370\\374  \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\17\\10\\10\\4\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0 \\340\\340 \\0\\0 \\340\\340\\0\\0\\0\\0\\0\\0\\0\\0\\7\\17\\14\\10\\10\\4\\17\\17\\10\\0\"\n  \"\\0\\0\\0\\0\\0 `\\340\\240\\0\\0\\240\\340` \\0\\0\\0\\0\\0\\0\\0\\0\\1\\7\\16\\16\\7\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0 `\\340\\240\\0\\0\\240\\340\\340\\240\\0\\0\\0\\240`\\0\\0\\0\\1\\7\\16\\16\\7\\1\\1\\7\\16\"\n  \"\\10\\6\\1\\0\\0  `\\340\\200\\0\\200\\340`  \\0\\0\\0\\0\\0\\10\\10\\14\\16\\3\\1\\3\\16\\14\\10\\10\"\n  \"\\0\\0\\0\\0\\0 `\\340\\240\\0\\0\\0 \\340  \\0\\0\\0\\0\\0 `@Ac>\\34\\7\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\340`  \\240\\340` \\0\\0\\0\\0\\0\\0\\0\\0\\10\\14\\16\\13\\11\\10\\14\\16\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FreeType-LucasArts SCUMM   Subtitle   Roman-Medium-R-Normal--16-160-72-72-P-88-ISO10646-1\n  Copyright: Copyright Goatmeal 2013\n  Glyphs: 16/95\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_lucasarts_scumm_subtitle_r_2x2_n[868] U8X8_FONT_SECTION(\"u8x8_font_lucasarts_scumm_subtitle_r_2x2_n\") = \n  \" :\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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\"\\0\\0\\0\\0\\0\\20\\30\\14\\204\\204\\204\\314x\\60\\0\\0\\0\\0\\0\\0\\0\\4\\14\\30\\20\\20\\20\\31\\17\\6\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\300`\\60\\30\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\3\\3\\2\\2\\2\\2\\37\\37\\2\\0\\0\"\n  \"\\0\\0\\0\\0\\0||DDDD\\304\\204\\4\\0\\0\\0\\0\\0\\0\\0\\4\\14\\30\\20\\20\\20\\30\\17\\7\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\360\\370\\314DDD\\314\\230\\20\\0\\0\\0\\0\\0\\0\\0\\7\\17\\30\\20\\20\\20\\30\\17\\7\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\4\\4\\4\\204\\304d\\64\\34\\14\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\60x\\314\\204\\204\\204\\314x\\60\\0\\0\\0\\0\\0\\0\\0\\6\\17\\31\\20\\20\\20\\31\\17\\6\\0\\0\"\n  \"\\0\\0\\0\\0\\0p\\370\\214\\4\\4\\4\\214\\370\\360\\0\\0\\0\\0\\0\\0\\0\\4\\14\\31\\21\\21\\21\\31\\17\\7\\0\\0\"\n  \"\\0\\0\\0\\0\\0``\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\14\\14\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FreeType-Inconsolata LGC-Medium-R-Normal--30-300-72-72-P-138-ISO10646-1\n  Copyright: Original Roman version created by Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr21_2x4_f[14340] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_f\") = \n  \" \\377\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\70\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\343\\343\\303\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\370\\0\\0\\0\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\3\\3\\3\\0\\0\\0\\3\\3\"\n  \"\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\60\\0\\0\\0\\360\\360\\20\\0\\0\\0\\6\\6\\6\\346\\377\\77\\6\\6\\6\\366\\377\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr21_2x4_r[6084] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_r\") = \n  \" ~\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\70\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\343\\343\\303\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\370\\0\\0\\0\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\3\\3\\3\\0\\0\\0\\3\\3\"\n  \"\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\60\\0\\0\\0\\360\\360\\20\\0\\0\\0\\6\\6\\6\\346\\377\\77\\6\\6\\6\\366\\377\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr21_2x4_n[1732] U8X8_FONT_SECTION(\"u8x8_font_inr21_2x4_n\") = \n  \" :\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr33_3x6_f[32260] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_f\") = \n  \" \\377\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\360\"\n  \"\\360\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\7\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr33_3x6_r[13684] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_r\") = \n  \" ~\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\360\"\n  \"\\360\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\7\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr33_3x6_n[3892] U8X8_FONT_SECTION(\"u8x8_font_inr33_3x6_n\") = \n  \" :\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\n#ifdef U8G2_USE_LARGE_FONTS\nconst uint8_t u8x8_font_inr46_4x8_f[57348] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_f\") = \n  \" \\377\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr46_4x8_r[24324] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_r\") = \n  \" ~\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inr46_4x8_n[6916] U8X8_FONT_SECTION(\"u8x8_font_inr46_4x8_n\") = \n  \" :\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb21_2x4_f[14340] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_f\") = \n  \" \\377\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0x\\374\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\363\\363\\363\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\0\\0\\0\\370\\374\\374\\0\\0\\0\\0\\0\\0\\0\\7\\7\\7\\0\\0\\0\\7\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\360\\20\\0\\0\\360\\360\\360\\20\\0\\0\\16\\16\\16\\356\\377\\377\\17\\6\\6\\366\\377\\377\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb21_2x4_r[6084] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_r\") = \n  \" ~\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0x\\374\\374\\374\\370\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\363\\363\\363\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\1\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\370\\374\\374\\0\\0\\0\\370\\374\\374\\0\\0\\0\\0\\0\\0\\0\\7\\7\\7\\0\\0\\0\\7\\7\"\n  \"\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\360\\20\\0\\0\\360\\360\\360\\20\\0\\0\\16\\16\\16\\356\\377\\377\\17\\6\\6\\366\\377\\377\"\n  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Original Roman version created by Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb21_2x4_n[1732] U8X8_FONT_SECTION(\"u8x8_font_inb21_2x4_n\") = \n  \" :\\2\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Original Roman version created by Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb33_3x6_f[32260] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_f\") = \n  \" \\377\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\340\\360\\360\"\n  \"\\340\\300\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\17\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\177\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Original Roman version created by Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb33_3x6_r[13684] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_r\") = \n  \" ~\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\340\\360\\360\"\n  \"\\340\\300\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\377\\17\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\377\\377\\377\\377\\177\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb33_3x6_n[3892] U8X8_FONT_SECTION(\"u8x8_font_inb33_3x6_n\") = \n  \" :\\3\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 191/658\n  BBX Build Mode: 3\n*/\n#ifdef U8G2_USE_LARGE_FONTS\nconst uint8_t u8x8_font_inb46_4x8_f[57348] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_f\") = \n  \" \\377\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 95/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb46_4x8_r[24324] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_r\") = \n  \" ~\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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Roman version created by Raph Levien using his own tools and FontForge. Copyright 2006 Raph Levien. Hellenisation of the Roman font, by Dimosthenis Kaponis, using FontForge. Hellenic glyphs Copyright 2010-2012 Dimosthenis Kaponis. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Cyrillic glyphs added by MihailJP, using FontForge. Cyrillic glyphs Copyright 2012 MihailJP. Released under the SIL Open Font License, http://scripts.sil.org/OFL.    Emboldened by MihailJP.    Some glyphs modified by Greg Omelaenko, using FontForge.\n  Glyphs: 18/658\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_inb46_4x8_n[6916] U8X8_FONT_SECTION(\"u8x8_font_inb46_4x8_n\") = \n  \" :\\4\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  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\"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\\300\"\n  \"\\300\\0\\0\\0\\0\\0\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\217\\377\\377\\377\\377\\377\\377\\177\\37\"\n  \"\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\360\\376\\377\\377\\377\\377\\177\\17\\3\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\370\\377\\377\\377\\377\\377\\77\\17\\1\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\340\\370\\377\\377\\377\\377\\377\\77\\17\\1\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\370\\377\\377\\377\\377\\377\\177\\17\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6\\7\\7\\7\\7\\7\\7\\3\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\200\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200\\340\\370\\374\\374\\376\\377\\377\\177\\77\\77\\77\\37\\37\\77\\77\\77\\177\\377\\377\\376\\374\\374\\370\\340\"\n  \"\\200\\0\\0\\0\\0\\0\\0\\77\\377\\377\\377\\377\\377\\377\\340\\200\\0\\0\\0\\0\\0\\0\\0\\0\\200\\341\\377\\377\\377\\377\\377\\177\"\n  \"\\37\\0\\0\\0\\0\\0\\0\\0\\0\\201\\303\\347\\357\\377\\377\\377\\377~~||\\374\\376\\377\\377\\377\\377\\357\\307\\303\\201\\0\"\n  \"\\0\\0\\0\\0\\0\\340\\370\\376\\377\\377\\377\\377\\37\\7\\3\\1\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\37\\377\\377\\377\\377\\376\"\n  \"\\374\\360\\0\\0\\0\\17\\77\\177\\377\\377\\377\\377\\376\\370\\360\\340\\300\\300\\300\\300\\300\\300\\300\\340\\340\\360\\374\\377\\377\\377\\377\\177\"\n  \"\\77\\17\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\7\\7\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\7\\7\\7\\3\\1\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\200\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\200\\340\\360\\370\\374\\376\\377\\377\\177\\77\\77\\37\\37\\37\\77\\77\\177\\377\\377\\376\\374\\370\\360\\340\\300\"\n  \"\\0\\0\\0\\0\\0\\0\\374\\377\\377\\377\\377\\377\\377\\7\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\17\\377\\377\\377\\377\\377\"\n  \"\\376\\360\\0\\0\\0\\0\\3\\37\\177\\377\\377\\377\\377\\376\\370\\360\\340\\300\\300\\300\\300\\300\\340\\340\\360\\370\\374\\377\\377\\377\\377\\377\"\n  \"\\377\\377\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\3\\7\\7\\17\\17\\17\\17\\17\\17\\17\\17\\7\\7\\3\\303\\377\\377\\377\\377\\377\"\n  \"\\377\\37\\0\\0\\0\\0\\0\\200\\340\\360\\370\\370\\370\\340\\340\\300\\300\\300\\300\\300\\300\\340\\340\\360\\370\\376\\377\\377\\377\\177\\37\\17\"\n  \"\\1\\0\\0\\0\\0\\0\\0\\1\\1\\3\\7\\7\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\17\\7\\7\\3\\3\\1\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\300\\300\\340\\340\\340\\340\\300\\300\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\17\\77\\77\\177\\177\\177\\177\\77\\77\\17\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\340\\340\\360\\360\\360\\360\\340\\340\\200\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\37\\37\\77\\77\\77\\77\\37\\37\\7\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\";\n/*\n  Fontname: -FreeType-Press Start 2P-Medium-R-Normal--8-80-72-72-P-69-ISO10646-1\n  Copyright: (c) 2011 Cody \n  Glyphs: 192/556\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pressstart2p_f[1796] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\7\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\42\\177\\177\\42\"\n  \"\\177\\177\\42\\0$.*\\177*:\\20\\0F%\\23\\10dR\\61\\0\\66\\177I_v`P\\0\\0\\0\\7\\7\"\n  \"\\0\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\200\\340`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0``\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\34>aAC>\\34\\0\\0@B\\177\\177@@\\0bsyY]OF\\0 aIM\"\n  \"O{\\61\\0\\30\\34\\26\\23\\177\\177\\20\\0'gEEE}\\70\\0<~KIIy\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66OMYYv\\60\\0\\6OIIi\\77\\36\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\24\\0\\0Ac\\66\\34\\10\\0\\0\\6\\7SS\"\n  \"[\\17\\6\\0>A]U]Q\\36\\0|~\\23\\21\\23~|\\0\\177\\177III\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0\\177\\177AAc>\\34\\0\\177\\177IIIIA\\0\\177\\177\\11\\11\\11\\11\\1\\0\\34>cA\"\n  \"Iyy\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0 `@@@\\177\\77\\0\\177\\177\\30<\"\n  \"vcA\\0\\0\\177\\177@@@@\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\16\\34\\70\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0\\177\\177\\21\\21\\21\\37\\16\\0>\\177AQq\\77^\\0\\177\\177\\21\\61yoN\\0&oII\"\n  \"Kz\\60\\0\\0\\1\\1\\177\\177\\1\\1\\0\\77\\177@@@\\177\\77\\0\\17\\37\\70p\\70\\37\\17\\0\\177\\177\\70\\34\"\n  \"\\70\\177\\177\\0cw>\\34>wc\\0\\0\\7\\17xx\\17\\7\\0aqy]OGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AA\\177\\177\\0\\0\\0\\0\\2\\3\\1\\3\\2\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\0\\0\\0\\0\\1\\2\\0\\0\\0 tTTT|x\\0\\77\\177DDD|\\70\\0\\70|DD\"\n  \"DDD\\0\\70|DDD\\177\\177\\0\\70|TTT\\134\\30\\0\\0\\4\\4~\\177\\5\\5\\0\\30\\274\\244\\244\"\n  \"\\244\\374|\\0\\177\\177\\4\\4\\4|x\\0\\0@D}}@@\\0\\0\\200\\200\\204\\375}\\0\\0\\177\\177\\30\\70\"\n  \"|lD\\0\\0@A\\177\\177@@\\0|\\4||\\4|x\\0||\\4\\4\\4|x\\0\\70|DD\"\n  \"D|\\70\\0\\374\\374$$$<\\30\\0\\30<$$$\\374\\374\\0\\0||\\10\\4\\4\\4\\0H\\134TT\"\n  \"Tt \\0\\0\\4\\4\\177\\177\\4\\4\\0<|@@@||\\0\\0\\34<``<\\34\\0<@||\"\n  \"@||\\0ll\\70\\70\\70ll\\0\\34\\274\\240\\240\\240\\374|\\0Ddt|\\134LD\\0\\0\\0\\10>\"\n  \"wA\\0\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0Aw>\\10\\0\\0\\0\\10\\4\\14\\34\\30\\20\\10\\0\\0``\\0\"\n  \"``\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0p}}\\0\\0\\0\\34>\\42\\177\\42\\66\\24\\0H~\\177I\"\n  \"IKB\\0\\0\\42\\34\\42\\42\\34\\42\\0\\0+/||/+\\0\\0\\0\\0ww\\0\\0\\0\\0&oU\"\n  \"U{\\62\\0\\0\\1\\1\\0\\1\\1\\0\\0<B\\231\\245\\245\\201B<\\0\\5\\17\\13\\17\\16\\0\\0\\10\\34\\66*\"\n  \"\\34\\66\\42\\0\\0\\4\\4\\4\\4\\34\\34\\0\\0\\10\\10\\10\\10\\10\\10\\0<B\\275\\225\\225\\251B<\\0\\1\\1\\1\"\n  \"\\1\\1\\0\\0\\0\\0\\2\\5\\2\\0\\0\\0\\0DD__DD\\0\\0\\0\\11\\15\\17\\12\\0\\0\\0\\0\\11\\13\"\n  \"\\17\\5\\0\\0\\0\\0\\0\\2\\1\\0\\0\\0\\374\\374@@<|@\\0\\0\\16\\33\\21\\177\\21\\177\\0\\0\\0\\30\\30\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200@\\0\\0\\0\\0\\0\\12\\17\\17\\10\\0\\0\\0\\6\\17\\11\\17\\6\\0\\0\\42\\66\\34*\"\n  \"\\66\\34\\10\\0B/\\20\\10$\\62y\\0B/\\20\\10DjY\\0I+\\25\\10$\\62y\\0\\60xme\"\n  \"ep\\60\\0px-&,xp\\0px,&-xp\\0pz/%/zp\\0pz-'\"\n  \".yp\\0py-$-yp\\0px.%.xp\\0|~\\23\\177\\177II\\0\\14\\36\\263\\241\"\n  \"a\\63\\22\\0||UVTTD\\0||TVUTD\\0|~WUWVD\\0|}UT\"\n  \"UUD\\0\\0DD}~DD\\0\\0DD~}DD\\0\\0DF\\177\\177FD\\0\\0EE|\"\n  \"|EE\\0\\10\\177\\177Ic>\\34\\0|~\\35;r}|\\0\\70|EFD|\\70\\0\\70|DF\"\n  \"E|\\70\\0\\70~GEG~\\70\\0\\70~EGF}\\70\\0\\70}EDE}\\70\\0\\0\\42\\24\\10\"\n  \"\\24\\42\\0\\0>\\177QIE\\177>\\0<|AB@|<\\0<|@BA|<\\0\\70zCA\"\n  \"Cz\\70\\0<}A@A}<\\0\\0\\14\\34rq\\34\\14\\0\\177\\177\\42\\42\\42>\\34\\0\\0~\\177!\"\n  \"I\\177\\66\\0 tUVT|x\\0 tTVU|x\\0 vWUW~x\\0 vUW\"\n  \"V}x\\0 uUTU}x\\0 tVUV|x\\0 tT|T\\134\\30\\0\\30<\\244\\244\"\n  \"d$$\\0\\70|UVT\\134\\30\\0\\70|TVU\\134\\30\\0\\70~WUW^\\30\\0\\70}UT\"\n  \"U]\\30\\0\\0@Izx@@\\0\\0@Hzy@@\\0\\0BKy{B@\\0\\0AE|\"\n  \"}A@\\0\\64{KNNy\\60\\0|~\\5\\7\\6}x\\0\\70|EFD|\\70\\0\\70|DF\"\n  \"E|\\70\\0\\70~GEG~\\70\\0\\70~EGF}\\70\\0\\70}EDE}\\70\\0\\0\\10\\10*\"\n  \"*\\10\\10\\0\\70|dTL|\\70\\0<|AB@||\\0<|@BA||\\0\\70zCA\"\n  \"Czx\\0<}A@A}|\\0\\34\\274\\240\\242\\241\\374|\\0\\377\\377$$$<\\30\\0\\34\\275\\241\\240\"\n  \"\\241\\375|\";\n/*\n  Fontname: -FreeType-Press Start 2P-Medium-R-Normal--8-80-72-72-P-69-ISO10646-1\n  Copyright: (c) 2011 Cody \n  Glyphs: 96/556\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pressstart2p_r[772] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\7\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\42\\177\\177\\42\"\n  \"\\177\\177\\42\\0$.*\\177*:\\20\\0F%\\23\\10dR\\61\\0\\66\\177I_v`P\\0\\0\\0\\7\\7\"\n  \"\\0\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\200\\340`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0``\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\34>aAC>\\34\\0\\0@B\\177\\177@@\\0bsyY]OF\\0 aIM\"\n  \"O{\\61\\0\\30\\34\\26\\23\\177\\177\\20\\0'gEEE}\\70\\0<~KIIy\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66OMYYv\\60\\0\\6OIIi\\77\\36\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\24\\0\\0Ac\\66\\34\\10\\0\\0\\6\\7SS\"\n  \"[\\17\\6\\0>A]U]Q\\36\\0|~\\23\\21\\23~|\\0\\177\\177III\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0\\177\\177AAc>\\34\\0\\177\\177IIIIA\\0\\177\\177\\11\\11\\11\\11\\1\\0\\34>cA\"\n  \"Iyy\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0 `@@@\\177\\77\\0\\177\\177\\30<\"\n  \"vcA\\0\\0\\177\\177@@@@\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\16\\34\\70\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0\\177\\177\\21\\21\\21\\37\\16\\0>\\177AQq\\77^\\0\\177\\177\\21\\61yoN\\0&oII\"\n  \"Kz\\60\\0\\0\\1\\1\\177\\177\\1\\1\\0\\77\\177@@@\\177\\77\\0\\17\\37\\70p\\70\\37\\17\\0\\177\\177\\70\\34\"\n  \"\\70\\177\\177\\0cw>\\34>wc\\0\\0\\7\\17xx\\17\\7\\0aqy]OGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AA\\177\\177\\0\\0\\0\\0\\2\\3\\1\\3\\2\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\0\\0\\0\\0\\1\\2\\0\\0\\0 tTTT|x\\0\\77\\177DDD|\\70\\0\\70|DD\"\n  \"DDD\\0\\70|DDD\\177\\177\\0\\70|TTT\\134\\30\\0\\0\\4\\4~\\177\\5\\5\\0\\30\\274\\244\\244\"\n  \"\\244\\374|\\0\\177\\177\\4\\4\\4|x\\0\\0@D}}@@\\0\\0\\200\\200\\204\\375}\\0\\0\\177\\177\\30\\70\"\n  \"|lD\\0\\0@A\\177\\177@@\\0|\\4||\\4|x\\0||\\4\\4\\4|x\\0\\70|DD\"\n  \"D|\\70\\0\\374\\374$$$<\\30\\0\\30<$$$\\374\\374\\0\\0||\\10\\4\\4\\4\\0H\\134TT\"\n  \"Tt \\0\\0\\4\\4\\177\\177\\4\\4\\0<|@@@||\\0\\0\\34<``<\\34\\0<@||\"\n  \"@||\\0ll\\70\\70\\70ll\\0\\34\\274\\240\\240\\240\\374|\\0Ddt|\\134LD\\0\\0\\0\\10>\"\n  \"wA\\0\\0\\0\\0\\0\\177\\177\\0\\0\\0\\0Aw>\\10\\0\\0\\0\\10\\4\\14\\34\\30\\20\\10\\0\\0``\\0\"\n  \"``\\0\";\n/*\n  Fontname: -FreeType-Press Start 2P-Medium-R-Normal--8-80-72-72-P-69-ISO10646-1\n  Copyright: (c) 2011 Cody \n  Glyphs: 18/556\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pressstart2p_n[220] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\200\\340`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0``\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\34>aAC>\\34\\0\\0@B\\177\\177@@\\0bsyY]OF\\0 aIM\"\n  \"O{\\61\\0\\30\\34\\26\\23\\177\\177\\20\\0'gEEE}\\70\\0<~KIIy\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66OMYYv\\60\\0\\6OIIi\\77\\36\\0\\0\\0\\66\\66\\0\\0\\0\";\n/*\n  Fontname: -FreeType-Press Start 2P-Medium-R-Normal--8-80-72-72-P-69-ISO10646-1\n  Copyright: (c) 2011 Cody \n  Glyphs: 64/556\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pressstart2p_u[516] U8X8_FONT_SECTION(\"u8x8_font_pressstart2p_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0__\\7\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\42\\177\\177\\42\"\n  \"\\177\\177\\42\\0$.*\\177*:\\20\\0F%\\23\\10dR\\61\\0\\66\\177I_v`P\\0\\0\\0\\7\\7\"\n  \"\\0\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34>*\\10\\0\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\200\\340`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0``\\0\\0\\0\\0@ \\20\\10\"\n  \"\\4\\2\\1\\0\\34>aAC>\\34\\0\\0@B\\177\\177@@\\0bsyY]OF\\0 aIM\"\n  \"O{\\61\\0\\30\\34\\26\\23\\177\\177\\20\\0'gEEE}\\70\\0<~KIIy\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66OMYYv\\60\\0\\6OIIi\\77\\36\\0\\0\\0\\66\\66\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\24\\24\\24\\24\\24\\24\\24\\0\\0Ac\\66\\34\\10\\0\\0\\6\\7SS\"\n  \"[\\17\\6\\0>A]U]Q\\36\\0|~\\23\\21\\23~|\\0\\177\\177III\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0\\177\\177AAc>\\34\\0\\177\\177IIIIA\\0\\177\\177\\11\\11\\11\\11\\1\\0\\34>cA\"\n  \"Iyy\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0AA\\177\\177AA\\0 `@@@\\177\\77\\0\\177\\177\\30<\"\n  \"vcA\\0\\0\\177\\177@@@@\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\16\\34\\70\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0\\177\\177\\21\\21\\21\\37\\16\\0>\\177AQq\\77^\\0\\177\\177\\21\\61yoN\\0&oII\"\n  \"Kz\\60\\0\\0\\1\\1\\177\\177\\1\\1\\0\\77\\177@@@\\177\\77\\0\\17\\37\\70p\\70\\37\\17\\0\\177\\177\\70\\34\"\n  \"\\70\\177\\177\\0cw>\\34>wc\\0\\0\\7\\17xx\\17\\7\\0aqy]OGC\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AA\\177\\177\\0\\0\\0\\0\\2\\3\\1\\3\\2\\0\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\";\n/*\n  Fontname: -FreeType-PC Senior-Medium-R-Normal--8-80-72-72-P-48-ISO10646-1\n  Copyright: TrueType conversion  2001 codeman38.\n  Glyphs: 192/260\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pcsenior_f[1796] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIof\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346f\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0&oMY\"\n  \"s\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\3\\7\\4\\0\\0\\0 tTT<x@\\0A\\177\\77HHx\\60\\0\\70|DD\"\n  \"l(\\0\\0\\60xHI\\77\\177@\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0A\\177\\177@\\0\\0\\0||\\30\\70\\34|x\\0||\\4\\4|x\\0\\0\\70|DD\"\n  \"|\\70\\0\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\34\\30\\0H\\134TT\"\n  \"t$\\0\\0\\0\\4>\\177D$\\0\\0<|@@<|@\\0\\34<``<\\34\\0\\0<|p\\70\"\n  \"p|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>w\"\n  \"AA\\0\\0\\0\\0\\0ww\\0\\0\\0AAw>\\10\\10\\0\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0{{\\0\\0\\0\\30<$\\347\\347$$\\0h~\\177I\"\n  \"Cf \\0\\0\\0\\0\\0\\0\\0\\0\\0+/\\374\\374/+\\0\\0\\0\\0\\0ww\\0\\0\\0@\\332\\277\\245\"\n  \"\\375Y\\3\\2\\0\\0\\0\\0\\0\\0\\0\\0~\\201\\225\\261\\261\\225\\201~\\0&/)//(\\0\\10\\34\\66\\42\"\n  \"\\10\\34\\66\\42\\10\\10\\10\\10\\70\\70\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\300\\377\\177\\5\\5e\\177\\77\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\6\\17\\11\\17\\6\\0\\0DD__DD\\0\\0\\0\\31\\35\\27\\22\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\376~  >\\36\\0\\6\\17\\11\\177\\177\\1\\177\\177\\0\\0\\0\\30\"\n  \"\\30\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0&/)/&\\0\\0\\42\\66\\34\\10\"\n  \"\\42\\66\\34\\10Oo\\60\\30lv\\373\\371o_(\\324\\262\\325\\253\\221\\0\\0\\0\\0\\0\\0\\0\\0\\60xME\"\n  \"` \\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0y}\\26\\22\\26}y\\0px++xp\\0\\0|~\\13\\11\\177\\177I\\0\\16\\237\\221\\261\"\n  \"\\373J\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0D||UUE\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0}}\\31\\61}}\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\31<ff<\\31\\1\\42\\66\\34\\10\"\n  \"\\34\\66\\42\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0=}@@}=\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\376**\"\n  \">\\24\\0\\0!uUT|x@\\0 tTU}y@\\0\\2#uUU}{B\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0!uTT}y@\\0 tWW|x@\\0 tTT||TT\\30<\\244\\244\"\n  \"\\344@\\0\\0\\71}UT\\134\\30\\0\\0\\70|TU]\\31\\0\\0\\2;}UU]\\33\\2\\71}TT\"\n  \"]\\31\\0\\0\\1E}|@\\0\\0\\0\\0D}}A\\0\\0\\0\\2\\3E}}C\\2\\0\\1E||\"\n  \"A\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0zz\\12\\12zp\\0\\0\\62zJHx\\60\\0\\0\\60xHJ\"\n  \"z\\62\\0\\0\\62{II{\\62\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\62zHHz\\62\\0\\0\\10\\10kk\"\n  \"\\10\\10\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0:zB@xx@\\0\\70x@Bzz@\\0:{AA\"\n  \"{z@\\0:z@@zz@\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\232\\272\\240\\240\"\n  \"\\372z\\0\";\n/*\n  Fontname: -FreeType-PC Senior-Medium-R-Normal--8-80-72-72-P-48-ISO10646-1\n  Copyright: TrueType conversion  2001 codeman38.\n  Glyphs: 96/260\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pcsenior_r[772] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIof\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346f\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0&oMY\"\n  \"s\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\3\\7\\4\\0\\0\\0 tTT<x@\\0A\\177\\77HHx\\60\\0\\70|DD\"\n  \"l(\\0\\0\\60xHI\\77\\177@\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0A\\177\\177@\\0\\0\\0||\\30\\70\\34|x\\0||\\4\\4|x\\0\\0\\70|DD\"\n  \"|\\70\\0\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\34\\30\\0H\\134TT\"\n  \"t$\\0\\0\\0\\4>\\177D$\\0\\0<|@@<|@\\0\\34<``<\\34\\0\\0<|p\\70\"\n  \"p|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>w\"\n  \"AA\\0\\0\\0\\0\\0ww\\0\\0\\0AAw>\\10\\10\\0\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\";\n/*\n  Fontname: -FreeType-PC Senior-Medium-R-Normal--8-80-72-72-P-48-ISO10646-1\n  Copyright: TrueType conversion  2001 codeman38.\n  Glyphs: 18/260\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pcsenior_n[220] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIof\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\";\n/*\n  Fontname: -FreeType-PC Senior-Medium-R-Normal--8-80-72-72-P-48-ISO10646-1\n  Copyright: TrueType conversion  2001 codeman38.\n  Glyphs: 64/260\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pcsenior_u[517] U8X8_FONT_SECTION(\"u8x8_font_pcsenior_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIof\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346f\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0&oMY\"\n  \"s\\62\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGAthin-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 192/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcgathin_f[1796] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6_\\6\\0\\0\\0\\0\\0\\7\\0\\0\\7\\0\\0\\0\\24\\177\\24\"\n  \"\\24\\177\\24\\0\\0$*kk*\\22\\0\\0F&\\20\\10db\\0\\60JEM\\62HH\\0\\0\\0\\4\\3\"\n  \"\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\10*\\34\\34\\34*\\10\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0`\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>aQIE>\\0\\0DB\\177@@\\0\\0\\0bQQIIf\\0\\0\\42AI\"\n  \"II\\66\\0\\20\\30\\24R\\177P\\20\\0\\0'EEEE\\71\\0\\0<JIII\\60\\0\\0\\3\\1q\"\n  \"\\11\\5\\3\\0\\0\\66IIII\\66\\0\\0\\6III)\\36\\0\\0\\0\\0f\\0\\0\\0\\0\\0\\0\\200f\"\n  \"\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\0$$$$$$\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1\\1\"\n  \"Q\\11\\6\\0\\0>A]UU\\36\\0\\0|\\22\\21\\21\\22|\\0\\0A\\177III\\66\\0\\0\\34\\42A\"\n  \"AA\\42\\0\\0A\\177AA\\42\\34\\0\\0A\\177I]Ac\\0\\0A\\177I\\35\\1\\3\\0\\0\\34\\42A\"\n  \"QQr\\0\\0\\177\\10\\10\\10\\10\\177\\0\\0\\0A\\177A\\0\\0\\0\\0\\60@@A\\77\\1\\0\\0A\\177\\10\"\n  \"\\24\\42A@\\0A\\177A@@`\\0\\0\\177\\1\\2\\4\\2\\1\\177\\0\\177\\1\\2\\4\\10\\177\\0\\0\\34\\42A\"\n  \"A\\42\\34\\0\\0A\\177I\\11\\11\\6\\0\\0\\36!!\\61!^@\\0A\\177I\\31)F\\0\\0&II\"\n  \"II\\62\\0\\0\\3\\1A\\177A\\1\\3\\0\\77@@@@\\77\\0\\0\\17\\20 @ \\20\\17\\0\\77@@\"\n  \"\\70@@\\77\\0A\\42\\24\\10\\24\\42A\\0\\1\\2DxD\\2\\1\\0CaQIECa\\0\\177AA\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AAA\\177\\0\\0\\0\\10\\4\\2\\1\\2\\4\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\3\\4\\0\\0\\0\\0 TTTTx@\\0\\1\\177\\60HHH\\60\\0\\70DD\"\n  \"DD(\\0\\0\\60HHH\\61\\177@\\0\\70TTTT\\30\\0\\0\\0H~I\\1\\2\\0\\0\\230\\244\\244\"\n  \"\\244\\244x\\4\\0A\\177\\10\\4\\4x\\0\\0\\0D}@\\0\\0\\0\\0`\\200\\200\\200\\204}\\0\\0\\1\\177\\20\"\n  \"(D@\\0\\0\\0A\\177@\\0\\0\\0\\0|\\4\\4x\\4\\4x\\0|\\10\\4\\4\\4x\\0\\0\\70DD\"\n  \"DD\\70\\0\\0\\204\\374\\230$$\\30\\0\\0\\30$$\\230\\374\\204\\0\\0D|H\\4\\4\\30\\0\\0HTT\"\n  \"TT$\\0\\0\\4\\4\\77DD \\0\\0<@@@ |\\0\\0\\14\\20 @ \\20\\14\\0<@@\"\n  \"\\70@@<\\0D(\\20(D\\0\\0\\0\\234\\240\\240\\240\\240|\\0\\0DdTLD\\0\\0\\0\\10\\10\\66\"\n  \"AA\\0\\0\\0\\0\\0w\\0\\0\\0\\0\\0\\0AA\\66\\10\\10\\0\\0\\2\\1\\1\\2\\2\\1\\0\\0pHD\"\n  \"BDHp\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0z\\0\\0\\0\\0\\0\\30$$\\347$$\\0\\0h^I\"\n  \"AB \\0BZ$$$ZB\\0\\0\\25\\26|\\26\\25\\0\\0\\0\\0\\0w\\0\\0\\0\\0@\\332\\247\\245\"\n  \"\\345Y\\3\\2\\0\\1\\0\\0\\0\\1\\0\\0~\\201\\231\\245\\245\\201~\\0\\0&)))/(\\0\\0\\10\\24\\42\"\n  \"\\10\\24\\42\\0\\0\\10\\10\\10\\10\\10\\70\\0\\0\\10\\10\\10\\10\\10\\10\\0~\\201\\275\\225\\251\\201~\\0\\1\\1\\1\\1\"\n  \"\\1\\1\\1\\1\\0\\6\\11\\11\\6\\0\\0\\0\\0DD_DD\\0\\0\\0\\22\\31\\25\\22\\0\\0\\0\\0\\12\\21\\25\"\n  \"\\12\\0\\0\\0\\0\\0\\0\\2\\1\\0\\0\\0\\200~\\20\\20\\20\\16\\20\\0\\6\\11\\11\\177\\1\\1\\177\\1\\0\\0\\0\\20\"\n  \"\\20\\0\\0\\0\\0\\0\\200\\200\\240@\\0\\0\\0\\22\\37\\20\\0\\0\\0\\0\\0&)))&\\0\\0\\0\\42\\24\\10\"\n  \"\\42\\24\\10\\0J/\\30(\\64*\\375 J/\\30\\210\\324\\312\\251\\260\\225U*PhT\\372@\\0\\60HE\"\n  \"@@ \\0\\1y\\24\\22\\22\\24x\\0\\0x\\24\\22\\22\\24y\\1\\0r)%%)r\\0\\0y\\25\\25\"\n  \"\\25\\25y\\0\\0y\\24\\22\\22\\24y\\0\\0p(++(p\\0\\0|\\12\\11\\11\\177II\\0\\16\\221\\221\"\n  \"\\261\\261J\\0\\0E}TTD\\0\\0\\0D|TUE\\0\\0\\2E}UUE\\2\\0\\0E|T\"\n  \"TE\\0\\0\\0\\1E|D\\0\\0\\0\\0\\0D|E\\1\\0\\0\\2\\1E}E\\1\\2\\0\\0\\1D|\"\n  \"D\\1\\0\\0\\0I\\177IA\\42\\34\\0\\0z\\11\\21\\42Cx\\0\\1\\31$BB$\\30\\0\\0\\30$B\"\n  \"B$\\31\\1\\22)EEE)\\22\\0\\0\\21)EEE)\\21\\0\\31$BB$\\31\\0\\0\\42\\24\\10\"\n  \"\\24\\42\\0\\0>qYIMG>\\0\\0=A@@@<\\0\\0<@@@A=\\0\\0:AA\"\n  \"AA:\\0\\0=@@@@=\\0\\0\\4HpH\\5\\1\\0\\0A\\177U\\24\\24\\10\\0\\0~\\1\\1\"\n  \"IV \\0\\0 UUTx@\\0\\0 TTUy@\\0\\0\\42UUUyB\\0\\0!UU\"\n  \"UUy@\\0!TTTxA\\0\\0 TUTx@\\0\\0 TTx\\70TT\\0\\30$\\244\"\n  \"\\244\\344@\\0\\0\\70UUTT\\30\\0\\0\\70TTUU\\30\\0\\0:UUUU\\32\\0\\0\\71TT\"\n  \"TT\\31\\0\\0\\0\\1E|@\\0\\0\\0\\0\\0D}A\\0\\0\\2\\1E}A\\2\\0\\0\\0\\0\\1D\"\n  \"|A\\0\\0\\0\\60JJK>\\2\\0\\0z\\11\\11\\12\\12q\\0\\0\\60IJHH\\60\\0\\0\\60HH\"\n  \"JI\\60\\0\\0\\60JIIJ\\60\\0\\0\\62JJJJ\\62\\0\\0\\62HHHH\\62\\0\\0\\10\\10k\"\n  \"k\\10\\10\\0\\270DdTLD:\\0\\0\\70AB@@\\70\\0\\0\\70@@DB\\70\\0\\0\\70BA\"\n  \"AB\\70\\0\\0:@@@z@\\0\\0\\30\\240\\240\\240\\242z\\0\\0\\201\\377\\244$$\\30\\0\\0\\32\\240\\240\"\n  \"\\240\\240z\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGAthin-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 96/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcgathin_r[773] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6_\\6\\0\\0\\0\\0\\0\\7\\0\\0\\7\\0\\0\\0\\24\\177\\24\"\n  \"\\24\\177\\24\\0\\0$*kk*\\22\\0\\0F&\\20\\10db\\0\\60JEM\\62HH\\0\\0\\0\\4\\3\"\n  \"\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\10*\\34\\34\\34*\\10\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0`\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>aQIE>\\0\\0DB\\177@@\\0\\0\\0bQQIIf\\0\\0\\42AI\"\n  \"II\\66\\0\\20\\30\\24R\\177P\\20\\0\\0'EEEE\\71\\0\\0<JIII\\60\\0\\0\\3\\1q\"\n  \"\\11\\5\\3\\0\\0\\66IIII\\66\\0\\0\\6III)\\36\\0\\0\\0\\0f\\0\\0\\0\\0\\0\\0\\200f\"\n  \"\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\0$$$$$$\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1\\1\"\n  \"Q\\11\\6\\0\\0>A]UU\\36\\0\\0|\\22\\21\\21\\22|\\0\\0A\\177III\\66\\0\\0\\34\\42A\"\n  \"AA\\42\\0\\0A\\177AA\\42\\34\\0\\0A\\177I]Ac\\0\\0A\\177I\\35\\1\\3\\0\\0\\34\\42A\"\n  \"QQr\\0\\0\\177\\10\\10\\10\\10\\177\\0\\0\\0A\\177A\\0\\0\\0\\0\\60@@A\\77\\1\\0\\0A\\177\\10\"\n  \"\\24\\42A@\\0A\\177A@@`\\0\\0\\177\\1\\2\\4\\2\\1\\177\\0\\177\\1\\2\\4\\10\\177\\0\\0\\34\\42A\"\n  \"A\\42\\34\\0\\0A\\177I\\11\\11\\6\\0\\0\\36!!\\61!^@\\0A\\177I\\31)F\\0\\0&II\"\n  \"II\\62\\0\\0\\3\\1A\\177A\\1\\3\\0\\77@@@@\\77\\0\\0\\17\\20 @ \\20\\17\\0\\77@@\"\n  \"\\70@@\\77\\0A\\42\\24\\10\\24\\42A\\0\\1\\2DxD\\2\\1\\0CaQIECa\\0\\177AA\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AAA\\177\\0\\0\\0\\10\\4\\2\\1\\2\\4\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\0\\3\\4\\0\\0\\0\\0 TTTTx@\\0\\1\\177\\60HHH\\60\\0\\70DD\"\n  \"DD(\\0\\0\\60HHH\\61\\177@\\0\\70TTTT\\30\\0\\0\\0H~I\\1\\2\\0\\0\\230\\244\\244\"\n  \"\\244\\244x\\4\\0A\\177\\10\\4\\4x\\0\\0\\0D}@\\0\\0\\0\\0`\\200\\200\\200\\204}\\0\\0\\1\\177\\20\"\n  \"(D@\\0\\0\\0A\\177@\\0\\0\\0\\0|\\4\\4x\\4\\4x\\0|\\10\\4\\4\\4x\\0\\0\\70DD\"\n  \"DD\\70\\0\\0\\204\\374\\230$$\\30\\0\\0\\30$$\\230\\374\\204\\0\\0D|H\\4\\4\\30\\0\\0HTT\"\n  \"TT$\\0\\0\\4\\4\\77DD \\0\\0<@@@ |\\0\\0\\14\\20 @ \\20\\14\\0<@@\"\n  \"\\70@@<\\0D(\\20(D\\0\\0\\0\\234\\240\\240\\240\\240|\\0\\0DdTLD\\0\\0\\0\\10\\10\\66\"\n  \"AA\\0\\0\\0\\0\\0w\\0\\0\\0\\0\\0\\0AA\\66\\10\\10\\0\\0\\2\\1\\1\\2\\2\\1\\0\\0pHD\"\n  \"BDHp\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGAthin-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 18/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcgathin_n[220] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*\\34\\34\\34*\\10\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0`\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>aQIE>\\0\\0DB\\177@@\\0\\0\\0bQQIIf\\0\\0\\42AI\"\n  \"II\\66\\0\\20\\30\\24R\\177P\\20\\0\\0'EEEE\\71\\0\\0<JIII\\60\\0\\0\\3\\1q\"\n  \"\\11\\5\\3\\0\\0\\66IIII\\66\\0\\0\\6III)\\36\\0\\0\\0\\0f\\0\\0\\0\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGAthin-Medium-R-Normal--8-80-72-72-P-64-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 64/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcgathin_u[517] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcgathin_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6_\\6\\0\\0\\0\\0\\0\\7\\0\\0\\7\\0\\0\\0\\24\\177\\24\"\n  \"\\24\\177\\24\\0\\0$*kk*\\22\\0\\0F&\\20\\10db\\0\\60JEM\\62HH\\0\\0\\0\\4\\3\"\n  \"\\0\\0\\0\\0\\0\\34\\42A\\0\\0\\0\\0\\0\\0A\\42\\34\\0\\0\\0\\10*\\34\\34\\34*\\10\\0\\0\\10\\10>\"\n  \"\\10\\10\\0\\0\\0\\0\\200`\\0\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0`\\0\\0\\0\\0\\0@ \\20\"\n  \"\\10\\4\\2\\0\\0>aQIE>\\0\\0DB\\177@@\\0\\0\\0bQQIIf\\0\\0\\42AI\"\n  \"II\\66\\0\\20\\30\\24R\\177P\\20\\0\\0'EEEE\\71\\0\\0<JIII\\60\\0\\0\\3\\1q\"\n  \"\\11\\5\\3\\0\\0\\66IIII\\66\\0\\0\\6III)\\36\\0\\0\\0\\0f\\0\\0\\0\\0\\0\\0\\200f\"\n  \"\\0\\0\\0\\0\\0\\10\\24\\42A\\0\\0\\0\\0$$$$$$\\0\\0\\0\\0A\\42\\24\\10\\0\\0\\2\\1\\1\"\n  \"Q\\11\\6\\0\\0>A]UU\\36\\0\\0|\\22\\21\\21\\22|\\0\\0A\\177III\\66\\0\\0\\34\\42A\"\n  \"AA\\42\\0\\0A\\177AA\\42\\34\\0\\0A\\177I]Ac\\0\\0A\\177I\\35\\1\\3\\0\\0\\34\\42A\"\n  \"QQr\\0\\0\\177\\10\\10\\10\\10\\177\\0\\0\\0A\\177A\\0\\0\\0\\0\\60@@A\\77\\1\\0\\0A\\177\\10\"\n  \"\\24\\42A@\\0A\\177A@@`\\0\\0\\177\\1\\2\\4\\2\\1\\177\\0\\177\\1\\2\\4\\10\\177\\0\\0\\34\\42A\"\n  \"A\\42\\34\\0\\0A\\177I\\11\\11\\6\\0\\0\\36!!\\61!^@\\0A\\177I\\31)F\\0\\0&II\"\n  \"II\\62\\0\\0\\3\\1A\\177A\\1\\3\\0\\77@@@@\\77\\0\\0\\17\\20 @ \\20\\17\\0\\77@@\"\n  \"\\70@@\\77\\0A\\42\\24\\10\\24\\42A\\0\\1\\2DxD\\2\\1\\0CaQIECa\\0\\177AA\"\n  \"A\\0\\0\\0\\1\\2\\4\\10\\20 @\\0\\0AAA\\177\\0\\0\\0\\10\\4\\2\\1\\2\\4\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGA-Medium-R-Normal--8-80-72-72-P-68-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 192/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcga_f[1796] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIOf\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0\\42gMY\"\n  \"s\\42\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\3\\7\\4\\0\\0\\0 tTT<x@\\0A\\177\\77HHx\\60\\0\\70|DD\"\n  \"l(\\0\\0\\60xHI\\77\\177@\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0A\\177\\177@\\0\\0\\0||\\30\\70\\34|x\\0||\\4\\4|x\\0\\0\\70|DD\"\n  \"|\\70\\0\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\34\\30\\0H\\134TT\"\n  \"t$\\0\\0\\0\\4>\\177D$\\0\\0<|@@<|@\\0\\34<``<\\34\\0\\0<|p\\70\"\n  \"p|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>w\"\n  \"AA\\0\\0\\0\\0\\0ww\\0\\0\\0AAw>\\10\\10\\0\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0{{\\0\\0\\0\\30<$\\347\\347$$\\0h~\\177I\"\n  \"Cf \\0Z~$$$~Z\\0+/\\374\\374/+\\0\\0\\0\\0\\0ww\\0\\0\\0@\\332\\277\\245\"\n  \"\\375Y\\3\\2\\1\\1\\0\\0\\0\\1\\1\\0~\\201\\231\\245\\245\\201~\\0\\0&/)//(\\0\\10\\34\\66\\42\"\n  \"\\10\\34\\66\\42\\10\\10\\10\\10\\70\\70\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0~\\201\\275\\225\\251\\201~\\0\\1\\1\\1\\1\"\n  \"\\1\\1\\1\\1\\0\\6\\17\\11\\17\\6\\0\\0DD__DD\\0\\0\\0\\31\\35\\27\\22\\0\\0\\0\\0\\21\\25\\37\"\n  \"\\12\\0\\0\\0\\0\\0\\2\\3\\1\\0\\0\\0\\200\\376~  >\\36\\0\\6\\17\\11\\177\\177\\1\\177\\177\\0\\0\\0\\20\"\n  \"\\20\\0\\0\\0\\0\\0\\200\\240\\340@\\0\\0\\0\\22\\37\\37\\20\\0\\0\\0\\0&/)/&\\0\\0\\42\\66\\34\\10\"\n  \"\\42\\66\\34\\10Oo\\60\\30lv\\373\\371Oo\\60\\30\\314\\356\\273\\221\\221\\325\\177:Xl\\366\\362\\60xME\"\n  \"` \\0\\0y}\\26\\22\\26|x\\0x|\\26\\22\\26}y\\0r{)){r\\0\\0y}\\25\\25\"\n  \"}y\\0\\0y}\\26\\22\\26}y\\0px++xp\\0\\0|~\\13\\11\\177\\177I\\0\\16\\237\\221\\261\"\n  \"\\373J\\0\\0E}}TTD\\0\\0D||UUE\\0\\0F\\177}UWF\\0\\0E}|T\"\n  \"UE\\0\\0\\1E}|D\\0\\0\\0\\0D|}E\\1\\0\\0\\2KyyK\\2\\0\\0\\1E||\"\n  \"E\\1\\0\\0I\\177\\177Ic>\\34\\0}}\\31\\61}}\\0\\0\\1\\31<ff<\\30\\0\\30<ff\"\n  \"<\\31\\1\\0\\22;mEm;\\22\\0\\21\\71mEm\\71\\21\\0\\1\\31<ff<\\31\\1\\42\\66\\34\\10\"\n  \"\\34\\66\\42\\0>\\177qYM\\177>\\0=}A@|<\\0\\0<|@A}=\\0\\0:{AA\"\n  \"{:\\0\\0=}@@}=\\0\\0\\14\\134pq]\\15\\0\\0A\\177\\177U\\24\\34\\10\\0~\\177\\1\\11\"\n  \"_v \\0!uUT|x@\\0 tTU}y@\\0\\2#uUU}{B!uUU\"\n  \"}y@\\0!uTT}y@\\0 tWW|x@\\0 tTT||TT\\30<\\244\\244\"\n  \"\\344@\\0\\0\\71}UT\\134\\30\\0\\0\\70|TU]\\31\\0\\0\\2;}UU]\\33\\2\\71}TT\"\n  \"]\\31\\0\\0\\1E}|@\\0\\0\\0\\0D}}A\\0\\0\\0\\2\\3E}}C\\2\\0\\1E||\"\n  \"A\\1\\0\\0\\60xJK\\177>\\2\\0zz\\12\\12zp\\0\\0\\62zJHx\\60\\0\\0\\60xHJ\"\n  \"z\\62\\0\\0\\62{II{\\62\\0\\0\\62zJJz\\62\\0\\0\\62zHHz\\62\\0\\0\\10\\10kk\"\n  \"\\10\\10\\0\\0\\270|dTL|:\\0:zB@xx@\\0\\70x@Bzz@\\0:{AA\"\n  \"{z@\\0:z@@zz@\\0\\30\\270\\240\\242\\372z\\0\\0\\201\\377\\377\\244$<\\30\\0\\232\\272\\240\\240\"\n  \"\\372z\\0\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGA-Medium-R-Normal--8-80-72-72-P-68-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 96/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcga_r[772] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIOf\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0\\42gMY\"\n  \"s\\42\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\3\\7\\4\\0\\0\\0 tTT<x@\\0A\\177\\77HHx\\60\\0\\70|DD\"\n  \"l(\\0\\0\\60xHI\\77\\177@\\0\\70|TT\\134\\30\\0\\0H~\\177I\\3\\2\\0\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0A\\177\\177@\\0\\0\\0||\\30\\70\\34|x\\0||\\4\\4|x\\0\\0\\70|DD\"\n  \"|\\70\\0\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\34\\30\\0H\\134TT\"\n  \"t$\\0\\0\\0\\4>\\177D$\\0\\0<|@@<|@\\0\\34<``<\\34\\0\\0<|p\\70\"\n  \"p|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>w\"\n  \"AA\\0\\0\\0\\0\\0ww\\0\\0\\0AAw>\\10\\10\\0\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGA-Medium-R-Normal--8-80-72-72-P-68-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 18/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcga_n[220] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIOf\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\";\n/*\n  Fontname: -FreeType-PxPlus IBM CGA-Medium-R-Normal--8-80-72-72-P-68-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 64/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplusibmcga_u[517] U8X8_FONT_SECTION(\"u8x8_font_pxplusibmcga_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\0\\7\\7\\0\\7\\7\\0\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0$.kk:\\22\\0\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\4\\7\\3\\0\"\n  \"\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\0\\10*>\\34\\34>*\\10\\10\\10>>\"\n  \"\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0>\\177qYM\\177>\\0@B\\177\\177@@\\0\\0bsYIOf\\0\\0\\42cII\"\n  \"\\177\\66\\0\\0\\30\\34\\26S\\177\\177P\\0'gEE}\\71\\0\\0<~KIy\\60\\0\\0\\3\\3qy\"\n  \"\\17\\7\\0\\0\\66\\177II\\177\\66\\0\\0\\6OIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0@v\\66\"\n  \"\\0\\0\\0\\0\\10\\34\\66cA\\0\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\0\\2\\3QY\"\n  \"\\17\\6\\0\\0>\\177A]]\\37\\36\\0|~\\23\\23~|\\0\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Qsr\\0\\177\\177\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0\\34>cA\"\n  \"c>\\34\\0A\\177\\177I\\11\\17\\6\\0\\36\\77!q\\177^\\0\\0A\\177\\177\\11\\31\\177f\\0\\42gMY\"\n  \"s\\42\\0\\0\\3A\\177\\177A\\3\\0\\0\\177\\177@@\\177\\177\\0\\0\\37\\77``\\77\\37\\0\\0\\177\\177\\60\\30\"\n  \"\\60\\177\\177\\0Cg<\\30<gC\\0\\7OxxO\\7\\0\\0GcqYMgs\\0\\0\\177\\177A\"\n  \"A\\0\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0AA\\177\\177\\0\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FreeType-PxPlus TandyNew TV-Medium-R-Normal--8-80-72-72-P-70-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 192/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplustandynewtv_f[1796] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_f\") = \n  \" \\377\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\3\\7\\0\\0\\7\\3\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0\\0$.kk:\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\4\\7\"\n  \"\\3\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0\\34>cIc>\\34\\0\\0@B\\177\\177@@\\0BcqYIof\\0\\42cII\"\n  \"I\\177\\66\\0\\30\\34\\26S\\177\\177P\\0/oIIIy\\61\\0<~KIIx\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66\\177III\\177\\66\\0\\6OIIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346\"\n  \"f\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\2\\3\\1Y\"\n  \"]\\7\\2\\0>\\177A]]\\37\\36\\0|~\\13\\11\\13~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Q\\63r\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0A\\177\\177I\\11\\17\\6\\0>\\177AA\\341\\377\\276\\0A\\177\\177\\11\\31wf\\0\\0\\42gM\"\n  \"Ys\\42\\0\\0\\3A\\177\\177A\\3\\0\\77\\177@@@\\177\\77\\0\\37\\77`@`\\77\\37\\0\\77\\177`\\70\"\n  \"`\\177\\77\\0cw\\34\\10\\34wc\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\1\\3\\6\\4\\0\\0 tTT<x@\\0A\\177\\77DD|\\70\\0\\70|DD\"\n  \"Dl(\\0\\70|DE\\77\\177@\\0\\70|TTT\\134\\30\\0H~\\177I\\11\\3\\2\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0A\\177\\177@\\0\\0||\\14x\\14|x\\0\\4|x\\4\\4|x\\0\\70|DD\"\n  \"D|\\70\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\14\\10\\0H\\134TT\"\n  \"Tt$\\0\\4\\4\\77\\177Dd \\0<|@@<|@\\0\\34<`@`<\\34\\0<|`\\70\"\n  \"`|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>\"\n  \"wAA\\0\\0\\0\\0\\357\\357\\0\\0\\0\\0AAw>\\10\\10\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\60}}\\60\\0\\0\\30<$\\347\\347$$\\0\\0h~\\177\"\n  \"ICf Z~$$$~Z\\0\\0+/\\374\\374/+\\0\\0\\0\\0\\357\\357\\0\\0\\0@\\232\\277\\245\"\n  \"\\245\\375Y\\2\\2\\2\\0\\0\\0\\2\\2\\0~\\201\\231\\245\\245\\245\\201~\\0&/)//(\\0\\10\\34\\66\\42\"\n  \"\\10\\34\\66\\42\\0\\10\\10\\10\\10\\70\\70\\0\\0\\10\\10\\10\\10\\10\\10\\0~\\201\\275\\225\\225\\251\\201~\\1\\1\\1\\1\"\n  \"\\1\\1\\1\\1\\0\\6\\17\\11\\17\\6\\0\\0\\0DD__DD\\0\\0\\21\\31\\35\\27\\22\\0\\0\\0\\21\\25\\25\"\n  \"\\37\\12\\0\\0\\0\\0\\4\\6\\3\\1\\0\\0\\0\\200\\376~  >\\36\\6\\17\\11\\177\\177\\1\\177\\177\\0\\0\\0\\20\"\n  \"\\20\\0\\0\\0\\0\\0\\200\\240\\340@\\0\\0\\0\\0\\22\\37\\37\\20\\0\\0\\0&/)/&\\0\\0\\42\\66\\34\\10\"\n  \"\\42\\66\\34\\10Bo\\77Xl\\326\\373ABo\\77\\30\\314\\356\\273\\221\\225U\\77Zh\\324\\372A\\0 p]\"\n  \"M@` px,%/zp\\0pz/%,xp\\0pz-%-zp\\0r{-'\"\n  \".{q\\0y}\\26\\22\\26}y\\0x|\\27\\23\\27|x\\0|~\\13\\11\\177\\177I\\0<~B\\302\"\n  \"\\302f$\\0||UWVTD\\0||VWUDD\\0|~UUUVD\\0}}TT\"\n  \"TUE\\0\\0\\0E\\177~D\\0\\0\\0\\0D~\\177E\\0\\0\\0\\2E}}E\\2\\0\\0\\1E|\"\n  \"|E\\1\\0I\\177\\177Ic>\\34\\0~\\177\\11\\23\\42\\177}\\0\\70|EGF|\\70\\0\\70|FG\"\n  \"E|\\70\\0\\70~EEE~\\70\\0:\\177EGF\\177\\71\\0=\\177BBB\\177=\\0\\42\\66\\34\\10\"\n  \"\\34\\66\\42\\0\\134>sIg>\\35\\0<}CB@|<\\0<|BCA|<\\0\\70zAA\"\n  \"Az\\70\\0=}@@@}=\\0\\0\\14\\134rs]\\14\\0A\\177\\177U\\24\\34\\10\\0~\\177\\1\\11\"\n  \"_v \\0 tUW>x@\\0 tVW=x@\\0 vUU>x@\\0\\42wUW\"\n  \">{A\\0!uTT<yA\\0 tWW<x@\\0 TT|TTX\\0\\70|D\\304\"\n  \"\\304l(\\0\\70|UWV\\134\\30\\0\\70|TVW]\\30\\0\\70~UUU^\\30\\0\\71}TT\"\n  \"T]\\31\\0\\0\\0D}\\177B\\0\\0\\0\\0F\\177}@\\0\\0\\0\\2E}}B\\0\\0\\0\\1E|\"\n  \"|A\\1\\0\\60zKK~>\\2\\0\\12{q\\13\\12{q\\0\\60xIKJx\\60\\0\\60xJK\"\n  \"Ix\\60\\0\\60zIIIz\\60\\0\\62{IKJ{\\61\\0\\61yHHHy\\61\\0\\0\\10\\10*\"\n  \"*\\10\\10\\0\\270|dTL|:\\0<}CB<|@\\0<|BC=|@\\0\\70zAA\"\n  \":x@\\0=}@@=}@\\0\\234\\274\\242\\243\\241\\374|\\0\\201\\377\\377\\244$<\\30\\0\\235\\275\\240\\240\"\n  \"\\240\\375}\";\n/*\n  Fontname: -FreeType-PxPlus TandyNew TV-Medium-R-Normal--8-80-72-72-P-70-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 96/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplustandynewtv_r[772] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_r\") = \n  \" \\177\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\3\\7\\0\\0\\7\\3\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0\\0$.kk:\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\4\\7\"\n  \"\\3\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0\\34>cIc>\\34\\0\\0@B\\177\\177@@\\0BcqYIof\\0\\42cII\"\n  \"I\\177\\66\\0\\30\\34\\26S\\177\\177P\\0/oIIIy\\61\\0<~KIIx\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66\\177III\\177\\66\\0\\6OIIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346\"\n  \"f\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\2\\3\\1Y\"\n  \"]\\7\\2\\0>\\177A]]\\37\\36\\0|~\\13\\11\\13~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Q\\63r\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0A\\177\\177I\\11\\17\\6\\0>\\177AA\\341\\377\\276\\0A\\177\\177\\11\\31wf\\0\\0\\42gM\"\n  \"Ys\\42\\0\\0\\3A\\177\\177A\\3\\0\\77\\177@@@\\177\\77\\0\\37\\77`@`\\77\\37\\0\\77\\177`\\70\"\n  \"`\\177\\77\\0cw\\34\\10\\34wc\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\\0\\0\\1\\3\\6\\4\\0\\0 tTT<x@\\0A\\177\\77DD|\\70\\0\\70|DD\"\n  \"Dl(\\0\\70|DE\\77\\177@\\0\\70|TTT\\134\\30\\0H~\\177I\\11\\3\\2\\0\\230\\274\\244\\244\"\n  \"\\370|\\4\\0A\\177\\177\\10\\4|x\\0\\0\\0D}}@\\0\\0\\0`\\340\\200\\200\\375}\\0A\\177\\177\\20\"\n  \"\\70lD\\0\\0\\0A\\177\\177@\\0\\0||\\14x\\14|x\\0\\4|x\\4\\4|x\\0\\70|DD\"\n  \"D|\\70\\0\\204\\374\\370\\244$<\\30\\0\\30<$\\244\\370\\374\\204\\0D|xL\\4\\14\\10\\0H\\134TT\"\n  \"Tt$\\0\\4\\4\\77\\177Dd \\0<|@@<|@\\0\\34<`@`<\\34\\0<|`\\70\"\n  \"`|<\\0Dl\\70\\20\\70lD\\0\\234\\274\\240\\240\\240\\374|\\0\\0Ldt\\134Ld\\0\\0\\10\\10>\"\n  \"wAA\\0\\0\\0\\0\\357\\357\\0\\0\\0\\0AAw>\\10\\10\\0\\2\\3\\1\\3\\2\\3\\1\\0pxLF\"\n  \"Lxp\";\n/*\n  Fontname: -FreeType-PxPlus TandyNew TV-Medium-R-Normal--8-80-72-72-P-70-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 18/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplustandynewtv_n[220] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_n\") = \n  \" :\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0\\34>cIc>\\34\\0\\0@B\\177\\177@@\\0BcqYIof\\0\\42cII\"\n  \"I\\177\\66\\0\\30\\34\\26S\\177\\177P\\0/oIIIy\\61\\0<~KIIx\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66\\177III\\177\\66\\0\\6OIIi\\77\\36\\0\\0\\0\\0ff\\0\\0\";\n/*\n  Fontname: -FreeType-PxPlus TandyNew TV-Medium-R-Normal--8-80-72-72-P-70-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 64/781\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_pxplustandynewtv_u[517] U8X8_FONT_SECTION(\"u8x8_font_pxplustandynewtv_u\") = \n  \" _\\1\\1\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\6__\\6\\0\\0\\0\\3\\7\\0\\0\\7\\3\\0\\24\\177\\177\\24\"\n  \"\\177\\177\\24\\0\\0$.kk:\\22\\0Ff\\60\\30\\14fb\\0\\60zO]\\67zH\\0\\0\\0\\4\\7\"\n  \"\\3\\0\\0\\0\\0\\0\\34>cA\\0\\0\\0\\0Ac>\\34\\0\\0\\10*>\\34\\34>*\\10\\0\\10\\10>\"\n  \">\\10\\10\\0\\0\\0\\200\\340`\\0\\0\\0\\0\\10\\10\\10\\10\\10\\10\\0\\0\\0\\0``\\0\\0\\0`\\60\\30\\14\"\n  \"\\6\\3\\1\\0\\34>cIc>\\34\\0\\0@B\\177\\177@@\\0BcqYIof\\0\\42cII\"\n  \"I\\177\\66\\0\\30\\34\\26S\\177\\177P\\0/oIIIy\\61\\0<~KIIx\\60\\0\\3\\3qy\"\n  \"\\15\\7\\3\\0\\66\\177III\\177\\66\\0\\6OIIi\\77\\36\\0\\0\\0\\0ff\\0\\0\\0\\0\\0\\200\\346\"\n  \"f\\0\\0\\0\\0\\0\\10\\34\\66cA\\0\\0$$$$$$\\0\\0\\0Ac\\66\\34\\10\\0\\2\\3\\1Y\"\n  \"]\\7\\2\\0>\\177A]]\\37\\36\\0|~\\13\\11\\13~|\\0A\\177\\177II\\177\\66\\0\\34>cA\"\n  \"Ac\\42\\0A\\177\\177Ac>\\34\\0A\\177\\177I]Ac\\0A\\177\\177I\\35\\1\\3\\0\\34>cA\"\n  \"Q\\63r\\0\\177\\177\\10\\10\\10\\177\\177\\0\\0\\0A\\177\\177A\\0\\0\\60p@A\\177\\77\\1\\0A\\177\\177\\10\"\n  \"\\34wc\\0A\\177\\177A@`p\\0\\177\\177\\16\\34\\16\\177\\177\\0\\177\\177\\6\\14\\30\\177\\177\\0>\\177AA\"\n  \"A\\177>\\0A\\177\\177I\\11\\17\\6\\0>\\177AA\\341\\377\\276\\0A\\177\\177\\11\\31wf\\0\\0\\42gM\"\n  \"Ys\\42\\0\\0\\3A\\177\\177A\\3\\0\\77\\177@@@\\177\\77\\0\\37\\77`@`\\77\\37\\0\\77\\177`\\70\"\n  \"`\\177\\77\\0cw\\34\\10\\34wc\\0\\0\\7OxxO\\7\\0GcqYMgs\\0\\0\\0\\177\\177\"\n  \"AA\\0\\0\\1\\3\\6\\14\\30\\60`\\0\\0\\0AA\\177\\177\\0\\0\\10\\14\\6\\3\\6\\14\\10\\0\\200\\200\\200\\200\"\n  \"\\200\\200\\200\\200\";\n/*\n  Fontname: -FreeType-Px437 Wyse700a-Medium-R-Normal--16-160-72-72-P-131-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 151/288\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_px437wyse700a_2x2_f[7172] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700a_2x2_f\") = \n  \" \\377\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0p\\370\\374\\374\\374\\374\\370p\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\33\\33\\33\\33\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\6\\16\\36\\36\\0\\0\\0\\0\\36\\36\\16\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0  \\370\\370\\370    \\370\\370\\370  \\0\\0\\4\\4\\37\\37\\37\\4\\4\\4\\4\\37\\37\"\n  \"\\37\\4\\4\\0\\0\\0\\60xx\\374\\317\\207\\207\\217\\234\\30\\30\\20\\0\\0\\0\\0\\4\\14\\14\\34xppy\\37\\17\"\n  \"\\17\\6\\0\\0\\0\\0\\60\\60\\60\\60\\0\\200\\300\\340\\360p\\60\\20\\0\\0\\0\\0\\20\\30\\34\\36\\17\\7\\3\\1\\30\\30\"\n  \"\\30\\30\\0\\0\\0\\0\\20\\70\\270\\374\\354\\304\\354|\\70\\270\\220\\200\\200\\0\\0\\6\\17\\17\\37\\31\\21\\21\\33\\17\\17\\37\"\n  \"\\37\\31\\20\\0\\0\\0\\0\\20\\36\\36\\36\\16\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\340\\360\\370\\374\\34\\14\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\3\\7\\17\\37\\34\\30\\20\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\4\\14\\34\\374\\370\\360\\340\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\30\\34\\37\\17\"\n  \"\\7\\3\\0\\0\\0\\200\\240\\240\\340\\340\\300\\300\\300\\300\\340\\340\\240\\240\\200\\0\\0\\0\\2\\2\\3\\3\\1\\1\\1\\1\\3\\3\"\n  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(vector) version (c) 2015 VileR\n  Glyphs: 96/288\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_px437wyse700a_2x2_r[3077] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700a_2x2_r\") = \n  \" \\177\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0p\\370\\374\\374\\374\\374\\370p\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\33\\33\\33\\33\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\6\\16\\36\\36\\0\\0\\0\\0\\36\\36\\16\\6\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0  \\370\\370\\370    \\370\\370\\370  \\0\\0\\4\\4\\37\\37\\37\\4\\4\\4\\4\\37\\37\"\n  \"\\37\\4\\4\\0\\0\\0\\60xx\\374\\317\\207\\207\\217\\234\\30\\30\\20\\0\\0\\0\\0\\4\\14\\14\\34xppy\\37\\17\"\n  \"\\17\\6\\0\\0\\0\\0\\60\\60\\60\\60\\0\\200\\300\\340\\360p\\60\\20\\0\\0\\0\\0\\20\\30\\34\\36\\17\\7\\3\\1\\30\\30\"\n  \"\\30\\30\\0\\0\\0\\0\\20\\70\\270\\374\\354\\304\\354|\\70\\270\\220\\200\\200\\0\\0\\6\\17\\17\\37\\31\\21\\21\\33\\17\\17\\37\"\n  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Glyphs: 151/288\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_px437wyse700b_2x2_f[7172] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700b_2x2_f\") = \n  \" \\377\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\33\\33\\33\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\36\\36\\36\\0\\0\\0\\0\\36\\36\\36\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0  \\370\\370\\370    \\370\\370\\370  \\0\\0\\4\\4\\37\\37\\37\\4\\4\\4\\4\\37\\37\"\n  \"\\37\\4\\4\\0\\0\\60xx\\314\\204\\204\\376\\376\\204\\204\\214\\30\\30\\20\\0\\0\\4\\14\\14\\30\\20\\20\\77\\77\\20\\20\\31\"\n  \"\\17\\17\\6\\0\\0\\0\\0\\60\\60\\60\\60\\0\\200\\300\\340p\\60\\20\\0\\0\\0\\0\\0\\20\\30\\34\\16\\7\\3\\1\\30\\30\"\n  \"\\30\\30\\0\\0\\0\\0\\20\\70\\270\\354\\304\\304\\304\\354\\70\\70\\220\\200\\200\\0\\0\\6\\17\\17\\31\\20\\20\\20\\31\\37\\17\\17\"\n  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\"\\77/\\7\\0\\0\\0\\374\\374\\374\\204\\204\\204\\204\\204\\204\\314xx\\60\\0\\0\\0\\37\\37\\37\\0\\0\\0\\1\\3\\7\\16\"\n  \"\\34\\30\\20\\0\\0\\60xx\\314\\204\\204\\204\\204\\204\\204\\214\\30\\30\\20\\0\\0\\4\\14\\14\\30\\20\\20\\20\\20\\20\\20\\31\"\n  \"\\17\\17\\6\\0\\0\\0\\4\\4\\4\\4\\4\\374\\374\\374\\4\\4\\4\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\0\\7\\17\\17\\30\\20\\20\\20\\20\\20\\30\"\n  \"\\17\\17\\7\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\1\\3\\7\\16\\34\\30\\30\\34\\16\\7\"\n  \"\\3\\1\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\7\\17\\37\\30\\34\\16\\7\\7\\16\\34\\30\"\n  \"\\37\\17\\7\\0\\0\\0\\14\\34<p\\340\\300\\300\\340p<\\34\\14\\0\\0\\0\\0\\30\\34\\36\\7\\3\\1\\1\\3\\7\\36\"\n  \"\\34\\30\\0\\0\\0\\0\\4\\14\\34\\70p\\340\\300\\340p\\70\\34\\14\\4\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\4\\4\\4\\4\\4\\204\\304\\344t<\\34\\14\\4\\0\\0\\0\\20\\30\\34\\36\\27\\23\\21\\20\\20\\20\"\n  \"\\20\\20\\20\\0\\0\\0\\0\\0\\0\\374\\374\\374\\4\\4\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\20\\20\\20\\20\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\10\\30\\70p\\340\\300\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\1\\3\\7\\16\"\n  \"\\14\\10\\0\\0\\0\\0\\0\\0\\0\\4\\4\\4\\4\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\0\\20\\20\\20\\20\\37\\37\\37\"\n  \"\\0\\0\\0\\0\\0\\0\\20\\30\\34\\16\\7\\3\\3\\7\\16\\34\\30\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@@@@@@@@@@@@\"\n  \"@@@@\\0\\0\\0\\0\\0\\2\\6\\16\\34\\30\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0@@@@@@@@\\300\\200\\200\\0\\0\\0\\16\\16\\37\\21\\21\\21\\21\\21\\21\\21\"\n  \"\\37\\37\\37\\0\\0\\0\\374\\374\\374@@@@@@\\300\\200\\200\\0\\0\\0\\0\\37\\37\\37\\20\\20\\20\\20\\20\\20\\20\"\n  \"\\37\\17\\17\\0\\0\\0\\200\\200\\300@@@@@@@\\300\\200\\200\\0\\0\\0\\17\\17\\37\\20\\20\\20\\20\\20\\20\\20\"\n  \"\\30\\10\\10\\0\\0\\0\\0\\200\\200\\300@@@@@@\\374\\374\\374\\0\\0\\0\\17\\17\\37\\20\\20\\20\\20\\20\\20\\20\"\n  \"\\37\\37\\37\\0\\0\\0\\200\\200\\300@@@@@@@\\300\\200\\200\\0\\0\\0\\17\\17\\37\\22\\22\\22\\22\\22\\22\\22\"\n  \"\\23\\23\\3\\0\\0\\0\\0\\0\\200\\200\\370\\370\\374\\204\\204\\204\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200\\300@@@@@@@\\300\\200\\200\\0\\0\\0\\7GOHHHHHHH\"\n  \"\\177\\77\\77\\0\\0\\0\\374\\374\\374\\200@@@@@@\\300\\200\\200\\0\\0\\0\\37\\37\\37\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\37\\37\\37\\0\\0\\0\\0\\0\\0\\0\\0\\330\\330\\330\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\330\\330\\330\\0\\0\\0\\0\\0\\0\\0\\0@@@@`\\77\\77\\37\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\200\\300\\300@\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\2\\7\\17\\35\\30\"\n  \"\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\300\\300@@\\200\\200\\300@@\\300\\200\\200\\0\\0\\0\\37\\37\\37\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\37\\37\\37\\0\\0\\0\\300\\300\\300@@@@@\\300\\200\\200\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\\0\\0\\0\\0\\37\"\n  \"\\37\\37\\0\\0\\0\\0\\0\\200\\200\\300@@@@@\\300\\200\\200\\0\\0\\0\\0\\7\\17\\17\\30\\20\\20\\20\\20\\20\\30\"\n  \"\\17\\17\\7\\0\\0\\0\\300\\300\\300@@@@@@\\300\\200\\200\\0\\0\\0\\0\\177\\177\\177\\10\\10\\10\\10\\10\\10\\14\"\n  \"\\7\\7\\3\\0\\0\\0\\0\\200\\200\\300@@@@@@\\300\\300\\300\\0\\0\\0\\3\\7\\7\\14\\10\\10\\10\\10\\10\\10\"\n  \"\\177\\177\\177\\0\\0\\0\\300\\300\\300@@@@@@\\300\\200\\200\\0\\0\\0\\0\\37\\37\\37\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200\\300@@@@@@@@@\\0\\0\\0\\0\\1\\21\\23\\22\\22\\22\\22\\22\\22\\22\"\n  \"\\36\\14\\14\\0\\0\\0\\0@@@@\\374\\374\\374@@@@\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\300\\300\\300\\0\\0\\0\\0\\0\\0\\300\\300\\300\\0\\0\\0\\0\\17\\17\\37\\20\\20\\20\\20\\20\\20\\37\"\n  \"\\37\\37\\0\\0\\0@\\300\\300\\200\\0\\0\\0\\0\\0\\0\\200\\300\\300@\\0\\0\\0\\0\\1\\3\\7\\16\\34\\34\\16\\7\\3\"\n  \"\\1\\0\\0\\0\\0\\0\\300\\300\\300\\0\\0\\0\\0\\0\\0\\0\\300\\300\\300\\0\\0\\0\\7\\17\\37\\30\\34\\16\\6\\16\\34\\30\"\n  \"\\37\\17\\7\\0\\0\\0\\0@\\300\\300\\200\\0\\0\\200\\300\\300@\\0\\0\\0\\0\\0\\0\\20\\30\\35\\17\\7\\7\\17\\35\\30\"\n  \"\\20\\0\\0\\0\\0\\0@\\300\\300\\200\\0\\0\\0\\0\\0\\200\\300\\300@\\0\\0\\0\\0\\0Acw>\\34\\16\\7\\3\"\n  \"\\1\\0\\0\\0\\0\\0@@@@@@@@@\\300\\300\\300@\\0\\0\\0\\20\\30\\30\\34\\24\\26\\22\\23\\21\\21\"\n  \"\\20\\20\\20\\0\\0\\0\\0\\200\\200\\200\\360x|\\14\\4\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\7\\17\\37\\30\\20\\20\"\n  \"\\20\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0|||\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\4\\4\\4\\14|x\\360\\200\\200\\200\\0\\0\\0\\0\\0\\0\\20\\20\\20\\30\\37\\17\\7\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\10\\10\\14\\4\\4\\14\\10\\10\\14\\4\\4\\4\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\200\\200\\300@` \\60\\20\\60 `@\\300\\200\\200\\0\\3\\3\\3\\2\\2\\2\\2\\2\\2\\2\\2\"\n  \"\\2\\3\\3\\3\";\n/*\n  Fontname: -FreeType-Px437 Wyse700b-Medium-R-Normal--16-160-72-72-P-124-ISO10646-1\n  Copyright: Outline (vector) version (c) 2015 VileR\n  Glyphs: 18/288\n  BBX Build Mode: 3\n*/\nconst uint8_t u8x8_font_px437wyse700b_2x2_n[868] U8X8_FONT_SECTION(\"u8x8_font_px437wyse700b_2x2_n\") = \n  \" :\\2\\2\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200\\240\\240\\340\\300\\300\\300\\340\\240\\240\\200\\200\\0\\0\\0\\0\\0\\2\\2\\3\\1\\1\\1\\3\\2\"\n  \"\\2\\0\\0\\0\\0\\0\\200\\200\\200\\200\\200\\360\\360\\360\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\\0\\0\\7\\7\\7\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0@xx\\70\\30\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\200\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\30\\30\\30\\30\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\200\\300\\340p\\70\\30\\10\\0\\0\\0\\0\\0\\10\\14\\16\\7\\3\\1\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\360\\370\\370\\14\\4\\204\\304d<\\370\\370\\360\\0\\0\\0\\0\\7\\17\\17\\36\\23\\21\\20\\20\\30\\17\"\n  \"\\17\\7\\0\\0\\0\\0\\0\\0\\20\\20\\30\\374\\374\\374\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\10\\10\\14\\4\\4\\4\\4\\204\\204\\314xx\\60\\0\\0\\0\\30\\34\\34\\26\\22\\23\\21\\21\\20\\20\"\n  \"\\20\\20\\20\\0\\0\\0\\10\\10\\14\\4\\4\\204\\204\\204\\204\\314xx\\60\\0\\0\\0\\10\\10\\30\\20\\20\\20\\20\\20\\20\\31\"\n  \"\\17\\17\\6\\0\\0\\0\\200\\300\\340p\\70\\34\\14\\374\\374\\374\\0\\0\\0\\0\\0\\0\\1\\1\\1\\1\\1\\1\\1\\37\\37\\37\"\n  \"\\1\\1\\0\\0\\0\\0|||DDDDDD\\304\\204\\204\\4\\0\\0\\0\\10\\10\\30\\20\\20\\20\\20\\20\\20\\30\"\n  \"\\17\\17\\7\\0\\0\\0\\360\\370\\370\\214\\204\\204\\204\\204\\204\\204\\0\\0\\0\\0\\0\\0\\7\\17\\17\\30\\20\\20\\20\\20\\20\\31\"\n  \"\\17\\17\\6\\0\\0\\0\\4\\4\\4\\4\\4\\204\\304\\344|<\\34\\0\\0\\0\\0\\0\\0\\0\\0\\0\\37\\37\\37\\0\\0\\0\"\n  \"\\0\\0\\0\\0\\0\\0\\60xx\\314\\204\\204\\204\\204\\204\\314xx\\60\\0\\0\\0\\6\\17\\17\\31\\20\\20\\20\\20\\20\\31\"\n  \"\\17\\17\\6\\0\\0\\0\\60xx\\314\\204\\204\\204\\204\\204\\214\\370\\370\\360\\0\\0\\0\\0\\0\\20\\20\\20\\20\\20\\20\\20\\30\"\n  \"\\17\\17\\7\\0\\0\\0\\0\\0\\0\\0\\60\\60\\60\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\0\\14\\14\\14\\0\\0\\0\"\n  \"\\0\\0\\0\";\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_gpio.c",
    "content": "/*\n\n  u8x8_gpio.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n\n#include \"u8x8.h\"\n\n\nvoid u8x8_gpio_call(u8x8_t *u8x8, uint8_t msg, uint8_t arg)\n{\n  u8x8->gpio_and_delay_cb(u8x8, msg, arg, NULL);\n}\n\n/*\nvoid u8x8_gpio_Delay(u8x8_t *u8x8, uint8_t msg, uint8_t dly)\n{\n  u8x8->gpio_and_delay_cb(u8x8, msg, dly, NULL);\n}\n*/"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_input_value.c",
    "content": "/*\n\n  u8x8_input_value.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8x8.h\"\n\n/*\n  return:\n    0: value is not changed (HOME/Break Button pressed)\n    1: value has been updated\n*/\n\nuint8_t u8x8_UserInterfaceInputValue(u8x8_t *u8x8, const char *title, const char *pre, uint8_t *value, uint8_t lo, uint8_t hi, uint8_t digits, const char *post)\n{\n  uint8_t height;\n  uint8_t y;\n  uint8_t width;\n  uint8_t x;\n  uint8_t local_value = *value;\n  uint8_t r;\n  uint8_t event;\n\n  /* calculate overall height of the input value box */\n  height = 1;\t/* button line */\n  height += u8x8_GetStringLineCnt(title);\n  \n  /* calculate offset from top */\n  y = 0;\n  if ( height < u8x8_GetRows(u8x8)  )\n  {\n    y = u8x8_GetRows(u8x8);\n    y -= height;\n    y /= 2;\n  }\n  \n  /* calculate offset from left for the label */\n  x = 0;\n  width = u8x8_GetUTF8Len(u8x8, pre);\n  width += digits;\n  width += u8x8_GetUTF8Len(u8x8, post);\n  if ( width < u8x8_GetCols(u8x8) )\n  {\n    x = u8x8_GetCols(u8x8);\n    x -= width;\n    x /= 2;\n  }\n  \n  /* render */\n  u8x8_ClearDisplay(u8x8);   /* required, because not everything is filled */\n  u8x8_SetInverseFont(u8x8, 0);  \n  y += u8x8_DrawUTF8Lines(u8x8, 0, y, u8x8_GetCols(u8x8), title);\n  x += u8x8_DrawUTF8(u8x8, x, y, pre);\n  u8x8_DrawUTF8(u8x8, x+digits, y, post);\n  u8x8_SetInverseFont(u8x8, 1);\n  \n  /* event loop */\n  u8x8_DrawUTF8(u8x8, x, y, u8x8_u8toa(local_value, digits));\n  for(;;)\n  {\n    event = u8x8_GetMenuEvent(u8x8);\n    if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n    {\n      *value = local_value;\n      r = 1;\n      break;\n    }\n    else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n    {\n      r = 0;\n      break;\n    }\n    else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_UP )\n    {\n      if ( local_value >= hi )\n\tlocal_value = lo;\n      else\n\tlocal_value++;\n      u8x8_DrawUTF8(u8x8, x, y, u8x8_u8toa(local_value, digits));\n    }\n    else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_DOWN )\n    {\n      if ( local_value <= lo )\n\tlocal_value = hi;\n      else\n\tlocal_value--;\n      u8x8_DrawUTF8(u8x8, x, y, u8x8_u8toa(local_value, digits));\n    }        \n  }\n  \n  u8x8_SetInverseFont(u8x8, 0);\n  return r;  \n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_message.c",
    "content": "/*\n\n  u8x8_message.c\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8x8.h\"\n\nuint8_t u8x8_draw_button_line(u8x8_t *u8x8, uint8_t y, uint8_t w, uint8_t cursor, const char *s)\n{\n  uint8_t i;\n  uint8_t cnt;\n  uint8_t total;\n  uint8_t d;\n  uint8_t x;\n  cnt = u8x8_GetStringLineCnt(s);\n  \n  /* calculate the width of the button */\n  total = 0;\n  for( i = 0; i < cnt; i++ )\n  {\n    total += u8x8_GetUTF8Len(u8x8, u8x8_GetStringLineStart(i, s));\n  }\n  total += (cnt-1);\t/* had one space between the buttons */\n  \n  /* calculate the left offset */\n  d = 0;\n  if ( total < w )\n  {\n    d = w;\n    d -= total;\n    d /= 2;\n  }\n  \n  /* draw the buttons */\n  x = d;\n  u8x8_SetInverseFont(u8x8, 0);\n  for( i = 0; i < cnt; i++ )\n  {\n    if ( i == cursor )\n      u8x8_SetInverseFont(u8x8, 1);\n      \n    x+=u8x8_DrawUTF8(u8x8, x, y, u8x8_GetStringLineStart(i, s));\n    u8x8_SetInverseFont(u8x8, 0);\n    x+=u8x8_DrawUTF8(u8x8, x, y, \" \");\n  }\n  \n  /* return the number of buttons */\n  return cnt;\n}\n\n/*\n  title1:\tMultiple lines,separated by '\\n'\n  title2:\tA single line/string which is terminated by '\\0' or '\\n' . \"title2\" accepts the return value from u8x8_GetStringLineStart()\n  title3:\tMultiple lines,separated by '\\n'\n  buttons:\tone more more buttons separated by '\\n' and terminated with '\\0'\n*/\n\nuint8_t u8x8_UserInterfaceMessage(u8x8_t *u8x8, const char *title1, const char *title2, const char *title3, const char *buttons)\n{\n  uint8_t height;\n  uint8_t y;\n  uint8_t cursor = 0;\n  uint8_t button_cnt;\n  uint8_t event;\n\n  u8x8_SetInverseFont(u8x8, 0);\n  \n  /* calculate overall height of the message box */\n  height = 1;\t/* button line */\n  height += u8x8_GetStringLineCnt(title1);\n  if ( title2 != NULL )\n    height ++;\n  height += u8x8_GetStringLineCnt(title3);\n  \n  /* calculate offset from top */\n  y = 0;\n  if ( height < u8x8_GetRows(u8x8)  )\n  {\n    y = u8x8_GetRows(u8x8);\n    y -= height;\n    y /= 2;\n  }\n\n  /* draw message box */\n  \n  u8x8_ClearDisplay(u8x8);   /* required, because not everything is filled */\n  \n  y += u8x8_DrawUTF8Lines(u8x8, 0, y, u8x8_GetCols(u8x8), title1);\n  if ( title2 != NULL )\n  {\n    u8x8_DrawUTF8Line(u8x8, 0, y, u8x8_GetCols(u8x8), title2);\n    y++;\n  }\n  y += u8x8_DrawUTF8Lines(u8x8, 0, y, u8x8_GetCols(u8x8), title3);\n\n  button_cnt = u8x8_draw_button_line(u8x8, y, u8x8_GetCols(u8x8), cursor, buttons);\n  \n  for(;;)\n  {\n    event = u8x8_GetMenuEvent(u8x8);\n    if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n      return cursor+1;\n    else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n      break;\n    else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_UP )\n    {\n      cursor++;\n      if ( cursor >= button_cnt )\n\tcursor = 0;\n      u8x8_draw_button_line(u8x8, y, u8x8_GetCols(u8x8), cursor, buttons);\n    }\n    else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_DOWN  )\n    {\n      if ( cursor == 0 )\n\tcursor = button_cnt;\n      cursor--;\n      u8x8_draw_button_line(u8x8, y, u8x8_GetCols(u8x8), cursor, buttons);\n    }    \n  }  \n  return 0;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_selection_list.c",
    "content": "/*\n\n  u8x8_selection_list.c\n  \n  selection list with scroll option\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n#include \"u8x8.h\"\n\n/*\n  increase the cursor position\n*/\nvoid u8sl_Next(u8sl_t *u8sl)\n{\n  u8sl->current_pos++;\n  if ( u8sl->current_pos >= u8sl->total )\n  {\n    u8sl->current_pos = 0;\n    u8sl->first_pos = 0;\n  }\n  else\n  {\n    if ( u8sl->first_pos + u8sl->visible <= u8sl->current_pos + 1 )\n    {\n      u8sl->first_pos = u8sl->current_pos - u8sl->visible + 1;\n    }\n  }\n}\n\nvoid u8sl_Prev(u8sl_t *u8sl)\n{\n  if ( u8sl->current_pos == 0 )\n  {\n    u8sl->current_pos = u8sl->total - 1;\n    u8sl->first_pos = 0;\n    if ( u8sl->total > u8sl->visible )\n      u8sl->first_pos = u8sl->total - u8sl->visible;\n  }\n  else\n  {\n    u8sl->current_pos--;\n    if ( u8sl->first_pos > u8sl->current_pos )\n      u8sl->first_pos = u8sl->current_pos;\n  }\n}\n\nvoid u8x8_DrawSelectionList(u8x8_t *u8x8, u8sl_t *u8sl, u8x8_sl_cb sl_cb, const void *aux)\n{\n  uint8_t i;\n  for( i = 0; i < u8sl->visible; i++ )\n  {\n    sl_cb(u8x8, u8sl, i+u8sl->first_pos, aux);\n  }\n}\n\n/* selection list with string line */\nvoid u8x8_sl_string_line_cb(u8x8_t *u8x8, u8sl_t *u8sl, uint8_t idx, const void *aux)\n{\n  const char *s;\n  uint8_t row;\n  /* calculate offset from display upper border */\n  row = u8sl->y;\n  \n  /* calculate target pos */\n  row += idx;\n  row -= u8sl->first_pos;\n  \n  /* check whether this is the current cursor line */\n  if ( idx == u8sl->current_pos )\n    u8x8_SetInverseFont(u8x8, 1);\n  else\n    u8x8_SetInverseFont(u8x8, 0);\n  \n  /* get the line from the array */\n  s = u8x8_GetStringLineStart(idx, (const char *)aux);\n  \n  /* draw the line */\n  if ( s == NULL )\n    s = \"\";\n  u8x8_DrawUTF8Line(u8x8, u8sl->x, row, u8x8_GetCols(u8x8), s);  \n  u8x8_SetInverseFont(u8x8, 0);\n}\n\n/*\n  title: \t\tNULL for no title, valid str for title line. Can contain mutliple lines, separated by '\\n'\n  start_pos: \tdefault position for the cursor (starts with 1)\n  sl:\t\t\tstring list (list of strings separated by \\n)\n  returns 0 if user has pressed the home key\n  returns the selected line+1 if user has pressed the select key (e.g. 1 for the first line)\n*/\nuint8_t u8x8_UserInterfaceSelectionList(u8x8_t *u8x8, const char *title, uint8_t start_pos, const char *sl)\n{\n  u8sl_t u8sl;\n  uint8_t event;\n  uint8_t title_lines;\n  \n  if ( start_pos > 0 )\n    start_pos--;\n  \n  u8sl.visible = u8x8_GetRows(u8x8);\n  u8sl.total = u8x8_GetStringLineCnt(sl);\n  u8sl.first_pos = 0;\n  u8sl.current_pos = start_pos;\n  u8sl.x = 0;\n  u8sl.y = 0;\n  \n\n  //u8x8_ClearDisplay(u8x8);   /* not required because all is 100% filled */\n  u8x8_SetInverseFont(u8x8, 0);\n  \n  if ( title != NULL )\n  {\n    title_lines = u8x8_DrawUTF8Lines(u8x8, u8sl.x, u8sl.y, u8x8_GetCols(u8x8), title);\n    u8sl.y+=title_lines;\n    u8sl.visible-=title_lines;\n  }\n  \n  if ( u8sl.current_pos >= u8sl.total )\n    u8sl.current_pos = u8sl.total-1;\n\n  \n  u8x8_DrawSelectionList(u8x8, &u8sl, u8x8_sl_string_line_cb, sl);\n\n  for(;;)\n  {\n    event = u8x8_GetMenuEvent(u8x8);\n    if ( event == U8X8_MSG_GPIO_MENU_SELECT )\n      return u8sl.current_pos+1;\n    else if ( event == U8X8_MSG_GPIO_MENU_HOME )\n      return 0;\n    else if ( event == U8X8_MSG_GPIO_MENU_NEXT || event == U8X8_MSG_GPIO_MENU_DOWN )\n    {\n      u8sl_Next(&u8sl);\n      u8x8_DrawSelectionList(u8x8, &u8sl, u8x8_sl_string_line_cb, sl);      \n    }\n    else if ( event == U8X8_MSG_GPIO_MENU_PREV || event == U8X8_MSG_GPIO_MENU_UP  )\n    {\n      u8sl_Prev(&u8sl);\n      u8x8_DrawSelectionList(u8x8, &u8sl, u8x8_sl_string_line_cb, sl);      \n    }\n  }\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_setup.c",
    "content": "/*\n\n  u8x8_setup.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n*/\n\n\n#include \"u8x8.h\"\n\n/* universal dummy callback, which will be default for all callbacks */\nuint8_t u8x8_dummy_cb(U8X8_UNUSED u8x8_t *u8x8, U8X8_UNUSED uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n  /* the dummy callback will not handle any message and will fail for all messages */\n  return 0;\n}\n\n\nstatic const u8x8_display_info_t u8x8_null_display_info =\n{\n  /* chip_enable_level = */ 0,\n  /* chip_disable_level = */ 1,\n  \n  /* post_chip_enable_wait_ns = */ 0,\n  /* pre_chip_disable_wait_ns = */ 0,\n  /* reset_pulse_width_ms = */ 0, \n  /* post_reset_wait_ms = */ 0, \n  /* sda_setup_time_ns = */ 0,\t\t\n  /* sck_pulse_width_ns = */ 0,\t/* half of cycle time (100ns according to datasheet), AVR: below 70: 8 MHz, >= 70 --> 4MHz clock */\n  /* sck_clock_hz = */ 4000000UL,\t/* since Arduino 1.6.0, the SPI bus speed in Hz. Should be  1000000000/sck_pulse_width_ns */\n  /* spi_mode = */ 0,\t\t/* active high, rising edge */\n  /* i2c_bus_clock_100kHz = */ 4,\n  /* data_setup_time_ns = */ 0,\n  /* write_pulse_width_ns = */ 0,\n  /* tile_width = */ 1,\t\t/* 8x8 */\n  /* tile_hight = */ 1,\n  /* default_x_offset = */ 0,\n  /* flipmode_x_offset = */ 0,\n  /* pixel_width = */ 8,\n  /* pixel_height = */ 8\n};\n\n\n/* a special null device */\nuint8_t u8x8_d_null_cb(u8x8_t *u8x8, uint8_t msg, U8X8_UNUSED uint8_t arg_int, U8X8_UNUSED void *arg_ptr)\n{\n  switch(msg)\n  {\n    case U8X8_MSG_DISPLAY_SETUP_MEMORY:\n      u8x8_d_helper_display_setup_memory(u8x8, &u8x8_null_display_info);\n      break;\n    case U8X8_MSG_DISPLAY_INIT:\n      u8x8_d_helper_display_init(u8x8);\n      break;\n  }\n  /* the null device callback will succeed for all messages */\n  return 1;\n}\n\n\n/*\n  Description:\n    Setup u8x8\n  Args:\n    u8x8\tAn empty u8x8 structure\n*/\nvoid u8x8_SetupDefaults(u8x8_t *u8x8)\n{\n    u8x8->display_info = NULL;\n    u8x8->display_cb = u8x8_dummy_cb;\n    u8x8->cad_cb = u8x8_dummy_cb;\n    u8x8->byte_cb = u8x8_dummy_cb;\n    u8x8->gpio_and_delay_cb = u8x8_dummy_cb;\n    u8x8->is_font_inverse_mode = 0;\n    //u8x8->device_address = 0;\n    u8x8->utf8_state = 0;\t\t/* also reset by u8x8_utf8_init */\n    u8x8->bus_clock = 0;\t\t/* issue 769 */\n    u8x8->i2c_address = 255;\n    u8x8->debounce_default_pin_state = 255;\t/* assume all low active buttons */\n  \n#ifdef U8X8_USE_PINS \n  {\n    uint8_t i;\n    for( i = 0; i < U8X8_PIN_CNT; i++ )\n      u8x8->pins[i] = U8X8_PIN_NONE;\n  }\n#endif\n}\n\n\n/*\n  Description:\n    Setup u8x8 and assign the callback function. The dummy \n    callback \"u8x8_dummy_cb\" can be used, if no callback is required.\n    This setup will not communicate with the display itself.\n    Use u8x8_InitDisplay() to send the startup code to the Display.\n  Args:\n    u8x8\t\t\t\tAn empty u8x8 structure\n    display_cb\t\t\tDisplay/controller specific callback function\n    cad_cb\t\t\t\tDisplay controller specific communication callback function\n    byte_cb\t\t\tDisplay controller/communication specific callback funtion\n    gpio_and_delay_cb\tEnvironment specific callback function\n\n*/\nvoid u8x8_Setup(u8x8_t *u8x8, u8x8_msg_cb display_cb, u8x8_msg_cb cad_cb, u8x8_msg_cb byte_cb, u8x8_msg_cb gpio_and_delay_cb)\n{\n  /* setup defaults and reset pins to U8X8_PIN_NONE */\n  u8x8_SetupDefaults(u8x8);\n\n  /* setup specific callbacks */\n  u8x8->display_cb = display_cb;\n  u8x8->cad_cb = cad_cb;\n  u8x8->byte_cb = byte_cb;\n  u8x8->gpio_and_delay_cb = gpio_and_delay_cb;\n\n  /* setup display info */\n  u8x8_SetupMemory(u8x8);\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_string.c",
    "content": "/*\n\n  u8x8_string.c\n  \n  string line procedures\n  \n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.    \n\n*/\n\n#include \"u8x8.h\"\n\nuint8_t u8x8_GetStringLineCnt(const char *str)\n{\n  char e;\n  uint8_t line_cnt = 1;\n  if ( str == NULL )\n    return 0;\n  for(;;)\n  {\n    e = *str;\n    if ( e == '\\0' )\n      break;\n    str++;\n    if ( e == '\\n' )\n      line_cnt++;\n  }\n  return line_cnt;\n}\n\n\n/*\n    Assumes strings, separated by '\\n' in \"str\".\n    Returns the string at index \"line_idx\". First strng has line_idx = 0\n    Example:\n      Returns \"xyz\" for line_idx = 1 with str = \"abc\\nxyz\"\n    Support both UTF8 and normal strings.\n*/\nconst char *u8x8_GetStringLineStart(uint8_t line_idx, const char *str )\n{\n  char e;\n  uint8_t line_cnt = 1;\n  \n  if ( line_idx == 0 )\n    return str;\n\n  for(;;)\n  {\n    e = *str;\n    if ( e == '\\0' )\n      break;\n    str++;\n    if ( e == '\\n' )\n    {\n      if ( line_cnt == line_idx )\n\treturn str;\n      line_cnt++;\n    }\n  }\n  return NULL;\t/* line not found */\n}\n\n/* copy until first '\\n' or '\\0' in str */\n/* Important: There is no string overflow check, ensure */\n/* that the destination buffer is large enough */\nvoid u8x8_CopyStringLine(char *dest, uint8_t line_idx, const char *str)\n{\n  if ( dest == NULL )\n    return;\n  str = u8x8_GetStringLineStart( line_idx, str );\n  if ( str != NULL )\n  {\n    for(;;)\n    {\n      if ( *str == '\\n' || *str == '\\0' )\n\tbreak;\n      *dest = *str;\n      dest++;\n      str++;\n    }\n  }\n  *dest = '\\0';\n}\n\n/*\n  Draw a string\n  Extend the string to size \"w\"\n  Center the string within \"w\"\n  return the size of the string\n\n*/\nuint8_t u8x8_DrawUTF8Line(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t w, const char *s)\n{\n  uint8_t d, lw;\n  uint8_t cx, dx;\n    \n  d = 0;\n  \n  lw = u8x8_GetUTF8Len(u8x8, s);\n  if ( lw < w )\n  {\n    d = w;\n    d -=lw;\n    d /= 2;\n  }\n    \n  cx = x;\n  dx = cx + d;\n  while( cx < dx )\n  {\n    u8x8_DrawUTF8(u8x8, cx, y, \" \");\n    cx++;\n  }\n  cx += u8x8_DrawUTF8(u8x8, cx, y, s);\n  dx = x + w;\n  while( cx < dx )\n  {\n    u8x8_DrawUTF8(u8x8, cx, y, \" \");\n    cx++;\n  }\n  cx -= x;\n  return cx;\n}\n\n/*\n  draw several lines at position x,y.\n  lines are stored in s and must be separated with '\\n'.\n  lines can be centered with respect to \"w\" \n  if s == NULL nothing is drawn and 0 is returned\n  returns the number of lines in s\n*/\nuint8_t u8x8_DrawUTF8Lines(u8x8_t *u8x8, uint8_t x, uint8_t y, uint8_t w, const char *s)\n{\n  uint8_t i;\n  uint8_t cnt;\n  cnt = u8x8_GetStringLineCnt(s);\n  for( i = 0; i < cnt; i++ )\n  {\n    u8x8_DrawUTF8Line(u8x8, x, y, w, u8x8_GetStringLineStart(i, s));\n    y++;\n  }\n  return cnt;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_u16toa.c",
    "content": "/*\n\n  u8x8_u16toa.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n\n  \n*/\n\n\n#include \"u8x8.h\"\n\nconst char *u8x8_u16toap(char * dest, uint16_t v)\n{\n  uint8_t pos;\n  uint8_t d;\n  uint16_t c;\n  c = 10000;\n  for( pos = 0; pos < 5; pos++ )\n  {\n      d = '0';\n      while( v >= c )\n      {\n\tv -= c;\n\td++;\n      }\n      dest[pos] = d;\n      c /= 10;\n  }  \n  dest[5] = '\\0';\n  return dest;\n}\n\n/* v = value, d = number of digits */\nconst char *u8x8_u16toa(uint16_t v, uint8_t d)\n{\n  static char buf[6];\n  d = 5-d;\n  return u8x8_u16toap(buf, v) + d;\n}\n\nconst char *u8x8_utoa(uint16_t v)\n{\n  const char *s = u8x8_u16toa(v, 5);\n  while( *s == '0' )\n    s++;\n  if ( *s == '\\0' )\n    s--;\n  return s;\n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/3rdParty/u8g2/u8x8_u8toa.c",
    "content": "/*\n\n  u8x8_u8toa.c\n\n  Universal 8bit Graphics Library (https://github.com/olikraus/u8g2/)\n\n  Copyright (c) 2016, olikraus@gmail.com\n  All rights reserved.\n\n  Redistribution and use in source and binary forms, with or without modification, \n  are permitted provided that the following conditions are met:\n\n  * Redistributions of source code must retain the above copyright notice, this list \n    of conditions and the following disclaimer.\n    \n  * Redistributions in binary form must reproduce the above copyright notice, this \n    list of conditions and the following disclaimer in the documentation and/or other \n    materials provided with the distribution.\n\n  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND \n  CONTRIBUTORS \"AS IS\" AND ANY EXPRESS OR IMPLIED WARRANTIES, \n  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF \n  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \n  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR \n  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \n  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT \n  NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \n  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER \n  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, \n  STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) \n  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF \n  ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.  \n  \n*/\n\n\n#include \"u8x8.h\"\n\nstatic const unsigned char u8x8_u8toa_tab[3]  = { 100, 10, 1 } ;\nconst char *u8x8_u8toap(char * dest, uint8_t v)\n{\n  uint8_t pos;\n  uint8_t d;\n  uint8_t c;\n  for( pos = 0; pos < 3; pos++ )\n  {\n      d = '0';\n      c = *(u8x8_u8toa_tab+pos);\n      while( v >= c )\n      {\n\tv -= c;\n\td++;\n      }\n      dest[pos] = d;\n  }  \n  dest[3] = '\\0';\n  return dest;\n}\n\n/* v = value, d = number of digits */\nconst char *u8x8_u8toa(uint8_t v, uint8_t d)\n{\n  static char buf[4];\n  d = 3-d;\n  return u8x8_u8toap(buf, v) + d;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/ascii_processor.cpp",
    "content": "/*\n* The ASCII protocol is a simpler, human readable alternative to the main native\n* protocol.\n* In the future this protocol might be extended to support selected GCode commands.\n* For a list of supported commands see doc/ascii-protocol.md\n*/\n\n/* Includes ------------------------------------------------------------------*/\n\n#include \"common_inc.h\"\n#include \"ascii_processor.hpp\"\n\n/* Private macros ------------------------------------------------------------*/\n/* Private typedef -----------------------------------------------------------*/\n/* Global constant data ------------------------------------------------------*/\n/* Global variables ----------------------------------------------------------*/\n/* Private constant data -----------------------------------------------------*/\n#define MAX_LINE_LENGTH 256\n#define TO_STR_INNER(s) #s\n#define TO_STR(s) TO_STR_INNER(s)\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Function implementations --------------------------------------------------*/\n\n\n// @brief Executes an ASCII protocol command\n// @param buffer buffer of ASCII encoded characters\n// @param len size of the buffer\nvoid ASCII_protocol_process_line(const uint8_t* buffer, size_t len, StreamSink &response_channel)\n{\n    static_assert(sizeof(char) == sizeof(uint8_t));\n\n    // copy everything into a local buffer so we can insert null-termination\n    char cmd[MAX_LINE_LENGTH + 1];\n    if (len > MAX_LINE_LENGTH) len = MAX_LINE_LENGTH;\n    memcpy(cmd, buffer, len);\n\n    cmd[len] = 0; // null-terminate\n\n    if (response_channel.channelType == StreamSink::CHANNEL_TYPE_USB)\n        OnUsbAsciiCmd(cmd, len, response_channel);\n    else if (response_channel.channelType == StreamSink::CHANNEL_TYPE_UART4)\n        OnUart4AsciiCmd(cmd, len, response_channel);\n    else if (response_channel.channelType == StreamSink::CHANNEL_TYPE_UART5)\n        OnUart5AsciiCmd(cmd, len, response_channel);\n}\n\nvoid ASCII_protocol_parse_stream(const uint8_t* buffer, size_t len, StreamSink &response_channel)\n{\n    static uint8_t parse_buffer[MAX_LINE_LENGTH];\n    static bool read_active = true;\n    static uint32_t parse_buffer_idx = 0;\n\n    while (len--)\n    {\n        // if the line becomes too long, reset buffer and wait for the next line\n        if (parse_buffer_idx >= MAX_LINE_LENGTH)\n        {\n            read_active = false;\n            parse_buffer_idx = 0;\n        }\n\n        // Fetch the next char\n        uint8_t c = *(buffer++);\n        bool is_end_of_line = (c == '\\r' || c == '\\n');\n        if (is_end_of_line)\n        {\n            if (read_active)\n                ASCII_protocol_process_line(parse_buffer, parse_buffer_idx, response_channel);\n            parse_buffer_idx = 0;\n            read_active = true;\n        } else\n        {\n            if (read_active)\n            {\n                parse_buffer[parse_buffer_idx++] = c;\n            }\n        }\n    }\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/ascii_processor.hpp",
    "content": "#ifndef __ASCII_PROTOCOL_H\n#define __ASCII_PROTOCOL_H\n\n\n/* Includes ------------------------------------------------------------------*/\n#include <fibre/protocol.hpp>\n\n#include <stdlib.h>\n#include <stdint.h>\n#include <stdbool.h>\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported variables --------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\nvoid ASCII_protocol_parse_stream(const uint8_t* buffer, size_t len, StreamSink& response_channel);\nvoid OnUsbAsciiCmd(const char* _cmd, size_t _len, StreamSink& _responseChannel);\nvoid OnUart4AsciiCmd(const char* _cmd, size_t _len, StreamSink& _responseChannel);\nvoid OnUart5AsciiCmd(const char* _cmd, size_t _len, StreamSink& _responseChannel);\n\n// Function to send messages back through specific channel (UART or USB-VCP).\n// Use this function instead of printf because printf will send messages over ALL CHANNEL.\ntemplate<typename ... TArgs>\nvoid Respond(StreamSink &output , const char *fmt, TArgs &&... args)\n{\n    char response[64];\n    size_t len = snprintf(response, sizeof(response), fmt, std::forward<TArgs>(args)...);\n    output.process_bytes((uint8_t *) response, len, nullptr);\n    output.process_bytes((const uint8_t *) \"\\r\\n\", 2, nullptr);\n}\n\n\n#endif /* __ASCII_PROTOCOL_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/communication.cpp",
    "content": "\r\n/* Includes ------------------------------------------------------------------*/\r\n\r\n#include \"communication.hpp\"\r\n#include \"common_inc.h\"\r\n\r\n/* Private defines -----------------------------------------------------------*/\r\n/* Private macros ------------------------------------------------------------*/\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* Global constant data ------------------------------------------------------*/\r\n/* Global variables ----------------------------------------------------------*/\r\n/* Private constant data -----------------------------------------------------*/\r\n/* Private variables ---------------------------------------------------------*/\r\nvolatile bool endpointListValid = false;\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* Function implementations --------------------------------------------------*/\r\n// @brief Sends a line on the specified output.\r\n\r\nosThreadId_t commTaskHandle;\r\nconst osThreadAttr_t commTask_attributes = {\r\n    .name = \"commTask\",\r\n    .stack_size = 45000,\r\n    .priority = (osPriority_t) osPriorityNormal,\r\n};\r\n\r\nvoid InitCommunication(void)\r\n{\r\n    // Start command handling thread\r\n    commTaskHandle = osThreadNew(CommunicationTask, nullptr, &commTask_attributes);\r\n\r\n    while (!endpointListValid)\r\n        osDelay(1);\r\n}\r\n\r\nextern PCD_HandleTypeDef hpcd_USB_OTG_FS;\r\nosThreadId_t usbIrqTaskHandle;\r\n\r\nvoid UsbDeferredInterruptTask(void* ctx)\r\n{\r\n    (void) ctx; // unused parameter\r\n\r\n    for (;;)\r\n    {\r\n        // Wait for signalling from USB interrupt (OTG_FS_IRQHandler)\r\n        osStatus semaphore_status = osSemaphoreAcquire(sem_usb_irq, osWaitForever);\r\n        if (semaphore_status == osOK)\r\n        {\r\n            // We have a new incoming USB transmission: handle it\r\n            HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);\r\n            // Let the irq (OTG_FS_IRQHandler) fire again.\r\n            HAL_NVIC_EnableIRQ(OTG_FS_IRQn);\r\n        }\r\n    }\r\n}\r\n\r\n// Thread to handle deffered processing of USB interrupt, and\r\n// read commands out of the UART DMA circular buffer\r\nvoid CommunicationTask(void* ctx)\r\n{\r\n    (void) ctx; // unused parameter\r\n\r\n    CommitProtocol();\r\n\r\n    // Allow main init to continue\r\n    endpointListValid = true;\r\n\r\n    StartUartServer();\r\n    StartUsbServer();\r\n    StartCanServer(CAN1);\r\n    StartCanServer(CAN2);\r\n\r\n    for (;;)\r\n    {\r\n        osDelay(1000); // nothing to do\r\n    }\r\n}\r\n\r\nextern \"C\" {\r\nint _write(int file, const char* data, int len);\r\n}\r\n\r\n// @brief This is what printf calls internally\r\nint _write(int file, const char* data, int len)\r\n{\r\n    usbStreamOutputPtr->process_bytes((const uint8_t*) data, len, nullptr);\r\n    uart4StreamOutputPtr->process_bytes((const uint8_t*) data, len, nullptr);\r\n\r\n    return len;\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/communication.hpp",
    "content": "#ifndef COMMANDS_H\n#define COMMANDS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <cmsis_os.h>\n\nvoid InitCommunication(void);\nvoid CommitProtocol();\nvoid CommunicationTask(void *ctx);\nvoid UsbDeferredInterruptTask(void *ctx);\n\n#ifdef __cplusplus\n}\n\n#include <functional>\n#include <limits>\n#include \"ascii_processor.hpp\"\n#include \"interface_usb.hpp\"\n#include \"interface_uart.hpp\"\n#include \"interface_can.hpp\"\n\n#define COMMIT_PROTOCOL \\\nusing treeType = decltype(MakeObjTree());\\\nuint8_t treeBuffer[sizeof(treeType)];\\\nvoid CommitProtocol()\\\n{\\\n    auto treePtr = new(treeBuffer) treeType(MakeObjTree());\\\n    fibre_publish(*treePtr);\\\n}\\\n\n\n#endif\n#endif /* COMMANDS_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_can.cpp",
    "content": "/*\r\n*\r\n* Zero-config node ID negotiation\r\n* -------------------------------\r\n*\r\n* A heartbeat message is a message with a 8 byte unique serial number as payload.\r\n* A regular message is any message that is not a heartbeat message.\r\n*\r\n* All nodes MUST obey these four rules:\r\n*\r\n* a) At a given point in time, a node MUST consider a node ID taken (by others)\r\n*   if any of the following is true:\r\n*     - the node received a (not self-emitted) heartbeat message with that node ID\r\n*       within the last second\r\n*     - the node attempted and failed at sending a heartbeat message with that\r\n*       node ID within the last second (failed in the sense of not ACK'd)\r\n*\r\n* b) At a given point in time, a node MUST NOT consider a node ID self-assigned\r\n*   if, within the last second, it did not succeed in sending a heartbeat\r\n*   message with that node ID.\r\n*\r\n* c) At a given point in time, a node MUST NOT send any heartbeat message with\r\n*   a node ID that is taken.\r\n*\r\n* d) At a given point in time, a node MUST NOT send any regular message with\r\n*   a node ID that is not self-assigned.\r\n*\r\n* Hardware allocation\r\n* -------------------\r\n*   RX FIFO0:\r\n*       - filter bank 0: heartbeat messages\r\n*/\r\n\r\n#include \"common_inc.h\"\r\n#include <stm32f4xx_hal.h>\r\n#include <cmsis_os.h>\r\n\r\n// defined in can.c\r\nextern CAN_HandleTypeDef hcan1;\r\nextern CAN_HandleTypeDef hcan2;\r\n\r\nCAN_context can1Ctx;\r\nCAN_context can2Ctx;\r\nstatic CAN_context* ctxs = nullptr;\r\nstatic CAN_RxHeaderTypeDef headerRx;\r\nstatic uint8_t data[8];\r\n\r\n\r\nstruct CAN_context* get_can_ctx(CAN_HandleTypeDef* hcan)\r\n{\r\n    if (hcan->Instance == CAN1)\r\n        return &can1Ctx;\r\n    else if (hcan->Instance == CAN2)\r\n        return &can2Ctx;\r\n    else\r\n        return nullptr;\r\n}\r\n\r\nbool StartCanServer(CAN_TypeDef* hcan)\r\n{\r\n    if (hcan == CAN1)\r\n    {\r\n        ctxs = &can1Ctx;\r\n        ctxs->handle = &hcan1;\r\n    } else if (hcan == CAN2)\r\n    {\r\n        ctxs = &can2Ctx;\r\n        ctxs->handle = &hcan2;\r\n    } else\r\n        return false; // fail if none of the above checks matched\r\n\r\n    HAL_StatusTypeDef status;\r\n\r\n    ctxs->node_id = 0;\r\n    ctxs->serial_number = serialNumber;\r\n    osSemaphoreDef(sem_send_heartbeat);\r\n    ctxs->sem_send_heartbeat = osSemaphoreNew(1, 0, osSemaphore(sem_send_heartbeat));\r\n\r\n    //// Set up filter\r\n    CAN_FilterTypeDef sFilterConfig = {\r\n        .FilterIdHigh = 0x0000,\r\n        .FilterIdLow = 0x0000,\r\n        .FilterMaskIdHigh = 0x0000,\r\n        .FilterMaskIdLow = 0x0000,\r\n        .FilterFIFOAssignment = CAN_RX_FIFO0,\r\n        .FilterBank = 0,\r\n        .FilterMode = CAN_FILTERMODE_IDMASK,\r\n        .FilterScale = CAN_FILTERSCALE_16BIT, // two 16-bit filters\r\n        .FilterActivation = ENABLE,\r\n        .SlaveStartFilterBank = 0\r\n    };\r\n    status = HAL_CAN_ConfigFilter(ctxs->handle, &sFilterConfig);\r\n    if (status != HAL_OK)\r\n        return false;\r\n\r\n    status = HAL_CAN_Start(ctxs->handle);\r\n    if (status != HAL_OK)\r\n        return false;\r\n\r\n    status = HAL_CAN_ActivateNotification(ctxs->handle,\r\n                                          CAN_IT_TX_MAILBOX_EMPTY |\r\n                                          CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING |\r\n                                          /* we probably only want this */\r\n                                          CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL |\r\n                                          CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN |\r\n                                          CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK |\r\n                                          CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE |\r\n                                          CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |\r\n                                          CAN_IT_ERROR);\r\n    if (status != HAL_OK)\r\n        return false;\r\n\r\n    return true;\r\n}\r\n\r\nvoid tx_complete_callback(CAN_HandleTypeDef* hcan, uint8_t mailbox_idx)\r\n{\r\n//    CAN_context* ctx = get_can_ctx(hcan);\r\n//    if (!ctx) return;\r\n//    ctx->tx_msg_cnt++;\r\n\r\n    if (hcan->Instance == CAN1)\r\n        osSemaphoreRelease(sem_can1_tx);\r\n    else if (hcan->Instance == CAN2)\r\n        osSemaphoreRelease(sem_can2_tx);\r\n}\r\n\r\nvoid tx_aborted_callback(CAN_HandleTypeDef* hcan, uint8_t mailbox_idx)\r\n{\r\n    if (!get_can_ctx(hcan))\r\n        return;\r\n    get_can_ctx(hcan)->TxMailboxAbortCallbackCnt++;\r\n}\r\n\r\nvoid tx_error(CAN_context* ctx, uint8_t mailbox_idx)\r\n{\r\n}\r\n\r\nvoid HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_complete_callback(hcan, 0); }\r\n\r\nvoid HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_complete_callback(hcan, 1); }\r\n\r\nvoid HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_complete_callback(hcan, 2); }\r\n\r\nvoid HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_aborted_callback(hcan, 0); }\r\n\r\nvoid HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_aborted_callback(hcan, 1); }\r\n\r\nvoid HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef* hcan)\r\n{ tx_aborted_callback(hcan, 2); }\r\n\r\nvoid HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* hcan)\r\n{\r\n    CAN_context* ctx = get_can_ctx(hcan);\r\n    if (!ctx) return;\r\n    ctx->received_msg_cnt++;\r\n\r\n    HAL_StatusTypeDef status = HAL_CAN_GetRxMessage(hcan, CAN_RX_FIFO0, &headerRx, data);\r\n    if (status != HAL_OK)\r\n    {\r\n        ctx->unexpected_errors++;\r\n        return;\r\n    }\r\n\r\n    OnCanMessage(ctx, &headerRx, data);\r\n}\r\n\r\nvoid HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef* hcan)\r\n{ if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo0FullCallbackCnt++; }\r\n\r\nvoid HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef* hcan)\r\n{ if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo1MsgPendingCallbackCnt++; }\r\n\r\nvoid HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef* hcan)\r\n{ if (get_can_ctx(hcan)) get_can_ctx(hcan)->RxFifo1FullCallbackCnt++; }\r\n\r\nvoid HAL_CAN_SleepCallback(CAN_HandleTypeDef* hcan)\r\n{ if (get_can_ctx(hcan)) get_can_ctx(hcan)->SleepCallbackCnt++; }\r\n\r\nvoid HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef* hcan)\r\n{ if (get_can_ctx(hcan)) get_can_ctx(hcan)->WakeUpFromRxMsgCallbackCnt++; }\r\n\r\nvoid HAL_CAN_ErrorCallback(CAN_HandleTypeDef* hcan)\r\n{\r\n    //__asm volatile (\"bkpt\");\r\n    CAN_context* ctx = get_can_ctx(hcan);\r\n    if (!ctx) return;\r\n    volatile uint32_t original_error = hcan->ErrorCode;\r\n    (void) original_error;\r\n\r\n    // handle transmit errors in all three mailboxes\r\n    if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST0)\r\n    {\r\n        SET_BIT(hcan->Instance->sTxMailBox[0].TIR, CAN_TI0R_TXRQ);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST0;\r\n    } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR0)\r\n    {\r\n        tx_error(ctx, 0);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR0;\r\n    }\r\n\r\n    if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST1)\r\n    {\r\n        SET_BIT(hcan->Instance->sTxMailBox[1].TIR, CAN_TI1R_TXRQ);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST1;\r\n    } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR1)\r\n    {\r\n        tx_error(ctx, 1);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR1;\r\n    }\r\n\r\n    if (hcan->ErrorCode & HAL_CAN_ERROR_TX_ALST2)\r\n    {\r\n        SET_BIT(hcan->Instance->sTxMailBox[2].TIR, CAN_TI2R_TXRQ);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_ALST2;\r\n    } else if (hcan->ErrorCode & HAL_CAN_ERROR_TX_TERR2)\r\n    {\r\n        tx_error(ctx, 2);\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_EWG;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_ACK;\r\n        hcan->ErrorCode &= ~HAL_CAN_ERROR_TX_TERR2;\r\n    }\r\n\r\n    if (hcan->ErrorCode)\r\n        ctx->unexpected_errors++;\r\n}\r\n\r\nvoid CanSendMessage(CAN_context* canCtx, uint8_t* txData, CAN_TxHeaderTypeDef* txHeader)\r\n{\r\n    osStatus semaphore_status;\r\n    if (canCtx->handle->Instance == CAN1)\r\n        semaphore_status = osSemaphoreAcquire(sem_can1_tx, osWaitForever);\r\n    else if (canCtx->handle->Instance == CAN2)\r\n        semaphore_status = osSemaphoreAcquire(sem_can2_tx, osWaitForever);\r\n    else\r\n        return;\r\n\r\n    if (semaphore_status == osOK)\r\n        HAL_CAN_AddTxMessage(canCtx->handle, txHeader, txData, &canCtx->last_heartbeat_mailbox);\r\n}\r\n\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_can.hpp",
    "content": "#ifndef __INTERFACE_CAN_HPP\n#define __INTERFACE_CAN_HPP\n\n#include \"fibre/protocol.hpp\"\n#include <stm32f4xx_hal.h>\n#include <cmsis_os.h>\n\nstruct CAN_context\n{\n    CAN_HandleTypeDef* handle = nullptr;\n    uint8_t node_id = 0;\n    uint64_t serial_number = 0;\n\n    uint32_t node_ids_in_use_0[4]; // 128 bits (indicate if a node ID was in use up to 1 second ago)\n    uint32_t node_ids_in_use_1[4]; // 128 bits (indicats if a node ID was in use 1-2 seconds ago)\n\n    uint32_t last_heartbeat_mailbox = 0;\n    uint32_t tx_msg_cnt = 0;\n\n    uint8_t node_id_rng_state = 0;\n\n    osSemaphoreId_t sem_send_heartbeat;\n\n    // count occurrence various callbacks\n    uint32_t TxMailboxCompleteCallbackCnt = 0;\n    uint32_t TxMailboxAbortCallbackCnt = 0;\n    int RxFifo0MsgPendingCallbackCnt = 0;\n    int RxFifo0FullCallbackCnt = 0;\n    int RxFifo1MsgPendingCallbackCnt = 0;\n    int RxFifo1FullCallbackCnt = 0;\n    int SleepCallbackCnt = 0;\n    int WakeUpFromRxMsgCallbackCnt = 0;\n    int ErrorCallbackCnt = 0;\n\n    uint32_t received_msg_cnt = 0;\n    uint32_t received_ack = 0;\n    uint32_t unexpected_errors = 0;\n    uint32_t unhandled_messages = 0;\n};\n\nstruct CAN_context* get_can_ctx(CAN_HandleTypeDef* hcan);\nbool StartCanServer(CAN_TypeDef* hcan);\nvoid CanSendMessage(CAN_context* canCtx, uint8_t* txData, CAN_TxHeaderTypeDef* txHeader);\nvoid OnCanMessage(CAN_context* canCtx, CAN_RxHeaderTypeDef* rxHeader, uint8_t* data);\n\n#endif // __INTERFACE_CAN_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_uart.cpp",
    "content": "#include \"common_inc.h\"\r\n#include \"interface_uart.hpp\"\r\n#include \"ascii_processor.hpp\"\r\n#include \"fibre/protocol.hpp\"\r\n#include \"usart.h\"\r\n\r\n#define UART_TX_BUFFER_SIZE 64\r\n#define UART_RX_BUFFER_SIZE 64\r\n\r\n// DMA open loop continous circular buffer\r\n// 1ms delay periodic, chase DMA ptr around\r\nstatic uint8_t dma_rx_buffer[2][UART_RX_BUFFER_SIZE];\r\nstatic uint32_t dma_last_rcv_idx[2];\r\n\r\n// FIXME: the stdlib doesn't know about CMSIS threads, so this is just a global variable\r\n// static thread_local uint32_t deadline_ms = 0;\r\n\r\nosThreadId_t uartServerTaskHandle;\r\n\r\n\r\nclass UART4Sender : public StreamSink\r\n{\r\npublic:\r\n    UART4Sender()\r\n    {\r\n        channelType = CHANNEL_TYPE_UART4;\r\n    }\r\n\r\n    int process_bytes(const uint8_t* buffer, size_t length, size_t* processed_bytes) override\r\n    {\r\n        // Loop to ensure all bytes get sent\r\n        while (length)\r\n        {\r\n            size_t chunk = length < UART_TX_BUFFER_SIZE ? length : UART_TX_BUFFER_SIZE;\r\n            // wait for USB interface to become ready\r\n            // TODO: implement ring buffer to get a more continuous stream of data\r\n            // if (osSemaphoreWait(sem_uart_dma, deadline_to_timeout(deadline_ms)) != osOK)\r\n            if (osSemaphoreAcquire(sem_uart4_dma, PROTOCOL_SERVER_TIMEOUT_MS) != osOK)\r\n                return -1;\r\n            // transmit chunk\r\n            memcpy(tx_buf_, buffer, chunk);\r\n            if (HAL_UART_Transmit_DMA(&huart4, tx_buf_, chunk) != HAL_OK)\r\n                return -1;\r\n            buffer += chunk;\r\n            length -= chunk;\r\n            if (processed_bytes)\r\n                *processed_bytes += chunk;\r\n        }\r\n        return 0;\r\n    }\r\n\r\n    size_t get_free_space() override\r\n    { return SIZE_MAX; }\r\n\r\nprivate:\r\n    uint8_t tx_buf_[UART_TX_BUFFER_SIZE];\r\n} uart4_stream_output;\r\n\r\nclass UART5Sender : public StreamSink\r\n{\r\npublic:\r\n    UART5Sender()\r\n    {\r\n        channelType = CHANNEL_TYPE_UART5;\r\n    }\r\n\r\n    int process_bytes(const uint8_t* buffer, size_t length, size_t* processed_bytes) override\r\n    {\r\n        // Loop to ensure all bytes get sent\r\n        while (length)\r\n        {\r\n            size_t chunk = length < UART_TX_BUFFER_SIZE ? length : UART_TX_BUFFER_SIZE;\r\n            // wait for USB interface to become ready\r\n            // TODO: implement ring buffer to get a more continuous stream of data\r\n            // if (osSemaphoreWait(sem_uart_dma, deadline_to_timeout(deadline_ms)) != osOK)\r\n            if (osSemaphoreAcquire(sem_uart5_dma, PROTOCOL_SERVER_TIMEOUT_MS) != osOK)\r\n                return -1;\r\n            // transmit chunk\r\n            memcpy(tx_buf_, buffer, chunk);\r\n            if (HAL_UART_Transmit_DMA(&huart5, tx_buf_, chunk) != HAL_OK)\r\n                return -1;\r\n            buffer += chunk;\r\n            length -= chunk;\r\n            if (processed_bytes)\r\n                *processed_bytes += chunk;\r\n        }\r\n        return 0;\r\n    }\r\n\r\n    size_t get_free_space() override\r\n    { return SIZE_MAX; }\r\n\r\nprivate:\r\n    uint8_t tx_buf_[UART_TX_BUFFER_SIZE];\r\n} uart5_stream_output;\r\n\r\nStreamSink* uart4StreamOutputPtr = &uart4_stream_output;\r\nStreamBasedPacketSink uart4_packet_output(uart4_stream_output);\r\nBidirectionalPacketBasedChannel uart4_channel(uart4_packet_output);\r\nStreamToPacketSegmenter uart4_stream_input(uart4_channel);\r\n\r\nStreamSink* uart5StreamOutputPtr = &uart5_stream_output;\r\nStreamBasedPacketSink uart5_packet_output(uart5_stream_output);\r\nBidirectionalPacketBasedChannel uart5_channel(uart5_packet_output);\r\nStreamToPacketSegmenter uart5_stream_input(uart5_channel);\r\n\r\nstatic void UartServerTask(void* ctx)\r\n{\r\n    (void) ctx;\r\n\r\n    for (;;)\r\n    {\r\n        // Check for UART errors and restart recieve DMA transfer if required\r\n        if (huart4.ErrorCode != HAL_UART_ERROR_NONE)\r\n        {\r\n            HAL_UART_AbortReceive(&huart4);\r\n            HAL_UART_Receive_DMA(&huart4, dma_rx_buffer[0], sizeof(dma_rx_buffer[0]));\r\n        }\r\n        // Fetch the circular buffer \"write pointer\", where it would write next\r\n        uint32_t new_rcv_idx = UART_RX_BUFFER_SIZE - huart4.hdmarx->Instance->NDTR;\r\n\r\n        // deadline_ms = timeout_to_deadline(PROTOCOL_SERVER_TIMEOUT_MS);\r\n        // Process bytes in one or two chunks (two in case there was a wrap)\r\n        if (new_rcv_idx < dma_last_rcv_idx[0])\r\n        {\r\n            uart4_stream_input.process_bytes(dma_rx_buffer[0] + dma_last_rcv_idx[0],\r\n                                             UART_RX_BUFFER_SIZE - dma_last_rcv_idx[0],\r\n                                             nullptr); // TODO: use process_all\r\n            ASCII_protocol_parse_stream(dma_rx_buffer[0] + dma_last_rcv_idx[0],\r\n                                        UART_RX_BUFFER_SIZE - dma_last_rcv_idx[0], uart4_stream_output);\r\n            dma_last_rcv_idx[0] = 0;\r\n        }\r\n        if (new_rcv_idx > dma_last_rcv_idx[0])\r\n        {\r\n            uart4_stream_input.process_bytes(dma_rx_buffer[0] + dma_last_rcv_idx[0],\r\n                                             new_rcv_idx - dma_last_rcv_idx[0],\r\n                                             nullptr); // TODO: use process_all\r\n            ASCII_protocol_parse_stream(dma_rx_buffer[0] + dma_last_rcv_idx[0],\r\n                                        new_rcv_idx - dma_last_rcv_idx[0], uart4_stream_output);\r\n            dma_last_rcv_idx[0] = new_rcv_idx;\r\n        }\r\n\r\n\r\n        // Check for UART errors and restart recieve DMA transfer if required\r\n        if (huart5.ErrorCode != HAL_UART_ERROR_NONE)\r\n        {\r\n            HAL_UART_AbortReceive(&huart5);\r\n            HAL_UART_Receive_DMA(&huart5, dma_rx_buffer[1], sizeof(dma_rx_buffer[1]));\r\n        }\r\n        // Fetch the circular buffer \"write pointer\", where it would write next\r\n        new_rcv_idx = UART_RX_BUFFER_SIZE - huart5.hdmarx->Instance->NDTR;\r\n\r\n        // deadline_ms = timeout_to_deadline(PROTOCOL_SERVER_TIMEOUT_MS);\r\n        // Process bytes in one or two chunks (two in case there was a wrap)\r\n        if (new_rcv_idx < dma_last_rcv_idx[1])\r\n        {\r\n            uart4_stream_input.process_bytes(dma_rx_buffer[1] + dma_last_rcv_idx[1],\r\n                                             UART_RX_BUFFER_SIZE - dma_last_rcv_idx[1],\r\n                                             nullptr); // TODO: use process_all\r\n            ASCII_protocol_parse_stream(dma_rx_buffer[1] + dma_last_rcv_idx[1],\r\n                                        UART_RX_BUFFER_SIZE - dma_last_rcv_idx[1], uart5_stream_output);\r\n            dma_last_rcv_idx[1] = 0;\r\n        }\r\n        if (new_rcv_idx > dma_last_rcv_idx[1])\r\n        {\r\n            uart4_stream_input.process_bytes(dma_rx_buffer[1] + dma_last_rcv_idx[1],\r\n                                             new_rcv_idx - dma_last_rcv_idx[1],\r\n                                             nullptr); // TODO: use process_all\r\n            ASCII_protocol_parse_stream(dma_rx_buffer[1] + dma_last_rcv_idx[1],\r\n                                        new_rcv_idx - dma_last_rcv_idx[1], uart5_stream_output);\r\n            dma_last_rcv_idx[1] = new_rcv_idx;\r\n        }\r\n\r\n\r\n        osDelay(1);\r\n    };\r\n}\r\n\r\nconst osThreadAttr_t uartServerTask_attributes = {\r\n    .name = \"UartServerTask\",\r\n    .stack_size = 2000,\r\n    .priority = (osPriority_t) osPriorityNormal,\r\n};\r\n\r\nvoid StartUartServer()\r\n{\r\n    // DMA is set up to receive in a circular buffer forever.\r\n    // We don't use interrupts to fetch the data, instead we periodically read\r\n    // data out of the circular buffer into a parse buffer, controlled by a state machine\r\n    HAL_UART_Receive_DMA(&huart4, dma_rx_buffer[0], sizeof(dma_rx_buffer[0]));\r\n    dma_last_rcv_idx[0] = UART_RX_BUFFER_SIZE - huart4.hdmarx->Instance->NDTR;\r\n\r\n    HAL_UART_Receive_DMA(&huart5, dma_rx_buffer[1], sizeof(dma_rx_buffer[1]));\r\n    dma_last_rcv_idx[1] = UART_RX_BUFFER_SIZE - huart5.hdmarx->Instance->NDTR;\r\n\r\n    // Start UART communication thread\r\n    uartServerTaskHandle = osThreadNew(UartServerTask, nullptr, &uartServerTask_attributes);\r\n}\r\n\r\nvoid HAL_UART_TxCpltCallback(UART_HandleTypeDef* huart)\r\n{\r\n    if (huart->Instance == UART4)\r\n        osSemaphoreRelease(sem_uart4_dma);\r\n    else if (huart->Instance == UART5)\r\n        osSemaphoreRelease(sem_uart5_dma);\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_uart.hpp",
    "content": "#ifndef __INTERFACE_UART_HPP\n#define __INTERFACE_UART_HPP\n\n#ifdef __cplusplus\n\n#include \"fibre/protocol.hpp\"\n\nextern StreamSink *uart4StreamOutputPtr;\nextern StreamSink *uart5StreamOutputPtr;\n\nextern \"C\" {\n#endif\n\n#include <cmsis_os.h>\n\nextern osThreadId uart_thread;\n\nvoid StartUartServer(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __INTERFACE_UART_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_usb.cpp",
    "content": "#include \"common_inc.h\"\r\n#include \"ascii_processor.hpp\"\r\n#include \"usbd_cdc.h\"\r\n#include \"usbd_cdc_if.h\"\r\n#include \"usb_device.h\"\r\n#include \"interface_usb.hpp\"\r\n\r\nosThreadId_t usbServerTaskHandle;\r\nUSBStats_t usb_stats_ = {0};\r\n\r\nclass USBSender : public PacketSink\r\n{\r\npublic:\r\n    USBSender(uint8_t endpoint_pair, const osSemaphoreId &sem_usb_tx)\r\n        : endpoint_pair_(endpoint_pair), sem_usb_tx_(sem_usb_tx)\r\n    {}\r\n\r\n    int process_packet(const uint8_t *buffer, size_t length) override\r\n    {\r\n        // cannot send partial packets\r\n        if (length > USB_TX_DATA_SIZE)\r\n            return -1;\r\n        // wait for USB interface to become ready\r\n        if (osSemaphoreAcquire(sem_usb_tx_, PROTOCOL_SERVER_TIMEOUT_MS) != osOK)\r\n        {\r\n            // If the host resets the device it might be that the TX-complete handler is never called\r\n            // and the sem_usb_tx_ semaphore is never released. To handle this we just override the\r\n            // TX buffer if this wait times out. The implication is that the channel is no longer lossless.\r\n            // TODO: handle endpoint reset properly\r\n            usb_stats_.tx_overrun_cnt++;\r\n        }\r\n\r\n        // transmit packet\r\n        uint8_t status = CDC_Transmit_FS(const_cast<uint8_t *>(buffer), length, endpoint_pair_);\r\n        if (status != USBD_OK)\r\n        {\r\n            osSemaphoreRelease(sem_usb_tx_);\r\n            return -1;\r\n        }\r\n        usb_stats_.tx_cnt++;\r\n\r\n        return 0;\r\n    }\r\n\r\nprivate:\r\n    uint8_t endpoint_pair_;\r\n    const osSemaphoreId &sem_usb_tx_;\r\n};\r\n\r\n// Note we could have independent semaphores here to allow concurrent transmission\r\nUSBSender usb_packet_output_cdc(CDC_OUT_EP, sem_usb_tx);\r\nUSBSender usb_packet_output_native(ODRIVE_OUT_EP, sem_usb_tx);\r\n\r\nclass TreatPacketSinkAsStreamSink : public StreamSink\r\n{\r\npublic:\r\n    TreatPacketSinkAsStreamSink(PacketSink &output) : output_(output)\r\n    {\r\n        channelType = CHANNEL_TYPE_USB;\r\n    }\r\n\r\n    int process_bytes(const uint8_t *buffer, size_t length, size_t *processed_bytes)\r\n    {\r\n        // Loop to ensure all bytes get sent\r\n        while (length)\r\n        {\r\n            size_t chunk = length < USB_TX_DATA_SIZE ? length : USB_TX_DATA_SIZE;\r\n            if (output_.process_packet(buffer, length) != 0)\r\n                return -1;\r\n            buffer += chunk;\r\n            length -= chunk;\r\n            if (processed_bytes)\r\n                *processed_bytes += chunk;\r\n        }\r\n        return 0;\r\n    }\r\n\r\n    size_t get_free_space()\r\n    { return SIZE_MAX; }\r\n\r\n\r\n\r\nprivate:\r\n    PacketSink &output_;\r\n} usb_stream_output(usb_packet_output_cdc);\r\n\r\n// This is used by the printf feature. Hence the above statics, and below seemingly random ptr (it's externed)\r\n// TODO: less spaghetti code\r\nStreamSink *usbStreamOutputPtr = &usb_stream_output;\r\n\r\nBidirectionalPacketBasedChannel usb_channel(usb_packet_output_native);\r\n\r\n\r\nstruct USBInterface\r\n{\r\n    uint8_t *rx_buf = nullptr;\r\n    uint32_t rx_len = 0;\r\n    bool data_pending = false;\r\n    uint8_t out_ep;\r\n    uint8_t in_ep;\r\n    USBSender &usb_sender;\r\n};\r\n\r\n// Note: statics make this less modular.\r\n// Note: we use a single rx semaphore and loop over data_pending to allow a single pump loop thread\r\nstatic USBInterface CDC_interface = {\r\n    .rx_buf = nullptr,\r\n    .rx_len = 0,\r\n    .data_pending = false,\r\n    .out_ep = CDC_OUT_EP,\r\n    .in_ep = CDC_IN_EP,\r\n    .usb_sender = usb_packet_output_cdc,\r\n};\r\nstatic USBInterface ODrive_interface = {\r\n    .rx_buf = nullptr,\r\n    .rx_len = 0,\r\n    .data_pending = false,\r\n    .out_ep = ODRIVE_OUT_EP,\r\n    .in_ep = ODRIVE_IN_EP,\r\n    .usb_sender = usb_packet_output_native,\r\n};\r\n\r\nstatic void UsbServerTask(void *ctx)\r\n{\r\n    (void) ctx;\r\n\r\n    for (;;)\r\n    {\r\n        // const uint32_t usb_check_timeout = 1; // ms\r\n        osStatus sem_stat = osSemaphoreAcquire(sem_usb_rx, osWaitForever);\r\n        if (sem_stat == osOK)\r\n        {\r\n            usb_stats_.rx_cnt++;\r\n\r\n            // CDC Interface\r\n            if (CDC_interface.data_pending)\r\n            {\r\n                CDC_interface.data_pending = false;\r\n\r\n                ASCII_protocol_parse_stream(CDC_interface.rx_buf, CDC_interface.rx_len, usb_stream_output);\r\n                USBD_CDC_ReceivePacket(&hUsbDeviceFS, CDC_interface.out_ep);  // Allow next packet\r\n            }\r\n\r\n            // Native Interface\r\n            if (ODrive_interface.data_pending)\r\n            {\r\n                ODrive_interface.data_pending = false;\r\n                usb_channel.process_packet(ODrive_interface.rx_buf, ODrive_interface.rx_len);\r\n                USBD_CDC_ReceivePacket(&hUsbDeviceFS, ODrive_interface.out_ep);  // Allow next packet\r\n            }\r\n        }\r\n    }\r\n}\r\n\r\n// Called from CDC_Receive_FS callback function, this allows the communication\r\n// thread to handle the incoming data\r\nvoid usb_rx_process_packet(uint8_t *buf, uint32_t len, uint8_t endpoint_pair)\r\n{\r\n    USBInterface *usb_iface;\r\n    if (endpoint_pair == CDC_interface.out_ep)\r\n    {\r\n        usb_iface = &CDC_interface;\r\n    } else if (endpoint_pair == ODrive_interface.out_ep)\r\n    {\r\n        usb_iface = &ODrive_interface;\r\n    } else\r\n    {\r\n        return;\r\n    }\r\n\r\n    // We don't allow the next USB packet until the previous one has been processed completely.\r\n    // Therefore it's safe to write to these vars directly since we know previous processing is complete.\r\n    usb_iface->rx_buf = buf;\r\n    usb_iface->rx_len = len;\r\n    usb_iface->data_pending = true;\r\n    osSemaphoreRelease(sem_usb_rx);\r\n}\r\n\r\n\r\nconst osThreadAttr_t usbServerTask_attributes = {\r\n    .name = \"UsbServerTask\",\r\n    .stack_size = 2000,\r\n    .priority = (osPriority_t) osPriorityNormal,\r\n};\r\n\r\nvoid StartUsbServer()\r\n{\r\n    // Start USB communication thread\r\n    usbServerTaskHandle = osThreadNew(UsbServerTask, nullptr, &usbServerTask_attributes);\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/communication/interface_usb.hpp",
    "content": "#ifndef __INTERFACE_USB_HPP\n#define __INTERFACE_USB_HPP\n\n#ifdef __cplusplus\n\n#include \"fibre/protocol.hpp\"\n\nextern StreamSink *usbStreamOutputPtr;\n\nextern \"C\" {\n#endif\n\n#include <cmsis_os.h>\n#include <stdint.h>\n\ntypedef struct\n{\n    uint32_t rx_cnt;\n    uint32_t tx_cnt;\n    uint32_t tx_overrun_cnt;\n} USBStats_t;\n\nextern USBStats_t usb_stats_;\n\nvoid usb_rx_process_packet(uint8_t *buf, uint32_t len, uint8_t endpoint_pair);\nvoid StartUsbServer(void);\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif // __INTERFACE_USB_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/analog.cpp",
    "content": "#include \"analog.hpp\"\n\nfloat Analog::GetChipTemperature()\n{\n    return AdcGetChipTemperature();\n}\n\nfloat Analog::GetVoltage(Analog::AdcChannel_t _channel)\n{\n    switch (_channel)\n    {\n        case CH1:\n            return AdcGetVoltage(ADC_CH1);\n        case CH2:\n            return AdcGetVoltage(ADC_CH2);\n        case CH3:\n            return AdcGetVoltage(ADC_CH3);\n        case CH4:\n            return AdcGetVoltage(ADC_CH4);\n    }\n\n    return 0;\n}\n\nuint16_t Analog::GetRaw(Analog::AdcChannel_t _channel)\n{\n    switch (_channel)\n    {\n        case CH1:\n            return AdcGetRaw(ADC_CH1);\n        case CH2:\n            return AdcGetRaw(ADC_CH2);\n        case CH3:\n            return AdcGetRaw(ADC_CH3);\n        case CH4:\n            return AdcGetRaw(ADC_CH4);\n    }\n\n    return 0;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/analog.hpp",
    "content": "#ifndef REF_STM32F4_ANALOG_H\n#define REF_STM32F4_ANALOG_H\n\n#include <cstdint>\n#include <adc.h>\n\nclass Analog\n{\nprivate:\n\npublic:\n    enum AdcChannel_t\n    {\n        CH1,\n        CH2,\n        CH3,\n        CH4\n    };\n\n    Analog()\n    = default;\n\n    float GetChipTemperature();\n\n    float GetVoltage(AdcChannel_t _channel);\n\n    uint16_t GetRaw(AdcChannel_t _channel);\n};\n\n#endif //REF_STM32F4_ANALOG_H\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/encoder.cpp",
    "content": "#include \"encoder.hpp\"\n\nEncoder::Encoder(TIM_HandleTypeDef *_htim, uint16_t _cpr, bool _inverse) :\n    htim(_htim), config(Config_t{})\n{\n    config.cpr = _cpr;\n    config.inverse = _inverse;\n}\n\nint64_t Encoder::GetCount()\n{\n    int64_t count = GetCntLoop(htim->Instance) * 65536 + htim->Instance->CNT;\n\n    return config.inverse ? -count : count;\n}\n\nfloat Encoder::GetAngle(bool _useRAD)\n{\n    float angle = (float) GetCount() / (float) config.cpr;\n\n    return _useRAD ? angle / RAD_TO_DEG : angle;\n}\n\nvoid Encoder::Start()\n{\n    ClearCntLoop(htim->Instance);\n    htim->Instance->CNT = 0;\n    HAL_TIM_Encoder_Start_IT(htim, TIM_CHANNEL_ALL);\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/encoder.hpp",
    "content": "#ifndef REF_STM32F4_ENCODER_HPP\n#define REF_STM32F4_ENCODER_HPP\n\n#include <fibre/protocol.hpp>\n#include \"tim.h\"\n\nclass Encoder\n{\nprivate:\n    const float RAD_TO_DEG = 57.295777754771045f;\n\n    TIM_HandleTypeDef *htim;\n\npublic:\n    explicit Encoder(TIM_HandleTypeDef *_htim, uint16_t _cpr = 4096, bool _inverse = false);\n\n    void Start();\n\n    int64_t GetCount();\n\n    float GetAngle(bool _useRAD = false);\n\n    struct Config_t\n    {\n        uint16_t cpr;\n\n        bool inverse;\n    };\n\n    // Communication protocol definitions\n    auto MakeProtocolDefinitions()\n    {\n        return make_protocol_member_list(\n            make_protocol_object(\"config\",\n                                 make_protocol_property(\"cpr\", &config.cpr),\n                                 make_protocol_property(\"inverse\", &config.inverse)\n            ),\n            make_protocol_function(\"get_count\", *this, &Encoder::GetCount),\n            make_protocol_function(\"get_angle\", *this, &Encoder::GetAngle, \"use_rad\")\n        );\n    }\n\n    Config_t config;\n};\n\n#endif //REF_STM32F4_ENCODER_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/pwm.cpp",
    "content": "#include \"pwm.hpp\"\n\nPWM::PWM(uint32_t _freqHzA, uint32_t _freqHzB)\n{\n    if (_freqHzA > 84000)_freqHzA = 84000;\n    else if (_freqHzA < 10)_freqHzA = 10;\n\n    if (_freqHzB > 84000)_freqHzB = 84000;\n    else if (_freqHzB < 10)_freqHzB = 10;\n\n\n    TIM_OC_InitTypeDef sConfigOC = {0};\n\n    htim9.Instance = TIM9;\n    htim9.Init.Prescaler = 168000 / _freqHzA - 1;\n    htim9.Init.CounterMode = TIM_COUNTERMODE_UP;\n    htim9.Init.Period = 999;\n    htim9.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n    htim9.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n    if (HAL_TIM_PWM_Init(&htim9) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    sConfigOC.OCMode = TIM_OCMODE_PWM1;\n    sConfigOC.Pulse = 0;\n    sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;\n    sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;\n    if (HAL_TIM_PWM_ConfigChannel(&htim9, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    if (HAL_TIM_PWM_ConfigChannel(&htim9, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    HAL_TIM_MspPostInit(&htim9);\n\n    htim12.Instance = TIM12;\n    htim12.Init.Prescaler = 84000 / _freqHzB - 1;\n    htim12.Init.CounterMode = TIM_COUNTERMODE_UP;\n    htim12.Init.Period = 999;\n    htim12.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n    htim12.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n    if (HAL_TIM_PWM_Init(&htim12) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    sConfigOC.OCMode = TIM_OCMODE_PWM1;\n    sConfigOC.Pulse = 0;\n    sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;\n    sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;\n    if (HAL_TIM_PWM_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    if (HAL_TIM_PWM_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)\n    {\n        Error_Handler();\n    }\n    HAL_TIM_MspPostInit(&htim12);\n\n}\n\nvoid PWM::Start(PWM::PwmChannel_t _channel)\n{\n    switch (_channel)\n    {\n        case CH_A1:\n            TIM9->CCR1 = 0;\n            HAL_TIM_PWM_Start(&htim9, TIM_CHANNEL_1);\n            break;\n        case CH_A2:\n            TIM9->CCR2 = 0;\n            HAL_TIM_PWM_Start(&htim9, TIM_CHANNEL_2);\n            break;\n        case CH_B1:\n            TIM12->CCR1 = 0;\n            HAL_TIM_PWM_Start(&htim12, TIM_CHANNEL_1);\n            break;\n        case CH_B2:\n            TIM12->CCR2 = 0;\n            HAL_TIM_PWM_Start(&htim12, TIM_CHANNEL_2);\n            break;\n        case CH_ALL:\n            TIM9->CCR1 = 0;\n            HAL_TIM_PWM_Start(&htim9, TIM_CHANNEL_1);\n            TIM9->CCR2 = 0;\n            HAL_TIM_PWM_Start(&htim9, TIM_CHANNEL_2);\n            TIM12->CCR1 = 0;\n            HAL_TIM_PWM_Start(&htim12, TIM_CHANNEL_1);\n            TIM12->CCR2 = 0;\n            HAL_TIM_PWM_Start(&htim12, TIM_CHANNEL_2);\n            break;\n    }\n}\n\nvoid PWM::SetDuty(PWM::PwmChannel_t _channel, float _duty)\n{\n    if (_duty > 1)_duty = 1;\n    else if (_duty < 0)_duty = 0;\n\n    auto ccr = static_cast<uint32_t>(1000 * _duty);\n\n    switch (_channel)\n    {\n        case CH_A1:\n            TIM9->CCR1 = ccr;\n            break;\n        case CH_A2:\n            TIM9->CCR2 = ccr;\n            break;\n        case CH_B1:\n            TIM12->CCR1 = ccr;\n            break;\n        case CH_B2:\n            TIM12->CCR2 = ccr;\n            break;\n        case CH_ALL:\n            TIM9->CCR1 = ccr;\n            TIM9->CCR2 = ccr;\n            TIM12->CCR1 = ccr;\n            TIM12->CCR2 = ccr;\n            break;\n    }\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/gpio/pwm.hpp",
    "content": "#ifndef REF_STM32F4_PWM_H\n#define REF_STM32F4_PWM_H\n\n#include <cstdint>\n#include <tim.h>\n\nclass PWM\n{\nprivate:\n\npublic:\n    enum PwmChannel_t\n    {\n        CH_ALL,\n        // TIM\n        CH_A1,\n        CH_A2,\n        CH_B1,\n        CH_B2\n    };\n\n    explicit PWM(uint32_t _freqHzA = 21000, uint32_t _freqHzB = 21000);\n\n    void Start(PwmChannel_t _channel = CH_ALL);\n\n    void SetDuty(PwmChannel_t _channel = CH_ALL, float _duty = 0);\n\n};\n\n#endif //REF_STM32F4_PWM_H\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/MPU6050.cpp",
    "content": "// I2Cdev library collection - MPU6050 I2C device class\n// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)\n// 8/24/2011 by Jeff Rowberg <jeff@rowberg.net>\n// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib\n//\n// Changelog:\n//     ... - ongoing debug release\n\n// NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE\n// DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF\n// YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING.\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2012 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#include \"mpu6050.hpp\"\n\n#define pgm_read_byte(addr)   (*(const unsigned char *)(addr))\n\n/** Specific address constructor.\n * @param address I2C address, uses default I2C address if none is specified\n * @see MPU6050_DEFAULT_ADDRESS\n * @see MPU6050_ADDRESS_AD0_LOW\n * @see MPU6050_ADDRESS_AD0_HIGH\n */\nMPU6050::MPU6050(I2C_HandleTypeDef *_hi2c, uint8_t address) : hi2c(_hi2c), devAddr(address)\n{\n    I2Cdev_init(hi2c);\n\n    InitFilter();\n}\n\n/** Power on and prepare for general usage.\n * This will activate the device and take it out of sleep mode (which must be done\n * after start-up). This function also sets both the accelerometer and the gyroscope\n * to their most sensitive settings, namely +/- 2g and +/- 250 degrees/sec, and sets\n * the clock source to use the X Gyro for reference, which is slightly better than\n * the default internal clock source.\n */\nvoid MPU6050::Init()\n{\n    setClockSource(MPU6050_CLOCK_PLL_XGYRO);\n    setFullScaleGyroRange(MPU6050_GYRO_FS_250);\n    setFullScaleAccelRange(MPU6050_ACCEL_FS_2);\n    setDLPFMode(MPU6050_DLPF_BW_98);\n    setSleepEnabled(false); // thanks to Jack Elston for pointing this one out!\n}\n\n/** Verify the I2C connection.\n * Make sure the device is connected and responds as expected.\n * @return True if connection is valid, false otherwise\n */\nbool MPU6050::testConnection()\n{\n    return getDeviceID() == 0x34;\n}\n\n// AUX_VDDIO register (InvenSense demo code calls this RA_*G_OFFS_TC)\n\n/** Get the auxiliary I2C supply voltage level.\n * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to\n * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to\n * the MPU-6000, which does not have a VLOGIC pin.\n * @return I2C supply voltage level (0=VLOGIC, 1=VDD)\n */\nuint8_t MPU6050::getAuxVDDIOLevel()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set the auxiliary I2C supply voltage level.\n * When set to 1, the auxiliary I2C bus high logic level is VDD. When cleared to\n * 0, the auxiliary I2C bus high logic level is VLOGIC. This does not apply to\n * the MPU-6000, which does not have a VLOGIC pin.\n * @param level I2C supply voltage level (0=VLOGIC, 1=VDD)\n */\nvoid MPU6050::setAuxVDDIOLevel(uint8_t level)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_PWR_MODE_BIT, level);\n}\n\n// SMPLRT_DIV register\n\n/** Get gyroscope output rate divider.\n * The sensor register output, FIFO output, DMP sampling, Motion detection, Zero\n * Motion detection, and Free Fall detection are all based on the Sample Rate.\n * The Sample Rate is generated by dividing the gyroscope output rate by\n * SMPLRT_DIV:\n *\n * Sample Rate = Gyroscope Output Rate / (1 + SMPLRT_DIV)\n *\n * where Gyroscope Output Rate = 8kHz when the DLPF is disabled (DLPF_CFG = 0 or\n * 7), and 1kHz when the DLPF is enabled (see Register 26).\n *\n * Note: The accelerometer output rate is 1kHz. This means that for a Sample\n * Rate greater than 1kHz, the same accelerometer sample may be output to the\n * FIFO, DMP, and sensor registers more than once.\n *\n * For a diagram of the gyroscope and accelerometer signal paths, see Section 8\n * of the MPU-6000/MPU-6050 Product Specification document.\n *\n * @return Current sample rate\n * @see MPU6050_RA_SMPLRT_DIV\n */\nuint8_t MPU6050::getRate()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SMPLRT_DIV, buffer);\n    return buffer[0];\n}\n\n/** Set gyroscope sample rate divider.\n * @param rate New sample rate divider\n * @see getRate()\n * @see MPU6050_RA_SMPLRT_DIV\n */\nvoid MPU6050::setRate(uint8_t rate)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_SMPLRT_DIV, rate);\n}\n\n// CONFIG register\n\n/** Get external FSYNC configuration.\n * Configures the external Frame Synchronization (FSYNC) pin sampling. An\n * external signal connected to the FSYNC pin can be sampled by configuring\n * EXT_SYNC_SET. Signal changes to the FSYNC pin are latched so that short\n * strobes may be captured. The latched FSYNC signal will be sampled at the\n * Sampling Rate, as defined in register 25. After sampling, the latch will\n * reset to the current FSYNC signal state.\n *\n * The sampled value will be reported in place of the least significant bit in\n * a sensor data register determined by the value of EXT_SYNC_SET according to\n * the following table.\n *\n * <pre>\n * EXT_SYNC_SET | FSYNC Bit Location\n * -------------+-------------------\n * 0            | Input disabled\n * 1            | TEMP_OUT_L[0]\n * 2            | GYRO_XOUT_L[0]\n * 3            | GYRO_YOUT_L[0]\n * 4            | GYRO_ZOUT_L[0]\n * 5            | ACCEL_XOUT_L[0]\n * 6            | ACCEL_YOUT_L[0]\n * 7            | ACCEL_ZOUT_L[0]\n * </pre>\n *\n * @return FSYNC configuration value\n */\nuint8_t MPU6050::getExternalFrameSync()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set external FSYNC configuration.\n * @see getExternalFrameSync()\n * @see MPU6050_RA_CONFIG\n * @param sync New FSYNC configuration value\n */\nvoid MPU6050::setExternalFrameSync(uint8_t sync)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_EXT_SYNC_SET_BIT, MPU6050_CFG_EXT_SYNC_SET_LENGTH, sync);\n}\n\n/** Get digital low-pass filter configuration.\n * The DLPF_CFG parameter sets the digital low pass filter configuration. It\n * also determines the internal sampling rate used by the device as shown in\n * the table below.\n *\n * Note: The accelerometer output rate is 1kHz. This means that for a Sample\n * Rate greater than 1kHz, the same accelerometer sample may be output to the\n * FIFO, DMP, and sensor registers more than once.\n *\n * <pre>\n *          |   ACCELEROMETER    |           GYROSCOPE\n * DLPF_CFG | Bandwidth | Delay  | Bandwidth | Delay  | Sample Rate\n * ---------+-----------+--------+-----------+--------+-------------\n * 0        | 260Hz     | 0ms    | 256Hz     | 0.98ms | 8kHz\n * 1        | 184Hz     | 2.0ms  | 188Hz     | 1.9ms  | 1kHz\n * 2        | 94Hz      | 3.0ms  | 98Hz      | 2.8ms  | 1kHz\n * 3        | 44Hz      | 4.9ms  | 42Hz      | 4.8ms  | 1kHz\n * 4        | 21Hz      | 8.5ms  | 20Hz      | 8.3ms  | 1kHz\n * 5        | 10Hz      | 13.8ms | 10Hz      | 13.4ms | 1kHz\n * 6        | 5Hz       | 19.0ms | 5Hz       | 18.6ms | 1kHz\n * 7        |   -- Reserved --   |   -- Reserved --   | Reserved\n * </pre>\n *\n * @return DLFP configuration\n * @see MPU6050_RA_CONFIG\n * @see MPU6050_CFG_DLPF_CFG_BIT\n * @see MPU6050_CFG_DLPF_CFG_LENGTH\n */\nuint8_t MPU6050::getDLPFMode()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set digital low-pass filter configuration.\n * @param mode New DLFP configuration setting\n * @see getDLPFBandwidth()\n * @see MPU6050_DLPF_BW_256\n * @see MPU6050_RA_CONFIG\n * @see MPU6050_CFG_DLPF_CFG_BIT\n * @see MPU6050_CFG_DLPF_CFG_LENGTH\n */\nvoid MPU6050::setDLPFMode(uint8_t mode)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_CONFIG, MPU6050_CFG_DLPF_CFG_BIT, MPU6050_CFG_DLPF_CFG_LENGTH, mode);\n}\n\n// GYRO_CONFIG register\n\n/** Get full-scale gyroscope range.\n * The FS_SEL parameter allows setting the full-scale range of the gyro sensors,\n * as described in the table below.\n *\n * <pre>\n * 0 = +/- 250 degrees/sec\n * 1 = +/- 500 degrees/sec\n * 2 = +/- 1000 degrees/sec\n * 3 = +/- 2000 degrees/sec\n * </pre>\n *\n * @return Current full-scale gyroscope range setting\n * @see MPU6050_GYRO_FS_250\n * @see MPU6050_RA_GYRO_CONFIG\n * @see MPU6050_GCONFIG_FS_SEL_BIT\n * @see MPU6050_GCONFIG_FS_SEL_LENGTH\n */\nuint8_t MPU6050::getFullScaleGyroRange()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set full-scale gyroscope range.\n * @param range New full-scale gyroscope range value\n * @see getFullScaleRange()\n * @see MPU6050_GYRO_FS_250\n * @see MPU6050_RA_GYRO_CONFIG\n * @see MPU6050_GCONFIG_FS_SEL_BIT\n * @see MPU6050_GCONFIG_FS_SEL_LENGTH\n */\nvoid MPU6050::setFullScaleGyroRange(uint8_t range)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_GYRO_CONFIG, MPU6050_GCONFIG_FS_SEL_BIT, MPU6050_GCONFIG_FS_SEL_LENGTH,\n                     range);\n\n    switch (range)\n    {\n        case MPU6050_GYRO_FS_250:\n            gyroRangeScale = 32768 / 250.0;\n            break;\n        case MPU6050_GYRO_FS_500:\n            gyroRangeScale = 32768 / 500.0;\n            break;\n        case MPU6050_GYRO_FS_1000:\n            gyroRangeScale = 32768 / 1000.0;\n            break;\n        case MPU6050_GYRO_FS_2000:\n            gyroRangeScale = 32768 / 2000.0;\n            break;\n        default:\n            break;\n    }\n}\n\n// SELF TEST FACTORY TRIM VALUES\n\n/** Get self-test factory trim value for accelerometer X axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_X\n */\nuint8_t MPU6050::getAccelXSelfTestFactoryTrim()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_X, &buffer[0]);\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_A, &buffer[1]);\n    return (buffer[0] >> 3) | ((buffer[1] >> 4) & 0x03);\n}\n\n/** Get self-test factory trim value for accelerometer Y axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_Y\n */\nuint8_t MPU6050::getAccelYSelfTestFactoryTrim()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_Y, &buffer[0]);\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_A, &buffer[1]);\n    return (buffer[0] >> 3) | ((buffer[1] >> 2) & 0x03);\n}\n\n/** Get self-test factory trim value for accelerometer Z axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_Z\n */\nuint8_t MPU6050::getAccelZSelfTestFactoryTrim()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_SELF_TEST_Z, 2, buffer);\n    return (buffer[0] >> 3) | (buffer[1] & 0x03);\n}\n\n/** Get self-test factory trim value for gyro X axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_X\n */\nuint8_t MPU6050::getGyroXSelfTestFactoryTrim()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_X, buffer);\n    return (buffer[0] & 0x1F);\n}\n\n/** Get self-test factory trim value for gyro Y axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_Y\n */\nuint8_t MPU6050::getGyroYSelfTestFactoryTrim()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_Y, buffer);\n    return (buffer[0] & 0x1F);\n}\n\n/** Get self-test factory trim value for gyro Z axis.\n * @return factory trim value\n * @see MPU6050_RA_SELF_TEST_Z\n */\nuint8_t MPU6050::getGyroZSelfTestFactoryTrim()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_SELF_TEST_Z, buffer);\n    return (buffer[0] & 0x1F);\n}\n\n// ACCEL_CONFIG register\n\n/** Get self-test enabled setting for accelerometer X axis.\n * @return Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nbool MPU6050::getAccelXSelfTest()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get self-test enabled setting for accelerometer X axis.\n * @param enabled Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nvoid MPU6050::setAccelXSelfTest(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_XA_ST_BIT, enabled);\n}\n\n/** Get self-test enabled value for accelerometer Y axis.\n * @return Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nbool MPU6050::getAccelYSelfTest()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get self-test enabled value for accelerometer Y axis.\n * @param enabled Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nvoid MPU6050::setAccelYSelfTest(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_YA_ST_BIT, enabled);\n}\n\n/** Get self-test enabled value for accelerometer Z axis.\n * @return Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nbool MPU6050::getAccelZSelfTest()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set self-test enabled value for accelerometer Z axis.\n * @param enabled Self-test enabled value\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nvoid MPU6050::setAccelZSelfTest(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ZA_ST_BIT, enabled);\n}\n\n/** Get full-scale accelerometer range.\n * The FS_SEL parameter allows setting the full-scale range of the accelerometer\n * sensors, as described in the table below.\n *\n * <pre>\n * 0 = +/- 2g\n * 1 = +/- 4g\n * 2 = +/- 8g\n * 3 = +/- 16g\n * </pre>\n *\n * @return Current full-scale accelerometer range setting\n * @see MPU6050_ACCEL_FS_2\n * @see MPU6050_RA_ACCEL_CONFIG\n * @see MPU6050_ACONFIG_AFS_SEL_BIT\n * @see MPU6050_ACONFIG_AFS_SEL_LENGTH\n */\nuint8_t MPU6050::getFullScaleAccelRange()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set full-scale accelerometer range.\n * @param range New full-scale accelerometer range setting\n * @see getFullScaleAccelRange()\n */\nvoid MPU6050::setFullScaleAccelRange(uint8_t range)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_AFS_SEL_BIT, MPU6050_ACONFIG_AFS_SEL_LENGTH,\n                     range);\n\n    switch (range)\n    {\n        case MPU6050_ACCEL_FS_2:\n            accRangeScale = 32768 / 2.0;\n            break;\n        case MPU6050_ACCEL_FS_4:\n            accRangeScale = 32768 / 4.0;\n            break;\n        case MPU6050_ACCEL_FS_8:\n            accRangeScale = 32768 / 8.0;\n            break;\n        case MPU6050_ACCEL_FS_16:\n            accRangeScale = 32768 / 16.0;\n            break;\n        default:\n            break;\n    }\n}\n\n/** Get the high-pass filter configuration.\n * The DHPF is a filter module in the path leading to motion detectors (Free\n * Fall, Motion threshold, and Zero Motion). The high pass filter output is not\n * available to the data registers (see Figure in Section 8 of the MPU-6000/\n * MPU-6050 Product Specification document).\n *\n * The high pass filter has three modes:\n *\n * <pre>\n *    Reset: The filter output settles to zero within one sample. This\n *           effectively disables the high pass filter. This mode may be toggled\n *           to quickly settle the filter.\n *\n *    On:    The high pass filter will pass signals above the cut off frequency.\n *\n *    Hold:  When triggered, the filter holds the present sample. The filter\n *           output will be the difference between the input sample and the held\n *           sample.\n * </pre>\n *\n * <pre>\n * ACCEL_HPF | Filter Mode | Cut-off Frequency\n * ----------+-------------+------------------\n * 0         | Reset       | None\n * 1         | On          | 5Hz\n * 2         | On          | 2.5Hz\n * 3         | On          | 1.25Hz\n * 4         | On          | 0.63Hz\n * 7         | Hold        | None\n * </pre>\n *\n * @return Current high-pass filter configuration\n * @see MPU6050_DHPF_RESET\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nuint8_t MPU6050::getDHPFMode()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set the high-pass filter configuration.\n * @param bandwidth New high-pass filter configuration\n * @see setDHPFMode()\n * @see MPU6050_DHPF_RESET\n * @see MPU6050_RA_ACCEL_CONFIG\n */\nvoid MPU6050::setDHPFMode(uint8_t bandwidth)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_ACCEL_CONFIG, MPU6050_ACONFIG_ACCEL_HPF_BIT, MPU6050_ACONFIG_ACCEL_HPF_LENGTH,\n                     bandwidth);\n}\n\n// FF_THR register\n\n/** Get free-fall event acceleration threshold.\n * This register configures the detection threshold for Free Fall event\n * detection. The unit of FF_THR is 1LSB = 2mg. Free Fall is detected when the\n * absolute value of the accelerometer measurements for the three axes are each\n * less than the detection threshold. This condition increments the Free Fall\n * duration counter (Register 30). The Free Fall interrupt is triggered when the\n * Free Fall duration counter reaches the time specified in FF_DUR.\n *\n * For more details on the Free Fall detection interrupt, see Section 8.2 of the\n * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and\n * 58 of this document.\n *\n * @return Current free-fall acceleration threshold value (LSB = 2mg)\n * @see MPU6050_RA_FF_THR\n */\nuint8_t MPU6050::getFreefallDetectionThreshold()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_FF_THR, buffer);\n    return buffer[0];\n}\n\n/** Get free-fall event acceleration threshold.\n * @param threshold New free-fall acceleration threshold value (LSB = 2mg)\n * @see getFreefallDetectionThreshold()\n * @see MPU6050_RA_FF_THR\n */\nvoid MPU6050::setFreefallDetectionThreshold(uint8_t threshold)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_FF_THR, threshold);\n}\n\n// FF_DUR register\n\n/** Get free-fall event duration threshold.\n * This register configures the duration counter threshold for Free Fall event\n * detection. The duration counter ticks at 1kHz, therefore FF_DUR has a unit\n * of 1 LSB = 1 ms.\n *\n * The Free Fall duration counter increments while the absolute value of the\n * accelerometer measurements are each less than the detection threshold\n * (Register 29). The Free Fall interrupt is triggered when the Free Fall\n * duration counter reaches the time specified in this register.\n *\n * For more details on the Free Fall detection interrupt, see Section 8.2 of\n * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56\n * and 58 of this document.\n *\n * @return Current free-fall duration threshold value (LSB = 1ms)\n * @see MPU6050_RA_FF_DUR\n */\nuint8_t MPU6050::getFreefallDetectionDuration()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_FF_DUR, buffer);\n    return buffer[0];\n}\n\n/** Get free-fall event duration threshold.\n * @param duration New free-fall duration threshold value (LSB = 1ms)\n * @see getFreefallDetectionDuration()\n * @see MPU6050_RA_FF_DUR\n */\nvoid MPU6050::setFreefallDetectionDuration(uint8_t duration)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_FF_DUR, duration);\n}\n\n// MOT_THR register\n\n/** Get motion detection event acceleration threshold.\n * This register configures the detection threshold for Motion interrupt\n * generation. The unit of MOT_THR is 1LSB = 2mg. Motion is detected when the\n * absolute value of any of the accelerometer measurements exceeds this Motion\n * detection threshold. This condition increments the Motion detection duration\n * counter (Register 32). The Motion detection interrupt is triggered when the\n * Motion Detection counter reaches the time count specified in MOT_DUR\n * (Register 32).\n *\n * The Motion interrupt will indicate the axis and polarity of detected motion\n * in MOT_DETECT_STATUS (Register 97).\n *\n * For more details on the Motion detection interrupt, see Section 8.3 of the\n * MPU-6000/MPU-6050 Product Specification document as well as Registers 56 and\n * 58 of this document.\n *\n * @return Current motion detection acceleration threshold value (LSB = 2mg)\n * @see MPU6050_RA_MOT_THR\n */\nuint8_t MPU6050::getMotionDetectionThreshold()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_MOT_THR, buffer);\n    return buffer[0];\n}\n\n/** Set motion detection event acceleration threshold.\n * @param threshold New motion detection acceleration threshold value (LSB = 2mg)\n * @see getMotionDetectionThreshold()\n * @see MPU6050_RA_MOT_THR\n */\nvoid MPU6050::setMotionDetectionThreshold(uint8_t threshold)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_MOT_THR, threshold);\n}\n\n// MOT_DUR register\n\n/** Get motion detection event duration threshold.\n * This register configures the duration counter threshold for Motion interrupt\n * generation. The duration counter ticks at 1 kHz, therefore MOT_DUR has a unit\n * of 1LSB = 1ms. The Motion detection duration counter increments when the\n * absolute value of any of the accelerometer measurements exceeds the Motion\n * detection threshold (Register 31). The Motion detection interrupt is\n * triggered when the Motion detection counter reaches the time count specified\n * in this register.\n *\n * For more details on the Motion detection interrupt, see Section 8.3 of the\n * MPU-6000/MPU-6050 Product Specification document.\n *\n * @return Current motion detection duration threshold value (LSB = 1ms)\n * @see MPU6050_RA_MOT_DUR\n */\nuint8_t MPU6050::getMotionDetectionDuration()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_MOT_DUR, buffer);\n    return buffer[0];\n}\n\n/** Set motion detection event duration threshold.\n * @param duration New motion detection duration threshold value (LSB = 1ms)\n * @see getMotionDetectionDuration()\n * @see MPU6050_RA_MOT_DUR\n */\nvoid MPU6050::setMotionDetectionDuration(uint8_t duration)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_MOT_DUR, duration);\n}\n\n// ZRMOT_THR register\n\n/** Get zero motion detection event acceleration threshold.\n * This register configures the detection threshold for Zero Motion interrupt\n * generation. The unit of ZRMOT_THR is 1LSB = 2mg. Zero Motion is detected when\n * the absolute value of the accelerometer measurements for the 3 axes are each\n * less than the detection threshold. This condition increments the Zero Motion\n * duration counter (Register 34). The Zero Motion interrupt is triggered when\n * the Zero Motion duration counter reaches the time count specified in\n * ZRMOT_DUR (Register 34).\n *\n * Unlike Free Fall or Motion detection, Zero Motion detection triggers an\n * interrupt both when Zero Motion is first detected and when Zero Motion is no\n * longer detected.\n *\n * When a zero motion event is detected, a Zero Motion Status will be indicated\n * in the MOT_DETECT_STATUS register (Register 97). When a motion-to-zero-motion\n * condition is detected, the status bit is set to 1. When a zero-motion-to-\n * motion condition is detected, the status bit is set to 0.\n *\n * For more details on the Zero Motion detection interrupt, see Section 8.4 of\n * the MPU-6000/MPU-6050 Product Specification document as well as Registers 56\n * and 58 of this document.\n *\n * @return Current zero motion detection acceleration threshold value (LSB = 2mg)\n * @see MPU6050_RA_ZRMOT_THR\n */\nuint8_t MPU6050::getZeroMotionDetectionThreshold()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_ZRMOT_THR, buffer);\n    return buffer[0];\n}\n\n/** Set zero motion detection event acceleration threshold.\n * @param threshold New zero motion detection acceleration threshold value (LSB = 2mg)\n * @see getZeroMotionDetectionThreshold()\n * @see MPU6050_RA_ZRMOT_THR\n */\nvoid MPU6050::setZeroMotionDetectionThreshold(uint8_t threshold)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_ZRMOT_THR, threshold);\n}\n\n// ZRMOT_DUR register\n\n/** Get zero motion detection event duration threshold.\n * This register configures the duration counter threshold for Zero Motion\n * interrupt generation. The duration counter ticks at 16 Hz, therefore\n * ZRMOT_DUR has a unit of 1 LSB = 64 ms. The Zero Motion duration counter\n * increments while the absolute value of the accelerometer measurements are\n * each less than the detection threshold (Register 33). The Zero Motion\n * interrupt is triggered when the Zero Motion duration counter reaches the time\n * count specified in this register.\n *\n * For more details on the Zero Motion detection interrupt, see Section 8.4 of\n * the MPU-6000/MPU-6050 Product Specification document, as well as Registers 56\n * and 58 of this document.\n *\n * @return Current zero motion detection duration threshold value (LSB = 64ms)\n * @see MPU6050_RA_ZRMOT_DUR\n */\nuint8_t MPU6050::getZeroMotionDetectionDuration()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_ZRMOT_DUR, buffer);\n    return buffer[0];\n}\n\n/** Set zero motion detection event duration threshold.\n * @param duration New zero motion detection duration threshold value (LSB = 1ms)\n * @see getZeroMotionDetectionDuration()\n * @see MPU6050_RA_ZRMOT_DUR\n */\nvoid MPU6050::setZeroMotionDetectionDuration(uint8_t duration)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_ZRMOT_DUR, duration);\n}\n\n// FIFO_EN register\n\n/** Get temperature FIFO enabled value.\n * When set to 1, this bit enables TEMP_OUT_H and TEMP_OUT_L (Registers 65 and\n * 66) to be written into the FIFO buffer.\n * @return Current temperature FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getTempFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set temperature FIFO enabled value.\n * @param enabled New temperature FIFO enabled value\n * @see getTempFIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setTempFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_TEMP_FIFO_EN_BIT, enabled);\n}\n\n/** Get gyroscope X-axis FIFO enabled value.\n * When set to 1, this bit enables GYRO_XOUT_H and GYRO_XOUT_L (Registers 67 and\n * 68) to be written into the FIFO buffer.\n * @return Current gyroscope X-axis FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getXGyroFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set gyroscope X-axis FIFO enabled value.\n * @param enabled New gyroscope X-axis FIFO enabled value\n * @see getXGyroFIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setXGyroFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_XG_FIFO_EN_BIT, enabled);\n}\n\n/** Get gyroscope Y-axis FIFO enabled value.\n * When set to 1, this bit enables GYRO_YOUT_H and GYRO_YOUT_L (Registers 69 and\n * 70) to be written into the FIFO buffer.\n * @return Current gyroscope Y-axis FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getYGyroFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set gyroscope Y-axis FIFO enabled value.\n * @param enabled New gyroscope Y-axis FIFO enabled value\n * @see getYGyroFIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setYGyroFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_YG_FIFO_EN_BIT, enabled);\n}\n\n/** Get gyroscope Z-axis FIFO enabled value.\n * When set to 1, this bit enables GYRO_ZOUT_H and GYRO_ZOUT_L (Registers 71 and\n * 72) to be written into the FIFO buffer.\n * @return Current gyroscope Z-axis FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getZGyroFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set gyroscope Z-axis FIFO enabled value.\n * @param enabled New gyroscope Z-axis FIFO enabled value\n * @see getZGyroFIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setZGyroFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ZG_FIFO_EN_BIT, enabled);\n}\n\n/** Get accelerometer FIFO enabled value.\n * When set to 1, this bit enables ACCEL_XOUT_H, ACCEL_XOUT_L, ACCEL_YOUT_H,\n * ACCEL_YOUT_L, ACCEL_ZOUT_H, and ACCEL_ZOUT_L (Registers 59 to 64) to be\n * written into the FIFO buffer.\n * @return Current accelerometer FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getAccelFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set accelerometer FIFO enabled value.\n * @param enabled New accelerometer FIFO enabled value\n * @see getAccelFIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setAccelFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_ACCEL_FIFO_EN_BIT, enabled);\n}\n\n/** Get Slave 2 FIFO enabled value.\n * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)\n * associated with Slave 2 to be written into the FIFO buffer.\n * @return Current Slave 2 FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getSlave2FIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Slave 2 FIFO enabled value.\n * @param enabled New Slave 2 FIFO enabled value\n * @see getSlave2FIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setSlave2FIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV2_FIFO_EN_BIT, enabled);\n}\n\n/** Get Slave 1 FIFO enabled value.\n * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)\n * associated with Slave 1 to be written into the FIFO buffer.\n * @return Current Slave 1 FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getSlave1FIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Slave 1 FIFO enabled value.\n * @param enabled New Slave 1 FIFO enabled value\n * @see getSlave1FIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setSlave1FIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV1_FIFO_EN_BIT, enabled);\n}\n\n/** Get Slave 0 FIFO enabled value.\n * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)\n * associated with Slave 0 to be written into the FIFO buffer.\n * @return Current Slave 0 FIFO enabled value\n * @see MPU6050_RA_FIFO_EN\n */\nbool MPU6050::getSlave0FIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Slave 0 FIFO enabled value.\n * @param enabled New Slave 0 FIFO enabled value\n * @see getSlave0FIFOEnabled()\n * @see MPU6050_RA_FIFO_EN\n */\nvoid MPU6050::setSlave0FIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_FIFO_EN, MPU6050_SLV0_FIFO_EN_BIT, enabled);\n}\n\n// I2C_MST_CTRL register\n\n/** Get multi-master enabled value.\n * Multi-master capability allows multiple I2C masters to operate on the same\n * bus. In circuits where multi-master capability is required, set MULT_MST_EN\n * to 1. This will increase current drawn by approximately 30uA.\n *\n * In circuits where multi-master capability is required, the state of the I2C\n * bus must always be monitored by each separate I2C Master. Before an I2C\n * Master can assume arbitration of the bus, it must first confirm that no other\n * I2C Master has arbitration of the bus. When MULT_MST_EN is set to 1, the\n * MPU-60X0's bus arbitration detection logic is turned on, enabling it to\n * detect when the bus is available.\n *\n * @return Current multi-master enabled value\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nbool MPU6050::getMultiMasterEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set multi-master enabled value.\n * @param enabled New multi-master enabled value\n * @see getMultiMasterEnabled()\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nvoid MPU6050::setMultiMasterEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_MULT_MST_EN_BIT, enabled);\n}\n\n/** Get wait-for-external-sensor-data enabled value.\n * When the WAIT_FOR_ES bit is set to 1, the Data Ready interrupt will be\n * delayed until External Sensor data from the Slave Devices are loaded into the\n * EXT_SENS_DATA registers. This is used to ensure that both the internal sensor\n * data (i.e. from gyro and accel) and external sensor data have been loaded to\n * their respective data registers (i.e. the data is synced) when the Data Ready\n * interrupt is triggered.\n *\n * @return Current wait-for-external-sensor-data enabled value\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nbool MPU6050::getWaitForExternalSensorEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set wait-for-external-sensor-data enabled value.\n * @param enabled New wait-for-external-sensor-data enabled value\n * @see getWaitForExternalSensorEnabled()\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nvoid MPU6050::setWaitForExternalSensorEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_WAIT_FOR_ES_BIT, enabled);\n}\n\n/** Get Slave 3 FIFO enabled value.\n * When set to 1, this bit enables EXT_SENS_DATA registers (Registers 73 to 96)\n * associated with Slave 3 to be written into the FIFO buffer.\n * @return Current Slave 3 FIFO enabled value\n * @see MPU6050_RA_MST_CTRL\n */\nbool MPU6050::getSlave3FIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Slave 3 FIFO enabled value.\n * @param enabled New Slave 3 FIFO enabled value\n * @see getSlave3FIFOEnabled()\n * @see MPU6050_RA_MST_CTRL\n */\nvoid MPU6050::setSlave3FIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_SLV_3_FIFO_EN_BIT, enabled);\n}\n\n/** Get slave read/write transition enabled value.\n * The I2C_MST_P_NSR bit configures the I2C Master's transition from one slave\n * read to the next slave read. If the bit equals 0, there will be a restart\n * between reads. If the bit equals 1, there will be a stop followed by a start\n * of the following read. When a write transaction follows a read transaction,\n * the stop followed by a start of the successive write will be always used.\n *\n * @return Current slave read/write transition enabled value\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nbool MPU6050::getSlaveReadWriteTransitionEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set slave read/write transition enabled value.\n * @param enabled New slave read/write transition enabled value\n * @see getSlaveReadWriteTransitionEnabled()\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nvoid MPU6050::setSlaveReadWriteTransitionEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_P_NSR_BIT, enabled);\n}\n\n/** Get I2C master clock speed.\n * I2C_MST_CLK is a 4 bit unsigned value which configures a divider on the\n * MPU-60X0 internal 8MHz clock. It sets the I2C master clock speed according to\n * the following table:\n *\n * <pre>\n * I2C_MST_CLK | I2C Master Clock Speed | 8MHz Clock Divider\n * ------------+------------------------+-------------------\n * 0           | 348kHz                 | 23\n * 1           | 333kHz                 | 24\n * 2           | 320kHz                 | 25\n * 3           | 308kHz                 | 26\n * 4           | 296kHz                 | 27\n * 5           | 286kHz                 | 28\n * 6           | 276kHz                 | 29\n * 7           | 267kHz                 | 30\n * 8           | 258kHz                 | 31\n * 9           | 500kHz                 | 16\n * 10          | 471kHz                 | 17\n * 11          | 444kHz                 | 18\n * 12          | 421kHz                 | 19\n * 13          | 400kHz                 | 20\n * 14          | 381kHz                 | 21\n * 15          | 364kHz                 | 22\n * </pre>\n *\n * @return Current I2C master clock speed\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nuint8_t MPU6050::getMasterClockSpeed()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set I2C master clock speed.\n * @reparam speed Current I2C master clock speed\n * @see MPU6050_RA_I2C_MST_CTRL\n */\nvoid MPU6050::setMasterClockSpeed(uint8_t speed)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_I2C_MST_CTRL, MPU6050_I2C_MST_CLK_BIT, MPU6050_I2C_MST_CLK_LENGTH, speed);\n}\n\n// I2C_SLV* registers (Slave 0-3)\n\n/** Get the I2C address of the specified slave (0-3).\n * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read\n * operation, and if it is cleared, then it's a write operation. The remaining\n * bits (6-0) are the 7-bit device address of the slave device.\n *\n * In read mode, the result of the read is placed in the lowest available\n * EXT_SENS_DATA register. For further information regarding the allocation of\n * read results, please refer to the EXT_SENS_DATA register description\n * (Registers 73 - 96).\n *\n * The MPU-6050 supports a total of five slaves, but Slave 4 has unique\n * characteristics, and so it has its own functions (getSlave4* and setSlave4*).\n *\n * I2C data transactions are performed at the Sample Rate, as defined in\n * Register 25. The user is responsible for ensuring that I2C data transactions\n * to and from each enabled Slave can be completed within a single period of the\n * Sample Rate.\n *\n * The I2C slave access rate can be reduced relative to the Sample Rate. This\n * reduced access rate is determined by I2C_MST_DLY (Register 52). Whether a\n * slave's access rate is reduced relative to the Sample Rate is determined by\n * I2C_MST_DELAY_CTRL (Register 103).\n *\n * The processing order for the slaves is fixed. The sequence followed for\n * processing the slaves is Slave 0, Slave 1, Slave 2, Slave 3 and Slave 4. If a\n * particular Slave is disabled it will be skipped.\n *\n * Each slave can either be accessed at the sample rate or at a reduced sample\n * rate. In a case where some slaves are accessed at the Sample Rate and some\n * slaves are accessed at the reduced rate, the sequence of accessing the slaves\n * (Slave 0 to Slave 4) is still followed. However, the reduced rate slaves will\n * be skipped if their access rate dictates that they should not be accessed\n * during that particular cycle. For further information regarding the reduced\n * access rate, please refer to Register 52. Whether a slave is accessed at the\n * Sample Rate or at the reduced rate is determined by the Delay Enable bits in\n * Register 103.\n *\n * @param num Slave number (0-3)\n * @return Current address for specified slave\n * @see MPU6050_RA_I2C_SLV0_ADDR\n */\nuint8_t MPU6050::getSlaveAddress(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num * 3, buffer);\n    return buffer[0];\n}\n\n/** Set the I2C address of the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param address New address for specified slave\n * @see getSlaveAddress()\n * @see MPU6050_RA_I2C_SLV0_ADDR\n */\nvoid MPU6050::setSlaveAddress(uint8_t num, uint8_t address)\n{\n    if (num > 3) return;\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV0_ADDR + num * 3, address);\n}\n\n/** Get the active internal register for the specified slave (0-3).\n * Read/write operations for this slave will be done to whatever internal\n * register address is stored in this MPU register.\n *\n * The MPU-6050 supports a total of five slaves, but Slave 4 has unique\n * characteristics, and so it has its own functions.\n *\n * @param num Slave number (0-3)\n * @return Current active register for specified slave\n * @see MPU6050_RA_I2C_SLV0_REG\n */\nuint8_t MPU6050::getSlaveRegister(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num * 3, buffer);\n    return buffer[0];\n}\n\n/** Set the active internal register for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param reg New active register for specified slave\n * @see getSlaveRegister()\n * @see MPU6050_RA_I2C_SLV0_REG\n */\nvoid MPU6050::setSlaveRegister(uint8_t num, uint8_t reg)\n{\n    if (num > 3) return;\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV0_REG + num * 3, reg);\n}\n\n/** Get the enabled value for the specified slave (0-3).\n * When set to 1, this bit enables Slave 0 for data transfer operations. When\n * cleared to 0, this bit disables Slave 0 from data transfer operations.\n * @param num Slave number (0-3)\n * @return Current enabled value for specified slave\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nbool MPU6050::getSlaveEnabled(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set the enabled value for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param enabled New enabled value for specified slave\n * @see getSlaveEnabled()\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nvoid MPU6050::setSlaveEnabled(uint8_t num, bool enabled)\n{\n    if (num > 3) return;\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_EN_BIT, enabled);\n}\n\n/** Get word pair byte-swapping enabled for the specified slave (0-3).\n * When set to 1, this bit enables byte swapping. When byte swapping is enabled,\n * the high and low bytes of a word pair are swapped. Please refer to\n * I2C_SLV0_GRP for the pairing convention of the word pairs. When cleared to 0,\n * bytes transferred to and from Slave 0 will be written to EXT_SENS_DATA\n * registers in the order they were transferred.\n *\n * @param num Slave number (0-3)\n * @return Current word pair byte-swapping enabled value for specified slave\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nbool MPU6050::getSlaveWordByteSwap(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_BYTE_SW_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set word pair byte-swapping enabled for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param enabled New word pair byte-swapping enabled value for specified slave\n * @see getSlaveWordByteSwap()\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nvoid MPU6050::setSlaveWordByteSwap(uint8_t num, bool enabled)\n{\n    if (num > 3) return;\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_BYTE_SW_BIT, enabled);\n}\n\n/** Get write mode for the specified slave (0-3).\n * When set to 1, the transaction will read or write data only. When cleared to\n * 0, the transaction will write a register address prior to reading or writing\n * data. This should equal 0 when specifying the register address within the\n * Slave device to/from which the ensuing data transaction will take place.\n *\n * @param num Slave number (0-3)\n * @return Current write mode for specified slave (0 = register address + data, 1 = data only)\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nbool MPU6050::getSlaveWriteMode(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_REG_DIS_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set write mode for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param mode New write mode for specified slave (0 = register address + data, 1 = data only)\n * @see getSlaveWriteMode()\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nvoid MPU6050::setSlaveWriteMode(uint8_t num, bool mode)\n{\n    if (num > 3) return;\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_REG_DIS_BIT, mode);\n}\n\n/** Get word pair grouping order offset for the specified slave (0-3).\n * This sets specifies the grouping order of word pairs received from registers.\n * When cleared to 0, bytes from register addresses 0 and 1, 2 and 3, etc (even,\n * then odd register addresses) are paired to form a word. When set to 1, bytes\n * from register addresses are paired 1 and 2, 3 and 4, etc. (odd, then even\n * register addresses) are paired to form a word.\n *\n * @param num Slave number (0-3)\n * @return Current word pair grouping order offset for specified slave\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nbool MPU6050::getSlaveWordGroupOffset(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_GRP_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set word pair grouping order offset for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param enabled New word pair grouping order offset for specified slave\n * @see getSlaveWordGroupOffset()\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nvoid MPU6050::setSlaveWordGroupOffset(uint8_t num, bool enabled)\n{\n    if (num > 3) return;\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_GRP_BIT, enabled);\n}\n\n/** Get number of bytes to read for the specified slave (0-3).\n * Specifies the number of bytes transferred to and from Slave 0. Clearing this\n * bit to 0 is equivalent to disabling the register by writing 0 to I2C_SLV0_EN.\n * @param num Slave number (0-3)\n * @return Number of bytes to read for specified slave\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nuint8_t MPU6050::getSlaveDataLength(uint8_t num)\n{\n    if (num > 3) return 0;\n    I2Cdev_readBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set number of bytes to read for the specified slave (0-3).\n * @param num Slave number (0-3)\n * @param length Number of bytes to read for specified slave\n * @see getSlaveDataLength()\n * @see MPU6050_RA_I2C_SLV0_CTRL\n */\nvoid MPU6050::setSlaveDataLength(uint8_t num, uint8_t length)\n{\n    if (num > 3) return;\n    I2Cdev_writeBits(devAddr, MPU6050_RA_I2C_SLV0_CTRL + num * 3, MPU6050_I2C_SLV_LEN_BIT, MPU6050_I2C_SLV_LEN_LENGTH,\n                     length);\n}\n\n// I2C_SLV* registers (Slave 4)\n\n/** Get the I2C address of Slave 4.\n * Note that Bit 7 (MSB) controls read/write mode. If Bit 7 is set, it's a read\n * operation, and if it is cleared, then it's a write operation. The remaining\n * bits (6-0) are the 7-bit device address of the slave device.\n *\n * @return Current address for Slave 4\n * @see getSlaveAddress()\n * @see MPU6050_RA_I2C_SLV4_ADDR\n */\nuint8_t MPU6050::getSlave4Address()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, buffer);\n    return buffer[0];\n}\n\n/** Set the I2C address of Slave 4.\n * @param address New address for Slave 4\n * @see getSlave4Address()\n * @see MPU6050_RA_I2C_SLV4_ADDR\n */\nvoid MPU6050::setSlave4Address(uint8_t address)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV4_ADDR, address);\n}\n\n/** Get the active internal register for the Slave 4.\n * Read/write operations for this slave will be done to whatever internal\n * register address is stored in this MPU register.\n *\n * @return Current active register for Slave 4\n * @see MPU6050_RA_I2C_SLV4_REG\n */\nuint8_t MPU6050::getSlave4Register()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_I2C_SLV4_REG, buffer);\n    return buffer[0];\n}\n\n/** Set the active internal register for Slave 4.\n * @param reg New active register for Slave 4\n * @see getSlave4Register()\n * @see MPU6050_RA_I2C_SLV4_REG\n */\nvoid MPU6050::setSlave4Register(uint8_t reg)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV4_REG, reg);\n}\n\n/** Set new byte to write to Slave 4.\n * This register stores the data to be written into the Slave 4. If I2C_SLV4_RW\n * is set 1 (set to read), this register has no effect.\n * @param data New byte to write to Slave 4\n * @see MPU6050_RA_I2C_SLV4_DO\n */\nvoid MPU6050::setSlave4OutputByte(uint8_t data)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV4_DO, data);\n}\n\n/** Get the enabled value for the Slave 4.\n * When set to 1, this bit enables Slave 4 for data transfer operations. When\n * cleared to 0, this bit disables Slave 4 from data transfer operations.\n * @return Current enabled value for Slave 4\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nbool MPU6050::getSlave4Enabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set the enabled value for Slave 4.\n * @param enabled New enabled value for Slave 4\n * @see getSlave4Enabled()\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nvoid MPU6050::setSlave4Enabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_EN_BIT, enabled);\n}\n\n/** Get the enabled value for Slave 4 transaction interrupts.\n * When set to 1, this bit enables the generation of an interrupt signal upon\n * completion of a Slave 4 transaction. When cleared to 0, this bit disables the\n * generation of an interrupt signal upon completion of a Slave 4 transaction.\n * The interrupt status can be observed in Register 54.\n *\n * @return Current enabled value for Slave 4 transaction interrupts.\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nbool MPU6050::getSlave4InterruptEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set the enabled value for Slave 4 transaction interrupts.\n * @param enabled New enabled value for Slave 4 transaction interrupts.\n * @see getSlave4InterruptEnabled()\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nvoid MPU6050::setSlave4InterruptEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_INT_EN_BIT, enabled);\n}\n\n/** Get write mode for Slave 4.\n * When set to 1, the transaction will read or write data only. When cleared to\n * 0, the transaction will write a register address prior to reading or writing\n * data. This should equal 0 when specifying the register address within the\n * Slave device to/from which the ensuing data transaction will take place.\n *\n * @return Current write mode for Slave 4 (0 = register address + data, 1 = data only)\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nbool MPU6050::getSlave4WriteMode()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set write mode for the Slave 4.\n * @param mode New write mode for Slave 4 (0 = register address + data, 1 = data only)\n * @see getSlave4WriteMode()\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nvoid MPU6050::setSlave4WriteMode(bool mode)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_REG_DIS_BIT, mode);\n}\n\n/** Get Slave 4 master delay value.\n * This configures the reduced access rate of I2C slaves relative to the Sample\n * Rate. When a slave's access rate is decreased relative to the Sample Rate,\n * the slave is accessed every:\n *\n *     1 / (1 + I2C_MST_DLY) samples\n *\n * This base Sample Rate in turn is determined by SMPLRT_DIV (register 25) and\n * DLPF_CFG (register 26). Whether a slave's access rate is reduced relative to\n * the Sample Rate is determined by I2C_MST_DELAY_CTRL (register 103). For\n * further information regarding the Sample Rate, please refer to register 25.\n *\n * @return Current Slave 4 master delay value\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nuint8_t MPU6050::getSlave4MasterDelay()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set Slave 4 master delay value.\n * @param delay New Slave 4 master delay value\n * @see getSlave4MasterDelay()\n * @see MPU6050_RA_I2C_SLV4_CTRL\n */\nvoid MPU6050::setSlave4MasterDelay(uint8_t delay)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_I2C_SLV4_CTRL, MPU6050_I2C_SLV4_MST_DLY_BIT, MPU6050_I2C_SLV4_MST_DLY_LENGTH,\n                     delay);\n}\n\n/** Get last available byte read from Slave 4.\n * This register stores the data read from Slave 4. This field is populated\n * after a read transaction.\n * @return Last available byte read from to Slave 4\n * @see MPU6050_RA_I2C_SLV4_DI\n */\nuint8_t MPU6050::getSlate4InputByte()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_I2C_SLV4_DI, buffer);\n    return buffer[0];\n}\n\n// I2C_MST_STATUS register\n\n/** Get FSYNC interrupt status.\n * This bit reflects the status of the FSYNC interrupt from an external device\n * into the MPU-60X0. This is used as a way to pass an external interrupt\n * through the MPU-60X0 to the host application processor. When set to 1, this\n * bit will cause an interrupt if FSYNC_INT_EN is asserted in INT_PIN_CFG\n * (Register 55).\n * @return FSYNC interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getPassthroughStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_PASS_THROUGH_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 4 transaction done status.\n * Automatically sets to 1 when a Slave 4 transaction has completed. This\n * triggers an interrupt if the I2C_MST_INT_EN bit in the INT_ENABLE register\n * (Register 56) is asserted and if the SLV_4_DONE_INT bit is asserted in the\n * I2C_SLV4_CTRL register (Register 52).\n * @return Slave 4 transaction done status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave4IsDone()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_DONE_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get master arbitration lost status.\n * This bit automatically sets to 1 when the I2C Master has lost arbitration of\n * the auxiliary I2C bus (an error condition). This triggers an interrupt if the\n * I2C_MST_INT_EN bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Master arbitration lost status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getLostArbitration()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_LOST_ARB_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 4 NACK status.\n * This bit automatically sets to 1 when the I2C Master receives a NACK in a\n * transaction with Slave 4. This triggers an interrupt if the I2C_MST_INT_EN\n * bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Slave 4 NACK interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave4Nack()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV4_NACK_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 3 NACK status.\n * This bit automatically sets to 1 when the I2C Master receives a NACK in a\n * transaction with Slave 3. This triggers an interrupt if the I2C_MST_INT_EN\n * bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Slave 3 NACK interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave3Nack()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV3_NACK_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 2 NACK status.\n * This bit automatically sets to 1 when the I2C Master receives a NACK in a\n * transaction with Slave 2. This triggers an interrupt if the I2C_MST_INT_EN\n * bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Slave 2 NACK interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave2Nack()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV2_NACK_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 1 NACK status.\n * This bit automatically sets to 1 when the I2C Master receives a NACK in a\n * transaction with Slave 1. This triggers an interrupt if the I2C_MST_INT_EN\n * bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Slave 1 NACK interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave1Nack()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV1_NACK_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Slave 0 NACK status.\n * This bit automatically sets to 1 when the I2C Master receives a NACK in a\n * transaction with Slave 0. This triggers an interrupt if the I2C_MST_INT_EN\n * bit in the INT_ENABLE register (Register 56) is asserted.\n * @return Slave 0 NACK interrupt status\n * @see MPU6050_RA_I2C_MST_STATUS\n */\nbool MPU6050::getSlave0Nack()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_STATUS, MPU6050_MST_I2C_SLV0_NACK_BIT, buffer);\n    return buffer[0];\n}\n\n// INT_PIN_CFG register\n\n/** Get interrupt logic level mode.\n * Will be set 0 for active-high, 1 for active-low.\n * @return Current interrupt mode (0=active-high, 1=active-low)\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_LEVEL_BIT\n */\nbool MPU6050::getInterruptMode()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set interrupt logic level mode.\n * @param mode New interrupt mode (0=active-high, 1=active-low)\n * @see getInterruptMode()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_LEVEL_BIT\n */\nvoid MPU6050::setInterruptMode(bool mode)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_LEVEL_BIT, mode);\n}\n\n/** Get interrupt drive mode.\n * Will be set 0 for push-pull, 1 for open-drain.\n * @return Current interrupt drive mode (0=push-pull, 1=open-drain)\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_OPEN_BIT\n */\nbool MPU6050::getInterruptDrive()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set interrupt drive mode.\n * @param drive New interrupt drive mode (0=push-pull, 1=open-drain)\n * @see getInterruptDrive()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_OPEN_BIT\n */\nvoid MPU6050::setInterruptDrive(bool drive)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_OPEN_BIT, drive);\n}\n\n/** Get interrupt latch mode.\n * Will be set 0 for 50us-pulse, 1 for latch-until-int-cleared.\n * @return Current latch mode (0=50us-pulse, 1=latch-until-int-cleared)\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_LATCH_INT_EN_BIT\n */\nbool MPU6050::getInterruptLatch()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set interrupt latch mode.\n * @param latch New latch mode (0=50us-pulse, 1=latch-until-int-cleared)\n * @see getInterruptLatch()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_LATCH_INT_EN_BIT\n */\nvoid MPU6050::setInterruptLatch(bool latch)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_LATCH_INT_EN_BIT, latch);\n}\n\n/** Get interrupt latch clear mode.\n * Will be set 0 for status-read-only, 1 for any-register-read.\n * @return Current latch clear mode (0=status-read-only, 1=any-register-read)\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT\n */\nbool MPU6050::getInterruptLatchClear()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set interrupt latch clear mode.\n * @param clear New latch clear mode (0=status-read-only, 1=any-register-read)\n * @see getInterruptLatchClear()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_INT_RD_CLEAR_BIT\n */\nvoid MPU6050::setInterruptLatchClear(bool clear)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_INT_RD_CLEAR_BIT, clear);\n}\n\n/** Get FSYNC interrupt logic level mode.\n * @return Current FSYNC interrupt mode (0=active-high, 1=active-low)\n * @see getFSyncInterruptMode()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT\n */\nbool MPU6050::getFSyncInterruptLevel()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set FSYNC interrupt logic level mode.\n * @param mode New FSYNC interrupt mode (0=active-high, 1=active-low)\n * @see getFSyncInterruptMode()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT\n */\nvoid MPU6050::setFSyncInterruptLevel(bool level)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT, level);\n}\n\n/** Get FSYNC pin interrupt enabled setting.\n * Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled setting\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT\n */\nbool MPU6050::getFSyncInterruptEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set FSYNC pin interrupt enabled setting.\n * @param enabled New FSYNC pin interrupt enabled setting\n * @see getFSyncInterruptEnabled()\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_FSYNC_INT_EN_BIT\n */\nvoid MPU6050::setFSyncInterruptEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_FSYNC_INT_EN_BIT, enabled);\n}\n\n/** Get I2C bypass enabled status.\n * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to\n * 0, the host application processor will be able to directly access the\n * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host\n * application processor will not be able to directly access the auxiliary I2C\n * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106\n * bit[5]).\n * @return Current I2C bypass enabled status\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT\n */\nbool MPU6050::getI2CBypassEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set I2C bypass enabled status.\n * When this bit is equal to 1 and I2C_MST_EN (Register 106 bit[5]) is equal to\n * 0, the host application processor will be able to directly access the\n * auxiliary I2C bus of the MPU-60X0. When this bit is equal to 0, the host\n * application processor will not be able to directly access the auxiliary I2C\n * bus of the MPU-60X0 regardless of the state of I2C_MST_EN (Register 106\n * bit[5]).\n * @param enabled New I2C bypass enabled status\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_I2C_BYPASS_EN_BIT\n */\nvoid MPU6050::setI2CBypassEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_I2C_BYPASS_EN_BIT, enabled);\n}\n\n/** Get reference clock output enabled status.\n * When this bit is equal to 1, a reference clock output is provided at the\n * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For\n * further information regarding CLKOUT, please refer to the MPU-60X0 Product\n * Specification document.\n * @return Current reference clock output enabled status\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_CLKOUT_EN_BIT\n */\nbool MPU6050::getClockOutputEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set reference clock output enabled status.\n * When this bit is equal to 1, a reference clock output is provided at the\n * CLKOUT pin. When this bit is equal to 0, the clock output is disabled. For\n * further information regarding CLKOUT, please refer to the MPU-60X0 Product\n * Specification document.\n * @param enabled New reference clock output enabled status\n * @see MPU6050_RA_INT_PIN_CFG\n * @see MPU6050_INTCFG_CLKOUT_EN_BIT\n */\nvoid MPU6050::setClockOutputEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_PIN_CFG, MPU6050_INTCFG_CLKOUT_EN_BIT, enabled);\n}\n\n// INT_ENABLE register\n\n/** Get full interrupt enabled status.\n * Full register byte for all interrupts, for quick reading. Each bit will be\n * set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FF_BIT\n **/\nuint8_t MPU6050::getIntEnabled()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_INT_ENABLE, buffer);\n    return buffer[0];\n}\n\n/** Set full interrupt enabled status.\n * Full register byte for all interrupts, for quick reading. Each bit should be\n * set 0 for disabled, 1 for enabled.\n * @param enabled New interrupt enabled status\n * @see getIntFreefallEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FF_BIT\n **/\nvoid MPU6050::setIntEnabled(uint8_t enabled)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_INT_ENABLE, enabled);\n}\n\n/** Get Free Fall interrupt enabled status.\n * Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FF_BIT\n **/\nbool MPU6050::getIntFreefallEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Free Fall interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntFreefallEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FF_BIT\n **/\nvoid MPU6050::setIntFreefallEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FF_BIT, enabled);\n}\n\n/** Get Motion Detection interrupt enabled status.\n * Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_MOT_BIT\n **/\nbool MPU6050::getIntMotionEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Motion Detection interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntMotionEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_MOT_BIT\n **/\nvoid MPU6050::setIntMotionEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_MOT_BIT, enabled);\n}\n\n/** Get Zero Motion Detection interrupt enabled status.\n * Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_ZMOT_BIT\n **/\nbool MPU6050::getIntZeroMotionEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Zero Motion Detection interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntZeroMotionEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_ZMOT_BIT\n **/\nvoid MPU6050::setIntZeroMotionEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_ZMOT_BIT, enabled);\n}\n\n/** Get FIFO Buffer Overflow interrupt enabled status.\n * Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT\n **/\nbool MPU6050::getIntFIFOBufferOverflowEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set FIFO Buffer Overflow interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntFIFOBufferOverflowEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT\n **/\nvoid MPU6050::setIntFIFOBufferOverflowEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, enabled);\n}\n\n/** Get I2C Master interrupt enabled status.\n * This enables any of the I2C Master interrupt sources to generate an\n * interrupt. Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT\n **/\nbool MPU6050::getIntI2CMasterEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set I2C Master interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntI2CMasterEnabled()\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT\n **/\nvoid MPU6050::setIntI2CMasterEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_I2C_MST_INT_BIT, enabled);\n}\n\n/** Get Data Ready interrupt enabled setting.\n * This event occurs each time a write operation to all of the sensor registers\n * has been completed. Will be set 0 for disabled, 1 for enabled.\n * @return Current interrupt enabled status\n * @see MPU6050_RA_INT_ENABLE\n * @see MPU6050_INTERRUPT_DATA_RDY_BIT\n */\nbool MPU6050::getIntDataReadyEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Data Ready interrupt enabled status.\n * @param enabled New interrupt enabled status\n * @see getIntDataReadyEnabled()\n * @see MPU6050_RA_INT_CFG\n * @see MPU6050_INTERRUPT_DATA_RDY_BIT\n */\nvoid MPU6050::setIntDataReadyEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DATA_RDY_BIT, enabled);\n}\n\n// INT_STATUS register\n\n/** Get full set of interrupt status bits.\n * These bits clear to 0 after the register has been read. Very useful\n * for getting multiple INT statuses, since each single bit read clears\n * all of them because it has to read the whole byte.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n */\nuint8_t MPU6050::getIntStatus()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_INT_STATUS, buffer);\n    return buffer[0];\n}\n\n/** Get Free Fall interrupt status.\n * This bit automatically sets to 1 when a Free Fall interrupt has been\n * generated. The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_FF_BIT\n */\nbool MPU6050::getIntFreefallStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FF_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Motion Detection interrupt status.\n * This bit automatically sets to 1 when a Motion Detection interrupt has been\n * generated. The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_MOT_BIT\n */\nbool MPU6050::getIntMotionStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_MOT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Zero Motion Detection interrupt status.\n * This bit automatically sets to 1 when a Zero Motion Detection interrupt has\n * been generated. The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_ZMOT_BIT\n */\nbool MPU6050::getIntZeroMotionStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_ZMOT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get FIFO Buffer Overflow interrupt status.\n * This bit automatically sets to 1 when a Free Fall interrupt has been\n * generated. The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_FIFO_OFLOW_BIT\n */\nbool MPU6050::getIntFIFOBufferOverflowStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_FIFO_OFLOW_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get I2C Master interrupt status.\n * This bit automatically sets to 1 when an I2C Master interrupt has been\n * generated. For a list of I2C Master interrupts, please refer to Register 54.\n * The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_I2C_MST_INT_BIT\n */\nbool MPU6050::getIntI2CMasterStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_I2C_MST_INT_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Data Ready interrupt status.\n * This bit automatically sets to 1 when a Data Ready interrupt has been\n * generated. The bit clears to 0 after the register has been read.\n * @return Current interrupt status\n * @see MPU6050_RA_INT_STATUS\n * @see MPU6050_INTERRUPT_DATA_RDY_BIT\n */\nbool MPU6050::getIntDataReadyStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DATA_RDY_BIT, buffer);\n    return buffer[0];\n}\n\n// ACCEL_*OUT_* registers\n\n/** Get raw 9-axis motion sensor readings (accel/gyro/compass).\n * FUNCTION NOT FULLY IMPLEMENTED YET.\n * @param ax 16-bit signed integer container for accelerometer X-axis value\n * @param ay 16-bit signed integer container for accelerometer Y-axis value\n * @param az 16-bit signed integer container for accelerometer Z-axis value\n * @param gx 16-bit signed integer container for gyroscope X-axis value\n * @param gy 16-bit signed integer container for gyroscope Y-axis value\n * @param gz 16-bit signed integer container for gyroscope Z-axis value\n * @param mx 16-bit signed integer container for magnetometer X-axis value\n * @param my 16-bit signed integer container for magnetometer Y-axis value\n * @param mz 16-bit signed integer container for magnetometer Z-axis value\n * @see Update()\n * @see getAcceleration()\n * @see getRotation()\n * @see MPU6050_RA_ACCEL_XOUT_H\n */\nvoid MPU6050::getMotion9(int16_t *ax, int16_t *ay, int16_t *az, int16_t *gx, int16_t *gy, int16_t *gz, int16_t *mx,\n                         int16_t *my, int16_t *mz)\n{\n    getMotion6(ax, ay, az, gx, gy, gz);\n    // TODO: magnetometer integration\n}\n\n/** Get raw 6-axis motion sensor readings (accel/gyro).\n * Retrieves all currently available motion sensor values.\n * @param ax 16-bit signed integer container for accelerometer X-axis value\n * @param ay 16-bit signed integer container for accelerometer Y-axis value\n * @param az 16-bit signed integer container for accelerometer Z-axis value\n * @param gx 16-bit signed integer container for gyroscope X-axis value\n * @param gy 16-bit signed integer container for gyroscope Y-axis value\n * @param gz 16-bit signed integer container for gyroscope Z-axis value\n * @see getAcceleration()\n * @see getRotation()\n * @see MPU6050_RA_ACCEL_XOUT_H\n */\nvoid MPU6050::getMotion6(int16_t *ax, int16_t *ay, int16_t *az, int16_t *gx, int16_t *gy, int16_t *gz)\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 14, buffer);\n    *ax = (((int16_t) buffer[0]) << 8) | buffer[1];\n    *ay = (((int16_t) buffer[2]) << 8) | buffer[3];\n    *az = (((int16_t) buffer[4]) << 8) | buffer[5];\n    *gx = (((int16_t) buffer[8]) << 8) | buffer[9];\n    *gy = (((int16_t) buffer[10]) << 8) | buffer[11];\n    *gz = (((int16_t) buffer[12]) << 8) | buffer[13];\n}\n\n/** Get 3-axis accelerometer readings.\n * These registers store the most recent accelerometer measurements.\n * Accelerometer measurements are written to these registers at the Sample Rate\n * as defined in Register 25.\n *\n * The accelerometer measurement registers, along with the temperature\n * measurement registers, gyroscope measurement registers, and external sensor\n * data registers, are composed of two sets of registers: an internal register\n * set and a user-facing read register set.\n *\n * The data within the accelerometer sensors' internal register set is always\n * updated at the Sample Rate. Meanwhile, the user-facing read register set\n * duplicates the internal register set's data values whenever the serial\n * interface is idle. This guarantees that a burst read of sensor registers will\n * read measurements from the same sampling instant. Note that if burst reads\n * are not used, the user is responsible for ensuring a set of single byte reads\n * correspond to a single sampling instant by checking the Data Ready interrupt.\n *\n * Each 16-bit accelerometer measurement has a full scale defined in ACCEL_FS\n * (Register 28). For each full scale setting, the accelerometers' sensitivity\n * per LSB in ACCEL_xOUT is shown in the table below:\n *\n * <pre>\n * AFS_SEL | Full Scale Range | LSB Sensitivity\n * --------+------------------+----------------\n * 0       | +/- 2g           | 8192 LSB/mg\n * 1       | +/- 4g           | 4096 LSB/mg\n * 2       | +/- 8g           | 2048 LSB/mg\n * 3       | +/- 16g          | 1024 LSB/mg\n * </pre>\n *\n * @param x 16-bit signed integer container for X-axis acceleration\n * @param y 16-bit signed integer container for Y-axis acceleration\n * @param z 16-bit signed integer container for Z-axis acceleration\n * @see MPU6050_RA_GYRO_XOUT_H\n */\nvoid MPU6050::getAcceleration(int16_t *x, int16_t *y, int16_t *z)\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 6, buffer);\n    *x = (((int16_t) buffer[0]) << 8) | buffer[1];\n    *y = (((int16_t) buffer[2]) << 8) | buffer[3];\n    *z = (((int16_t) buffer[4]) << 8) | buffer[5];\n}\n\n/** Get X-axis accelerometer reading.\n * @return X-axis acceleration measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_ACCEL_XOUT_H\n */\nint16_t MPU6050::getAccelerationX()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ACCEL_XOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n/** Get Y-axis accelerometer reading.\n * @return Y-axis acceleration measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_ACCEL_YOUT_H\n */\nint16_t MPU6050::getAccelerationY()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ACCEL_YOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n/** Get Z-axis accelerometer reading.\n * @return Z-axis acceleration measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_ACCEL_ZOUT_H\n */\nint16_t MPU6050::getAccelerationZ()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ACCEL_ZOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n// TEMP_OUT_* registers\n\n/** Get current internal temperature.\n * @return Temperature reading in 16-bit 2's complement format\n * @see MPU6050_RA_TEMP_OUT_H\n */\nint16_t MPU6050::getTemperature()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_TEMP_OUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n// GYRO_*OUT_* registers\n\n/** Get 3-axis gyroscope readings.\n * These gyroscope measurement registers, along with the accelerometer\n * measurement registers, temperature measurement registers, and external sensor\n * data registers, are composed of two sets of registers: an internal register\n * set and a user-facing read register set.\n * The data within the gyroscope sensors' internal register set is always\n * updated at the Sample Rate. Meanwhile, the user-facing read register set\n * duplicates the internal register set's data values whenever the serial\n * interface is idle. This guarantees that a burst read of sensor registers will\n * read measurements from the same sampling instant. Note that if burst reads\n * are not used, the user is responsible for ensuring a set of single byte reads\n * correspond to a single sampling instant by checking the Data Ready interrupt.\n *\n * Each 16-bit gyroscope measurement has a full scale defined in FS_SEL\n * (Register 27). For each full scale setting, the gyroscopes' sensitivity per\n * LSB in GYRO_xOUT is shown in the table below:\n *\n * <pre>\n * FS_SEL | Full Scale Range   | LSB Sensitivity\n * -------+--------------------+----------------\n * 0      | +/- 250 degrees/s  | 131 LSB/deg/s\n * 1      | +/- 500 degrees/s  | 65.5 LSB/deg/s\n * 2      | +/- 1000 degrees/s | 32.8 LSB/deg/s\n * 3      | +/- 2000 degrees/s | 16.4 LSB/deg/s\n * </pre>\n *\n * @param x 16-bit signed integer container for X-axis rotation\n * @param y 16-bit signed integer container for Y-axis rotation\n * @param z 16-bit signed integer container for Z-axis rotation\n * @see Update()\n * @see MPU6050_RA_GYRO_XOUT_H\n */\nvoid MPU6050::getRotation(int16_t *x, int16_t *y, int16_t *z)\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 6, buffer);\n    *x = (((int16_t) buffer[0]) << 8) | buffer[1];\n    *y = (((int16_t) buffer[2]) << 8) | buffer[3];\n    *z = (((int16_t) buffer[4]) << 8) | buffer[5];\n}\n\n/** Get X-axis gyroscope reading.\n * @return X-axis rotation measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_GYRO_XOUT_H\n */\nint16_t MPU6050::getRotationX()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_GYRO_XOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n/** Get Y-axis gyroscope reading.\n * @return Y-axis rotation measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_GYRO_YOUT_H\n */\nint16_t MPU6050::getRotationY()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_GYRO_YOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n/** Get Z-axis gyroscope reading.\n * @return Z-axis rotation measurement in 16-bit 2's complement format\n * @see Update()\n * @see MPU6050_RA_GYRO_ZOUT_H\n */\nint16_t MPU6050::getRotationZ()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_GYRO_ZOUT_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\n// EXT_SENS_DATA_* registers\n\n/** Read single byte from external sensor data register.\n * These registers store data read from external sensors by the Slave 0, 1, 2,\n * and 3 on the auxiliary I2C interface. Data read by Slave 4 is stored in\n * I2C_SLV4_DI (Register 53).\n *\n * External sensor data is written to these registers at the Sample Rate as\n * defined in Register 25. This access rate can be reduced by using the Slave\n * Delay Enable registers (Register 103).\n *\n * External sensor data registers, along with the gyroscope measurement\n * registers, accelerometer measurement registers, and temperature measurement\n * registers, are composed of two sets of registers: an internal register set\n * and a user-facing read register set.\n *\n * The data within the external sensors' internal register set is always updated\n * at the Sample Rate (or the reduced access rate) whenever the serial interface\n * is idle. This guarantees that a burst read of sensor registers will read\n * measurements from the same sampling instant. Note that if burst reads are not\n * used, the user is responsible for ensuring a set of single byte reads\n * correspond to a single sampling instant by checking the Data Ready interrupt.\n *\n * Data is placed in these external sensor data registers according to\n * I2C_SLV0_CTRL, I2C_SLV1_CTRL, I2C_SLV2_CTRL, and I2C_SLV3_CTRL (Registers 39,\n * 42, 45, and 48). When more than zero bytes are read (I2C_SLVx_LEN > 0) from\n * an enabled slave (I2C_SLVx_EN = 1), the slave is read at the Sample Rate (as\n * defined in Register 25) or delayed rate (if specified in Register 52 and\n * 103). During each Sample cycle, slave reads are performed in order of Slave\n * number. If all slaves are enabled with more than zero bytes to be read, the\n * order will be Slave 0, followed by Slave 1, Slave 2, and Slave 3.\n *\n * Each enabled slave will have EXT_SENS_DATA registers associated with it by\n * number of bytes read (I2C_SLVx_LEN) in order of slave number, starting from\n * EXT_SENS_DATA_00. Note that this means enabling or disabling a slave may\n * change the higher numbered slaves' associated registers. Furthermore, if\n * fewer total bytes are being read from the external sensors as a result of\n * such a change, then the data remaining in the registers which no longer have\n * an associated slave device (i.e. high numbered registers) will remain in\n * these previously allocated registers unless reset.\n *\n * If the sum of the read lengths of all SLVx transactions exceed the number of\n * available EXT_SENS_DATA registers, the excess bytes will be dropped. There\n * are 24 EXT_SENS_DATA registers and hence the total read lengths between all\n * the slaves cannot be greater than 24 or some bytes will be lost.\n *\n * Note: Slave 4's behavior is distinct from that of Slaves 0-3. For further\n * information regarding the characteristics of Slave 4, please refer to\n * Registers 49 to 53.\n *\n * EXAMPLE:\n * Suppose that Slave 0 is enabled with 4 bytes to be read (I2C_SLV0_EN = 1 and\n * I2C_SLV0_LEN = 4) while Slave 1 is enabled with 2 bytes to be read so that\n * I2C_SLV1_EN = 1 and I2C_SLV1_LEN = 2. In such a situation, EXT_SENS_DATA _00\n * through _03 will be associated with Slave 0, while EXT_SENS_DATA _04 and 05\n * will be associated with Slave 1. If Slave 2 is enabled as well, registers\n * starting from EXT_SENS_DATA_06 will be allocated to Slave 2.\n *\n * If Slave 2 is disabled while Slave 3 is enabled in this same situation, then\n * registers starting from EXT_SENS_DATA_06 will be allocated to Slave 3\n * instead.\n *\n * REGISTER ALLOCATION FOR DYNAMIC DISABLE VS. NORMAL DISABLE:\n * If a slave is disabled at any time, the space initially allocated to the\n * slave in the EXT_SENS_DATA register, will remain associated with that slave.\n * This is to avoid dynamic adjustment of the register allocation.\n *\n * The allocation of the EXT_SENS_DATA registers is recomputed only when (1) all\n * slaves are disabled, or (2) the I2C_MST_RST bit is set (Register 106).\n *\n * This above is also true if one of the slaves gets NACKed and stops\n * functioning.\n *\n * @param position Starting position (0-23)\n * @return Byte read from register\n */\nuint8_t MPU6050::getExternalSensorByte(int position)\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, buffer);\n    return buffer[0];\n}\n\n/** Read word (2 bytes) from external sensor data registers.\n * @param position Starting position (0-21)\n * @return Word read from register\n * @see getExternalSensorByte()\n */\nuint16_t MPU6050::getExternalSensorWord(int position)\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 2, buffer);\n    return (((uint16_t) buffer[0]) << 8) | buffer[1];\n}\n\n/** Read double word (4 bytes) from external sensor data registers.\n * @param position Starting position (0-20)\n * @return Double word read from registers\n * @see getExternalSensorByte()\n */\nuint32_t MPU6050::getExternalSensorDWord(int position)\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_EXT_SENS_DATA_00 + position, 4, buffer);\n    return (((uint32_t) buffer[0]) << 24) | (((uint32_t) buffer[1]) << 16) | (((uint16_t) buffer[2]) << 8) | buffer[3];\n}\n\n// MOT_DETECT_STATUS register\n\n/** Get full motion detection status register content (all bits).\n * @return Motion detection status byte\n * @see MPU6050_RA_MOT_DETECT_STATUS\n */\nuint8_t MPU6050::getMotionStatus()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_MOT_DETECT_STATUS, buffer);\n    return buffer[0];\n}\n\n/** Get X-axis negative motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_XNEG_BIT\n */\nbool MPU6050::getXNegMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XNEG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get X-axis positive motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_XPOS_BIT\n */\nbool MPU6050::getXPosMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_XPOS_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Y-axis negative motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_YNEG_BIT\n */\nbool MPU6050::getYNegMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YNEG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Y-axis positive motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_YPOS_BIT\n */\nbool MPU6050::getYPosMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_YPOS_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Z-axis negative motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_ZNEG_BIT\n */\nbool MPU6050::getZNegMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZNEG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get Z-axis positive motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_ZPOS_BIT\n */\nbool MPU6050::getZPosMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZPOS_BIT, buffer);\n    return buffer[0];\n}\n\n/** Get zero motion detection interrupt status.\n * @return Motion detection status\n * @see MPU6050_RA_MOT_DETECT_STATUS\n * @see MPU6050_MOTION_MOT_ZRMOT_BIT\n */\nbool MPU6050::getZeroMotionDetected()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_MOT_DETECT_STATUS, MPU6050_MOTION_MOT_ZRMOT_BIT, buffer);\n    return buffer[0];\n}\n\n// I2C_SLV*_DO register\n\n/** Write byte to Data Output container for specified slave.\n * This register holds the output data written into Slave when Slave is set to\n * write mode. For further information regarding Slave control, please\n * refer to Registers 37 to 39 and immediately following.\n * @param num Slave number (0-3)\n * @param data Byte to write\n * @see MPU6050_RA_I2C_SLV0_DO\n */\nvoid MPU6050::setSlaveOutputByte(uint8_t num, uint8_t data)\n{\n    if (num > 3) return;\n    I2Cdev_writeByte(devAddr, MPU6050_RA_I2C_SLV0_DO + num, data);\n}\n\n// I2C_MST_DELAY_CTRL register\n\n/** Get external data shadow delay enabled status.\n * This register is used to specify the timing of external sensor data\n * shadowing. When DELAY_ES_SHADOW is set to 1, shadowing of external\n * sensor data is delayed until all data has been received.\n * @return Current external data shadow delay enabled status.\n * @see MPU6050_RA_I2C_MST_DELAY_CTRL\n * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT\n */\nbool MPU6050::getExternalShadowDelayEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set external data shadow delay enabled status.\n * @param enabled New external data shadow delay enabled status.\n * @see getExternalShadowDelayEnabled()\n * @see MPU6050_RA_I2C_MST_DELAY_CTRL\n * @see MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT\n */\nvoid MPU6050::setExternalShadowDelayEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT, enabled);\n}\n\n/** Get slave delay enabled status.\n * When a particular slave delay is enabled, the rate of access for the that\n * slave device is reduced. When a slave's access rate is decreased relative to\n * the Sample Rate, the slave is accessed every:\n *\n *     1 / (1 + I2C_MST_DLY) Samples\n *\n * This base Sample Rate in turn is determined by SMPLRT_DIV (register  * 25)\n * and DLPF_CFG (register 26).\n *\n * For further information regarding I2C_MST_DLY, please refer to register 52.\n * For further information regarding the Sample Rate, please refer to register 25.\n *\n * @param num Slave number (0-4)\n * @return Current slave delay enabled status.\n * @see MPU6050_RA_I2C_MST_DELAY_CTRL\n * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT\n */\nbool MPU6050::getSlaveDelayEnabled(uint8_t num)\n{\n    // MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT is 4, SLV3 is 3, etc.\n    if (num > 4) return 0;\n    I2Cdev_readBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, buffer);\n    return buffer[0];\n}\n\n/** Set slave delay enabled status.\n * @param num Slave number (0-4)\n * @param enabled New slave delay enabled status.\n * @see MPU6050_RA_I2C_MST_DELAY_CTRL\n * @see MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT\n */\nvoid MPU6050::setSlaveDelayEnabled(uint8_t num, bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_I2C_MST_DELAY_CTRL, num, enabled);\n}\n\n// SIGNAL_PATH_RESET register\n\n/** Reset gyroscope signal path.\n * The reset will revert the signal path analog to digital converters and\n * filters to their power up configurations.\n * @see MPU6050_RA_SIGNAL_PATH_RESET\n * @see MPU6050_PATHRESET_GYRO_RESET_BIT\n */\nvoid MPU6050::resetGyroscopePath()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_GYRO_RESET_BIT, true);\n}\n\n/** Reset accelerometer signal path.\n * The reset will revert the signal path analog to digital converters and\n * filters to their power up configurations.\n * @see MPU6050_RA_SIGNAL_PATH_RESET\n * @see MPU6050_PATHRESET_ACCEL_RESET_BIT\n */\nvoid MPU6050::resetAccelerometerPath()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_ACCEL_RESET_BIT, true);\n}\n\n/** Reset temperature sensor signal path.\n * The reset will revert the signal path analog to digital converters and\n * filters to their power up configurations.\n * @see MPU6050_RA_SIGNAL_PATH_RESET\n * @see MPU6050_PATHRESET_TEMP_RESET_BIT\n */\nvoid MPU6050::resetTemperaturePath()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_SIGNAL_PATH_RESET, MPU6050_PATHRESET_TEMP_RESET_BIT, true);\n}\n\n// MOT_DETECT_CTRL register\n\n/** Get accelerometer power-on delay.\n * The accelerometer data path provides samples to the sensor registers, Motion\n * detection, Zero Motion detection, and Free Fall detection modules. The\n * signal path contains filters which must be flushed on wake-up with new\n * samples before the detection modules begin operations. The default wake-up\n * delay, of 4ms can be lengthened by up to 3ms. This additional delay is\n * specified in ACCEL_ON_DELAY in units of 1 LSB = 1 ms. The user may select\n * any value above zero unless instructed otherwise by InvenSense. Please refer\n * to Section 8 of the MPU-6000/MPU-6050 Product Specification document for\n * further information regarding the detection modules.\n * @return Current accelerometer power-on delay\n * @see MPU6050_RA_MOT_DETECT_CTRL\n * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT\n */\nuint8_t MPU6050::getAccelerometerPowerOnDelay()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT,\n                    MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set accelerometer power-on delay.\n * @param delay New accelerometer power-on delay (0-3)\n * @see getAccelerometerPowerOnDelay()\n * @see MPU6050_RA_MOT_DETECT_CTRL\n * @see MPU6050_DETECT_ACCEL_ON_DELAY_BIT\n */\nvoid MPU6050::setAccelerometerPowerOnDelay(uint8_t delay)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_ACCEL_ON_DELAY_BIT,\n                     MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH, delay);\n}\n\n/** Get Free Fall detection counter decrement configuration.\n * Detection is registered by the Free Fall detection module after accelerometer\n * measurements meet their respective threshold conditions over a specified\n * number of samples. When the threshold conditions are met, the corresponding\n * detection counter increments by 1. The user may control the rate at which the\n * detection counter decrements when the threshold condition is not met by\n * configuring FF_COUNT. The decrement rate can be set according to the\n * following table:\n *\n * <pre>\n * FF_COUNT | Counter Decrement\n * ---------+------------------\n * 0        | Reset\n * 1        | 1\n * 2        | 2\n * 3        | 4\n * </pre>\n *\n * When FF_COUNT is configured to 0 (reset), any non-qualifying sample will\n * reset the counter to 0. For further information on Free Fall detection,\n * please refer to Registers 29 to 32.\n *\n * @return Current decrement configuration\n * @see MPU6050_RA_MOT_DETECT_CTRL\n * @see MPU6050_DETECT_FF_COUNT_BIT\n */\nuint8_t MPU6050::getFreefallDetectionCounterDecrement()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set Free Fall detection counter decrement configuration.\n * @param decrement New decrement configuration value\n * @see getFreefallDetectionCounterDecrement()\n * @see MPU6050_RA_MOT_DETECT_CTRL\n * @see MPU6050_DETECT_FF_COUNT_BIT\n */\nvoid MPU6050::setFreefallDetectionCounterDecrement(uint8_t decrement)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_FF_COUNT_BIT, MPU6050_DETECT_FF_COUNT_LENGTH,\n                     decrement);\n}\n\n/** Get Motion detection counter decrement configuration.\n * Detection is registered by the Motion detection module after accelerometer\n * measurements meet their respective threshold conditions over a specified\n * number of samples. When the threshold conditions are met, the corresponding\n * detection counter increments by 1. The user may control the rate at which the\n * detection counter decrements when the threshold condition is not met by\n * configuring MOT_COUNT. The decrement rate can be set according to the\n * following table:\n *\n * <pre>\n * MOT_COUNT | Counter Decrement\n * ----------+------------------\n * 0         | Reset\n * 1         | 1\n * 2         | 2\n * 3         | 4\n * </pre>\n *\n * When MOT_COUNT is configured to 0 (reset), any non-qualifying sample will\n * reset the counter to 0. For further information on Motion detection,\n * please refer to Registers 29 to 32.\n *\n */\nuint8_t MPU6050::getMotionDetectionCounterDecrement()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT, MPU6050_DETECT_MOT_COUNT_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set Motion detection counter decrement configuration.\n * @param decrement New decrement configuration value\n * @see getMotionDetectionCounterDecrement()\n * @see MPU6050_RA_MOT_DETECT_CTRL\n * @see MPU6050_DETECT_MOT_COUNT_BIT\n */\nvoid MPU6050::setMotionDetectionCounterDecrement(uint8_t decrement)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_MOT_DETECT_CTRL, MPU6050_DETECT_MOT_COUNT_BIT,\n                     MPU6050_DETECT_MOT_COUNT_LENGTH, decrement);\n}\n\n// USER_CTRL register\n\n/** Get FIFO enabled status.\n * When this bit is set to 0, the FIFO buffer is disabled. The FIFO buffer\n * cannot be written to or read from while disabled. The FIFO buffer's state\n * does not change unless the MPU-60X0 is power cycled.\n * @return Current FIFO enabled status\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_FIFO_EN_BIT\n */\nbool MPU6050::getFIFOEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set FIFO enabled status.\n * @param enabled New FIFO enabled status\n * @see getFIFOEnabled()\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_FIFO_EN_BIT\n */\nvoid MPU6050::setFIFOEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_EN_BIT, enabled);\n}\n\n/** Get I2C Master Mode enabled status.\n * When this mode is enabled, the MPU-60X0 acts as the I2C Master to the\n * external sensor slave devices on the auxiliary I2C bus. When this bit is\n * cleared to 0, the auxiliary I2C bus lines (AUX_DA and AUX_CL) are logically\n * driven by the primary I2C bus (SDA and SCL). This is a precondition to\n * enabling Bypass Mode. For further information regarding Bypass Mode, please\n * refer to Register 55.\n * @return Current I2C Master Mode enabled status\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_I2C_MST_EN_BIT\n */\nbool MPU6050::getI2CMasterModeEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set I2C Master Mode enabled status.\n * @param enabled New I2C Master Mode enabled status\n * @see getI2CMasterModeEnabled()\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_I2C_MST_EN_BIT\n */\nvoid MPU6050::setI2CMasterModeEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_EN_BIT, enabled);\n}\n\n/** Switch from I2C to SPI mode (MPU-6000 only)\n * If this is set, the primary SPI interface will be enabled in place of the\n * disabled primary I2C interface.\n */\nvoid MPU6050::switchSPIEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_IF_DIS_BIT, enabled);\n}\n\n/** Reset the FIFO.\n * This bit resets the FIFO buffer when set to 1 while FIFO_EN equals 0. This\n * bit automatically clears to 0 after the reset has been triggered.\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_FIFO_RESET_BIT\n */\nvoid MPU6050::resetFIFO()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_FIFO_RESET_BIT, true);\n}\n\n/** Reset the I2C Master.\n * This bit resets the I2C Master when set to 1 while I2C_MST_EN equals 0.\n * This bit automatically clears to 0 after the reset has been triggered.\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_I2C_MST_RESET_BIT\n */\nvoid MPU6050::resetI2CMaster()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_I2C_MST_RESET_BIT, true);\n}\n\n/** Reset all sensor registers and signal paths.\n * When set to 1, this bit resets the signal paths for all sensors (gyroscopes,\n * accelerometers, and temperature sensor). This operation will also clear the\n * sensor registers. This bit automatically clears to 0 after the reset has been\n * triggered.\n *\n * When resetting only the signal path (and not the sensor registers), please\n * use Register 104, SIGNAL_PATH_RESET.\n *\n * @see MPU6050_RA_USER_CTRL\n * @see MPU6050_USERCTRL_SIG_COND_RESET_BIT\n */\nvoid MPU6050::resetSensors()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_SIG_COND_RESET_BIT, true);\n}\n\n// PWR_MGMT_1 register\n\n/** Trigger a full device reset.\n * A small delay of ~50ms may be desirable after triggering a reset.\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_DEVICE_RESET_BIT\n */\nvoid MPU6050::reset()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_DEVICE_RESET_BIT, true);\n}\n\n/** Get sleep mode status.\n * Setting the SLEEP bit in the register puts the device into very low power\n * sleep mode. In this mode, only the serial interface and internal registers\n * remain active, allowing for a very low standby current. Clearing this bit\n * puts the device back into normal mode. To save power, the individual standby\n * selections for each of the gyros should be used if any gyro axis is not used\n * by the application.\n * @return Current sleep mode enabled status\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_SLEEP_BIT\n */\nbool MPU6050::getSleepEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set sleep mode status.\n * @param enabled New sleep mode enabled status\n * @see getSleepEnabled()\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_SLEEP_BIT\n */\nvoid MPU6050::setSleepEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_SLEEP_BIT, enabled);\n}\n\n/** Get wake cycle enabled status.\n * When this bit is set to 1 and SLEEP is disabled, the MPU-60X0 will cycle\n * between sleep mode and waking up to take a single sample of data from active\n * sensors at a rate determined by LP_WAKE_CTRL (register 108).\n * @return Current sleep mode enabled status\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_CYCLE_BIT\n */\nbool MPU6050::getWakeCycleEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set wake cycle enabled status.\n * @param enabled New sleep mode enabled status\n * @see getWakeCycleEnabled()\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_CYCLE_BIT\n */\nvoid MPU6050::setWakeCycleEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CYCLE_BIT, enabled);\n}\n\n/** Get temperature sensor enabled status.\n * Control the usage of the internal temperature sensor.\n *\n * Note: this register stores the *disabled* value, but for consistency with the\n * rest of the code, the function is named and used with standard true/false\n * values to indicate whether the sensor is enabled or disabled, respectively.\n *\n * @return Current temperature sensor enabled status\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_TEMP_DIS_BIT\n */\nbool MPU6050::getTempSensorEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, buffer);\n    return buffer[0] == 0; // 1 is actually disabled here\n}\n\n/** Set temperature sensor enabled status.\n * Note: this register stores the *disabled* value, but for consistency with the\n * rest of the code, the function is named and used with standard true/false\n * values to indicate whether the sensor is enabled or disabled, respectively.\n *\n * @param enabled New temperature sensor enabled status\n * @see getTempSensorEnabled()\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_TEMP_DIS_BIT\n */\nvoid MPU6050::setTempSensorEnabled(bool enabled)\n{\n    // 1 is actually disabled here\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_TEMP_DIS_BIT, !enabled);\n}\n\n/** Get clock source setting.\n * @return Current clock source setting\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_CLKSEL_BIT\n * @see MPU6050_PWR1_CLKSEL_LENGTH\n */\nuint8_t MPU6050::getClockSource()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set clock source setting.\n * An internal 8MHz oscillator, gyroscope based clock, or external sources can\n * be selected as the MPU-60X0 clock source. When the internal 8 MHz oscillator\n * or an external source is chosen as the clock source, the MPU-60X0 can operate\n * in low power modes with the gyroscopes disabled.\n *\n * Upon power up, the MPU-60X0 clock source defaults to the internal oscillator.\n * However, it is highly recommended that the device be configured to use one of\n * the gyroscopes (or an external clock source) as the clock reference for\n * improved stability. The clock source can be selected according to the following table:\n *\n * <pre>\n * CLK_SEL | Clock Source\n * --------+--------------------------------------\n * 0       | Internal oscillator\n * 1       | PLL with X Gyro reference\n * 2       | PLL with Y Gyro reference\n * 3       | PLL with Z Gyro reference\n * 4       | PLL with external 32.768kHz reference\n * 5       | PLL with external 19.2MHz reference\n * 6       | Reserved\n * 7       | Stops the clock and keeps the timing generator in reset\n * </pre>\n *\n * @param source New clock source setting\n * @see getClockSource()\n * @see MPU6050_RA_PWR_MGMT_1\n * @see MPU6050_PWR1_CLKSEL_BIT\n * @see MPU6050_PWR1_CLKSEL_LENGTH\n */\nvoid MPU6050::setClockSource(uint8_t source)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_PWR_MGMT_1, MPU6050_PWR1_CLKSEL_BIT, MPU6050_PWR1_CLKSEL_LENGTH, source);\n}\n\n// PWR_MGMT_2 register\n\n/** Get wake frequency in Accel-Only Low Power Mode.\n * The MPU-60X0 can be put into Accerlerometer Only Low Power Mode by setting\n * PWRSEL to 1 in the Power Management 1 register (Register 107). In this mode,\n * the device will power off all devices except for the primary I2C interface,\n * waking only the accelerometer at fixed intervals to take a single\n * measurement. The frequency of wake-ups can be configured with LP_WAKE_CTRL\n * as shown below:\n *\n * <pre>\n * LP_WAKE_CTRL | Wake-up Frequency\n * -------------+------------------\n * 0            | 1.25 Hz\n * 1            | 2.5 Hz\n * 2            | 5 Hz\n * 3            | 10 Hz\n * </pre>\n *\n * For further information regarding the MPU-60X0's power modes, please refer to\n * Register 107.\n *\n * @return Current wake frequency\n * @see MPU6050_RA_PWR_MGMT_2\n */\nuint8_t MPU6050::getWakeFrequency()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH,\n                    buffer);\n    return buffer[0];\n}\n\n/** Set wake frequency in Accel-Only Low Power Mode.\n * @param frequency New wake frequency\n * @see MPU6050_RA_PWR_MGMT_2\n */\nvoid MPU6050::setWakeFrequency(uint8_t frequency)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_LP_WAKE_CTRL_BIT, MPU6050_PWR2_LP_WAKE_CTRL_LENGTH,\n                     frequency);\n}\n\n/** Get X-axis accelerometer standby enabled status.\n * If enabled, the X-axis will not gather or report data (or use power).\n * @return Current X-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_XA_BIT\n */\nbool MPU6050::getStandbyXAccelEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set X-axis accelerometer standby enabled status.\n * @param New X-axis standby enabled status\n * @see getStandbyXAccelEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_XA_BIT\n */\nvoid MPU6050::setStandbyXAccelEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XA_BIT, enabled);\n}\n\n/** Get Y-axis accelerometer standby enabled status.\n * If enabled, the Y-axis will not gather or report data (or use power).\n * @return Current Y-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_YA_BIT\n */\nbool MPU6050::getStandbyYAccelEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Y-axis accelerometer standby enabled status.\n * @param New Y-axis standby enabled status\n * @see getStandbyYAccelEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_YA_BIT\n */\nvoid MPU6050::setStandbyYAccelEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YA_BIT, enabled);\n}\n\n/** Get Z-axis accelerometer standby enabled status.\n * If enabled, the Z-axis will not gather or report data (or use power).\n * @return Current Z-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_ZA_BIT\n */\nbool MPU6050::getStandbyZAccelEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Z-axis accelerometer standby enabled status.\n * @param New Z-axis standby enabled status\n * @see getStandbyZAccelEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_ZA_BIT\n */\nvoid MPU6050::setStandbyZAccelEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZA_BIT, enabled);\n}\n\n/** Get X-axis gyroscope standby enabled status.\n * If enabled, the X-axis will not gather or report data (or use power).\n * @return Current X-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_XG_BIT\n */\nbool MPU6050::getStandbyXGyroEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set X-axis gyroscope standby enabled status.\n * @param New X-axis standby enabled status\n * @see getStandbyXGyroEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_XG_BIT\n */\nvoid MPU6050::setStandbyXGyroEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_XG_BIT, enabled);\n}\n\n/** Get Y-axis gyroscope standby enabled status.\n * If enabled, the Y-axis will not gather or report data (or use power).\n * @return Current Y-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_YG_BIT\n */\nbool MPU6050::getStandbyYGyroEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Y-axis gyroscope standby enabled status.\n * @param New Y-axis standby enabled status\n * @see getStandbyYGyroEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_YG_BIT\n */\nvoid MPU6050::setStandbyYGyroEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_YG_BIT, enabled);\n}\n\n/** Get Z-axis gyroscope standby enabled status.\n * If enabled, the Z-axis will not gather or report data (or use power).\n * @return Current Z-axis standby enabled status\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_ZG_BIT\n */\nbool MPU6050::getStandbyZGyroEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, buffer);\n    return buffer[0];\n}\n\n/** Set Z-axis gyroscope standby enabled status.\n * @param New Z-axis standby enabled status\n * @see getStandbyZGyroEnabled()\n * @see MPU6050_RA_PWR_MGMT_2\n * @see MPU6050_PWR2_STBY_ZG_BIT\n */\nvoid MPU6050::setStandbyZGyroEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_PWR_MGMT_2, MPU6050_PWR2_STBY_ZG_BIT, enabled);\n}\n\n// FIFO_COUNT* registers\n\n/** Get current FIFO buffer size.\n * This value indicates the number of bytes stored in the FIFO buffer. This\n * number is in turn the number of bytes that can be read from the FIFO buffer\n * and it is directly proportional to the number of samples available given the\n * set of sensor data bound to be stored in the FIFO (register 35 and 36).\n * @return Current FIFO buffer size\n */\nuint16_t MPU6050::getFIFOCount()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_FIFO_COUNTH, 2, buffer);\n    return (((uint16_t) buffer[0]) << 8) | buffer[1];\n}\n\n// FIFO_R_W register\n\n/** Get byte from FIFO buffer.\n * This register is used to read and write data from the FIFO buffer. Data is\n * written to the FIFO in order of register number (from lowest to highest). If\n * all the FIFO enable flags (see below) are enabled and all External Sensor\n * Data registers (Registers 73 to 96) are associated with a Slave device, the\n * contents of registers 59 through 96 will be written in order at the Sample\n * Rate.\n *\n * The contents of the sensor data registers (Registers 59 to 96) are written\n * into the FIFO buffer when their corresponding FIFO enable flags are set to 1\n * in FIFO_EN (Register 35). An additional flag for the sensor data registers\n * associated with I2C Slave 3 can be found in I2C_MST_CTRL (Register 36).\n *\n * If the FIFO buffer has overflowed, the status bit FIFO_OFLOW_INT is\n * automatically set to 1. This bit is located in INT_STATUS (Register 58).\n * When the FIFO buffer has overflowed, the oldest data will be lost and new\n * data will be written to the FIFO.\n *\n * If the FIFO buffer is empty, reading this register will return the last byte\n * that was previously read from the FIFO until new data is available. The user\n * should check FIFO_COUNT to ensure that the FIFO buffer is not read when\n * empty.\n *\n * @return Byte from FIFO buffer\n */\nuint8_t MPU6050::getFIFOByte()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_FIFO_R_W, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::getFIFOBytes(uint8_t *data, uint8_t length)\n{\n    if (length > 0)\n    {\n        I2Cdev_readBytes(devAddr, MPU6050_RA_FIFO_R_W, length, data);\n    } else\n    {\n        *data = 0;\n    }\n}\n\n/** Write byte to FIFO buffer.\n * @see getFIFOByte()\n * @see MPU6050_RA_FIFO_R_W\n */\nvoid MPU6050::setFIFOByte(uint8_t data)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_FIFO_R_W, data);\n}\n\n// WHO_AM_I register\n\n/** Get Device ID.\n * This register is used to verify the identity of the device (0b110100, 0x34).\n * @return Device ID (6 bits only! should be 0x34)\n * @see MPU6050_RA_WHO_AM_I\n * @see MPU6050_WHO_AM_I_BIT\n * @see MPU6050_WHO_AM_I_LENGTH\n */\nuint8_t MPU6050::getDeviceID()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, buffer);\n    return buffer[0];\n}\n\n/** Set Device ID.\n * Write a new ID into the WHO_AM_I register (no idea why this should ever be\n * necessary though).\n * @param id New device ID to set.\n * @see getDeviceID()\n * @see MPU6050_RA_WHO_AM_I\n * @see MPU6050_WHO_AM_I_BIT\n * @see MPU6050_WHO_AM_I_LENGTH\n */\nvoid MPU6050::setDeviceID(uint8_t id)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, id);\n}\n\n// ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========\n\n// XG_OFFS_TC register\n\nuint8_t MPU6050::getOTPBankValid()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setOTPBankValid(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OTP_BNK_VLD_BIT, enabled);\n}\n\nint8_t MPU6050::getXGyroOffsetTC()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setXGyroOffsetTC(int8_t offset)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_XG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);\n}\n\n// YG_OFFS_TC register\n\nint8_t MPU6050::getYGyroOffsetTC()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setYGyroOffsetTC(int8_t offset)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_YG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);\n}\n\n// ZG_OFFS_TC register\n\nint8_t MPU6050::getZGyroOffsetTC()\n{\n    I2Cdev_readBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setZGyroOffsetTC(int8_t offset)\n{\n    I2Cdev_writeBits(devAddr, MPU6050_RA_ZG_OFFS_TC, MPU6050_TC_OFFSET_BIT, MPU6050_TC_OFFSET_LENGTH, offset);\n}\n\n// X_FINE_GAIN register\n\nint8_t MPU6050::getXFineGain()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_X_FINE_GAIN, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setXFineGain(int8_t gain)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_X_FINE_GAIN, gain);\n}\n\n// Y_FINE_GAIN register\n\nint8_t MPU6050::getYFineGain()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_Y_FINE_GAIN, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setYFineGain(int8_t gain)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_Y_FINE_GAIN, gain);\n}\n\n// Z_FINE_GAIN register\n\nint8_t MPU6050::getZFineGain()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_Z_FINE_GAIN, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setZFineGain(int8_t gain)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_Z_FINE_GAIN, gain);\n}\n\n// XA_OFFS_* registers\n\nint16_t MPU6050::getXAccelOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_XA_OFFS_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setXAccelOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_XA_OFFS_H, offset);\n}\n\n// YA_OFFS_* register\n\nint16_t MPU6050::getYAccelOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_YA_OFFS_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setYAccelOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_YA_OFFS_H, offset);\n}\n\n// ZA_OFFS_* register\n\nint16_t MPU6050::getZAccelOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ZA_OFFS_H, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setZAccelOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_ZA_OFFS_H, offset);\n}\n\n// XG_OFFS_USR* registers\n\nint16_t MPU6050::getXGyroOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_XG_OFFS_USRH, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setXGyroOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_XG_OFFS_USRH, offset);\n}\n\n// YG_OFFS_USR* register\n\nint16_t MPU6050::getYGyroOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_YG_OFFS_USRH, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setYGyroOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_YG_OFFS_USRH, offset);\n}\n\n// ZG_OFFS_USR* register\n\nint16_t MPU6050::getZGyroOffset()\n{\n    I2Cdev_readBytes(devAddr, MPU6050_RA_ZG_OFFS_USRH, 2, buffer);\n    return (((int16_t) buffer[0]) << 8) | buffer[1];\n}\n\nvoid MPU6050::setZGyroOffset(int16_t offset)\n{\n    I2Cdev_writeWord(devAddr, MPU6050_RA_ZG_OFFS_USRH, offset);\n}\n\n// INT_ENABLE register (DMP functions)\n\nbool MPU6050::getIntPLLReadyEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setIntPLLReadyEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, enabled);\n}\n\nbool MPU6050::getIntDMPEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setIntDMPEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_INT_ENABLE, MPU6050_INTERRUPT_DMP_INT_BIT, enabled);\n}\n\n// DMP_INT_STATUS\n\nbool MPU6050::getDMPInt5Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_5_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getDMPInt4Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_4_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getDMPInt3Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_3_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getDMPInt2Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_2_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getDMPInt1Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_1_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getDMPInt0Status()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_DMP_INT_STATUS, MPU6050_DMPINT_0_BIT, buffer);\n    return buffer[0];\n}\n\n// INT_STATUS register (DMP functions)\n\nbool MPU6050::getIntPLLReadyStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_PLL_RDY_INT_BIT, buffer);\n    return buffer[0];\n}\n\nbool MPU6050::getIntDMPStatus()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_INT_STATUS, MPU6050_INTERRUPT_DMP_INT_BIT, buffer);\n    return buffer[0];\n}\n\n// USER_CTRL register (DMP functions)\n\nbool MPU6050::getDMPEnabled()\n{\n    I2Cdev_readBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setDMPEnabled(bool enabled)\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_EN_BIT, enabled);\n}\n\nvoid MPU6050::resetDMP()\n{\n    I2Cdev_writeBit(devAddr, MPU6050_RA_USER_CTRL, MPU6050_USERCTRL_DMP_RESET_BIT, true);\n}\n\n// BANK_SEL register\n\nvoid MPU6050::setMemoryBank(uint8_t bank, bool prefetchEnabled, bool userBank)\n{\n    bank &= 0x1F;\n    if (userBank) bank |= 0x20;\n    if (prefetchEnabled) bank |= 0x40;\n    I2Cdev_writeByte(devAddr, MPU6050_RA_BANK_SEL, bank);\n}\n\n// MEM_START_ADDR register\n\nvoid MPU6050::setMemoryStartAddress(uint8_t address)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_MEM_START_ADDR, address);\n}\n\n// MEM_R_W register\n\nuint8_t MPU6050::readMemoryByte()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_MEM_R_W, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::writeMemoryByte(uint8_t data)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_MEM_R_W, data);\n}\n\nvoid MPU6050::readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address)\n{\n    setMemoryBank(bank);\n    setMemoryStartAddress(address);\n    uint8_t chunkSize;\n    for (uint16_t i = 0; i < dataSize;)\n    {\n        // determine correct chunk size according to bank position and data size\n        chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;\n\n        // make sure we don't go past the data size\n        if (i + chunkSize > dataSize) chunkSize = dataSize - i;\n\n        // make sure this chunk doesn't go past the bank boundary (256 bytes)\n        if (chunkSize > 256 - address) chunkSize = 256 - address;\n\n        // read the chunk of data as specified\n        I2Cdev_readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, data + i);\n\n        // increase byte index by [chunkSize]\n        i += chunkSize;\n\n        // uint8_t automatically wraps to 0 at 256\n        address += chunkSize;\n\n        // if we aren't done, update bank (if necessary) and address\n        if (i < dataSize)\n        {\n            if (address == 0) bank++;\n            setMemoryBank(bank);\n            setMemoryStartAddress(address);\n        }\n    }\n}\n\nbool MPU6050::writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify,\n                               bool useProgMem)\n{\n    setMemoryBank(bank);\n    setMemoryStartAddress(address);\n    uint8_t chunkSize;\n    uint8_t *verifyBuffer = 0;\n    uint8_t *progBuffer = 0;\n    uint16_t i;\n    uint8_t j;\n    if (verify) verifyBuffer = (uint8_t *) malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);\n    if (useProgMem) progBuffer = (uint8_t *) malloc(MPU6050_DMP_MEMORY_CHUNK_SIZE);\n    for (i = 0; i < dataSize;)\n    {\n        // determine correct chunk size according to bank position and data size\n        chunkSize = MPU6050_DMP_MEMORY_CHUNK_SIZE;\n\n        // make sure we don't go past the data size\n        if (i + chunkSize > dataSize) chunkSize = dataSize - i;\n\n        // make sure this chunk doesn't go past the bank boundary (256 bytes)\n        if (chunkSize > 256 - address) chunkSize = 256 - address;\n\n        if (useProgMem)\n        {\n            // write the chunk of data as specified\n            for (j = 0; j < chunkSize; j++) progBuffer[j] = pgm_read_byte(data + i + j);\n        } else\n        {\n            // write the chunk of data as specified\n            progBuffer = (uint8_t *) data + i;\n        }\n\n        I2Cdev_writeBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, progBuffer);\n\n        // verify data if needed\n        if (verify && verifyBuffer)\n        {\n            setMemoryBank(bank);\n            setMemoryStartAddress(address);\n            I2Cdev_readBytes(devAddr, MPU6050_RA_MEM_R_W, chunkSize, verifyBuffer);\n            if (memcmp(progBuffer, verifyBuffer, chunkSize) != 0)\n            {\n                /*Serial.print(\"Block write verification error, bank \");\n                Serial.print(bank, DEC);\n                Serial.print(\", address \");\n                Serial.print(address, DEC);\n                Serial.print(\"!\\nExpected:\");\n                for (j = 0; j < chunkSize; j++) {\n                    Serial.print(\" 0x\");\n                    if (progBuffer[j] < 16) Serial.print(\"0\");\n                    Serial.print(progBuffer[j], HEX);\n                }\n                Serial.print(\"\\nReceived:\");\n                for (uint8_t j = 0; j < chunkSize; j++) {\n                    Serial.print(\" 0x\");\n                    if (verifyBuffer[i + j] < 16) Serial.print(\"0\");\n                    Serial.print(verifyBuffer[i + j], HEX);\n                }\n                Serial.print(\"\\n\");*/\n                free(verifyBuffer);\n                if (useProgMem) free(progBuffer);\n                return false; // uh oh.\n            }\n        }\n\n        // increase byte index by [chunkSize]\n        i += chunkSize;\n\n        // uint8_t automatically wraps to 0 at 256\n        address += chunkSize;\n\n        // if we aren't done, update bank (if necessary) and address\n        if (i < dataSize)\n        {\n            if (address == 0) bank++;\n            setMemoryBank(bank);\n            setMemoryStartAddress(address);\n        }\n    }\n    if (verify) free(verifyBuffer);\n    if (useProgMem) free(progBuffer);\n    return true;\n}\n\nbool MPU6050::writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank, uint8_t address, bool verify)\n{\n    return writeMemoryBlock(data, dataSize, bank, address, verify, true);\n}\n\nbool MPU6050::writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem)\n{\n    uint8_t *progBuffer = 0;\n    uint8_t success, special;\n    uint16_t i, j;\n    if (useProgMem)\n    {\n        progBuffer = (uint8_t *) malloc(8); // assume 8-byte blocks, realloc later if necessary\n    }\n\n    // config set data is a long string of blocks with the following structure:\n    // [bank] [offset] [length] [byte[0], byte[1], ..., byte[length]]\n    uint8_t bank, offset, length;\n    for (i = 0; i < dataSize;)\n    {\n        if (useProgMem)\n        {\n            bank = pgm_read_byte(data + i++);\n            offset = pgm_read_byte(data + i++);\n            length = pgm_read_byte(data + i++);\n        } else\n        {\n            bank = data[i++];\n            offset = data[i++];\n            length = data[i++];\n        }\n\n        // write data or perform special action\n        if (length > 0)\n        {\n            // regular block of data to write\n            /*Serial.print(\"Writing config block to bank \");\n            Serial.print(bank);\n            Serial.print(\", offset \");\n            Serial.print(offset);\n            Serial.print(\", length=\");\n            Serial.println(length);*/\n            if (useProgMem)\n            {\n                if (sizeof(progBuffer) < length) progBuffer = (uint8_t *) realloc(progBuffer, length);\n                for (j = 0; j < length; j++) progBuffer[j] = pgm_read_byte(data + i + j);\n            } else\n            {\n                progBuffer = (uint8_t *) data + i;\n            }\n            success = writeMemoryBlock(progBuffer, length, bank, offset, true);\n            i += length;\n        } else\n        {\n            // special instruction\n            // NOTE: this kind of behavior (what and when to do certain things)\n            // is totally undocumented. This code is in here based on observed\n            // behavior only, and exactly why (or even whether) it has to be here\n            // is anybody's guess for now.\n            if (useProgMem)\n            {\n                special = pgm_read_byte(data + i++);\n            } else\n            {\n                special = data[i++];\n            }\n            /*Serial.print(\"Special command code \");\n            Serial.print(special, HEX);\n            Serial.println(\" found...\");*/\n            if (special == 0x01)\n            {\n                // enable DMP-related interrupts\n\n                //setIntZeroMotionEnabled(true);\n                //setIntFIFOBufferOverflowEnabled(true);\n                //setIntDMPEnabled(true);\n                I2Cdev_writeByte(devAddr, MPU6050_RA_INT_ENABLE, 0x32);  // single operation\n\n                success = true;\n            } else\n            {\n                // unknown special command\n                success = false;\n            }\n        }\n\n        if (!success)\n        {\n            if (useProgMem) free(progBuffer);\n            return false; // uh oh\n        }\n    }\n    if (useProgMem) free(progBuffer);\n    return true;\n}\n\nbool MPU6050::writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize)\n{\n    return writeDMPConfigurationSet(data, dataSize, true);\n}\n\n// DMP_CFG_1 register\n\nuint8_t MPU6050::getDMPConfig1()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_DMP_CFG_1, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setDMPConfig1(uint8_t config)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_DMP_CFG_1, config);\n}\n\n// DMP_CFG_2 register\n\nuint8_t MPU6050::getDMPConfig2()\n{\n    I2Cdev_readByte(devAddr, MPU6050_RA_DMP_CFG_2, buffer);\n    return buffer[0];\n}\n\nvoid MPU6050::setDMPConfig2(uint8_t config)\n{\n    I2Cdev_writeByte(devAddr, MPU6050_RA_DMP_CFG_2, config);\n}\n\nvoid MPU6050::Update(bool _useFilter)\n{\n    getMotion6(&dataRaw.ax, &dataRaw.ay, &dataRaw.az, &dataRaw.gx, &dataRaw.gy, &dataRaw.gz);\n    data.ax = (float) dataRaw.ax / accRangeScale;\n    data.ay = (float) dataRaw.ay / accRangeScale;\n    data.az = (float) dataRaw.az / accRangeScale;\n    data.gx = (float) dataRaw.gx / gyroRangeScale;\n    data.gy = (float) dataRaw.gy / gyroRangeScale;\n    data.gz = (float) dataRaw.gz / gyroRangeScale;\n\n    if (_useFilter)\n    {\n        data.ax = biquadFilterApply(&accFilterLPF[0], data.ax);\n        data.ay = biquadFilterApply(&accFilterLPF[1], data.ay);\n        data.az = biquadFilterApply(&accFilterLPF[2], data.az);\n        data.gx = biquadFilterApply(&gyroFilterLPF[0], data.gx);\n        data.gy = biquadFilterApply(&gyroFilterLPF[1], data.gy);\n        data.gz = biquadFilterApply(&gyroFilterLPF[2], data.gz);\n    }\n}\nvoid MPU6050::InitFilter(float _imuUpdateRate,\n                         float _gyroFilterCutoffFreq,\n                         float _accFilterCutoffFreq)\n{\n\n    for (int i = 0; i < 3; i++)\n    {\n        biquadFilterInitLPF(&gyroFilterLPF[i], _imuUpdateRate, _gyroFilterCutoffFreq);\n        biquadFilterInitLPF(&accFilterLPF[i], _imuUpdateRate, _accFilterCutoffFreq);\n    }\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/MPU6050.hpp",
    "content": "// I2Cdev library collection - MPU6050 I2C device class\n// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)\n// 10/3/2011 by Jeff Rowberg <jeff@rowberg.net>\n// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib\n//\n// Changelog:\n//     ... - ongoing debug release\n\n// NOTE: THIS IS ONLY A PARIAL RELEASE. THIS DEVICE CLASS IS CURRENTLY UNDERGOING ACTIVE\n// DEVELOPMENT AND IS STILL MISSING SOME IMPORTANT FEATURES. PLEASE KEEP THIS IN MIND IF\n// YOU DECIDE TO USE THIS PARTICULAR CODE FOR ANYTHING.\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2012 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#ifndef _MPU6050_H_\n#define _MPU6050_H_\n\n#include \"i2c_dev.hpp\"\n#include \"biquad_filter.h\"\n\n// supporting link:  http://forum.arduino.cc/index.php?&topic=143444.msg1079517#msg1079517\n// also: http://forum.arduino.cc/index.php?&topic=141571.msg1062899#msg1062899s\n\n#define MPU6050_ADDRESS_AD0_LOW     0x68 // address pin low (GND), default for InvenSense evaluation board\n#define MPU6050_ADDRESS_AD0_HIGH    0x69 // address pin high (VCC)\n#define MPU6050_DEFAULT_ADDRESS     MPU6050_ADDRESS_AD0_LOW\n\n#define MPU6050_RA_XG_OFFS_TC       0x00 //[7] PWR_MODE, [6:1] XG_OFFS_TC, [0] OTP_BNK_VLD\n#define MPU6050_RA_YG_OFFS_TC       0x01 //[7] PWR_MODE, [6:1] YG_OFFS_TC, [0] OTP_BNK_VLD\n#define MPU6050_RA_ZG_OFFS_TC       0x02 //[7] PWR_MODE, [6:1] ZG_OFFS_TC, [0] OTP_BNK_VLD\n#define MPU6050_RA_X_FINE_GAIN      0x03 //[7:0] X_FINE_GAIN\n#define MPU6050_RA_Y_FINE_GAIN      0x04 //[7:0] Y_FINE_GAIN\n#define MPU6050_RA_Z_FINE_GAIN      0x05 //[7:0] Z_FINE_GAIN\n#define MPU6050_RA_XA_OFFS_H        0x06 //[15:0] XA_OFFS\n#define MPU6050_RA_XA_OFFS_L_TC     0x07\n#define MPU6050_RA_YA_OFFS_H        0x08 //[15:0] YA_OFFS\n#define MPU6050_RA_YA_OFFS_L_TC     0x09\n#define MPU6050_RA_ZA_OFFS_H        0x0A //[15:0] ZA_OFFS\n#define MPU6050_RA_ZA_OFFS_L_TC     0x0B\n#define MPU6050_RA_SELF_TEST_X      0x0D //[7:5] XA_TEST[4-2], [4:0] XG_TEST[4-0]\n#define MPU6050_RA_SELF_TEST_Y      0x0E //[7:5] YA_TEST[4-2], [4:0] YG_TEST[4-0]\n#define MPU6050_RA_SELF_TEST_Z      0x0F //[7:5] ZA_TEST[4-2], [4:0] ZG_TEST[4-0]\n#define MPU6050_RA_SELF_TEST_A      0x10 //[5:4] XA_TEST[1-0], [3:2] YA_TEST[1-0], [1:0] ZA_TEST[1-0]\n#define MPU6050_RA_XG_OFFS_USRH     0x13 //[15:0] XG_OFFS_USR\n#define MPU6050_RA_XG_OFFS_USRL     0x14\n#define MPU6050_RA_YG_OFFS_USRH     0x15 //[15:0] YG_OFFS_USR\n#define MPU6050_RA_YG_OFFS_USRL     0x16\n#define MPU6050_RA_ZG_OFFS_USRH     0x17 //[15:0] ZG_OFFS_USR\n#define MPU6050_RA_ZG_OFFS_USRL     0x18\n#define MPU6050_RA_SMPLRT_DIV       0x19\n#define MPU6050_RA_CONFIG           0x1A\n#define MPU6050_RA_GYRO_CONFIG      0x1B\n#define MPU6050_RA_ACCEL_CONFIG     0x1C\n#define MPU6050_RA_FF_THR           0x1D\n#define MPU6050_RA_FF_DUR           0x1E\n#define MPU6050_RA_MOT_THR          0x1F\n#define MPU6050_RA_MOT_DUR          0x20\n#define MPU6050_RA_ZRMOT_THR        0x21\n#define MPU6050_RA_ZRMOT_DUR        0x22\n#define MPU6050_RA_FIFO_EN          0x23\n#define MPU6050_RA_I2C_MST_CTRL     0x24\n#define MPU6050_RA_I2C_SLV0_ADDR    0x25\n#define MPU6050_RA_I2C_SLV0_REG     0x26\n#define MPU6050_RA_I2C_SLV0_CTRL    0x27\n#define MPU6050_RA_I2C_SLV1_ADDR    0x28\n#define MPU6050_RA_I2C_SLV1_REG     0x29\n#define MPU6050_RA_I2C_SLV1_CTRL    0x2A\n#define MPU6050_RA_I2C_SLV2_ADDR    0x2B\n#define MPU6050_RA_I2C_SLV2_REG     0x2C\n#define MPU6050_RA_I2C_SLV2_CTRL    0x2D\n#define MPU6050_RA_I2C_SLV3_ADDR    0x2E\n#define MPU6050_RA_I2C_SLV3_REG     0x2F\n#define MPU6050_RA_I2C_SLV3_CTRL    0x30\n#define MPU6050_RA_I2C_SLV4_ADDR    0x31\n#define MPU6050_RA_I2C_SLV4_REG     0x32\n#define MPU6050_RA_I2C_SLV4_DO      0x33\n#define MPU6050_RA_I2C_SLV4_CTRL    0x34\n#define MPU6050_RA_I2C_SLV4_DI      0x35\n#define MPU6050_RA_I2C_MST_STATUS   0x36\n#define MPU6050_RA_INT_PIN_CFG      0x37\n#define MPU6050_RA_INT_ENABLE       0x38\n#define MPU6050_RA_DMP_INT_STATUS   0x39\n#define MPU6050_RA_INT_STATUS       0x3A\n#define MPU6050_RA_ACCEL_XOUT_H     0x3B\n#define MPU6050_RA_ACCEL_XOUT_L     0x3C\n#define MPU6050_RA_ACCEL_YOUT_H     0x3D\n#define MPU6050_RA_ACCEL_YOUT_L     0x3E\n#define MPU6050_RA_ACCEL_ZOUT_H     0x3F\n#define MPU6050_RA_ACCEL_ZOUT_L     0x40\n#define MPU6050_RA_TEMP_OUT_H       0x41\n#define MPU6050_RA_TEMP_OUT_L       0x42\n#define MPU6050_RA_GYRO_XOUT_H      0x43\n#define MPU6050_RA_GYRO_XOUT_L      0x44\n#define MPU6050_RA_GYRO_YOUT_H      0x45\n#define MPU6050_RA_GYRO_YOUT_L      0x46\n#define MPU6050_RA_GYRO_ZOUT_H      0x47\n#define MPU6050_RA_GYRO_ZOUT_L      0x48\n#define MPU6050_RA_EXT_SENS_DATA_00 0x49\n#define MPU6050_RA_EXT_SENS_DATA_01 0x4A\n#define MPU6050_RA_EXT_SENS_DATA_02 0x4B\n#define MPU6050_RA_EXT_SENS_DATA_03 0x4C\n#define MPU6050_RA_EXT_SENS_DATA_04 0x4D\n#define MPU6050_RA_EXT_SENS_DATA_05 0x4E\n#define MPU6050_RA_EXT_SENS_DATA_06 0x4F\n#define MPU6050_RA_EXT_SENS_DATA_07 0x50\n#define MPU6050_RA_EXT_SENS_DATA_08 0x51\n#define MPU6050_RA_EXT_SENS_DATA_09 0x52\n#define MPU6050_RA_EXT_SENS_DATA_10 0x53\n#define MPU6050_RA_EXT_SENS_DATA_11 0x54\n#define MPU6050_RA_EXT_SENS_DATA_12 0x55\n#define MPU6050_RA_EXT_SENS_DATA_13 0x56\n#define MPU6050_RA_EXT_SENS_DATA_14 0x57\n#define MPU6050_RA_EXT_SENS_DATA_15 0x58\n#define MPU6050_RA_EXT_SENS_DATA_16 0x59\n#define MPU6050_RA_EXT_SENS_DATA_17 0x5A\n#define MPU6050_RA_EXT_SENS_DATA_18 0x5B\n#define MPU6050_RA_EXT_SENS_DATA_19 0x5C\n#define MPU6050_RA_EXT_SENS_DATA_20 0x5D\n#define MPU6050_RA_EXT_SENS_DATA_21 0x5E\n#define MPU6050_RA_EXT_SENS_DATA_22 0x5F\n#define MPU6050_RA_EXT_SENS_DATA_23 0x60\n#define MPU6050_RA_MOT_DETECT_STATUS    0x61\n#define MPU6050_RA_I2C_SLV0_DO      0x63\n#define MPU6050_RA_I2C_SLV1_DO      0x64\n#define MPU6050_RA_I2C_SLV2_DO      0x65\n#define MPU6050_RA_I2C_SLV3_DO      0x66\n#define MPU6050_RA_I2C_MST_DELAY_CTRL   0x67\n#define MPU6050_RA_SIGNAL_PATH_RESET    0x68\n#define MPU6050_RA_MOT_DETECT_CTRL      0x69\n#define MPU6050_RA_USER_CTRL        0x6A\n#define MPU6050_RA_PWR_MGMT_1       0x6B\n#define MPU6050_RA_PWR_MGMT_2       0x6C\n#define MPU6050_RA_BANK_SEL         0x6D\n#define MPU6050_RA_MEM_START_ADDR   0x6E\n#define MPU6050_RA_MEM_R_W          0x6F\n#define MPU6050_RA_DMP_CFG_1        0x70\n#define MPU6050_RA_DMP_CFG_2        0x71\n#define MPU6050_RA_FIFO_COUNTH      0x72\n#define MPU6050_RA_FIFO_COUNTL      0x73\n#define MPU6050_RA_FIFO_R_W         0x74\n#define MPU6050_RA_WHO_AM_I         0x75\n\n#define MPU6050_SELF_TEST_XA_1_BIT     0x07\n#define MPU6050_SELF_TEST_XA_1_LENGTH  0x03\n#define MPU6050_SELF_TEST_XA_2_BIT     0x05\n#define MPU6050_SELF_TEST_XA_2_LENGTH  0x02\n#define MPU6050_SELF_TEST_YA_1_BIT     0x07\n#define MPU6050_SELF_TEST_YA_1_LENGTH  0x03\n#define MPU6050_SELF_TEST_YA_2_BIT     0x03\n#define MPU6050_SELF_TEST_YA_2_LENGTH  0x02\n#define MPU6050_SELF_TEST_ZA_1_BIT     0x07\n#define MPU6050_SELF_TEST_ZA_1_LENGTH  0x03\n#define MPU6050_SELF_TEST_ZA_2_BIT     0x01\n#define MPU6050_SELF_TEST_ZA_2_LENGTH  0x02\n\n#define MPU6050_SELF_TEST_XG_1_BIT     0x04\n#define MPU6050_SELF_TEST_XG_1_LENGTH  0x05\n#define MPU6050_SELF_TEST_YG_1_BIT     0x04\n#define MPU6050_SELF_TEST_YG_1_LENGTH  0x05\n#define MPU6050_SELF_TEST_ZG_1_BIT     0x04\n#define MPU6050_SELF_TEST_ZG_1_LENGTH  0x05\n\n#define MPU6050_TC_PWR_MODE_BIT     7\n#define MPU6050_TC_OFFSET_BIT       6\n#define MPU6050_TC_OFFSET_LENGTH    6\n#define MPU6050_TC_OTP_BNK_VLD_BIT  0\n\n#define MPU6050_VDDIO_LEVEL_VLOGIC  0\n#define MPU6050_VDDIO_LEVEL_VDD     1\n\n#define MPU6050_CFG_EXT_SYNC_SET_BIT    5\n#define MPU6050_CFG_EXT_SYNC_SET_LENGTH 3\n#define MPU6050_CFG_DLPF_CFG_BIT    2\n#define MPU6050_CFG_DLPF_CFG_LENGTH 3\n\n#define MPU6050_EXT_SYNC_DISABLED       0x0\n#define MPU6050_EXT_SYNC_TEMP_OUT_L     0x1\n#define MPU6050_EXT_SYNC_GYRO_XOUT_L    0x2\n#define MPU6050_EXT_SYNC_GYRO_YOUT_L    0x3\n#define MPU6050_EXT_SYNC_GYRO_ZOUT_L    0x4\n#define MPU6050_EXT_SYNC_ACCEL_XOUT_L   0x5\n#define MPU6050_EXT_SYNC_ACCEL_YOUT_L   0x6\n#define MPU6050_EXT_SYNC_ACCEL_ZOUT_L   0x7\n\n#define MPU6050_DLPF_BW_256         0x00\n#define MPU6050_DLPF_BW_188         0x01\n#define MPU6050_DLPF_BW_98          0x02\n#define MPU6050_DLPF_BW_42          0x03\n#define MPU6050_DLPF_BW_20          0x04\n#define MPU6050_DLPF_BW_10          0x05\n#define MPU6050_DLPF_BW_5           0x06\n\n#define MPU6050_GCONFIG_FS_SEL_BIT      4\n#define MPU6050_GCONFIG_FS_SEL_LENGTH   2\n\n#define MPU6050_GYRO_FS_250         0x00\n#define MPU6050_GYRO_FS_500         0x01\n#define MPU6050_GYRO_FS_1000        0x02\n#define MPU6050_GYRO_FS_2000        0x03\n\n#define MPU6050_ACONFIG_XA_ST_BIT           7\n#define MPU6050_ACONFIG_YA_ST_BIT           6\n#define MPU6050_ACONFIG_ZA_ST_BIT           5\n#define MPU6050_ACONFIG_AFS_SEL_BIT         4\n#define MPU6050_ACONFIG_AFS_SEL_LENGTH      2\n#define MPU6050_ACONFIG_ACCEL_HPF_BIT       2\n#define MPU6050_ACONFIG_ACCEL_HPF_LENGTH    3\n\n#define MPU6050_ACCEL_FS_2          0x00\n#define MPU6050_ACCEL_FS_4          0x01\n#define MPU6050_ACCEL_FS_8          0x02\n#define MPU6050_ACCEL_FS_16         0x03\n\n#define MPU6050_DHPF_RESET          0x00\n#define MPU6050_DHPF_5              0x01\n#define MPU6050_DHPF_2P5            0x02\n#define MPU6050_DHPF_1P25           0x03\n#define MPU6050_DHPF_0P63           0x04\n#define MPU6050_DHPF_HOLD           0x07\n\n#define MPU6050_TEMP_FIFO_EN_BIT    7\n#define MPU6050_XG_FIFO_EN_BIT      6\n#define MPU6050_YG_FIFO_EN_BIT      5\n#define MPU6050_ZG_FIFO_EN_BIT      4\n#define MPU6050_ACCEL_FIFO_EN_BIT   3\n#define MPU6050_SLV2_FIFO_EN_BIT    2\n#define MPU6050_SLV1_FIFO_EN_BIT    1\n#define MPU6050_SLV0_FIFO_EN_BIT    0\n\n#define MPU6050_MULT_MST_EN_BIT     7\n#define MPU6050_WAIT_FOR_ES_BIT     6\n#define MPU6050_SLV_3_FIFO_EN_BIT   5\n#define MPU6050_I2C_MST_P_NSR_BIT   4\n#define MPU6050_I2C_MST_CLK_BIT     3\n#define MPU6050_I2C_MST_CLK_LENGTH  4\n\n#define MPU6050_CLOCK_DIV_348       0x0\n#define MPU6050_CLOCK_DIV_333       0x1\n#define MPU6050_CLOCK_DIV_320       0x2\n#define MPU6050_CLOCK_DIV_308       0x3\n#define MPU6050_CLOCK_DIV_296       0x4\n#define MPU6050_CLOCK_DIV_286       0x5\n#define MPU6050_CLOCK_DIV_276       0x6\n#define MPU6050_CLOCK_DIV_267       0x7\n#define MPU6050_CLOCK_DIV_258       0x8\n#define MPU6050_CLOCK_DIV_500       0x9\n#define MPU6050_CLOCK_DIV_471       0xA\n#define MPU6050_CLOCK_DIV_444       0xB\n#define MPU6050_CLOCK_DIV_421       0xC\n#define MPU6050_CLOCK_DIV_400       0xD\n#define MPU6050_CLOCK_DIV_381       0xE\n#define MPU6050_CLOCK_DIV_364       0xF\n\n#define MPU6050_I2C_SLV_RW_BIT      7\n#define MPU6050_I2C_SLV_ADDR_BIT    6\n#define MPU6050_I2C_SLV_ADDR_LENGTH 7\n#define MPU6050_I2C_SLV_EN_BIT      7\n#define MPU6050_I2C_SLV_BYTE_SW_BIT 6\n#define MPU6050_I2C_SLV_REG_DIS_BIT 5\n#define MPU6050_I2C_SLV_GRP_BIT     4\n#define MPU6050_I2C_SLV_LEN_BIT     3\n#define MPU6050_I2C_SLV_LEN_LENGTH  4\n\n#define MPU6050_I2C_SLV4_RW_BIT         7\n#define MPU6050_I2C_SLV4_ADDR_BIT       6\n#define MPU6050_I2C_SLV4_ADDR_LENGTH    7\n#define MPU6050_I2C_SLV4_EN_BIT         7\n#define MPU6050_I2C_SLV4_INT_EN_BIT     6\n#define MPU6050_I2C_SLV4_REG_DIS_BIT    5\n#define MPU6050_I2C_SLV4_MST_DLY_BIT    4\n#define MPU6050_I2C_SLV4_MST_DLY_LENGTH 5\n\n#define MPU6050_MST_PASS_THROUGH_BIT    7\n#define MPU6050_MST_I2C_SLV4_DONE_BIT   6\n#define MPU6050_MST_I2C_LOST_ARB_BIT    5\n#define MPU6050_MST_I2C_SLV4_NACK_BIT   4\n#define MPU6050_MST_I2C_SLV3_NACK_BIT   3\n#define MPU6050_MST_I2C_SLV2_NACK_BIT   2\n#define MPU6050_MST_I2C_SLV1_NACK_BIT   1\n#define MPU6050_MST_I2C_SLV0_NACK_BIT   0\n\n#define MPU6050_INTCFG_INT_LEVEL_BIT        7\n#define MPU6050_INTCFG_INT_OPEN_BIT         6\n#define MPU6050_INTCFG_LATCH_INT_EN_BIT     5\n#define MPU6050_INTCFG_INT_RD_CLEAR_BIT     4\n#define MPU6050_INTCFG_FSYNC_INT_LEVEL_BIT  3\n#define MPU6050_INTCFG_FSYNC_INT_EN_BIT     2\n#define MPU6050_INTCFG_I2C_BYPASS_EN_BIT    1\n#define MPU6050_INTCFG_CLKOUT_EN_BIT        0\n\n#define MPU6050_INTMODE_ACTIVEHIGH  0x00\n#define MPU6050_INTMODE_ACTIVELOW   0x01\n\n#define MPU6050_INTDRV_PUSHPULL     0x00\n#define MPU6050_INTDRV_OPENDRAIN    0x01\n\n#define MPU6050_INTLATCH_50USPULSE  0x00\n#define MPU6050_INTLATCH_WAITCLEAR  0x01\n\n#define MPU6050_INTCLEAR_STATUSREAD 0x00\n#define MPU6050_INTCLEAR_ANYREAD    0x01\n\n#define MPU6050_INTERRUPT_FF_BIT            7\n#define MPU6050_INTERRUPT_MOT_BIT           6\n#define MPU6050_INTERRUPT_ZMOT_BIT          5\n#define MPU6050_INTERRUPT_FIFO_OFLOW_BIT    4\n#define MPU6050_INTERRUPT_I2C_MST_INT_BIT   3\n#define MPU6050_INTERRUPT_PLL_RDY_INT_BIT   2\n#define MPU6050_INTERRUPT_DMP_INT_BIT       1\n#define MPU6050_INTERRUPT_DATA_RDY_BIT      0\n\n// TODO: figure out what these actually do\n// UMPL source code is not very obivous\n#define MPU6050_DMPINT_5_BIT            5\n#define MPU6050_DMPINT_4_BIT            4\n#define MPU6050_DMPINT_3_BIT            3\n#define MPU6050_DMPINT_2_BIT            2\n#define MPU6050_DMPINT_1_BIT            1\n#define MPU6050_DMPINT_0_BIT            0\n\n#define MPU6050_MOTION_MOT_XNEG_BIT     7\n#define MPU6050_MOTION_MOT_XPOS_BIT     6\n#define MPU6050_MOTION_MOT_YNEG_BIT     5\n#define MPU6050_MOTION_MOT_YPOS_BIT     4\n#define MPU6050_MOTION_MOT_ZNEG_BIT     3\n#define MPU6050_MOTION_MOT_ZPOS_BIT     2\n#define MPU6050_MOTION_MOT_ZRMOT_BIT    0\n\n#define MPU6050_DELAYCTRL_DELAY_ES_SHADOW_BIT   7\n#define MPU6050_DELAYCTRL_I2C_SLV4_DLY_EN_BIT   4\n#define MPU6050_DELAYCTRL_I2C_SLV3_DLY_EN_BIT   3\n#define MPU6050_DELAYCTRL_I2C_SLV2_DLY_EN_BIT   2\n#define MPU6050_DELAYCTRL_I2C_SLV1_DLY_EN_BIT   1\n#define MPU6050_DELAYCTRL_I2C_SLV0_DLY_EN_BIT   0\n\n#define MPU6050_PATHRESET_GYRO_RESET_BIT    2\n#define MPU6050_PATHRESET_ACCEL_RESET_BIT   1\n#define MPU6050_PATHRESET_TEMP_RESET_BIT    0\n\n#define MPU6050_DETECT_ACCEL_ON_DELAY_BIT       5\n#define MPU6050_DETECT_ACCEL_ON_DELAY_LENGTH    2\n#define MPU6050_DETECT_FF_COUNT_BIT             3\n#define MPU6050_DETECT_FF_COUNT_LENGTH          2\n#define MPU6050_DETECT_MOT_COUNT_BIT            1\n#define MPU6050_DETECT_MOT_COUNT_LENGTH         2\n\n#define MPU6050_DETECT_DECREMENT_RESET  0x0\n#define MPU6050_DETECT_DECREMENT_1      0x1\n#define MPU6050_DETECT_DECREMENT_2      0x2\n#define MPU6050_DETECT_DECREMENT_4      0x3\n\n#define MPU6050_USERCTRL_DMP_EN_BIT             7\n#define MPU6050_USERCTRL_FIFO_EN_BIT            6\n#define MPU6050_USERCTRL_I2C_MST_EN_BIT         5\n#define MPU6050_USERCTRL_I2C_IF_DIS_BIT         4\n#define MPU6050_USERCTRL_DMP_RESET_BIT          3\n#define MPU6050_USERCTRL_FIFO_RESET_BIT         2\n#define MPU6050_USERCTRL_I2C_MST_RESET_BIT      1\n#define MPU6050_USERCTRL_SIG_COND_RESET_BIT     0\n\n#define MPU6050_PWR1_DEVICE_RESET_BIT   7\n#define MPU6050_PWR1_SLEEP_BIT          6\n#define MPU6050_PWR1_CYCLE_BIT          5\n#define MPU6050_PWR1_TEMP_DIS_BIT       3\n#define MPU6050_PWR1_CLKSEL_BIT         2\n#define MPU6050_PWR1_CLKSEL_LENGTH      3\n\n#define MPU6050_CLOCK_INTERNAL          0x00\n#define MPU6050_CLOCK_PLL_XGYRO         0x01\n#define MPU6050_CLOCK_PLL_YGYRO         0x02\n#define MPU6050_CLOCK_PLL_ZGYRO         0x03\n#define MPU6050_CLOCK_PLL_EXT32K        0x04\n#define MPU6050_CLOCK_PLL_EXT19M        0x05\n#define MPU6050_CLOCK_KEEP_RESET        0x07\n\n#define MPU6050_PWR2_LP_WAKE_CTRL_BIT       7\n#define MPU6050_PWR2_LP_WAKE_CTRL_LENGTH    2\n#define MPU6050_PWR2_STBY_XA_BIT            5\n#define MPU6050_PWR2_STBY_YA_BIT            4\n#define MPU6050_PWR2_STBY_ZA_BIT            3\n#define MPU6050_PWR2_STBY_XG_BIT            2\n#define MPU6050_PWR2_STBY_YG_BIT            1\n#define MPU6050_PWR2_STBY_ZG_BIT            0\n\n#define MPU6050_WAKE_FREQ_1P25      0x0\n#define MPU6050_WAKE_FREQ_2P5       0x1\n#define MPU6050_WAKE_FREQ_5         0x2\n#define MPU6050_WAKE_FREQ_10        0x3\n\n#define MPU6050_BANKSEL_PRFTCH_EN_BIT       6\n#define MPU6050_BANKSEL_CFG_USER_BANK_BIT   5\n#define MPU6050_BANKSEL_MEM_SEL_BIT         4\n#define MPU6050_BANKSEL_MEM_SEL_LENGTH      5\n\n#define MPU6050_WHO_AM_I_BIT        6\n#define MPU6050_WHO_AM_I_LENGTH     6\n\n#define MPU6050_DMP_MEMORY_BANKS        8\n#define MPU6050_DMP_MEMORY_BANK_SIZE    256\n#define MPU6050_DMP_MEMORY_CHUNK_SIZE   16\n\n// note: DMP code memory blocks defined at end of header file\n\nclass MPU6050\n{\nprivate:\n    I2C_HandleTypeDef *hi2c;\n\n    // Filters\n    BiquadFilter_t gyroFilterLPF[3];\n    BiquadFilter_t accFilterLPF[3];\n\n    float gyroRangeScale;\n    float accRangeScale;\n\npublic:\n    struct ImuDataRaw_t\n    {\n        int16_t ax;\n        int16_t ay;\n        int16_t az;\n        int16_t gx;\n        int16_t gy;\n        int16_t gz;\n    } dataRaw;\n\n    struct ImuData_t\n    {\n        float ax;\n        float ay;\n        float az;\n        float gx;\n        float gy;\n        float gz;\n    } data;\n\n    explicit MPU6050(I2C_HandleTypeDef *_hi2c, uint8_t address = MPU6050_DEFAULT_ADDRESS);\n\n    void Init();\n    bool testConnection();\n\n    void InitFilter(float _imuUpdateRate = 200,\n                    float _gyroFilterCutoffFreq = 100,\n                    float _accFilterCutoffFreq = 50);\n\n    // AUX_VDDIO register\n    uint8_t getAuxVDDIOLevel();\n    void setAuxVDDIOLevel(uint8_t level);\n\n    // SMPLRT_DIV register\n    uint8_t getRate();\n    void setRate(uint8_t rate);\n\n    // CONFIG register\n    uint8_t getExternalFrameSync();\n    void setExternalFrameSync(uint8_t sync);\n    uint8_t getDLPFMode();\n    void setDLPFMode(uint8_t bandwidth);\n\n    // GYRO_CONFIG register\n    uint8_t getFullScaleGyroRange();\n    void setFullScaleGyroRange(uint8_t range);\n\n    // SELF_TEST registers\n    uint8_t getAccelXSelfTestFactoryTrim();\n    uint8_t getAccelYSelfTestFactoryTrim();\n    uint8_t getAccelZSelfTestFactoryTrim();\n\n    uint8_t getGyroXSelfTestFactoryTrim();\n    uint8_t getGyroYSelfTestFactoryTrim();\n    uint8_t getGyroZSelfTestFactoryTrim();\n\n    // ACCEL_CONFIG register\n    bool getAccelXSelfTest();\n    void setAccelXSelfTest(bool enabled);\n    bool getAccelYSelfTest();\n    void setAccelYSelfTest(bool enabled);\n    bool getAccelZSelfTest();\n    void setAccelZSelfTest(bool enabled);\n    uint8_t getFullScaleAccelRange();\n    void setFullScaleAccelRange(uint8_t range);\n    uint8_t getDHPFMode();\n    void setDHPFMode(uint8_t mode);\n\n    // FF_THR register\n    uint8_t getFreefallDetectionThreshold();\n    void setFreefallDetectionThreshold(uint8_t threshold);\n\n    // FF_DUR register\n    uint8_t getFreefallDetectionDuration();\n    void setFreefallDetectionDuration(uint8_t duration);\n\n    // MOT_THR register\n    uint8_t getMotionDetectionThreshold();\n    void setMotionDetectionThreshold(uint8_t threshold);\n\n    // MOT_DUR register\n    uint8_t getMotionDetectionDuration();\n    void setMotionDetectionDuration(uint8_t duration);\n\n    // ZRMOT_THR register\n    uint8_t getZeroMotionDetectionThreshold();\n    void setZeroMotionDetectionThreshold(uint8_t threshold);\n\n    // ZRMOT_DUR register\n    uint8_t getZeroMotionDetectionDuration();\n    void setZeroMotionDetectionDuration(uint8_t duration);\n\n    // FIFO_EN register\n    bool getTempFIFOEnabled();\n    void setTempFIFOEnabled(bool enabled);\n    bool getXGyroFIFOEnabled();\n    void setXGyroFIFOEnabled(bool enabled);\n    bool getYGyroFIFOEnabled();\n    void setYGyroFIFOEnabled(bool enabled);\n    bool getZGyroFIFOEnabled();\n    void setZGyroFIFOEnabled(bool enabled);\n    bool getAccelFIFOEnabled();\n    void setAccelFIFOEnabled(bool enabled);\n    bool getSlave2FIFOEnabled();\n    void setSlave2FIFOEnabled(bool enabled);\n    bool getSlave1FIFOEnabled();\n    void setSlave1FIFOEnabled(bool enabled);\n    bool getSlave0FIFOEnabled();\n    void setSlave0FIFOEnabled(bool enabled);\n\n    // I2C_MST_CTRL register\n    bool getMultiMasterEnabled();\n    void setMultiMasterEnabled(bool enabled);\n    bool getWaitForExternalSensorEnabled();\n    void setWaitForExternalSensorEnabled(bool enabled);\n    bool getSlave3FIFOEnabled();\n    void setSlave3FIFOEnabled(bool enabled);\n    bool getSlaveReadWriteTransitionEnabled();\n    void setSlaveReadWriteTransitionEnabled(bool enabled);\n    uint8_t getMasterClockSpeed();\n    void setMasterClockSpeed(uint8_t speed);\n\n    // I2C_SLV* registers (Slave 0-3)\n    uint8_t getSlaveAddress(uint8_t num);\n    void setSlaveAddress(uint8_t num, uint8_t address);\n    uint8_t getSlaveRegister(uint8_t num);\n    void setSlaveRegister(uint8_t num, uint8_t reg);\n    bool getSlaveEnabled(uint8_t num);\n    void setSlaveEnabled(uint8_t num, bool enabled);\n    bool getSlaveWordByteSwap(uint8_t num);\n    void setSlaveWordByteSwap(uint8_t num, bool enabled);\n    bool getSlaveWriteMode(uint8_t num);\n    void setSlaveWriteMode(uint8_t num, bool mode);\n    bool getSlaveWordGroupOffset(uint8_t num);\n    void setSlaveWordGroupOffset(uint8_t num, bool enabled);\n    uint8_t getSlaveDataLength(uint8_t num);\n    void setSlaveDataLength(uint8_t num, uint8_t length);\n\n    // I2C_SLV* registers (Slave 4)\n    uint8_t getSlave4Address();\n    void setSlave4Address(uint8_t address);\n    uint8_t getSlave4Register();\n    void setSlave4Register(uint8_t reg);\n    void setSlave4OutputByte(uint8_t data);\n    bool getSlave4Enabled();\n    void setSlave4Enabled(bool enabled);\n    bool getSlave4InterruptEnabled();\n    void setSlave4InterruptEnabled(bool enabled);\n    bool getSlave4WriteMode();\n    void setSlave4WriteMode(bool mode);\n    uint8_t getSlave4MasterDelay();\n    void setSlave4MasterDelay(uint8_t delay);\n    uint8_t getSlate4InputByte();\n\n    // I2C_MST_STATUS register\n    bool getPassthroughStatus();\n    bool getSlave4IsDone();\n    bool getLostArbitration();\n    bool getSlave4Nack();\n    bool getSlave3Nack();\n    bool getSlave2Nack();\n    bool getSlave1Nack();\n    bool getSlave0Nack();\n\n    // INT_PIN_CFG register\n    bool getInterruptMode();\n    void setInterruptMode(bool mode);\n    bool getInterruptDrive();\n    void setInterruptDrive(bool drive);\n    bool getInterruptLatch();\n    void setInterruptLatch(bool latch);\n    bool getInterruptLatchClear();\n    void setInterruptLatchClear(bool clear);\n    bool getFSyncInterruptLevel();\n    void setFSyncInterruptLevel(bool level);\n    bool getFSyncInterruptEnabled();\n    void setFSyncInterruptEnabled(bool enabled);\n    bool getI2CBypassEnabled();\n    void setI2CBypassEnabled(bool enabled);\n    bool getClockOutputEnabled();\n    void setClockOutputEnabled(bool enabled);\n\n    // INT_ENABLE register\n    uint8_t getIntEnabled();\n    void setIntEnabled(uint8_t enabled);\n    bool getIntFreefallEnabled();\n    void setIntFreefallEnabled(bool enabled);\n    bool getIntMotionEnabled();\n    void setIntMotionEnabled(bool enabled);\n    bool getIntZeroMotionEnabled();\n    void setIntZeroMotionEnabled(bool enabled);\n    bool getIntFIFOBufferOverflowEnabled();\n    void setIntFIFOBufferOverflowEnabled(bool enabled);\n    bool getIntI2CMasterEnabled();\n    void setIntI2CMasterEnabled(bool enabled);\n    bool getIntDataReadyEnabled();\n    void setIntDataReadyEnabled(bool enabled);\n\n    // INT_STATUS register\n    uint8_t getIntStatus();\n    bool getIntFreefallStatus();\n    bool getIntMotionStatus();\n    bool getIntZeroMotionStatus();\n    bool getIntFIFOBufferOverflowStatus();\n    bool getIntI2CMasterStatus();\n    bool getIntDataReadyStatus();\n\n    // ACCEL_*OUT_* registers\n    void\n    getMotion9(int16_t *ax, int16_t *ay, int16_t *az, int16_t *gx, int16_t *gy, int16_t *gz, int16_t *mx, int16_t *my,\n               int16_t *mz);\n    void getMotion6(int16_t *ax, int16_t *ay, int16_t *az, int16_t *gx, int16_t *gy, int16_t *gz);\n    void Update(bool _useFilter = false);\n    void getAcceleration(int16_t *x, int16_t *y, int16_t *z);\n    int16_t getAccelerationX();\n    int16_t getAccelerationY();\n    int16_t getAccelerationZ();\n\n    // TEMP_OUT_* registers\n    int16_t getTemperature();\n\n    // GYRO_*OUT_* registers\n    void getRotation(int16_t *x, int16_t *y, int16_t *z);\n    int16_t getRotationX();\n    int16_t getRotationY();\n    int16_t getRotationZ();\n\n    // EXT_SENS_DATA_* registers\n    uint8_t getExternalSensorByte(int position);\n    uint16_t getExternalSensorWord(int position);\n    uint32_t getExternalSensorDWord(int position);\n\n    // MOT_DETECT_STATUS register\n    uint8_t getMotionStatus();\n    bool getXNegMotionDetected();\n    bool getXPosMotionDetected();\n    bool getYNegMotionDetected();\n    bool getYPosMotionDetected();\n    bool getZNegMotionDetected();\n    bool getZPosMotionDetected();\n    bool getZeroMotionDetected();\n\n    // I2C_SLV*_DO register\n    void setSlaveOutputByte(uint8_t num, uint8_t data);\n\n    // I2C_MST_DELAY_CTRL register\n    bool getExternalShadowDelayEnabled();\n    void setExternalShadowDelayEnabled(bool enabled);\n    bool getSlaveDelayEnabled(uint8_t num);\n    void setSlaveDelayEnabled(uint8_t num, bool enabled);\n\n    // SIGNAL_PATH_RESET register\n    void resetGyroscopePath();\n    void resetAccelerometerPath();\n    void resetTemperaturePath();\n\n    // MOT_DETECT_CTRL register\n    uint8_t getAccelerometerPowerOnDelay();\n    void setAccelerometerPowerOnDelay(uint8_t delay);\n    uint8_t getFreefallDetectionCounterDecrement();\n    void setFreefallDetectionCounterDecrement(uint8_t decrement);\n    uint8_t getMotionDetectionCounterDecrement();\n    void setMotionDetectionCounterDecrement(uint8_t decrement);\n\n    // USER_CTRL register\n    bool getFIFOEnabled();\n    void setFIFOEnabled(bool enabled);\n    bool getI2CMasterModeEnabled();\n    void setI2CMasterModeEnabled(bool enabled);\n    void switchSPIEnabled(bool enabled);\n    void resetFIFO();\n    void resetI2CMaster();\n    void resetSensors();\n\n    // PWR_MGMT_1 register\n    void reset();\n    bool getSleepEnabled();\n    void setSleepEnabled(bool enabled);\n    bool getWakeCycleEnabled();\n    void setWakeCycleEnabled(bool enabled);\n    bool getTempSensorEnabled();\n    void setTempSensorEnabled(bool enabled);\n    uint8_t getClockSource();\n    void setClockSource(uint8_t source);\n\n    // PWR_MGMT_2 register\n    uint8_t getWakeFrequency();\n    void setWakeFrequency(uint8_t frequency);\n    bool getStandbyXAccelEnabled();\n    void setStandbyXAccelEnabled(bool enabled);\n    bool getStandbyYAccelEnabled();\n    void setStandbyYAccelEnabled(bool enabled);\n    bool getStandbyZAccelEnabled();\n    void setStandbyZAccelEnabled(bool enabled);\n    bool getStandbyXGyroEnabled();\n    void setStandbyXGyroEnabled(bool enabled);\n    bool getStandbyYGyroEnabled();\n    void setStandbyYGyroEnabled(bool enabled);\n    bool getStandbyZGyroEnabled();\n    void setStandbyZGyroEnabled(bool enabled);\n\n    // FIFO_COUNT_* registers\n    uint16_t getFIFOCount();\n\n    // FIFO_R_W register\n    uint8_t getFIFOByte();\n    void setFIFOByte(uint8_t data);\n    void getFIFOBytes(uint8_t *data, uint8_t length);\n\n    // WHO_AM_I register\n    uint8_t getDeviceID();\n    void setDeviceID(uint8_t id);\n\n    // ======== UNDOCUMENTED/DMP REGISTERS/METHODS ========\n\n    // XG_OFFS_TC register\n    uint8_t getOTPBankValid();\n    void setOTPBankValid(bool enabled);\n    int8_t getXGyroOffsetTC();\n    void setXGyroOffsetTC(int8_t offset);\n\n    // YG_OFFS_TC register\n    int8_t getYGyroOffsetTC();\n    void setYGyroOffsetTC(int8_t offset);\n\n    // ZG_OFFS_TC register\n    int8_t getZGyroOffsetTC();\n    void setZGyroOffsetTC(int8_t offset);\n\n    // X_FINE_GAIN register\n    int8_t getXFineGain();\n    void setXFineGain(int8_t gain);\n\n    // Y_FINE_GAIN register\n    int8_t getYFineGain();\n    void setYFineGain(int8_t gain);\n\n    // Z_FINE_GAIN register\n    int8_t getZFineGain();\n    void setZFineGain(int8_t gain);\n\n    // XA_OFFS_* registers\n    int16_t getXAccelOffset();\n    void setXAccelOffset(int16_t offset);\n\n    // YA_OFFS_* register\n    int16_t getYAccelOffset();\n    void setYAccelOffset(int16_t offset);\n\n    // ZA_OFFS_* register\n    int16_t getZAccelOffset();\n    void setZAccelOffset(int16_t offset);\n\n    // XG_OFFS_USR* registers\n    int16_t getXGyroOffset();\n    void setXGyroOffset(int16_t offset);\n\n    // YG_OFFS_USR* register\n    int16_t getYGyroOffset();\n    void setYGyroOffset(int16_t offset);\n\n    // ZG_OFFS_USR* register\n    int16_t getZGyroOffset();\n    void setZGyroOffset(int16_t offset);\n\n    // INT_ENABLE register (DMP functions)\n    bool getIntPLLReadyEnabled();\n    void setIntPLLReadyEnabled(bool enabled);\n    bool getIntDMPEnabled();\n    void setIntDMPEnabled(bool enabled);\n\n    // DMP_INT_STATUS\n    bool getDMPInt5Status();\n    bool getDMPInt4Status();\n    bool getDMPInt3Status();\n    bool getDMPInt2Status();\n    bool getDMPInt1Status();\n    bool getDMPInt0Status();\n\n    // INT_STATUS register (DMP functions)\n    bool getIntPLLReadyStatus();\n    bool getIntDMPStatus();\n\n    // USER_CTRL register (DMP functions)\n    bool getDMPEnabled();\n    void setDMPEnabled(bool enabled);\n    void resetDMP();\n\n    // BANK_SEL register\n    void setMemoryBank(uint8_t bank, bool prefetchEnabled = false, bool userBank = false);\n\n    // MEM_START_ADDR register\n    void setMemoryStartAddress(uint8_t address);\n\n    // MEM_R_W register\n    uint8_t readMemoryByte();\n    void writeMemoryByte(uint8_t data);\n    void readMemoryBlock(uint8_t *data, uint16_t dataSize, uint8_t bank = 0, uint8_t address = 0);\n    bool\n    writeMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank = 0, uint8_t address = 0, bool verify = true,\n                     bool useProgMem = false);\n    bool writeProgMemoryBlock(const uint8_t *data, uint16_t dataSize, uint8_t bank = 0, uint8_t address = 0,\n                              bool verify = true);\n\n    bool writeDMPConfigurationSet(const uint8_t *data, uint16_t dataSize, bool useProgMem = false);\n    bool writeProgDMPConfigurationSet(const uint8_t *data, uint16_t dataSize);\n\n    // DMP_CFG_1 register\n    uint8_t getDMPConfig1();\n    void setDMPConfig1(uint8_t config);\n\n    // DMP_CFG_2 register\n    uint8_t getDMPConfig2();\n    void setDMPConfig2(uint8_t config);\n\n    // special methods for MotionApps 2.0 implementation\n#ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS20\n\n    uint8_t dmpInitialize();\n            bool dmpPacketAvailable();\n\n            uint8_t dmpSetFIFORate(uint8_t fifoRate);\n            uint8_t dmpGetFIFORate();\n            uint8_t dmpGetSampleStepSizeMS();\n            uint8_t dmpGetSampleFrequency();\n            int32_t dmpDecodeTemperature(int8_t tempReg);\n            \n            // Register callbacks after a packet of FIFO data is processed\n            //uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);\n            //uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);\n            uint8_t dmpRunFIFORateProcesses();\n            \n            // Setup FIFO for various output\n            uint8_t dmpSendQuaternion(uint_fast16_t accuracy);\n            uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);\n            uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);\n\n            // Get Fixed Point data from FIFO\n            uint8_t dmpGetAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(Quaternion *q, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(Quaternion *q, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(Quaternion *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpSetLinearAccelFilterCoefficient(float coef);\n            uint8_t dmpGetLinearAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity);\n            uint8_t dmpGetLinearAccelInWorld(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q);\n            uint8_t dmpGetGyroAndAccelSensor(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroAndAccelSensor(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroAndAccelSensor(VectorInt16 *g, VectorInt16 *a, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetControlData(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetTemperature(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(VectorFloat *v, Quaternion *q);\n            uint8_t dmpGetUnquantizedAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetUnquantizedAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetUnquantizedAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetExternalSensorData(int32_t *data, uint16_t size, const uint8_t* packet=0);\n            uint8_t dmpGetEIS(int32_t *data, const uint8_t* packet=0);\n            \n            uint8_t dmpGetEuler(float *data, Quaternion *q);\n            uint8_t dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity);\n\n            // Get Floating Point data from FIFO\n            uint8_t dmpGetAccelFloat(float *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternionFloat(float *data, const uint8_t* packet=0);\n\n            uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);\n            uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);\n\n            uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));\n\n            uint8_t dmpInitFIFOParam();\n            uint8_t dmpCloseFIFO();\n            uint8_t dmpSetGyroDataSource(uint8_t source);\n            uint8_t dmpDecodeQuantizedAccel();\n            uint32_t dmpGetGyroSumOfSquare();\n            uint32_t dmpGetAccelSumOfSquare();\n            void dmpOverrideQuaternion(long *q);\n            uint16_t dmpGetFIFOPacketSize();\n#endif\n\n    // special methods for MotionApps 4.1 implementation\n#ifdef MPU6050_INCLUDE_DMP_MOTIONAPPS41\n\n    uint8_t dmpInitialize();\n            bool dmpPacketAvailable();\n\n            uint8_t dmpSetFIFORate(uint8_t fifoRate);\n            uint8_t dmpGetFIFORate();\n            uint8_t dmpGetSampleStepSizeMS();\n            uint8_t dmpGetSampleFrequency();\n            int32_t dmpDecodeTemperature(int8_t tempReg);\n            \n            // Register callbacks after a packet of FIFO data is processed\n            //uint8_t dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);\n            //uint8_t dmpUnregisterFIFORateProcess(inv_obj_func func);\n            uint8_t dmpRunFIFORateProcesses();\n            \n            // Setup FIFO for various output\n            uint8_t dmpSendQuaternion(uint_fast16_t accuracy);\n            uint8_t dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendPacketNumber(uint_fast16_t accuracy);\n            uint8_t dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n            uint8_t dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);\n\n            // Get Fixed Point data from FIFO\n            uint8_t dmpGetAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternion(Quaternion *q, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGet6AxisQuaternion(Quaternion *q, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetRelativeQuaternion(Quaternion *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyro(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetMag(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpSetLinearAccelFilterCoefficient(float coef);\n            uint8_t dmpGetLinearAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity);\n            uint8_t dmpGetLinearAccelInWorld(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q);\n            uint8_t dmpGetGyroAndAccelSensor(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroAndAccelSensor(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroAndAccelSensor(VectorInt16 *g, VectorInt16 *a, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGyroSensor(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetControlData(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetTemperature(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetGravity(VectorFloat *v, Quaternion *q);\n            uint8_t dmpGetUnquantizedAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetUnquantizedAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetUnquantizedAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(int32_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(int16_t *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuantizedAccel(VectorInt16 *v, const uint8_t* packet=0);\n            uint8_t dmpGetExternalSensorData(int32_t *data, uint16_t size, const uint8_t* packet=0);\n            uint8_t dmpGetEIS(int32_t *data, const uint8_t* packet=0);\n            \n            uint8_t dmpGetEuler(float *data, Quaternion *q);\n            uint8_t dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity);\n\n            // Get Floating Point data from FIFO\n            uint8_t dmpGetAccelFloat(float *data, const uint8_t* packet=0);\n            uint8_t dmpGetQuaternionFloat(float *data, const uint8_t* packet=0);\n\n            uint8_t dmpProcessFIFOPacket(const unsigned char *dmpData);\n            uint8_t dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed=NULL);\n\n            uint8_t dmpSetFIFOProcessedCallback(void (*func) (void));\n\n            uint8_t dmpInitFIFOParam();\n            uint8_t dmpCloseFIFO();\n            uint8_t dmpSetGyroDataSource(uint8_t source);\n            uint8_t dmpDecodeQuantizedAccel();\n            uint32_t dmpGetGyroSumOfSquare();\n            uint32_t dmpGetAccelSumOfSquare();\n            void dmpOverrideQuaternion(long *q);\n            uint16_t dmpGetFIFOPacketSize();\n#endif\n\nprivate:\n    uint8_t devAddr;\n    uint8_t buffer[14];\n#if defined(MPU6050_INCLUDE_DMP_MOTIONAPPS20) or defined(MPU6050_INCLUDE_DMP_MOTIONAPPS41)\n    uint8_t *dmpPacketBuffer;\n        uint16_t dmpPacketSize;\n#endif\n};\n\n#endif /* _MPU6050_H_ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/MPU6050_6Axis_MotionApps20.h",
    "content": "// I2Cdev library collection - MPU6050 I2C device class, 6-axis MotionApps 2.0 implementation\n// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)\n// 5/20/2013 by Jeff Rowberg <jeff@rowberg.net>\n// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib\n//\n// Changelog:\n//     ... - ongoing debug release\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2012 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#ifndef _MPU6050_6AXIS_MOTIONAPPS20_H_\n#define _MPU6050_6AXIS_MOTIONAPPS20_H_\n\n#include \"i2c_dev.hpp\"\n#include \"helper_3dmath.h\"\n\n// MotionApps 2.0 DMP implementation, built using the MPU-6050EVB evaluation board\n#define MPU6050_INCLUDE_DMP_MOTIONAPPS20\n\n#include \"mpu6050.hpp\"\n\n// Tom Carpenter's conditional PROGMEM code\n// http://forum.arduino.cc/index.php?topic=129407.0\n#ifdef __AVR__\n    #include <avr/pgmspace.h>\n#else\n    // Teensy 3.0 library conditional PROGMEM code from Paul Stoffregen\n    #ifndef __PGMSPACE_H_\n        #define __PGMSPACE_H_ 1\n        #include <inttypes.h>\n\n        #define PROGMEM\n        #define PGM_P  const char *\n        #define PSTR(str) (str)\n        #define F(x) x\n\n        //typedef void prog_void;\n        //typedef char prog_char;\n        //typedef unsigned char prog_uchar;\n        //typedef int8_t prog_int8_t;\n        //typedef uint8_t prog_uint8_t;\n        //typedef int16_t prog_int16_t;\n        //typedef uint16_t prog_uint16_t;\n        //typedef int32_t prog_int32_t;\n        //typedef uint32_t prog_uint32_t;\n        \n        #define strcpy_P(dest, src) strcpy((dest), (src))\n        #define strcat_P(dest, src) strcat((dest), (src))\n        #define strcmp_P(a, b) strcmp((a), (b))\n        \n        #define pgm_read_byte(addr) (*(const unsigned char *)(addr))\n        #define pgm_read_word(addr) (*(const unsigned short *)(addr))\n        #define pgm_read_dword(addr) (*(const unsigned long *)(addr))\n        #define pgm_read_float(addr) (*(const float *)(addr))\n        \n        #define pgm_read_byte_near(addr) pgm_read_byte(addr)\n        #define pgm_read_word_near(addr) pgm_read_word(addr)\n        #define pgm_read_dword_near(addr) pgm_read_dword(addr)\n        #define pgm_read_float_near(addr) pgm_read_float(addr)\n        #define pgm_read_byte_far(addr) pgm_read_byte(addr)\n        #define pgm_read_word_far(addr) pgm_read_word(addr)\n        #define pgm_read_dword_far(addr) pgm_read_dword(addr)\n        #define pgm_read_float_far(addr) pgm_read_float(addr)\n    #endif\n#endif\n\n/* Source is from the InvenSense MotionApps v2 demo code. Original source is\n * unavailable, unless you happen to be amazing as decompiling binary by\n * hand (in which case, please contact me, and I'm totally serious).\n *\n * Also, I'd like to offer many, many thanks to Noah Zerkin for all of the\n * DMP reverse-engineering he did to help make this bit of wizardry\n * possible.\n */\n\n// NOTE! Enabling DEBUG adds about 3.3kB to the flash program size.\n// Debug output is now working even on ATMega328P MCUs (e.g. Arduino Uno)\n// after moving string constants to flash memory storage using the F()\n// compiler macro (Arduino IDE 1.0+ required).\n\n//#define DEBUG\n#ifdef DEBUG\n    #define DEBUG_PRINT(x) Serial.print(x)\n    #define DEBUG_PRINTF(x, y) Serial.print(x, y)\n    #define DEBUG_PRINTLN(x) Serial.println(x)\n    #define DEBUG_PRINTLNF(x, y) Serial.println(x, y)\n#else\n    #define DEBUG_PRINT(x)\n    #define DEBUG_PRINTF(x, y)\n    #define DEBUG_PRINTLN(x)\n    #define DEBUG_PRINTLNF(x, y)\n#endif\n\n#define MPU6050_DMP_CODE_SIZE       1929    // dmpMemory[]\n#define MPU6050_DMP_CONFIG_SIZE     192     // dmpConfig[]\n#define MPU6050_DMP_UPDATES_SIZE    47      // dmpUpdates[]\n\n/* ================================================================================================ *\n | Default MotionApps v2.0 42-byte FIFO packet structure:                                           |\n |                                                                                                  |\n | [QUAT W][      ][QUAT X][      ][QUAT Y][      ][QUAT Z][      ][GYRO X][      ][GYRO Y][      ] |\n |   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  |\n |                                                                                                  |\n | [GYRO Z][      ][ACC X ][      ][ACC Y ][      ][ACC Z ][      ][      ]                         |\n |  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41                          |\n * ================================================================================================ */\n\n// this block of memory gets written to the MPU on start-up, and it seems\n// to be volatile memory, so it has to be done each time (it only takes ~1\n// second though)\nconst unsigned char dmpMemory[MPU6050_DMP_CODE_SIZE] PROGMEM = {\n    // bank 0, 256 bytes\n    0xFB, 0x00, 0x00, 0x3E, 0x00, 0x0B, 0x00, 0x36, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00,\n    0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0xFA, 0x80, 0x00, 0x0B, 0x12, 0x82, 0x00, 0x01,\n    0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x28, 0x00, 0x00, 0xFF, 0xFF, 0x45, 0x81, 0xFF, 0xFF, 0xFA, 0x72, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x03, 0xE8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x7F, 0xFF, 0xFF, 0xFE, 0x80, 0x01,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x3E, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xCA, 0xE3, 0x09, 0x3E, 0x80, 0x00, 0x00,\n    0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00,\n    0x41, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0x00, 0x00, 0x16, 0x55, 0x00, 0x00, 0x21, 0x82,\n    0xFD, 0x87, 0x26, 0x50, 0xFD, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x6F, 0x00, 0x02, 0x65, 0x32, 0x00, 0x00, 0x5E, 0xC0,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0xFB, 0x8C, 0x6F, 0x5D, 0xFD, 0x5D, 0x08, 0xD9, 0x00, 0x7C, 0x73, 0x3B, 0x00, 0x6C, 0x12, 0xCC,\n    0x32, 0x00, 0x13, 0x9D, 0x32, 0x00, 0xD0, 0xD6, 0x32, 0x00, 0x08, 0x00, 0x40, 0x00, 0x01, 0xF4,\n    0xFF, 0xE6, 0x80, 0x79, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0xD6, 0x00, 0x00, 0x27, 0x10,\n\n    // bank 1, 256 bytes\n    0xFB, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0xFA, 0x36, 0xFF, 0xBC, 0x30, 0x8E, 0x00, 0x05, 0xFB, 0xF0, 0xFF, 0xD9, 0x5B, 0xC8,\n    0xFF, 0xD0, 0x9A, 0xBE, 0x00, 0x00, 0x10, 0xA9, 0xFF, 0xF4, 0x1E, 0xB2, 0x00, 0xCE, 0xBB, 0xF7,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02, 0x02, 0x00, 0x00, 0x0C,\n    0xFF, 0xC2, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xCF, 0x80, 0x00, 0x40, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x03, 0x3F, 0x68, 0xB6, 0x79, 0x35, 0x28, 0xBC, 0xC6, 0x7E, 0xD1, 0x6C,\n    0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0x6A, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x30,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x25, 0x4D, 0x00, 0x2F, 0x70, 0x6D, 0x00, 0x00, 0x05, 0xAE, 0x00, 0x0C, 0x02, 0xD0,\n\n    // bank 2, 256 bytes\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0xFF, 0xEF, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n\n    // bank 3, 256 bytes\n    0xD8, 0xDC, 0xBA, 0xA2, 0xF1, 0xDE, 0xB2, 0xB8, 0xB4, 0xA8, 0x81, 0x91, 0xF7, 0x4A, 0x90, 0x7F,\n    0x91, 0x6A, 0xF3, 0xF9, 0xDB, 0xA8, 0xF9, 0xB0, 0xBA, 0xA0, 0x80, 0xF2, 0xCE, 0x81, 0xF3, 0xC2,\n    0xF1, 0xC1, 0xF2, 0xC3, 0xF3, 0xCC, 0xA2, 0xB2, 0x80, 0xF1, 0xC6, 0xD8, 0x80, 0xBA, 0xA7, 0xDF,\n    0xDF, 0xDF, 0xF2, 0xA7, 0xC3, 0xCB, 0xC5, 0xB6, 0xF0, 0x87, 0xA2, 0x94, 0x24, 0x48, 0x70, 0x3C,\n    0x95, 0x40, 0x68, 0x34, 0x58, 0x9B, 0x78, 0xA2, 0xF1, 0x83, 0x92, 0x2D, 0x55, 0x7D, 0xD8, 0xB1,\n    0xB4, 0xB8, 0xA1, 0xD0, 0x91, 0x80, 0xF2, 0x70, 0xF3, 0x70, 0xF2, 0x7C, 0x80, 0xA8, 0xF1, 0x01,\n    0xB0, 0x98, 0x87, 0xD9, 0x43, 0xD8, 0x86, 0xC9, 0x88, 0xBA, 0xA1, 0xF2, 0x0E, 0xB8, 0x97, 0x80,\n    0xF1, 0xA9, 0xDF, 0xDF, 0xDF, 0xAA, 0xDF, 0xDF, 0xDF, 0xF2, 0xAA, 0xC5, 0xCD, 0xC7, 0xA9, 0x0C,\n    0xC9, 0x2C, 0x97, 0x97, 0x97, 0x97, 0xF1, 0xA9, 0x89, 0x26, 0x46, 0x66, 0xB0, 0xB4, 0xBA, 0x80,\n    0xAC, 0xDE, 0xF2, 0xCA, 0xF1, 0xB2, 0x8C, 0x02, 0xA9, 0xB6, 0x98, 0x00, 0x89, 0x0E, 0x16, 0x1E,\n    0xB8, 0xA9, 0xB4, 0x99, 0x2C, 0x54, 0x7C, 0xB0, 0x8A, 0xA8, 0x96, 0x36, 0x56, 0x76, 0xF1, 0xB9,\n    0xAF, 0xB4, 0xB0, 0x83, 0xC0, 0xB8, 0xA8, 0x97, 0x11, 0xB1, 0x8F, 0x98, 0xB9, 0xAF, 0xF0, 0x24,\n    0x08, 0x44, 0x10, 0x64, 0x18, 0xF1, 0xA3, 0x29, 0x55, 0x7D, 0xAF, 0x83, 0xB5, 0x93, 0xAF, 0xF0,\n    0x00, 0x28, 0x50, 0xF1, 0xA3, 0x86, 0x9F, 0x61, 0xA6, 0xDA, 0xDE, 0xDF, 0xD9, 0xFA, 0xA3, 0x86,\n    0x96, 0xDB, 0x31, 0xA6, 0xD9, 0xF8, 0xDF, 0xBA, 0xA6, 0x8F, 0xC2, 0xC5, 0xC7, 0xB2, 0x8C, 0xC1,\n    0xB8, 0xA2, 0xDF, 0xDF, 0xDF, 0xA3, 0xDF, 0xDF, 0xDF, 0xD8, 0xD8, 0xF1, 0xB8, 0xA8, 0xB2, 0x86,\n\n    // bank 4, 256 bytes\n    0xB4, 0x98, 0x0D, 0x35, 0x5D, 0xB8, 0xAA, 0x98, 0xB0, 0x87, 0x2D, 0x35, 0x3D, 0xB2, 0xB6, 0xBA,\n    0xAF, 0x8C, 0x96, 0x19, 0x8F, 0x9F, 0xA7, 0x0E, 0x16, 0x1E, 0xB4, 0x9A, 0xB8, 0xAA, 0x87, 0x2C,\n    0x54, 0x7C, 0xB9, 0xA3, 0xDE, 0xDF, 0xDF, 0xA3, 0xB1, 0x80, 0xF2, 0xC4, 0xCD, 0xC9, 0xF1, 0xB8,\n    0xA9, 0xB4, 0x99, 0x83, 0x0D, 0x35, 0x5D, 0x89, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0xB5, 0x93, 0xA3,\n    0x0E, 0x16, 0x1E, 0xA9, 0x2C, 0x54, 0x7C, 0xB8, 0xB4, 0xB0, 0xF1, 0x97, 0x83, 0xA8, 0x11, 0x84,\n    0xA5, 0x09, 0x98, 0xA3, 0x83, 0xF0, 0xDA, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xD8, 0xF1, 0xA5,\n    0x29, 0x55, 0x7D, 0xA5, 0x85, 0x95, 0x02, 0x1A, 0x2E, 0x3A, 0x56, 0x5A, 0x40, 0x48, 0xF9, 0xF3,\n    0xA3, 0xD9, 0xF8, 0xF0, 0x98, 0x83, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0x97, 0x82, 0xA8, 0xF1,\n    0x11, 0xF0, 0x98, 0xA2, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xDA, 0xF3, 0xDE, 0xD8, 0x83, 0xA5,\n    0x94, 0x01, 0xD9, 0xA3, 0x02, 0xF1, 0xA2, 0xC3, 0xC5, 0xC7, 0xD8, 0xF1, 0x84, 0x92, 0xA2, 0x4D,\n    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,\n    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0x93, 0xA3, 0x4D,\n    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,\n    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0xA8, 0x8A, 0x9A,\n    0xF0, 0x28, 0x50, 0x78, 0x9E, 0xF3, 0x88, 0x18, 0xF1, 0x9F, 0x1D, 0x98, 0xA8, 0xD9, 0x08, 0xD8,\n    0xC8, 0x9F, 0x12, 0x9E, 0xF3, 0x15, 0xA8, 0xDA, 0x12, 0x10, 0xD8, 0xF1, 0xAF, 0xC8, 0x97, 0x87,\n\n    // bank 5, 256 bytes\n    0x34, 0xB5, 0xB9, 0x94, 0xA4, 0x21, 0xF3, 0xD9, 0x22, 0xD8, 0xF2, 0x2D, 0xF3, 0xD9, 0x2A, 0xD8,\n    0xF2, 0x35, 0xF3, 0xD9, 0x32, 0xD8, 0x81, 0xA4, 0x60, 0x60, 0x61, 0xD9, 0x61, 0xD8, 0x6C, 0x68,\n    0x69, 0xD9, 0x69, 0xD8, 0x74, 0x70, 0x71, 0xD9, 0x71, 0xD8, 0xB1, 0xA3, 0x84, 0x19, 0x3D, 0x5D,\n    0xA3, 0x83, 0x1A, 0x3E, 0x5E, 0x93, 0x10, 0x30, 0x81, 0x10, 0x11, 0xB8, 0xB0, 0xAF, 0x8F, 0x94,\n    0xF2, 0xDA, 0x3E, 0xD8, 0xB4, 0x9A, 0xA8, 0x87, 0x29, 0xDA, 0xF8, 0xD8, 0x87, 0x9A, 0x35, 0xDA,\n    0xF8, 0xD8, 0x87, 0x9A, 0x3D, 0xDA, 0xF8, 0xD8, 0xB1, 0xB9, 0xA4, 0x98, 0x85, 0x02, 0x2E, 0x56,\n    0xA5, 0x81, 0x00, 0x0C, 0x14, 0xA3, 0x97, 0xB0, 0x8A, 0xF1, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9,\n    0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x84, 0x0D, 0xDA, 0x0E, 0xD8, 0xA3, 0x29, 0x83, 0xDA,\n    0x2C, 0x0E, 0xD8, 0xA3, 0x84, 0x49, 0x83, 0xDA, 0x2C, 0x4C, 0x0E, 0xD8, 0xB8, 0xB0, 0xA8, 0x8A,\n    0x9A, 0xF5, 0x20, 0xAA, 0xDA, 0xDF, 0xD8, 0xA8, 0x40, 0xAA, 0xD0, 0xDA, 0xDE, 0xD8, 0xA8, 0x60,\n    0xAA, 0xDA, 0xD0, 0xDF, 0xD8, 0xF1, 0x97, 0x86, 0xA8, 0x31, 0x9B, 0x06, 0x99, 0x07, 0xAB, 0x97,\n    0x28, 0x88, 0x9B, 0xF0, 0x0C, 0x20, 0x14, 0x40, 0xB8, 0xB0, 0xB4, 0xA8, 0x8C, 0x9C, 0xF0, 0x04,\n    0x28, 0x51, 0x79, 0x1D, 0x30, 0x14, 0x38, 0xB2, 0x82, 0xAB, 0xD0, 0x98, 0x2C, 0x50, 0x50, 0x78,\n    0x78, 0x9B, 0xF1, 0x1A, 0xB0, 0xF0, 0x8A, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x8B, 0x29, 0x51, 0x79,\n    0x8A, 0x24, 0x70, 0x59, 0x8B, 0x20, 0x58, 0x71, 0x8A, 0x44, 0x69, 0x38, 0x8B, 0x39, 0x40, 0x68,\n    0x8A, 0x64, 0x48, 0x31, 0x8B, 0x30, 0x49, 0x60, 0xA5, 0x88, 0x20, 0x09, 0x71, 0x58, 0x44, 0x68,\n\n    // bank 6, 256 bytes\n    0x11, 0x39, 0x64, 0x49, 0x30, 0x19, 0xF1, 0xAC, 0x00, 0x2C, 0x54, 0x7C, 0xF0, 0x8C, 0xA8, 0x04,\n    0x28, 0x50, 0x78, 0xF1, 0x88, 0x97, 0x26, 0xA8, 0x59, 0x98, 0xAC, 0x8C, 0x02, 0x26, 0x46, 0x66,\n    0xF0, 0x89, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38, 0x64, 0x48, 0x31,\n    0xA9, 0x88, 0x09, 0x20, 0x59, 0x70, 0xAB, 0x11, 0x38, 0x40, 0x69, 0xA8, 0x19, 0x31, 0x48, 0x60,\n    0x8C, 0xA8, 0x3C, 0x41, 0x5C, 0x20, 0x7C, 0x00, 0xF1, 0x87, 0x98, 0x19, 0x86, 0xA8, 0x6E, 0x76,\n    0x7E, 0xA9, 0x99, 0x88, 0x2D, 0x55, 0x7D, 0x9E, 0xB9, 0xA3, 0x8A, 0x22, 0x8A, 0x6E, 0x8A, 0x56,\n    0x8A, 0x5E, 0x9F, 0xB1, 0x83, 0x06, 0x26, 0x46, 0x66, 0x0E, 0x2E, 0x4E, 0x6E, 0x9D, 0xB8, 0xAD,\n    0x00, 0x2C, 0x54, 0x7C, 0xF2, 0xB1, 0x8C, 0xB4, 0x99, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0x81, 0x91,\n    0xAC, 0x38, 0xAD, 0x3A, 0xB5, 0x83, 0x91, 0xAC, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9, 0x48, 0xD8,\n    0x6D, 0xD9, 0x68, 0xD8, 0x8C, 0x9D, 0xAE, 0x29, 0xD9, 0x04, 0xAE, 0xD8, 0x51, 0xD9, 0x04, 0xAE,\n    0xD8, 0x79, 0xD9, 0x04, 0xD8, 0x81, 0xF3, 0x9D, 0xAD, 0x00, 0x8D, 0xAE, 0x19, 0x81, 0xAD, 0xD9,\n    0x01, 0xD8, 0xF2, 0xAE, 0xDA, 0x26, 0xD8, 0x8E, 0x91, 0x29, 0x83, 0xA7, 0xD9, 0xAD, 0xAD, 0xAD,\n    0xAD, 0xF3, 0x2A, 0xD8, 0xD8, 0xF1, 0xB0, 0xAC, 0x89, 0x91, 0x3E, 0x5E, 0x76, 0xF3, 0xAC, 0x2E,\n    0x2E, 0xF1, 0xB1, 0x8C, 0x5A, 0x9C, 0xAC, 0x2C, 0x28, 0x28, 0x28, 0x9C, 0xAC, 0x30, 0x18, 0xA8,\n    0x98, 0x81, 0x28, 0x34, 0x3C, 0x97, 0x24, 0xA7, 0x28, 0x34, 0x3C, 0x9C, 0x24, 0xF2, 0xB0, 0x89,\n    0xAC, 0x91, 0x2C, 0x4C, 0x6C, 0x8A, 0x9B, 0x2D, 0xD9, 0xD8, 0xD8, 0x51, 0xD9, 0xD8, 0xD8, 0x79,\n\n    // bank 7, 138 bytes (remainder)\n    0xD9, 0xD8, 0xD8, 0xF1, 0x9E, 0x88, 0xA3, 0x31, 0xDA, 0xD8, 0xD8, 0x91, 0x2D, 0xD9, 0x28, 0xD8,\n    0x4D, 0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x83, 0x93, 0x35, 0x3D, 0x80, 0x25, 0xDA,\n    0xD8, 0xD8, 0x85, 0x69, 0xDA, 0xD8, 0xD8, 0xB4, 0x93, 0x81, 0xA3, 0x28, 0x34, 0x3C, 0xF3, 0xAB,\n    0x8B, 0xF8, 0xA3, 0x91, 0xB6, 0x09, 0xB4, 0xD9, 0xAB, 0xDE, 0xFA, 0xB0, 0x87, 0x9C, 0xB9, 0xA3,\n    0xDD, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x95, 0xF1, 0xA3, 0xA3, 0xA3, 0x9D, 0xF1, 0xA3, 0xA3, 0xA3,\n    0xA3, 0xF2, 0xA3, 0xB4, 0x90, 0x80, 0xF2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,\n    0xA3, 0xB2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xB0, 0x87, 0xB5, 0x99, 0xF1, 0xA3, 0xA3, 0xA3,\n    0x98, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x97, 0xA3, 0xA3, 0xA3, 0xA3, 0xF3, 0x9B, 0xA3, 0xA3, 0xDC,\n    0xB9, 0xA7, 0xF1, 0x26, 0x26, 0x26, 0xD8, 0xD8, 0xFF\n};\n\n#ifndef MPU6050_DMP_FIFO_RATE_DIVISOR \n#define MPU6050_DMP_FIFO_RATE_DIVISOR 0x01\n#endif\n\n// thanks to Noah Zerkin for piecing this stuff together!\nconst unsigned char dmpConfig[MPU6050_DMP_CONFIG_SIZE] PROGMEM = {\n//  BANK    OFFSET  LENGTH  [DATA]\n    0x03,   0x7B,   0x03,   0x4C, 0xCD, 0x6C,         // FCFG_1 inv_set_gyro_calibration\n    0x03,   0xAB,   0x03,   0x36, 0x56, 0x76,         // FCFG_3 inv_set_gyro_calibration\n    0x00,   0x68,   0x04,   0x02, 0xCB, 0x47, 0xA2,   // D_0_104 inv_set_gyro_calibration\n    0x02,   0x18,   0x04,   0x00, 0x05, 0x8B, 0xC1,   // D_0_24 inv_set_gyro_calibration\n    0x01,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // D_1_152 inv_set_accel_calibration\n    0x03,   0x7F,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_accel_calibration\n    0x03,   0x89,   0x03,   0x26, 0x46, 0x66,         // FCFG_7 inv_set_accel_calibration\n    0x00,   0x6C,   0x02,   0x20, 0x00,               // D_0_108 inv_set_accel_calibration\n    0x02,   0x40,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_00 inv_set_compass_calibration\n    0x02,   0x44,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_01\n    0x02,   0x48,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_02\n    0x02,   0x4C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_10\n    0x02,   0x50,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_11\n    0x02,   0x54,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_12\n    0x02,   0x58,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_20\n    0x02,   0x5C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_21\n    0x02,   0xBC,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_22\n    0x01,   0xEC,   0x04,   0x00, 0x00, 0x40, 0x00,   // D_1_236 inv_apply_endian_accel\n    0x03,   0x7F,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_mpu_sensors\n    0x04,   0x02,   0x03,   0x0D, 0x35, 0x5D,         // CFG_MOTION_BIAS inv_turn_on_bias_from_no_motion\n    0x04,   0x09,   0x04,   0x87, 0x2D, 0x35, 0x3D,   // FCFG_5 inv_set_bias_update\n    0x00,   0xA3,   0x01,   0x00,                     // D_0_163 inv_set_dead_zone\n                 // SPECIAL 0x01 = enable interrupts\n    0x00,   0x00,   0x00,   0x01, // SET INT_ENABLE at i=22, SPECIAL INSTRUCTION\n    0x07,   0x86,   0x01,   0xFE,                     // CFG_6 inv_set_fifo_interupt\n    0x07,   0x41,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // CFG_8 inv_send_quaternion\n    0x07,   0x7E,   0x01,   0x30,                     // CFG_16 inv_set_footer\n    0x07,   0x46,   0x01,   0x9A,                     // CFG_GYRO_SOURCE inv_send_gyro\n    0x07,   0x47,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_9 inv_send_gyro -> inv_construct3_fifo\n    0x07,   0x6C,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_12 inv_send_accel -> inv_construct3_fifo\n    0x02,   0x16,   0x02,   0x00, MPU6050_DMP_FIFO_RATE_DIVISOR // D_0_22 inv_set_fifo_rate\n\n    // This very last 0x01 WAS a 0x09, which drops the FIFO rate down to 20 Hz. 0x07 is 25 Hz,\n    // 0x01 is 100Hz. Going faster than 100Hz (0x00=200Hz) tends to result in very noisy data.\n    // DMP output frequency is calculated easily using this equation: (200Hz / (1 + value))\n\n    // It is important to make sure the host processor can keep up with reading and processing\n    // the FIFO output at the desired rate. Handling FIFO overflow cleanly is also a good idea.\n};\n\nconst unsigned char dmpUpdates[MPU6050_DMP_UPDATES_SIZE] PROGMEM = {\n    0x01,   0xB2,   0x02,   0xFF, 0xFF,\n    0x01,   0x90,   0x04,   0x09, 0x23, 0xA1, 0x35,\n    0x01,   0x6A,   0x02,   0x06, 0x00,\n    0x01,   0x60,   0x08,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,\n    0x01,   0x62,   0x02,   0x00, 0x00,\n    0x00,   0x60,   0x04,   0x00, 0x40, 0x00, 0x00\n};\n\nuint8_t MPU6050::dmpInitialize() {\n    // reset device\n    DEBUG_PRINTLN(F(\"\\n\\nResetting MPU6050...\"));\n    reset();\n    delay(30); // wait after reset\n\n    // enable sleep mode and wake cycle\n    /*Serial.println(F(\"Enabling sleep mode...\"));\n    setSleepEnabled(true);\n    Serial.println(F(\"Enabling wake cycle...\"));\n    setWakeCycleEnabled(true);*/\n\n    // disable sleep mode\n    DEBUG_PRINTLN(F(\"Disabling sleep mode...\"));\n    setSleepEnabled(false);\n\n    // get MPU hardware revision\n    DEBUG_PRINTLN(F(\"Selecting user bank 16...\"));\n    setMemoryBank(0x10, true, true);\n    DEBUG_PRINTLN(F(\"Selecting memory byte 6...\"));\n    setMemoryStartAddress(0x06);\n    DEBUG_PRINTLN(F(\"Checking hardware revision...\"));\n    DEBUG_PRINT(F(\"Revision @ user[16][6] = \"));\n    DEBUG_PRINTLNF(readMemoryByte(), HEX);\n    DEBUG_PRINTLN(F(\"Resetting memory bank selection to 0...\"));\n    setMemoryBank(0, false, false);\n\n    // check OTP bank valid\n    DEBUG_PRINTLN(F(\"Reading OTP bank valid flag...\"));\n    DEBUG_PRINT(F(\"OTP bank is \"));\n    DEBUG_PRINTLN(getOTPBankValid() ? F(\"valid!\") : F(\"invalid!\"));\n\n    // get X/Y/Z gyro offsets\n    DEBUG_PRINTLN(F(\"Reading gyro offset TC values...\"));\n    int8_t xgOffsetTC = getXGyroOffsetTC();\n    int8_t ygOffsetTC = getYGyroOffsetTC();\n    int8_t zgOffsetTC = getZGyroOffsetTC();\n    DEBUG_PRINT(F(\"X gyro offset = \"));\n    DEBUG_PRINTLN(xgOffsetTC);\n    DEBUG_PRINT(F(\"Y gyro offset = \"));\n    DEBUG_PRINTLN(ygOffsetTC);\n    DEBUG_PRINT(F(\"Z gyro offset = \"));\n    DEBUG_PRINTLN(zgOffsetTC);\n\n    // setup weird slave stuff (?)\n    DEBUG_PRINTLN(F(\"Setting slave 0 address to 0x7F...\"));\n    setSlaveAddress(0, 0x7F);\n    DEBUG_PRINTLN(F(\"Disabling I2C Master mode...\"));\n    setI2CMasterModeEnabled(false);\n    DEBUG_PRINTLN(F(\"Setting slave 0 address to 0x68 (self)...\"));\n    setSlaveAddress(0, 0x68);\n    DEBUG_PRINTLN(F(\"Resetting I2C Master control...\"));\n    resetI2CMaster();\n    delay(20);\n\n    // load DMP code into memory banks\n    DEBUG_PRINT(F(\"Writing DMP code to MPU memory banks (\"));\n    DEBUG_PRINT(MPU6050_DMP_CODE_SIZE);\n    DEBUG_PRINTLN(F(\" bytes)\"));\n    if (writeProgMemoryBlock(dmpMemory, MPU6050_DMP_CODE_SIZE)) {\n        DEBUG_PRINTLN(F(\"Success! DMP code written and verified.\"));\n\n        // write DMP configuration\n        DEBUG_PRINT(F(\"Writing DMP configuration to MPU memory banks (\"));\n        DEBUG_PRINT(MPU6050_DMP_CONFIG_SIZE);\n        DEBUG_PRINTLN(F(\" bytes in config def)\"));\n        if (writeProgDMPConfigurationSet(dmpConfig, MPU6050_DMP_CONFIG_SIZE)) {\n            DEBUG_PRINTLN(F(\"Success! DMP configuration written and verified.\"));\n\n            DEBUG_PRINTLN(F(\"Setting clock source to Z Gyro...\"));\n            setClockSource(MPU6050_CLOCK_PLL_ZGYRO);\n\n            DEBUG_PRINTLN(F(\"Setting DMP and FIFO_OFLOW interrupts enabled...\"));\n            setIntEnabled(1<<MPU6050_INTERRUPT_FIFO_OFLOW_BIT|1<<MPU6050_INTERRUPT_DMP_INT_BIT);\n\n            DEBUG_PRINTLN(F(\"Setting sample rate to 200Hz...\"));\n            setRate(4); // 1khz / (1 + 4) = 200 Hz\n\n            DEBUG_PRINTLN(F(\"Setting external frame sync to TEMP_OUT_L[0]...\"));\n            setExternalFrameSync(MPU6050_EXT_SYNC_TEMP_OUT_L);\n\n            DEBUG_PRINTLN(F(\"Setting DLPF bandwidth to 42Hz...\"));\n            setDLPFMode(MPU6050_DLPF_BW_42);\n\n            DEBUG_PRINTLN(F(\"Setting gyro sensitivity to +/- 2000 deg/sec...\"));\n            setFullScaleGyroRange(MPU6050_GYRO_FS_2000);\n\n            DEBUG_PRINTLN(F(\"Setting DMP programm start address\"));\n            //write start address MSB into register\n            setDMPConfig1(0x03);\n            //write start address LSB into register\n            setDMPConfig2(0x00);\n\n            DEBUG_PRINTLN(F(\"Clearing OTP Bank flag...\"));\n            setOTPBankValid(false);\n\n            DEBUG_PRINTLN(F(\"Setting X/Y/Z gyro offset TCs to previous values...\"));\n            setXGyroOffsetTC(xgOffsetTC);\n            setYGyroOffsetTC(ygOffsetTC);\n            setZGyroOffsetTC(zgOffsetTC);\n\n            //DEBUG_PRINTLN(F(\"Setting X/Y/Z gyro user offsets to zero...\"));\n            //setXGyroOffset(0);\n            //setYGyroOffset(0);\n            //setZGyroOffset(0);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 1/7 (function unknown)...\"));\n            uint8_t dmpUpdate[16], j;\n            uint16_t pos = 0;\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 2/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Resetting FIFO...\"));\n            resetFIFO();\n\n            DEBUG_PRINTLN(F(\"Reading FIFO count...\"));\n            uint16_t fifoCount = getFIFOCount();\n            uint8_t fifoBuffer[128];\n\n            DEBUG_PRINT(F(\"Current FIFO count=\"));\n            DEBUG_PRINTLN(fifoCount);\n            getFIFOBytes(fifoBuffer, fifoCount);\n\n            DEBUG_PRINTLN(F(\"Setting motion detection threshold to 2...\"));\n            setMotionDetectionThreshold(2);\n\n            DEBUG_PRINTLN(F(\"Setting zero-motion detection threshold to 156...\"));\n            setZeroMotionDetectionThreshold(156);\n\n            DEBUG_PRINTLN(F(\"Setting motion detection duration to 80...\"));\n            setMotionDetectionDuration(80);\n\n            DEBUG_PRINTLN(F(\"Setting zero-motion detection duration to 0...\"));\n            setZeroMotionDetectionDuration(0);\n\n            DEBUG_PRINTLN(F(\"Resetting FIFO...\"));\n            resetFIFO();\n\n            DEBUG_PRINTLN(F(\"Enabling FIFO...\"));\n            setFIFOEnabled(true);\n\n            DEBUG_PRINTLN(F(\"Enabling DMP...\"));\n            setDMPEnabled(true);\n\n            DEBUG_PRINTLN(F(\"Resetting DMP...\"));\n            resetDMP();\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 3/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 4/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 5/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Waiting for FIFO count > 2...\"));\n            while ((fifoCount = getFIFOCount()) < 3);\n\n            DEBUG_PRINT(F(\"Current FIFO count=\"));\n            DEBUG_PRINTLN(fifoCount);\n            DEBUG_PRINTLN(F(\"Reading FIFO data...\"));\n            getFIFOBytes(fifoBuffer, fifoCount);\n\n            DEBUG_PRINTLN(F(\"Reading interrupt status...\"));\n\n            DEBUG_PRINT(F(\"Current interrupt status=\"));\n            DEBUG_PRINTLNF(getIntStatus(), HEX);\n\n            DEBUG_PRINTLN(F(\"Reading final memory update 6/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            readMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Waiting for FIFO count > 2...\"));\n            while ((fifoCount = getFIFOCount()) < 3);\n\n            DEBUG_PRINT(F(\"Current FIFO count=\"));\n            DEBUG_PRINTLN(fifoCount);\n\n            DEBUG_PRINTLN(F(\"Reading FIFO data...\"));\n            getFIFOBytes(fifoBuffer, fifoCount);\n\n            DEBUG_PRINTLN(F(\"Reading interrupt status...\"));\n\n            DEBUG_PRINT(F(\"Current interrupt status=\"));\n            DEBUG_PRINTLNF(getIntStatus(), HEX);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 7/7 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"DMP is good to go! Finally.\"));\n\n            DEBUG_PRINTLN(F(\"Disabling DMP (you turn it on later)...\"));\n            setDMPEnabled(false);\n\n            DEBUG_PRINTLN(F(\"Setting up internal 42-byte (default) DMP packet buffer...\"));\n            dmpPacketSize = 42;\n            /*if ((dmpPacketBuffer = (uint8_t *)malloc(42)) == 0) {\n                return 3; // TODO: proper error code for no memory\n            }*/\n\n            DEBUG_PRINTLN(F(\"Resetting FIFO and clearing INT status one last time...\"));\n            resetFIFO();\n            getIntStatus();\n        } else {\n            DEBUG_PRINTLN(F(\"ERROR! DMP configuration verification failed.\"));\n            return 2; // configuration block loading failed\n        }\n    } else {\n        DEBUG_PRINTLN(F(\"ERROR! DMP code verification failed.\"));\n        return 1; // main binary block loading failed\n    }\n    return 0; // success\n}\n\nbool MPU6050::dmpPacketAvailable() {\n    return getFIFOCount() >= dmpGetFIFOPacketSize();\n}\n\n// uint8_t MPU6050::dmpSetFIFORate(uint8_t fifoRate);\n// uint8_t MPU6050::dmpGetFIFORate();\n// uint8_t MPU6050::dmpGetSampleStepSizeMS();\n// uint8_t MPU6050::dmpGetSampleFrequency();\n// int32_t MPU6050::dmpDecodeTemperature(int8_t tempReg);\n\n//uint8_t MPU6050::dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);\n//uint8_t MPU6050::dmpUnregisterFIFORateProcess(inv_obj_func func);\n//uint8_t MPU6050::dmpRunFIFORateProcesses();\n\n// uint8_t MPU6050::dmpSendQuaternion(uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendPacketNumber(uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);\n\nuint8_t MPU6050::dmpGetAccel(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[28] << 24) | ((uint32_t)packet[29] << 16) | ((uint32_t)packet[30] << 8) | packet[31]);\n    data[1] = (((uint32_t)packet[32] << 24) | ((uint32_t)packet[33] << 16) | ((uint32_t)packet[34] << 8) | packet[35]);\n    data[2] = (((uint32_t)packet[36] << 24) | ((uint32_t)packet[37] << 16) | ((uint32_t)packet[38] << 8) | packet[39]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetAccel(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (packet[28] << 8) | packet[29];\n    data[1] = (packet[32] << 8) | packet[33];\n    data[2] = (packet[36] << 8) | packet[37];\n    return 0;\n}\nuint8_t MPU6050::dmpGetAccel(VectorInt16 *v, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    v -> x = (packet[28] << 8) | packet[29];\n    v -> y = (packet[32] << 8) | packet[33];\n    v -> z = (packet[36] << 8) | packet[37];\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[0] << 24) | ((uint32_t)packet[1] << 16) | ((uint32_t)packet[2] << 8) | packet[3]);\n    data[1] = (((uint32_t)packet[4] << 24) | ((uint32_t)packet[5] << 16) | ((uint32_t)packet[6] << 8) | packet[7]);\n    data[2] = (((uint32_t)packet[8] << 24) | ((uint32_t)packet[9] << 16) | ((uint32_t)packet[10] << 8) | packet[11]);\n    data[3] = (((uint32_t)packet[12] << 24) | ((uint32_t)packet[13] << 16) | ((uint32_t)packet[14] << 8) | packet[15]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = ((packet[0] << 8) | packet[1]);\n    data[1] = ((packet[4] << 8) | packet[5]);\n    data[2] = ((packet[8] << 8) | packet[9]);\n    data[3] = ((packet[12] << 8) | packet[13]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(Quaternion *q, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    int16_t qI[4];\n    uint8_t status = dmpGetQuaternion(qI, packet);\n    if (status == 0) {\n        q -> w = (float)qI[0] / 16384.0f;\n        q -> x = (float)qI[1] / 16384.0f;\n        q -> y = (float)qI[2] / 16384.0f;\n        q -> z = (float)qI[3] / 16384.0f;\n        return 0;\n    }\n    return status; // int16 return value, indicates error if this line is reached\n}\n// uint8_t MPU6050::dmpGet6AxisQuaternion(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetRelativeQuaternion(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetGyro(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[16] << 24) | ((uint32_t)packet[17] << 16) | ((uint32_t)packet[18] << 8) | packet[19]);\n    data[1] = (((uint32_t)packet[20] << 24) | ((uint32_t)packet[21] << 16) | ((uint32_t)packet[22] << 8) | packet[23]);\n    data[2] = (((uint32_t)packet[24] << 24) | ((uint32_t)packet[25] << 16) | ((uint32_t)packet[26] << 8) | packet[27]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetGyro(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (packet[16] << 8) | packet[17];\n    data[1] = (packet[20] << 8) | packet[21];\n    data[2] = (packet[24] << 8) | packet[25];\n    return 0;\n}\nuint8_t MPU6050::dmpGetGyro(VectorInt16 *v, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    v -> x = (packet[16] << 8) | packet[17];\n    v -> y = (packet[20] << 8) | packet[21];\n    v -> z = (packet[24] << 8) | packet[25];\n    return 0;\n}\n// uint8_t MPU6050::dmpSetLinearAccelFilterCoefficient(float coef);\n// uint8_t MPU6050::dmpGetLinearAccel(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity) {\n    // get rid of the gravity component (+1g = +8192 in standard DMP FIFO packet, sensitivity is 2g)\n    v -> x = vRaw -> x - gravity -> x*8192;\n    v -> y = vRaw -> y - gravity -> y*8192;\n    v -> z = vRaw -> z - gravity -> z*8192;\n    return 0;\n}\n// uint8_t MPU6050::dmpGetLinearAccelInWorld(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q) {\n    // rotate measured 3D acceleration vector into original state\n    // frame of reference based on orientation quaternion\n    memcpy(v, vReal, sizeof(VectorInt16));\n    v -> rotate(q);\n    return 0;\n}\n// uint8_t MPU6050::dmpGetGyroAndAccelSensor(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetGyroSensor(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetControlData(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetTemperature(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetGravity(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetGravity(int16_t *data, const uint8_t* packet) {\n    /* +1g corresponds to +8192, sensitivity is 2g. */\n    int16_t qI[4];\n    uint8_t status = dmpGetQuaternion(qI, packet);\n    data[0] = ((int32_t)qI[1] * qI[3] - (int32_t)qI[0] * qI[2]) / 16384;\n    data[1] = ((int32_t)qI[0] * qI[1] + (int32_t)qI[2] * qI[3]) / 16384;\n    data[2] = ((int32_t)qI[0] * qI[0] - (int32_t)qI[1] * qI[1]\n\t       - (int32_t)qI[2] * qI[2] + (int32_t)qI[3] * qI[3]) / (2 * 16384);\n    return status;\n}\n\nuint8_t MPU6050::dmpGetGravity(VectorFloat *v, Quaternion *q) {\n    v -> x = 2 * (q -> x*q -> z - q -> w*q -> y);\n    v -> y = 2 * (q -> w*q -> x + q -> y*q -> z);\n    v -> z = q -> w*q -> w - q -> x*q -> x - q -> y*q -> y + q -> z*q -> z;\n    return 0;\n}\n// uint8_t MPU6050::dmpGetUnquantizedAccel(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetQuantizedAccel(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetExternalSensorData(long *data, int size, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetEIS(long *data, const uint8_t* packet);\n\nuint8_t MPU6050::dmpGetEuler(float *data, Quaternion *q) {\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);   // psi\n    data[1] = -asin(2*q -> x*q -> z + 2*q -> w*q -> y);                              // theta\n    data[2] = atan2(2*q -> y*q -> z - 2*q -> w*q -> x, 2*q -> w*q -> w + 2*q -> z*q -> z - 1);   // phi\n    return 0;\n}\n\n#ifdef USE_OLD_DMPGETYAWPITCHROLL\nuint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {\n    // yaw: (about Z axis)\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);\n    // pitch: (nose up/down, about Y axis)\n    data[1] = atan(gravity -> x / sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));\n    // roll: (tilt left/right, about X axis)\n    data[2] = atan(gravity -> y / sqrt(gravity -> x*gravity -> x + gravity -> z*gravity -> z));\n    return 0;\n}\n#else \nuint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {\n    // yaw: (about Z axis)\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);\n    // pitch: (nose up/down, about Y axis)\n    data[1] = atan2(gravity -> x , sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));\n    // roll: (tilt left/right, about X axis)\n    data[2] = atan2(gravity -> y , gravity -> z);\n    if (gravity -> z < 0) {\n        if(data[1] > 0) {\n            data[1] = PI - data[1]; \n        } else { \n            data[1] = -PI - data[1];\n        }\n    }\n    return 0;\n}\n#endif\n\n// uint8_t MPU6050::dmpGetAccelFloat(float *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetQuaternionFloat(float *data, const uint8_t* packet);\n\nuint8_t MPU6050::dmpProcessFIFOPacket(const unsigned char *dmpData) {\n    /*for (uint8_t k = 0; k < dmpPacketSize; k++) {\n        if (dmpData[k] < 0x10) Serial.print(\"0\");\n        Serial.print(dmpData[k], HEX);\n        Serial.print(\" \");\n    }\n    Serial.print(\"\\n\");*/\n    //Serial.println((uint16_t)dmpPacketBuffer);\n    return 0;\n}\nuint8_t MPU6050::dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed) {\n    uint8_t status;\n    uint8_t buf[dmpPacketSize];\n    for (uint8_t i = 0; i < numPackets; i++) {\n        // read packet from FIFO\n        getFIFOBytes(buf, dmpPacketSize);\n\n        // process packet\n        if ((status = dmpProcessFIFOPacket(buf)) > 0) return status;\n        \n        // increment external process count variable, if supplied\n        if (processed != 0) (*processed)++;\n    }\n    return 0;\n}\n\n// uint8_t MPU6050::dmpSetFIFOProcessedCallback(void (*func) (void));\n\n// uint8_t MPU6050::dmpInitFIFOParam();\n// uint8_t MPU6050::dmpCloseFIFO();\n// uint8_t MPU6050::dmpSetGyroDataSource(uint_fast8_t source);\n// uint8_t MPU6050::dmpDecodeQuantizedAccel();\n// uint32_t MPU6050::dmpGetGyroSumOfSquare();\n// uint32_t MPU6050::dmpGetAccelSumOfSquare();\n// void MPU6050::dmpOverrideQuaternion(long *q);\nuint16_t MPU6050::dmpGetFIFOPacketSize() {\n    return dmpPacketSize;\n}\n\n#endif /* _MPU6050_6AXIS_MOTIONAPPS20_H_ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/MPU6050_9Axis_MotionApps41.h",
    "content": "// I2Cdev library collection - MPU6050 I2C device class, 9-axis MotionApps 4.1 implementation\n// Based on InvenSense MPU-6050 register map document rev. 2.0, 5/19/2011 (RM-MPU-6000A-00)\n// 6/18/2012 by Jeff Rowberg <jeff@rowberg.net>\n// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib\n//\n// Changelog:\n//     ... - ongoing debug release\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2012 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#ifndef _MPU6050_9AXIS_MOTIONAPPS41_H_\n#define _MPU6050_9AXIS_MOTIONAPPS41_H_\n\n#include \"i2c_dev.hpp\"\n#include \"helper_3dmath.h\"\n\n// MotionApps 4.1 DMP implementation, built using the MPU-9150 \"MotionFit\" board\n#define MPU6050_INCLUDE_DMP_MOTIONAPPS41\n\n#include \"mpu6050.hpp\"\n\n// Tom Carpenter's conditional PROGMEM code\n// http://forum.arduino.cc/index.php?topic=129407.0\n#ifdef __AVR__\n    #include <avr/pgmspace.h>\n#else\n    // Teensy 3.0 library conditional PROGMEM code from Paul Stoffregen\n    #ifndef __PGMSPACE_H_\n        #define __PGMSPACE_H_ 1\n        #include <inttypes.h>\n\n        #define PROGMEM\n        #define PGM_P  const char *\n        #define PSTR(str) (str)\n        #define F(x) x\n\n        typedef void prog_void;\n        typedef char prog_char;\n        //typedef unsigned char prog_uchar;\n        typedef int8_t prog_int8_t;\n        typedef uint8_t prog_uint8_t;\n        typedef int16_t prog_int16_t;\n        typedef uint16_t prog_uint16_t;\n        typedef int32_t prog_int32_t;\n        typedef uint32_t prog_uint32_t;\n        \n        #define strcpy_P(dest, src) strcpy((dest), (src))\n        #define strcat_P(dest, src) strcat((dest), (src))\n        #define strcmp_P(a, b) strcmp((a), (b))\n        \n        #define pgm_read_byte(addr) (*(const unsigned char *)(addr))\n        #define pgm_read_word(addr) (*(const unsigned short *)(addr))\n        #define pgm_read_dword(addr) (*(const unsigned long *)(addr))\n        #define pgm_read_float(addr) (*(const float *)(addr))\n        \n        #define pgm_read_byte_near(addr) pgm_read_byte(addr)\n        #define pgm_read_word_near(addr) pgm_read_word(addr)\n        #define pgm_read_dword_near(addr) pgm_read_dword(addr)\n        #define pgm_read_float_near(addr) pgm_read_float(addr)\n        #define pgm_read_byte_far(addr) pgm_read_byte(addr)\n        #define pgm_read_word_far(addr) pgm_read_word(addr)\n        #define pgm_read_dword_far(addr) pgm_read_dword(addr)\n        #define pgm_read_float_far(addr) pgm_read_float(addr)\n    #endif\n#endif\n\n// NOTE! Enabling DEBUG adds about 3.3kB to the flash program size.\n// Debug output is now working even on ATMega328P MCUs (e.g. Arduino Uno)\n// after moving string constants to flash memory storage using the F()\n// compiler macro (Arduino IDE 1.0+ required).\n\n//#define DEBUG\n#ifdef DEBUG\n    #define DEBUG_PRINT(x) Serial.print(x)\n    #define DEBUG_PRINTF(x, y) Serial.print(x, y)\n    #define DEBUG_PRINTLN(x) Serial.println(x)\n    #define DEBUG_PRINTLNF(x, y) Serial.println(x, y)\n#else\n    #define DEBUG_PRINT(x)\n    #define DEBUG_PRINTF(x, y)\n    #define DEBUG_PRINTLN(x)\n    #define DEBUG_PRINTLNF(x, y)\n#endif\n\n#define MPU6050_DMP_CODE_SIZE       1962    // dmpMemory[]\n#define MPU6050_DMP_CONFIG_SIZE     232     // dmpConfig[]\n#define MPU6050_DMP_UPDATES_SIZE    140     // dmpUpdates[]\n\n/* ================================================================================================ *\n | Default MotionApps v4.1 48-byte FIFO packet structure:                                           |\n |                                                                                                  |\n | [QUAT W][      ][QUAT X][      ][QUAT Y][      ][QUAT Z][      ][GYRO X][      ][GYRO Y][      ] |\n |   0   1   2   3   4   5   6   7   8   9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  |\n |                                                                                                  |\n | [GYRO Z][      ][MAG X ][MAG Y ][MAG Z ][ACC X ][      ][ACC Y ][      ][ACC Z ][      ][      ] |\n |  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  |\n * ================================================================================================ */\n\n// this block of memory gets written to the MPU on start-up, and it seems\n// to be volatile memory, so it has to be done each time (it only takes ~1\n// second though)\nconst unsigned char dmpMemory[MPU6050_DMP_CODE_SIZE] PROGMEM = {\n    // bank 0, 256 bytes\n    0xFB, 0x00, 0x00, 0x3E, 0x00, 0x0B, 0x00, 0x36, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x00,\n    0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0xFA, 0x80, 0x00, 0x0B, 0x12, 0x82, 0x00, 0x01,\n    0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x28, 0x00, 0x00, 0xFF, 0xFF, 0x45, 0x81, 0xFF, 0xFF, 0xFA, 0x72, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x03, 0xE8, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x7F, 0xFF, 0xFF, 0xFE, 0x80, 0x01,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x3E, 0x03, 0x30, 0x40, 0x00, 0x00, 0x00, 0x02, 0xCA, 0xE3, 0x09, 0x3E, 0x80, 0x00, 0x00,\n    0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00,\n    0x41, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x2A, 0x00, 0x00, 0x16, 0x55, 0x00, 0x00, 0x21, 0x82,\n    0xFD, 0x87, 0x26, 0x50, 0xFD, 0x80, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x05, 0x80, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x6F, 0x00, 0x02, 0x65, 0x32, 0x00, 0x00, 0x5E, 0xC0,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0xFB, 0x8C, 0x6F, 0x5D, 0xFD, 0x5D, 0x08, 0xD9, 0x00, 0x7C, 0x73, 0x3B, 0x00, 0x6C, 0x12, 0xCC,\n    0x32, 0x00, 0x13, 0x9D, 0x32, 0x00, 0xD0, 0xD6, 0x32, 0x00, 0x08, 0x00, 0x40, 0x00, 0x01, 0xF4,\n    0xFF, 0xE6, 0x80, 0x79, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0xD6, 0x00, 0x00, 0x27, 0x10,\n\n    // bank 1, 256 bytes\n    0xFB, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0xFA, 0x36, 0xFF, 0xBC, 0x30, 0x8E, 0x00, 0x05, 0xFB, 0xF0, 0xFF, 0xD9, 0x5B, 0xC8,\n    0xFF, 0xD0, 0x9A, 0xBE, 0x00, 0x00, 0x10, 0xA9, 0xFF, 0xF4, 0x1E, 0xB2, 0x00, 0xCE, 0xBB, 0xF7,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x02, 0x00, 0x02, 0x02, 0x00, 0x00, 0x0C,\n    0xFF, 0xC2, 0x80, 0x00, 0x00, 0x01, 0x80, 0x00, 0x00, 0xCF, 0x80, 0x00, 0x40, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x14,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x03, 0x3F, 0x68, 0xB6, 0x79, 0x35, 0x28, 0xBC, 0xC6, 0x7E, 0xD1, 0x6C,\n    0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xB2, 0x6A, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x00, 0x00, 0x30,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x25, 0x4D, 0x00, 0x2F, 0x70, 0x6D, 0x00, 0x00, 0x05, 0xAE, 0x00, 0x0C, 0x02, 0xD0,\n    \n    // bank 2, 256 bytes\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x54, 0xFF, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x01, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0xFF, 0xEF, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00,\n    0x00, 0x1B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x78, 0xA2,\n    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    \n    // bank 3, 256 bytes\n    0xD8, 0xDC, 0xF4, 0xD8, 0xB9, 0xAB, 0xF3, 0xF8, 0xFA, 0xF1, 0xBA, 0xA2, 0xDE, 0xB2, 0xB8, 0xB4,\n    0xA8, 0x81, 0x98, 0xF7, 0x4A, 0x90, 0x7F, 0x91, 0x6A, 0xF3, 0xF9, 0xDB, 0xA8, 0xF9, 0xB0, 0xBA,\n    0xA0, 0x80, 0xF2, 0xCE, 0x81, 0xF3, 0xC2, 0xF1, 0xC1, 0xF2, 0xC3, 0xF3, 0xCC, 0xA2, 0xB2, 0x80,\n    0xF1, 0xC6, 0xD8, 0x80, 0xBA, 0xA7, 0xDF, 0xDF, 0xDF, 0xF2, 0xA7, 0xC3, 0xCB, 0xC5, 0xB6, 0xF0,\n    0x87, 0xA2, 0x94, 0x24, 0x48, 0x70, 0x3C, 0x95, 0x40, 0x68, 0x34, 0x58, 0x9B, 0x78, 0xA2, 0xF1,\n    0x83, 0x92, 0x2D, 0x55, 0x7D, 0xD8, 0xB1, 0xB4, 0xB8, 0xA1, 0xD0, 0x91, 0x80, 0xF2, 0x70, 0xF3,\n    0x70, 0xF2, 0x7C, 0x80, 0xA8, 0xF1, 0x01, 0xB0, 0x98, 0x87, 0xD9, 0x43, 0xD8, 0x86, 0xC9, 0x88,\n    0xBA, 0xA1, 0xF2, 0x0E, 0xB8, 0x97, 0x80, 0xF1, 0xA9, 0xDF, 0xDF, 0xDF, 0xAA, 0xDF, 0xDF, 0xDF,\n    0xF2, 0xAA, 0xC5, 0xCD, 0xC7, 0xA9, 0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, 0x97, 0xF1, 0xA9, 0x89,\n    0x26, 0x46, 0x66, 0xB0, 0xB4, 0xBA, 0x80, 0xAC, 0xDE, 0xF2, 0xCA, 0xF1, 0xB2, 0x8C, 0x02, 0xA9,\n    0xB6, 0x98, 0x00, 0x89, 0x0E, 0x16, 0x1E, 0xB8, 0xA9, 0xB4, 0x99, 0x2C, 0x54, 0x7C, 0xB0, 0x8A,\n    0xA8, 0x96, 0x36, 0x56, 0x76, 0xF1, 0xB9, 0xAF, 0xB4, 0xB0, 0x83, 0xC0, 0xB8, 0xA8, 0x97, 0x11,\n    0xB1, 0x8F, 0x98, 0xB9, 0xAF, 0xF0, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xF1, 0xA3, 0x29, 0x55,\n    0x7D, 0xAF, 0x83, 0xB5, 0x93, 0xF0, 0x00, 0x28, 0x50, 0xF5, 0xBA, 0xAD, 0x8F, 0x9F, 0x28, 0x54,\n    0x7C, 0xB9, 0xF1, 0xA3, 0x86, 0x9F, 0x61, 0xA6, 0xDA, 0xDE, 0xDF, 0xDB, 0xB2, 0xB6, 0x8E, 0x9D,\n    0xAE, 0xF5, 0x60, 0x68, 0x70, 0xB1, 0xB5, 0xF1, 0xDA, 0xA6, 0xDF, 0xD9, 0xA6, 0xFA, 0xA3, 0x86,\n    \n    // bank 4, 256 bytes\n    0x96, 0xDB, 0x31, 0xA6, 0xD9, 0xF8, 0xDF, 0xBA, 0xA6, 0x8F, 0xC2, 0xC5, 0xC7, 0xB2, 0x8C, 0xC1,\n    0xB8, 0xA2, 0xDF, 0xDF, 0xDF, 0xA3, 0xDF, 0xDF, 0xDF, 0xD8, 0xD8, 0xF1, 0xB8, 0xA8, 0xB2, 0x86,\n    0xB4, 0x98, 0x0D, 0x35, 0x5D, 0xB8, 0xAA, 0x98, 0xB0, 0x87, 0x2D, 0x35, 0x3D, 0xB2, 0xB6, 0xBA,\n    0xAF, 0x8C, 0x96, 0x19, 0x8F, 0x9F, 0xA7, 0x0E, 0x16, 0x1E, 0xB4, 0x9A, 0xB8, 0xAA, 0x87, 0x2C,\n    0x54, 0x7C, 0xB9, 0xA3, 0xDE, 0xDF, 0xDF, 0xA3, 0xB1, 0x80, 0xF2, 0xC4, 0xCD, 0xC9, 0xF1, 0xB8,\n    0xA9, 0xB4, 0x99, 0x83, 0x0D, 0x35, 0x5D, 0x89, 0xB9, 0xA3, 0x2D, 0x55, 0x7D, 0xB5, 0x93, 0xA3,\n    0x0E, 0x16, 0x1E, 0xA9, 0x2C, 0x54, 0x7C, 0xB8, 0xB4, 0xB0, 0xF1, 0x97, 0x83, 0xA8, 0x11, 0x84,\n    0xA5, 0x09, 0x98, 0xA3, 0x83, 0xF0, 0xDA, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xD8, 0xF1, 0xA5,\n    0x29, 0x55, 0x7D, 0xA5, 0x85, 0x95, 0x02, 0x1A, 0x2E, 0x3A, 0x56, 0x5A, 0x40, 0x48, 0xF9, 0xF3,\n    0xA3, 0xD9, 0xF8, 0xF0, 0x98, 0x83, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0x97, 0x82, 0xA8, 0xF1,\n    0x11, 0xF0, 0x98, 0xA2, 0x24, 0x08, 0x44, 0x10, 0x64, 0x18, 0xDA, 0xF3, 0xDE, 0xD8, 0x83, 0xA5,\n    0x94, 0x01, 0xD9, 0xA3, 0x02, 0xF1, 0xA2, 0xC3, 0xC5, 0xC7, 0xD8, 0xF1, 0x84, 0x92, 0xA2, 0x4D,\n    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,\n    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0x93, 0xA3, 0x4D,\n    0xDA, 0x2A, 0xD8, 0x48, 0x69, 0xD9, 0x2A, 0xD8, 0x68, 0x55, 0xDA, 0x32, 0xD8, 0x50, 0x71, 0xD9,\n    0x32, 0xD8, 0x70, 0x5D, 0xDA, 0x3A, 0xD8, 0x58, 0x79, 0xD9, 0x3A, 0xD8, 0x78, 0xA8, 0x8A, 0x9A,\n    \n    // bank 5, 256 bytes\n    0xF0, 0x28, 0x50, 0x78, 0x9E, 0xF3, 0x88, 0x18, 0xF1, 0x9F, 0x1D, 0x98, 0xA8, 0xD9, 0x08, 0xD8,\n    0xC8, 0x9F, 0x12, 0x9E, 0xF3, 0x15, 0xA8, 0xDA, 0x12, 0x10, 0xD8, 0xF1, 0xAF, 0xC8, 0x97, 0x87,\n    0x34, 0xB5, 0xB9, 0x94, 0xA4, 0x21, 0xF3, 0xD9, 0x22, 0xD8, 0xF2, 0x2D, 0xF3, 0xD9, 0x2A, 0xD8,\n    0xF2, 0x35, 0xF3, 0xD9, 0x32, 0xD8, 0x81, 0xA4, 0x60, 0x60, 0x61, 0xD9, 0x61, 0xD8, 0x6C, 0x68,\n    0x69, 0xD9, 0x69, 0xD8, 0x74, 0x70, 0x71, 0xD9, 0x71, 0xD8, 0xB1, 0xA3, 0x84, 0x19, 0x3D, 0x5D,\n    0xA3, 0x83, 0x1A, 0x3E, 0x5E, 0x93, 0x10, 0x30, 0x81, 0x10, 0x11, 0xB8, 0xB0, 0xAF, 0x8F, 0x94,\n    0xF2, 0xDA, 0x3E, 0xD8, 0xB4, 0x9A, 0xA8, 0x87, 0x29, 0xDA, 0xF8, 0xD8, 0x87, 0x9A, 0x35, 0xDA,\n    0xF8, 0xD8, 0x87, 0x9A, 0x3D, 0xDA, 0xF8, 0xD8, 0xB1, 0xB9, 0xA4, 0x98, 0x85, 0x02, 0x2E, 0x56,\n    0xA5, 0x81, 0x00, 0x0C, 0x14, 0xA3, 0x97, 0xB0, 0x8A, 0xF1, 0x2D, 0xD9, 0x28, 0xD8, 0x4D, 0xD9,\n    0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x84, 0x0D, 0xDA, 0x0E, 0xD8, 0xA3, 0x29, 0x83, 0xDA,\n    0x2C, 0x0E, 0xD8, 0xA3, 0x84, 0x49, 0x83, 0xDA, 0x2C, 0x4C, 0x0E, 0xD8, 0xB8, 0xB0, 0x97, 0x86,\n    0xA8, 0x31, 0x9B, 0x06, 0x99, 0x07, 0xAB, 0x97, 0x28, 0x88, 0x9B, 0xF0, 0x0C, 0x20, 0x14, 0x40,\n    0xB9, 0xA3, 0x8A, 0xC3, 0xC5, 0xC7, 0x9A, 0xA3, 0x28, 0x50, 0x78, 0xF1, 0xB5, 0x93, 0x01, 0xD9,\n    0xDF, 0xDF, 0xDF, 0xD8, 0xB8, 0xB4, 0xA8, 0x8C, 0x9C, 0xF0, 0x04, 0x28, 0x51, 0x79, 0x1D, 0x30,\n    0x14, 0x38, 0xB2, 0x82, 0xAB, 0xD0, 0x98, 0x2C, 0x50, 0x50, 0x78, 0x78, 0x9B, 0xF1, 0x1A, 0xB0,\n    0xF0, 0xB1, 0x83, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0xB0, 0x8B, 0x29, 0x51, 0x79, 0xB1, 0x83, 0x24,\n\n    // bank 6, 256 bytes\n    0x70, 0x59, 0xB0, 0x8B, 0x20, 0x58, 0x71, 0xB1, 0x83, 0x44, 0x69, 0x38, 0xB0, 0x8B, 0x39, 0x40,\n    0x68, 0xB1, 0x83, 0x64, 0x48, 0x31, 0xB0, 0x8B, 0x30, 0x49, 0x60, 0xA5, 0x88, 0x20, 0x09, 0x71,\n    0x58, 0x44, 0x68, 0x11, 0x39, 0x64, 0x49, 0x30, 0x19, 0xF1, 0xAC, 0x00, 0x2C, 0x54, 0x7C, 0xF0,\n    0x8C, 0xA8, 0x04, 0x28, 0x50, 0x78, 0xF1, 0x88, 0x97, 0x26, 0xA8, 0x59, 0x98, 0xAC, 0x8C, 0x02,\n    0x26, 0x46, 0x66, 0xF0, 0x89, 0x9C, 0xA8, 0x29, 0x51, 0x79, 0x24, 0x70, 0x59, 0x44, 0x69, 0x38,\n    0x64, 0x48, 0x31, 0xA9, 0x88, 0x09, 0x20, 0x59, 0x70, 0xAB, 0x11, 0x38, 0x40, 0x69, 0xA8, 0x19,\n    0x31, 0x48, 0x60, 0x8C, 0xA8, 0x3C, 0x41, 0x5C, 0x20, 0x7C, 0x00, 0xF1, 0x87, 0x98, 0x19, 0x86,\n    0xA8, 0x6E, 0x76, 0x7E, 0xA9, 0x99, 0x88, 0x2D, 0x55, 0x7D, 0x9E, 0xB9, 0xA3, 0x8A, 0x22, 0x8A,\n    0x6E, 0x8A, 0x56, 0x8A, 0x5E, 0x9F, 0xB1, 0x83, 0x06, 0x26, 0x46, 0x66, 0x0E, 0x2E, 0x4E, 0x6E,\n    0x9D, 0xB8, 0xAD, 0x00, 0x2C, 0x54, 0x7C, 0xF2, 0xB1, 0x8C, 0xB4, 0x99, 0xB9, 0xA3, 0x2D, 0x55,\n    0x7D, 0x81, 0x91, 0xAC, 0x38, 0xAD, 0x3A, 0xB5, 0x83, 0x91, 0xAC, 0x2D, 0xD9, 0x28, 0xD8, 0x4D,\n    0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0x8C, 0x9D, 0xAE, 0x29, 0xD9, 0x04, 0xAE, 0xD8, 0x51,\n    0xD9, 0x04, 0xAE, 0xD8, 0x79, 0xD9, 0x04, 0xD8, 0x81, 0xF3, 0x9D, 0xAD, 0x00, 0x8D, 0xAE, 0x19,\n    0x81, 0xAD, 0xD9, 0x01, 0xD8, 0xF2, 0xAE, 0xDA, 0x26, 0xD8, 0x8E, 0x91, 0x29, 0x83, 0xA7, 0xD9,\n    0xAD, 0xAD, 0xAD, 0xAD, 0xF3, 0x2A, 0xD8, 0xD8, 0xF1, 0xB0, 0xAC, 0x89, 0x91, 0x3E, 0x5E, 0x76,\n    0xF3, 0xAC, 0x2E, 0x2E, 0xF1, 0xB1, 0x8C, 0x5A, 0x9C, 0xAC, 0x2C, 0x28, 0x28, 0x28, 0x9C, 0xAC,\n    \n    // bank 7, 170 bytes (remainder)\n    0x30, 0x18, 0xA8, 0x98, 0x81, 0x28, 0x34, 0x3C, 0x97, 0x24, 0xA7, 0x28, 0x34, 0x3C, 0x9C, 0x24,\n    0xF2, 0xB0, 0x89, 0xAC, 0x91, 0x2C, 0x4C, 0x6C, 0x8A, 0x9B, 0x2D, 0xD9, 0xD8, 0xD8, 0x51, 0xD9,\n    0xD8, 0xD8, 0x79, 0xD9, 0xD8, 0xD8, 0xF1, 0x9E, 0x88, 0xA3, 0x31, 0xDA, 0xD8, 0xD8, 0x91, 0x2D,\n    0xD9, 0x28, 0xD8, 0x4D, 0xD9, 0x48, 0xD8, 0x6D, 0xD9, 0x68, 0xD8, 0xB1, 0x83, 0x93, 0x35, 0x3D,\n    0x80, 0x25, 0xDA, 0xD8, 0xD8, 0x85, 0x69, 0xDA, 0xD8, 0xD8, 0xB4, 0x93, 0x81, 0xA3, 0x28, 0x34,\n    0x3C, 0xF3, 0xAB, 0x8B, 0xA3, 0x91, 0xB6, 0x09, 0xB4, 0xD9, 0xAB, 0xDE, 0xB0, 0x87, 0x9C, 0xB9,\n    0xA3, 0xDD, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x95, 0xF1, 0xA3, 0xA3, 0xA3, 0x9D, 0xF1, 0xA3, 0xA3,\n    0xA3, 0xA3, 0xF2, 0xA3, 0xB4, 0x90, 0x80, 0xF2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,\n    0xA3, 0xA3, 0xB2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xB0, 0x87, 0xB5, 0x99, 0xF1, 0xA3, 0xA3,\n    0xA3, 0x98, 0xF1, 0xA3, 0xA3, 0xA3, 0xA3, 0x97, 0xA3, 0xA3, 0xA3, 0xA3, 0xF3, 0x9B, 0xA3, 0xA3,\n    0xDC, 0xB9, 0xA7, 0xF1, 0x26, 0x26, 0x26, 0xD8, 0xD8, 0xFF\n};\n\n#ifndef MPU6050_DMP_FIFO_RATE_DIVISOR \n#define MPU6050_DMP_FIFO_RATE_DIVISOR 0x03\n#endif\n\nconst unsigned char dmpConfig[MPU6050_DMP_CONFIG_SIZE] PROGMEM = {\n//  BANK    OFFSET  LENGTH  [DATA]\n    0x02,   0xEC,   0x04,   0x00, 0x47, 0x7D, 0x1A,   // ?\n    0x03,   0x82,   0x03,   0x4C, 0xCD, 0x6C,         // FCFG_1 inv_set_gyro_calibration\n    0x03,   0xB2,   0x03,   0x36, 0x56, 0x76,         // FCFG_3 inv_set_gyro_calibration\n    0x00,   0x68,   0x04,   0x02, 0xCA, 0xE3, 0x09,   // D_0_104 inv_set_gyro_calibration\n    0x01,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // D_1_152 inv_set_accel_calibration\n    0x03,   0x86,   0x03,   0x0C, 0xC9, 0x2C,         // FCFG_2 inv_set_accel_calibration\n    0x03,   0x90,   0x03,   0x26, 0x46, 0x66,         //   (continued)...FCFG_2 inv_set_accel_calibration\n    0x00,   0x6C,   0x02,   0x40, 0x00,               // D_0_108 inv_set_accel_calibration\n\n    0x02,   0x40,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_00 inv_set_compass_calibration\n    0x02,   0x44,   0x04,   0x40, 0x00, 0x00, 0x00,   // CPASS_MTX_01\n    0x02,   0x48,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_02\n    0x02,   0x4C,   0x04,   0x40, 0x00, 0x00, 0x00,   // CPASS_MTX_10\n    0x02,   0x50,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_11\n    0x02,   0x54,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_12\n    0x02,   0x58,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_20\n    0x02,   0x5C,   0x04,   0x00, 0x00, 0x00, 0x00,   // CPASS_MTX_21\n    0x02,   0xBC,   0x04,   0xC0, 0x00, 0x00, 0x00,   // CPASS_MTX_22\n\n    0x01,   0xEC,   0x04,   0x00, 0x00, 0x40, 0x00,   // D_1_236 inv_apply_endian_accel\n    0x03,   0x86,   0x06,   0x0C, 0xC9, 0x2C, 0x97, 0x97, 0x97, // FCFG_2 inv_set_mpu_sensors\n    0x04,   0x22,   0x03,   0x0D, 0x35, 0x5D,         // CFG_MOTION_BIAS inv_turn_on_bias_from_no_motion\n    0x00,   0xA3,   0x01,   0x00,                     // ?\n    0x04,   0x29,   0x04,   0x87, 0x2D, 0x35, 0x3D,   // FCFG_5 inv_set_bias_update\n    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // CFG_8 inv_send_quaternion\n    0x07,   0x9F,   0x01,   0x30,                     // CFG_16 inv_set_footer\n    0x07,   0x67,   0x01,   0x9A,                     // CFG_GYRO_SOURCE inv_send_gyro\n    0x07,   0x68,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_9 inv_send_gyro -> inv_construct3_fifo\n    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // ?\n    0x02,   0x0C,   0x04,   0x00, 0x00, 0x00, 0x00,   // ?\n    0x07,   0x83,   0x06,   0xC2, 0xCA, 0xC4, 0xA3, 0xA3, 0xA3, // ?\n                 // SPECIAL 0x01 = enable interrupts\n    0x00,   0x00,   0x00,   0x01, // SET INT_ENABLE, SPECIAL INSTRUCTION\n    0x07,   0xA7,   0x01,   0xFE,                     // ?\n    0x07,   0x62,   0x05,   0xF1, 0x20, 0x28, 0x30, 0x38, // ?\n    0x07,   0x67,   0x01,   0x9A,                     // ?\n    0x07,   0x68,   0x04,   0xF1, 0x28, 0x30, 0x38,   // CFG_12 inv_send_accel -> inv_construct3_fifo\n    0x07,   0x8D,   0x04,   0xF1, 0x28, 0x30, 0x38,   // ??? CFG_12 inv_send_mag -> inv_construct3_fifo\n    0x02,   0x16,   0x02,   0x00, MPU6050_DMP_FIFO_RATE_DIVISOR // D_0_22 inv_set_fifo_rate\n\n    // This very last 0x03 WAS a 0x09, which drops the FIFO rate down to 20 Hz. 0x07 is 25 Hz,\n    // 0x01 is 100Hz. Going faster than 100Hz (0x00=200Hz) tends to result in very noisy data.\n    // DMP output frequency is calculated easily using this equation: (200Hz / (1 + value))\n\n    // It is important to make sure the host processor can keep up with reading and processing\n    // the FIFO output at the desired rate. Handling FIFO overflow cleanly is also a good idea.\n};\n\nconst unsigned char dmpUpdates[MPU6050_DMP_UPDATES_SIZE] PROGMEM = {\n    0x01,   0xB2,   0x02,   0xFF, 0xF5,\n    0x01,   0x90,   0x04,   0x0A, 0x0D, 0x97, 0xC0,\n    0x00,   0xA3,   0x01,   0x00,\n    0x04,   0x29,   0x04,   0x87, 0x2D, 0x35, 0x3D,\n    0x01,   0x6A,   0x02,   0x06, 0x00,\n    0x01,   0x60,   0x08,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,\n    0x02,   0x60,   0x0C,   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,\n    0x01,   0x08,   0x02,   0x01, 0x20,\n    0x01,   0x0A,   0x02,   0x00, 0x4E,\n    0x01,   0x02,   0x02,   0xFE, 0xB3,\n    0x02,   0x6C,   0x04,   0x00, 0x00, 0x00, 0x00, // READ\n    0x02,   0x6C,   0x04,   0xFA, 0xFE, 0x00, 0x00,\n    0x02,   0x60,   0x0C,   0xFF, 0xFF, 0xCB, 0x4D, 0x00, 0x01, 0x08, 0xC1, 0xFF, 0xFF, 0xBC, 0x2C,\n    0x02,   0xF4,   0x04,   0x00, 0x00, 0x00, 0x00,\n    0x02,   0xF8,   0x04,   0x00, 0x00, 0x00, 0x00,\n    0x02,   0xFC,   0x04,   0x00, 0x00, 0x00, 0x00,\n    0x00,   0x60,   0x04,   0x40, 0x00, 0x00, 0x00,\n    0x00,   0x60,   0x04,   0x00, 0x40, 0x00, 0x00\n};\n\nuint8_t MPU6050::dmpInitialize() {\n    // reset device\n    DEBUG_PRINTLN(F(\"\\n\\nResetting MPU6050...\"));\n    reset();\n    delay(30); // wait after reset\n\n    // disable sleep mode\n    DEBUG_PRINTLN(F(\"Disabling sleep mode...\"));\n    setSleepEnabled(false);\n\n    // get MPU product ID\n    DEBUG_PRINTLN(F(\"Getting product ID...\"));\n    //uint8_t productID = 0; //getProductID();\n    DEBUG_PRINT(F(\"Product ID = \"));\n    DEBUG_PRINT(productID);\n\n    // get MPU hardware revision\n    DEBUG_PRINTLN(F(\"Selecting user bank 16...\"));\n    setMemoryBank(0x10, true, true);\n    DEBUG_PRINTLN(F(\"Selecting memory byte 6...\"));\n    setMemoryStartAddress(0x06);\n    DEBUG_PRINTLN(F(\"Checking hardware revision...\"));\n    uint8_t hwRevision = readMemoryByte();\n    DEBUG_PRINT(F(\"Revision @ user[16][6] = \"));\n    DEBUG_PRINTLNF(hwRevision, HEX);\n    DEBUG_PRINTLN(F(\"Resetting memory bank selection to 0...\"));\n    setMemoryBank(0, false, false);\n\n    // check OTP bank valid\n    DEBUG_PRINTLN(F(\"Reading OTP bank valid flag...\"));\n    uint8_t otpValid = getOTPBankValid();\n    DEBUG_PRINT(F(\"OTP bank is \"));\n    DEBUG_PRINTLN(otpValid ? F(\"valid!\") : F(\"invalid!\"));\n\n    // get X/Y/Z gyro offsets\n    DEBUG_PRINTLN(F(\"Reading gyro offset values...\"));\n    int8_t xgOffset = getXGyroOffset();\n    int8_t ygOffset = getYGyroOffset();\n    int8_t zgOffset = getZGyroOffset();\n    DEBUG_PRINT(F(\"X gyro offset = \"));\n    DEBUG_PRINTLN(xgOffset);\n    DEBUG_PRINT(F(\"Y gyro offset = \"));\n    DEBUG_PRINTLN(ygOffset);\n    DEBUG_PRINT(F(\"Z gyro offset = \"));\n    DEBUG_PRINTLN(zgOffset);\n    \n    I2Cdev::readByte(devAddr, MPU6050_RA_USER_CTRL, buffer); // ?\n    \n    DEBUG_PRINTLN(F(\"Enabling interrupt latch, clear on any read, AUX bypass enabled\"));\n    I2Cdev::writeByte(devAddr, MPU6050_RA_INT_PIN_CFG, 0x32);\n\n    // enable MPU AUX I2C bypass mode\n    //DEBUG_PRINTLN(F(\"Enabling AUX I2C bypass mode...\"));\n    //setI2CBypassEnabled(true);\n\n    DEBUG_PRINTLN(F(\"Setting magnetometer mode to power-down...\"));\n    //mag -> setMode(0);\n    I2Cdev::writeByte(0x0E, 0x0A, 0x00);\n\n    DEBUG_PRINTLN(F(\"Setting magnetometer mode to fuse access...\"));\n    //mag -> setMode(0x0F);\n    I2Cdev::writeByte(0x0E, 0x0A, 0x0F);\n\n    DEBUG_PRINTLN(F(\"Reading mag magnetometer factory calibration...\"));\n    int8_t asax, asay, asaz;\n    //mag -> getAdjustment(&asax, &asay, &asaz);\n    I2Cdev::readBytes(0x0E, 0x10, 3, buffer);\n    asax = (int8_t)buffer[0];\n    asay = (int8_t)buffer[1];\n    asaz = (int8_t)buffer[2];\n    DEBUG_PRINT(F(\"Adjustment X/Y/Z = \"));\n    DEBUG_PRINT(asax);\n    DEBUG_PRINT(F(\" / \"));\n    DEBUG_PRINT(asay);\n    DEBUG_PRINT(F(\" / \"));\n    DEBUG_PRINTLN(asaz);\n\n    DEBUG_PRINTLN(F(\"Setting magnetometer mode to power-down...\"));\n    //mag -> setMode(0);\n    I2Cdev::writeByte(0x0E, 0x0A, 0x00);\n\n    // load DMP code into memory banks\n    DEBUG_PRINT(F(\"Writing DMP code to MPU memory banks (\"));\n    DEBUG_PRINT(MPU6050_DMP_CODE_SIZE);\n    DEBUG_PRINTLN(F(\" bytes)\"));\n    if (writeProgMemoryBlock(dmpMemory, MPU6050_DMP_CODE_SIZE)) {\n        DEBUG_PRINTLN(F(\"Success! DMP code written and verified.\"));\n\n        DEBUG_PRINTLN(F(\"Configuring DMP and related settings...\"));\n\n        // write DMP configuration\n        DEBUG_PRINT(F(\"Writing DMP configuration to MPU memory banks (\"));\n        DEBUG_PRINT(MPU6050_DMP_CONFIG_SIZE);\n        DEBUG_PRINTLN(F(\" bytes in config def)\"));\n        if (writeProgDMPConfigurationSet(dmpConfig, MPU6050_DMP_CONFIG_SIZE)) {\n            DEBUG_PRINTLN(F(\"Success! DMP configuration written and verified.\"));\n\n            DEBUG_PRINTLN(F(\"Setting DMP and FIFO_OFLOW interrupts enabled...\"));\n            setIntEnabled(1<<MPU6050_INTERRUPT_FIFO_OFLOW_BIT|1<<MPU6050_INTERRUPT_DMP_INT_BIT);\n\n            DEBUG_PRINTLN(F(\"Setting sample rate to 200Hz...\"));\n            setRate(4); // 1khz / (1 + 4) = 200 Hz\n\n            DEBUG_PRINTLN(F(\"Setting clock source to Z Gyro...\"));\n            setClockSource(MPU6050_CLOCK_PLL_ZGYRO);\n\n            DEBUG_PRINTLN(F(\"Setting DLPF bandwidth to 42Hz...\"));\n            setDLPFMode(MPU6050_DLPF_BW_42);\n\n            DEBUG_PRINTLN(F(\"Setting external frame sync to TEMP_OUT_L[0]...\"));\n            setExternalFrameSync(MPU6050_EXT_SYNC_TEMP_OUT_L);\n\n            DEBUG_PRINTLN(F(\"Setting gyro sensitivity to +/- 2000 deg/sec...\"));\n            setFullScaleGyroRange(MPU6050_GYRO_FS_2000);\n\n            DEBUG_PRINTLN(F(\"Setting DMP configuration bytes (function unknown)...\"));\n            setDMPConfig1(0x03);\n            setDMPConfig2(0x00);\n\n            DEBUG_PRINTLN(F(\"Clearing OTP Bank flag...\"));\n            setOTPBankValid(false);\n\n            DEBUG_PRINTLN(F(\"Setting X/Y/Z gyro offsets to previous values...\"));\n            setXGyroOffsetTC(xgOffset);\n            setYGyroOffsetTC(ygOffset);\n            setZGyroOffsetTC(zgOffset);\n\n            //DEBUG_PRINTLN(F(\"Setting X/Y/Z gyro user offsets to zero...\"));\n            //setXGyroOffset(0);\n            //setYGyroOffset(0);\n            //setZGyroOffset(0);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 1/19 (function unknown)...\"));\n            uint8_t dmpUpdate[16], j;\n            uint16_t pos = 0;\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 2/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Resetting FIFO...\"));\n            resetFIFO();\n\n            DEBUG_PRINTLN(F(\"Reading FIFO count...\"));\n            uint8_t fifoCount = getFIFOCount();\n\n            DEBUG_PRINT(F(\"Current FIFO count=\"));\n            DEBUG_PRINTLN(fifoCount);\n            uint8_t fifoBuffer[128];\n            //getFIFOBytes(fifoBuffer, fifoCount);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 3/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 4/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Disabling all standby flags...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_PWR_MGMT_2, 0x00);\n\n            DEBUG_PRINTLN(F(\"Setting accelerometer sensitivity to +/- 2g...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_ACCEL_CONFIG, 0x00);\n\n            DEBUG_PRINTLN(F(\"Setting motion detection threshold to 2...\"));\n            setMotionDetectionThreshold(2);\n\n            DEBUG_PRINTLN(F(\"Setting zero-motion detection threshold to 156...\"));\n            setZeroMotionDetectionThreshold(156);\n\n            DEBUG_PRINTLN(F(\"Setting motion detection duration to 80...\"));\n            setMotionDetectionDuration(80);\n\n            DEBUG_PRINTLN(F(\"Setting zero-motion detection duration to 0...\"));\n            setZeroMotionDetectionDuration(0);\n\n            DEBUG_PRINTLN(F(\"Setting AK8975 to single measurement mode...\"));\n            //mag -> setMode(1);\n            I2Cdev::writeByte(0x0E, 0x0A, 0x01);\n\n            // setup AK8975 (0x0E) as Slave 0 in read mode\n            DEBUG_PRINTLN(F(\"Setting up AK8975 read slave 0...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_ADDR, 0x8E);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_REG,  0x01);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV0_CTRL, 0xDA);\n\n            // setup AK8975 (0x0E) as Slave 2 in write mode\n            DEBUG_PRINTLN(F(\"Setting up AK8975 write slave 2...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_ADDR, 0x0E);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_REG,  0x0A);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_CTRL, 0x81);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV2_DO,   0x01);\n\n            // setup I2C timing/delay control\n            DEBUG_PRINTLN(F(\"Setting up slave access delay...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_SLV4_CTRL, 0x18);\n            I2Cdev::writeByte(0x68, MPU6050_RA_I2C_MST_DELAY_CTRL, 0x05);\n\n            // enable interrupts\n            DEBUG_PRINTLN(F(\"Enabling default interrupt behavior/no bypass...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_INT_PIN_CFG, 0x00);\n\n            // enable I2C master mode and reset DMP/FIFO\n            DEBUG_PRINTLN(F(\"Enabling I2C master mode...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x20);\n            DEBUG_PRINTLN(F(\"Resetting FIFO...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x24);\n            DEBUG_PRINTLN(F(\"Rewriting I2C master mode enabled because...I don't know\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0x20);\n            DEBUG_PRINTLN(F(\"Enabling and resetting DMP/FIFO...\"));\n            I2Cdev::writeByte(0x68, MPU6050_RA_USER_CTRL, 0xE8);\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 5/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 6/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 7/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 8/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 9/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 10/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 11/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            \n            DEBUG_PRINTLN(F(\"Reading final memory update 12/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            readMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            #ifdef DEBUG\n                DEBUG_PRINT(F(\"Read bytes: \"));\n                for (j = 0; j < 4; j++) {\n                    DEBUG_PRINTF(dmpUpdate[3 + j], HEX);\n                    DEBUG_PRINT(\" \");\n                }\n                DEBUG_PRINTLN(\"\");\n            #endif\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 13/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 14/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 15/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 16/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n            DEBUG_PRINTLN(F(\"Writing final memory update 17/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Waiting for FIRO count >= 46...\"));\n            while ((fifoCount = getFIFOCount()) < 46);\n            DEBUG_PRINTLN(F(\"Reading FIFO...\"));\n            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes\n            DEBUG_PRINTLN(F(\"Reading interrupt status...\"));\n            getIntStatus();\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 18/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Waiting for FIRO count >= 48...\"));\n            while ((fifoCount = getFIFOCount()) < 48);\n            DEBUG_PRINTLN(F(\"Reading FIFO...\"));\n            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes\n            DEBUG_PRINTLN(F(\"Reading interrupt status...\"));\n            getIntStatus();\n            DEBUG_PRINTLN(F(\"Waiting for FIRO count >= 48...\"));\n            while ((fifoCount = getFIFOCount()) < 48);\n            DEBUG_PRINTLN(F(\"Reading FIFO...\"));\n            getFIFOBytes(fifoBuffer, min(fifoCount, 128)); // safeguard only 128 bytes\n            DEBUG_PRINTLN(F(\"Reading interrupt status...\"));\n            getIntStatus();\n\n            DEBUG_PRINTLN(F(\"Writing final memory update 19/19 (function unknown)...\"));\n            for (j = 0; j < 4 || j < dmpUpdate[2] + 3; j++, pos++) dmpUpdate[j] = pgm_read_byte(&dmpUpdates[pos]);\n            writeMemoryBlock(dmpUpdate + 3, dmpUpdate[2], dmpUpdate[0], dmpUpdate[1]);\n\n            DEBUG_PRINTLN(F(\"Disabling DMP (you turn it on later)...\"));\n            setDMPEnabled(false);\n\n            DEBUG_PRINTLN(F(\"Setting up internal 48-byte (default) DMP packet buffer...\"));\n            dmpPacketSize = 48;\n            /*if ((dmpPacketBuffer = (uint8_t *)malloc(42)) == 0) {\n                return 3; // TODO: proper error code for no memory\n            }*/\n\n            DEBUG_PRINTLN(F(\"Resetting FIFO and clearing INT status one last time...\"));\n            resetFIFO();\n            getIntStatus();\n        } else {\n            DEBUG_PRINTLN(F(\"ERROR! DMP configuration verification failed.\"));\n            return 2; // configuration block loading failed\n        }\n    } else {\n        DEBUG_PRINTLN(F(\"ERROR! DMP code verification failed.\"));\n        return 1; // main binary block loading failed\n    }\n    return 0; // success\n}\n\nbool MPU6050::dmpPacketAvailable() {\n    return getFIFOCount() >= dmpGetFIFOPacketSize();\n}\n\n// uint8_t MPU6050::dmpSetFIFORate(uint8_t fifoRate);\n// uint8_t MPU6050::dmpGetFIFORate();\n// uint8_t MPU6050::dmpGetSampleStepSizeMS();\n// uint8_t MPU6050::dmpGetSampleFrequency();\n// int32_t MPU6050::dmpDecodeTemperature(int8_t tempReg);\n\n//uint8_t MPU6050::dmpRegisterFIFORateProcess(inv_obj_func func, int16_t priority);\n//uint8_t MPU6050::dmpUnregisterFIFORateProcess(inv_obj_func func);\n//uint8_t MPU6050::dmpRunFIFORateProcesses();\n\n// uint8_t MPU6050::dmpSendQuaternion(uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendGyro(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendLinearAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendLinearAccelInWorld(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendControlData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendExternalSensorData(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendGravity(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendPacketNumber(uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendQuantizedAccel(uint_fast16_t elements, uint_fast16_t accuracy);\n// uint8_t MPU6050::dmpSendEIS(uint_fast16_t elements, uint_fast16_t accuracy);\n\nuint8_t MPU6050::dmpGetAccel(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[34] << 24) | ((uint32_t)packet[35] << 16) | ((uint32_t)packet[36] << 8) | packet[37]);\n    data[1] = (((uint32_t)packet[38] << 24) | ((uint32_t)packet[39] << 16) | ((uint32_t)packet[40] << 8) | packet[41]);\n    data[2] = (((uint32_t)packet[42] << 24) | ((uint32_t)packet[43] << 16) | ((uint32_t)packet[44] << 8) | packet[45]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetAccel(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (packet[34] << 8) | packet[35];\n    data[1] = (packet[38] << 8) | packet[39];\n    data[2] = (packet[42] << 8) | packet[43];\n    return 0;\n}\nuint8_t MPU6050::dmpGetAccel(VectorInt16 *v, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    v -> x = (packet[34] << 8) | packet[35];\n    v -> y = (packet[38] << 8) | packet[39];\n    v -> z = (packet[42] << 8) | packet[43];\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[0] << 24) | ((uint32_t)packet[1] << 16) | ((uint32_t)packet[2] << 8) | packet[3]);\n    data[1] = (((uint32_t)packet[4] << 24) | ((uint32_t)packet[5] << 16) | ((uint32_t)packet[6] << 8) | packet[7]);\n    data[2] = (((uint32_t)packet[8] << 24) | ((uint32_t)packet[9] << 16) | ((uint32_t)packet[10] << 8) | packet[11]);\n    data[3] = (((uint32_t)packet[12] << 24) | ((uint32_t)packet[13] << 16) | ((uint32_t)packet[14] << 8) | packet[15]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = ((packet[0] << 8) | packet[1]);\n    data[1] = ((packet[4] << 8) | packet[5]);\n    data[2] = ((packet[8] << 8) | packet[9]);\n    data[3] = ((packet[12] << 8) | packet[13]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetQuaternion(Quaternion *q, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    int16_t qI[4];\n    uint8_t status = dmpGetQuaternion(qI, packet);\n    if (status == 0) {\n        q -> w = (float)qI[0] / 16384.0f;\n        q -> x = (float)qI[1] / 16384.0f;\n        q -> y = (float)qI[2] / 16384.0f;\n        q -> z = (float)qI[3] / 16384.0f;\n        return 0;\n    }\n    return status; // int16 return value, indicates error if this line is reached\n}\n// uint8_t MPU6050::dmpGet6AxisQuaternion(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetRelativeQuaternion(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetGyro(int32_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (((uint32_t)packet[16] << 24) | ((uint32_t)packet[17] << 16) | ((uint32_t)packet[18] << 8) | packet[19]);\n    data[1] = (((uint32_t)packet[20] << 24) | ((uint32_t)packet[21] << 16) | ((uint32_t)packet[22] << 8) | packet[23]);\n    data[2] = (((uint32_t)packet[24] << 24) | ((uint32_t)packet[25] << 16) | ((uint32_t)packet[26] << 8) | packet[27]);\n    return 0;\n}\nuint8_t MPU6050::dmpGetGyro(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (packet[16] << 8) | packet[17];\n    data[1] = (packet[20] << 8) | packet[21];\n    data[2] = (packet[24] << 8) | packet[25];\n    return 0;\n}\nuint8_t MPU6050::dmpGetMag(int16_t *data, const uint8_t* packet) {\n    // TODO: accommodate different arrangements of sent data (ONLY default supported now)\n    if (packet == 0) packet = dmpPacketBuffer;\n    data[0] = (packet[28] << 8) | packet[29];\n    data[1] = (packet[30] << 8) | packet[31];\n    data[2] = (packet[32] << 8) | packet[33];\n    return 0;\n}\n// uint8_t MPU6050::dmpSetLinearAccelFilterCoefficient(float coef);\n// uint8_t MPU6050::dmpGetLinearAccel(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetLinearAccel(VectorInt16 *v, VectorInt16 *vRaw, VectorFloat *gravity) {\n    // get rid of the gravity component (+1g = +4096 in standard DMP FIFO packet)\n    v -> x = vRaw -> x - gravity -> x*4096;\n    v -> y = vRaw -> y - gravity -> y*4096;\n    v -> z = vRaw -> z - gravity -> z*4096;\n    return 0;\n}\n// uint8_t MPU6050::dmpGetLinearAccelInWorld(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetLinearAccelInWorld(VectorInt16 *v, VectorInt16 *vReal, Quaternion *q) {\n    // rotate measured 3D acceleration vector into original state\n    // frame of reference based on orientation quaternion\n    memcpy(v, vReal, sizeof(VectorInt16));\n    v -> rotate(q);\n    return 0;\n}\n// uint8_t MPU6050::dmpGetGyroAndAccelSensor(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetGyroSensor(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetControlData(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetTemperature(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetGravity(long *data, const uint8_t* packet);\nuint8_t MPU6050::dmpGetGravity(int16_t *data, const uint8_t* packet) {\n    /* +1g corresponds to +8192, sensitivity is 2g. */\n    int16_t qI[4];\n    uint8_t status = dmpGetQuaternion(qI, packet);\n    data[0] = ((int32_t)qI[1] * qI[3] - (int32_t)qI[0] * qI[2]) / 16384;\n    data[1] = ((int32_t)qI[0] * qI[1] + (int32_t)qI[2] * qI[3]) / 16384;\n    data[2] = ((int32_t)qI[0] * qI[0] - (int32_t)qI[1] * qI[1]\n\t       - (int32_t)qI[2] * qI[2] + (int32_t)qI[3] * qI[3]) / (2 * 16384);\n    return status;\n}\n\nuint8_t MPU6050::dmpGetGravity(VectorFloat *v, Quaternion *q) {\n    v -> x = 2 * (q -> x*q -> z - q -> w*q -> y);\n    v -> y = 2 * (q -> w*q -> x + q -> y*q -> z);\n    v -> z = q -> w*q -> w - q -> x*q -> x - q -> y*q -> y + q -> z*q -> z;\n    return 0;\n}\n// uint8_t MPU6050::dmpGetUnquantizedAccel(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetQuantizedAccel(long *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetExternalSensorData(long *data, int size, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetEIS(long *data, const uint8_t* packet);\n\nuint8_t MPU6050::dmpGetEuler(float *data, Quaternion *q) {\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);   // psi\n    data[1] = -asin(2*q -> x*q -> z + 2*q -> w*q -> y);                              // theta\n    data[2] = atan2(2*q -> y*q -> z - 2*q -> w*q -> x, 2*q -> w*q -> w + 2*q -> z*q -> z - 1);   // phi\n    return 0;\n}\n\n#ifdef USE_OLD_DMPGETYAWPITCHROLL\nuint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {\n    // yaw: (about Z axis)\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);\n    // pitch: (nose up/down, about Y axis)\n    data[1] = atan(gravity -> x / sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));\n    // roll: (tilt left/right, about X axis)\n    data[2] = atan(gravity -> y / sqrt(gravity -> x*gravity -> x + gravity -> z*gravity -> z));\n    return 0;\n}\n#else \nuint8_t MPU6050::dmpGetYawPitchRoll(float *data, Quaternion *q, VectorFloat *gravity) {\n    // yaw: (about Z axis)\n    data[0] = atan2(2*q -> x*q -> y - 2*q -> w*q -> z, 2*q -> w*q -> w + 2*q -> x*q -> x - 1);\n    // pitch: (nose up/down, about Y axis)\n    data[1] = atan2(gravity -> x , sqrt(gravity -> y*gravity -> y + gravity -> z*gravity -> z));\n    // roll: (tilt left/right, about X axis)\n    data[2] = atan2(gravity -> y , gravity -> z);\n    if(gravity->z<0) {\n        if(data[1]>0) {\n            data[1] = PI - data[1]; \n        } else { \n            data[1] = -PI - data[1];\n        }\n    }\n    return 0;\n}\n#endif\n\n// uint8_t MPU6050::dmpGetAccelFloat(float *data, const uint8_t* packet);\n// uint8_t MPU6050::dmpGetQuaternionFloat(float *data, const uint8_t* packet);\n\nuint8_t MPU6050::dmpProcessFIFOPacket(const unsigned char *dmpData) {\n    /*for (uint8_t k = 0; k < dmpPacketSize; k++) {\n        if (dmpData[k] < 0x10) Serial.print(\"0\");\n        Serial.print(dmpData[k], HEX);\n        Serial.print(\" \");\n    }\n    Serial.print(\"\\n\");*/\n    //Serial.println((uint16_t)dmpPacketBuffer);\n    return 0;\n}\nuint8_t MPU6050::dmpReadAndProcessFIFOPacket(uint8_t numPackets, uint8_t *processed) {\n    uint8_t status;\n    uint8_t buf[dmpPacketSize];\n    for (uint8_t i = 0; i < numPackets; i++) {\n        // read packet from FIFO\n        getFIFOBytes(buf, dmpPacketSize);\n\n        // process packet\n        if ((status = dmpProcessFIFOPacket(buf)) > 0) return status;\n        \n        // increment external process count variable, if supplied\n        if (processed != 0) *processed++;\n    }\n    return 0;\n}\n\n// uint8_t MPU6050::dmpSetFIFOProcessedCallback(void (*func) (void));\n\n// uint8_t MPU6050::dmpInitFIFOParam();\n// uint8_t MPU6050::dmpCloseFIFO();\n// uint8_t MPU6050::dmpSetGyroDataSource(uint_fast8_t source);\n// uint8_t MPU6050::dmpDecodeQuantizedAccel();\n// uint32_t MPU6050::dmpGetGyroSumOfSquare();\n// uint32_t MPU6050::dmpGetAccelSumOfSquare();\n// void MPU6050::dmpOverrideQuaternion(long *q);\nuint16_t MPU6050::dmpGetFIFOPacketSize() {\n    return dmpPacketSize;\n}\n\n#endif /* _MPU6050_9AXIS_MOTIONAPPS41_H_ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/filters/biquad_filter.c",
    "content": "#include <stdbool.h>\n#include <stdint.h>\n#include <string.h>\n#include <math.h>\n\n#include \"biquad_filter.h\"\n#include \"filter_math.h\"\n\n#define BIQUAD_Q 1.0f / sqrtf(2.0f)     /* quality factor - 2nd order butterworth*/\n\n// NULL filter\n\nfloat nullFilterApply(filter_t *filter, float input)\n{\n    (void) (filter);\n    return input;\n}\n\n\n// PT1 Low Pass filter\n\nfloat pt1FilterGain(float f_cut, float dT)\n{\n    float RC = 1 / (2 * M_PIf * f_cut);\n    return dT / (RC + dT);\n}\n\nvoid pt1FilterInit(pt1Filter_t *filter, float k)\n{\n    filter->state = 0.0f;\n    filter->k = k;\n}\n\nvoid pt1FilterUpdateCutoff(pt1Filter_t *filter, float k)\n{\n    filter->k = k;\n}\n\nfloat pt1FilterApply(pt1Filter_t *filter, float input)\n{\n    filter->state = filter->state + filter->k * (input - filter->state);\n    return filter->state;\n}\n\n// PT2 Low Pass filter\n\nfloat pt2FilterGain(float f_cut, float dT)\n{\n    const float order = 2.0f;\n    const float orderCutoffCorrection = 1 / sqrtf(powf(2, 1.0f / order) - 1);\n    float RC = 1 / (2 * orderCutoffCorrection * M_PIf * f_cut);\n    // float RC = 1 / (2 * 1.553773974f * M_PIf * f_cut);\n    // where 1.553773974 = 1 / sqrt( (2^(1 / order) - 1) ) and order is 2\n    return dT / (RC + dT);\n}\n\nvoid pt2FilterInit(pt2Filter_t *filter, float k)\n{\n    filter->state = 0.0f;\n    filter->state1 = 0.0f;\n    filter->k = k;\n}\n\nvoid pt2FilterUpdateCutoff(pt2Filter_t *filter, float k)\n{\n    filter->k = k;\n}\n\nfloat pt2FilterApply(pt2Filter_t *filter, float input)\n{\n    filter->state1 = filter->state1 + filter->k * (input - filter->state1);\n    filter->state = filter->state + filter->k * (filter->state1 - filter->state);\n    return filter->state;\n}\n\n// PT3 Low Pass filter\n\nfloat pt3FilterGain(float f_cut, float dT)\n{\n    const float order = 3.0f;\n    const float orderCutoffCorrection = 1 / sqrtf(powf(2, 1.0f / order) - 1);\n    float RC = 1 / (2 * orderCutoffCorrection * M_PIf * f_cut);\n    // float RC = 1 / (2 * 1.961459177f * M_PIf * f_cut);\n    // where 1.961459177 = 1 / sqrt( (2^(1 / order) - 1) ) and order is 3\n    return dT / (RC + dT);\n}\n\nvoid pt3FilterInit(pt3Filter_t *filter, float k)\n{\n    filter->state = 0.0f;\n    filter->state1 = 0.0f;\n    filter->state2 = 0.0f;\n    filter->k = k;\n}\n\nvoid pt3FilterUpdateCutoff(pt3Filter_t *filter, float k)\n{\n    filter->k = k;\n}\n\nfloat pt3FilterApply(pt3Filter_t *filter, float input)\n{\n    filter->state1 = filter->state1 + filter->k * (input - filter->state1);\n    filter->state2 = filter->state2 + filter->k * (filter->state1 - filter->state2);\n    filter->state = filter->state + filter->k * (filter->state2 - filter->state);\n    return filter->state;\n}\n\n\n// Slew filter with limit\n\nvoid slewFilterInit(slewFilter_t *filter, float slewLimit, float threshold)\n{\n    filter->state = 0.0f;\n    filter->slewLimit = slewLimit;\n    filter->threshold = threshold;\n}\n\nfloat slewFilterApply(slewFilter_t *filter, float input)\n{\n    if (filter->state >= filter->threshold)\n    {\n        if (input >= filter->state - filter->slewLimit)\n        {\n            filter->state = input;\n        }\n    } else if (filter->state <= -filter->threshold)\n    {\n        if (input <= filter->state + filter->slewLimit)\n        {\n            filter->state = input;\n        }\n    } else\n    {\n        filter->state = input;\n    }\n    return filter->state;\n}\n\n// get notch filter Q given center frequency (f0) and lower cutoff frequency (f1)\n// Q = f0 / (f2 - f1) ; f2 = f0^2 / f1\nfloat filterGetNotchQ(float centerFreq, float cutoffFreq)\n{\n    return centerFreq * cutoffFreq / (centerFreq * centerFreq - cutoffFreq * cutoffFreq);\n}\n\n/* sets up a biquad filter as a 2nd order butterworth LPF */\nvoid biquadFilterInitLPF(BiquadFilter_t *filter, float _filterCallFreq, float _cutoffFreq)\n{\n    biquadFilterInit(filter, _filterCallFreq, _cutoffFreq, BIQUAD_Q, FILTER_LPF);\n}\n\nvoid\nbiquadFilterInit(BiquadFilter_t *filter, float _filterCallFreq, float _cutoffFreq, float Q,\n                 biquadFilterType_e filterType)\n{\n    biquadFilterUpdate(filter, _filterCallFreq, _cutoffFreq, Q, filterType);\n\n    // zero initial samples\n    filter->x1 = filter->x2 = 0;\n    filter->y1 = filter->y2 = 0;\n}\n\nvoid biquadFilterUpdate(BiquadFilter_t *filter, float _filterCallFreq, float _cutoffFreq, float Q,\n                        biquadFilterType_e filterType)\n{\n    // setup variables\n    const float omega = 2.0f * M_PIf * _filterCallFreq * _cutoffFreq * 0.000001f;\n    const float sn = sin_approx(omega);\n    const float cs = cos_approx(omega);\n    const float alpha = sn / (2.0f * Q);\n\n    switch (filterType)\n    {\n        case FILTER_LPF:\n            // 2nd order Butterworth (with Q=1/sqrt(2)) / Butterworth biquad section with Q\n            // described in http://www.ti.com/lit/an/slaa447/slaa447.pdf\n            filter->b1 = 1 - cs;\n            filter->b0 = filter->b1 * 0.5f;\n            filter->b2 = filter->b0;\n            filter->a1 = -2 * cs;\n            filter->a2 = 1 - alpha;\n            break;\n        case FILTER_NOTCH:\n            filter->b0 = 1;\n            filter->b1 = -2 * cs;\n            filter->b2 = 1;\n            filter->a1 = filter->b1;\n            filter->a2 = 1 - alpha;\n            break;\n        case FILTER_BPF:\n            filter->b0 = alpha;\n            filter->b1 = 0;\n            filter->b2 = -alpha;\n            filter->a1 = -2 * cs;\n            filter->a2 = 1 - alpha;\n            break;\n    }\n\n    const float a0 = 1 + alpha;\n\n    // precompute the coefficients\n    filter->b0 /= a0;\n    filter->b1 /= a0;\n    filter->b2 /= a0;\n    filter->a1 /= a0;\n    filter->a2 /= a0;\n}\n\nvoid biquadFilterUpdateLPF(BiquadFilter_t *filter, float filterFreq, float refreshRate)\n{\n    biquadFilterUpdate(filter, filterFreq, refreshRate, BIQUAD_Q, FILTER_LPF);\n}\n\n/* Computes a biquadFilter_t filter on a sample (slightly less precise than df2 but works in dynamic mode) */\nfloat biquadFilterApplyDF1(BiquadFilter_t *filter, float input)\n{\n    /* compute result */\n    const float result =\n        filter->b0 * input + filter->b1 * filter->x1 + filter->b2 * filter->x2 - filter->a1 * filter->y1 -\n        filter->a2 * filter->y2;\n\n    /* shift x1 to x2, input to x1 */\n    filter->x2 = filter->x1;\n    filter->x1 = input;\n\n    /* shift y1 to y2, result to y1 */\n    filter->y2 = filter->y1;\n    filter->y1 = result;\n\n    return result;\n}\n\n/* Computes a biquadFilter_t filter in direct form 2 on a sample (higher precision but can't handle changes in coefficients */\nfloat biquadFilterApply(BiquadFilter_t *filter, float input)\n{\n    const float result = filter->b0 * input + filter->x1;\n    filter->x1 = filter->b1 * input - filter->a1 * result + filter->x2;\n    filter->x2 = filter->b2 * input - filter->a2 * result;\n    return result;\n}\n\nvoid laggedMovingAverageInit(laggedMovingAverage_t *filter, uint16_t windowSize, float *buf)\n{\n    filter->movingWindowIndex = 0;\n    filter->windowSize = windowSize;\n    filter->buf = buf;\n    filter->movingSum = 0;\n    memset(filter->buf, 0, windowSize * sizeof(float));\n    filter->primed = false;\n}\n\nfloat laggedMovingAverageUpdate(laggedMovingAverage_t *filter, float input)\n{\n    filter->movingSum -= filter->buf[filter->movingWindowIndex];\n    filter->buf[filter->movingWindowIndex] = input;\n    filter->movingSum += input;\n\n    if (++filter->movingWindowIndex == filter->windowSize)\n    {\n        filter->movingWindowIndex = 0;\n        filter->primed = true;\n    }\n\n    const uint16_t denom = filter->primed ? filter->windowSize : filter->movingWindowIndex;\n    return filter->movingSum / denom;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/filters/biquad_filter.h",
    "content": "#ifndef __FILTER_H\n#define __FILTER_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\nstruct filter_s;\ntypedef struct filter_s filter_t;\n\ntypedef struct pt1Filter_s\n{\n    float state;\n    float k;\n} pt1Filter_t;\n\ntypedef struct pt2Filter_s\n{\n    float state;\n    float state1;\n    float k;\n} pt2Filter_t;\n\ntypedef struct pt3Filter_s\n{\n    float state;\n    float state1;\n    float state2;\n    float k;\n} pt3Filter_t;\n\ntypedef struct slewFilter_s\n{\n    float state;\n    float slewLimit;\n    float threshold;\n} slewFilter_t;\n\n/* this holds the data required to update samples thru a filter */\ntypedef struct biquadFilter_s\n{\n    float b0, b1, b2, a1, a2;\n    float x1, x2, y1, y2;\n} BiquadFilter_t;\n\ntypedef struct laggedMovingAverage_s\n{\n    uint16_t movingWindowIndex;\n    uint16_t windowSize;\n    float movingSum;\n    float *buf;\n    uint8_t primed;\n} laggedMovingAverage_t;\n\ntypedef enum\n{\n    FILTER_PT1 = 0,\n    FILTER_BIQUAD,\n    FILTER_PT2,\n    FILTER_PT3,\n} lowpassFilterType_e;\n\ntypedef enum\n{\n    FILTER_LPF,    // 2nd order Butterworth section\n    FILTER_NOTCH,\n    FILTER_BPF,\n} biquadFilterType_e;\n\ntypedef float (*filterApplyFnPtr)(filter_t *filter, float input);\n\nfloat nullFilterApply(filter_t *filter, float input);\n\nvoid biquadFilterInitLPF(BiquadFilter_t *filter, float _filterCallFreq, float _cutoffFreq);\n\nvoid biquadFilterInit(BiquadFilter_t *filter, float _filterCallFreq, float _cutoffFreq, float Q,\n                      biquadFilterType_e filterType);\n\nvoid biquadFilterUpdate(BiquadFilter_t *filter,float _filterCallFreq, float _cutoffFreq, float Q,\n                        biquadFilterType_e filterType);\n\nvoid biquadFilterUpdateLPF(BiquadFilter_t *filter, float filterFreq, float refreshRate);\n\nfloat biquadFilterApplyDF1(BiquadFilter_t *filter, float input);\n\nfloat biquadFilterApply(BiquadFilter_t *filter, float input);\n\nfloat filterGetNotchQ(float centerFreq, float cutoffFreq);\n\nvoid laggedMovingAverageInit(laggedMovingAverage_t *filter, uint16_t windowSize, float *buf);\n\nfloat laggedMovingAverageUpdate(laggedMovingAverage_t *filter, float input);\n\nfloat pt1FilterGain(float f_cut, float dT);\n\nvoid pt1FilterInit(pt1Filter_t *filter, float k);\n\nvoid pt1FilterUpdateCutoff(pt1Filter_t *filter, float k);\n\nfloat pt1FilterApply(pt1Filter_t *filter, float input);\n\nfloat pt2FilterGain(float f_cut, float dT);\n\nvoid pt2FilterInit(pt2Filter_t *filter, float k);\n\nvoid pt2FilterUpdateCutoff(pt2Filter_t *filter, float k);\n\nfloat pt2FilterApply(pt2Filter_t *filter, float input);\n\nfloat pt3FilterGain(float f_cut, float dT);\n\nvoid pt3FilterInit(pt3Filter_t *filter, float k);\n\nvoid pt3FilterUpdateCutoff(pt3Filter_t *filter, float k);\n\nfloat pt3FilterApply(pt3Filter_t *filter, float input);\n\nvoid slewFilterInit(slewFilter_t *filter, float slewLimit, float threshold);\n\nfloat slewFilterApply(slewFilter_t *filter, float input);\n\n\n#ifdef __cplusplus\n}\n#endif\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/filters/filter_math.c",
    "content": "#include <stdint.h>\n#include <math.h>\n\n#include \"filter_math.h\"\n\n#if defined(FAST_MATH) || defined(VERY_FAST_MATH)\n#if defined(VERY_FAST_MATH)\n\n// http://lolengine.net/blog/2011/12/21/better-function-approximations\n// Chebyshev http://stackoverflow.com/questions/345085/how-do-trigonometric-functions-work/345117#345117\n// Thanks for ledvinap for making such accuracy possible! See: https://github.com/cleanflight/cleanflight/issues/940#issuecomment-110323384\n// https://github.com/Crashpilot1000/HarakiriWebstore1/blob/master/src/mw.c#L1235\n// sin_approx maximum absolute error = 2.305023e-06\n// cos_approx maximum absolute error = 2.857298e-06\n#define sinPolyCoef3 -1.666568107e-1f\n#define sinPolyCoef5  8.312366210e-3f\n#define sinPolyCoef7 -1.849218155e-4f\n#define sinPolyCoef9  0\n#else\n#define sinPolyCoef3 -1.666665710e-1f                                          // Double: -1.666665709650470145824129400050267289858e-1\n#define sinPolyCoef5  8.333017292e-3f                                          // Double:  8.333017291562218127986291618761571373087e-3\n#define sinPolyCoef7 -1.980661520e-4f                                          // Double: -1.980661520135080504411629636078917643846e-4\n#define sinPolyCoef9  2.600054768e-6f                                          // Double:  2.600054767890361277123254766503271638682e-6\n#endif\n\nfloat sin_approx(float x)\n{\n    int32_t xint = x;\n    if (xint < -32 || xint > 32) return 0.0f;                               // Stop here on error input (5 * 360 Deg)\n    while (x > M_PIf) x -= (2.0f * M_PIf);                                 // always wrap input angle to -PI..PI\n    while (x < -M_PIf) x += (2.0f * M_PIf);\n    if (x > (0.5f * M_PIf)) x = (0.5f * M_PIf) - (x - (0.5f * M_PIf));   // We just pick -90..+90 Degree\n    else if (x < -(0.5f * M_PIf)) x = -(0.5f * M_PIf) - ((0.5f * M_PIf) + x);\n    float x2 = x * x;\n    return x + x * x2 * (sinPolyCoef3 + x2 * (sinPolyCoef5 + x2 * (sinPolyCoef7 + x2 * sinPolyCoef9)));\n}\n\nfloat cos_approx(float x)\n{\n    return sin_approx(x + (0.5f * M_PIf));\n}\n\n// Initial implementation by Crashpilot1000 (https://github.com/Crashpilot1000/HarakiriWebstore1/blob/396715f73c6fcf859e0db0f34e12fe44bace6483/src/mw.c#L1292)\n// Polynomial coefficients by Andor (http://www.dsprelated.com/showthread/comp.dsp/21872-1.php) optimized by Ledvinap to save one multiplication\n// Max absolute error 0,000027 degree\n// atan2_approx maximum absolute error = 7.152557e-07 rads (4.098114e-05 degree)\nfloat atan2_approx(float y, float x)\n{\n#define atanPolyCoef1  3.14551665884836e-07f\n#define atanPolyCoef2  0.99997356613987f\n#define atanPolyCoef3  0.14744007058297684f\n#define atanPolyCoef4  0.3099814292351353f\n#define atanPolyCoef5  0.05030176425872175f\n#define atanPolyCoef6  0.1471039133652469f\n#define atanPolyCoef7  0.6444640676891548f\n\n    float res, absX, absY;\n    absX = fabsf(x);\n    absY = fabsf(y);\n    res = MAX(absX, absY);\n    if (res) res = MIN(absX, absY) / res;\n    else res = 0.0f;\n    res =\n        -((((atanPolyCoef5 * res - atanPolyCoef4) * res - atanPolyCoef3) * res - atanPolyCoef2) * res - atanPolyCoef1) /\n        ((atanPolyCoef7 * res + atanPolyCoef6) * res + 1.0f);\n    if (absY > absX) res = (M_PIf / 2.0f) - res;\n    if (x < 0) res = M_PIf - res;\n    if (y < 0) res = -res;\n    return res;\n}\n\n// http://http.developer.nvidia.com/Cg/acos.html\n// Handbook of Mathematical Functions\n// M. Abramowitz and I.A. Stegun, Ed.\n// acos_approx maximum absolute error = 6.760856e-05 rads (3.873685e-03 degree)\nfloat acos_approx(float x)\n{\n    float xa = fabsf(x);\n    float result = sqrtf(1.0f - xa) * (1.5707288f + xa * (-0.2121144f + xa * (0.0742610f + (-0.0187293f * xa))));\n    if (x < 0.0f)\n        return M_PIf - result;\n    else\n        return result;\n}\n\n#endif\n\nint gcd(int num, int denom)\n{\n    if (denom == 0)\n    {\n        return num;\n    }\n\n    return gcd(denom, num % denom);\n}\n\nint32_t applyDeadband(const int32_t value, const int32_t deadband)\n{\n    if (ABS(value) < deadband)\n    {\n        return 0;\n    }\n\n    return value >= 0 ? value - deadband : value + deadband;\n}\n\nfloat fapplyDeadband(const float value, const float deadband)\n{\n    if (fabsf(value) < deadband)\n    {\n        return 0;\n    }\n\n    return value >= 0 ? value - deadband : value + deadband;\n}\n\nvoid devClear(stdev_t *dev)\n{\n    dev->m_n = 0;\n}\n\nvoid devPush(stdev_t *dev, float x)\n{\n    dev->m_n++;\n    if (dev->m_n == 1)\n    {\n        dev->m_oldM = dev->m_newM = x;\n        dev->m_oldS = 0.0f;\n    } else\n    {\n        dev->m_newM = dev->m_oldM + (x - dev->m_oldM) / dev->m_n;\n        dev->m_newS = dev->m_oldS + (x - dev->m_oldM) * (x - dev->m_newM);\n        dev->m_oldM = dev->m_newM;\n        dev->m_oldS = dev->m_newS;\n    }\n}\n\nfloat devVariance(stdev_t *dev)\n{\n    return ((dev->m_n > 1) ? dev->m_newS / (dev->m_n - 1) : 0.0f);\n}\n\nfloat devStandardDeviation(stdev_t *dev)\n{\n    return sqrtf(devVariance(dev));\n}\n\nfloat degreesToRadians(int16_t degrees)\n{\n    return degrees * RAD;\n}\n\nint scaleRange(int x, int srcFrom, int srcTo, int destFrom, int destTo)\n{\n    long int a = ((long int) destTo - (long int) destFrom) * ((long int) x - (long int) srcFrom);\n    long int b = (long int) srcTo - (long int) srcFrom;\n    return (a / b) + destFrom;\n}\n\nfloat scaleRangef(float x, float srcFrom, float srcTo, float destFrom, float destTo)\n{\n    float a = (destTo - destFrom) * (x - srcFrom);\n    float b = srcTo - srcFrom;\n    return (a / b) + destFrom;\n}\n\n// Quick median filter implementation\n// (c) N. Devillard - 1998\n// http://ndevilla.free.fr/median/median.pdf\n#define QMF_SORT(a, b) { if ((a)>(b)) QMF_SWAP((a),(b)); }\n#define QMF_SWAP(a, b) { int32_t temp=(a);(a)=(b);(b)=temp; }\n#define QMF_COPY(p, v, n) { int32_t i; for (i=0; i<n; i++) p[i]=v[i]; }\n#define QMF_SORTF(a, b) { if ((a)>(b)) QMF_SWAPF((a),(b)); }\n#define QMF_SWAPF(a, b) { float temp=(a);(a)=(b);(b)=temp; }\n\nint32_t quickMedianFilter3(int32_t *v)\n{\n    int32_t p[3];\n    QMF_COPY(p, v, 3);\n\n    QMF_SORT(p[0], p[1]);\n    QMF_SORT(p[1], p[2]);\n    QMF_SORT(p[0], p[1]);\n    return p[1];\n}\n\nint32_t quickMedianFilter5(int32_t *v)\n{\n    int32_t p[5];\n    QMF_COPY(p, v, 5);\n\n    QMF_SORT(p[0], p[1]);\n    QMF_SORT(p[3], p[4]);\n    QMF_SORT(p[0], p[3]);\n    QMF_SORT(p[1], p[4]);\n    QMF_SORT(p[1], p[2]);\n    QMF_SORT(p[2], p[3]);\n    QMF_SORT(p[1], p[2]);\n    return p[2];\n}\n\nint32_t quickMedianFilter7(int32_t *v)\n{\n    int32_t p[7];\n    QMF_COPY(p, v, 7);\n\n    QMF_SORT(p[0], p[5]);\n    QMF_SORT(p[0], p[3]);\n    QMF_SORT(p[1], p[6]);\n    QMF_SORT(p[2], p[4]);\n    QMF_SORT(p[0], p[1]);\n    QMF_SORT(p[3], p[5]);\n    QMF_SORT(p[2], p[6]);\n    QMF_SORT(p[2], p[3]);\n    QMF_SORT(p[3], p[6]);\n    QMF_SORT(p[4], p[5]);\n    QMF_SORT(p[1], p[4]);\n    QMF_SORT(p[1], p[3]);\n    QMF_SORT(p[3], p[4]);\n    return p[3];\n}\n\nint32_t quickMedianFilter9(int32_t *v)\n{\n    int32_t p[9];\n    QMF_COPY(p, v, 9);\n\n    QMF_SORT(p[1], p[2]);\n    QMF_SORT(p[4], p[5]);\n    QMF_SORT(p[7], p[8]);\n    QMF_SORT(p[0], p[1]);\n    QMF_SORT(p[3], p[4]);\n    QMF_SORT(p[6], p[7]);\n    QMF_SORT(p[1], p[2]);\n    QMF_SORT(p[4], p[5]);\n    QMF_SORT(p[7], p[8]);\n    QMF_SORT(p[0], p[3]);\n    QMF_SORT(p[5], p[8]);\n    QMF_SORT(p[4], p[7]);\n    QMF_SORT(p[3], p[6]);\n    QMF_SORT(p[1], p[4]);\n    QMF_SORT(p[2], p[5]);\n    QMF_SORT(p[4], p[7]);\n    QMF_SORT(p[4], p[2]);\n    QMF_SORT(p[6], p[4]);\n    QMF_SORT(p[4], p[2]);\n    return p[4];\n}\n\nfloat quickMedianFilter3f(float *v)\n{\n    float p[3];\n    QMF_COPY(p, v, 3);\n\n    QMF_SORTF(p[0], p[1]);\n    QMF_SORTF(p[1], p[2]);\n    QMF_SORTF(p[0], p[1]);\n    return p[1];\n}\n\nfloat quickMedianFilter5f(float *v)\n{\n    float p[5];\n    QMF_COPY(p, v, 5);\n\n    QMF_SORTF(p[0], p[1]);\n    QMF_SORTF(p[3], p[4]);\n    QMF_SORTF(p[0], p[3]);\n    QMF_SORTF(p[1], p[4]);\n    QMF_SORTF(p[1], p[2]);\n    QMF_SORTF(p[2], p[3]);\n    QMF_SORTF(p[1], p[2]);\n    return p[2];\n}\n\nfloat quickMedianFilter7f(float *v)\n{\n    float p[7];\n    QMF_COPY(p, v, 7);\n\n    QMF_SORTF(p[0], p[5]);\n    QMF_SORTF(p[0], p[3]);\n    QMF_SORTF(p[1], p[6]);\n    QMF_SORTF(p[2], p[4]);\n    QMF_SORTF(p[0], p[1]);\n    QMF_SORTF(p[3], p[5]);\n    QMF_SORTF(p[2], p[6]);\n    QMF_SORTF(p[2], p[3]);\n    QMF_SORTF(p[3], p[6]);\n    QMF_SORTF(p[4], p[5]);\n    QMF_SORTF(p[1], p[4]);\n    QMF_SORTF(p[1], p[3]);\n    QMF_SORTF(p[3], p[4]);\n    return p[3];\n}\n\nfloat quickMedianFilter9f(float *v)\n{\n    float p[9];\n    QMF_COPY(p, v, 9);\n\n    QMF_SORTF(p[1], p[2]);\n    QMF_SORTF(p[4], p[5]);\n    QMF_SORTF(p[7], p[8]);\n    QMF_SORTF(p[0], p[1]);\n    QMF_SORTF(p[3], p[4]);\n    QMF_SORTF(p[6], p[7]);\n    QMF_SORTF(p[1], p[2]);\n    QMF_SORTF(p[4], p[5]);\n    QMF_SORTF(p[7], p[8]);\n    QMF_SORTF(p[0], p[3]);\n    QMF_SORTF(p[5], p[8]);\n    QMF_SORTF(p[4], p[7]);\n    QMF_SORTF(p[3], p[6]);\n    QMF_SORTF(p[1], p[4]);\n    QMF_SORTF(p[2], p[5]);\n    QMF_SORTF(p[4], p[7]);\n    QMF_SORTF(p[4], p[2]);\n    QMF_SORTF(p[6], p[4]);\n    QMF_SORTF(p[4], p[2]);\n    return p[4];\n}\n\nvoid arraySubInt32(int32_t *dest, int32_t *array1, int32_t *array2, int count)\n{\n    for (int i = 0; i < count; i++)\n    {\n        dest[i] = array1[i] - array2[i];\n    }\n}\n\nint16_t qPercent(fix12_t q)\n{\n    return (100 * q) >> 12;\n}\n\nint16_t qMultiply(fix12_t q, int16_t input)\n{\n    return (input * q) >> 12;\n}\n\nfix12_t qConstruct(int16_t num, int16_t den)\n{\n    return (num << 12) / den;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/filters/filter_math.h",
    "content": "#ifndef __MATHS_H\n#define __MATHS_H\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#ifndef sq\n#define sq(x) ((x)*(x))\n#endif\n#define power3(x) ((x)*(x)*(x))\n\n// Undefine this for use libc sinf/cosf. Keep this defined to use fast sin/cos approximations\n//#define FAST_MATH             // order 9 approximation\n#define VERY_FAST_MATH        // order 7 approximation\n\n// Use floating point M_PI instead explicitly.\n#define M_PIf       3.14159265358979323846f\n#define M_EULERf    2.71828182845904523536f\n\n#define RAD    (M_PIf / 180.0f)\n#define DEGREES_TO_DECIDEGREES(angle) ((angle) * 10)\n#define DECIDEGREES_TO_DEGREES(angle) ((angle) / 10)\n#define DECIDEGREES_TO_RADIANS(angle) ((angle) / 10.0f * 0.0174532925f)\n#define DEGREES_TO_RADIANS(angle) ((angle) * 0.0174532925f)\n\n#define CM_S_TO_KM_H(centimetersPerSecond) ((centimetersPerSecond) * 36 / 1000)\n#define CM_S_TO_MPH(centimetersPerSecond) ((centimetersPerSecond) * 10000 / 5080 / 88)\n\n#define MIN(a, b) \\\n  __extension__ ({ __typeof__ (a) _a = (a); \\\n  __typeof__ (b) _b = (b); \\\n  _a < _b ? _a : _b; })\n#define MAX(a, b) \\\n  __extension__ ({ __typeof__ (a) _a = (a); \\\n  __typeof__ (b) _b = (b); \\\n  _a > _b ? _a : _b; })\n#define ABS(x) \\\n  __extension__ ({ __typeof__ (x) _x = (x); \\\n  _x > 0 ? _x : -_x; })\n\n#define Q12 (1 << 12)\n\n#define HZ_TO_INTERVAL(x) (1.0f / (x))\n#define HZ_TO_INTERVAL_US(x) (1000000 / (x))\n\ntypedef int32_t fix12_t;\n\ntypedef struct stdev_s\n{\n    float m_oldM, m_newM, m_oldS, m_newS;\n    int m_n;\n} stdev_t;\n\n// Floating point 3 vector.\ntypedef struct fp_vector\n{\n    float X;\n    float Y;\n    float Z;\n} t_fp_vector_def;\n\ntypedef union u_fp_vector\n{\n    float A[3];\n    t_fp_vector_def V;\n} t_fp_vector;\n\n// Floating point Euler angles.\n// Be carefull, could be either of degrees or radians.\ntypedef struct fp_angles\n{\n    float roll;\n    float pitch;\n    float yaw;\n} fp_angles_def;\n\ntypedef union\n{\n    float raw[3];\n    fp_angles_def angles;\n} fp_angles_t;\n\ntypedef struct fp_rotationMatrix_s\n{\n    float m[3][3];              // matrix\n} fp_rotationMatrix_t;\n\nint gcd(int num, int denom);\n\nint32_t applyDeadband(int32_t value, int32_t deadband);\n\nfloat fapplyDeadband(float value, float deadband);\n\nvoid devClear(stdev_t *dev);\n\nvoid devPush(stdev_t *dev, float x);\n\nfloat devVariance(stdev_t *dev);\n\nfloat devStandardDeviation(stdev_t *dev);\n\nfloat degreesToRadians(int16_t degrees);\n\nint scaleRange(int x, int srcFrom, int srcTo, int destFrom, int destTo);\n\nfloat scaleRangef(float x, float srcFrom, float srcTo, float destFrom, float destTo);\n\nint32_t quickMedianFilter3(int32_t *v);\n\nint32_t quickMedianFilter5(int32_t *v);\n\nint32_t quickMedianFilter7(int32_t *v);\n\nint32_t quickMedianFilter9(int32_t *v);\n\nfloat quickMedianFilter3f(float *v);\n\nfloat quickMedianFilter5f(float *v);\n\nfloat quickMedianFilter7f(float *v);\n\nfloat quickMedianFilter9f(float *v);\n\n#if defined(FAST_MATH) || defined(VERY_FAST_MATH)\n\nfloat sin_approx(float x);\n\nfloat cos_approx(float x);\n\nfloat atan2_approx(float y, float x);\n\nfloat acos_approx(float x);\n\n#define tan_approx(x)       (sin_approx(x) / cos_approx(x))\n\nfloat exp_approx(float val);\n\nfloat log_approx(float val);\n\nfloat pow_approx(float a, float b);\n\n#else\n#define sin_approx(x)       sinf(x)\n#define cos_approx(x)       cosf(x)\n#define atan2_approx(y,x)   atan2f(y,x)\n#define acos_approx(x)      acosf(x)\n#define tan_approx(x)       tanf(x)\n#define exp_approx(x)       expf(x)\n#define log_approx(x)       logf(x)\n#define pow_approx(a, b)    powf(b, a)\n#endif\n\nvoid arraySubInt32(int32_t *dest, int32_t *array1, int32_t *array2, int count);\n\nint16_t qPercent(fix12_t q);\n\nint16_t qMultiply(fix12_t q, int16_t input);\n\nfix12_t qConstruct(int16_t num, int16_t den);\n\nstatic inline int constrain(int amt, int low, int high)\n{\n    if (amt < low)\n        return low;\n    else if (amt > high)\n        return high;\n    else\n        return amt;\n}\n\nstatic inline float constrainf(float amt, float low, float high)\n{\n    if (amt < low)\n        return low;\n    else if (amt > high)\n        return high;\n    else\n        return amt;\n}\n\n#ifdef __cplusplus\n}\n#endif\n#endif"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/helper_3dmath.h",
    "content": "// I2C device class (I2Cdev) demonstration Arduino sketch for MPU6050 class, 3D math helper\n// 6/5/2012 by Jeff Rowberg <jeff@rowberg.net>\n// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib\n//\n// Changelog:\n//     2012-06-05 - add 3D math helper file to DMP6 example sketch\n\n/* ============================================\nI2Cdev device library code is placed under the MIT license\nCopyright (c) 2012 Jeff Rowberg\n\nPermission is hereby granted, free of charge, to any person obtaining a copy\nof this software and associated documentation files (the \"Software\"), to deal\nin the Software without restriction, including without limitation the rights\nto use, copy, modify, merge, publish, distribute, sublicense, and/or sell\ncopies of the Software, and to permit persons to whom the Software is\nfurnished to do so, subject to the following conditions:\n\nThe above copyright notice and this permission notice shall be included in\nall copies or substantial portions of the Software.\n\nTHE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\nIMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\nFITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE\nAUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\nLIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\nOUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\nTHE SOFTWARE.\n===============================================\n*/\n\n#ifndef _HELPER_3DMATH_H_\n#define _HELPER_3DMATH_H_\n\nclass Quaternion {\n    public:\n        float w;\n        float x;\n        float y;\n        float z;\n        \n        Quaternion() {\n            w = 1.0f;\n            x = 0.0f;\n            y = 0.0f;\n            z = 0.0f;\n        }\n        \n        Quaternion(float nw, float nx, float ny, float nz) {\n            w = nw;\n            x = nx;\n            y = ny;\n            z = nz;\n        }\n\n        Quaternion getProduct(Quaternion q) {\n            // Quaternion multiplication is defined by:\n            //     (Q1 * Q2).w = (w1w2 - x1x2 - y1y2 - z1z2)\n            //     (Q1 * Q2).x = (w1x2 + x1w2 + y1z2 - z1y2)\n            //     (Q1 * Q2).y = (w1y2 - x1z2 + y1w2 + z1x2)\n            //     (Q1 * Q2).z = (w1z2 + x1y2 - y1x2 + z1w2\n            return Quaternion(\n                w*q.w - x*q.x - y*q.y - z*q.z,  // new w\n                w*q.x + x*q.w + y*q.z - z*q.y,  // new x\n                w*q.y - x*q.z + y*q.w + z*q.x,  // new y\n                w*q.z + x*q.y - y*q.x + z*q.w); // new z\n        }\n\n        Quaternion getConjugate() {\n            return Quaternion(w, -x, -y, -z);\n        }\n        \n        float getMagnitude() {\n            return sqrt(w*w + x*x + y*y + z*z);\n        }\n        \n        void normalize() {\n            float m = getMagnitude();\n            w /= m;\n            x /= m;\n            y /= m;\n            z /= m;\n        }\n        \n        Quaternion getNormalized() {\n            Quaternion r(w, x, y, z);\n            r.normalize();\n            return r;\n        }\n};\n\nclass VectorInt16 {\n    public:\n        int16_t x;\n        int16_t y;\n        int16_t z;\n\n        VectorInt16() {\n            x = 0;\n            y = 0;\n            z = 0;\n        }\n        \n        VectorInt16(int16_t nx, int16_t ny, int16_t nz) {\n            x = nx;\n            y = ny;\n            z = nz;\n        }\n\n        float getMagnitude() {\n            return sqrt(x*x + y*y + z*z);\n        }\n\n        void normalize() {\n            float m = getMagnitude();\n            x /= m;\n            y /= m;\n            z /= m;\n        }\n        \n        VectorInt16 getNormalized() {\n            VectorInt16 r(x, y, z);\n            r.normalize();\n            return r;\n        }\n        \n        void rotate(Quaternion *q) {\n            // http://www.cprogramming.com/tutorial/3d/quaternions.html\n            // http://www.euclideanspace.com/maths/algebra/realNormedAlgebra/quaternions/transforms/index.htm\n            // http://content.gpwiki.org/index.php/OpenGL:Tutorials:Using_Quaternions_to_represent_rotation\n            // ^ or: http://webcache.googleusercontent.com/search?q=cache:xgJAp3bDNhQJ:content.gpwiki.org/index.php/OpenGL:Tutorials:Using_Quaternions_to_represent_rotation&hl=en&gl=us&strip=1\n        \n            // P_out = q * P_in * conj(q)\n            // - P_out is the output vector\n            // - q is the orientation quaternion\n            // - P_in is the input vector (a*aReal)\n            // - conj(q) is the conjugate of the orientation quaternion (q=[w,x,y,z], q*=[w,-x,-y,-z])\n            Quaternion p(0, x, y, z);\n\n            // quaternion multiplication: q * p, stored back in p\n            p = q -> getProduct(p);\n\n            // quaternion multiplication: p * conj(q), stored back in p\n            p = p.getProduct(q -> getConjugate());\n\n            // p quaternion is now [0, x', y', z']\n            x = p.x;\n            y = p.y;\n            z = p.z;\n        }\n\n        VectorInt16 getRotated(Quaternion *q) {\n            VectorInt16 r(x, y, z);\n            r.rotate(q);\n            return r;\n        }\n};\n\nclass VectorFloat {\n    public:\n        float x;\n        float y;\n        float z;\n\n        VectorFloat() {\n            x = 0;\n            y = 0;\n            z = 0;\n        }\n        \n        VectorFloat(float nx, float ny, float nz) {\n            x = nx;\n            y = ny;\n            z = nz;\n        }\n\n        float getMagnitude() {\n            return sqrt(x*x + y*y + z*z);\n        }\n\n        void normalize() {\n            float m = getMagnitude();\n            x /= m;\n            y /= m;\n            z /= m;\n        }\n        \n        VectorFloat getNormalized() {\n            VectorFloat r(x, y, z);\n            r.normalize();\n            return r;\n        }\n        \n        void rotate(Quaternion *q) {\n            Quaternion p(0, x, y, z);\n\n            // quaternion multiplication: q * p, stored back in p\n            p = q -> getProduct(p);\n\n            // quaternion multiplication: p * conj(q), stored back in p\n            p = p.getProduct(q -> getConjugate());\n\n            // p quaternion is now [0, x', y', z']\n            x = p.x;\n            y = p.y;\n            z = p.z;\n        }\n\n        VectorFloat getRotated(Quaternion *q) {\n            VectorFloat r(x, y, z);\n            r.rotate(q);\n            return r;\n        }\n};\n\n#endif /* _HELPER_3DMATH_H_ */"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/i2c_dev.cpp",
    "content": "// I2Cdev library collection - Main I2C device class header file\n// Abstracts bit and byte I2C R/W functions into a convenient class\n// 7/26/2018 by Saeed Bazargan <Bazargan0241@hotmail.com>\n// ported to STM32 HAL library from Arduino code\n\n#include \"i2c_dev.hpp\"\n\n// Hold pointer to inited HAL I2C device\nstatic I2C_HandleTypeDef *I2Cdev_hi2c;\n\n/** Default timeout value for read operations.\n * Set this to 0 to disable timeout detection.\n */\nuint16_t I2Cdev_readTimeout = I2CDEV_DEFAULT_READ_TIMEOUT;\n\n/** Sets device handle to use for communications\n * You can call this function and set any other device at any moment\n */\nvoid I2Cdev_init(I2C_HandleTypeDef *hi2c)\n{\n    I2Cdev_hi2c = hi2c;\n}\n\n/** Read a single bit from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitNum Bit position to read (0-7)\n * @param data Container for single bit value\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (true = success)\n */\nuint8_t I2Cdev_readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data, uint16_t timeout)\n{\n    uint8_t b;\n    uint8_t count = I2Cdev_readByte(devAddr, regAddr, &b, timeout);\n    *data = b & (1 << bitNum);\n    return count;\n}\n\n/** Read a single bit from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitNum Bit position to read (0-15)\n * @param data Container for single bit value\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (true = success)\n */\nuint8_t I2Cdev_readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data, uint16_t timeout)\n{\n    uint16_t b;\n    uint8_t count = I2Cdev_readWord(devAddr, regAddr, &b, timeout);\n    *data = b & (1 << bitNum);\n    return count;\n}\n\n/** Read multiple bits from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitStart First bit position to read (0-7)\n * @param length Number of bits to read (not more than 8)\n * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05)\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (true = success)\n */\nuint8_t\nI2Cdev_readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data, uint16_t timeout)\n{\n    // 01101001 read byte\n    // 76543210 bit numbers\n    //    xxx   args: bitStart=4, length=3\n    //    010   masked\n    //   -> 010 shifted\n    uint8_t count, b;\n    if ((count = I2Cdev_readByte(devAddr, regAddr, &b, timeout)) != 0)\n    {\n        uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        b &= mask;\n        b >>= (bitStart - length + 1);\n        *data = b;\n    }\n    return count;\n}\n\n/** Read multiple bits from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param bitStart First bit position to read (0-15)\n * @param length Number of bits to read (not more than 16)\n * @param data Container for right-aligned value (i.e. '101' read from any bitStart position will equal 0x05)\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (1 = success, 0 = failure, -1 = timeout)\n */\nuint8_t\nI2Cdev_readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data, uint16_t timeout)\n{\n    // 1101011001101001 read byte\n    // fedcba9876543210 bit numbers\n    //    xxx           args: bitStart=12, length=3\n    //    010           masked\n    //           -> 010 shifted\n    uint8_t count;\n    uint16_t w;\n    if ((count = I2Cdev_readWord(devAddr, regAddr, &w, timeout)) != 0)\n    {\n        uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        w &= mask;\n        w >>= (bitStart - length + 1);\n        *data = w;\n    }\n    return count;\n}\n\n/** Read single byte from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param data Container for byte value read from device\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (true = success)\n */\nuint8_t I2Cdev_readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout)\n{\n    return I2Cdev_readBytes(devAddr, regAddr, 1, data, timeout);\n}\n\n/** Read single word from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to read from\n * @param data Container for word value read from device\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Status of read operation (true = success)\n */\nuint8_t I2Cdev_readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout)\n{\n    return I2Cdev_readWords(devAddr, regAddr, 1, data, timeout);\n}\n\n/** Read multiple bytes from an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register regAddr to read from\n * @param length Number of bytes to read\n * @param data Buffer to store read data in\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Number of bytes read (-1 indicates failure)\n */\nuint8_t I2Cdev_readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data, uint16_t timeout)\n{\n    uint16_t tout = timeout > 0 ? timeout : I2CDEV_DEFAULT_READ_TIMEOUT;\n\n    HAL_I2C_Master_Transmit(I2Cdev_hi2c, devAddr << 1, &regAddr, 1, tout);\n    if (HAL_I2C_Master_Receive(I2Cdev_hi2c, devAddr << 1, data, length, tout) == HAL_OK) return length;\n    return -1;\n}\n\n/** Read multiple words from a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register regAddr to read from\n * @param length Number of words to read\n * @param data Buffer to store read data in\n * @param timeout Optional read timeout in milliseconds (0 to disable, leave off to use default class value in I2Cdev_readTimeout)\n * @return Number of words read (-1 indicates failure)\n */\nuint8_t I2Cdev_readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data, uint16_t timeout)\n{\n    uint16_t tout = timeout > 0 ? timeout : I2CDEV_DEFAULT_READ_TIMEOUT;\n\n    HAL_I2C_Master_Transmit(I2Cdev_hi2c, devAddr << 1, &regAddr, 1, tout);\n    if (HAL_I2C_Master_Receive(I2Cdev_hi2c, devAddr << 1, (uint8_t *) data, length * 2, tout) == HAL_OK)\n        return length;\n    else\n        return -1;\n}\n\n/** write a single bit in an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitNum Bit position to write (0-7)\n * @param value New bit value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data)\n{\n    uint8_t b;\n    I2Cdev_readByte(devAddr, regAddr, &b, I2Cdev_readTimeout);\n    b = (data != 0) ? (b | (1 << bitNum)) : (b & ~(1 << bitNum));\n    return I2Cdev_writeByte(devAddr, regAddr, b);\n}\n\n/** write a single bit in a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitNum Bit position to write (0-15)\n * @param value New bit value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data)\n{\n    uint16_t w;\n    I2Cdev_readWord(devAddr, regAddr, &w, 100);\n    w = (data != 0) ? (w | (1 << bitNum)) : (w & ~(1 << bitNum));\n    return I2Cdev_writeWord(devAddr, regAddr, w);\n}\n\n/** Write multiple bits in an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitStart First bit position to write (0-7)\n * @param length Number of bits to write (not more than 8)\n * @param data Right-aligned value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data)\n{\n    //      010 value to write\n    // 76543210 bit numbers\n    //    xxx   args: bitStart=4, length=3\n    // 00011100 mask byte\n    // 10101111 original value (sample)\n    // 10100011 original & ~mask\n    // 10101011 masked | value\n    uint8_t b;\n    if (I2Cdev_readByte(devAddr, regAddr, &b, 100) != 0)\n    {\n        uint8_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        data <<= (bitStart - length + 1); // shift data into correct position\n        data &= mask; // zero all non-important bits in data\n        b &= ~(mask); // zero all important bits in existing byte\n        b |= data; // combine data with existing byte\n        return I2Cdev_writeByte(devAddr, regAddr, b);\n    } else\n    {\n        return 0;\n    }\n}\n\n/** Write multiple bits in a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register regAddr to write to\n * @param bitStart First bit position to write (0-15)\n * @param length Number of bits to write (not more than 16)\n * @param data Right-aligned value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data)\n{\n    //              010 value to write\n    // fedcba9876543210 bit numbers\n    //    xxx           args: bitStart=12, length=3\n    // 0001110000000000 mask word\n    // 1010111110010110 original value (sample)\n    // 1010001110010110 original & ~mask\n    // 1010101110010110 masked | value\n    uint16_t w;\n    if (I2Cdev_readWord(devAddr, regAddr, &w, 100) != 0)\n    {\n        uint16_t mask = ((1 << length) - 1) << (bitStart - length + 1);\n        data <<= (bitStart - length + 1); // shift data into correct position\n        data &= mask; // zero all non-important bits in data\n        w &= ~(mask); // zero all important bits in existing word\n        w |= data; // combine data with existing word\n        return I2Cdev_writeWord(devAddr, regAddr, w);\n    } else\n    {\n        return 0;\n    }\n}\n\n/** Write single byte to an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register address to write to\n * @param data New byte value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data)\n{\n    return I2Cdev_writeBytes(devAddr, regAddr, 1, &data);\n}\n\n/** Write single word to a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr Register address to write to\n * @param data New word value to write\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data)\n{\n    return I2Cdev_writeWords(devAddr, regAddr, 1, &data);\n}\n\n/** Write multiple bytes to an 8-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register address to write to\n * @param length Number of bytes to write\n * @param data Buffer to copy new data from\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t Size, uint8_t *pData)\n{\n    // Creating dynamic array to store regAddr + data in one buffer\n    uint8_t *dynBuffer;\n    dynBuffer = (uint8_t *) malloc(sizeof(uint8_t) * (Size + 1));\n    dynBuffer[0] = regAddr;\n\n    // copy array\n    memcpy(dynBuffer + 1, pData, sizeof(uint8_t) * Size);\n\n    HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(I2Cdev_hi2c, devAddr << 1, dynBuffer, Size + 1, 1000);\n    free(dynBuffer);\n    return status == HAL_OK;\n}\n\n/** Write multiple words to a 16-bit device register.\n * @param devAddr I2C slave device address\n * @param regAddr First register address to write to\n * @param length Number of words to write\n * @param data Buffer to copy new data from\n * @return Status of operation (true = success)\n */\nuint16_t I2Cdev_writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data)\n{\n    // Creating dynamic array to store regAddr + data in one buffer\n    uint8_t *dynBuffer;\n    dynBuffer = (uint8_t *) malloc(sizeof(uint8_t) + sizeof(uint16_t) * length);\n    dynBuffer[0] = regAddr;\n\n    // copy array\n    memcpy(dynBuffer + 1, data, sizeof(uint16_t) * length);\n    HAL_StatusTypeDef status = HAL_I2C_Master_Transmit(I2Cdev_hi2c, devAddr << 1, dynBuffer,\n                                                       sizeof(uint8_t) + sizeof(uint16_t) * length, 1000);\n    free(dynBuffer);\n    return status == HAL_OK;\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/imu/i2c_dev.hpp",
    "content": "// ported to STM32 HAL library from Arduino code\n\n\n#ifndef _I2CDEV_H_\n#define _I2CDEV_H_\n\n#include <stdint.h>\n#include <stdlib.h>\n#include <string.h>\n\n#include \"stm32f4xx_hal.h\"\n#include \"i2c.h\"\n\n#define true 1\n#define false 0\n\n// 1000ms default read timeout (modify with \"I2Cdev::readTimeout = [ms];\")\n#define I2CDEV_DEFAULT_READ_TIMEOUT     1000\n\nvoid I2Cdev_init(I2C_HandleTypeDef *hi2c);\n\nuint8_t I2Cdev_readBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t *data,\n                       uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t I2Cdev_readBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t *data,\n                        uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t\nI2Cdev_readBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t *data,\n                uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t\nI2Cdev_readBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t *data,\n                 uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t\nI2Cdev_readByte(uint8_t devAddr, uint8_t regAddr, uint8_t *data, uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t\nI2Cdev_readWord(uint8_t devAddr, uint8_t regAddr, uint16_t *data, uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t I2Cdev_readBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data,\n                         uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\nuint8_t I2Cdev_readWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data,\n                         uint16_t timeout = I2CDEV_DEFAULT_READ_TIMEOUT);\n\nuint16_t I2Cdev_writeBit(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint8_t data);\nuint16_t I2Cdev_writeBitW(uint8_t devAddr, uint8_t regAddr, uint8_t bitNum, uint16_t data);\nuint16_t I2Cdev_writeBits(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint8_t data);\nuint16_t I2Cdev_writeBitsW(uint8_t devAddr, uint8_t regAddr, uint8_t bitStart, uint8_t length, uint16_t data);\nuint16_t I2Cdev_writeByte(uint8_t devAddr, uint8_t regAddr, uint8_t data);\nuint16_t I2Cdev_writeWord(uint8_t devAddr, uint8_t regAddr, uint16_t data);\nuint16_t I2Cdev_writeBytes(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint8_t *data);\nuint16_t I2Cdev_writeWords(uint8_t devAddr, uint8_t regAddr, uint8_t length, uint16_t *data);\n\n#endif /* _I2CDEV_H_ */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/memory/eeprom_interface.h",
    "content": "#ifndef FlashStorage_STM32_h\n#define FlashStorage_STM32_h\n\n\n#if !(defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || \\\n       defined(STM32L0) || defined(STM32L1) || defined(STM32L4) || defined(STM32H7) || defined(STM32G0) || defined(STM32G4) || \\\n       defined(STM32WB) || defined(STM32MP1) || defined(STM32L5))\n#error This code is intended to run on STM32F/L/H/G/WB/MP1 platform! Please check your Tools->Board setting.\n#endif\n\n#define FLASH_STORAGE_STM32_VERSION     \"FlashStorage_STM32 v1.1.0\"\n\n// Only use this with emulated EEPROM, without integrated EEPROM\n#if !defined(DATA_EEPROM_BASE)\n\n#include \"emulated_eeprom.h\"\n\nclass EEPROMClass\n{\npublic:\n\n    EEPROMClass() : _initialized(false), _dirtyBuffer(false), _commitASAP(true), _validEEPROM(true)\n    {}\n\n    /**\n     * Read an eeprom cell\n     * @param index\n     * @return value\n     */\n    uint8_t read(int address)\n    {\n        if (!_initialized)\n            init();\n\n        return eeprom_buffered_read_byte(address);\n    }\n\n    /**\n     * Update an eeprom cell\n     * @param index\n     * @param value\n     */\n    void update(int address, uint8_t value)\n    {\n        if (!_initialized)\n            init();\n\n        if (eeprom_buffered_read_byte(address) != value)\n        {\n            _dirtyBuffer = true;\n            eeprom_buffered_write_byte(address, value);\n        }\n    }\n\n    /**\n     * Write value to an eeprom cell\n     * @param index\n     * @param value\n     */\n    void write(int address, uint8_t value)\n    {\n        update(address, value);\n    }\n\n    /**\n     * Update eeprom cells from an object\n     * @param index\n     * @param value\n     */\n    //Functionality to 'get' and 'put' objects to and from EEPROM.\n    template<typename T>\n    T &get(int idx, T &t)\n    {\n        // Copy the data from the flash to the buffer if not yet\n        if (!_initialized)\n            init();\n\n        uint16_t offset = idx;\n        uint8_t* _pointer = (uint8_t * ) & t;\n\n        for (uint16_t count = sizeof(T); count; --count, ++offset)\n        {\n            *_pointer++ = eeprom_buffered_read_byte(offset);\n        }\n\n        return t;\n    }\n\n    template<typename T>\n    const T &put(int idx, const T &t)\n    {\n        // Copy the data from the flash to the buffer if not yet\n        if (!_initialized)\n            init();\n\n        uint16_t offset = idx;\n\n        const uint8_t* _pointer = (const uint8_t*) &t;\n\n        for (uint16_t count = sizeof(T); count; --count, ++offset)\n        {\n            eeprom_buffered_write_byte(offset, *_pointer++);\n        }\n\n        if (_commitASAP)\n        {\n            // Save the data from the buffer to the flash right away\n            eeprom_buffer_flush();\n\n            _dirtyBuffer = false;\n            _validEEPROM = true;\n        } else\n        {\n            // Delay saving the data from the buffer to the flash. Just flag and wait for commit() later\n            _dirtyBuffer = true;\n        }\n\n        return t;\n    }\n\n    /**\n     * Check whether the eeprom data is valid\n     * @return true, if eeprom data is valid (has been written at least once), false if not\n     */\n    bool isValid()\n    {\n        return _validEEPROM;\n    }\n\n    /**\n     * Write previously made eeprom changes to the underlying flash storage\n     * Use this with care: Each and every commit will harm the flash and reduce it's lifetime (like with every flash memory)\n     */\n    void commit()\n    {\n        if (!_initialized)\n            init();\n\n        if (_dirtyBuffer)\n        {\n            // Save the data from the buffer to the flash\n            eeprom_buffer_flush();\n\n            _dirtyBuffer = false;\n            _validEEPROM = true;\n        }\n    }\n\n    uint16_t length()\n    { return E2END + 1; }\n\n    void setCommitASAP(bool value = true)\n    { _commitASAP = value; }\n    bool getCommitASAP()\n    { return _commitASAP; }\n\nprivate:\n\n    void init()\n    {\n        // Copy the data from the flash to the buffer\n        eeprom_buffer_fill();\n        _initialized = true;\n    }\n\n    bool _initialized;\n    bool _dirtyBuffer;\n    bool _commitASAP;\n    bool _validEEPROM;\n};\n\n\n#else\n\n#include \"EEPROM.h\"\n\n#endif    // #if !defined(DATA_EEPROM_BASE)\n\n#endif    //#ifndef FlashAsEEPROM_SAMD_h\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/memory/emulated_eeprom.cpp",
    "content": "#ifndef __STM32_EEPROM_HPP\n#define __STM32_EEPROM_HPP\n\n#include <string.h>\n#include \"emulated_eeprom.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n\n#endif\n\n/* Be able to change FLASH_BANK_NUMBER to use if relevant */\n#if !defined(FLASH_BANK_NUMBER) && \\\n    (defined(STM32F0xx) || defined(STM32F1xx) || defined(STM32G4xx) || \\\n     defined(STM32H7xx) || defined(STM32L4xx) || defined(STM32L5xx))\n/* For STM32F0xx, FLASH_BANK_1 is not defined only FLASH_BANK1_END is defined */\n#if defined(STM32F0xx)\n#define FLASH_BANK_1 1U\n#endif\n#if defined(FLASH_BANK_2)\n#define FLASH_BANK_NUMBER   FLASH_BANK_2\n#else\n#define FLASH_BANK_NUMBER   FLASH_BANK_1\n#endif /* FLASH_BANK_2 */\n#ifndef FLASH_BANK_NUMBER\n#error \"FLASH_BANK_NUMBER could not be defined\"\n#endif\n#endif /* !FLASH_BANK_NUMBER */\n\n/* Be able to change FLASH_DATA_SECTOR to use if relevant */\n#if defined(STM32F2xx) || defined(STM32F4xx) || defined(STM32F7xx) || \\\n    defined(STM32H7xx)\n#if !defined(FLASH_DATA_SECTOR)\n#define FLASH_DATA_SECTOR   ((uint32_t)(FLASH_SECTOR_TOTAL - 1))\n#else\n#ifndef FLASH_BASE_ADDRESS\n#error \"FLASH_BASE_ADDRESS have to be defined when FLASH_DATA_SECTOR is defined\"\n#endif\n#endif /* !FLASH_DATA_SECTOR */\n#endif /* STM32F2xx || STM32F4xx || STM32F7xx */\n\n/* Be able to change FLASH_PAGE_NUMBER to use if relevant */\n#if !defined(FLASH_PAGE_NUMBER) && \\\n    (defined (STM32G0xx) || defined(STM32G4xx) || defined (STM32L4xx) || \\\n     defined (STM32L5xx) || defined(STM32WBxx))\n#define FLASH_PAGE_NUMBER   ((uint32_t)((FLASH_SIZE / FLASH_PAGE_SIZE) - 1))\n#endif /* !FLASH_PAGE_NUMBER */\n\n/* Be able to change FLASH_END to use */\n#if !defined(FLASH_END)\n#if defined (STM32F0xx) || defined (STM32F1xx)\n#if defined (FLASH_BANK2_END) && (FLASH_BANK_NUMBER == FLASH_BANK_2)\n#define FLASH_END  FLASH_BANK2_END\n#elif defined (FLASH_BANK1_END) && (FLASH_BANK_NUMBER == FLASH_BANK_1)\n#define FLASH_END  FLASH_BANK1_END\n#endif\n#elif defined (STM32F3xx)\nstatic inline uint32_t get_flash_end(void)\n{\n  uint32_t size;\n  switch ((*((uint16_t *)FLASH_SIZE_DATA_REGISTER))) {\n    case 0x200U:\n      size = 0x0807FFFFU;\n      break;\n    case 0x100U:\n      size = 0x0803FFFFU;\n      break;\n    case 0x80U:\n      size = 0x0801FFFFU;\n      break;\n    case 0x40U:\n      size = 0x0800FFFFU;\n      break;\n    case 0x20U:\n      size = 0x08007FFFU;\n      break;\n    default:\n      size = 0x08003FFFU;\n      break;\n  }\n  return size;\n}\n#define FLASH_END  get_flash_end()\n#elif defined(STM32G0xx) || defined(STM32G4xx) || defined (STM32L4xx) || \\\n      defined (STM32L5xx) || defined(STM32WBxx)\n/* If FLASH_PAGE_NUMBER is defined by user, this is not really end of the flash */\n#define FLASH_END  ((uint32_t)(FLASH_BASE + (((FLASH_PAGE_NUMBER +1) * FLASH_PAGE_SIZE))-1))\n#elif defined(EEPROM_RETRAM_MODE)\n#define FLASH_END  ((uint32_t)(EEPROM_RETRAM_START_ADDRESS + EEPROM_RETRAM_MODE_SIZE -1))\n#elif defined(DATA_EEPROM_END)\n#define FLASH_END DATA_EEPROM_END\n#endif\n#ifndef FLASH_END\n#error \"FLASH_END could not be defined\"\n#endif\n#endif /* FLASH_END */\n\n/* Be able to change FLASH_BASE_ADDRESS to use */\n#ifndef FLASH_BASE_ADDRESS\n/*\n * By default, Use the last page of the flash to store data\n * in order to prevent overwritting\n * program data\n */\n#if defined(EEPROM_RETRAM_MODE)\n#define FLASH_BASE_ADDRESS  EEPROM_RETRAM_START_ADDRESS\n#else\n#define FLASH_BASE_ADDRESS  ((uint32_t)((FLASH_END + 1) - FLASH_PAGE_SIZE))\n#endif\n#ifndef FLASH_BASE_ADDRESS\n#error \"FLASH_BASE_ADDRESS could not be defined\"\n#endif\n#endif /* FLASH_BASE_ADDRESS */\n\n#if !defined(DATA_EEPROM_BASE)\nstatic uint8_t eeprom_buffer[E2END + 1] __attribute__((aligned(8))) = {0};\n#endif\n\n/**\n  * @brief  Function reads a byte from emulated eeprom (flash)\n  * @param  pos : address to read\n  * @retval byte : data read from eeprom\n  */\nuint8_t eeprom_read_byte(const uint32_t pos)\n{\n#if defined(DATA_EEPROM_BASE)\n    __IO uint8_t data = 0;\n    if (pos <= (DATA_EEPROM_END - DATA_EEPROM_BASE)) {\n      /* with actual EEPROM, pos is a relative address */\n      data = *(__IO uint8_t *)(DATA_EEPROM_BASE + pos);\n    }\n    return (uint8_t)data;\n#else\n    eeprom_buffer_fill();\n    return eeprom_buffered_read_byte(pos);\n#endif /* _EEPROM_BASE */\n}\n\n/**\n  * @brief  Function writes a byte to emulated eeprom (flash)\n  * @param  pos : address to write\n  * @param  value : value to write\n  * @retval none\n  */\nvoid eeprom_write_byte(uint32_t pos, uint8_t value)\n{\n#if defined(DATA_EEPROM_BASE)\n    /* with actual EEPROM, pos is a relative address */\n    if (pos <= (DATA_EEPROM_END - DATA_EEPROM_BASE)) {\n      if (HAL_FLASHEx_DATAEEPROM_Unlock() == HAL_OK) {\n        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_BYTE, (pos + DATA_EEPROM_BASE), (uint32_t)value);\n        HAL_FLASHEx_DATAEEPROM_Lock();\n      }\n    }\n#else\n    eeprom_buffered_write_byte(pos, value);\n    eeprom_buffer_flush();\n#endif /* _EEPROM_BASE */\n}\n\n#if !defined(DATA_EEPROM_BASE)\n\n/**\n  * @brief  Function reads a byte from the eeprom buffer\n  * @param  pos : address to read\n  * @retval byte : data read from eeprom\n  */\nuint8_t eeprom_buffered_read_byte(const uint32_t pos)\n{\n    return eeprom_buffer[pos];\n}\n\n/**\n  * @brief  Function writes a byte to the eeprom buffer\n  * @param  pos : address to write\n  * @param  value : value to write\n  * @retval none\n  */\nvoid eeprom_buffered_write_byte(uint32_t pos, uint8_t value)\n{\n    eeprom_buffer[pos] = value;\n}\n\n/**\n  * @brief  This function copies the data from flash into the buffer\n  * @param  none\n  * @retval none\n  */\nvoid eeprom_buffer_fill(void)\n{\n    memcpy(eeprom_buffer, (uint8_t*) (FLASH_BASE_ADDRESS), E2END + 1);\n}\n\n#if defined(EEPROM_RETRAM_MODE)\n\n/**\n  * @brief  This function writes the buffer content into the flash\n  * @param  none\n  * @retval none\n  */\nvoid eeprom_buffer_flush(void)\n{\n  memcpy((uint8_t *)(FLASH_BASE_ADDRESS), eeprom_buffer, E2END + 1);\n}\n\n#else /* defined(EEPROM_RETRAM_MODE) */\n\n/**\n  * @brief  This function writes the buffer content into the flash\n  * @param  none\n  * @retval none\n  */\nvoid eeprom_buffer_flush(void)\n{\n    FLASH_EraseInitTypeDef EraseInitStruct;\n    uint32_t offset = 0;\n    uint32_t address = FLASH_BASE_ADDRESS;\n    uint32_t address_end = FLASH_BASE_ADDRESS + E2END;\n#if defined (STM32F0xx) || defined (STM32F1xx) || defined (STM32F3xx) || \\\n    defined (STM32G0xx) || defined (STM32G4xx) || \\\n    defined (STM32L4xx) || defined (STM32L5xx) || defined (STM32WBxx)\n    uint32_t pageError = 0;\n    uint64_t data = 0;\n\n    /* ERASING page */\n    EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;\n#if defined (STM32F1xx) || defined (STM32G4xx) || defined (STM32L4xx) || \\\n    defined (STM32L5xx)\n    EraseInitStruct.Banks = FLASH_BANK_NUMBER;\n#endif\n#if defined (STM32G0xx) || defined (STM32G4xx) || defined (STM32L4xx) || \\\n    defined (STM32L5xx) || defined (STM32WBxx)\n    EraseInitStruct.Page = FLASH_PAGE_NUMBER;\n#else\n    EraseInitStruct.PageAddress = FLASH_BASE_ADDRESS;\n#endif\n    EraseInitStruct.NbPages = 1;\n\n    if (HAL_FLASH_Unlock() == HAL_OK)\n    {\n#if defined (STM32G0xx) || defined (STM32G4xx) || defined (STM32L4xx) || \\\n      defined (STM32L5xx) || defined (STM32WBxx)\n        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);\n#else\n        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR);\n#endif\n        if (HAL_FLASHEx_Erase(&EraseInitStruct, &pageError) == HAL_OK)\n        {\n            while (address <= address_end)\n            {\n\n                data = *((uint64_t*) ((uint8_t*) eeprom_buffer + offset));\n\n                if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, address, data) == HAL_OK)\n                {\n                    address += 8;\n                    offset += 8;\n                } else\n                {\n                    address = address_end + 1;\n                }\n            }\n        }\n        HAL_FLASH_Lock();\n    }\n#else\n    uint32_t SectorError = 0;\n#if defined(STM32H7xx)\n    uint64_t data[4] = {0x0000};\n#else\n    uint32_t data = 0;\n#endif\n\n    /* ERASING page */\n    EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;\n#if defined(STM32H7xx)\n    EraseInitStruct.Banks = FLASH_BANK_NUMBER;\n#endif\n    EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;\n    EraseInitStruct.Sector = FLASH_DATA_SECTOR;\n    EraseInitStruct.NbSectors = 1;\n\n    HAL_FLASH_Unlock();\n\n    if (HAL_FLASHEx_Erase(&EraseInitStruct, &SectorError) == HAL_OK)\n    {\n        while (address <= address_end)\n        {\n#if defined(STM32H7xx)\n            /* 256 bits */\n            memcpy(&data, eeprom_buffer + offset, 8 * sizeof(uint32_t));\n            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_FLASHWORD, address, (uint32_t)data) == HAL_OK) {\n              address += 32;\n              offset += 32;\n#else\n            memcpy(&data, eeprom_buffer + offset, sizeof(uint32_t));\n            if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, address, data) == HAL_OK)\n            {\n                address += 4;\n                offset += 4;\n#endif\n            } else\n            {\n                address = address_end + 1;\n            }\n        }\n    }\n    HAL_FLASH_Lock();\n#endif\n}\n\n#endif /* defined(EEPROM_RETRAM_MODE) */\n\n#endif /* ! DATA_EEPROM_BASE */\n\n#ifdef __cplusplus\n}\n#endif\n#endif\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/memory/emulated_eeprom.h",
    "content": "/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32_EEPROM_H\n#define __STM32_EEPROM_H\n\n/* Includes ------------------------------------------------------------------*/\n\n#ifdef __cplusplus\nextern \"C\" {\n#include \"main.h\"\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n#if defined(STM32MP1xx)\n/* Note for STM32MP1xx devices:\n * Those devices do not have non-volatile memory. The emulation is done\n * in RETRAM. Therefore data will be preserved *only* when VBAT is supplied\n * (e.g. A coin battery is connected to CN3 on STM32MP157A_DK1) and\n * the coprocessor is waken up from STANBY mode.\n * The data won't be preserved from cold boot, even if VBAT is connected.\n * See: https://community.st.com/s/question/0D50X0000B44pHUSQY/doesnt-the-mcu-coprocessor-have-nonvolatile-memory\n */\n#define EEPROM_RETRAM_MODE\n/* 4kB is the same size as EEPROM size of ATMega2560. */\n#ifndef EEPROM_RETRAM_MODE_SIZE\n#define EEPROM_RETRAM_MODE_SIZE ((uint32_t)(4*1024))\n#endif\n/* RETRAM start address is 0x00000000 (retset entry) and end address is\n * 0x00020000 (64kB in total). The by default, ldscript.ld for STM32MP1xx\n * does not define address between 0x00000298 (end of ISR Vector) and 0x00020000.\n * So it is okay to use in this address range. Make sure ldscript.ld does not\n * overrap the following address range.\n */\n#ifndef EEPROM_RETRAM_START_ADDRESS\n#define EEPROM_RETRAM_START_ADDRESS (0x00000400UL)\n#endif\n#define E2END (EEPROM_RETRAM_MODE_SIZE - 1)\n#else\n#ifndef FLASH_PAGE_SIZE\n/*\n * FLASH_PAGE_SIZE is not defined for STM32F2xx, STM32F4xx and STM32F7xx\n * Could be redefined in variant.h or using build_opt.h\n * Warning: This is not the sector size, only the size used for EEPROM\n * emulation. Anyway, all the sector size will be erased.\n * So pay attention to not use this sector for other stuff.\n */\n#define FLASH_PAGE_SIZE     ((uint32_t)(1*1024)) /* 1kB page */\n#endif\n\n#if defined(DATA_EEPROM_BASE) || defined(FLASH_EEPROM_BASE)\n\n#if defined (DATA_EEPROM_END)\n#define E2END (DATA_EEPROM_END - DATA_EEPROM_BASE)\n#elif defined (DATA_EEPROM_BANK2_END)\n/* assuming two contiguous banks */\n#define DATA_EEPROM_END DATA_EEPROM_BANK2_END\n#define E2END (DATA_EEPROM_BANK2_END - DATA_EEPROM_BASE)\n#elif defined (FLASH_EEPROM_END)\n#define DATA_EEPROM_BASE FLASH_EEPROM_BASE\n#define DATA_EEPROM_END FLASH_EEPROM_END\n#define E2END (DATA_EEPROM_END - DATA_EEPROM_BASE)\n#endif /* __EEPROM_END */\n\n#else /* _EEPROM_BASE */\n#define E2END (FLASH_PAGE_SIZE - 1)\n#endif /* _EEPROM_BASE */\n\n#endif\n\n\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions ------------------------------------------------------- */\n\nuint8_t eeprom_read_byte(uint32_t pos);\nvoid eeprom_write_byte(uint32_t pos, uint8_t value);\n\n#if !defined(DATA_EEPROM_BASE)\nvoid eeprom_buffer_fill();\nvoid eeprom_buffer_flush();\nuint8_t eeprom_buffered_read_byte(uint32_t pos);\nvoid eeprom_buffered_write_byte(uint32_t pos, uint8_t value);\n#endif /* ! DATA_EEPROM_BASE */\n\n#ifdef __cplusplus\n}\n\n\n#endif\n#endif /* __STM32_EEPROM_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/arm_math/arm_common_tables.h",
    "content": "/* ----------------------------------------------------------------------\n * Project:      CMSIS DSP Library\n * Title:        arm_common_tables.h\n * Description:  Extern declaration for common tables\n *\n * $Date:        27. January 2017\n * $Revision:    V.1.5.1\n *\n * Target Processor: Cortex-M cores\n * -------------------------------------------------------------------- */\n/*\n * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _ARM_COMMON_TABLES_H\n#define _ARM_COMMON_TABLES_H\n\n#include \"arm_math.h\"\n\nextern const uint16_t armBitRevTable[1024];\nextern const q15_t armRecipTableQ15[64];\nextern const q31_t armRecipTableQ31[64];\nextern const float32_t twiddleCoef_16[32];\nextern const float32_t twiddleCoef_32[64];\nextern const float32_t twiddleCoef_64[128];\nextern const float32_t twiddleCoef_128[256];\nextern const float32_t twiddleCoef_256[512];\nextern const float32_t twiddleCoef_512[1024];\nextern const float32_t twiddleCoef_1024[2048];\nextern const float32_t twiddleCoef_2048[4096];\nextern const float32_t twiddleCoef_4096[8192];\n#define twiddleCoef twiddleCoef_4096\nextern const q31_t twiddleCoef_16_q31[24];\nextern const q31_t twiddleCoef_32_q31[48];\nextern const q31_t twiddleCoef_64_q31[96];\nextern const q31_t twiddleCoef_128_q31[192];\nextern const q31_t twiddleCoef_256_q31[384];\nextern const q31_t twiddleCoef_512_q31[768];\nextern const q31_t twiddleCoef_1024_q31[1536];\nextern const q31_t twiddleCoef_2048_q31[3072];\nextern const q31_t twiddleCoef_4096_q31[6144];\nextern const q15_t twiddleCoef_16_q15[24];\nextern const q15_t twiddleCoef_32_q15[48];\nextern const q15_t twiddleCoef_64_q15[96];\nextern const q15_t twiddleCoef_128_q15[192];\nextern const q15_t twiddleCoef_256_q15[384];\nextern const q15_t twiddleCoef_512_q15[768];\nextern const q15_t twiddleCoef_1024_q15[1536];\nextern const q15_t twiddleCoef_2048_q15[3072];\nextern const q15_t twiddleCoef_4096_q15[6144];\nextern const float32_t twiddleCoef_rfft_32[32];\nextern const float32_t twiddleCoef_rfft_64[64];\nextern const float32_t twiddleCoef_rfft_128[128];\nextern const float32_t twiddleCoef_rfft_256[256];\nextern const float32_t twiddleCoef_rfft_512[512];\nextern const float32_t twiddleCoef_rfft_1024[1024];\nextern const float32_t twiddleCoef_rfft_2048[2048];\nextern const float32_t twiddleCoef_rfft_4096[4096];\n\n/* floating-point bit reversal tables */\n#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)\n#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)\n#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)\n#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)\n#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)\n#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)\n#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)\n#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)\n#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)\n\nextern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];\n\n/* fixed-point bit reversal tables */\n#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)\n#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)\n#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)\n#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)\n#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)\n#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)\n#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)\n#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)\n#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)\n\nextern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];\nextern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];\n\n/* Tables for Fast Math Sine and Cosine */\nextern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];\nextern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];\nextern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];\n\n#endif /*  ARM_COMMON_TABLES_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/arm_math/arm_const_structs.h",
    "content": "/* ----------------------------------------------------------------------\n * Project:      CMSIS DSP Library\n * Title:        arm_const_structs.h\n * Description:  Constant structs that are initialized for user convenience.\n *               For example, some can be given as arguments to the arm_cfft_f32() function.\n *\n * $Date:        27. January 2017\n * $Revision:    V.1.5.1\n *\n * Target Processor: Cortex-M cores\n * -------------------------------------------------------------------- */\n/*\n * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef _ARM_CONST_STRUCTS_H\n#define _ARM_CONST_STRUCTS_H\n\n#include \"arm_math.h\"\n#include \"arm_common_tables.h\"\n\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;\n   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;\n\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;\n   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;\n\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;\n   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/arm_math/arm_math.h",
    "content": "/******************************************************************************\n * @file     arm_math.h\n * @brief    Public header file for CMSIS DSP LibraryU\n * @version  V1.5.3\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/**\n   \\mainpage CMSIS DSP Software Library\n   *\n   * Introduction\n   * ------------\n   *\n   * This user manual describes the CMSIS DSP software library,\n   * a suite of common signal processing functions for use on Cortex-M processor based devices.\n   *\n   * The library is divided into a number of functions each covering a specific category:\n   * - Basic math functions\n   * - Fast math functions\n   * - Complex math functions\n   * - Filters\n   * - Matrix functions\n   * - Transforms\n   * - Motor control functions\n   * - Statistical functions\n   * - Support functions\n   * - Interpolation functions\n   *\n   * The library has separate functions for operating on 8-bit integers, 16-bit integers,\n   * 32-bit integer and 32-bit floating-point values.\n   *\n   * Using the Library\n   * ------------\n   *\n   * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.\n   * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit)\n   * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit)\n   * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit)\n   * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on)\n   * - arm_cortexM7l_math.lib (Cortex-M7, Little endian)\n   * - arm_cortexM7b_math.lib (Cortex-M7, Big endian)\n   * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit)\n   * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit)\n   * - arm_cortexM4l_math.lib (Cortex-M4, Little endian)\n   * - arm_cortexM4b_math.lib (Cortex-M4, Big endian)\n   * - arm_cortexM3l_math.lib (Cortex-M3, Little endian)\n   * - arm_cortexM3b_math.lib (Cortex-M3, Big endian)\n   * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian)\n   * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian)\n   * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian)\n   * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian)\n   * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit)\n   * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions)\n   * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit)\n   *\n   * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.\n   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single\n   * public header file <code> arm_math.h</code> for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.\n   * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or\n   * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.\n   * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML.\n   * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions.\n   * \n   *\n   * Examples\n   * --------\n   *\n   * The library ships with a number of examples which demonstrate how to use the library functions.\n   *\n   * Toolchain Support\n   * ------------\n   *\n   * The library has been developed and tested with MDK version 5.14.0.0\n   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.\n   *\n   * Building the Library\n   * ------------\n   *\n   * The library installer contains a project file to rebuild libraries on MDK toolchain in the <code>CMSIS\\\\DSP_Lib\\\\Source\\\\ARM</code> folder.\n   * - arm_cortexM_math.uvprojx\n   *\n   *\n   * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above.\n   *\n   * Preprocessor Macros\n   * ------------\n   *\n   * Each library project have different preprocessor macros.\n   *\n   * - UNALIGNED_SUPPORT_DISABLE:\n   *\n   * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access\n   *\n   * - ARM_MATH_BIG_ENDIAN:\n   *\n   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.\n   *\n   * - ARM_MATH_MATRIX_CHECK:\n   *\n   * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices\n   *\n   * - ARM_MATH_ROUNDING:\n   *\n   * Define macro ARM_MATH_ROUNDING for rounding on support functions\n   *\n   * - ARM_MATH_CMx:\n   *\n   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target\n   * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and\n   * ARM_MATH_CM7 for building the library on cortex-M7.\n   *\n   * - ARM_MATH_ARMV8MxL:\n   *\n   * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library\n   * on Armv8-M Mainline target.\n   *\n   * - __FPU_PRESENT:\n   *\n   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries.\n   *\n   * - __DSP_PRESENT:\n   *\n   * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions.\n   *\n   * <hr>\n   * CMSIS-DSP in ARM::CMSIS Pack\n   * -----------------------------\n   *\n   * The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:\n   * |File/Folder                   |Content                                                                 |\n   * |------------------------------|------------------------------------------------------------------------|\n   * |\\b CMSIS\\\\Documentation\\\\DSP  | This documentation                                                     |\n   * |\\b CMSIS\\\\DSP_Lib             | Software license agreement (license.txt)                               |\n   * |\\b CMSIS\\\\DSP_Lib\\\\Examples   | Example projects demonstrating the usage of the library functions      |\n   * |\\b CMSIS\\\\DSP_Lib\\\\Source     | Source files for rebuilding the library                                |\n   *\n   * <hr>\n   * Revision History of CMSIS-DSP\n   * ------------\n   * Please refer to \\ref ChangeLog_pg.\n   *\n   * Copyright Notice\n   * ------------\n   *\n   * Copyright (C) 2010-2015 Arm Limited. All rights reserved.\n   */\n\n\n/**\n * @defgroup groupMath Basic Math Functions\n */\n\n/**\n * @defgroup groupFastMath Fast Math Functions\n * This set of functions provides a fast approximation to sine, cosine, and square root.\n * As compared to most of the other functions in the CMSIS math library, the fast math functions\n * operate on individual values and not arrays.\n * There are separate functions for Q15, Q31, and floating-point data.\n *\n */\n\n/**\n * @defgroup groupCmplxMath Complex Math Functions\n * This set of functions operates on complex data vectors.\n * The data in the complex arrays is stored in an interleaved fashion\n * (real, imag, real, imag, ...).\n * In the API functions, the number of samples in a complex array refers\n * to the number of complex values; the array contains twice this number of\n * real values.\n */\n\n/**\n * @defgroup groupFilters Filtering Functions\n */\n\n/**\n * @defgroup groupMatrix Matrix Functions\n *\n * This set of functions provides basic matrix math operations.\n * The functions operate on matrix data structures.  For example,\n * the type\n * definition for the floating-point matrix structure is shown\n * below:\n * <pre>\n *     typedef struct\n *     {\n *       uint16_t numRows;     // number of rows of the matrix.\n *       uint16_t numCols;     // number of columns of the matrix.\n *       float32_t *pData;     // points to the data of the matrix.\n *     } arm_matrix_instance_f32;\n * </pre>\n * There are similar definitions for Q15 and Q31 data types.\n *\n * The structure specifies the size of the matrix and then points to\n * an array of data.  The array is of size <code>numRows X numCols</code>\n * and the values are arranged in row order.  That is, the\n * matrix element (i, j) is stored at:\n * <pre>\n *     pData[i*numCols + j]\n * </pre>\n *\n * \\par Init Functions\n * There is an associated initialization function for each type of matrix\n * data structure.\n * The initialization function sets the values of the internal structure fields.\n * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>\n * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types,  respectively.\n *\n * \\par\n * Use of the initialization function is optional. However, if initialization function is used\n * then the instance structure cannot be placed into a const data section.\n * To place the instance structure in a const data\n * section, manually initialize the data structure.  For example:\n * <pre>\n * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>\n * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>\n * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>\n * </pre>\n * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>\n * specifies the number of columns, and <code>pData</code> points to the\n * data array.\n *\n * \\par Size Checking\n * By default all of the matrix functions perform size checking on the input and\n * output matrices. For example, the matrix addition function verifies that the\n * two input matrices and the output matrix all have the same number of rows and\n * columns. If the size check fails the functions return:\n * <pre>\n *     ARM_MATH_SIZE_MISMATCH\n * </pre>\n * Otherwise the functions return\n * <pre>\n *     ARM_MATH_SUCCESS\n * </pre>\n * There is some overhead associated with this matrix size checking.\n * The matrix size checking is enabled via the \\#define\n * <pre>\n *     ARM_MATH_MATRIX_CHECK\n * </pre>\n * within the library project settings.  By default this macro is defined\n * and size checking is enabled. By changing the project settings and\n * undefining this macro size checking is eliminated and the functions\n * run a bit faster. With size checking disabled the functions always\n * return <code>ARM_MATH_SUCCESS</code>.\n */\n\n/**\n * @defgroup groupTransforms Transform Functions\n */\n\n/**\n * @defgroup groupController Controller Functions\n */\n\n/**\n * @defgroup groupStats Statistics Functions\n */\n/**\n * @defgroup groupSupport Support Functions\n */\n\n/**\n * @defgroup groupInterpolation Interpolation Functions\n * These functions perform 1- and 2-dimensional interpolation of data.\n * Linear interpolation is used for 1-dimensional data and\n * bilinear interpolation is used for 2-dimensional data.\n */\n\n/**\n * @defgroup groupExamples Examples\n */\n#ifndef _ARM_MATH_H\n#define _ARM_MATH_H\n\n/* Compiler specific diagnostic adjustment */\n#if   defined ( __CC_ARM )\n\n#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\n\n#elif defined ( __GNUC__ )\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n#elif defined ( __ICCARM__ )\n\n#elif defined ( __TI_ARM__ )\n\n#elif defined ( __CSMC__ )\n\n#elif defined ( __TASKING__ )\n\n#else\n  #error Unknown compiler\n#endif\n\n\n#define __CMSIS_GENERIC         /* disable NVIC and Systick functions */\n\n#if defined(ARM_MATH_CM7)\n  #include \"core_cm7.h\"\n  #define ARM_MATH_DSP\n#elif defined (ARM_MATH_CM4)\n  #include \"core_cm4.h\"\n  #define ARM_MATH_DSP\n#elif defined (ARM_MATH_CM3)\n  #include \"core_cm3.h\"\n#elif defined (ARM_MATH_CM0)\n  #include \"core_cm0.h\"\n  #define ARM_MATH_CM0_FAMILY\n#elif defined (ARM_MATH_CM0PLUS)\n  #include \"core_cm0plus.h\"\n  #define ARM_MATH_CM0_FAMILY\n#elif defined (ARM_MATH_ARMV8MBL)\n  #include \"core_armv8mbl.h\"\n  #define ARM_MATH_CM0_FAMILY\n#elif defined (ARM_MATH_ARMV8MML)\n  #include \"core_armv8mml.h\"\n  #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1))\n    #define ARM_MATH_DSP\n  #endif\n#else\n  #error \"Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML\"\n#endif\n\n#undef  __CMSIS_GENERIC         /* enable NVIC and Systick functions */\n#include \"string.h\"\n#include \"math.h\"\n#ifdef   __cplusplus\nextern \"C\"\n{\n#endif\n\n\n  /**\n   * @brief Macros required for reciprocal calculation in Normalized LMS\n   */\n\n#define DELTA_Q31          (0x100)\n#define DELTA_Q15          0x5\n#define INDEX_MASK         0x0000003F\n#ifndef PI\n  #define PI               3.14159265358979f\n#endif\n\n  /**\n   * @brief Macros required for SINE and COSINE Fast math approximations\n   */\n\n#define FAST_MATH_TABLE_SIZE  512\n#define FAST_MATH_Q31_SHIFT   (32 - 10)\n#define FAST_MATH_Q15_SHIFT   (16 - 10)\n#define CONTROLLER_Q31_SHIFT  (32 - 9)\n#define TABLE_SPACING_Q31     0x400000\n#define TABLE_SPACING_Q15     0x80\n\n  /**\n   * @brief Macros required for SINE and COSINE Controller functions\n   */\n  /* 1.31(q31) Fixed value of 2/360 */\n  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */\n#define INPUT_SPACING         0xB60B61\n\n  /**\n   * @brief Macro for Unaligned Support\n   */\n#ifndef UNALIGNED_SUPPORT_DISABLE\n    #define ALIGN4\n#else\n  #if defined  (__GNUC__)\n    #define ALIGN4 __attribute__((aligned(4)))\n  #else\n    #define ALIGN4 __align(4)\n  #endif\n#endif   /* #ifndef UNALIGNED_SUPPORT_DISABLE */\n\n  /**\n   * @brief Error status returned by some functions in the library.\n   */\n\n  typedef enum\n  {\n    ARM_MATH_SUCCESS = 0,                /**< No error */\n    ARM_MATH_ARGUMENT_ERROR = -1,        /**< One or more arguments are incorrect */\n    ARM_MATH_LENGTH_ERROR = -2,          /**< Length of data buffer is incorrect */\n    ARM_MATH_SIZE_MISMATCH = -3,         /**< Size of matrices is not compatible with the operation. */\n    ARM_MATH_NANINF = -4,                /**< Not-a-number (NaN) or infinity is generated */\n    ARM_MATH_SINGULAR = -5,              /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */\n    ARM_MATH_TEST_FAILURE = -6           /**< Test Failed  */\n  } arm_status;\n\n  /**\n   * @brief 8-bit fractional data type in 1.7 format.\n   */\n  typedef int8_t q7_t;\n\n  /**\n   * @brief 16-bit fractional data type in 1.15 format.\n   */\n  typedef int16_t q15_t;\n\n  /**\n   * @brief 32-bit fractional data type in 1.31 format.\n   */\n  typedef int32_t q31_t;\n\n  /**\n   * @brief 64-bit fractional data type in 1.63 format.\n   */\n  typedef int64_t q63_t;\n\n  /**\n   * @brief 32-bit floating-point type definition.\n   */\n  typedef float float32_t;\n\n  /**\n   * @brief 64-bit floating-point type definition.\n   */\n  typedef double float64_t;\n\n  /**\n   * @brief definition to read/write two 16 bit values.\n   */\n#if   defined ( __CC_ARM )\n  #define __SIMD32_TYPE int32_t __packed\n  #define CMSIS_UNUSED __attribute__((unused))\n  #define CMSIS_INLINE __attribute__((always_inline))\n\n#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED __attribute__((unused))\n  #define CMSIS_INLINE __attribute__((always_inline))\n\n#elif defined ( __GNUC__ )\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED __attribute__((unused))\n  #define CMSIS_INLINE __attribute__((always_inline))\n\n#elif defined ( __ICCARM__ )\n  #define __SIMD32_TYPE int32_t __packed\n  #define CMSIS_UNUSED\n  #define CMSIS_INLINE\n\n#elif defined ( __TI_ARM__ )\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED __attribute__((unused))\n  #define CMSIS_INLINE\n\n#elif defined ( __CSMC__ )\n  #define __SIMD32_TYPE int32_t\n  #define CMSIS_UNUSED\n  #define CMSIS_INLINE\n\n#elif defined ( __TASKING__ )\n  #define __SIMD32_TYPE __unaligned int32_t\n  #define CMSIS_UNUSED\n  #define CMSIS_INLINE\n\n#else\n  #error Unknown compiler\n#endif\n\n#define __SIMD32(addr)        (*(__SIMD32_TYPE **) & (addr))\n#define __SIMD32_CONST(addr)  ((__SIMD32_TYPE *)(addr))\n#define _SIMD32_OFFSET(addr)  (*(__SIMD32_TYPE *)  (addr))\n#define __SIMD64(addr)        (*(int64_t **) & (addr))\n\n#if !defined (ARM_MATH_DSP)\n  /**\n   * @brief definition to pack two 16 bit values.\n   */\n#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0x0000FFFF) | \\\n                                    (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )\n#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) <<    0) & (int32_t)0xFFFF0000) | \\\n                                    (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)  )\n\n#endif /* !defined (ARM_MATH_DSP) */\n\n   /**\n   * @brief definition to pack four 8 bit values.\n   */\n#ifndef ARM_MATH_BIG_ENDIAN\n\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \\\n                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \\\n                                (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \\\n                                (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )\n#else\n\n#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) | \\\n                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) | \\\n                                (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \\\n                                (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )\n\n#endif\n\n\n  /**\n   * @brief Clips Q63 to Q31 values.\n   */\n  CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31(\n  q63_t x)\n  {\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\n      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;\n  }\n\n  /**\n   * @brief Clips Q63 to Q15 values.\n   */\n  CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15(\n  q63_t x)\n  {\n    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?\n      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);\n  }\n\n  /**\n   * @brief Clips Q31 to Q7 values.\n   */\n  CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7(\n  q31_t x)\n  {\n    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?\n      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;\n  }\n\n  /**\n   * @brief Clips Q31 to Q15 values.\n   */\n  CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15(\n  q31_t x)\n  {\n    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?\n      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;\n  }\n\n  /**\n   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.\n   */\n\n  CMSIS_INLINE __STATIC_INLINE q63_t mult32x64(\n  q63_t x,\n  q31_t y)\n  {\n    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +\n            (((q63_t) (x >> 32) * y)));\n  }\n\n  /**\n   * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.\n   */\n\n  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31(\n  q31_t in,\n  q31_t * dst,\n  q31_t * pRecipTable)\n  {\n    q31_t out;\n    uint32_t tempVal;\n    uint32_t index, i;\n    uint32_t signBits;\n\n    if (in > 0)\n    {\n      signBits = ((uint32_t) (__CLZ( in) - 1));\n    }\n    else\n    {\n      signBits = ((uint32_t) (__CLZ(-in) - 1));\n    }\n\n    /* Convert input sample to 1.31 format */\n    in = (in << signBits);\n\n    /* calculation of index for initial approximated Val */\n    index = (uint32_t)(in >> 24);\n    index = (index & INDEX_MASK);\n\n    /* 1.31 with exp 1 */\n    out = pRecipTable[index];\n\n    /* calculation of reciprocal value */\n    /* running approximation for two iterations */\n    for (i = 0U; i < 2U; i++)\n    {\n      tempVal = (uint32_t) (((q63_t) in * out) >> 31);\n      tempVal = 0x7FFFFFFFu - tempVal;\n      /*      1.31 with exp 1 */\n      /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */\n      out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);\n    }\n\n    /* write output */\n    *dst = out;\n\n    /* return num of signbits of out = 1/in value */\n    return (signBits + 1U);\n  }\n\n\n  /**\n   * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15(\n  q15_t in,\n  q15_t * dst,\n  q15_t * pRecipTable)\n  {\n    q15_t out = 0;\n    uint32_t tempVal = 0;\n    uint32_t index = 0, i = 0;\n    uint32_t signBits = 0;\n\n    if (in > 0)\n    {\n      signBits = ((uint32_t)(__CLZ( in) - 17));\n    }\n    else\n    {\n      signBits = ((uint32_t)(__CLZ(-in) - 17));\n    }\n\n    /* Convert input sample to 1.15 format */\n    in = (in << signBits);\n\n    /* calculation of index for initial approximated Val */\n    index = (uint32_t)(in >>  8);\n    index = (index & INDEX_MASK);\n\n    /*      1.15 with exp 1  */\n    out = pRecipTable[index];\n\n    /* calculation of reciprocal value */\n    /* running approximation for two iterations */\n    for (i = 0U; i < 2U; i++)\n    {\n      tempVal = (uint32_t) (((q31_t) in * out) >> 15);\n      tempVal = 0x7FFFu - tempVal;\n      /*      1.15 with exp 1 */\n      out = (q15_t) (((q31_t) out * tempVal) >> 14);\n      /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */\n    }\n\n    /* write output */\n    *dst = out;\n\n    /* return num of signbits of out = 1/in value */\n    return (signBits + 1);\n  }\n\n\n/*\n * @brief C custom defined intrinsic function for M3 and M0 processors\n */\n#if !defined (ARM_MATH_DSP)\n\n  /*\n   * @brief C custom defined QADD8 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s, t, u;\n\n    r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\n    s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\n    t = __SSAT(((((q31_t)x <<  8) >> 24) + (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\n    u = __SSAT(((((q31_t)x      ) >> 24) + (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\n\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB8 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s, t, u;\n\n    r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;\n    s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;\n    t = __SSAT(((((q31_t)x <<  8) >> 24) - (((q31_t)y <<  8) >> 24)), 8) & (int32_t)0x000000FF;\n    u = __SSAT(((((q31_t)x      ) >> 24) - (((q31_t)y      ) >> 24)), 8) & (int32_t)0x000000FF;\n\n    return ((uint32_t)((u << 24) | (t << 16) | (s <<  8) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QADD16 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16(\n  uint32_t x,\n  uint32_t y)\n  {\n/*  q31_t r,     s;  without initialisation 'arm_offset_q15 test' fails  but 'intrinsic' tests pass! for armCC */\n    q31_t r = 0, s = 0;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHADD16 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB16 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHSUB16 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QASX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QASX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHASX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) - (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined QSAX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)), 16) & (int32_t)0x0000FFFF;\n    s = __SSAT(((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SHSAX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX(\n  uint32_t x,\n  uint32_t y)\n  {\n    q31_t r, s;\n\n    r = (((((q31_t)x << 16) >> 16) + (((q31_t)y      ) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n    s = (((((q31_t)x      ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;\n\n    return ((uint32_t)((s << 16) | (r      )));\n  }\n\n\n  /*\n   * @brief C custom defined SMUSDX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\n  }\n\n  /*\n   * @brief C custom defined SMUADX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined QADD for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE int32_t __QADD(\n  int32_t x,\n  int32_t y)\n  {\n    return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));\n  }\n\n\n  /*\n   * @brief C custom defined QSUB for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE int32_t __QSUB(\n  int32_t x,\n  int32_t y)\n  {\n    return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));\n  }\n\n\n  /*\n   * @brief C custom defined SMLAD for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLADX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLSDX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX(\n  uint32_t x,\n  uint32_t y,\n  uint32_t sum)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q31_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLALD for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD(\n  uint32_t x,\n  uint32_t y,\n  uint64_t sum)\n  {\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ( ((q63_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMLALDX for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX(\n  uint32_t x,\n  uint32_t y,\n  uint64_t sum)\n  {\n/*  return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */\n    return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y      ) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ( ((q63_t)sum    )                                  )   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMUAD for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined SMUSD for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD(\n  uint32_t x,\n  uint32_t y)\n  {\n    return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -\n                       ((((q31_t)x      ) >> 16) * (((q31_t)y      ) >> 16))   ));\n  }\n\n\n  /*\n   * @brief C custom defined SXTB16 for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16(\n  uint32_t x)\n  {\n    return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |\n                       ((((q31_t)x <<  8) >>  8) & (q31_t)0xFFFF0000)  ));\n  }\n\n  /*\n   * @brief C custom defined SMMLA for M3 and M0 processors\n   */\n  CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA(\n  int32_t x,\n  int32_t y,\n  int32_t sum)\n  {\n    return (sum + (int32_t) (((int64_t) x * y) >> 32));\n  }\n\n#endif /* !defined (ARM_MATH_DSP) */\n\n\n  /**\n   * @brief Instance structure for the Q7 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;        /**< number of filter coefficients in the filter. */\n    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n  } arm_fir_instance_q7;\n\n  /**\n   * @brief Instance structure for the Q15 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\n    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n  } arm_fir_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;         /**< number of filter coefficients in the filter. */\n    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */\n  } arm_fir_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of filter coefficients in the filter. */\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\n  } arm_fir_instance_f32;\n\n\n  /**\n   * @brief Processing function for the Q7 FIR filter.\n   * @param[in]  S          points to an instance of the Q7 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q7(\n  const arm_fir_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q7 FIR filter.\n   * @param[in,out] S          points to an instance of the Q7 FIR structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed.\n   */\n  void arm_fir_init_q7(\n  arm_fir_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR filter.\n   * @param[in]  S          points to an instance of the Q15 FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_fast_q15(\n  const arm_fir_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR filter.\n   * @param[in,out] S          points to an instance of the Q15 FIR filter structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter. Must be even and greater than or equal to 4.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if\n   * <code>numTaps</code> is not a supported value.\n   */\n  arm_status arm_fir_init_q15(\n  arm_fir_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR filter.\n   * @param[in]  S          points to an instance of the Q31 FIR filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_fast_q31(\n  const arm_fir_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR filter.\n   * @param[in,out] S          points to an instance of the Q31 FIR structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   */\n  void arm_fir_init_q31(\n  arm_fir_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR filter.\n   * @param[in]  S          points to an instance of the floating-point FIR structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_f32(\n  const arm_fir_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR filter.\n   * @param[in,out] S          points to an instance of the floating-point FIR filter structure.\n   * @param[in]     numTaps    Number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of samples that are processed at a time.\n   */\n  void arm_fir_init_f32(\n  arm_fir_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    int8_t numStages;        /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q15_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    q15_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n    int8_t postShift;        /**< Additional shift, in bits, applied to each output sample. */\n  } arm_biquad_casd_df1_inst_q15;\n\n  /**\n   * @brief Instance structure for the Q31 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */\n  } arm_biquad_casd_df1_inst_q31;\n\n  /**\n   * @brief Instance structure for the floating-point Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;       /**< Points to the array of state coefficients.  The array is of length 4*numStages. */\n    float32_t *pCoeffs;      /**< Points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_casd_df1_inst_f32;\n\n\n  /**\n   * @brief Processing function for the Q15 Biquad cascade filter.\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cascade_df1_init_q15(\n  arm_biquad_casd_df1_inst_q15 * S,\n  uint8_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int8_t postShift);\n\n\n  /**\n   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_fast_q15(\n  const arm_biquad_casd_df1_inst_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 Biquad cascade filter\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_fast_q31(\n  const arm_biquad_casd_df1_inst_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the Q31 Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  Shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cascade_df1_init_q31(\n  arm_biquad_casd_df1_inst_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int8_t postShift);\n\n\n  /**\n   * @brief Processing function for the floating-point Biquad cascade filter.\n   * @param[in]  S          points to an instance of the floating-point Biquad cascade structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df1_f32(\n  const arm_biquad_casd_df1_inst_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the floating-point Biquad cascade structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df1_init_f32(\n  arm_biquad_casd_df1_inst_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief Instance structure for the floating-point matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    float32_t *pData;     /**< points to the data of the matrix. */\n  } arm_matrix_instance_f32;\n\n\n  /**\n   * @brief Instance structure for the floating-point matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    float64_t *pData;     /**< points to the data of the matrix. */\n  } arm_matrix_instance_f64;\n\n  /**\n   * @brief Instance structure for the Q15 matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    q15_t *pData;         /**< points to the data of the matrix. */\n  } arm_matrix_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 matrix structure.\n   */\n  typedef struct\n  {\n    uint16_t numRows;     /**< number of rows of the matrix.     */\n    uint16_t numCols;     /**< number of columns of the matrix.  */\n    q31_t *pData;         /**< points to the data of the matrix. */\n  } arm_matrix_instance_q31;\n\n\n  /**\n   * @brief Floating-point matrix addition.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix addition.\n   * @param[in]   pSrcA  points to the first input matrix structure\n   * @param[in]   pSrcB  points to the second input matrix structure\n   * @param[out]  pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix addition.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_add_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point, complex, matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15, complex,  matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Q31, complex, matrix multiplication.\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_cmplx_mult_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix transpose.\n   * @param[in]  pSrc  points to the input matrix\n   * @param[out] pDst  points to the output matrix\n   * @return    The function returns either  <code>ARM_MATH_SIZE_MISMATCH</code>\n   * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_trans_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix multiplication\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix multiplication\n   * @param[in]  pSrcA   points to the first input matrix structure\n   * @param[in]  pSrcB   points to the second input matrix structure\n   * @param[out] pDst    points to output matrix structure\n   * @param[in]  pState  points to the array for storing intermediate results\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState);\n\n\n  /**\n   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA   points to the first input matrix structure\n   * @param[in]  pSrcB   points to the second input matrix structure\n   * @param[out] pDst    points to output matrix structure\n   * @param[in]  pState  points to the array for storing intermediate results\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_fast_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst,\n  q15_t * pState);\n\n\n  /**\n   * @brief Q31 matrix multiplication\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_mult_fast_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_f32(\n  const arm_matrix_instance_f32 * pSrcA,\n  const arm_matrix_instance_f32 * pSrcB,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_q15(\n  const arm_matrix_instance_q15 * pSrcA,\n  const arm_matrix_instance_q15 * pSrcB,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix subtraction\n   * @param[in]  pSrcA  points to the first input matrix structure\n   * @param[in]  pSrcB  points to the second input matrix structure\n   * @param[out] pDst   points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_sub_q31(\n  const arm_matrix_instance_q31 * pSrcA,\n  const arm_matrix_instance_q31 * pSrcB,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief Floating-point matrix scaling.\n   * @param[in]  pSrc   points to the input matrix\n   * @param[in]  scale  scale factor\n   * @param[out] pDst   points to the output matrix\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_f32(\n  const arm_matrix_instance_f32 * pSrc,\n  float32_t scale,\n  arm_matrix_instance_f32 * pDst);\n\n\n  /**\n   * @brief Q15 matrix scaling.\n   * @param[in]  pSrc        points to input matrix\n   * @param[in]  scaleFract  fractional portion of the scale factor\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to output matrix\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_q15(\n  const arm_matrix_instance_q15 * pSrc,\n  q15_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q15 * pDst);\n\n\n  /**\n   * @brief Q31 matrix scaling.\n   * @param[in]  pSrc        points to input matrix\n   * @param[in]  scaleFract  fractional portion of the scale factor\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to output matrix structure\n   * @return     The function returns either\n   * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.\n   */\n  arm_status arm_mat_scale_q31(\n  const arm_matrix_instance_q31 * pSrc,\n  q31_t scaleFract,\n  int32_t shift,\n  arm_matrix_instance_q31 * pDst);\n\n\n  /**\n   * @brief  Q31 matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_q31(\n  arm_matrix_instance_q31 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q31_t * pData);\n\n\n  /**\n   * @brief  Q15 matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_q15(\n  arm_matrix_instance_q15 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  q15_t * pData);\n\n\n  /**\n   * @brief  Floating-point matrix initialization.\n   * @param[in,out] S         points to an instance of the floating-point matrix structure.\n   * @param[in]     nRows     number of rows in the matrix.\n   * @param[in]     nColumns  number of columns in the matrix.\n   * @param[in]     pData     points to the matrix data array.\n   */\n  void arm_mat_init_f32(\n  arm_matrix_instance_f32 * S,\n  uint16_t nRows,\n  uint16_t nColumns,\n  float32_t * pData);\n\n\n\n  /**\n   * @brief Instance structure for the Q15 PID Control.\n   */\n  typedef struct\n  {\n    q15_t A0;           /**< The derived gain, A0 = Kp + Ki + Kd . */\n#if !defined (ARM_MATH_DSP)\n    q15_t A1;\n    q15_t A2;\n#else\n    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/\n#endif\n    q15_t state[3];     /**< The state array of length 3. */\n    q15_t Kp;           /**< The proportional gain. */\n    q15_t Ki;           /**< The integral gain. */\n    q15_t Kd;           /**< The derivative gain. */\n  } arm_pid_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 PID Control.\n   */\n  typedef struct\n  {\n    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */\n    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */\n    q31_t A2;            /**< The derived gain, A2 = Kd . */\n    q31_t state[3];      /**< The state array of length 3. */\n    q31_t Kp;            /**< The proportional gain. */\n    q31_t Ki;            /**< The integral gain. */\n    q31_t Kd;            /**< The derivative gain. */\n  } arm_pid_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point PID Control.\n   */\n  typedef struct\n  {\n    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */\n    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */\n    float32_t A2;          /**< The derived gain, A2 = Kd . */\n    float32_t state[3];    /**< The state array of length 3. */\n    float32_t Kp;          /**< The proportional gain. */\n    float32_t Ki;          /**< The integral gain. */\n    float32_t Kd;          /**< The derivative gain. */\n  } arm_pid_instance_f32;\n\n\n\n  /**\n   * @brief  Initialization function for the floating-point PID Control.\n   * @param[in,out] S               points to an instance of the PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_f32(\n  arm_pid_instance_f32 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the floating-point PID Control.\n   * @param[in,out] S  is an instance of the floating-point PID Control structure\n   */\n  void arm_pid_reset_f32(\n  arm_pid_instance_f32 * S);\n\n\n  /**\n   * @brief  Initialization function for the Q31 PID Control.\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_q31(\n  arm_pid_instance_q31 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the Q31 PID Control.\n   * @param[in,out] S   points to an instance of the Q31 PID Control structure\n   */\n\n  void arm_pid_reset_q31(\n  arm_pid_instance_q31 * S);\n\n\n  /**\n   * @brief  Initialization function for the Q15 PID Control.\n   * @param[in,out] S               points to an instance of the Q15 PID structure.\n   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.\n   */\n  void arm_pid_init_q15(\n  arm_pid_instance_q15 * S,\n  int32_t resetStateFlag);\n\n\n  /**\n   * @brief  Reset function for the Q15 PID Control.\n   * @param[in,out] S  points to an instance of the q15 PID Control structure\n   */\n  void arm_pid_reset_q15(\n  arm_pid_instance_q15 * S);\n\n\n  /**\n   * @brief Instance structure for the floating-point Linear Interpolate function.\n   */\n  typedef struct\n  {\n    uint32_t nValues;           /**< nValues */\n    float32_t x1;               /**< x1 */\n    float32_t xSpacing;         /**< xSpacing */\n    float32_t *pYData;          /**< pointer to the table of Y values */\n  } arm_linear_interp_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    float32_t *pData;   /**< points to the data table. */\n  } arm_bilinear_interp_instance_f32;\n\n   /**\n   * @brief Instance structure for the Q31 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q31_t *pData;       /**< points to the data table. */\n  } arm_bilinear_interp_instance_q31;\n\n   /**\n   * @brief Instance structure for the Q15 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q15_t *pData;       /**< points to the data table. */\n  } arm_bilinear_interp_instance_q15;\n\n   /**\n   * @brief Instance structure for the Q15 bilinear interpolation function.\n   */\n  typedef struct\n  {\n    uint16_t numRows;   /**< number of rows in the data table. */\n    uint16_t numCols;   /**< number of columns in the data table. */\n    q7_t *pData;        /**< points to the data table. */\n  } arm_bilinear_interp_instance_q7;\n\n\n  /**\n   * @brief Q7 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector multiplication.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_mult_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q15_t *pTwiddle;                 /**< points to the Sin twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix2_instance_q15;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_q15(\n  arm_cfft_radix2_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_q15(\n  const arm_cfft_radix2_instance_q15 * S,\n  q15_t * pSrc);\n\n\n  /**\n   * @brief Instance structure for the Q15 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q15_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix4_instance_q15;\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_q15(\n  arm_cfft_radix4_instance_q15 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix4_q15(\n  const arm_cfft_radix4_instance_q15 * S,\n  q15_t * pSrc);\n\n  /**\n   * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q31_t *pTwiddle;                 /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix2_instance_q31;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_q31(\n  arm_cfft_radix2_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_q31(\n  const arm_cfft_radix2_instance_q31 * S,\n  q31_t * pSrc);\n\n  /**\n   * @brief Instance structure for the Q31 CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                 /**< length of the FFT. */\n    uint8_t ifftFlag;                /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;          /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    q31_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    uint16_t *pBitRevTable;          /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;       /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;           /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n  } arm_cfft_radix4_instance_q31;\n\n/* Deprecated */\n  void arm_cfft_radix4_q31(\n  const arm_cfft_radix4_instance_q31 * S,\n  q31_t * pSrc);\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_q31(\n  arm_cfft_radix4_instance_q31 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\n  } arm_cfft_radix2_instance_f32;\n\n/* Deprecated */\n  arm_status arm_cfft_radix2_init_f32(\n  arm_cfft_radix2_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix2_f32(\n  const arm_cfft_radix2_instance_f32 * S,\n  float32_t * pSrc);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    uint8_t ifftFlag;                  /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */\n    uint8_t bitReverseFlag;            /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */\n    float32_t *pTwiddle;               /**< points to the Twiddle factor table. */\n    uint16_t *pBitRevTable;            /**< points to the bit reversal table. */\n    uint16_t twidCoefModifier;         /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    uint16_t bitRevFactor;             /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */\n    float32_t onebyfftLen;             /**< value of 1/fftLen. */\n  } arm_cfft_radix4_instance_f32;\n\n/* Deprecated */\n  arm_status arm_cfft_radix4_init_f32(\n  arm_cfft_radix4_instance_f32 * S,\n  uint16_t fftLen,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n/* Deprecated */\n  void arm_cfft_radix4_f32(\n  const arm_cfft_radix4_instance_f32 * S,\n  float32_t * pSrc);\n\n  /**\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const q15_t *pTwiddle;             /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_q15;\n\nvoid arm_cfft_q15(\n    const arm_cfft_instance_q15 * S,\n    q15_t * p1,\n    uint8_t ifftFlag,\n    uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the fixed-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const q31_t *pTwiddle;             /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_q31;\n\nvoid arm_cfft_q31(\n    const arm_cfft_instance_q31 * S,\n    q31_t * p1,\n    uint8_t ifftFlag,\n    uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the floating-point CFFT/CIFFT function.\n   */\n  typedef struct\n  {\n    uint16_t fftLen;                   /**< length of the FFT. */\n    const float32_t *pTwiddle;         /**< points to the Twiddle factor table. */\n    const uint16_t *pBitRevTable;      /**< points to the bit reversal table. */\n    uint16_t bitRevLength;             /**< bit reversal table length. */\n  } arm_cfft_instance_f32;\n\n  void arm_cfft_f32(\n  const arm_cfft_instance_f32 * S,\n  float32_t * p1,\n  uint8_t ifftFlag,\n  uint8_t bitReverseFlag);\n\n  /**\n   * @brief Instance structure for the Q15 RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                      /**< length of the real FFT. */\n    uint8_t ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    q15_t *pTwiddleAReal;                     /**< points to the real twiddle factor table. */\n    q15_t *pTwiddleBReal;                     /**< points to the imag twiddle factor table. */\n    const arm_cfft_instance_q15 *pCfft;       /**< points to the complex FFT instance. */\n  } arm_rfft_instance_q15;\n\n  arm_status arm_rfft_init_q15(\n  arm_rfft_instance_q15 * S,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_q15(\n  const arm_rfft_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst);\n\n  /**\n   * @brief Instance structure for the Q31 RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    q31_t *pTwiddleAReal;                       /**< points to the real twiddle factor table. */\n    q31_t *pTwiddleBReal;                       /**< points to the imag twiddle factor table. */\n    const arm_cfft_instance_q31 *pCfft;         /**< points to the complex FFT instance. */\n  } arm_rfft_instance_q31;\n\n  arm_status arm_rfft_init_q31(\n  arm_rfft_instance_q31 * S,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_q31(\n  const arm_rfft_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst);\n\n  /**\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\n   */\n  typedef struct\n  {\n    uint32_t fftLenReal;                        /**< length of the real FFT. */\n    uint16_t fftLenBy2;                         /**< length of the complex FFT. */\n    uint8_t ifftFlagR;                          /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */\n    uint8_t bitReverseFlagR;                    /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */\n    uint32_t twidCoefRModifier;                     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */\n    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */\n    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */\n    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */\n  } arm_rfft_instance_f32;\n\n  arm_status arm_rfft_init_f32(\n  arm_rfft_instance_f32 * S,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint32_t fftLenReal,\n  uint32_t ifftFlagR,\n  uint32_t bitReverseFlag);\n\n  void arm_rfft_f32(\n  const arm_rfft_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst);\n\n  /**\n   * @brief Instance structure for the floating-point RFFT/RIFFT function.\n   */\ntypedef struct\n  {\n    arm_cfft_instance_f32 Sint;      /**< Internal CFFT structure. */\n    uint16_t fftLenRFFT;             /**< length of the real sequence */\n    float32_t * pTwiddleRFFT;        /**< Twiddle factors real stage  */\n  } arm_rfft_fast_instance_f32 ;\n\narm_status arm_rfft_fast_init_f32 (\n   arm_rfft_fast_instance_f32 * S,\n   uint16_t fftLen);\n\nvoid arm_rfft_fast_f32(\n  arm_rfft_fast_instance_f32 * S,\n  float32_t * p, float32_t * pOut,\n  uint8_t ifftFlag);\n\n  /**\n   * @brief Instance structure for the floating-point DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    float32_t normalize;                 /**< normalizing factor. */\n    float32_t *pTwiddle;                 /**< points to the twiddle factor table. */\n    float32_t *pCosFactor;               /**< points to the cosFactor table. */\n    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_f32;\n\n\n  /**\n   * @brief  Initialization function for the floating-point DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of floating-point DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of floating-point RFFT/RIFFT structure.\n   * @param[in]     S_CFFT     points to an instance of floating-point CFFT/CIFFT structure.\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_f32(\n  arm_dct4_instance_f32 * S,\n  arm_rfft_instance_f32 * S_RFFT,\n  arm_cfft_radix4_instance_f32 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  float32_t normalize);\n\n\n  /**\n   * @brief Processing function for the floating-point DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the floating-point DCT4/IDCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_f32(\n  const arm_dct4_instance_f32 * S,\n  float32_t * pState,\n  float32_t * pInlineBuffer);\n\n\n  /**\n   * @brief Instance structure for the Q31 DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    q31_t normalize;                     /**< normalizing factor. */\n    q31_t *pTwiddle;                     /**< points to the twiddle factor table. */\n    q31_t *pCosFactor;                   /**< points to the cosFactor table. */\n    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_q31;\n\n\n  /**\n   * @brief  Initialization function for the Q31 DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of Q31 DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of Q31 RFFT/RIFFT structure\n   * @param[in]     S_CFFT     points to an instance of Q31 CFFT/CIFFT structure\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_q31(\n  arm_dct4_instance_q31 * S,\n  arm_rfft_instance_q31 * S_RFFT,\n  arm_cfft_radix4_instance_q31 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q31_t normalize);\n\n\n  /**\n   * @brief Processing function for the Q31 DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the Q31 DCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_q31(\n  const arm_dct4_instance_q31 * S,\n  q31_t * pState,\n  q31_t * pInlineBuffer);\n\n\n  /**\n   * @brief Instance structure for the Q15 DCT4/IDCT4 function.\n   */\n  typedef struct\n  {\n    uint16_t N;                          /**< length of the DCT4. */\n    uint16_t Nby2;                       /**< half of the length of the DCT4. */\n    q15_t normalize;                     /**< normalizing factor. */\n    q15_t *pTwiddle;                     /**< points to the twiddle factor table. */\n    q15_t *pCosFactor;                   /**< points to the cosFactor table. */\n    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */\n    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */\n  } arm_dct4_instance_q15;\n\n\n  /**\n   * @brief  Initialization function for the Q15 DCT4/IDCT4.\n   * @param[in,out] S          points to an instance of Q15 DCT4/IDCT4 structure.\n   * @param[in]     S_RFFT     points to an instance of Q15 RFFT/RIFFT structure.\n   * @param[in]     S_CFFT     points to an instance of Q15 CFFT/CIFFT structure.\n   * @param[in]     N          length of the DCT4.\n   * @param[in]     Nby2       half of the length of the DCT4.\n   * @param[in]     normalize  normalizing factor.\n   * @return      arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.\n   */\n  arm_status arm_dct4_init_q15(\n  arm_dct4_instance_q15 * S,\n  arm_rfft_instance_q15 * S_RFFT,\n  arm_cfft_radix4_instance_q15 * S_CFFT,\n  uint16_t N,\n  uint16_t Nby2,\n  q15_t normalize);\n\n\n  /**\n   * @brief Processing function for the Q15 DCT4/IDCT4.\n   * @param[in]     S              points to an instance of the Q15 DCT4 structure.\n   * @param[in]     pState         points to state buffer.\n   * @param[in,out] pInlineBuffer  points to the in-place input and output buffer.\n   */\n  void arm_dct4_q15(\n  const arm_dct4_instance_q15 * S,\n  q15_t * pState,\n  q15_t * pInlineBuffer);\n\n\n  /**\n   * @brief Floating-point vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector addition.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_add_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector subtraction.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_sub_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a floating-point vector by a scalar.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  scale      scale factor to be applied\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_scale_f32(\n  float32_t * pSrc,\n  float32_t scale,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q7 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q7(\n  q7_t * pSrc,\n  q7_t scaleFract,\n  int8_t shift,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q15 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q15(\n  q15_t * pSrc,\n  q15_t scaleFract,\n  int8_t shift,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Multiplies a Q31 vector by a scalar.\n   * @param[in]  pSrc        points to the input vector\n   * @param[in]  scaleFract  fractional portion of the scale value\n   * @param[in]  shift       number of bits to shift the result by\n   * @param[out] pDst        points to the output vector\n   * @param[in]  blockSize   number of samples in the vector\n   */\n  void arm_scale_q31(\n  q31_t * pSrc,\n  q31_t scaleFract,\n  int8_t shift,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q7 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Floating-point vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q15 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Q31 vector absolute value.\n   * @param[in]  pSrc       points to the input buffer\n   * @param[out] pDst       points to the output buffer\n   * @param[in]  blockSize  number of samples in each vector\n   */\n  void arm_abs_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Dot product of floating-point vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  uint32_t blockSize,\n  float32_t * result);\n\n\n  /**\n   * @brief Dot product of Q7 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q7(\n  q7_t * pSrcA,\n  q7_t * pSrcB,\n  uint32_t blockSize,\n  q31_t * result);\n\n\n  /**\n   * @brief Dot product of Q15 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  uint32_t blockSize,\n  q63_t * result);\n\n\n  /**\n   * @brief Dot product of Q31 vectors.\n   * @param[in]  pSrcA      points to the first input vector\n   * @param[in]  pSrcB      points to the second input vector\n   * @param[in]  blockSize  number of samples in each vector\n   * @param[out] result     output result returned here\n   */\n  void arm_dot_prod_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  uint32_t blockSize,\n  q63_t * result);\n\n\n  /**\n   * @brief  Shifts the elements of a Q7 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q7(\n  q7_t * pSrc,\n  int8_t shiftBits,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Shifts the elements of a Q15 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q15(\n  q15_t * pSrc,\n  int8_t shiftBits,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Shifts the elements of a Q31 vector a specified number of bits.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  shiftBits  number of bits to shift.  A positive value shifts left; a negative value shifts right.\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_shift_q31(\n  q31_t * pSrc,\n  int8_t shiftBits,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a floating-point vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_f32(\n  float32_t * pSrc,\n  float32_t offset,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q7 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q7(\n  q7_t * pSrc,\n  q7_t offset,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q15 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q15(\n  q15_t * pSrc,\n  q15_t offset,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Adds a constant offset to a Q31 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[in]  offset     is the offset to be added\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_offset_q31(\n  q31_t * pSrc,\n  q31_t offset,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a floating-point vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q7 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q15 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Negates the elements of a Q31 vector.\n   * @param[in]  pSrc       points to the input vector\n   * @param[out] pDst       points to the output vector\n   * @param[in]  blockSize  number of samples in the vector\n   */\n  void arm_negate_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a floating-point vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q7 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q7(\n  q7_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q15 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Copies the elements of a Q31 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_copy_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a floating-point vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_f32(\n  float32_t value,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q7 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q7(\n  q7_t value,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q15 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q15(\n  q15_t value,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Fills a constant value into a Q31 vector.\n   * @param[in]  value      input value to be filled\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_fill_q31(\n  q31_t value,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Convolution of floating-point sequences.\n * @param[in]  pSrcA    points to the first input sequence.\n * @param[in]  srcALen  length of the first input sequence.\n * @param[in]  pSrcB    points to the second input sequence.\n * @param[in]  srcBLen  length of the second input sequence.\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\n */\n  void arm_conv_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\n   */\n  void arm_conv_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n/**\n * @brief Convolution of Q15 sequences.\n * @param[in]  pSrcA    points to the first input sequence.\n * @param[in]  srcALen  length of the first input sequence.\n * @param[in]  pSrcB    points to the second input sequence.\n * @param[in]  srcBLen  length of the second input sequence.\n * @param[out] pDst     points to the location where the output result is written.  Length srcALen+srcBLen-1.\n */\n  void arm_conv_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_fast_q15(\n          q15_t * pSrcA,\n          uint32_t srcALen,\n          q15_t * pSrcB,\n          uint32_t srcBLen,\n          q15_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer of size min(srcALen, srcBLen).\n   */\n  void arm_conv_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Convolution of Q31 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n  /**\n   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n    /**\n   * @brief Convolution of Q7 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length srcALen+srcBLen-1.\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   */\n  void arm_conv_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Convolution of Q7 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length srcALen+srcBLen-1.\n   */\n  void arm_conv_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst);\n\n\n  /**\n   * @brief Partial convolution of floating-point sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Partial convolution of Q31 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Partial convolution of Q7 sequences\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @param[in]  pScratch1   points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2   points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n/**\n   * @brief Partial convolution of Q7 sequences.\n   * @param[in]  pSrcA       points to the first input sequence.\n   * @param[in]  srcALen     length of the first input sequence.\n   * @param[in]  pSrcB       points to the second input sequence.\n   * @param[in]  srcBLen     length of the second input sequence.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  firstIndex  is the first output sample to start with.\n   * @param[in]  numPoints   is the number of output points to be computed.\n   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].\n   */\n  arm_status arm_conv_partial_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  uint32_t firstIndex,\n  uint32_t numPoints);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    q15_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\n    q15_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    q31_t *pCoeffs;             /**< points to the coefficient array. The array is of length numTaps.*/\n    q31_t *pState;              /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR decimator.\n   */\n  typedef struct\n  {\n    uint8_t M;                  /**< decimation factor. */\n    uint16_t numTaps;           /**< number of coefficients in the filter. */\n    float32_t *pCoeffs;         /**< points to the coefficient array. The array is of length numTaps.*/\n    float32_t *pState;          /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n  } arm_fir_decimate_instance_f32;\n\n\n  /**\n   * @brief Processing function for the floating-point FIR decimator.\n   * @param[in]  S          points to an instance of the floating-point FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_f32(\n  const arm_fir_decimate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR decimator.\n   * @param[in,out] S          points to an instance of the floating-point FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_f32(\n  arm_fir_decimate_instance_f32 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR decimator.\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_fast_q15(\n  const arm_fir_decimate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR decimator.\n   * @param[in,out] S          points to an instance of the Q15 FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_q15(\n  arm_fir_decimate_instance_q15 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR decimator.\n   * @param[in]  S     points to an instance of the Q31 FIR decimator structure.\n   * @param[in]  pSrc  points to the block of input data.\n   * @param[out] pDst  points to the block of output data\n   * @param[in] blockSize number of input samples to process per call.\n   */\n  void arm_fir_decimate_q31(\n  const arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n  /**\n   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.\n   * @param[in]  S          points to an instance of the Q31 FIR decimator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_decimate_fast_q31(\n  arm_fir_decimate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR decimator.\n   * @param[in,out] S          points to an instance of the Q31 FIR decimator structure.\n   * @param[in]     numTaps    number of coefficients in the filter.\n   * @param[in]     M          decimation factor.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * <code>blockSize</code> is not a multiple of <code>M</code>.\n   */\n  arm_status arm_fir_decimate_init_q31(\n  arm_fir_decimate_instance_q31 * S,\n  uint16_t numTaps,\n  uint8_t M,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                      /**< upsample factor. */\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\n    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\n    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\n  } arm_fir_interpolate_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                      /**< upsample factor. */\n    uint16_t phaseLength;           /**< length of each polyphase filter component. */\n    q31_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */\n    q31_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */\n  } arm_fir_interpolate_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR interpolator.\n   */\n  typedef struct\n  {\n    uint8_t L;                     /**< upsample factor. */\n    uint16_t phaseLength;          /**< length of each polyphase filter component. */\n    float32_t *pCoeffs;            /**< points to the coefficient array. The array is of length L*phaseLength. */\n    float32_t *pState;             /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */\n  } arm_fir_interpolate_instance_f32;\n\n\n  /**\n   * @brief Processing function for the Q15 FIR interpolator.\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_q15(\n  const arm_fir_interpolate_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 FIR interpolator.\n   * @param[in,out] S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_q15(\n  arm_fir_interpolate_instance_q15 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR interpolator.\n   * @param[in]  S          points to an instance of the Q15 FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_q31(\n  const arm_fir_interpolate_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 FIR interpolator.\n   * @param[in,out] S          points to an instance of the Q31 FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_q31(\n  arm_fir_interpolate_instance_q31 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR interpolator.\n   * @param[in]  S          points to an instance of the floating-point FIR interpolator structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of input samples to process per call.\n   */\n  void arm_fir_interpolate_f32(\n  const arm_fir_interpolate_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point FIR interpolator.\n   * @param[in,out] S          points to an instance of the floating-point FIR interpolator structure.\n   * @param[in]     L          upsample factor.\n   * @param[in]     numTaps    number of filter coefficients in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficient buffer.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     blockSize  number of input samples to process per call.\n   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if\n   * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.\n   */\n  arm_status arm_fir_interpolate_init_f32(\n  arm_fir_interpolate_instance_f32 * S,\n  uint8_t L,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the high precision Q31 Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */\n    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */\n    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */\n  } arm_biquad_cas_df1_32x64_ins_q31;\n\n\n  /**\n   * @param[in]  S          points to an instance of the high precision Q31 Biquad cascade filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cas_df1_32x64_q31(\n  const arm_biquad_cas_df1_32x64_ins_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @param[in,out] S          points to an instance of the high precision Q31 Biquad cascade filter structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     postShift  shift to be applied to the output. Varies according to the coefficients format\n   */\n  void arm_biquad_cas_df1_32x64_init_q31(\n  arm_biquad_cas_df1_32x64_ins_q31 * S,\n  uint8_t numStages,\n  q31_t * pCoeffs,\n  q63_t * pState,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_df2T_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 4*numStages. */\n    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_stereo_df2T_instance_f32;\n\n  /**\n   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.\n   */\n  typedef struct\n  {\n    uint8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */\n    float64_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */\n    float64_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */\n  } arm_biquad_cascade_df2T_instance_f64;\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df2T_f32(\n  const arm_biquad_cascade_df2T_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_stereo_df2T_f32(\n  const arm_biquad_cascade_stereo_df2T_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in]  S          points to an instance of the filter data structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_biquad_cascade_df2T_f64(\n  const arm_biquad_cascade_df2T_instance_f64 * S,\n  float64_t * pSrc,\n  float64_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df2T_init_f32(\n  arm_biquad_cascade_df2T_instance_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_stereo_df2T_init_f32(\n  arm_biquad_cascade_stereo_df2T_instance_f32 * S,\n  uint8_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.\n   * @param[in,out] S          points to an instance of the filter data structure.\n   * @param[in]     numStages  number of 2nd order stages in the filter.\n   * @param[in]     pCoeffs    points to the filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   */\n  void arm_biquad_cascade_df2T_init_f64(\n  arm_biquad_cascade_df2T_instance_f64 * S,\n  uint8_t numStages,\n  float64_t * pCoeffs,\n  float64_t * pState);\n\n\n  /**\n   * @brief Instance structure for the Q15 FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\n    q15_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages. */\n    q31_t *pCoeffs;                      /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point FIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of filter stages. */\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */\n    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */\n  } arm_fir_lattice_instance_f32;\n\n\n  /**\n   * @brief Initialization function for the Q15 FIR lattice filter.\n   * @param[in] S          points to an instance of the Q15 FIR lattice structure.\n   * @param[in] numStages  number of filter stages.\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages.\n   */\n  void arm_fir_lattice_init_q15(\n  arm_fir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pCoeffs,\n  q15_t * pState);\n\n\n  /**\n   * @brief Processing function for the Q15 FIR lattice filter.\n   * @param[in]  S          points to an instance of the Q15 FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_q15(\n  const arm_fir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the Q31 FIR lattice filter.\n   * @param[in] S          points to an instance of the Q31 FIR lattice structure.\n   * @param[in] numStages  number of filter stages.\n   * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n   * @param[in] pState     points to the state buffer.   The array is of length numStages.\n   */\n  void arm_fir_lattice_init_q31(\n  arm_fir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pCoeffs,\n  q31_t * pState);\n\n\n  /**\n   * @brief Processing function for the Q31 FIR lattice filter.\n   * @param[in]  S          points to an instance of the Q31 FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_q31(\n  const arm_fir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Initialization function for the floating-point FIR lattice filter.\n * @param[in] S          points to an instance of the floating-point FIR lattice structure.\n * @param[in] numStages  number of filter stages.\n * @param[in] pCoeffs    points to the coefficient buffer.  The array is of length numStages.\n * @param[in] pState     points to the state buffer.  The array is of length numStages.\n */\n  void arm_fir_lattice_init_f32(\n  arm_fir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pCoeffs,\n  float32_t * pState);\n\n\n  /**\n   * @brief Processing function for the floating-point FIR lattice filter.\n   * @param[in]  S          points to an instance of the floating-point FIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_fir_lattice_f32(\n  const arm_fir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    q15_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\n    q15_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\n    q15_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q31 IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    q31_t *pState;                       /**< points to the state variable array. The array is of length numStages+blockSize. */\n    q31_t *pkCoeffs;                     /**< points to the reflection coefficient array. The array is of length numStages. */\n    q31_t *pvCoeffs;                     /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_q31;\n\n  /**\n   * @brief Instance structure for the floating-point IIR lattice filter.\n   */\n  typedef struct\n  {\n    uint16_t numStages;                  /**< number of stages in the filter. */\n    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages+blockSize. */\n    float32_t *pkCoeffs;                 /**< points to the reflection coefficient array. The array is of length numStages. */\n    float32_t *pvCoeffs;                 /**< points to the ladder coefficient array. The array is of length numStages+1. */\n  } arm_iir_lattice_instance_f32;\n\n\n  /**\n   * @brief Processing function for the floating-point IIR lattice filter.\n   * @param[in]  S          points to an instance of the floating-point IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_f32(\n  const arm_iir_lattice_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the floating-point IIR lattice filter.\n   * @param[in] S          points to an instance of the floating-point IIR lattice structure.\n   * @param[in] numStages  number of stages in the filter.\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize-1.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_init_f32(\n  arm_iir_lattice_instance_f32 * S,\n  uint16_t numStages,\n  float32_t * pkCoeffs,\n  float32_t * pvCoeffs,\n  float32_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 IIR lattice filter.\n   * @param[in]  S          points to an instance of the Q31 IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_q31(\n  const arm_iir_lattice_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for the Q31 IIR lattice filter.\n   * @param[in] S          points to an instance of the Q31 IIR lattice structure.\n   * @param[in] numStages  number of stages in the filter.\n   * @param[in] pkCoeffs   points to the reflection coefficient buffer.  The array is of length numStages.\n   * @param[in] pvCoeffs   points to the ladder coefficient buffer.  The array is of length numStages+1.\n   * @param[in] pState     points to the state buffer.  The array is of length numStages+blockSize.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_init_q31(\n  arm_iir_lattice_instance_q31 * S,\n  uint16_t numStages,\n  q31_t * pkCoeffs,\n  q31_t * pvCoeffs,\n  q31_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 IIR lattice filter.\n   * @param[in]  S          points to an instance of the Q15 IIR lattice structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[out] pDst       points to the block of output data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_iir_lattice_q15(\n  const arm_iir_lattice_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n/**\n * @brief Initialization function for the Q15 IIR lattice filter.\n * @param[in] S          points to an instance of the fixed-point Q15 IIR lattice structure.\n * @param[in] numStages  number of stages in the filter.\n * @param[in] pkCoeffs   points to reflection coefficient buffer.  The array is of length numStages.\n * @param[in] pvCoeffs   points to ladder coefficient buffer.  The array is of length numStages+1.\n * @param[in] pState     points to state buffer.  The array is of length numStages+blockSize.\n * @param[in] blockSize  number of samples to process per call.\n */\n  void arm_iir_lattice_init_q15(\n  arm_iir_lattice_instance_q15 * S,\n  uint16_t numStages,\n  q15_t * pkCoeffs,\n  q15_t * pvCoeffs,\n  q15_t * pState,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the floating-point LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */\n    float32_t mu;        /**< step size that controls filter coefficient updates. */\n  } arm_lms_instance_f32;\n\n\n  /**\n   * @brief Processing function for floating-point LMS filter.\n   * @param[in]  S          points to an instance of the floating-point LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_f32(\n  const arm_lms_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for floating-point LMS filter.\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to the coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_lms_init_f32(\n  arm_lms_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q15 LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\n    q15_t mu;            /**< step size that controls filter coefficient updates. */\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\n  } arm_lms_instance_q15;\n\n\n  /**\n   * @brief Initialization function for the Q15 LMS filter.\n   * @param[in] S          points to an instance of the Q15 LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to the coefficient buffer.\n   * @param[in] pState     points to the state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_init_q15(\n  arm_lms_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint32_t postShift);\n\n\n  /**\n   * @brief Processing function for Q15 LMS filter.\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_q15(\n  const arm_lms_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q31 LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;    /**< number of coefficients in the filter. */\n    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */\n    q31_t mu;            /**< step size that controls filter coefficient updates. */\n    uint32_t postShift;  /**< bit shift applied to coefficients. */\n  } arm_lms_instance_q31;\n\n\n  /**\n   * @brief Processing function for Q31 LMS filter.\n   * @param[in]  S          points to an instance of the Q15 LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_q31(\n  const arm_lms_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q31 LMS filter.\n   * @param[in] S          points to an instance of the Q31 LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_init_q31(\n  arm_lms_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint32_t postShift);\n\n\n  /**\n   * @brief Instance structure for the floating-point normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\n    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */\n    float32_t mu;         /**< step size that control filter coefficient updates. */\n    float32_t energy;     /**< saves previous frame energy. */\n    float32_t x0;         /**< saves previous input sample. */\n  } arm_lms_norm_instance_f32;\n\n\n  /**\n   * @brief Processing function for floating-point normalized LMS filter.\n   * @param[in]  S          points to an instance of the floating-point normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_f32(\n  arm_lms_norm_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pRef,\n  float32_t * pOut,\n  float32_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for floating-point normalized LMS filter.\n   * @param[in] S          points to an instance of the floating-point LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   */\n  void arm_lms_norm_init_f32(\n  arm_lms_norm_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  float32_t mu,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Instance structure for the Q31 normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< number of coefficients in the filter. */\n    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\n    q31_t mu;             /**< step size that controls filter coefficient updates. */\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\n    q31_t *recipTable;    /**< points to the reciprocal initial value table. */\n    q31_t energy;         /**< saves previous frame energy. */\n    q31_t x0;             /**< saves previous input sample. */\n  } arm_lms_norm_instance_q31;\n\n\n  /**\n   * @brief Processing function for Q31 normalized LMS filter.\n   * @param[in]  S          points to an instance of the Q31 normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_q31(\n  arm_lms_norm_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pRef,\n  q31_t * pOut,\n  q31_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q31 normalized LMS filter.\n   * @param[in] S          points to an instance of the Q31 normalized LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_norm_init_q31(\n  arm_lms_norm_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  q31_t mu,\n  uint32_t blockSize,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Instance structure for the Q15 normalized LMS filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;     /**< Number of coefficients in the filter. */\n    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */\n    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */\n    q15_t mu;             /**< step size that controls filter coefficient updates. */\n    uint8_t postShift;    /**< bit shift applied to coefficients. */\n    q15_t *recipTable;    /**< Points to the reciprocal initial value table. */\n    q15_t energy;         /**< saves previous frame energy. */\n    q15_t x0;             /**< saves previous input sample. */\n  } arm_lms_norm_instance_q15;\n\n\n  /**\n   * @brief Processing function for Q15 normalized LMS filter.\n   * @param[in]  S          points to an instance of the Q15 normalized LMS filter structure.\n   * @param[in]  pSrc       points to the block of input data.\n   * @param[in]  pRef       points to the block of reference data.\n   * @param[out] pOut       points to the block of output data.\n   * @param[out] pErr       points to the block of error data.\n   * @param[in]  blockSize  number of samples to process.\n   */\n  void arm_lms_norm_q15(\n  arm_lms_norm_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pRef,\n  q15_t * pOut,\n  q15_t * pErr,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Initialization function for Q15 normalized LMS filter.\n   * @param[in] S          points to an instance of the Q15 normalized LMS filter structure.\n   * @param[in] numTaps    number of filter coefficients.\n   * @param[in] pCoeffs    points to coefficient buffer.\n   * @param[in] pState     points to state buffer.\n   * @param[in] mu         step size that controls filter coefficient updates.\n   * @param[in] blockSize  number of samples to process.\n   * @param[in] postShift  bit shift applied to coefficients.\n   */\n  void arm_lms_norm_init_q15(\n  arm_lms_norm_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  q15_t mu,\n  uint32_t blockSize,\n  uint8_t postShift);\n\n\n  /**\n   * @brief Correlation of floating-point sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_f32(\n  float32_t * pSrcA,\n  uint32_t srcALen,\n  float32_t * pSrcB,\n  uint32_t srcBLen,\n  float32_t * pDst);\n\n\n   /**\n   * @brief Correlation of Q15 sequences\n   * @param[in]  pSrcA     points to the first input sequence.\n   * @param[in]  srcALen   length of the first input sequence.\n   * @param[in]  pSrcB     points to the second input sequence.\n   * @param[in]  srcBLen   length of the second input sequence.\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   */\n  void arm_correlate_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Correlation of Q15 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n\n  void arm_correlate_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n\n  void arm_correlate_fast_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.\n   * @param[in]  pSrcA     points to the first input sequence.\n   * @param[in]  srcALen   length of the first input sequence.\n   * @param[in]  pSrcB     points to the second input sequence.\n   * @param[in]  srcBLen   length of the second input sequence.\n   * @param[out] pDst      points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch  points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   */\n  void arm_correlate_fast_opt_q15(\n  q15_t * pSrcA,\n  uint32_t srcALen,\n  q15_t * pSrcB,\n  uint32_t srcBLen,\n  q15_t * pDst,\n  q15_t * pScratch);\n\n\n  /**\n   * @brief Correlation of Q31 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n  /**\n   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_fast_q31(\n  q31_t * pSrcA,\n  uint32_t srcALen,\n  q31_t * pSrcB,\n  uint32_t srcBLen,\n  q31_t * pDst);\n\n\n /**\n   * @brief Correlation of Q7 sequences.\n   * @param[in]  pSrcA      points to the first input sequence.\n   * @param[in]  srcALen    length of the first input sequence.\n   * @param[in]  pSrcB      points to the second input sequence.\n   * @param[in]  srcBLen    length of the second input sequence.\n   * @param[out] pDst       points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   * @param[in]  pScratch1  points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.\n   * @param[in]  pScratch2  points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).\n   */\n  void arm_correlate_opt_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst,\n  q15_t * pScratch1,\n  q15_t * pScratch2);\n\n\n  /**\n   * @brief Correlation of Q7 sequences.\n   * @param[in]  pSrcA    points to the first input sequence.\n   * @param[in]  srcALen  length of the first input sequence.\n   * @param[in]  pSrcB    points to the second input sequence.\n   * @param[in]  srcBLen  length of the second input sequence.\n   * @param[out] pDst     points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.\n   */\n  void arm_correlate_q7(\n  q7_t * pSrcA,\n  uint32_t srcALen,\n  q7_t * pSrcB,\n  uint32_t srcBLen,\n  q7_t * pDst);\n\n\n  /**\n   * @brief Instance structure for the floating-point sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_f32;\n\n  /**\n   * @brief Instance structure for the Q31 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q31;\n\n  /**\n   * @brief Instance structure for the Q15 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q15;\n\n  /**\n   * @brief Instance structure for the Q7 sparse FIR filter.\n   */\n  typedef struct\n  {\n    uint16_t numTaps;             /**< number of coefficients in the filter. */\n    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */\n    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */\n    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/\n    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */\n    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */\n  } arm_fir_sparse_instance_q7;\n\n\n  /**\n   * @brief Processing function for the floating-point sparse FIR filter.\n   * @param[in]  S           points to an instance of the floating-point sparse FIR structure.\n   * @param[in]  pSrc        points to the block of input data.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize   number of input samples to process per call.\n   */\n  void arm_fir_sparse_f32(\n  arm_fir_sparse_instance_f32 * S,\n  float32_t * pSrc,\n  float32_t * pDst,\n  float32_t * pScratchIn,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the floating-point sparse FIR filter.\n   * @param[in,out] S          points to an instance of the floating-point sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_f32(\n  arm_fir_sparse_instance_f32 * S,\n  uint16_t numTaps,\n  float32_t * pCoeffs,\n  float32_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q31 sparse FIR filter.\n   * @param[in]  S           points to an instance of the Q31 sparse FIR structure.\n   * @param[in]  pSrc        points to the block of input data.\n   * @param[out] pDst        points to the block of output data\n   * @param[in]  pScratchIn  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize   number of input samples to process per call.\n   */\n  void arm_fir_sparse_q31(\n  arm_fir_sparse_instance_q31 * S,\n  q31_t * pSrc,\n  q31_t * pDst,\n  q31_t * pScratchIn,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q31 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q31 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q31(\n  arm_fir_sparse_instance_q31 * S,\n  uint16_t numTaps,\n  q31_t * pCoeffs,\n  q31_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q15 sparse FIR filter.\n   * @param[in]  S            points to an instance of the Q15 sparse FIR structure.\n   * @param[in]  pSrc         points to the block of input data.\n   * @param[out] pDst         points to the block of output data\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize    number of input samples to process per call.\n   */\n  void arm_fir_sparse_q15(\n  arm_fir_sparse_instance_q15 * S,\n  q15_t * pSrc,\n  q15_t * pDst,\n  q15_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q15 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q15 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q15(\n  arm_fir_sparse_instance_q15 * S,\n  uint16_t numTaps,\n  q15_t * pCoeffs,\n  q15_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Processing function for the Q7 sparse FIR filter.\n   * @param[in]  S            points to an instance of the Q7 sparse FIR structure.\n   * @param[in]  pSrc         points to the block of input data.\n   * @param[out] pDst         points to the block of output data\n   * @param[in]  pScratchIn   points to a temporary buffer of size blockSize.\n   * @param[in]  pScratchOut  points to a temporary buffer of size blockSize.\n   * @param[in]  blockSize    number of input samples to process per call.\n   */\n  void arm_fir_sparse_q7(\n  arm_fir_sparse_instance_q7 * S,\n  q7_t * pSrc,\n  q7_t * pDst,\n  q7_t * pScratchIn,\n  q31_t * pScratchOut,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Initialization function for the Q7 sparse FIR filter.\n   * @param[in,out] S          points to an instance of the Q7 sparse FIR structure.\n   * @param[in]     numTaps    number of nonzero coefficients in the filter.\n   * @param[in]     pCoeffs    points to the array of filter coefficients.\n   * @param[in]     pState     points to the state buffer.\n   * @param[in]     pTapDelay  points to the array of offset times.\n   * @param[in]     maxDelay   maximum offset time supported.\n   * @param[in]     blockSize  number of samples that will be processed per block.\n   */\n  void arm_fir_sparse_init_q7(\n  arm_fir_sparse_instance_q7 * S,\n  uint16_t numTaps,\n  q7_t * pCoeffs,\n  q7_t * pState,\n  int32_t * pTapDelay,\n  uint16_t maxDelay,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Floating-point sin_cos function.\n   * @param[in]  theta   input value in degrees\n   * @param[out] pSinVal  points to the processed sine output.\n   * @param[out] pCosVal  points to the processed cos output.\n   */\n  void arm_sin_cos_f32(\n  float32_t theta,\n  float32_t * pSinVal,\n  float32_t * pCosVal);\n\n\n  /**\n   * @brief  Q31 sin_cos function.\n   * @param[in]  theta    scaled input value in degrees\n   * @param[out] pSinVal  points to the processed sine output.\n   * @param[out] pCosVal  points to the processed cosine output.\n   */\n  void arm_sin_cos_q31(\n  q31_t theta,\n  q31_t * pSinVal,\n  q31_t * pCosVal);\n\n\n  /**\n   * @brief  Floating-point complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n  /**\n   * @brief  Q31 complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex conjugate.\n   * @param[in]  pSrc        points to the input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_conj_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex magnitude squared\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_squared_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup PID PID Motor Control\n   *\n   * A Proportional Integral Derivative (PID) controller is a generic feedback control\n   * loop mechanism widely used in industrial control systems.\n   * A PID controller is the most commonly used type of feedback controller.\n   *\n   * This set of functions implements (PID) controllers\n   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample\n   * of data and each call to the function returns a single processed value.\n   * <code>S</code> points to an instance of the PID control data structure.  <code>in</code>\n   * is the input sample value. The functions return the output value.\n   *\n   * \\par Algorithm:\n   * <pre>\n   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]\n   *    A0 = Kp + Ki + Kd\n   *    A1 = (-Kp ) - (2 * Kd )\n   *    A2 = Kd  </pre>\n   *\n   * \\par\n   * where \\c Kp is proportional constant, \\c Ki is Integral constant and \\c Kd is Derivative constant\n   *\n   * \\par\n   * \\image html PID.gif \"Proportional Integral Derivative Controller\"\n   *\n   * \\par\n   * The PID controller calculates an \"error\" value as the difference between\n   * the measured output and the reference input.\n   * The controller attempts to minimize the error by adjusting the process control inputs.\n   * The proportional value determines the reaction to the current error,\n   * the integral value determines the reaction based on the sum of recent errors,\n   * and the derivative value determines the reaction based on the rate at which the error has been changing.\n   *\n   * \\par Instance Structure\n   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.\n   * A separate instance structure must be defined for each PID Controller.\n   * There are separate instance structure declarations for each of the 3 supported data types.\n   *\n   * \\par Reset Functions\n   * There is also an associated reset function for each data type which clears the state array.\n   *\n   * \\par Initialization Functions\n   * There is also an associated initialization function for each data type.\n   * The initialization function performs the following operations:\n   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.\n   * - Zeros out the values in the state buffer.\n   *\n   * \\par\n   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.\n   *\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the fixed-point versions of the PID Controller functions.\n   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup PID\n   * @{\n   */\n\n  /**\n   * @brief  Process function for the floating-point PID Control.\n   * @param[in,out] S   is an instance of the floating-point PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   */\n  CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32(\n  arm_pid_instance_f32 * S,\n  float32_t in)\n  {\n    float32_t out;\n\n    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */\n    out = (S->A0 * in) +\n      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n\n  }\n\n  /**\n   * @brief  Process function for the Q31 PID Control.\n   * @param[in,out] S  points to an instance of the Q31 PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 64-bit accumulator.\n   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.\n   * Thus, if the accumulator result overflows it wraps around rather than clip.\n   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.\n   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.\n   */\n  CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31(\n  arm_pid_instance_q31 * S,\n  q31_t in)\n  {\n    q63_t acc;\n    q31_t out;\n\n    /* acc = A0 * x[n]  */\n    acc = (q63_t) S->A0 * in;\n\n    /* acc += A1 * x[n-1] */\n    acc += (q63_t) S->A1 * S->state[0];\n\n    /* acc += A2 * x[n-2]  */\n    acc += (q63_t) S->A2 * S->state[1];\n\n    /* convert output to 1.31 format to add y[n-1] */\n    out = (q31_t) (acc >> 31U);\n\n    /* out += y[n-1] */\n    out += S->state[2];\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n  }\n\n\n  /**\n   * @brief  Process function for the Q15 PID Control.\n   * @param[in,out] S   points to an instance of the Q15 PID Control structure\n   * @param[in]     in  input sample to process\n   * @return out processed output sample.\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using a 64-bit internal accumulator.\n   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.\n   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.\n   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.\n   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.\n   * Lastly, the accumulator is saturated to yield a result in 1.15 format.\n   */\n  CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15(\n  arm_pid_instance_q15 * S,\n  q15_t in)\n  {\n    q63_t acc;\n    q15_t out;\n\n#if defined (ARM_MATH_DSP)\n    __SIMD32_TYPE *vstate;\n\n    /* Implementation of PID controller */\n\n    /* acc = A0 * x[n]  */\n    acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);\n\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\n    vstate = __SIMD32_CONST(S->state);\n    acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc);\n#else\n    /* acc = A0 * x[n]  */\n    acc = ((q31_t) S->A0) * in;\n\n    /* acc += A1 * x[n-1] + A2 * x[n-2]  */\n    acc += (q31_t) S->A1 * S->state[0];\n    acc += (q31_t) S->A2 * S->state[1];\n#endif\n\n    /* acc += y[n-1] */\n    acc += (q31_t) S->state[2] << 15;\n\n    /* saturate the output */\n    out = (q15_t) (__SSAT((acc >> 15), 16));\n\n    /* Update state */\n    S->state[1] = S->state[0];\n    S->state[0] = in;\n    S->state[2] = out;\n\n    /* return to application */\n    return (out);\n  }\n\n  /**\n   * @} end of PID group\n   */\n\n\n  /**\n   * @brief Floating-point matrix inverse.\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\n   */\n  arm_status arm_mat_inverse_f32(\n  const arm_matrix_instance_f32 * src,\n  arm_matrix_instance_f32 * dst);\n\n\n  /**\n   * @brief Floating-point matrix inverse.\n   * @param[in]  src   points to the instance of the input floating-point matrix structure.\n   * @param[out] dst   points to the instance of the output floating-point matrix structure.\n   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.\n   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.\n   */\n  arm_status arm_mat_inverse_f64(\n  const arm_matrix_instance_f64 * src,\n  arm_matrix_instance_f64 * dst);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup clarke Vector Clarke Transform\n   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.\n   * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents\n   * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.\n   * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below\n   * \\image html clarke.gif Stator current space vector and its components in (a,b).\n   * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>\n   * can be calculated using only <code>Ia</code> and <code>Ib</code>.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html clarkeFormula.gif\n   * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and\n   * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Clarke transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup clarke\n   * @{\n   */\n\n  /**\n   *\n   * @brief  Floating-point Clarke transform\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32(\n  float32_t Ia,\n  float32_t Ib,\n  float32_t * pIalpha,\n  float32_t * pIbeta)\n  {\n    /* Calculate pIalpha using the equation, pIalpha = Ia */\n    *pIalpha = Ia;\n\n    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */\n    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);\n  }\n\n\n  /**\n   * @brief  Clarke transform for Q31 version\n   * @param[in]  Ia       input three-phase coordinate <code>a</code>\n   * @param[in]  Ib       input three-phase coordinate <code>b</code>\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition, hence there is no risk of overflow.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31(\n  q31_t Ia,\n  q31_t Ib,\n  q31_t * pIalpha,\n  q31_t * pIbeta)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n\n    /* Calculating pIalpha from Ia by equation pIalpha = Ia */\n    *pIalpha = Ia;\n\n    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */\n    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);\n\n    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */\n    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);\n\n    /* pIbeta is calculated by adding the intermediate products */\n    *pIbeta = __QADD(product1, product2);\n  }\n\n  /**\n   * @} end of clarke group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to Q31 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_q7_to_q31(\n  q7_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup inv_clarke Vector Inverse Clarke Transform\n   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html clarkeInvFormula.gif\n   * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and\n   * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Clarke transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup inv_clarke\n   * @{\n   */\n\n   /**\n   * @brief  Floating-point Inverse Clarke transform\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32(\n  float32_t Ialpha,\n  float32_t Ibeta,\n  float32_t * pIa,\n  float32_t * pIb)\n  {\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\n    *pIa = Ialpha;\n\n    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */\n    *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;\n  }\n\n\n  /**\n   * @brief  Inverse Clarke transform for Q31 version\n   * @param[in]  Ialpha  input two-phase orthogonal vector axis alpha\n   * @param[in]  Ibeta   input two-phase orthogonal vector axis beta\n   * @param[out] pIa     points to output three-phase coordinate <code>a</code>\n   * @param[out] pIb     points to output three-phase coordinate <code>b</code>\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the subtraction, hence there is no risk of overflow.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31(\n  q31_t Ialpha,\n  q31_t Ibeta,\n  q31_t * pIa,\n  q31_t * pIb)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n\n    /* Calculating pIa from Ialpha by equation pIa = Ialpha */\n    *pIa = Ialpha;\n\n    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */\n    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);\n\n    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */\n    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);\n\n    /* pIb is calculated by subtracting the products */\n    *pIb = __QSUB(product2, product1);\n  }\n\n  /**\n   * @} end of inv_clarke group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to Q15 vector.\n   * @param[in]  pSrc       input pointer\n   * @param[out] pDst       output pointer\n   * @param[in]  blockSize  number of samples to process\n   */\n  void arm_q7_to_q15(\n  q7_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup park Vector Park Transform\n   *\n   * Forward Park transform converts the input two-coordinate vector to flux and torque components.\n   * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents\n   * from the stationary to the moving reference frame and control the spatial relationship between\n   * the stator vector current and rotor flux vector.\n   * If we consider the d axis aligned with the rotor flux, the diagram below shows the\n   * current vector and the relationship from the two reference frames:\n   * \\image html park.gif \"Stator current space vector and its component in (a,b) and in the d,q rotating reference frame\"\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html parkFormula.gif\n   * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,\n   * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\n   * cosine and sine values of theta (rotor flux position).\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Park transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup park\n   * @{\n   */\n\n  /**\n   * @brief Floating-point Park transform\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\n   * @param[out] pId     points to output   rotor reference frame d\n   * @param[out] pIq     points to output   rotor reference frame q\n   * @param[in]  sinVal  sine value of rotation angle theta\n   * @param[in]  cosVal  cosine value of rotation angle theta\n   *\n   * The function implements the forward Park transform.\n   *\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_park_f32(\n  float32_t Ialpha,\n  float32_t Ibeta,\n  float32_t * pId,\n  float32_t * pIq,\n  float32_t sinVal,\n  float32_t cosVal)\n  {\n    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */\n    *pId = Ialpha * cosVal + Ibeta * sinVal;\n\n    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */\n    *pIq = -Ialpha * sinVal + Ibeta * cosVal;\n  }\n\n\n  /**\n   * @brief  Park transform for Q31 version\n   * @param[in]  Ialpha  input two-phase vector coordinate alpha\n   * @param[in]  Ibeta   input two-phase vector coordinate beta\n   * @param[out] pId     points to output rotor reference frame d\n   * @param[out] pIq     points to output rotor reference frame q\n   * @param[in]  sinVal  sine value of rotation angle theta\n   * @param[in]  cosVal  cosine value of rotation angle theta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition and subtraction, hence there is no risk of overflow.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_park_q31(\n  q31_t Ialpha,\n  q31_t Ibeta,\n  q31_t * pId,\n  q31_t * pIq,\n  q31_t sinVal,\n  q31_t cosVal)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\n\n    /* Intermediate product is calculated by (Ialpha * cosVal) */\n    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);\n\n    /* Intermediate product is calculated by (Ibeta * sinVal) */\n    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);\n\n\n    /* Intermediate product is calculated by (Ialpha * sinVal) */\n    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);\n\n    /* Intermediate product is calculated by (Ibeta * cosVal) */\n    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);\n\n    /* Calculate pId by adding the two intermediate products 1 and 2 */\n    *pId = __QADD(product1, product2);\n\n    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */\n    *pIq = __QSUB(product4, product3);\n  }\n\n  /**\n   * @} end of park group\n   */\n\n  /**\n   * @brief  Converts the elements of the Q7 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q7_to_float(\n  q7_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @ingroup groupController\n   */\n\n  /**\n   * @defgroup inv_park Vector Inverse Park transform\n   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.\n   *\n   * The function operates on a single sample of data and each call to the function returns the processed output.\n   * The library provides separate functions for Q31 and floating-point data types.\n   * \\par Algorithm\n   * \\image html parkInvFormula.gif\n   * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,\n   * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the\n   * cosine and sine values of theta (rotor flux position).\n   * \\par Fixed-Point Behavior\n   * Care must be taken when using the Q31 version of the Park transform.\n   * In particular, the overflow and saturation behavior of the accumulator used must be considered.\n   * Refer to the function specific documentation below for usage guidelines.\n   */\n\n  /**\n   * @addtogroup inv_park\n   * @{\n   */\n\n   /**\n   * @brief  Floating-point Inverse Park transform\n   * @param[in]  Id       input coordinate of rotor reference frame d\n   * @param[in]  Iq       input coordinate of rotor reference frame q\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   * @param[in]  sinVal   sine value of rotation angle theta\n   * @param[in]  cosVal   cosine value of rotation angle theta\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32(\n  float32_t Id,\n  float32_t Iq,\n  float32_t * pIalpha,\n  float32_t * pIbeta,\n  float32_t sinVal,\n  float32_t cosVal)\n  {\n    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */\n    *pIalpha = Id * cosVal - Iq * sinVal;\n\n    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */\n    *pIbeta = Id * sinVal + Iq * cosVal;\n  }\n\n\n  /**\n   * @brief  Inverse Park transform for   Q31 version\n   * @param[in]  Id       input coordinate of rotor reference frame d\n   * @param[in]  Iq       input coordinate of rotor reference frame q\n   * @param[out] pIalpha  points to output two-phase orthogonal vector axis alpha\n   * @param[out] pIbeta   points to output two-phase orthogonal vector axis beta\n   * @param[in]  sinVal   sine value of rotation angle theta\n   * @param[in]  cosVal   cosine value of rotation angle theta\n   *\n   * <b>Scaling and Overflow Behavior:</b>\n   * \\par\n   * The function is implemented using an internal 32-bit accumulator.\n   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.\n   * There is saturation on the addition, hence there is no risk of overflow.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31(\n  q31_t Id,\n  q31_t Iq,\n  q31_t * pIalpha,\n  q31_t * pIbeta,\n  q31_t sinVal,\n  q31_t cosVal)\n  {\n    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */\n    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */\n\n    /* Intermediate product is calculated by (Id * cosVal) */\n    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);\n\n    /* Intermediate product is calculated by (Iq * sinVal) */\n    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);\n\n\n    /* Intermediate product is calculated by (Id * sinVal) */\n    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);\n\n    /* Intermediate product is calculated by (Iq * cosVal) */\n    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);\n\n    /* Calculate pIalpha by using the two intermediate products 1 and 2 */\n    *pIalpha = __QSUB(product1, product2);\n\n    /* Calculate pIbeta by using the two intermediate products 3 and 4 */\n    *pIbeta = __QADD(product4, product3);\n  }\n\n  /**\n   * @} end of Inverse park group\n   */\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_float(\n  q31_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n  /**\n   * @ingroup groupInterpolation\n   */\n\n  /**\n   * @defgroup LinearInterpolate Linear Interpolation\n   *\n   * Linear interpolation is a method of curve fitting using linear polynomials.\n   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line\n   *\n   * \\par\n   * \\image html LinearInterp.gif \"Linear interpolation\"\n   *\n   * \\par\n   * A  Linear Interpolate function calculates an output value(y), for the input(x)\n   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)\n   *\n   * \\par Algorithm:\n   * <pre>\n   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))\n   *       where x0, x1 are nearest values of input x\n   *             y0, y1 are nearest values to output y\n   * </pre>\n   *\n   * \\par\n   * This set of functions implements Linear interpolation process\n   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single\n   * sample of data and each call to the function returns a single processed value.\n   * <code>S</code> points to an instance of the Linear Interpolate function data structure.\n   * <code>x</code> is the input sample value. The functions returns the output value.\n   *\n   * \\par\n   * if x is outside of the table boundary, Linear interpolation returns first value of the table\n   * if x is below input range and returns last value of table if x is above range.\n   */\n\n  /**\n   * @addtogroup LinearInterpolate\n   * @{\n   */\n\n  /**\n   * @brief  Process function for the floating-point Linear Interpolation Function.\n   * @param[in,out] S  is an instance of the floating-point Linear Interpolation structure\n   * @param[in]     x  input sample to process\n   * @return y processed output sample.\n   *\n   */\n  CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32(\n  arm_linear_interp_instance_f32 * S,\n  float32_t x)\n  {\n    float32_t y;\n    float32_t x0, x1;                            /* Nearest input values */\n    float32_t y0, y1;                            /* Nearest output values */\n    float32_t xSpacing = S->xSpacing;            /* spacing between input values */\n    int32_t i;                                   /* Index variable */\n    float32_t *pYData = S->pYData;               /* pointer to output table */\n\n    /* Calculation of index */\n    i = (int32_t) ((x - S->x1) / xSpacing);\n\n    if (i < 0)\n    {\n      /* Iniatilize output for below specified range as least output value of table */\n      y = pYData[0];\n    }\n    else if ((uint32_t)i >= S->nValues)\n    {\n      /* Iniatilize output for above specified range as last output value of table */\n      y = pYData[S->nValues - 1];\n    }\n    else\n    {\n      /* Calculation of nearest input values */\n      x0 = S->x1 +  i      * xSpacing;\n      x1 = S->x1 + (i + 1) * xSpacing;\n\n      /* Read of nearest output values */\n      y0 = pYData[i];\n      y1 = pYData[i + 1];\n\n      /* Calculation of output */\n      y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));\n\n    }\n\n    /* returns output value */\n    return (y);\n  }\n\n\n   /**\n   *\n   * @brief  Process function for the Q31 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q31 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   *\n   */\n  CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31(\n  q31_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q31_t y;                                     /* output */\n    q31_t y0, y1;                                /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    int32_t index;                               /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    index = ((x & (q31_t)0xFFF00000) >> 20);\n\n    if (index >= (int32_t)(nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else if (index < 0)\n    {\n      return (pYData[0]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* shift left by 11 to keep fract in 1.31 format */\n      fract = (x & 0x000FFFFF) << 11;\n\n      /* Read two nearest output values from the index in 1.31(q31) format */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract) and y is in 2.30 format */\n      y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));\n\n      /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */\n      y += ((q31_t) (((q63_t) y1 * fract) >> 32));\n\n      /* Convert y to 1.31 format */\n      return (y << 1U);\n    }\n  }\n\n\n  /**\n   *\n   * @brief  Process function for the Q15 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q15 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   *\n   */\n  CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15(\n  q15_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q63_t y;                                     /* output */\n    q15_t y0, y1;                                /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    int32_t index;                               /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    index = ((x & (int32_t)0xFFF00000) >> 20);\n\n    if (index >= (int32_t)(nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else if (index < 0)\n    {\n      return (pYData[0]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* fract is in 12.20 format */\n      fract = (x & 0x000FFFFF);\n\n      /* Read two nearest output values from the index */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract) and y is in 13.35 format */\n      y = ((q63_t) y0 * (0xFFFFF - fract));\n\n      /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */\n      y += ((q63_t) y1 * (fract));\n\n      /* convert y to 1.15 format */\n      return (q15_t) (y >> 20);\n    }\n  }\n\n\n  /**\n   *\n   * @brief  Process function for the Q7 Linear Interpolation Function.\n   * @param[in] pYData   pointer to Q7 Linear Interpolation table\n   * @param[in] x        input sample to process\n   * @param[in] nValues  number of table values\n   * @return y processed output sample.\n   *\n   * \\par\n   * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.\n   * This function can support maximum of table size 2^12.\n   */\n  CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7(\n  q7_t * pYData,\n  q31_t x,\n  uint32_t nValues)\n  {\n    q31_t y;                                     /* output */\n    q7_t y0, y1;                                 /* Nearest output values */\n    q31_t fract;                                 /* fractional part */\n    uint32_t index;                              /* Index to read nearest output values */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    if (x < 0)\n    {\n      return (pYData[0]);\n    }\n    index = (x >> 20) & 0xfff;\n\n    if (index >= (nValues - 1))\n    {\n      return (pYData[nValues - 1]);\n    }\n    else\n    {\n      /* 20 bits for the fractional part */\n      /* fract is in 12.20 format */\n      fract = (x & 0x000FFFFF);\n\n      /* Read two nearest output values from the index and are in 1.7(q7) format */\n      y0 = pYData[index];\n      y1 = pYData[index + 1];\n\n      /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */\n      y = ((y0 * (0xFFFFF - fract)));\n\n      /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */\n      y += (y1 * fract);\n\n      /* convert y to 1.7(q7) format */\n      return (q7_t) (y >> 20);\n     }\n  }\n\n  /**\n   * @} end of LinearInterpolate group\n   */\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for floating-point data.\n   * @param[in] x  input value in radians.\n   * @return  sin(x).\n   */\n  float32_t arm_sin_f32(\n  float32_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for Q31 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  sin(x).\n   */\n  q31_t arm_sin_q31(\n  q31_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric sine function for Q15 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  sin(x).\n   */\n  q15_t arm_sin_q15(\n  q15_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.\n   * @param[in] x  input value in radians.\n   * @return  cos(x).\n   */\n  float32_t arm_cos_f32(\n  float32_t x);\n\n\n  /**\n   * @brief Fast approximation to the trigonometric cosine function for Q31 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  cos(x).\n   */\n  q31_t arm_cos_q31(\n  q31_t x);\n\n\n  /**\n   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.\n   * @param[in] x  Scaled input value in radians.\n   * @return  cos(x).\n   */\n  q15_t arm_cos_q15(\n  q15_t x);\n\n\n  /**\n   * @ingroup groupFastMath\n   */\n\n\n  /**\n   * @defgroup SQRT Square Root\n   *\n   * Computes the square root of a number.\n   * There are separate functions for Q15, Q31, and floating-point data types.\n   * The square root function is computed using the Newton-Raphson algorithm.\n   * This is an iterative algorithm of the form:\n   * <pre>\n   *      x1 = x0 - f(x0)/f'(x0)\n   * </pre>\n   * where <code>x1</code> is the current estimate,\n   * <code>x0</code> is the previous estimate, and\n   * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.\n   * For the square root function, the algorithm reduces to:\n   * <pre>\n   *     x0 = in/2                         [initial guess]\n   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]\n   * </pre>\n   */\n\n\n  /**\n   * @addtogroup SQRT\n   * @{\n   */\n\n  /**\n   * @brief  Floating-point square root function.\n   * @param[in]  in    input value.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32(\n  float32_t in,\n  float32_t * pOut)\n  {\n    if (in >= 0.0f)\n    {\n\n#if   (__FPU_USED == 1) && defined ( __CC_ARM   )\n      *pOut = __sqrtf(in);\n#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n      *pOut = __builtin_sqrtf(in);\n#elif (__FPU_USED == 1) && defined(__GNUC__)\n      *pOut = __builtin_sqrtf(in);\n#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000)\n      __ASM(\"VSQRT.F32 %0,%1\" : \"=t\"(*pOut) : \"t\"(in));\n#else\n      *pOut = sqrtf(in);\n#endif\n\n      return (ARM_MATH_SUCCESS);\n    }\n    else\n    {\n      *pOut = 0.0f;\n      return (ARM_MATH_ARGUMENT_ERROR);\n    }\n  }\n\n\n  /**\n   * @brief Q31 square root function.\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  arm_status arm_sqrt_q31(\n  q31_t in,\n  q31_t * pOut);\n\n\n  /**\n   * @brief  Q15 square root function.\n   * @param[in]  in    input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.\n   * @param[out] pOut  square root of input value.\n   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if\n   * <code>in</code> is negative value and returns zero output for negative values.\n   */\n  arm_status arm_sqrt_q15(\n  q15_t in,\n  q15_t * pOut);\n\n  /**\n   * @} end of SQRT group\n   */\n\n\n  /**\n   * @brief floating-point Circular write function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32(\n  int32_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const int32_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0U;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if (wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n\n  /**\n   * @brief floating-point Circular Read function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32(\n  int32_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  int32_t * dst,\n  int32_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0U;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if (dst == (int32_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update rOffset.  Watch out for positive and negative value  */\n      rOffset += bufferInc;\n\n      if (rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief Q15 Circular write function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15(\n  q15_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const q15_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0U;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if (wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n  /**\n   * @brief Q15 Circular Read function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15(\n  q15_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  q15_t * dst,\n  q15_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if (dst == (q15_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      rOffset += bufferInc;\n\n      if (rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief Q7 Circular write function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7(\n  q7_t * circBuffer,\n  int32_t L,\n  uint16_t * writeOffset,\n  int32_t bufferInc,\n  const q7_t * src,\n  int32_t srcInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0U;\n    int32_t wOffset;\n\n    /* Copy the value of Index pointer that points\n     * to the current location where the input samples to be copied */\n    wOffset = *writeOffset;\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the input sample to the circular buffer */\n      circBuffer[wOffset] = *src;\n\n      /* Update the input pointer */\n      src += srcInc;\n\n      /* Circularly update wOffset.  Watch out for positive and negative value */\n      wOffset += bufferInc;\n      if (wOffset >= L)\n        wOffset -= L;\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *writeOffset = (uint16_t)wOffset;\n  }\n\n\n  /**\n   * @brief Q7 Circular Read function.\n   */\n  CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7(\n  q7_t * circBuffer,\n  int32_t L,\n  int32_t * readOffset,\n  int32_t bufferInc,\n  q7_t * dst,\n  q7_t * dst_base,\n  int32_t dst_length,\n  int32_t dstInc,\n  uint32_t blockSize)\n  {\n    uint32_t i = 0;\n    int32_t rOffset, dst_end;\n\n    /* Copy the value of Index pointer that points\n     * to the current location from where the input samples to be read */\n    rOffset = *readOffset;\n\n    dst_end = (int32_t) (dst_base + dst_length);\n\n    /* Loop over the blockSize */\n    i = blockSize;\n\n    while (i > 0U)\n    {\n      /* copy the sample from the circular buffer to the destination buffer */\n      *dst = circBuffer[rOffset];\n\n      /* Update the input pointer */\n      dst += dstInc;\n\n      if (dst == (q7_t *) dst_end)\n      {\n        dst = dst_base;\n      }\n\n      /* Circularly update rOffset.  Watch out for positive and negative value */\n      rOffset += bufferInc;\n\n      if (rOffset >= L)\n      {\n        rOffset -= L;\n      }\n\n      /* Decrement the loop counter */\n      i--;\n    }\n\n    /* Update the index pointer */\n    *readOffset = rOffset;\n  }\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q63_t * pResult);\n\n\n  /**\n   * @brief  Sum of the squares of the elements of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_power_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Mean value of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_mean_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Variance of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_var_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Root Mean Square of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_rms_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult);\n\n\n  /**\n   * @brief  Standard deviation of the elements of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output value.\n   */\n  void arm_std_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult);\n\n\n  /**\n   * @brief  Floating-point complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_f32(\n  float32_t * pSrc,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_q31(\n  q31_t * pSrc,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex magnitude\n   * @param[in]  pSrc        points to the complex input vector\n   * @param[out] pDst        points to the real output vector\n   * @param[in]  numSamples  number of complex samples in the input vector\n   */\n  void arm_cmplx_mag_q15(\n  q15_t * pSrc,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q15 complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  uint32_t numSamples,\n  q31_t * realResult,\n  q31_t * imagResult);\n\n\n  /**\n   * @brief  Q31 complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  uint32_t numSamples,\n  q63_t * realResult,\n  q63_t * imagResult);\n\n\n  /**\n   * @brief  Floating-point complex dot product\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   * @param[out] realResult  real part of the result returned here\n   * @param[out] imagResult  imaginary part of the result returned here\n   */\n  void arm_cmplx_dot_prod_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  uint32_t numSamples,\n  float32_t * realResult,\n  float32_t * imagResult);\n\n\n  /**\n   * @brief  Q15 complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_q15(\n  q15_t * pSrcCmplx,\n  q15_t * pSrcReal,\n  q15_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_q31(\n  q31_t * pSrcCmplx,\n  q31_t * pSrcReal,\n  q31_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex-by-real multiplication\n   * @param[in]  pSrcCmplx   points to the complex input vector\n   * @param[in]  pSrcReal    points to the real input vector\n   * @param[out] pCmplxDst   points to the complex output vector\n   * @param[in]  numSamples  number of samples in each vector\n   */\n  void arm_cmplx_mult_real_f32(\n  float32_t * pSrcCmplx,\n  float32_t * pSrcReal,\n  float32_t * pCmplxDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Minimum value of a Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] result     is output pointer\n   * @param[in]  index      is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * result,\n  uint32_t * index);\n\n\n  /**\n   * @brief  Minimum value of a Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[in]  pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Minimum value of a Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Minimum value of a floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[in]  blockSize  is the number of samples to process\n   * @param[out] pResult    is output pointer\n   * @param[out] pIndex     is the array index of the minimum value in the input buffer.\n   */\n  void arm_min_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q7 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q7(\n  q7_t * pSrc,\n  uint32_t blockSize,\n  q7_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q15 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q15(\n  q15_t * pSrc,\n  uint32_t blockSize,\n  q15_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a Q31 vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_q31(\n  q31_t * pSrc,\n  uint32_t blockSize,\n  q31_t * pResult,\n  uint32_t * pIndex);\n\n\n/**\n * @brief Maximum value of a floating-point vector.\n * @param[in]  pSrc       points to the input buffer\n * @param[in]  blockSize  length of the input vector\n * @param[out] pResult    maximum value returned here\n * @param[out] pIndex     index of maximum value returned here\n */\n  void arm_max_f32(\n  float32_t * pSrc,\n  uint32_t blockSize,\n  float32_t * pResult,\n  uint32_t * pIndex);\n\n\n  /**\n   * @brief  Q15 complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_q15(\n  q15_t * pSrcA,\n  q15_t * pSrcB,\n  q15_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Q31 complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_q31(\n  q31_t * pSrcA,\n  q31_t * pSrcB,\n  q31_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief  Floating-point complex-by-complex multiplication\n   * @param[in]  pSrcA       points to the first input vector\n   * @param[in]  pSrcB       points to the second input vector\n   * @param[out] pDst        points to the output vector\n   * @param[in]  numSamples  number of complex samples in each vector\n   */\n  void arm_cmplx_mult_cmplx_f32(\n  float32_t * pSrcA,\n  float32_t * pSrcB,\n  float32_t * pDst,\n  uint32_t numSamples);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q31 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q31 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q31(\n  float32_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q15 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q15 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q15(\n  float32_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief Converts the elements of the floating-point vector to Q7 vector.\n   * @param[in]  pSrc       points to the floating-point input vector\n   * @param[out] pDst       points to the Q7 output vector\n   * @param[in]  blockSize  length of the input vector\n   */\n  void arm_float_to_q7(\n  float32_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to Q15 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_q15(\n  q31_t * pSrc,\n  q15_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q31 vector to Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q31_to_q7(\n  q31_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to floating-point vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_float(\n  q15_t * pSrc,\n  float32_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to Q31 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_q31(\n  q15_t * pSrc,\n  q31_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @brief  Converts the elements of the Q15 vector to Q7 vector.\n   * @param[in]  pSrc       is input pointer\n   * @param[out] pDst       is output pointer\n   * @param[in]  blockSize  is the number of samples to process\n   */\n  void arm_q15_to_q7(\n  q15_t * pSrc,\n  q7_t * pDst,\n  uint32_t blockSize);\n\n\n  /**\n   * @ingroup groupInterpolation\n   */\n\n  /**\n   * @defgroup BilinearInterpolate Bilinear Interpolation\n   *\n   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.\n   * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process\n   * determines values between the grid points.\n   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.\n   * Bilinear interpolation is often used in image processing to rescale images.\n   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.\n   *\n   * <b>Algorithm</b>\n   * \\par\n   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.\n   * For floating-point, the instance structure is defined as:\n   * <pre>\n   *   typedef struct\n   *   {\n   *     uint16_t numRows;\n   *     uint16_t numCols;\n   *     float32_t *pData;\n   * } arm_bilinear_interp_instance_f32;\n   * </pre>\n   *\n   * \\par\n   * where <code>numRows</code> specifies the number of rows in the table;\n   * <code>numCols</code> specifies the number of columns in the table;\n   * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.\n   * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.\n   * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.\n   *\n   * \\par\n   * Let <code>(x, y)</code> specify the desired interpolation point.  Then define:\n   * <pre>\n   *     XF = floor(x)\n   *     YF = floor(y)\n   * </pre>\n   * \\par\n   * The interpolated output point is computed as:\n   * <pre>\n   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))\n   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))\n   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)\n   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)\n   * </pre>\n   * Note that the coordinates (x, y) contain integer and fractional components.\n   * The integer components specify which portion of the table to use while the\n   * fractional components control the interpolation processor.\n   *\n   * \\par\n   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.\n   */\n\n  /**\n   * @addtogroup BilinearInterpolate\n   * @{\n   */\n\n\n  /**\n  *\n  * @brief  Floating-point bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate.\n  * @param[in]     Y  interpolation coordinate.\n  * @return out interpolated value.\n  */\n  CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32(\n  const arm_bilinear_interp_instance_f32 * S,\n  float32_t X,\n  float32_t Y)\n  {\n    float32_t out;\n    float32_t f00, f01, f10, f11;\n    float32_t *pData = S->pData;\n    int32_t xIndex, yIndex, index;\n    float32_t xdiff, ydiff;\n    float32_t b1, b2, b3, b4;\n\n    xIndex = (int32_t) X;\n    yIndex = (int32_t) Y;\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* Calculation of index for two nearest points in X-direction */\n    index = (xIndex - 1) + (yIndex - 1) * S->numCols;\n\n\n    /* Read two nearest points in X-direction */\n    f00 = pData[index];\n    f01 = pData[index + 1];\n\n    /* Calculation of index for two nearest points in Y-direction */\n    index = (xIndex - 1) + (yIndex) * S->numCols;\n\n\n    /* Read two nearest points in Y-direction */\n    f10 = pData[index];\n    f11 = pData[index + 1];\n\n    /* Calculation of intermediate values */\n    b1 = f00;\n    b2 = f01 - f00;\n    b3 = f10 - f00;\n    b4 = f00 - f01 - f10 + f11;\n\n    /* Calculation of fractional part in X */\n    xdiff = X - xIndex;\n\n    /* Calculation of fractional part in Y */\n    ydiff = Y - yIndex;\n\n    /* Calculation of bi-linear interpolated output */\n    out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;\n\n    /* return to application */\n    return (out);\n  }\n\n\n  /**\n  *\n  * @brief  Q31 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31(\n  arm_bilinear_interp_instance_q31 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q31_t out;                                   /* Temporary output */\n    q31_t acc = 0;                               /* output */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    q31_t x1, x2, y1, y2;                        /* Nearest output values */\n    int32_t rI, cI;                              /* Row and column indices */\n    q31_t *pYData = S->pData;                    /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* shift left xfract by 11 to keep 1.31 format */\n    xfract = (X & 0x000FFFFF) << 11U;\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[(rI) + (int32_t)nCols * (cI)    ];\n    x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* shift left yfract by 11 to keep 1.31 format */\n    yfract = (Y & 0x000FFFFF) << 11U;\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[(rI) + (int32_t)nCols * (cI + 1)    ];\n    y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */\n    out = ((q31_t) (((q63_t) x1  * (0x7FFFFFFF - xfract)) >> 32));\n    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));\n\n    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));\n\n    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\n\n    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */\n    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));\n    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));\n\n    /* Convert acc to 1.31(q31) format */\n    return ((q31_t)(acc << 2));\n  }\n\n\n  /**\n  * @brief  Q15 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15(\n  arm_bilinear_interp_instance_q15 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q63_t acc = 0;                               /* output */\n    q31_t out;                                   /* Temporary output */\n    q15_t x1, x2, y1, y2;                        /* Nearest output values */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    int32_t rI, cI;                              /* Row and column indices */\n    q15_t *pYData = S->pData;                    /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* xfract should be in 12.20 format */\n    xfract = (X & 0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* yfract should be in 12.20 format */\n    yfract = (Y & 0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */\n\n    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */\n    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */\n    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U);\n    acc = ((q63_t) out * (0xFFFFF - yfract));\n\n    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U);\n    acc += ((q63_t) out * (xfract));\n\n    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U);\n    acc += ((q63_t) out * (yfract));\n\n    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */\n    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U);\n    acc += ((q63_t) out * (yfract));\n\n    /* acc is in 13.51 format and down shift acc by 36 times */\n    /* Convert out to 1.15 format */\n    return ((q15_t)(acc >> 36));\n  }\n\n\n  /**\n  * @brief  Q7 bilinear interpolation.\n  * @param[in,out] S  points to an instance of the interpolation structure.\n  * @param[in]     X  interpolation coordinate in 12.20 format.\n  * @param[in]     Y  interpolation coordinate in 12.20 format.\n  * @return out interpolated value.\n  */\n  CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7(\n  arm_bilinear_interp_instance_q7 * S,\n  q31_t X,\n  q31_t Y)\n  {\n    q63_t acc = 0;                               /* output */\n    q31_t out;                                   /* Temporary output */\n    q31_t xfract, yfract;                        /* X, Y fractional parts */\n    q7_t x1, x2, y1, y2;                         /* Nearest output values */\n    int32_t rI, cI;                              /* Row and column indices */\n    q7_t *pYData = S->pData;                     /* pointer to output table values */\n    uint32_t nCols = S->numCols;                 /* num of rows */\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    rI = ((X & (q31_t)0xFFF00000) >> 20);\n\n    /* Input is in 12.20 format */\n    /* 12 bits for the table index */\n    /* Index value calculation */\n    cI = ((Y & (q31_t)0xFFF00000) >> 20);\n\n    /* Care taken for table outside boundary */\n    /* Returns zero output when values are outside table boundary */\n    if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))\n    {\n      return (0);\n    }\n\n    /* 20 bits for the fractional part */\n    /* xfract should be in 12.20 format */\n    xfract = (X & (q31_t)0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI)    ];\n    x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1];\n\n    /* 20 bits for the fractional part */\n    /* yfract should be in 12.20 format */\n    yfract = (Y & (q31_t)0x000FFFFF);\n\n    /* Read two nearest output values from the index */\n    y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1)    ];\n    y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1];\n\n    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */\n    out = ((x1 * (0xFFFFF - xfract)));\n    acc = (((q63_t) out * (0xFFFFF - yfract)));\n\n    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */\n    out = ((x2 * (0xFFFFF - yfract)));\n    acc += (((q63_t) out * (xfract)));\n\n    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */\n    out = ((y1 * (0xFFFFF - xfract)));\n    acc += (((q63_t) out * (yfract)));\n\n    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */\n    out = ((y2 * (yfract)));\n    acc += (((q63_t) out * (xfract)));\n\n    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */\n    return ((q7_t)(acc >> 40));\n  }\n\n  /**\n   * @} end of BilinearInterpolate group\n   */\n\n\n/* SMMLAR */\n#define multAcc_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)\n\n/* SMMLSR */\n#define multSub_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)\n\n/* SMMULR */\n#define mult_32x32_keep32_R(a, x, y) \\\n    a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)\n\n/* SMMLA */\n#define multAcc_32x32_keep32(a, x, y) \\\n    a += (q31_t) (((q63_t) x * y) >> 32)\n\n/* SMMLS */\n#define multSub_32x32_keep32(a, x, y) \\\n    a -= (q31_t) (((q63_t) x * y) >> 32)\n\n/* SMMUL */\n#define mult_32x32_keep32(a, x, y) \\\n    a = (q31_t) (((q63_t) x * y ) >> 32)\n\n\n#if   defined ( __CC_ARM )\n  /* Enter low optimization region - place directly above function definition */\n  #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7)\n    #define LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"push\")         \\\n       _Pragma (\"O1\")\n  #else\n    #define LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\n    #define LOW_OPTIMIZATION_EXIT \\\n       _Pragma (\"pop\")\n  #else\n    #define LOW_OPTIMIZATION_EXIT\n  #endif\n\n  /* Enter low optimization region - place directly above function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined ( __GNUC__ )\n  #define LOW_OPTIMIZATION_ENTER \\\n       __attribute__(( optimize(\"-O1\") ))\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined ( __ICCARM__ )\n  /* Enter low optimization region - place directly above function definition */\n  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\n    #define LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"optimize=low\")\n  #else\n    #define LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define LOW_OPTIMIZATION_EXIT\n\n  /* Enter low optimization region - place directly above function definition */\n  #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 )\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \\\n       _Pragma (\"optimize=low\")\n  #else\n    #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #endif\n\n  /* Exit low optimization region - place directly after end of function definition */\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined ( __TI_ARM__ )\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined ( __CSMC__ )\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#elif defined ( __TASKING__ )\n  #define LOW_OPTIMIZATION_ENTER\n  #define LOW_OPTIMIZATION_EXIT\n  #define IAR_ONLY_LOW_OPTIMIZATION_ENTER\n  #define IAR_ONLY_LOW_OPTIMIZATION_EXIT\n\n#endif\n\n\n#ifdef   __cplusplus\n}\n#endif\n\n/* Compiler specific diagnostic adjustment */\n#if   defined ( __CC_ARM )\n\n#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )\n\n#elif defined ( __GNUC__ )\n#pragma GCC diagnostic pop\n\n#elif defined ( __ICCARM__ )\n\n#elif defined ( __TI_ARM__ )\n\n#elif defined ( __CSMC__ )\n\n#elif defined ( __TASKING__ )\n\n#else\n  #error Unknown compiler\n#endif\n\n#endif /* _ARM_MATH_H */\n\n/**\n *\n * End of file.\n */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/software_i2c/soft_i2c.c",
    "content": "#include \"soft_i2c.h\"\n\nI2C_HandleTypeDef hi2c0 =\n    {\n        .Instance = I2C_SOFT\n    };\n\nvoid delay_xus(__IO uint32_t nTime)\n{\n    int old_val, new_val, val;\n\n    if (nTime > 900)\n    {\n        for (old_val = 0; old_val < nTime / 900; old_val++)\n        {\n            delay_xus(900);\n        }\n        nTime = nTime % 900;\n    }\n\n    old_val = SysTick->VAL;\n    new_val = old_val - CPU_FREQUENCY_MHZ * nTime;\n    if (new_val >= 0)\n    {\n        do\n        {\n            val = SysTick->VAL;\n        } while ((val < old_val) && (val >= new_val));\n    } else\n    {\n        new_val += CPU_FREQUENCY_MHZ * 1000;\n        do\n        {\n            val = SysTick->VAL;\n        } while ((val <= old_val) || (val > new_val));\n\n    }\n}\n\n//--------------------------------------------\nvoid SDA_Output(void)\n{\n    GPIO_InitTypeDef GPIO_InitStruct;\n    GPIO_InitStruct.Pin = MYI2C_SDA_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(MYI2C_SDA_PORT, &GPIO_InitStruct);\n}\n\n\nvoid SDA_Input(void)\n{\n    GPIO_InitTypeDef GPIO_InitStruct;\n    GPIO_InitStruct.Pin = MYI2C_SDA_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(MYI2C_SDA_PORT, &GPIO_InitStruct);\n}\n\nvoid SCL_Output(void)\n{\n    GPIO_InitTypeDef GPIO_InitStruct;\n    GPIO_InitStruct.Pin = MYI2C_SCL_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(MYI2C_SCL_PORT, &GPIO_InitStruct);\n}\n\n\nvoid SCL_Input(void)\n{\n    GPIO_InitTypeDef GPIO_InitStruct;\n    GPIO_InitStruct.Pin = MYI2C_SCL_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(MYI2C_SCL_PORT, &GPIO_InitStruct);\n}\n\n\nvoid Soft_I2C_Init(void)\n{\n    SCL_Output();\n    SDA_Output();\n    SCL_Dout_HIGH();\n    SDA_Dout_HIGH();\n}\n\n\n//产生IIC起始信号\n\nvoid Soft_I2C_Start(void)\n{\n    SDA_Output();\n    SDA_Dout_HIGH();\n    SCL_Dout_HIGH();\n    Delay_us(4);\n    SDA_Dout_LOW();\n    Delay_us(4);\n    SCL_Dout_LOW();\n}\n\n\n//产生IIC停止信号\n\nvoid Soft_I2C_Stop(void)\n{\n    SDA_Output();\n    SCL_Dout_LOW();\n    SDA_Dout_LOW();\n    Delay_us(4);\n    SCL_Dout_HIGH();\n    SDA_Dout_HIGH();\n    Delay_us(4);\n}\n\nuint8_t Soft_I2C_Wait_Ack(void)\n{\n    uint8_t ucErrTime = 0;\n    SDA_Input();\n    SDA_Dout_HIGH();\n    Delay_us(1);\n    SCL_Dout_HIGH();\n    Delay_us(1);\n    while (SDA_Data_IN())\n    {\n        ucErrTime++;\n        if (ucErrTime > 250)\n        {\n            Soft_I2C_Stop();\n            return 1;\n        }\n    }\n    SCL_Dout_LOW();//时钟输出0\n    return 0;\n}\n\n//产生ACK应答\n\nvoid Soft_I2C_Ack(void)\n{\n    SCL_Dout_LOW();\n    SDA_Output();\n    SDA_Dout_LOW();\n    Delay_us(2);\n    SCL_Dout_HIGH();\n    Delay_us(2);\n    SCL_Dout_LOW();\n}\n\n//不产生ACK应答\n\nvoid Soft_I2C_NAck(void)\n{\n    SCL_Dout_LOW();\n    SDA_Output();\n    SDA_Dout_HIGH();\n    Delay_us(2);\n    SCL_Dout_HIGH();\n    Delay_us(2);\n    SCL_Dout_LOW();\n}\n\n//IIC发送一个字节\n//返回从机有无应答\n//1，有应答\n//0，无应答\nvoid Soft_I2C_Send_Byte(uint8_t txd)\n{\n    uint8_t t;\n    //拉低时钟开始数据传输\n    SDA_Output();\n    SCL_Dout_LOW();\n    for (t = 0; t < 8; t++)\n    {\n        SDA_Write((txd & 0x80) >> 7);\n        txd <<= 1;\n        Delay_us(5);   //对TEA5767这三个延时都是必须的\n        SCL_Dout_HIGH();\n        Delay_us(5);\n        SCL_Dout_LOW();\n        //Delay_us(2);\n    }\n}\n\n//读1个字节，ack=1时，发送ACK，ack=0，发送nACK\nuint8_t Soft_I2C_Read_Byte(uint8_t ack)\n{\n    unsigned char i, receive = 0;\n    //SDA设置为输入\n    SDA_Input();\n    for (i = 0; i < 8; i++)\n    {\n        SCL_Dout_LOW();\n        Delay_us(5);\n        SCL_Dout_HIGH();\n        receive <<= 1;\n        if (SDA_Data_IN())receive++;\n        Delay_us(5);\n    }\n    if (!ack)Soft_I2C_NAck();//发送nACK\n    else Soft_I2C_Ack(); //发送ACK\n\n    return receive;\n}\n\n\nvoid SOFT_I2C_Master_Transmit(uint8_t daddr, uint8_t *buff, uint8_t len)\n{\n    Soft_I2C_Start();\n    Soft_I2C_Send_Byte(daddr);\n    Soft_I2C_Wait_Ack();\n\n    for (int i = 0; i < len; i++)\n    {\n        Soft_I2C_Send_Byte(*(buff + i));\n        Soft_I2C_Wait_Ack();\n    }\n\n    Soft_I2C_Stop();\n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/software_i2c/soft_i2c.h",
    "content": "#ifndef __MYI2C_H__\n#define __MYI2C_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"stm32f4xx_hal.h\"\n#include \"gpio.h\"\n\n#define CPU_FREQUENCY_MHZ   0 //4\n#define MYI2C_SCL_PIN        GPIO_PIN_10\n#define MYI2C_SCL_PORT        GPIOB\n#define MYI2C_SDA_PIN            GPIO_PIN_11\n#define MYI2C_SDA_PORT        GPIOB\n\n#define SDA_Dout_LOW()                          HAL_GPIO_WritePin(MYI2C_SDA_PORT,MYI2C_SDA_PIN,GPIO_PIN_RESET)\n#define SDA_Dout_HIGH()                         HAL_GPIO_WritePin(MYI2C_SDA_PORT,MYI2C_SDA_PIN,GPIO_PIN_SET)\n#define SDA_Data_IN()                           HAL_GPIO_ReadPin(MYI2C_SDA_PORT,MYI2C_SDA_PIN)\n#define SCL_Dout_LOW()                          HAL_GPIO_WritePin(MYI2C_SCL_PORT,MYI2C_SCL_PIN,GPIO_PIN_RESET)\n#define SCL_Dout_HIGH()                         HAL_GPIO_WritePin(MYI2C_SCL_PORT,MYI2C_SCL_PIN,GPIO_PIN_SET)\n#define SCL_Data_IN()                           HAL_GPIO_ReadPin(MYI2C_SCL_PORT,MYI2C_SCL_PIN)\n#define SDA_Write(XX)                           HAL_GPIO_WritePin(MYI2C_SDA_PORT,MYI2C_SDA_PIN,(XX?GPIO_PIN_SET:GPIO_PIN_RESET))\n\n#define I2C_SOFT                ((I2C_TypeDef *) 0x00000000UL)\nextern I2C_HandleTypeDef hi2c0;\n\nvoid Soft_I2C_Init(void);\n\nvoid Soft_I2C_Start(void);\n\nvoid Soft_I2C_Stop(void);\n\nvoid Soft_I2C_Send_Byte(uint8_t txd);\n\nuint8_t Soft_I2C_Read_Byte(uint8_t ack);\n\nvoid Soft_I2C_NAck(void);\n\nvoid Soft_I2C_Ack(void);\n\nuint8_t Soft_I2C_Wait_Ack(void);\n\n\nvoid delay_xus(__IO uint32_t nTime);\n\nvoid SOFT_I2C_Master_Transmit(uint8_t daddr, uint8_t *buff, uint8_t len);\n\n\n#define Delay_us(xx)  delay_xus(xx)\n\n#ifdef __cplusplus\n}\n#endif\n#endif"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/time_utils.c",
    "content": "#include \"time_utils.h\"\n\n__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)\n{\n    //判断COUNTFLAG位是否为1，1则计数器已经递减到0了至少一次。读取该位后该位自动清零。\n    return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));\n}\n\nuint32_t micros(void)\n{\n    /* Ensure COUNTFLAG is reset by reading SysTick control and status register */\n    LL_SYSTICK_IsActiveCounterFlag();           //清除计数器\"溢出\"标志位\n    uint32_t m = HAL_GetTick();\n    const uint32_t tms = SysTick->LOAD + 1;\n    __IO uint32_t u = tms - SysTick->VAL;\n    if (LL_SYSTICK_IsActiveCounterFlag())\n    {\n        m = HAL_GetTick();\n        u = tms - SysTick->VAL;\n    }\n    return (m * 1000 + (u * 1000) / tms);\n}\n\nuint32_t millis(void)\n{\n    return HAL_GetTick();\n}\n\nvoid delayMicroseconds(uint32_t us)\n{\n    us *= 23;\n    while (us--)\n        __NOP();\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/time_utils.h",
    "content": "#ifndef REF_STM32F4_TIME_UTILS_H\n#define REF_STM32F4_TIME_UTILS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"main.h\"\n\nuint32_t micros(void);\nuint32_t millis(void);\nvoid delayMicroseconds(uint32_t us);\n\n#ifdef __cplusplus\n}\n#endif\n#endif //REF_STM32F4_TIME_UTILS_H\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/timer.cpp",
    "content": "#include \"timer.hpp\"\n\nstatic TimerCallback_t timerCallbacks[5];\n\nTimer::Timer(TIM_HandleTypeDef *_htim, uint32_t _freqHz)\n{\n    htim7.Instance = TIM7;\n    htim10.Instance = TIM10;\n    htim11.Instance = TIM11;\n    htim13.Instance = TIM13;\n    htim14.Instance = TIM14;\n\n    if (!(_htim->Instance == TIM7 ||\n          _htim->Instance == TIM10 ||\n          _htim->Instance == TIM11 ||\n          _htim->Instance == TIM13 ||\n          _htim->Instance == TIM14))\n    {\n        Error_Handler();\n    }\n\n    if (_freqHz < 1) _freqHz = 1;\n    else if (_freqHz > 10000000) _freqHz = 10000000;\n\n    htim = _htim;\n    freq = _freqHz;\n\n    CalcRegister(freq);\n\n    HAL_TIM_Base_DeInit(_htim);\n    _htim->Init.Prescaler = PSC - 1;\n    _htim->Init.CounterMode = TIM_COUNTERMODE_UP;\n    _htim->Init.Period = ARR - 1;\n    _htim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n    _htim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;\n    if (HAL_TIM_Base_Init(_htim) != HAL_OK)\n    {\n        Error_Handler();\n    }\n}\n\nvoid Timer::Start()\n{\n    HAL_TIM_Base_Start_IT(htim);\n}\n\nvoid Timer::CalcRegister(uint32_t _freq)\n{\n    float psc = 0.5;\n    float arr;\n\n    do\n    {\n        psc *= 2;\n        arr = 84000000.0f / psc / (float) _freq;\n    } while (arr > 65535);\n\n    if (htim->Instance == TIM7 || htim->Instance == TIM13 || htim->Instance == TIM14) // APB1 @84MHz\n    {\n        PSC = (uint16_t) round((double) psc);\n        ARR = (uint16_t) (84000000.0f / (float) _freq / psc);\n    } else if (htim->Instance == TIM10 || htim->Instance == TIM11) // APB2 @168MHz\n    {\n        PSC = (uint16_t) round((double) psc) * 2;\n        ARR = (uint16_t) (84000000.0f / (float) _freq / psc);\n    }\n}\n\n\nvoid Timer::SetCallback(TimerCallback_t _timerCallback)\n{\n    if (htim->Instance == TIM7)\n    {\n        timerCallbacks[0] = _timerCallback;\n    } else if (htim->Instance == TIM10)\n    {\n        timerCallbacks[1] = _timerCallback;\n    } else if (htim->Instance == TIM11)\n    {\n        timerCallbacks[2] = _timerCallback;\n    } else if (htim->Instance == TIM13)\n    {\n        timerCallbacks[3] = _timerCallback;\n    } else if (htim->Instance == TIM14)\n    {\n        timerCallbacks[4] = _timerCallback;\n    }\n}\n\n\nextern \"C\"\nvoid OnTimerCallback(TIM_TypeDef *timInstance)\n{\n    if (timInstance == TIM7)\n    {\n        timerCallbacks[0]();\n    } else if (timInstance == TIM10)\n    {\n        timerCallbacks[1]();\n    } else if (timInstance == TIM11)\n    {\n        timerCallbacks[2]();\n    } else if (timInstance == TIM13)\n    {\n        timerCallbacks[3]();\n    } else if (timInstance == TIM14)\n    {\n        timerCallbacks[4]();\n    }\n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Bsp/utils/timer.hpp",
    "content": "#ifndef REF_STM32F4_TIMER_HPP\n#define REF_STM32F4_TIMER_HPP\n\n#include <cmath>\n#include \"tim.h\"\n\ntypedef void (*TimerCallback_t)();\n\nclass Timer\n{\nprivate:\n    TIM_HandleTypeDef *htim;\n    uint32_t freq;\n    uint16_t PSC = 83;\n    uint16_t ARR = 9999;\n\n    void CalcRegister(uint32_t _freqHz);\n\npublic:\n    explicit Timer(TIM_HandleTypeDef *_htim, uint32_t _freqHz = 100);\n\n    void SetCallback(TimerCallback_t _timerCallback);\n\n    void Start();\n};\n\n#endif //REF_STM32F4_TIMER_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/CMakeLists.txt",
    "content": "#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!\r\nset(CMAKE_SYSTEM_NAME Generic)\r\nset(CMAKE_SYSTEM_VERSION 1)\r\ncmake_minimum_required(VERSION 3.19)\r\n\r\n# specify cross compilers and tools\r\nset(CMAKE_C_COMPILER arm-none-eabi-gcc)\r\nset(CMAKE_CXX_COMPILER arm-none-eabi-g++)\r\nset(CMAKE_ASM_COMPILER arm-none-eabi-gcc)\r\nset(CMAKE_AR arm-none-eabi-ar)\r\nset(CMAKE_OBJCOPY arm-none-eabi-objcopy)\r\nset(CMAKE_OBJDUMP arm-none-eabi-objdump)\r\nset(SIZE arm-none-eabi-size)\r\nset(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)\r\n\r\n# project settings\r\nproject(Core-STM32F4-fw C CXX ASM)\r\nset(CMAKE_CXX_STANDARD 17)\r\nset(CMAKE_C_STANDARD 11)\r\n\r\n# for use printf & scanf with float\r\nset(COMMON_FLAGS \"-specs=nosys.specs -specs=nano.specs -u _printf_float -u _scanf_float\")\r\n\r\n#Uncomment for hardware floating point\r\nadd_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)\r\nadd_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\r\nadd_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\r\n\r\n#Uncomment for software floating point\r\n#add_compile_options(-mfloat-abi=soft)\r\n\r\nadd_compile_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)\r\nadd_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)\r\n\r\n# uncomment to mitigate c++17 absolute addresses warnings\r\n#set(CMAKE_CXX_FLAGS \"${CMAKE_CXX_FLAGS} -Wno-register\")\r\n\r\nif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"Release\")\r\n    message(STATUS \"Maximum optimization for speed\")\r\n    add_compile_options(-Ofast)\r\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"RelWithDebInfo\")\r\n    message(STATUS \"Maximum optimization for speed, debug info included\")\r\n    add_compile_options(-Ofast -g)\r\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"MinSizeRel\")\r\n    message(STATUS \"Maximum optimization for size\")\r\n    add_compile_options(-Os)\r\nelse ()\r\n    message(STATUS \"Minimal optimization, debug info included\")\r\n    add_compile_options(-Og -g)\r\nendif ()\r\n\r\ninclude_directories(\r\n        Core/Inc\r\n        Drivers/STM32F4xx_HAL_Driver/Inc\r\n        Drivers/STM32F4xx_HAL_Driver/Inc/Legacy\r\n        Drivers/CMSIS/Device/ST/STM32F4xx/Include\r\n        Drivers/CMSIS/Include\r\n        Middlewares/Third_Party/FreeRTOS/Source/include\r\n        Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2\r\n        Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F\r\n        Middlewares/ST/STM32_USB_Device_Library/Core/Inc\r\n        Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc\r\n        USB_DEVICE/App\r\n        USB_DEVICE/Target\r\n        3rdParty/fibre/cpp/include\r\n        3rdParty/u8g2\r\n        3rdParty/u8g2/cpp\r\n        Bsp\r\n        Bsp/imu\r\n        Bsp/imu/filters\r\n        Bsp/communication\r\n        Bsp/memory\r\n        Bsp/utils\r\n        Bsp/gpio\r\n        Bsp/utils/software_i2c\r\n        Bsp/utils/arm_math\r\n        Robot\r\n        UserApp\r\n)\r\n\r\nadd_definitions(-DUSE_HAL_DRIVER -DSTM32F4 -DSTM32F4xx -DSTM32F405xx -DconfigAPPLICATION_ALLOCATED_HEAP)\r\n\r\nfile(GLOB_RECURSE SOURCES\r\n        \"startup/*.*\"\r\n        \"Drivers/*.*\"\r\n        \"Core/*.*\"\r\n        \"UserApp/*.*\"\r\n        \"3rdParty/*.*\"\r\n        \"Middlewares/*.*\"\r\n        \"USB_DEVICE/*.*\"\r\n        \"Robot/*.*\"\r\n        \"Bsp/*.*\"\r\n        )\r\n\r\nset(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32F405RGTx_FLASH.ld)\r\n\r\nadd_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)\r\nadd_link_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)\r\nadd_link_options(-T ${LINKER_SCRIPT})\r\n\r\nlink_directories(\"Drivers/CMSIS/Lib\")\r\nlink_libraries(\"arm_cortexM4lf_math.a\")\r\n\r\nadd_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})\r\n\r\nset(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)\r\nset(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)\r\n\r\nadd_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD\r\n        COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}\r\n        COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}\r\n        COMMENT \"Building ${HEX_FILE}\r\nBuilding ${BIN_FILE}\")\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/CMakeLists_template.txt",
    "content": "#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!\r\nset(CMAKE_SYSTEM_NAME Generic)\r\nset(CMAKE_SYSTEM_VERSION 1)\r\ncmake_minimum_required(VERSION 3.19)\r\n\r\n# specify cross compilers and tools\r\nset(CMAKE_C_COMPILER arm-none-eabi-gcc)\r\nset(CMAKE_CXX_COMPILER arm-none-eabi-g++)\r\nset(CMAKE_ASM_COMPILER arm-none-eabi-gcc)\r\nset(CMAKE_AR arm-none-eabi-ar)\r\nset(CMAKE_OBJCOPY arm-none-eabi-objcopy)\r\nset(CMAKE_OBJDUMP arm-none-eabi-objdump)\r\nset(SIZE arm-none-eabi-size)\r\nset(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)\r\n\r\n# project settings\r\nproject(Core-STM32F4-fw C CXX ASM)\r\nset(CMAKE_CXX_STANDARD 17)\r\nset(CMAKE_C_STANDARD 11)\r\n\r\n# for use printf & scanf with float\r\nset(COMMON_FLAGS \"-specs=nosys.specs -specs=nano.specs -u _printf_float -u _scanf_float\")\r\n\r\n#Uncomment for hardware floating point\r\nadd_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)\r\nadd_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\r\nadd_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\r\n\r\n#Uncomment for software floating point\r\n#add_compile_options(-mfloat-abi=soft)\r\n\r\nadd_compile_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)\r\nadd_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)\r\n\r\n# uncomment to mitigate c++17 absolute addresses warnings\r\n#set(CMAKE_CXX_FLAGS \"${CMAKE_CXX_FLAGS} -Wno-register\")\r\n\r\nif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"Release\")\r\n    message(STATUS \"Maximum optimization for speed\")\r\n    add_compile_options(-Ofast)\r\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"RelWithDebInfo\")\r\n    message(STATUS \"Maximum optimization for speed, debug info included\")\r\n    add_compile_options(-Ofast -g)\r\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"MinSizeRel\")\r\n    message(STATUS \"Maximum optimization for size\")\r\n    add_compile_options(-Os)\r\nelse ()\r\n    message(STATUS \"Minimal optimization, debug info included\")\r\n    add_compile_options(-Og -g)\r\nendif ()\r\n\r\ninclude_directories(\r\n        Core/Inc\r\n        Drivers/STM32F4xx_HAL_Driver/Inc\r\n        Drivers/STM32F4xx_HAL_Driver/Inc/Legacy\r\n        Drivers/CMSIS/Device/ST/STM32F4xx/Include\r\n        Drivers/CMSIS/Include\r\n        Middlewares/Third_Party/FreeRTOS/Source/include\r\n        Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2\r\n        Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F\r\n        Middlewares/ST/STM32_USB_Device_Library/Core/Inc\r\n        Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc\r\n        USB_DEVICE/App\r\n        USB_DEVICE/Target\r\n        3rdParty/fibre/cpp/include\r\n        3rdParty/u8g2\r\n        3rdParty/u8g2/cpp\r\n        Bsp\r\n        Bsp/imu\r\n        Bsp/imu/filters\r\n        Bsp/communication\r\n        Bsp/memory\r\n        Bsp/utils\r\n        Bsp/gpio\r\n        Bsp/utils/software_i2c\r\n        Bsp/utils/arm_math\r\n        Robot\r\n        UserApp\r\n)\r\n\r\nadd_definitions(-DUSE_HAL_DRIVER -DSTM32F4 -DSTM32F4xx -DSTM32F405xx -DconfigAPPLICATION_ALLOCATED_HEAP)\r\n\r\nfile(GLOB_RECURSE SOURCES\r\n        \"startup/*.*\"\r\n        \"Drivers/*.*\"\r\n        \"Core/*.*\"\r\n        \"UserApp/*.*\"\r\n        \"3rdParty/*.*\"\r\n        \"Middlewares/*.*\"\r\n        \"USB_DEVICE/*.*\"\r\n        \"Robot/*.*\"\r\n        \"Bsp/*.*\"\r\n        )\r\n\r\nset(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32F405RGTx_FLASH.ld)\r\n\r\nadd_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)\r\nadd_link_options(-mcpu=cortex-m4 -mthumb -mthumb-interwork)\r\nadd_link_options(-T ${LINKER_SCRIPT})\r\n\r\nlink_directories(\"Drivers/CMSIS/Lib\")\r\nlink_libraries(\"arm_cortexM4lf_math.a\")\r\n\r\nadd_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})\r\n\r\nset(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)\r\nset(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)\r\n\r\nadd_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD\r\n        COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}\r\n        COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}\r\n        COMMENT \"Building ${HEX_FILE}\r\nBuilding ${BIN_FILE}\")\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/FreeRTOSConfig.h",
    "content": "/* USER CODE BEGIN Header */\n/*\n * FreeRTOS Kernel V10.3.1\n * Portion Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n * Portion Copyright (C) 2019 StMicroelectronics, Inc.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n/* USER CODE END Header */\n\n#ifndef FREERTOS_CONFIG_H\n#define FREERTOS_CONFIG_H\n\n/*-----------------------------------------------------------\n * Application specific definitions.\n *\n * These definitions should be adjusted for your particular hardware and\n * application requirements.\n *\n * These parameters and more are described within the 'configuration' section of the\n * FreeRTOS API documentation available on the FreeRTOS.org web site.\n *\n * See http://www.freertos.org/a00110.html\n *----------------------------------------------------------*/\n\n/* USER CODE BEGIN Includes */\n/* Section where include file can be added */\n/* USER CODE END Includes */\n\n/* Ensure definitions are only used by the compiler, and not by the assembler. */\n#if defined(__ICCARM__) || defined(__CC_ARM) || defined(__GNUC__)\n  #include <stdint.h>\n  extern uint32_t SystemCoreClock;\n#endif\n#ifndef CMSIS_device_header\n#define CMSIS_device_header \"stm32f4xx.h\"\n#endif /* CMSIS_device_header */\n\n#define configENABLE_FPU                         1\n#define configENABLE_MPU                         0\n\n#define configUSE_PREEMPTION                     1\n#define configSUPPORT_STATIC_ALLOCATION          1\n#define configSUPPORT_DYNAMIC_ALLOCATION         1\n#define configUSE_IDLE_HOOK                      0\n#define configUSE_TICK_HOOK                      0\n#define configCPU_CLOCK_HZ                       ( SystemCoreClock )\n#define configTICK_RATE_HZ                       ((TickType_t)1000)\n#define configMAX_PRIORITIES                     ( 56 )\n#define configMINIMAL_STACK_SIZE                 ((uint16_t)128)\n#define configTOTAL_HEAP_SIZE                    ((size_t)65536)\n#define configMAX_TASK_NAME_LEN                  ( 16 )\n#define configUSE_TRACE_FACILITY                 1\n#define configUSE_16_BIT_TICKS                   0\n#define configUSE_MUTEXES                        1\n#define configQUEUE_REGISTRY_SIZE                8\n#define configUSE_RECURSIVE_MUTEXES              1\n#define configUSE_COUNTING_SEMAPHORES            1\n#define configUSE_PORT_OPTIMISED_TASK_SELECTION  0\n/* USER CODE BEGIN MESSAGE_BUFFER_LENGTH_TYPE */\n/* Defaults to size_t for backward compatibility, but can be changed\n   if lengths will always be less than the number of bytes in a size_t. */\n#define configMESSAGE_BUFFER_LENGTH_TYPE         size_t\n/* USER CODE END MESSAGE_BUFFER_LENGTH_TYPE */\n\n/* Co-routine definitions. */\n#define configUSE_CO_ROUTINES                    0\n#define configMAX_CO_ROUTINE_PRIORITIES          ( 2 )\n\n/* Software timer definitions. */\n#define configUSE_TIMERS                         1\n#define configTIMER_TASK_PRIORITY                ( 2 )\n#define configTIMER_QUEUE_LENGTH                 10\n#define configTIMER_TASK_STACK_DEPTH             256\n\n/* CMSIS-RTOS V2 flags */\n#define configUSE_OS2_THREAD_SUSPEND_RESUME  1\n#define configUSE_OS2_THREAD_ENUMERATE       1\n#define configUSE_OS2_EVENTFLAGS_FROM_ISR    1\n#define configUSE_OS2_THREAD_FLAGS           1\n#define configUSE_OS2_TIMER                  1\n#define configUSE_OS2_MUTEX                  1\n\n/* Set the following definitions to 1 to include the API function, or zero\nto exclude the API function. */\n#define INCLUDE_vTaskPrioritySet             1\n#define INCLUDE_uxTaskPriorityGet            1\n#define INCLUDE_vTaskDelete                  1\n#define INCLUDE_vTaskCleanUpResources        0\n#define INCLUDE_vTaskSuspend                 1\n#define INCLUDE_vTaskDelayUntil              1\n#define INCLUDE_vTaskDelay                   1\n#define INCLUDE_xTaskGetSchedulerState       1\n#define INCLUDE_xTimerPendFunctionCall       1\n#define INCLUDE_xQueueGetMutexHolder         1\n#define INCLUDE_uxTaskGetStackHighWaterMark  1\n#define INCLUDE_xTaskGetCurrentTaskHandle    1\n#define INCLUDE_eTaskGetState                1\n\n/*\n * The CMSIS-RTOS V2 FreeRTOS wrapper is dependent on the heap implementation used\n * by the application thus the correct define need to be enabled below\n */\n#define USE_FreeRTOS_HEAP_4\n\n/* Cortex-M specific definitions. */\n#ifdef __NVIC_PRIO_BITS\n /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */\n #define configPRIO_BITS         __NVIC_PRIO_BITS\n#else\n #define configPRIO_BITS         4\n#endif\n\n/* The lowest interrupt priority that can be used in a call to a \"set priority\"\nfunction. */\n#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY   15\n\n/* The highest interrupt priority that can be used by any interrupt service\nroutine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL\nINTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER\nPRIORITY THAN THIS! (higher priorities are lower numeric values. */\n#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5\n\n/* Interrupt priorities used by the kernel port layer itself.  These are generic\nto all Cortex-M ports, and do not rely on any particular library functions. */\n#define configKERNEL_INTERRUPT_PRIORITY \t\t( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!\nSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */\n#define configMAX_SYSCALL_INTERRUPT_PRIORITY \t( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )\n\n/* Normal assert() semantics without relying on the provision of an assert.h\nheader file. */\n/* USER CODE BEGIN 1 */\n#define configASSERT(x) if ((x) == 0) {taskDISABLE_INTERRUPTS(); for( ;; );}\n/* USER CODE END 1 */\n\n/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS\nstandard names. */\n#define vPortSVCHandler    SVC_Handler\n#define xPortPendSVHandler PendSV_Handler\n\n/* IMPORTANT: After 10.3.1 update, Systick_Handler comes from NVIC (if SYS timebase = systick), otherwise from cmsis_os2.c */\n\n#define USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION 0\n\n/* USER CODE BEGIN Defines */\n/* Section where parameter definitions can be added (for instance, to override default ones in FreeRTOS.h) */\n/* USER CODE END Defines */\n\n#endif /* FREERTOS_CONFIG_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/adc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    adc.h\n  * @brief   This file contains all the function prototypes for\n  *          the adc.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __ADC_H__\n#define __ADC_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern ADC_HandleTypeDef hadc1;\n\n/* USER CODE BEGIN Private defines */\n#define ADC_CH1 ADC_CHANNEL_12\n#define ADC_CH2 ADC_CHANNEL_13\n#define ADC_CH3 ADC_CHANNEL_14\n#define ADC_CH4 ADC_CHANNEL_15\n\n\n#define ADC_CHANNEL_REF 5\n#define ADC_CHANNEL_TEMP 4\nextern uint16_t adc1ValBuf[ADC_CHANNEL_REF + 1];\n\n\n/* USER CODE END Private defines */\n\nvoid MX_ADC1_Init(void);\n\n/* USER CODE BEGIN Prototypes */\nfloat AdcGetChipTemperature();\n\nfloat AdcGetVoltage(uint32_t _channel);\n\nuint16_t AdcGetRaw(uint32_t _channel);\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __ADC_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/can.h",
    "content": "/**\n  ******************************************************************************\n  * @file    can.h\n  * @brief   This file contains all the function prototypes for\n  *          the can.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __CAN_H__\n#define __CAN_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern CAN_HandleTypeDef hcan1;\nextern CAN_HandleTypeDef hcan2;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_CAN1_Init(void);\nvoid MX_CAN2_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CAN_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/dma.h",
    "content": "/**\n  ******************************************************************************\n  * @file    dma.h\n  * @brief   This file contains all the function prototypes for\n  *          the dma.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __DMA_H__\n#define __DMA_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* DMA memory to memory transfer handles -------------------------------------*/\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_DMA_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __DMA_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    gpio.h\n  * @brief   This file contains all the function prototypes for\n  *          the gpio.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __GPIO_H__\n#define __GPIO_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_GPIO_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n#endif /*__ GPIO_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/i2c.h",
    "content": "/**\n  ******************************************************************************\n  * @file    i2c.h\n  * @brief   This file contains all the function prototypes for\n  *          the i2c.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __I2C_H__\n#define __I2C_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern I2C_HandleTypeDef hi2c1;\nextern I2C_HandleTypeDef hi2c2;\nextern I2C_HandleTypeDef hi2c3;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_I2C1_Init(void);\nvoid MX_I2C2_Init(void);\nvoid MX_I2C3_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __I2C_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/main.h",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : main.h\n  * @brief          : Header for main.c file.\n  *                   This file contains the common defines of the application.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __MAIN_H\n#define __MAIN_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Exported types ------------------------------------------------------------*/\n/* USER CODE BEGIN ET */\n\n/* USER CODE END ET */\n\n/* Exported constants --------------------------------------------------------*/\n/* USER CODE BEGIN EC */\n\n/* USER CODE END EC */\n\n/* Exported macro ------------------------------------------------------------*/\n/* USER CODE BEGIN EM */\n\n/* USER CODE END EM */\n\n/* Exported functions prototypes ---------------------------------------------*/\nvoid Error_Handler(void);\n\n/* USER CODE BEGIN EFP */\n\n/* USER CODE END EFP */\n\n/* Private defines -----------------------------------------------------------*/\n#define KEY_Pin GPIO_PIN_13\n#define KEY_GPIO_Port GPIOC\n#define OLED_I2C2_SCL_Pin GPIO_PIN_10\n#define OLED_I2C2_SCL_GPIO_Port GPIOB\n#define OLED_I2C2_SDA_Pin GPIO_PIN_11\n#define OLED_I2C2_SDA_GPIO_Port GPIOB\n#define LED_Pin GPIO_PIN_8\n#define LED_GPIO_Port GPIOC\n#define IMU_I2C1_SCL_Pin GPIO_PIN_6\n#define IMU_I2C1_SCL_GPIO_Port GPIOB\n#define IMU_I2C1_SDA_Pin GPIO_PIN_7\n#define IMU_I2C1_SDA_GPIO_Port GPIOB\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __MAIN_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/spi.h",
    "content": "/**\n  ******************************************************************************\n  * @file    spi.h\n  * @brief   This file contains all the function prototypes for\n  *          the spi.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __SPI_H__\n#define __SPI_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern SPI_HandleTypeDef hspi1;\nextern SPI_HandleTypeDef hspi3;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_SPI1_Init(void);\nvoid MX_SPI3_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SPI_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/stm32f4xx_hal_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_conf_template.h\n  * @author  MCD Application Team\n  * @brief   HAL configuration template file.\n  *          This file should be copied to the application folder and renamed\n  *          to stm32f4xx_hal_conf.h.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_CONF_H\n#define __STM32F4xx_HAL_CONF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* ########################## Module Selection ############################## */\n/**\n  * @brief This is the list of modules to be used in the HAL driver\n  */\n#define HAL_MODULE_ENABLED\n\n  #define HAL_ADC_MODULE_ENABLED\n/* #define HAL_CRYP_MODULE_ENABLED   */\n#define HAL_CAN_MODULE_ENABLED\n/* #define HAL_CRC_MODULE_ENABLED   */\n/* #define HAL_CAN_LEGACY_MODULE_ENABLED   */\n/* #define HAL_CRYP_MODULE_ENABLED   */\n/* #define HAL_DAC_MODULE_ENABLED   */\n/* #define HAL_DCMI_MODULE_ENABLED   */\n/* #define HAL_DMA2D_MODULE_ENABLED   */\n/* #define HAL_ETH_MODULE_ENABLED   */\n/* #define HAL_NAND_MODULE_ENABLED   */\n/* #define HAL_NOR_MODULE_ENABLED   */\n/* #define HAL_PCCARD_MODULE_ENABLED   */\n/* #define HAL_SRAM_MODULE_ENABLED   */\n/* #define HAL_SDRAM_MODULE_ENABLED   */\n/* #define HAL_HASH_MODULE_ENABLED   */\n#define HAL_I2C_MODULE_ENABLED\n/* #define HAL_I2S_MODULE_ENABLED   */\n/* #define HAL_IWDG_MODULE_ENABLED   */\n/* #define HAL_LTDC_MODULE_ENABLED   */\n/* #define HAL_RNG_MODULE_ENABLED   */\n/* #define HAL_RTC_MODULE_ENABLED   */\n/* #define HAL_SAI_MODULE_ENABLED   */\n/* #define HAL_SD_MODULE_ENABLED   */\n/* #define HAL_MMC_MODULE_ENABLED   */\n#define HAL_SPI_MODULE_ENABLED\n#define HAL_TIM_MODULE_ENABLED\n#define HAL_UART_MODULE_ENABLED\n/* #define HAL_USART_MODULE_ENABLED   */\n/* #define HAL_IRDA_MODULE_ENABLED   */\n/* #define HAL_SMARTCARD_MODULE_ENABLED   */\n/* #define HAL_SMBUS_MODULE_ENABLED   */\n/* #define HAL_WWDG_MODULE_ENABLED   */\n#define HAL_PCD_MODULE_ENABLED\n/* #define HAL_HCD_MODULE_ENABLED   */\n/* #define HAL_DSI_MODULE_ENABLED   */\n/* #define HAL_QSPI_MODULE_ENABLED   */\n/* #define HAL_QSPI_MODULE_ENABLED   */\n/* #define HAL_CEC_MODULE_ENABLED   */\n/* #define HAL_FMPI2C_MODULE_ENABLED   */\n/* #define HAL_FMPSMBUS_MODULE_ENABLED   */\n/* #define HAL_SPDIFRX_MODULE_ENABLED   */\n/* #define HAL_DFSDM_MODULE_ENABLED   */\n/* #define HAL_LPTIM_MODULE_ENABLED   */\n#define HAL_GPIO_MODULE_ENABLED\n#define HAL_EXTI_MODULE_ENABLED\n#define HAL_DMA_MODULE_ENABLED\n#define HAL_RCC_MODULE_ENABLED\n#define HAL_FLASH_MODULE_ENABLED\n#define HAL_PWR_MODULE_ENABLED\n#define HAL_CORTEX_MODULE_ENABLED\n\n/* ########################## HSE/HSI Values adaptation ##################### */\n/**\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSE is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSE_STARTUP_TIMEOUT)\n  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief Internal High Speed oscillator (HSI) value.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSI is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @brief Internal Low Speed oscillator (LSI) value.\n  */\n#if !defined  (LSI_VALUE)\n #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/\n#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz\n                                             The real value may vary depending on the variations\n                                             in voltage and temperature.*/\n/**\n  * @brief External Low Speed oscillator (LSE) value.\n  */\n#if !defined  (LSE_VALUE)\n #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */\n#endif /* LSE_VALUE */\n\n#if !defined  (LSE_STARTUP_TIMEOUT)\n  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */\n#endif /* LSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief External clock source for I2S peripheral\n  *        This value is used by the I2S HAL module to compute the I2S clock source\n  *        frequency, this source is inserted directly through I2S_CKIN pad.\n  */\n#if !defined  (EXTERNAL_CLOCK_VALUE)\n  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/\n#endif /* EXTERNAL_CLOCK_VALUE */\n\n/* Tip: To avoid modifying this file each time you need to use different HSE,\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\n\n/* ########################### System Configuration ######################### */\n/**\n  * @brief This is the HAL system configuration section\n  */\n#define  VDD_VALUE\t\t      3300U /*!< Value of VDD in mv */\n#define  TICK_INT_PRIORITY            0U   /*!< tick interrupt priority */\n#define  USE_RTOS                     0U\n#define  PREFETCH_ENABLE              1U\n#define  INSTRUCTION_CACHE_ENABLE     1U\n#define  DATA_CACHE_ENABLE            1U\n\n#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */\n#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */\n#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */\n#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */\n#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */\n#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */\n#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */\n#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */\n#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */\n#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */\n#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */\n#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */\n#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */\n#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */\n#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */\n#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */\n#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */\n#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */\n#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */\n#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */\n#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */\n#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */\n#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */\n#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */\n#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */\n#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */\n#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */\n#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */\n#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */\n#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */\n#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */\n#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */\n#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */\n#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */\n#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */\n#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */\n#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */\n#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */\n#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT    1U */\n\n/* ################## Ethernet peripheral configuration ##################### */\n\n/* Section 1 : Ethernet peripheral configuration */\n\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\n#define MAC_ADDR0   2U\n#define MAC_ADDR1   0U\n#define MAC_ADDR2   0U\n#define MAC_ADDR3   0U\n#define MAC_ADDR4   0U\n#define MAC_ADDR5   0U\n\n/* Definition of the Ethernet driver buffers size and count */\n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\n#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */\n#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */\n\n/* Section 2: PHY configuration section */\n\n/* DP83848_PHY_ADDRESS Address*/\n#define DP83848_PHY_ADDRESS           0x01U\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/\n#define PHY_RESET_DELAY                 0x000000FFU\n/* PHY Configuration delay */\n#define PHY_CONFIG_DELAY                0x00000FFFU\n\n#define PHY_READ_TO                     0x0000FFFFU\n#define PHY_WRITE_TO                    0x0000FFFFU\n\n/* Section 3: Common PHY Registers */\n\n#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */\n#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */\n\n#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */\n#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */\n#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */\n#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */\n\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */\n\n/* Section 4: Extended PHY Registers */\n#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */\n\n#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */\n\n/* ################## SPI peripheral configuration ########################## */\n\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\n* Activated: CRC code is present inside driver\n* Deactivated: CRC code cleaned from driver\n*/\n\n#define USE_SPI_CRC                     0U\n\n/* Includes ------------------------------------------------------------------*/\n/**\n  * @brief Include module's header file\n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_rcc.h\"\n#endif /* HAL_RCC_MODULE_ENABLED */\n\n#ifdef HAL_GPIO_MODULE_ENABLED\n  #include \"stm32f4xx_hal_gpio.h\"\n#endif /* HAL_GPIO_MODULE_ENABLED */\n\n#ifdef HAL_EXTI_MODULE_ENABLED\n  #include \"stm32f4xx_hal_exti.h\"\n#endif /* HAL_EXTI_MODULE_ENABLED */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dma.h\"\n#endif /* HAL_DMA_MODULE_ENABLED */\n\n#ifdef HAL_CORTEX_MODULE_ENABLED\n  #include \"stm32f4xx_hal_cortex.h\"\n#endif /* HAL_CORTEX_MODULE_ENABLED */\n\n#ifdef HAL_ADC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_adc.h\"\n#endif /* HAL_ADC_MODULE_ENABLED */\n\n#ifdef HAL_CAN_MODULE_ENABLED\n  #include \"stm32f4xx_hal_can.h\"\n#endif /* HAL_CAN_MODULE_ENABLED */\n\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\n  #include \"stm32f4xx_hal_can_legacy.h\"\n#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */\n\n#ifdef HAL_CRC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_crc.h\"\n#endif /* HAL_CRC_MODULE_ENABLED */\n\n#ifdef HAL_CRYP_MODULE_ENABLED\n  #include \"stm32f4xx_hal_cryp.h\"\n#endif /* HAL_CRYP_MODULE_ENABLED */\n\n#ifdef HAL_DMA2D_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dma2d.h\"\n#endif /* HAL_DMA2D_MODULE_ENABLED */\n\n#ifdef HAL_DAC_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dac.h\"\n#endif /* HAL_DAC_MODULE_ENABLED */\n\n#ifdef HAL_DCMI_MODULE_ENABLED\n  #include \"stm32f4xx_hal_dcmi.h\"\n#endif /* HAL_DCMI_MODULE_ENABLED */\n\n#ifdef HAL_ETH_MODULE_ENABLED\n  #include \"stm32f4xx_hal_eth.h\"\n#endif /* HAL_ETH_MODULE_ENABLED */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n  #include \"stm32f4xx_hal_flash.h\"\n#endif /* HAL_FLASH_MODULE_ENABLED */\n\n#ifdef HAL_SRAM_MODULE_ENABLED\n  #include \"stm32f4xx_hal_sram.h\"\n#endif /* HAL_SRAM_MODULE_ENABLED */\n\n#ifdef HAL_NOR_MODULE_ENABLED\n  #include \"stm32f4xx_hal_nor.h\"\n#endif /* HAL_NOR_MODULE_ENABLED */\n\n#ifdef HAL_NAND_MODULE_ENABLED\n  #include \"stm32f4xx_hal_nand.h\"\n#endif /* HAL_NAND_MODULE_ENABLED */\n\n#ifdef HAL_PCCARD_MODULE_ENABLED\n  #include \"stm32f4xx_hal_pccard.h\"\n#endif /* HAL_PCCARD_MODULE_ENABLED */\n\n#ifdef HAL_SDRAM_MODULE_ENABLED\n  #include \"stm32f4xx_hal_sdram.h\"\n#endif /* HAL_SDRAM_MODULE_ENABLED */\n\n#ifdef HAL_HASH_MODULE_ENABLED\n #include \"stm32f4xx_hal_hash.h\"\n#endif /* HAL_HASH_MODULE_ENABLED */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n #include \"stm32f4xx_hal_i2c.h\"\n#endif /* HAL_I2C_MODULE_ENABLED */\n\n#ifdef HAL_SMBUS_MODULE_ENABLED\n #include \"stm32f4xx_hal_smbus.h\"\n#endif /* HAL_SMBUS_MODULE_ENABLED */\n\n#ifdef HAL_I2S_MODULE_ENABLED\n #include \"stm32f4xx_hal_i2s.h\"\n#endif /* HAL_I2S_MODULE_ENABLED */\n\n#ifdef HAL_IWDG_MODULE_ENABLED\n #include \"stm32f4xx_hal_iwdg.h\"\n#endif /* HAL_IWDG_MODULE_ENABLED */\n\n#ifdef HAL_LTDC_MODULE_ENABLED\n #include \"stm32f4xx_hal_ltdc.h\"\n#endif /* HAL_LTDC_MODULE_ENABLED */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n #include \"stm32f4xx_hal_pwr.h\"\n#endif /* HAL_PWR_MODULE_ENABLED */\n\n#ifdef HAL_RNG_MODULE_ENABLED\n #include \"stm32f4xx_hal_rng.h\"\n#endif /* HAL_RNG_MODULE_ENABLED */\n\n#ifdef HAL_RTC_MODULE_ENABLED\n #include \"stm32f4xx_hal_rtc.h\"\n#endif /* HAL_RTC_MODULE_ENABLED */\n\n#ifdef HAL_SAI_MODULE_ENABLED\n #include \"stm32f4xx_hal_sai.h\"\n#endif /* HAL_SAI_MODULE_ENABLED */\n\n#ifdef HAL_SD_MODULE_ENABLED\n #include \"stm32f4xx_hal_sd.h\"\n#endif /* HAL_SD_MODULE_ENABLED */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n #include \"stm32f4xx_hal_spi.h\"\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n #include \"stm32f4xx_hal_tim.h\"\n#endif /* HAL_TIM_MODULE_ENABLED */\n\n#ifdef HAL_UART_MODULE_ENABLED\n #include \"stm32f4xx_hal_uart.h\"\n#endif /* HAL_UART_MODULE_ENABLED */\n\n#ifdef HAL_USART_MODULE_ENABLED\n #include \"stm32f4xx_hal_usart.h\"\n#endif /* HAL_USART_MODULE_ENABLED */\n\n#ifdef HAL_IRDA_MODULE_ENABLED\n #include \"stm32f4xx_hal_irda.h\"\n#endif /* HAL_IRDA_MODULE_ENABLED */\n\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\n #include \"stm32f4xx_hal_smartcard.h\"\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\n\n#ifdef HAL_WWDG_MODULE_ENABLED\n #include \"stm32f4xx_hal_wwdg.h\"\n#endif /* HAL_WWDG_MODULE_ENABLED */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n #include \"stm32f4xx_hal_pcd.h\"\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n#ifdef HAL_HCD_MODULE_ENABLED\n #include \"stm32f4xx_hal_hcd.h\"\n#endif /* HAL_HCD_MODULE_ENABLED */\n\n#ifdef HAL_DSI_MODULE_ENABLED\n #include \"stm32f4xx_hal_dsi.h\"\n#endif /* HAL_DSI_MODULE_ENABLED */\n\n#ifdef HAL_QSPI_MODULE_ENABLED\n #include \"stm32f4xx_hal_qspi.h\"\n#endif /* HAL_QSPI_MODULE_ENABLED */\n\n#ifdef HAL_CEC_MODULE_ENABLED\n #include \"stm32f4xx_hal_cec.h\"\n#endif /* HAL_CEC_MODULE_ENABLED */\n\n#ifdef HAL_FMPI2C_MODULE_ENABLED\n #include \"stm32f4xx_hal_fmpi2c.h\"\n#endif /* HAL_FMPI2C_MODULE_ENABLED */\n\n#ifdef HAL_FMPSMBUS_MODULE_ENABLED\n #include \"stm32f4xx_hal_fmpsmbus.h\"\n#endif /* HAL_FMPSMBUS_MODULE_ENABLED */\n\n#ifdef HAL_SPDIFRX_MODULE_ENABLED\n #include \"stm32f4xx_hal_spdifrx.h\"\n#endif /* HAL_SPDIFRX_MODULE_ENABLED */\n\n#ifdef HAL_DFSDM_MODULE_ENABLED\n #include \"stm32f4xx_hal_dfsdm.h\"\n#endif /* HAL_DFSDM_MODULE_ENABLED */\n\n#ifdef HAL_LPTIM_MODULE_ENABLED\n #include \"stm32f4xx_hal_lptim.h\"\n#endif /* HAL_LPTIM_MODULE_ENABLED */\n\n#ifdef HAL_MMC_MODULE_ENABLED\n #include \"stm32f4xx_hal_mmc.h\"\n#endif /* HAL_MMC_MODULE_ENABLED */\n\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\n  void assert_failed(uint8_t* file, uint32_t line);\n#else\n  #define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_CONF_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/stm32f4xx_it.h",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file    stm32f4xx_it.h\n  * @brief   This file contains the headers of the interrupt handlers.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_IT_H\n#define __STM32F4xx_IT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Exported types ------------------------------------------------------------*/\n/* USER CODE BEGIN ET */\n\n/* USER CODE END ET */\n\n/* Exported constants --------------------------------------------------------*/\n/* USER CODE BEGIN EC */\n\n/* USER CODE END EC */\n\n/* Exported macro ------------------------------------------------------------*/\n/* USER CODE BEGIN EM */\n\n/* USER CODE END EM */\n\n/* Exported functions prototypes ---------------------------------------------*/\nvoid NMI_Handler(void);\nvoid HardFault_Handler(void);\nvoid MemManage_Handler(void);\nvoid BusFault_Handler(void);\nvoid UsageFault_Handler(void);\nvoid DebugMon_Handler(void);\nvoid DMA1_Stream0_IRQHandler(void);\nvoid DMA1_Stream2_IRQHandler(void);\nvoid DMA1_Stream4_IRQHandler(void);\nvoid ADC_IRQHandler(void);\nvoid CAN1_TX_IRQHandler(void);\nvoid CAN1_RX0_IRQHandler(void);\nvoid CAN1_RX1_IRQHandler(void);\nvoid CAN1_SCE_IRQHandler(void);\nvoid TIM1_UP_TIM10_IRQHandler(void);\nvoid TIM1_TRG_COM_TIM11_IRQHandler(void);\nvoid TIM2_IRQHandler(void);\nvoid TIM3_IRQHandler(void);\nvoid TIM8_UP_TIM13_IRQHandler(void);\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void);\nvoid DMA1_Stream7_IRQHandler(void);\nvoid SPI3_IRQHandler(void);\nvoid UART4_IRQHandler(void);\nvoid UART5_IRQHandler(void);\nvoid TIM6_DAC_IRQHandler(void);\nvoid TIM7_IRQHandler(void);\nvoid DMA2_Stream0_IRQHandler(void);\nvoid CAN2_TX_IRQHandler(void);\nvoid CAN2_RX0_IRQHandler(void);\nvoid CAN2_RX1_IRQHandler(void);\nvoid CAN2_SCE_IRQHandler(void);\nvoid OTG_FS_IRQHandler(void);\n/* USER CODE BEGIN EFP */\n\n/* USER CODE END EFP */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_IT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/tim.h",
    "content": "/**\n  ******************************************************************************\n  * @file    tim.h\n  * @brief   This file contains all the function prototypes for\n  *          the tim.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __TIM_H__\n#define __TIM_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern TIM_HandleTypeDef htim2;\nextern TIM_HandleTypeDef htim3;\nextern TIM_HandleTypeDef htim7;\nextern TIM_HandleTypeDef htim9;\nextern TIM_HandleTypeDef htim10;\nextern TIM_HandleTypeDef htim11;\nextern TIM_HandleTypeDef htim12;\nextern TIM_HandleTypeDef htim13;\nextern TIM_HandleTypeDef htim14;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_TIM2_Init(void);\nvoid MX_TIM3_Init(void);\nvoid MX_TIM7_Init(void);\nvoid MX_TIM9_Init(void);\nvoid MX_TIM10_Init(void);\nvoid MX_TIM11_Init(void);\nvoid MX_TIM12_Init(void);\nvoid MX_TIM13_Init(void);\nvoid MX_TIM14_Init(void);\n\nvoid HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);\n\n/* USER CODE BEGIN Prototypes */\nint64_t GetEncoderCount(TIM_TypeDef *tim);\nint64_t GetCntLoop(TIM_TypeDef *tim);\nvoid ClearCntLoop(TIM_TypeDef *tim);\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __TIM_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Inc/usart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usart.h\n  * @brief   This file contains all the function prototypes for\n  *          the usart.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USART_H__\n#define __USART_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern UART_HandleTypeDef huart4;\nextern UART_HandleTypeDef huart5;\nextern UART_HandleTypeDef huart1;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_UART4_Init(void);\nvoid MX_UART5_Init(void);\nvoid MX_USART1_UART_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USART_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/adc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    adc.c\n  * @brief   This file provides code for the configuration\n  *          of the ADC instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"adc.h\"\n\n/* USER CODE BEGIN 0 */\nuint16_t adc1ValBuf[ADC_CHANNEL_REF + 1] = {0};\n\n/* USER CODE END 0 */\n\nADC_HandleTypeDef hadc1;\nDMA_HandleTypeDef hdma_adc1;\n\n/* ADC1 init function */\nvoid MX_ADC1_Init(void)\n{\n\n  /* USER CODE BEGIN ADC1_Init 0 */\n\n  /* USER CODE END ADC1_Init 0 */\n\n  ADC_ChannelConfTypeDef sConfig = {0};\n\n  /* USER CODE BEGIN ADC1_Init 1 */\n\n  /* USER CODE END ADC1_Init 1 */\n  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)\n  */\n  hadc1.Instance = ADC1;\n  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;\n  hadc1.Init.Resolution = ADC_RESOLUTION_12B;\n  hadc1.Init.ScanConvMode = ENABLE;\n  hadc1.Init.ContinuousConvMode = ENABLE;\n  hadc1.Init.DiscontinuousConvMode = DISABLE;\n  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;\n  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;\n  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;\n  hadc1.Init.NbrOfConversion = 6;\n  hadc1.Init.DMAContinuousRequests = ENABLE;\n  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;\n  if (HAL_ADC_Init(&hadc1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_12;\n  sConfig.Rank = 1;\n  sConfig.SamplingTime = ADC_SAMPLETIME_28CYCLES;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_13;\n  sConfig.Rank = 2;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_14;\n  sConfig.Rank = 3;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_15;\n  sConfig.Rank = 4;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;\n  sConfig.Rank = 5;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.\n  */\n  sConfig.Channel = ADC_CHANNEL_VREFINT;\n  sConfig.Rank = 6;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN ADC1_Init 2 */\n    HAL_ADC_Start_DMA(&hadc1, (uint32_t *) &adc1ValBuf, hadc1.Init.NbrOfConversion);\n  /* USER CODE END ADC1_Init 2 */\n\n}\n\nvoid HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(adcHandle->Instance==ADC1)\n  {\n  /* USER CODE BEGIN ADC1_MspInit 0 */\n\n  /* USER CODE END ADC1_MspInit 0 */\n    /* ADC1 clock enable */\n    __HAL_RCC_ADC1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOC_CLK_ENABLE();\n    /**ADC1 GPIO Configuration\n    PC2     ------> ADC1_IN12\n    PC3     ------> ADC1_IN13\n    PC4     ------> ADC1_IN14\n    PC5     ------> ADC1_IN15\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5;\n    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n    /* ADC1 DMA Init */\n    /* ADC1 Init */\n    hdma_adc1.Instance = DMA2_Stream0;\n    hdma_adc1.Init.Channel = DMA_CHANNEL_0;\n    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;\n    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;\n    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;\n    hdma_adc1.Init.Mode = DMA_CIRCULAR;\n    hdma_adc1.Init.Priority = DMA_PRIORITY_LOW;\n    hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1);\n\n    /* ADC1 interrupt Init */\n    HAL_NVIC_SetPriority(ADC_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(ADC_IRQn);\n  /* USER CODE BEGIN ADC1_MspInit 1 */\n\n  /* USER CODE END ADC1_MspInit 1 */\n  }\n}\n\nvoid HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)\n{\n\n  if(adcHandle->Instance==ADC1)\n  {\n  /* USER CODE BEGIN ADC1_MspDeInit 0 */\n\n  /* USER CODE END ADC1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_ADC1_CLK_DISABLE();\n\n    /**ADC1 GPIO Configuration\n    PC2     ------> ADC1_IN12\n    PC3     ------> ADC1_IN13\n    PC4     ------> ADC1_IN14\n    PC5     ------> ADC1_IN15\n    */\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);\n\n    /* ADC1 DMA DeInit */\n    HAL_DMA_DeInit(adcHandle->DMA_Handle);\n\n    /* ADC1 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(ADC_IRQn);\n  /* USER CODE BEGIN ADC1_MspDeInit 1 */\n\n  /* USER CODE END ADC1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\nfloat AdcGetChipTemperature()\n{\n    float tempVal = TEMPSENSOR_CAL1_TEMP +\n                    (float) (adc1ValBuf[ADC_CHANNEL_TEMP] - *(__IO uint16_t *) (TEMPSENSOR_CAL1_ADDR))\n                    * (TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)\n                    / (float) (*(__IO uint16_t *) (TEMPSENSOR_CAL2_ADDR) - *(__IO uint16_t *) (TEMPSENSOR_CAL1_ADDR));\n\n    return tempVal;\n}\n\n\nfloat AdcGetVoltage(uint32_t _channel)\n{\n    uint8_t index = 0;\n    switch (_channel)\n    {\n        case ADC_CH1:\n            index = 0;\n            break;\n        case ADC_CH2:\n            index = 1;\n            break;\n        case ADC_CH3:\n            index = 2;\n            break;\n        case ADC_CH4:\n            index = 3;\n            break;\n        default:\n            index = 0;\n    }\n\n    float val = (float) adc1ValBuf[ADC_CHANNEL_REF] / (float) (*(__IO uint16_t *) (VREFINT_CAL_ADDR))\n                * (float) adc1ValBuf[index] / 4095\n                * 3.3f;\n\n    return val;\n}\n\nuint16_t AdcGetRaw(uint32_t _channel)\n{\n    uint8_t index = 0;\n    switch (_channel)\n    {\n        case ADC_CH1:\n            index = 0;\n            break;\n        case ADC_CH2:\n            index = 1;\n            break;\n        case ADC_CH3:\n            index = 2;\n            break;\n        case ADC_CH4:\n            index = 3;\n            break;\n        default:\n            index = 0;\n    }\n\n    return adc1ValBuf[index];\n}\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/can.c",
    "content": "/**\n  ******************************************************************************\n  * @file    can.c\n  * @brief   This file provides code for the configuration\n  *          of the CAN instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"can.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\nCAN_HandleTypeDef hcan1;\nCAN_HandleTypeDef hcan2;\n\n/* CAN1 init function */\nvoid MX_CAN1_Init(void)\n{\n\n  /* USER CODE BEGIN CAN1_Init 0 */\n\n  /* USER CODE END CAN1_Init 0 */\n\n  /* USER CODE BEGIN CAN1_Init 1 */\n\n  /* USER CODE END CAN1_Init 1 */\n  hcan1.Instance = CAN1;\n  hcan1.Init.Prescaler = 7;\n  hcan1.Init.Mode = CAN_MODE_NORMAL;\n  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;\n  hcan1.Init.TimeSeg1 = CAN_BS1_3TQ;\n  hcan1.Init.TimeSeg2 = CAN_BS2_2TQ;\n  hcan1.Init.TimeTriggeredMode = DISABLE;\n  hcan1.Init.AutoBusOff = DISABLE;\n  hcan1.Init.AutoWakeUp = ENABLE;\n  hcan1.Init.AutoRetransmission = DISABLE;\n  hcan1.Init.ReceiveFifoLocked = DISABLE;\n  hcan1.Init.TransmitFifoPriority = ENABLE;\n  if (HAL_CAN_Init(&hcan1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN CAN1_Init 2 */\n\n  /* USER CODE END CAN1_Init 2 */\n\n}\n/* CAN2 init function */\nvoid MX_CAN2_Init(void)\n{\n\n  /* USER CODE BEGIN CAN2_Init 0 */\n\n  /* USER CODE END CAN2_Init 0 */\n\n  /* USER CODE BEGIN CAN2_Init 1 */\n\n  /* USER CODE END CAN2_Init 1 */\n  hcan2.Instance = CAN2;\n  hcan2.Init.Prescaler = 7;\n  hcan2.Init.Mode = CAN_MODE_NORMAL;\n  hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;\n  hcan2.Init.TimeSeg1 = CAN_BS1_3TQ;\n  hcan2.Init.TimeSeg2 = CAN_BS2_2TQ;\n  hcan2.Init.TimeTriggeredMode = DISABLE;\n  hcan2.Init.AutoBusOff = DISABLE;\n  hcan2.Init.AutoWakeUp = ENABLE;\n  hcan2.Init.AutoRetransmission = DISABLE;\n  hcan2.Init.ReceiveFifoLocked = DISABLE;\n  hcan2.Init.TransmitFifoPriority = DISABLE;\n  if (HAL_CAN_Init(&hcan2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN CAN2_Init 2 */\n\n  /* USER CODE END CAN2_Init 2 */\n\n}\n\nstatic uint32_t HAL_RCC_CAN1_CLK_ENABLED=0;\n\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(canHandle->Instance==CAN1)\n  {\n  /* USER CODE BEGIN CAN1_MspInit 0 */\n\n  /* USER CODE END CAN1_MspInit 0 */\n    /* CAN1 clock enable */\n    HAL_RCC_CAN1_CLK_ENABLED++;\n    if(HAL_RCC_CAN1_CLK_ENABLED==1){\n      __HAL_RCC_CAN1_CLK_ENABLE();\n    }\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**CAN1 GPIO Configuration\n    PB8     ------> CAN1_RX\n    PB9     ------> CAN1_TX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_8;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_9;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* CAN1 interrupt Init */\n    HAL_NVIC_SetPriority(CAN1_TX_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN1_TX_IRQn);\n    HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);\n    HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);\n    HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);\n  /* USER CODE BEGIN CAN1_MspInit 1 */\n\n  /* USER CODE END CAN1_MspInit 1 */\n  }\n  else if(canHandle->Instance==CAN2)\n  {\n  /* USER CODE BEGIN CAN2_MspInit 0 */\n\n  /* USER CODE END CAN2_MspInit 0 */\n    /* CAN2 clock enable */\n    __HAL_RCC_CAN2_CLK_ENABLE();\n    HAL_RCC_CAN1_CLK_ENABLED++;\n    if(HAL_RCC_CAN1_CLK_ENABLED==1){\n      __HAL_RCC_CAN1_CLK_ENABLE();\n    }\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**CAN2 GPIO Configuration\n    PB12     ------> CAN2_RX\n    PB13     ------> CAN2_TX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_12;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_13;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* CAN2 interrupt Init */\n    HAL_NVIC_SetPriority(CAN2_TX_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN2_TX_IRQn);\n    HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);\n    HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);\n    HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn);\n  /* USER CODE BEGIN CAN2_MspInit 1 */\n\n  /* USER CODE END CAN2_MspInit 1 */\n  }\n}\n\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)\n{\n\n  if(canHandle->Instance==CAN1)\n  {\n  /* USER CODE BEGIN CAN1_MspDeInit 0 */\n\n  /* USER CODE END CAN1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    HAL_RCC_CAN1_CLK_ENABLED--;\n    if(HAL_RCC_CAN1_CLK_ENABLED==0){\n      __HAL_RCC_CAN1_CLK_DISABLE();\n    }\n\n    /**CAN1 GPIO Configuration\n    PB8     ------> CAN1_RX\n    PB9     ------> CAN1_TX\n    */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);\n\n    /* CAN1 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(CAN1_TX_IRQn);\n    HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);\n    HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);\n    HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn);\n  /* USER CODE BEGIN CAN1_MspDeInit 1 */\n\n  /* USER CODE END CAN1_MspDeInit 1 */\n  }\n  else if(canHandle->Instance==CAN2)\n  {\n  /* USER CODE BEGIN CAN2_MspDeInit 0 */\n\n  /* USER CODE END CAN2_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_CAN2_CLK_DISABLE();\n    HAL_RCC_CAN1_CLK_ENABLED--;\n    if(HAL_RCC_CAN1_CLK_ENABLED==0){\n      __HAL_RCC_CAN1_CLK_DISABLE();\n    }\n\n    /**CAN2 GPIO Configuration\n    PB12     ------> CAN2_RX\n    PB13     ------> CAN2_TX\n    */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);\n\n    /* CAN2 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(CAN2_TX_IRQn);\n    HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn);\n    HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn);\n    HAL_NVIC_DisableIRQ(CAN2_SCE_IRQn);\n  /* USER CODE BEGIN CAN2_MspDeInit 1 */\n\n  /* USER CODE END CAN2_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/dma.c",
    "content": "/**\n  ******************************************************************************\n  * @file    dma.c\n  * @brief   This file provides code for the configuration\n  *          of all the requested memory to memory DMA transfers.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"dma.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/*----------------------------------------------------------------------------*/\n/* Configure DMA                                                              */\n/*----------------------------------------------------------------------------*/\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/**\n  * Enable DMA controller clock\n  */\nvoid MX_DMA_Init(void)\n{\n\n  /* DMA controller clock enable */\n  __HAL_RCC_DMA1_CLK_ENABLE();\n  __HAL_RCC_DMA2_CLK_ENABLE();\n\n  /* DMA interrupt init */\n  /* DMA1_Stream0_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 6, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);\n  /* DMA1_Stream2_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 6, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);\n  /* DMA1_Stream4_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 6, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);\n  /* DMA1_Stream7_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Stream7_IRQn, 6, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Stream7_IRQn);\n  /* DMA2_Stream0_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 5, 0);\n  HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);\n\n}\n\n/* USER CODE BEGIN 2 */\n\n/* USER CODE END 2 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/freertos.c",
    "content": "/* USER CODE BEGIN Header */\r\n/**\r\n  ******************************************************************************\r\n  * File Name          : freertos.c\r\n  * Description        : Code for freertos applications\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under Ultimate Liberty license\r\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\r\n  * the License. You may obtain a copy of the License at:\r\n  *                             www.st.com/SLA0044\r\n  *\r\n  ******************************************************************************\r\n  */\r\n/* USER CODE END Header */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"FreeRTOS.h\"\r\n#include \"task.h\"\r\n#include \"main.h\"\r\n#include \"cmsis_os.h\"\r\n\r\n/* Private includes ----------------------------------------------------------*/\r\n/* USER CODE BEGIN Includes */\r\n#include \"common_inc.h\"\r\n#include \"communication.hpp\"\r\n/* USER CODE END Includes */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* USER CODE BEGIN PTD */\r\n\r\n/* USER CODE END PTD */\r\n\r\n/* Private define ------------------------------------------------------------*/\r\n/* USER CODE BEGIN PD */\r\n\r\n/* USER CODE END PD */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* USER CODE BEGIN PM */\r\n\r\n/* USER CODE END PM */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* USER CODE BEGIN Variables */\r\n\r\n// List of semaphores\r\nosSemaphoreId sem_usb_irq;\r\nosSemaphoreId sem_uart4_dma;\r\nosSemaphoreId sem_uart5_dma;\r\nosSemaphoreId sem_usb_rx;\r\nosSemaphoreId sem_usb_tx;\r\nosSemaphoreId sem_can1_tx;\r\nosSemaphoreId sem_can2_tx;\r\n\r\n/* USER CODE END Variables */\r\n/* Definitions for defaultTask */\r\nosThreadId_t defaultTaskHandle;\r\nconst osThreadAttr_t defaultTask_attributes = {\r\n  .name = \"defaultTask\",\r\n  .stack_size = 2000,\r\n  .priority = (osPriority_t) osPriorityNormal,\r\n};\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* USER CODE BEGIN FunctionPrototypes */\r\n\r\n\r\n/* USER CODE END FunctionPrototypes */\r\n\r\nvoid StartDefaultTask(void *argument);\r\n\r\nextern void MX_USB_DEVICE_Init(void);\r\nvoid MX_FREERTOS_Init(void); /* (MISRA C 2004 rule 8.1) */\r\n\r\n/**\r\n  * @brief  FreeRTOS initialization\r\n  * @param  None\r\n  * @retval None\r\n  */\r\nvoid MX_FREERTOS_Init(void) {\r\n  /* USER CODE BEGIN Init */\r\n\r\n  /* USER CODE END Init */\r\n\r\n  /* USER CODE BEGIN RTOS_MUTEX */\r\n    /* add mutexes, ... */\r\n  /* USER CODE END RTOS_MUTEX */\r\n\r\n  /* USER CODE BEGIN RTOS_SEMAPHORES */\r\n    // Init usb irq binary semaphore, and start with no tokens by removing the starting one.\r\n    osSemaphoreDef(sem_usb_irq);\r\n    sem_usb_irq = osSemaphoreNew(1, 0, osSemaphore(sem_usb_irq));\r\n\r\n    // Create a semaphore for UART DMA and remove a token\r\n    osSemaphoreDef(sem_uart4_dma);\r\n    sem_uart4_dma = osSemaphoreNew(1, 1, osSemaphore(sem_uart4_dma));\r\n    osSemaphoreDef(sem_uart5_dma);\r\n    sem_uart5_dma = osSemaphoreNew(1, 1, osSemaphore(sem_uart5_dma));\r\n\r\n    // Create a semaphore for USB RX, and start with no tokens by removing the starting one.\r\n    osSemaphoreDef(sem_usb_rx);\r\n    sem_usb_rx = osSemaphoreNew(1, 0, osSemaphore(sem_usb_rx));\r\n\r\n    // Create a semaphore for USB TX\r\n    osSemaphoreDef(sem_usb_tx);\r\n    sem_usb_tx = osSemaphoreNew(1, 1, osSemaphore(sem_usb_tx));\r\n\r\n    // Create a semaphore for CAN TX\r\n    osSemaphoreDef(sem_can1_tx);\r\n    sem_can1_tx = osSemaphoreNew(1, 1, osSemaphore(sem_can1_tx));\r\n    osSemaphoreDef(sem_can2_tx);\r\n    sem_can2_tx = osSemaphoreNew(1, 1, osSemaphore(sem_can2_tx));\r\n\r\n  /* USER CODE END RTOS_SEMAPHORES */\r\n\r\n  /* USER CODE BEGIN RTOS_TIMERS */\r\n\r\n  /* USER CODE END RTOS_TIMERS */\r\n\r\n  /* USER CODE BEGIN RTOS_QUEUES */\r\n    // This Task must run before MX_USB_DEVICE_Init(), so have to put it here.\r\n    const osThreadAttr_t usbIrqTask_attributes = {\r\n        .name = \"usbIrqTask\",\r\n        .stack_size = 500,\r\n        .priority = (osPriority_t) osPriorityAboveNormal,\r\n    };\r\n    usbIrqTaskHandle = osThreadNew(UsbDeferredInterruptTask, NULL, &usbIrqTask_attributes);\r\n\r\n  /* USER CODE END RTOS_QUEUES */\r\n\r\n  /* Create the thread(s) */\r\n  /* creation of defaultTask */\r\n  defaultTaskHandle = osThreadNew(StartDefaultTask, NULL, &defaultTask_attributes);\r\n\r\n  /* USER CODE BEGIN RTOS_THREADS */\r\n    /* add threads, ... */\r\n  /* USER CODE END RTOS_THREADS */\r\n\r\n  /* USER CODE BEGIN RTOS_EVENTS */\r\n    /* add events, ... */\r\n  /* USER CODE END RTOS_EVENTS */\r\n\r\n}\r\n\r\n/* USER CODE BEGIN Header_StartDefaultTask */\r\n/**\r\n  * @brief  Function implementing the defaultTask thread.\r\n  * @param  argument: Not used\r\n  * @retval None\r\n  */\r\n/* USER CODE END Header_StartDefaultTask */\r\nvoid StartDefaultTask(void *argument)\r\n{\r\n  /* init code for USB_DEVICE */\r\n  MX_USB_DEVICE_Init();\r\n  /* USER CODE BEGIN StartDefaultTask */\r\n\r\n    // Invoke cpp-version main().\r\n    Main();\r\n\r\n    vTaskDelete(defaultTaskHandle);\r\n  /* USER CODE END StartDefaultTask */\r\n}\r\n\r\n/* Private application code --------------------------------------------------*/\r\n/* USER CODE BEGIN Application */\r\n\r\n/* USER CODE END Application */\r\n\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/gpio.c",
    "content": "/**\n  ******************************************************************************\n  * @file    gpio.c\n  * @brief   This file provides code for the configuration\n  *          of all used GPIO pins.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"gpio.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/*----------------------------------------------------------------------------*/\n/* Configure GPIO                                                             */\n/*----------------------------------------------------------------------------*/\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/** Configure pins as\n        * Analog\n        * Input\n        * Output\n        * EVENT_OUT\n        * EXTI\n*/\nvoid MX_GPIO_Init(void)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n\n  /* GPIO Ports Clock Enable */\n  __HAL_RCC_GPIOC_CLK_ENABLE();\n  __HAL_RCC_GPIOH_CLK_ENABLE();\n  __HAL_RCC_GPIOA_CLK_ENABLE();\n  __HAL_RCC_GPIOB_CLK_ENABLE();\n  __HAL_RCC_GPIOD_CLK_ENABLE();\n\n  /*Configure GPIO pin Output Level */\n  HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_SET);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = KEY_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n  GPIO_InitStruct.Pull = GPIO_PULLUP;\n  HAL_GPIO_Init(KEY_GPIO_Port, &GPIO_InitStruct);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = LED_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n  HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct);\n\n}\n\n/* USER CODE BEGIN 2 */\n\n/* USER CODE END 2 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/i2c.c",
    "content": "/**\n  ******************************************************************************\n  * @file    i2c.c\n  * @brief   This file provides code for the configuration\n  *          of the I2C instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"i2c.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\nI2C_HandleTypeDef hi2c1;\nI2C_HandleTypeDef hi2c2;\nI2C_HandleTypeDef hi2c3;\n\n/* I2C1 init function */\nvoid MX_I2C1_Init(void)\n{\n\n  /* USER CODE BEGIN I2C1_Init 0 */\n\n  /* USER CODE END I2C1_Init 0 */\n\n  /* USER CODE BEGIN I2C1_Init 1 */\n\n  /* USER CODE END I2C1_Init 1 */\n  hi2c1.Instance = I2C1;\n  hi2c1.Init.ClockSpeed = 400000;\n  hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;\n  hi2c1.Init.OwnAddress1 = 0;\n  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\n  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\n  hi2c1.Init.OwnAddress2 = 0;\n  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\n  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\n  if (HAL_I2C_Init(&hi2c1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN I2C1_Init 2 */\n\n  /* USER CODE END I2C1_Init 2 */\n\n}\n/* I2C2 init function */\nvoid MX_I2C2_Init(void)\n{\n\n  /* USER CODE BEGIN I2C2_Init 0 */\n\n  /* USER CODE END I2C2_Init 0 */\n\n  /* USER CODE BEGIN I2C2_Init 1 */\n\n  /* USER CODE END I2C2_Init 1 */\n  hi2c2.Instance = I2C2;\n  hi2c2.Init.ClockSpeed = 400000;\n  hi2c2.Init.DutyCycle = I2C_DUTYCYCLE_2;\n  hi2c2.Init.OwnAddress1 = 0;\n  hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\n  hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\n  hi2c2.Init.OwnAddress2 = 0;\n  hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\n  hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\n  if (HAL_I2C_Init(&hi2c2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN I2C2_Init 2 */\n\n  /* USER CODE END I2C2_Init 2 */\n\n}\n/* I2C3 init function */\nvoid MX_I2C3_Init(void)\n{\n\n  /* USER CODE BEGIN I2C3_Init 0 */\n\n  /* USER CODE END I2C3_Init 0 */\n\n  /* USER CODE BEGIN I2C3_Init 1 */\n\n  /* USER CODE END I2C3_Init 1 */\n  hi2c3.Instance = I2C3;\n  hi2c3.Init.ClockSpeed = 400000;\n  hi2c3.Init.DutyCycle = I2C_DUTYCYCLE_2;\n  hi2c3.Init.OwnAddress1 = 0;\n  hi2c3.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;\n  hi2c3.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;\n  hi2c3.Init.OwnAddress2 = 0;\n  hi2c3.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;\n  hi2c3.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;\n  if (HAL_I2C_Init(&hi2c3) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN I2C3_Init 2 */\n\n  /* USER CODE END I2C3_Init 2 */\n\n}\n\nvoid HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(i2cHandle->Instance==I2C1)\n  {\n  /* USER CODE BEGIN I2C1_MspInit 0 */\n\n  /* USER CODE END I2C1_MspInit 0 */\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**I2C1 GPIO Configuration\n    PB6     ------> I2C1_SCL\n    PB7     ------> I2C1_SDA\n    */\n    GPIO_InitStruct.Pin = IMU_I2C1_SCL_Pin|IMU_I2C1_SDA_Pin;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* I2C1 clock enable */\n    __HAL_RCC_I2C1_CLK_ENABLE();\n  /* USER CODE BEGIN I2C1_MspInit 1 */\n\n  /* USER CODE END I2C1_MspInit 1 */\n  }\n  else if(i2cHandle->Instance==I2C2)\n  {\n  /* USER CODE BEGIN I2C2_MspInit 0 */\n\n  /* USER CODE END I2C2_MspInit 0 */\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**I2C2 GPIO Configuration\n    PB10     ------> I2C2_SCL\n    PB11     ------> I2C2_SDA\n    */\n    GPIO_InitStruct.Pin = OLED_I2C2_SCL_Pin|OLED_I2C2_SDA_Pin;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* I2C2 clock enable */\n    __HAL_RCC_I2C2_CLK_ENABLE();\n  /* USER CODE BEGIN I2C2_MspInit 1 */\n\n  /* USER CODE END I2C2_MspInit 1 */\n  }\n  else if(i2cHandle->Instance==I2C3)\n  {\n  /* USER CODE BEGIN I2C3_MspInit 0 */\n\n  /* USER CODE END I2C3_MspInit 0 */\n\n    __HAL_RCC_GPIOC_CLK_ENABLE();\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**I2C3 GPIO Configuration\n    PC9     ------> I2C3_SDA\n    PA8     ------> I2C3_SCL\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_9;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_8;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF4_I2C3;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* I2C3 clock enable */\n    __HAL_RCC_I2C3_CLK_ENABLE();\n  /* USER CODE BEGIN I2C3_MspInit 1 */\n\n  /* USER CODE END I2C3_MspInit 1 */\n  }\n}\n\nvoid HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle)\n{\n\n  if(i2cHandle->Instance==I2C1)\n  {\n  /* USER CODE BEGIN I2C1_MspDeInit 0 */\n\n  /* USER CODE END I2C1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_I2C1_CLK_DISABLE();\n\n    /**I2C1 GPIO Configuration\n    PB6     ------> I2C1_SCL\n    PB7     ------> I2C1_SDA\n    */\n    HAL_GPIO_DeInit(IMU_I2C1_SCL_GPIO_Port, IMU_I2C1_SCL_Pin);\n\n    HAL_GPIO_DeInit(IMU_I2C1_SDA_GPIO_Port, IMU_I2C1_SDA_Pin);\n\n  /* USER CODE BEGIN I2C1_MspDeInit 1 */\n\n  /* USER CODE END I2C1_MspDeInit 1 */\n  }\n  else if(i2cHandle->Instance==I2C2)\n  {\n  /* USER CODE BEGIN I2C2_MspDeInit 0 */\n\n  /* USER CODE END I2C2_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_I2C2_CLK_DISABLE();\n\n    /**I2C2 GPIO Configuration\n    PB10     ------> I2C2_SCL\n    PB11     ------> I2C2_SDA\n    */\n    HAL_GPIO_DeInit(OLED_I2C2_SCL_GPIO_Port, OLED_I2C2_SCL_Pin);\n\n    HAL_GPIO_DeInit(OLED_I2C2_SDA_GPIO_Port, OLED_I2C2_SDA_Pin);\n\n  /* USER CODE BEGIN I2C2_MspDeInit 1 */\n\n  /* USER CODE END I2C2_MspDeInit 1 */\n  }\n  else if(i2cHandle->Instance==I2C3)\n  {\n  /* USER CODE BEGIN I2C3_MspDeInit 0 */\n\n  /* USER CODE END I2C3_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_I2C3_CLK_DISABLE();\n\n    /**I2C3 GPIO Configuration\n    PC9     ------> I2C3_SDA\n    PA8     ------> I2C3_SCL\n    */\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_9);\n\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8);\n\n  /* USER CODE BEGIN I2C3_MspDeInit 1 */\n\n  /* USER CODE END I2C3_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/main.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : main.c\n  * @brief          : Main program body\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n#include \"cmsis_os.h\"\n#include \"adc.h\"\n#include \"can.h\"\n#include \"dma.h\"\n#include \"i2c.h\"\n#include \"spi.h\"\n#include \"tim.h\"\n#include \"usart.h\"\n#include \"usb_device.h\"\n#include \"gpio.h\"\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* USER CODE BEGIN PTD */\n\n/* USER CODE END PTD */\n\n/* Private define ------------------------------------------------------------*/\n/* USER CODE BEGIN PD */\n/* USER CODE END PD */\n\n/* Private macro -------------------------------------------------------------*/\n/* USER CODE BEGIN PM */\n\n/* USER CODE END PM */\n\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE BEGIN PV */\nuint64_t serialNumber;\nchar serialNumberStr[13];\n__attribute__((section(\".ccmram\"))) uint8_t ucHeap[configTOTAL_HEAP_SIZE];\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\nvoid SystemClock_Config(void);\nvoid MX_FREERTOS_Init(void);\n/* USER CODE BEGIN PFP */\n\n/* USER CODE END PFP */\n\n/* Private user code ---------------------------------------------------------*/\n/* USER CODE BEGIN 0 */\n\n\n/* USER CODE END 0 */\n\n/**\n  * @brief  The application entry point.\n  * @retval int\n  */\nint main(void)\n{\n  /* USER CODE BEGIN 1 */\n\n    // This procedure of building a USB serial number should be identical\n    // to the way the STM's built-in USB bootloader does it. This means\n    // that the device will have the same serial number in normal and DFU mode.\n    uint32_t uuid0 = *(uint32_t *) (UID_BASE + 0);\n    uint32_t uuid1 = *(uint32_t *) (UID_BASE + 4);\n    uint32_t uuid2 = *(uint32_t *) (UID_BASE + 8);\n    uint32_t uuid_mixed_part = uuid0 + uuid2;\n    serialNumber = ((uint64_t) uuid_mixed_part << 16) | (uint64_t) (uuid1 >> 16);\n\n    uint64_t val = serialNumber;\n    for (size_t i = 0; i < 12; ++i)\n    {\n        serialNumberStr[i] = \"0123456789ABCDEF\"[(val >> (48 - 4)) & 0xf];\n        val <<= 4;\n    }\n    serialNumberStr[12] = 0;\n\n  /* USER CODE END 1 */\n\n  /* MCU Configuration--------------------------------------------------------*/\n\n  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\n  HAL_Init();\n\n  /* USER CODE BEGIN Init */\n    HAL_RCC_DeInit();\n\n  /* USER CODE END Init */\n\n  /* Configure the system clock */\n  SystemClock_Config();\n\n  /* USER CODE BEGIN SysInit */\n\n  /* USER CODE END SysInit */\n\n  /* Initialize all configured peripherals */\n  MX_GPIO_Init();\n  MX_DMA_Init();\n  MX_I2C1_Init();\n  MX_I2C2_Init();\n  MX_CAN1_Init();\n  MX_CAN2_Init();\n  MX_USART1_UART_Init();\n  MX_I2C3_Init();\n  MX_SPI1_Init();\n  MX_SPI3_Init();\n  MX_UART4_Init();\n  MX_ADC1_Init();\n  MX_UART5_Init();\n  MX_TIM2_Init();\n  MX_TIM3_Init();\n  /* USER CODE BEGIN 2 */\n\n  /* USER CODE END 2 */\n\n  /* Init scheduler */\n  osKernelInitialize();  /* Call init function for freertos objects (in freertos.c) */\n  MX_FREERTOS_Init();\n  /* Start scheduler */\n  osKernelStart();\n\n  /* We should never get here as control is now taken by the scheduler */\n  /* Infinite loop */\n  /* USER CODE BEGIN WHILE */\n\n    while (1)\n    {\n    /* USER CODE END WHILE */\n\n    /* USER CODE BEGIN 3 */\n    }\n  /* USER CODE END 3 */\n}\n\n/**\n  * @brief System Clock Configuration\n  * @retval None\n  */\nvoid SystemClock_Config(void)\n{\n  RCC_OscInitTypeDef RCC_OscInitStruct = {0};\n  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\n\n  /** Configure the main internal regulator output voltage\n  */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);\n  /** Initializes the RCC Oscillators according to the specified parameters\n  * in the RCC_OscInitTypeDef structure.\n  */\n  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n  RCC_OscInitStruct.HSEState = RCC_HSE_ON;\n  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n  RCC_OscInitStruct.PLL.PLLM = 4;\n  RCC_OscInitStruct.PLL.PLLN = 168;\n  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;\n  RCC_OscInitStruct.PLL.PLLQ = 7;\n  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Initializes the CPU, AHB and APB buses clocks\n  */\n  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\n                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\n  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\n  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\n  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;\n  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;\n\n  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)\n  {\n    Error_Handler();\n  }\n}\n\n/* USER CODE BEGIN 4 */\nvoid OnTimerCallback(TIM_TypeDef *timInstance);\n/* USER CODE END 4 */\n\n /**\n  * @brief  Period elapsed callback in non blocking mode\n  * @note   This function is called  when TIM6 interrupt took place, inside\n  * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment\n  * a global variable \"uwTick\" used as application time base.\n  * @param  htim : TIM handle\n  * @retval None\n  */\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\n{\n  /* USER CODE BEGIN Callback 0 */\n\n  /* USER CODE END Callback 0 */\n  if (htim->Instance == TIM6) {\n    HAL_IncTick();\n  }\n  /* USER CODE BEGIN Callback 1 */\n  else\n  {\n      OnTimerCallback(htim->Instance);\n  }\n  /* USER CODE END Callback 1 */\n}\n\n/**\n  * @brief  This function is executed in case of error occurrence.\n  * @retval None\n  */\nvoid Error_Handler(void)\n{\n  /* USER CODE BEGIN Error_Handler_Debug */\n    /* User can add his own implementation to report the HAL error return state */\n    __disable_irq();\n    while (1)\n    {\n    }\n  /* USER CODE END Error_Handler_Debug */\n}\n\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  Reports the name of the source file and the source line number\n  *         where the assert_param error has occurred.\n  * @param  file: pointer to the source file name\n  * @param  line: assert_param error line source number\n  * @retval None\n  */\nvoid assert_failed(uint8_t *file, uint32_t line)\n{\n  /* USER CODE BEGIN 6 */\n  /* User can add his own implementation to report the file name and line number,\n     ex: printf(\"Wrong parameters value: file %s on line %d\\r\\n\", file, line) */\n  /* USER CODE END 6 */\n}\n#endif /* USE_FULL_ASSERT */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/spi.c",
    "content": "/**\n  ******************************************************************************\n  * @file    spi.c\n  * @brief   This file provides code for the configuration\n  *          of the SPI instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"spi.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\nSPI_HandleTypeDef hspi1;\nSPI_HandleTypeDef hspi3;\n\n/* SPI1 init function */\nvoid MX_SPI1_Init(void)\n{\n\n  /* USER CODE BEGIN SPI1_Init 0 */\n\n  /* USER CODE END SPI1_Init 0 */\n\n  /* USER CODE BEGIN SPI1_Init 1 */\n\n  /* USER CODE END SPI1_Init 1 */\n  hspi1.Instance = SPI1;\n  hspi1.Init.Mode = SPI_MODE_MASTER;\n  hspi1.Init.Direction = SPI_DIRECTION_2LINES;\n  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;\n  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;\n  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;\n  hspi1.Init.NSS = SPI_NSS_SOFT;\n  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\n  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;\n  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;\n  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n  hspi1.Init.CRCPolynomial = 10;\n  if (HAL_SPI_Init(&hspi1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN SPI1_Init 2 */\n\n  /* USER CODE END SPI1_Init 2 */\n\n}\n/* SPI3 init function */\nvoid MX_SPI3_Init(void)\n{\n\n  /* USER CODE BEGIN SPI3_Init 0 */\n\n  /* USER CODE END SPI3_Init 0 */\n\n  /* USER CODE BEGIN SPI3_Init 1 */\n\n  /* USER CODE END SPI3_Init 1 */\n  hspi3.Instance = SPI3;\n  hspi3.Init.Mode = SPI_MODE_MASTER;\n  hspi3.Init.Direction = SPI_DIRECTION_2LINES;\n  hspi3.Init.DataSize = SPI_DATASIZE_8BIT;\n  hspi3.Init.CLKPolarity = SPI_POLARITY_LOW;\n  hspi3.Init.CLKPhase = SPI_PHASE_1EDGE;\n  hspi3.Init.NSS = SPI_NSS_SOFT;\n  hspi3.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\n  hspi3.Init.FirstBit = SPI_FIRSTBIT_MSB;\n  hspi3.Init.TIMode = SPI_TIMODE_DISABLE;\n  hspi3.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n  hspi3.Init.CRCPolynomial = 10;\n  if (HAL_SPI_Init(&hspi3) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN SPI3_Init 2 */\n\n  /* USER CODE END SPI3_Init 2 */\n\n}\n\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(spiHandle->Instance==SPI1)\n  {\n  /* USER CODE BEGIN SPI1_MspInit 0 */\n\n  /* USER CODE END SPI1_MspInit 0 */\n    /* SPI1 clock enable */\n    __HAL_RCC_SPI1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**SPI1 GPIO Configuration\n    PA5     ------> SPI1_SCK\n    PA7     ------> SPI1_MOSI\n    PB4     ------> SPI1_MISO\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_4;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n  /* USER CODE BEGIN SPI1_MspInit 1 */\n\n  /* USER CODE END SPI1_MspInit 1 */\n  }\n  else if(spiHandle->Instance==SPI3)\n  {\n  /* USER CODE BEGIN SPI3_MspInit 0 */\n\n  /* USER CODE END SPI3_MspInit 0 */\n    /* SPI3 clock enable */\n    __HAL_RCC_SPI3_CLK_ENABLE();\n\n    __HAL_RCC_GPIOC_CLK_ENABLE();\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**SPI3 GPIO Configuration\n    PC10     ------> SPI3_SCK\n    PC11     ------> SPI3_MISO\n    PB5     ------> SPI3_MOSI\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_5;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* SPI3 interrupt Init */\n    HAL_NVIC_SetPriority(SPI3_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(SPI3_IRQn);\n  /* USER CODE BEGIN SPI3_MspInit 1 */\n\n  /* USER CODE END SPI3_MspInit 1 */\n  }\n}\n\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)\n{\n\n  if(spiHandle->Instance==SPI1)\n  {\n  /* USER CODE BEGIN SPI1_MspDeInit 0 */\n\n  /* USER CODE END SPI1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_SPI1_CLK_DISABLE();\n\n    /**SPI1 GPIO Configuration\n    PA5     ------> SPI1_SCK\n    PA7     ------> SPI1_MOSI\n    PB4     ------> SPI1_MISO\n    */\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_7);\n\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_4);\n\n  /* USER CODE BEGIN SPI1_MspDeInit 1 */\n\n  /* USER CODE END SPI1_MspDeInit 1 */\n  }\n  else if(spiHandle->Instance==SPI3)\n  {\n  /* USER CODE BEGIN SPI3_MspDeInit 0 */\n\n  /* USER CODE END SPI3_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_SPI3_CLK_DISABLE();\n\n    /**SPI3 GPIO Configuration\n    PC10     ------> SPI3_SCK\n    PC11     ------> SPI3_MISO\n    PB5     ------> SPI3_MOSI\n    */\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11);\n\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);\n\n    /* SPI3 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(SPI3_IRQn);\n  /* USER CODE BEGIN SPI3_MspDeInit 1 */\n\n  /* USER CODE END SPI3_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/stm32f4xx_hal_msp.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file         stm32f4xx_hal_msp.c\n  * @brief        This file provides code for the MSP Initialization\n  *               and de-Initialization codes.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* USER CODE BEGIN TD */\n\n/* USER CODE END TD */\n\n/* Private define ------------------------------------------------------------*/\n/* USER CODE BEGIN Define */\n\n/* USER CODE END Define */\n\n/* Private macro -------------------------------------------------------------*/\n/* USER CODE BEGIN Macro */\n\n/* USER CODE END Macro */\n\n/* Private variables ---------------------------------------------------------*/\n/* USER CODE BEGIN PV */\n\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\n/* USER CODE BEGIN PFP */\n\n/* USER CODE END PFP */\n\n/* External functions --------------------------------------------------------*/\n/* USER CODE BEGIN ExternalFunctions */\n\n/* USER CODE END ExternalFunctions */\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n/**\n  * Initializes the Global MSP.\n  */\nvoid HAL_MspInit(void)\n{\n  /* USER CODE BEGIN MspInit 0 */\n\n  /* USER CODE END MspInit 0 */\n\n  __HAL_RCC_SYSCFG_CLK_ENABLE();\n  __HAL_RCC_PWR_CLK_ENABLE();\n\n  /* System interrupt init*/\n  /* PendSV_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);\n\n  /* USER CODE BEGIN MspInit 1 */\n\n  /* USER CODE END MspInit 1 */\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/stm32f4xx_hal_timebase_tim.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_timebase_TIM.c\n  * @brief   HAL time base based on the hardware TIM.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n#include \"stm32f4xx_hal_tim.h\"\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\nTIM_HandleTypeDef        htim6;\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n\n/**\n  * @brief  This function configures the TIM6 as a time base source.\n  *         The time source is configured  to have 1ms time base with a dedicated\n  *         Tick interrupt priority.\n  * @note   This function is called  automatically at the beginning of program after\n  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().\n  * @param  TickPriority: Tick interrupt priority.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\n{\n  RCC_ClkInitTypeDef    clkconfig;\n  uint32_t              uwTimclock = 0;\n  uint32_t              uwPrescalerValue = 0;\n  uint32_t              pFLatency;\n  /*Configure the TIM6 IRQ priority */\n  HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0);\n\n  /* Enable the TIM6 global Interrupt */\n  HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);\n  /* Enable TIM6 clock */\n  __HAL_RCC_TIM6_CLK_ENABLE();\n\n  /* Get clock configuration */\n  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);\n\n  /* Compute TIM6 clock */\n  uwTimclock = 2*HAL_RCC_GetPCLK1Freq();\n  /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */\n  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);\n\n  /* Initialize TIM6 */\n  htim6.Instance = TIM6;\n\n  /* Initialize TIMx peripheral as follow:\n  + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.\n  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.\n  + ClockDivision = 0\n  + Counter direction = Up\n  */\n  htim6.Init.Period = (1000000U / 1000U) - 1U;\n  htim6.Init.Prescaler = uwPrescalerValue;\n  htim6.Init.ClockDivision = 0;\n  htim6.Init.CounterMode = TIM_COUNTERMODE_UP;\n  if(HAL_TIM_Base_Init(&htim6) == HAL_OK)\n  {\n    /* Start the TIM time Base generation in interrupt mode */\n    return HAL_TIM_Base_Start_IT(&htim6);\n  }\n\n  /* Return function status */\n  return HAL_ERROR;\n}\n\n/**\n  * @brief  Suspend Tick increment.\n  * @note   Disable the tick increment by disabling TIM6 update interrupt.\n  * @param  None\n  * @retval None\n  */\nvoid HAL_SuspendTick(void)\n{\n  /* Disable TIM6 update Interrupt */\n  __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE);\n}\n\n/**\n  * @brief  Resume Tick increment.\n  * @note   Enable the tick increment by Enabling TIM6 update interrupt.\n  * @param  None\n  * @retval None\n  */\nvoid HAL_ResumeTick(void)\n{\n  /* Enable TIM6 Update interrupt */\n  __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE);\n}\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/stm32f4xx_it.c",
    "content": "/* USER CODE BEGIN Header */\r\n/**\r\n  ******************************************************************************\r\n  * @file    stm32f4xx_it.c\r\n  * @brief   Interrupt Service Routines.\r\n  ******************************************************************************\r\n  * @attention\r\n  *\r\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\r\n  * All rights reserved.</center></h2>\r\n  *\r\n  * This software component is licensed by ST under BSD 3-Clause license,\r\n  * the \"License\"; You may not use this file except in compliance with the\r\n  * License. You may obtain a copy of the License at:\r\n  *                        opensource.org/licenses/BSD-3-Clause\r\n  *\r\n  ******************************************************************************\r\n  */\r\n/* USER CODE END Header */\r\n\r\n/* Includes ------------------------------------------------------------------*/\r\n#include \"main.h\"\r\n#include \"stm32f4xx_it.h\"\r\n/* Private includes ----------------------------------------------------------*/\r\n/* USER CODE BEGIN Includes */\r\n/* USER CODE END Includes */\r\n\r\n/* Private typedef -----------------------------------------------------------*/\r\n/* USER CODE BEGIN TD */\r\n\r\n/* USER CODE END TD */\r\n\r\n/* Private define ------------------------------------------------------------*/\r\n/* USER CODE BEGIN PD */\r\n\r\n/* USER CODE END PD */\r\n\r\n/* Private macro -------------------------------------------------------------*/\r\n/* USER CODE BEGIN PM */\r\n\r\n/* USER CODE END PM */\r\n\r\n/* Private variables ---------------------------------------------------------*/\r\n/* USER CODE BEGIN PV */\r\n\r\n/* USER CODE END PV */\r\n\r\n/* Private function prototypes -----------------------------------------------*/\r\n/* USER CODE BEGIN PFP */\r\n\r\n/* USER CODE END PFP */\r\n\r\n/* Private user code ---------------------------------------------------------*/\r\n/* USER CODE BEGIN 0 */\r\n\r\n/* USER CODE END 0 */\r\n\r\n/* External variables --------------------------------------------------------*/\r\nextern PCD_HandleTypeDef hpcd_USB_OTG_FS;\r\nextern DMA_HandleTypeDef hdma_adc1;\r\nextern ADC_HandleTypeDef hadc1;\r\nextern CAN_HandleTypeDef hcan1;\r\nextern CAN_HandleTypeDef hcan2;\r\nextern SPI_HandleTypeDef hspi3;\r\nextern TIM_HandleTypeDef htim2;\r\nextern TIM_HandleTypeDef htim3;\r\nextern TIM_HandleTypeDef htim7;\r\nextern TIM_HandleTypeDef htim10;\r\nextern TIM_HandleTypeDef htim11;\r\nextern TIM_HandleTypeDef htim13;\r\nextern TIM_HandleTypeDef htim14;\r\nextern DMA_HandleTypeDef hdma_uart4_rx;\r\nextern DMA_HandleTypeDef hdma_uart4_tx;\r\nextern DMA_HandleTypeDef hdma_uart5_rx;\r\nextern DMA_HandleTypeDef hdma_uart5_tx;\r\nextern UART_HandleTypeDef huart4;\r\nextern UART_HandleTypeDef huart5;\r\nextern TIM_HandleTypeDef htim6;\r\n\r\n/* USER CODE BEGIN EV */\r\n\r\n/* USER CODE END EV */\r\n\r\n/******************************************************************************/\r\n/*           Cortex-M4 Processor Interruption and Exception Handlers          */\r\n/******************************************************************************/\r\n/**\r\n  * @brief This function handles Non maskable interrupt.\r\n  */\r\nvoid NMI_Handler(void)\r\n{\r\n  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\r\n\r\n  /* USER CODE END NonMaskableInt_IRQn 0 */\r\n  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\r\n    while (1)\r\n    {\r\n    }\r\n  /* USER CODE END NonMaskableInt_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles Hard fault interrupt.\r\n  */\r\nvoid HardFault_Handler(void)\r\n{\r\n  /* USER CODE BEGIN HardFault_IRQn 0 */\r\n\r\n  /* USER CODE END HardFault_IRQn 0 */\r\n  while (1)\r\n  {\r\n    /* USER CODE BEGIN W1_HardFault_IRQn 0 */\r\n    /* USER CODE END W1_HardFault_IRQn 0 */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief This function handles Memory management fault.\r\n  */\r\nvoid MemManage_Handler(void)\r\n{\r\n  /* USER CODE BEGIN MemoryManagement_IRQn 0 */\r\n\r\n  /* USER CODE END MemoryManagement_IRQn 0 */\r\n  while (1)\r\n  {\r\n    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */\r\n    /* USER CODE END W1_MemoryManagement_IRQn 0 */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief This function handles Pre-fetch fault, memory access fault.\r\n  */\r\nvoid BusFault_Handler(void)\r\n{\r\n  /* USER CODE BEGIN BusFault_IRQn 0 */\r\n\r\n  /* USER CODE END BusFault_IRQn 0 */\r\n  while (1)\r\n  {\r\n    /* USER CODE BEGIN W1_BusFault_IRQn 0 */\r\n    /* USER CODE END W1_BusFault_IRQn 0 */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief This function handles Undefined instruction or illegal state.\r\n  */\r\nvoid UsageFault_Handler(void)\r\n{\r\n  /* USER CODE BEGIN UsageFault_IRQn 0 */\r\n\r\n  /* USER CODE END UsageFault_IRQn 0 */\r\n  while (1)\r\n  {\r\n    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\r\n    /* USER CODE END W1_UsageFault_IRQn 0 */\r\n  }\r\n}\r\n\r\n/**\r\n  * @brief This function handles Debug monitor.\r\n  */\r\nvoid DebugMon_Handler(void)\r\n{\r\n  /* USER CODE BEGIN DebugMonitor_IRQn 0 */\r\n\r\n  /* USER CODE END DebugMonitor_IRQn 0 */\r\n  /* USER CODE BEGIN DebugMonitor_IRQn 1 */\r\n\r\n  /* USER CODE END DebugMonitor_IRQn 1 */\r\n}\r\n\r\n/******************************************************************************/\r\n/* STM32F4xx Peripheral Interrupt Handlers                                    */\r\n/* Add here the Interrupt Handlers for the used peripherals.                  */\r\n/* For the available peripheral interrupt handler names,                      */\r\n/* please refer to the startup file (startup_stm32f4xx.s).                    */\r\n/******************************************************************************/\r\n\r\n/**\r\n  * @brief This function handles DMA1 stream0 global interrupt.\r\n  */\r\nvoid DMA1_Stream0_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN DMA1_Stream0_IRQn 0 */\r\n\r\n  /* USER CODE END DMA1_Stream0_IRQn 0 */\r\n  HAL_DMA_IRQHandler(&hdma_uart5_rx);\r\n  /* USER CODE BEGIN DMA1_Stream0_IRQn 1 */\r\n\r\n  /* USER CODE END DMA1_Stream0_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles DMA1 stream2 global interrupt.\r\n  */\r\nvoid DMA1_Stream2_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN DMA1_Stream2_IRQn 0 */\r\n\r\n  /* USER CODE END DMA1_Stream2_IRQn 0 */\r\n  HAL_DMA_IRQHandler(&hdma_uart4_rx);\r\n  /* USER CODE BEGIN DMA1_Stream2_IRQn 1 */\r\n\r\n  /* USER CODE END DMA1_Stream2_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles DMA1 stream4 global interrupt.\r\n  */\r\nvoid DMA1_Stream4_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN DMA1_Stream4_IRQn 0 */\r\n\r\n  /* USER CODE END DMA1_Stream4_IRQn 0 */\r\n  HAL_DMA_IRQHandler(&hdma_uart4_tx);\r\n  /* USER CODE BEGIN DMA1_Stream4_IRQn 1 */\r\n\r\n  /* USER CODE END DMA1_Stream4_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles ADC1, ADC2 and ADC3 global interrupts.\r\n  */\r\nvoid ADC_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN ADC_IRQn 0 */\r\n\r\n  /* USER CODE END ADC_IRQn 0 */\r\n  HAL_ADC_IRQHandler(&hadc1);\r\n  /* USER CODE BEGIN ADC_IRQn 1 */\r\n\r\n  /* USER CODE END ADC_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN1 TX interrupts.\r\n  */\r\nvoid CAN1_TX_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN1_TX_IRQn 0 */\r\n\r\n  /* USER CODE END CAN1_TX_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan1);\r\n  /* USER CODE BEGIN CAN1_TX_IRQn 1 */\r\n\r\n  /* USER CODE END CAN1_TX_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN1 RX0 interrupts.\r\n  */\r\nvoid CAN1_RX0_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN1_RX0_IRQn 0 */\r\n    if (( READ_REG(hcan1.Instance->IER) & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)\r\n    {\r\n        /* Check if message is still pending */\r\n        if ((hcan1.Instance->RF0R & CAN_RF0R_FMP0) != 0U)\r\n        {\r\n            /* Call weak (surcharged) callback */\r\n            HAL_CAN_RxFifo0MsgPendingCallback(&hcan1);\r\n        }\r\n    }\r\n    return;\r\n  /* USER CODE END CAN1_RX0_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan1);\r\n  /* USER CODE BEGIN CAN1_RX0_IRQn 1 */\r\n\r\n  /* USER CODE END CAN1_RX0_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN1 RX1 interrupt.\r\n  */\r\nvoid CAN1_RX1_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN1_RX1_IRQn 0 */\r\n\r\n  /* USER CODE END CAN1_RX1_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan1);\r\n  /* USER CODE BEGIN CAN1_RX1_IRQn 1 */\r\n\r\n  /* USER CODE END CAN1_RX1_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN1 SCE interrupt.\r\n  */\r\nvoid CAN1_SCE_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN1_SCE_IRQn 0 */\r\n\r\n  /* USER CODE END CAN1_SCE_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan1);\r\n  /* USER CODE BEGIN CAN1_SCE_IRQn 1 */\r\n\r\n  /* USER CODE END CAN1_SCE_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM1 update interrupt and TIM10 global interrupt.\r\n  */\r\nvoid TIM1_UP_TIM10_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */\r\n\r\n  /* USER CODE END TIM1_UP_TIM10_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim10);\r\n  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */\r\n\r\n  /* USER CODE END TIM1_UP_TIM10_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM1 trigger and commutation interrupts and TIM11 global interrupt.\r\n  */\r\nvoid TIM1_TRG_COM_TIM11_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 0 */\r\n\r\n  /* USER CODE END TIM1_TRG_COM_TIM11_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim11);\r\n  /* USER CODE BEGIN TIM1_TRG_COM_TIM11_IRQn 1 */\r\n\r\n  /* USER CODE END TIM1_TRG_COM_TIM11_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM2 global interrupt.\r\n  */\r\nvoid TIM2_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM2_IRQn 0 */\r\n\r\n  /* USER CODE END TIM2_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim2);\r\n  /* USER CODE BEGIN TIM2_IRQn 1 */\r\n\r\n  /* USER CODE END TIM2_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM3 global interrupt.\r\n  */\r\nvoid TIM3_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM3_IRQn 0 */\r\n\r\n  /* USER CODE END TIM3_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim3);\r\n  /* USER CODE BEGIN TIM3_IRQn 1 */\r\n\r\n  /* USER CODE END TIM3_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM8 update interrupt and TIM13 global interrupt.\r\n  */\r\nvoid TIM8_UP_TIM13_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 0 */\r\n\r\n  /* USER CODE END TIM8_UP_TIM13_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim13);\r\n  /* USER CODE BEGIN TIM8_UP_TIM13_IRQn 1 */\r\n\r\n  /* USER CODE END TIM8_UP_TIM13_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM8 trigger and commutation interrupts and TIM14 global interrupt.\r\n  */\r\nvoid TIM8_TRG_COM_TIM14_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 0 */\r\n\r\n  /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim14);\r\n  /* USER CODE BEGIN TIM8_TRG_COM_TIM14_IRQn 1 */\r\n\r\n  /* USER CODE END TIM8_TRG_COM_TIM14_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles DMA1 stream7 global interrupt.\r\n  */\r\nvoid DMA1_Stream7_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN DMA1_Stream7_IRQn 0 */\r\n\r\n  /* USER CODE END DMA1_Stream7_IRQn 0 */\r\n  HAL_DMA_IRQHandler(&hdma_uart5_tx);\r\n  /* USER CODE BEGIN DMA1_Stream7_IRQn 1 */\r\n\r\n  /* USER CODE END DMA1_Stream7_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles SPI3 global interrupt.\r\n  */\r\nvoid SPI3_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN SPI3_IRQn 0 */\r\n\r\n  /* USER CODE END SPI3_IRQn 0 */\r\n  HAL_SPI_IRQHandler(&hspi3);\r\n  /* USER CODE BEGIN SPI3_IRQn 1 */\r\n\r\n  /* USER CODE END SPI3_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles UART4 global interrupt.\r\n  */\r\nvoid UART4_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN UART4_IRQn 0 */\r\n\r\n  /* USER CODE END UART4_IRQn 0 */\r\n  HAL_UART_IRQHandler(&huart4);\r\n  /* USER CODE BEGIN UART4_IRQn 1 */\r\n\r\n  /* USER CODE END UART4_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles UART5 global interrupt.\r\n  */\r\nvoid UART5_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN UART5_IRQn 0 */\r\n\r\n  /* USER CODE END UART5_IRQn 0 */\r\n  HAL_UART_IRQHandler(&huart5);\r\n  /* USER CODE BEGIN UART5_IRQn 1 */\r\n\r\n  /* USER CODE END UART5_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts.\r\n  */\r\nvoid TIM6_DAC_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM6_DAC_IRQn 0 */\r\n\r\n  /* USER CODE END TIM6_DAC_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim6);\r\n  /* USER CODE BEGIN TIM6_DAC_IRQn 1 */\r\n\r\n  /* USER CODE END TIM6_DAC_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles TIM7 global interrupt.\r\n  */\r\nvoid TIM7_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN TIM7_IRQn 0 */\r\n\r\n  /* USER CODE END TIM7_IRQn 0 */\r\n  HAL_TIM_IRQHandler(&htim7);\r\n  /* USER CODE BEGIN TIM7_IRQn 1 */\r\n\r\n  /* USER CODE END TIM7_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles DMA2 stream0 global interrupt.\r\n  */\r\nvoid DMA2_Stream0_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */\r\n\r\n  /* USER CODE END DMA2_Stream0_IRQn 0 */\r\n  HAL_DMA_IRQHandler(&hdma_adc1);\r\n  /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */\r\n\r\n  /* USER CODE END DMA2_Stream0_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN2 TX interrupts.\r\n  */\r\nvoid CAN2_TX_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN2_TX_IRQn 0 */\r\n\r\n  /* USER CODE END CAN2_TX_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan2);\r\n  /* USER CODE BEGIN CAN2_TX_IRQn 1 */\r\n\r\n  /* USER CODE END CAN2_TX_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN2 RX0 interrupts.\r\n  */\r\nvoid CAN2_RX0_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN2_RX0_IRQn 0 */\r\n\r\n  /* USER CODE END CAN2_RX0_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan2);\r\n  /* USER CODE BEGIN CAN2_RX0_IRQn 1 */\r\n\r\n  /* USER CODE END CAN2_RX0_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN2 RX1 interrupt.\r\n  */\r\nvoid CAN2_RX1_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN2_RX1_IRQn 0 */\r\n\r\n  /* USER CODE END CAN2_RX1_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan2);\r\n  /* USER CODE BEGIN CAN2_RX1_IRQn 1 */\r\n\r\n  /* USER CODE END CAN2_RX1_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles CAN2 SCE interrupt.\r\n  */\r\nvoid CAN2_SCE_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN CAN2_SCE_IRQn 0 */\r\n\r\n  /* USER CODE END CAN2_SCE_IRQn 0 */\r\n  HAL_CAN_IRQHandler(&hcan2);\r\n  /* USER CODE BEGIN CAN2_SCE_IRQn 1 */\r\n\r\n  /* USER CODE END CAN2_SCE_IRQn 1 */\r\n}\r\n\r\n/**\r\n  * @brief This function handles USB On The Go FS global interrupt.\r\n  */\r\nvoid OTG_FS_IRQHandler(void)\r\n{\r\n  /* USER CODE BEGIN OTG_FS_IRQn 0 */\r\n\r\n  /* USER CODE END OTG_FS_IRQn 0 */\r\n  HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS);\r\n  /* USER CODE BEGIN OTG_FS_IRQn 1 */\r\n\r\n  /* USER CODE END OTG_FS_IRQn 1 */\r\n}\r\n\r\n/* USER CODE BEGIN 1 */\r\n\r\n/* USER CODE END 1 */\r\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/syscalls.c",
    "content": "/**\n*****************************************************************************\n**\n**  File        : syscalls.c\n**\n**  Author\t\t: Auto-generated by System workbench for STM32\n**\n**  Abstract    : System Workbench Minimal System calls file\n**\n** \t\t          For more information about which c-functions\n**                need which of these lowlevel functions\n**                please consult the Newlib libc-manual\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Distribution: The file is distributed as is, without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and/or other materials provided with the distribution.\n**   3. Neither the name of STMicroelectronics nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*/\n\n/* Includes */\n#include <sys/stat.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <stdio.h>\n#include <signal.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/times.h>\n\n\n/* Variables */\n//#undef errno\nextern int errno;\nextern int __io_putchar(int ch) __attribute__((weak));\nextern int __io_getchar(void) __attribute__((weak));\n\nregister char * stack_ptr asm(\"sp\");\n\nchar *__env[1] = { 0 };\nchar **environ = __env;\n\n\n/* Functions */\nvoid initialise_monitor_handles()\n{\n}\n\nint _getpid(void)\n{\n\treturn 1;\n}\n\nint _kill(int pid, int sig)\n{\n\terrno = EINVAL;\n\treturn -1;\n}\n\nvoid _exit (int status)\n{\n\t_kill(status, -1);\n\twhile (1) {}\t\t/* Make sure we hang here */\n}\n\n__attribute__((weak)) int _read(int file, char *ptr, int len)\n{\n\tint DataIdx;\n\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\n\t{\n\t\t*ptr++ = __io_getchar();\n\t}\n\nreturn len;\n}\n\n__attribute__((weak)) int _write(int file, char *ptr, int len)\n{\n\tint DataIdx;\n\n\tfor (DataIdx = 0; DataIdx < len; DataIdx++)\n\t{\n\t\t__io_putchar(*ptr++);\n\t}\n\treturn len;\n}\n\ncaddr_t _sbrk(int incr)\n{\n\textern char end asm(\"end\");\n\tstatic char *heap_end;\n\tchar *prev_heap_end;\n\n\tif (heap_end == 0)\n\t\theap_end = &end;\n\n\tprev_heap_end = heap_end;\n\tif (heap_end + incr > stack_ptr)\n\t{\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\n//\t\tabort();\n\t\terrno = ENOMEM;\n\t\treturn (caddr_t) -1;\n\t}\n\n\theap_end += incr;\n\n\treturn (caddr_t) prev_heap_end;\n}\n\nint _close(int file)\n{\n\treturn -1;\n}\n\n\nint _fstat(int file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _isatty(int file)\n{\n\treturn 1;\n}\n\nint _lseek(int file, int ptr, int dir)\n{\n\treturn 0;\n}\n\nint _open(char *path, int flags, ...)\n{\n\t/* Pretend like we always fail */\n\treturn -1;\n}\n\nint _wait(int *status)\n{\n\terrno = ECHILD;\n\treturn -1;\n}\n\nint _unlink(char *name)\n{\n\terrno = ENOENT;\n\treturn -1;\n}\n\nint _times(struct tms *buf)\n{\n\treturn -1;\n}\n\nint _stat(char *file, struct stat *st)\n{\n\tst->st_mode = S_IFCHR;\n\treturn 0;\n}\n\nint _link(char *old, char *new)\n{\n\terrno = EMLINK;\n\treturn -1;\n}\n\nint _fork(void)\n{\n\terrno = EAGAIN;\n\treturn -1;\n}\n\nint _execve(char *name, char **argv, char **env)\n{\n\terrno = ENOMEM;\n\treturn -1;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/system_stm32f4xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.c\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.\n  *\n  *   This file provides two functions and one global variable to be called from \n  *   user application:\n  *      - SystemInit(): This function is called at startup just after reset and \n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32f4xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick \n  *                                  timer or configure other parameters.\n  *                                     \n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Includes\n  * @{\n  */\n\n\n#include \"stm32f4xx.h\"\n\n#if !defined  (HSE_VALUE)\n#define HSE_VALUE    ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n#define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Defines\n  * @{\n  */\n\n/************************* Miscellaneous Configuration ************************/\n/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\\\n || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\n/* #define DATA_IN_ExtSRAM */\n#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\\\n          STM32F412Zx || STM32F412Vx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/* #define DATA_IN_ExtSDRAM */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\\\n          STM32F479xx */\n\n/* Note: Following vector table addresses must be defined in line with linker\n         configuration. */\n/*!< Uncomment the following line if you need to relocate the vector table\n     anywhere in Flash or Sram, else the vector table is kept at the automatic\n     remap of boot address selected */\n/* #define USER_VECT_TAB_ADDRESS */\n\n#if defined(USER_VECT_TAB_ADDRESS)\n/*!< Uncomment the following line if you need to relocate your vector Table\n     in Sram else user remap will be done in Flash. */\n/* #define VECT_TAB_SRAM */\n#if defined(VECT_TAB_SRAM)\n#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.\n                                                     This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.\n                                                     This value must be a multiple of 0x200. */\n#else\n#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.\n                                                     This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.\n                                                     This value must be a multiple of 0x200. */\n#endif /* VECT_TAB_SRAM */\n#endif /* USER_VECT_TAB_ADDRESS */\n/******************************************************************************/\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Variables\n  * @{\n  */\n/* This variable is updated in three ways:\n    1) by calling CMSIS function SystemCoreClockUpdate()\n    2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n    3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency\n       Note: If you use this function to configure the system clock; then there\n             is no need to call the 2 first functions listed above, since SystemCoreClock\n             variable is updated automatically.\n*/\nuint32_t SystemCoreClock = 16000000;\nconst uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\nconst uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\nstatic void SystemInit_ExtMemCtl(void);\n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system\n  *         Initialize the FPU setting, vector table location and External memory\n  *         configuration.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit(void)\n{\n    /* FPU settings ------------------------------------------------------------*/\n#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\n    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */\n#endif\n\n#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n    SystemInit_ExtMemCtl();\n#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */\n\n    /* Configure the Vector Table location -------------------------------------*/\n#if defined(USER_VECT_TAB_ADDRESS)\n    SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */\n#endif /* USER_VECT_TAB_ADDRESS */\n}\n\n/**\n   * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *\n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.\n  *\n  * @note   - The system frequency computed by this function is not the real\n  *           frequency in the chip. It is calculated based on the predefined\n  *           constant and the selected clock source:\n  *\n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *\n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *\n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)\n  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  *\n  *         (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *             16 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.\n  *\n  *         (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value\n  *              depends on the application requirements), user has to ensure that HSE_VALUE\n  *              is same as the real frequency of the crystal used. Otherwise, this function\n  *              may have wrong result.\n  *\n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  *\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate(void)\n{\n    uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;\n\n    /* Get SYSCLK source -------------------------------------------------------*/\n    tmp = RCC->CFGR & RCC_CFGR_SWS;\n\n    switch (tmp)\n    {\n        case 0x00:  /* HSI used as system clock source */\n            SystemCoreClock = HSI_VALUE;\n            break;\n        case 0x04:  /* HSE used as system clock source */\n            SystemCoreClock = HSE_VALUE;\n            break;\n        case 0x08:  /* PLL used as system clock source */\n\n            /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N\n               SYSCLK = PLL_VCO / PLL_P\n               */\n            pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;\n            pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n\n            if (pllsource != 0)\n            {\n                /* HSE used as PLL clock source */\n                pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n            }\n            else\n            {\n                /* HSI used as PLL clock source */\n                pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);\n            }\n\n            pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;\n            SystemCoreClock = pllvco/pllp;\n            break;\n        default:\n            SystemCoreClock = HSI_VALUE;\n            break;\n    }\n    /* Compute HCLK frequency --------------------------------------------------*/\n    /* Get HCLK prescaler */\n    tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];\n    /* HCLK frequency */\n    SystemCoreClock >>= tmp;\n}\n\n#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Setup the external memory controller.\n  *         Called in startup_stm32f4xx.s before jump to main.\n  *         This function configures the external memories (SRAM/SDRAM)\n  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit_ExtMemCtl(void)\n{\n  __IO uint32_t tmp = 0x00;\n\n  register uint32_t tmpreg = 0, timeout = 0xFFFF;\n  register __IO uint32_t index;\n\n  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */\n  RCC->AHB1ENR |= 0x000001F8;\n\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\n  \n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x00CCC0CC;\n  GPIOD->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xAAAA0A8A;\n  /* Configure PDx pins speed to 100 MHz */  \n  GPIOD->OSPEEDR = 0xFFFF0FCF;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00CC0CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA828A;\n  /* Configure PEx pins speed to 100 MHz */ \n  GPIOE->OSPEEDR = 0xFFFFC3CF;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n  \n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0xCCCCCCCC;\n  GPIOF->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA800AAA;\n  /* Configure PFx pins speed to 50 MHz */ \n  GPIOF->OSPEEDR = 0xAA800AAA;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0xCCCCCCCC;\n  GPIOG->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0xAAAAAAAA;\n  /* Configure PGx pins speed to 50 MHz */ \n  GPIOG->OSPEEDR = 0xAAAAAAAA;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n  \n  /* Connect PHx pins to FMC Alternate function */\n  GPIOH->AFR[0]  = 0x00C0CC00;\n  GPIOH->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PHx pins in Alternate function mode */ \n  GPIOH->MODER   = 0xAAAA08A0;\n  /* Configure PHx pins speed to 50 MHz */ \n  GPIOH->OSPEEDR = 0xAAAA08A0;\n  /* Configure PHx pins Output type to push-pull */  \n  GPIOH->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PHx pins */ \n  GPIOH->PUPDR   = 0x00000000;\n  \n  /* Connect PIx pins to FMC Alternate function */\n  GPIOI->AFR[0]  = 0xCCCCCCCC;\n  GPIOI->AFR[1]  = 0x00000CC0;\n  /* Configure PIx pins in Alternate function mode */ \n  GPIOI->MODER   = 0x0028AAAA;\n  /* Configure PIx pins speed to 50 MHz */ \n  GPIOI->OSPEEDR = 0x0028AAAA;\n  /* Configure PIx pins Output type to push-pull */  \n  GPIOI->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PIx pins */ \n  GPIOI->PUPDR   = 0x00000000;\n  \n/*-- FMC Configuration -------------------------------------------------------*/\n  /* Enable the FMC interface clock */\n  RCC->AHB3ENR |= 0x00000001;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n\n  FMC_Bank5_6->SDCR[0] = 0x000019E4;\n  FMC_Bank5_6->SDTR[0] = 0x01115351;      \n  \n  /* SDRAM initialization sequence */\n  /* Clock enable command */\n  FMC_Bank5_6->SDCMR = 0x00000011; \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n\n  /* Delay */\n  for (index = 0; index<1000; index++);\n  \n  /* PALL command */\n  FMC_Bank5_6->SDCMR = 0x00000012;           \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n  \n  /* Auto refresh command */\n  FMC_Bank5_6->SDCMR = 0x00000073;\n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n \n  /* MRD register program */\n  FMC_Bank5_6->SDCMR = 0x00046014;\n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  } \n  \n  /* Set refresh count */\n  tmpreg = FMC_Bank5_6->SDRTR;\n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));\n  \n  /* Disable write protection */\n  tmpreg = FMC_Bank5_6->SDCR[0]; \n  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001011;\n  FMC_Bank1->BTCR[3]  = 0x00000201;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ \n#if defined(STM32F469xx) || defined(STM32F479xx)\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001091;\n  FMC_Bank1->BTCR[3]  = 0x00110212;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F469xx || STM32F479xx */\n\n  (void)(tmp); \n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)\n/**\n  * @brief  Setup the external memory controller.\n  *         Called in startup_stm32f4xx.s before jump to main.\n  *         This function configures the external memories (SRAM/SDRAM)\n  *         This SRAM/SDRAM will be used as program data memory (including heap and stack).\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit_ExtMemCtl(void)\n{\n  __IO uint32_t tmp = 0x00;\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#if defined (DATA_IN_ExtSDRAM)\n  register uint32_t tmpreg = 0, timeout = 0xFFFF;\n  register __IO uint32_t index;\n\n#if defined(STM32F446xx)\n  /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface\n      clock */\n  RCC->AHB1ENR |= 0x0000007D;\n#else\n  /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface \n      clock */\n  RCC->AHB1ENR |= 0x000001F8;\n#endif /* STM32F446xx */  \n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\n  \n#if defined(STM32F446xx)\n  /* Connect PAx pins to FMC Alternate function */\n  GPIOA->AFR[0]  |= 0xC0000000;\n  GPIOA->AFR[1]  |= 0x00000000;\n  /* Configure PDx pins in Alternate function mode */\n  GPIOA->MODER   |= 0x00008000;\n  /* Configure PDx pins speed to 50 MHz */\n  GPIOA->OSPEEDR |= 0x00008000;\n  /* Configure PDx pins Output type to push-pull */\n  GPIOA->OTYPER  |= 0x00000000;\n  /* No pull-up, pull-down for PDx pins */\n  GPIOA->PUPDR   |= 0x00000000;\n\n  /* Connect PCx pins to FMC Alternate function */\n  GPIOC->AFR[0]  |= 0x00CC0000;\n  GPIOC->AFR[1]  |= 0x00000000;\n  /* Configure PDx pins in Alternate function mode */\n  GPIOC->MODER   |= 0x00000A00;\n  /* Configure PDx pins speed to 50 MHz */\n  GPIOC->OSPEEDR |= 0x00000A00;\n  /* Configure PDx pins Output type to push-pull */\n  GPIOC->OTYPER  |= 0x00000000;\n  /* No pull-up, pull-down for PDx pins */\n  GPIOC->PUPDR   |= 0x00000000;\n#endif /* STM32F446xx */\n\n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x000000CC;\n  GPIOD->AFR[1]  = 0xCC000CCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xA02A000A;\n  /* Configure PDx pins speed to 50 MHz */  \n  GPIOD->OSPEEDR = 0xA02A000A;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00000CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA800A;\n  /* Configure PEx pins speed to 50 MHz */ \n  GPIOE->OSPEEDR = 0xAAAA800A;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n\n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0xCCCCCCCC;\n  GPIOF->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA800AAA;\n  /* Configure PFx pins speed to 50 MHz */ \n  GPIOF->OSPEEDR = 0xAA800AAA;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0xCCCCCCCC;\n  GPIOG->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0xAAAAAAAA;\n  /* Configure PGx pins speed to 50 MHz */ \n  GPIOG->OSPEEDR = 0xAAAAAAAA;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx)  \n  /* Connect PHx pins to FMC Alternate function */\n  GPIOH->AFR[0]  = 0x00C0CC00;\n  GPIOH->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PHx pins in Alternate function mode */ \n  GPIOH->MODER   = 0xAAAA08A0;\n  /* Configure PHx pins speed to 50 MHz */ \n  GPIOH->OSPEEDR = 0xAAAA08A0;\n  /* Configure PHx pins Output type to push-pull */  \n  GPIOH->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PHx pins */ \n  GPIOH->PUPDR   = 0x00000000;\n  \n  /* Connect PIx pins to FMC Alternate function */\n  GPIOI->AFR[0]  = 0xCCCCCCCC;\n  GPIOI->AFR[1]  = 0x00000CC0;\n  /* Configure PIx pins in Alternate function mode */ \n  GPIOI->MODER   = 0x0028AAAA;\n  /* Configure PIx pins speed to 50 MHz */ \n  GPIOI->OSPEEDR = 0x0028AAAA;\n  /* Configure PIx pins Output type to push-pull */  \n  GPIOI->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PIx pins */ \n  GPIOI->PUPDR   = 0x00000000;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n  \n/*-- FMC Configuration -------------------------------------------------------*/\n  /* Enable the FMC interface clock */\n  RCC->AHB3ENR |= 0x00000001;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n\n  /* Configure and enable SDRAM bank1 */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCR[0] = 0x00001954;\n#else  \n  FMC_Bank5_6->SDCR[0] = 0x000019E4;\n#endif /* STM32F446xx */\n  FMC_Bank5_6->SDTR[0] = 0x01115351;      \n  \n  /* SDRAM initialization sequence */\n  /* Clock enable command */\n  FMC_Bank5_6->SDCMR = 0x00000011; \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n\n  /* Delay */\n  for (index = 0; index<1000; index++);\n  \n  /* PALL command */\n  FMC_Bank5_6->SDCMR = 0x00000012;           \n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n  \n  /* Auto refresh command */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCMR = 0x000000F3;\n#else  \n  FMC_Bank5_6->SDCMR = 0x00000073;\n#endif /* STM32F446xx */\n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  }\n \n  /* MRD register program */\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDCMR = 0x00044014;\n#else  \n  FMC_Bank5_6->SDCMR = 0x00046014;\n#endif /* STM32F446xx */\n  tmpreg = FMC_Bank5_6->SDSR & 0x00000020;\n  timeout = 0xFFFF;\n  while((tmpreg != 0) && (timeout-- > 0))\n  {\n    tmpreg = FMC_Bank5_6->SDSR & 0x00000020; \n  } \n  \n  /* Set refresh count */\n  tmpreg = FMC_Bank5_6->SDRTR;\n#if defined(STM32F446xx)\n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));\n#else    \n  FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));\n#endif /* STM32F446xx */\n  \n  /* Disable write protection */\n  tmpreg = FMC_Bank5_6->SDCR[0]; \n  FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);\n#endif /* DATA_IN_ExtSDRAM */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\\\n || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\\\n || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)\n\n#if defined(DATA_IN_ExtSRAM)\n/*-- GPIOs Configuration -----------------------------------------------------*/\n   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */\n  RCC->AHB1ENR   |= 0x00000078;\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\n  \n  /* Connect PDx pins to FMC Alternate function */\n  GPIOD->AFR[0]  = 0x00CCC0CC;\n  GPIOD->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PDx pins in Alternate function mode */  \n  GPIOD->MODER   = 0xAAAA0A8A;\n  /* Configure PDx pins speed to 100 MHz */  \n  GPIOD->OSPEEDR = 0xFFFF0FCF;\n  /* Configure PDx pins Output type to push-pull */  \n  GPIOD->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PDx pins */ \n  GPIOD->PUPDR   = 0x00000000;\n\n  /* Connect PEx pins to FMC Alternate function */\n  GPIOE->AFR[0]  = 0xC00CC0CC;\n  GPIOE->AFR[1]  = 0xCCCCCCCC;\n  /* Configure PEx pins in Alternate function mode */ \n  GPIOE->MODER   = 0xAAAA828A;\n  /* Configure PEx pins speed to 100 MHz */ \n  GPIOE->OSPEEDR = 0xFFFFC3CF;\n  /* Configure PEx pins Output type to push-pull */  \n  GPIOE->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PEx pins */ \n  GPIOE->PUPDR   = 0x00000000;\n\n  /* Connect PFx pins to FMC Alternate function */\n  GPIOF->AFR[0]  = 0x00CCCCCC;\n  GPIOF->AFR[1]  = 0xCCCC0000;\n  /* Configure PFx pins in Alternate function mode */   \n  GPIOF->MODER   = 0xAA000AAA;\n  /* Configure PFx pins speed to 100 MHz */ \n  GPIOF->OSPEEDR = 0xFF000FFF;\n  /* Configure PFx pins Output type to push-pull */  \n  GPIOF->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PFx pins */ \n  GPIOF->PUPDR   = 0x00000000;\n\n  /* Connect PGx pins to FMC Alternate function */\n  GPIOG->AFR[0]  = 0x00CCCCCC;\n  GPIOG->AFR[1]  = 0x000000C0;\n  /* Configure PGx pins in Alternate function mode */ \n  GPIOG->MODER   = 0x00085AAA;\n  /* Configure PGx pins speed to 100 MHz */ \n  GPIOG->OSPEEDR = 0x000CAFFF;\n  /* Configure PGx pins Output type to push-pull */  \n  GPIOG->OTYPER  = 0x00000000;\n  /* No pull-up, pull-down for PGx pins */ \n  GPIOG->PUPDR   = 0x00000000;\n  \n/*-- FMC/FSMC Configuration --------------------------------------------------*/\n  /* Enable the FMC/FSMC interface clock */\n  RCC->AHB3ENR         |= 0x00000001;\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001011;\n  FMC_Bank1->BTCR[3]  = 0x00000201;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ \n#if defined(STM32F469xx) || defined(STM32F479xx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FMC_Bank1->BTCR[2]  = 0x00001091;\n  FMC_Bank1->BTCR[3]  = 0x00110212;\n  FMC_Bank1E->BWTR[2] = 0x0fffffff;\n#endif /* STM32F469xx || STM32F479xx */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\\\n   || defined(STM32F412Zx) || defined(STM32F412Vx)\n  /* Delay after an RCC peripheral clock enabling */\n  tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\n  /* Configure and enable Bank1_SRAM2 */\n  FSMC_Bank1->BTCR[2]  = 0x00001011;\n  FSMC_Bank1->BTCR[3]  = 0x00000201;\n  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */\n\n#endif /* DATA_IN_ExtSRAM */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\\\n          STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx  */ \n  (void)(tmp); \n}\n#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/tim.c",
    "content": "/**\n  ******************************************************************************\n  * @file    tim.c\n  * @brief   This file provides code for the configuration\n  *          of the TIM instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"tim.h\"\n\n/* USER CODE BEGIN 0 */\nvolatile int64_t encCntLoop[2];\n\n/* USER CODE END 0 */\n\nTIM_HandleTypeDef htim2;\nTIM_HandleTypeDef htim3;\nTIM_HandleTypeDef htim7;\nTIM_HandleTypeDef htim9;\nTIM_HandleTypeDef htim10;\nTIM_HandleTypeDef htim11;\nTIM_HandleTypeDef htim12;\nTIM_HandleTypeDef htim13;\nTIM_HandleTypeDef htim14;\n\n/* TIM2 init function */\nvoid MX_TIM2_Init(void)\n{\n\n  /* USER CODE BEGIN TIM2_Init 0 */\n\n  /* USER CODE END TIM2_Init 0 */\n\n  TIM_Encoder_InitTypeDef sConfig = {0};\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n  /* USER CODE BEGIN TIM2_Init 1 */\n\n  /* USER CODE END TIM2_Init 1 */\n  htim2.Instance = TIM2;\n  htim2.Init.Prescaler = 0;\n  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim2.Init.Period = 65535;\n  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  sConfig.EncoderMode = TIM_ENCODERMODE_TI12;\n  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;\n  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;\n  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;\n  sConfig.IC1Filter = 4;\n  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;\n  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;\n  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;\n  sConfig.IC2Filter = 4;\n  if (HAL_TIM_Encoder_Init(&htim2, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM2_Init 2 */\n    TIM2->CNT = 0;\n    TIM2->SR = TIM2->SR & 0xFE; // clear flag\n\n  /* USER CODE END TIM2_Init 2 */\n\n}\n/* TIM3 init function */\nvoid MX_TIM3_Init(void)\n{\n\n  /* USER CODE BEGIN TIM3_Init 0 */\n\n  /* USER CODE END TIM3_Init 0 */\n\n  TIM_Encoder_InitTypeDef sConfig = {0};\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n  /* USER CODE BEGIN TIM3_Init 1 */\n\n  /* USER CODE END TIM3_Init 1 */\n  htim3.Instance = TIM3;\n  htim3.Init.Prescaler = 0;\n  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim3.Init.Period = 65535;\n  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  sConfig.EncoderMode = TIM_ENCODERMODE_TI12;\n  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;\n  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;\n  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;\n  sConfig.IC1Filter = 4;\n  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;\n  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;\n  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;\n  sConfig.IC2Filter = 4;\n  if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM3_Init 2 */\n    TIM3->CNT = 0;\n    TIM3->SR = TIM3->SR & 0xFE; // clear flag\n\n  /* USER CODE END TIM3_Init 2 */\n\n}\n/* TIM7 init function */\nvoid MX_TIM7_Init(void)\n{\n\n  /* USER CODE BEGIN TIM7_Init 0 */\n\n  /* USER CODE END TIM7_Init 0 */\n\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n  /* USER CODE BEGIN TIM7_Init 1 */\n\n  /* USER CODE END TIM7_Init 1 */\n  htim7.Instance = TIM7;\n  htim7.Init.Prescaler = 83;\n  htim7.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim7.Init.Period = 9999;\n  htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;\n  if (HAL_TIM_Base_Init(&htim7) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim7, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM7_Init 2 */\n\n  /* USER CODE END TIM7_Init 2 */\n\n}\n/* TIM9 init function */\nvoid MX_TIM9_Init(void)\n{\n\n  /* USER CODE BEGIN TIM9_Init 0 */\n\n  /* USER CODE END TIM9_Init 0 */\n\n  TIM_OC_InitTypeDef sConfigOC = {0};\n\n  /* USER CODE BEGIN TIM9_Init 1 */\n\n  /* USER CODE END TIM9_Init 1 */\n  htim9.Instance = TIM9;\n  htim9.Init.Prescaler = 7;\n  htim9.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim9.Init.Period = 999;\n  htim9.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim9.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_PWM_Init(&htim9) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sConfigOC.OCMode = TIM_OCMODE_PWM1;\n  sConfigOC.Pulse = 0;\n  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;\n  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;\n  if (HAL_TIM_PWM_ConfigChannel(&htim9, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  if (HAL_TIM_PWM_ConfigChannel(&htim9, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM9_Init 2 */\n\n  /* USER CODE END TIM9_Init 2 */\n  HAL_TIM_MspPostInit(&htim9);\n\n}\n/* TIM10 init function */\nvoid MX_TIM10_Init(void)\n{\n\n  /* USER CODE BEGIN TIM10_Init 0 */\n\n  /* USER CODE END TIM10_Init 0 */\n\n  /* USER CODE BEGIN TIM10_Init 1 */\n\n  /* USER CODE END TIM10_Init 1 */\n  htim10.Instance = TIM10;\n  htim10.Init.Prescaler = 167;\n  htim10.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim10.Init.Period = 9999;\n  htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;\n  if (HAL_TIM_Base_Init(&htim10) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM10_Init 2 */\n\n  /* USER CODE END TIM10_Init 2 */\n\n}\n/* TIM11 init function */\nvoid MX_TIM11_Init(void)\n{\n\n  /* USER CODE BEGIN TIM11_Init 0 */\n\n  /* USER CODE END TIM11_Init 0 */\n\n  /* USER CODE BEGIN TIM11_Init 1 */\n\n  /* USER CODE END TIM11_Init 1 */\n  htim11.Instance = TIM11;\n  htim11.Init.Prescaler = 167;\n  htim11.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim11.Init.Period = 9999;\n  htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_Base_Init(&htim11) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM11_Init 2 */\n\n  /* USER CODE END TIM11_Init 2 */\n\n}\n/* TIM12 init function */\nvoid MX_TIM12_Init(void)\n{\n\n  /* USER CODE BEGIN TIM12_Init 0 */\n\n  /* USER CODE END TIM12_Init 0 */\n\n  TIM_OC_InitTypeDef sConfigOC = {0};\n\n  /* USER CODE BEGIN TIM12_Init 1 */\n\n  /* USER CODE END TIM12_Init 1 */\n  htim12.Instance = TIM12;\n  htim12.Init.Prescaler = 3;\n  htim12.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim12.Init.Period = 999;\n  htim12.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim12.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_PWM_Init(&htim12) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sConfigOC.OCMode = TIM_OCMODE_PWM1;\n  sConfigOC.Pulse = 0;\n  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;\n  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;\n  if (HAL_TIM_PWM_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  if (HAL_TIM_PWM_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM12_Init 2 */\n\n  /* USER CODE END TIM12_Init 2 */\n  HAL_TIM_MspPostInit(&htim12);\n\n}\n/* TIM13 init function */\nvoid MX_TIM13_Init(void)\n{\n\n  /* USER CODE BEGIN TIM13_Init 0 */\n\n  /* USER CODE END TIM13_Init 0 */\n\n  /* USER CODE BEGIN TIM13_Init 1 */\n\n  /* USER CODE END TIM13_Init 1 */\n  htim13.Instance = TIM13;\n  htim13.Init.Prescaler = 83;\n  htim13.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim13.Init.Period = 9999;\n  htim13.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim13.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_Base_Init(&htim13) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM13_Init 2 */\n\n  /* USER CODE END TIM13_Init 2 */\n\n}\n/* TIM14 init function */\nvoid MX_TIM14_Init(void)\n{\n\n  /* USER CODE BEGIN TIM14_Init 0 */\n\n  /* USER CODE END TIM14_Init 0 */\n\n  /* USER CODE BEGIN TIM14_Init 1 */\n\n  /* USER CODE END TIM14_Init 1 */\n  htim14.Instance = TIM14;\n  htim14.Init.Prescaler = 83;\n  htim14.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim14.Init.Period = 9999;\n  htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_Base_Init(&htim14) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM14_Init 2 */\n\n  /* USER CODE END TIM14_Init 2 */\n\n}\n\nvoid HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* tim_encoderHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(tim_encoderHandle->Instance==TIM2)\n  {\n  /* USER CODE BEGIN TIM2_MspInit 0 */\n\n  /* USER CODE END TIM2_MspInit 0 */\n    /* TIM2 clock enable */\n    __HAL_RCC_TIM2_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**TIM2 GPIO Configuration\n    PA15     ------> TIM2_CH1\n    PB3     ------> TIM2_CH2\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_15;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_3;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    /* TIM2 interrupt Init */\n    HAL_NVIC_SetPriority(TIM2_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM2_IRQn);\n  /* USER CODE BEGIN TIM2_MspInit 1 */\n\n  /* USER CODE END TIM2_MspInit 1 */\n  }\n  else if(tim_encoderHandle->Instance==TIM3)\n  {\n  /* USER CODE BEGIN TIM3_MspInit 0 */\n\n  /* USER CODE END TIM3_MspInit 0 */\n    /* TIM3 clock enable */\n    __HAL_RCC_TIM3_CLK_ENABLE();\n\n    __HAL_RCC_GPIOC_CLK_ENABLE();\n    /**TIM3 GPIO Configuration\n    PC6     ------> TIM3_CH1\n    PC7     ------> TIM3_CH2\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n    /* TIM3 interrupt Init */\n    HAL_NVIC_SetPriority(TIM3_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM3_IRQn);\n  /* USER CODE BEGIN TIM3_MspInit 1 */\n\n  /* USER CODE END TIM3_MspInit 1 */\n  }\n}\n\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)\n{\n\n  if(tim_baseHandle->Instance==TIM7)\n  {\n  /* USER CODE BEGIN TIM7_MspInit 0 */\n\n  /* USER CODE END TIM7_MspInit 0 */\n    /* TIM7 clock enable */\n    __HAL_RCC_TIM7_CLK_ENABLE();\n\n    /* TIM7 interrupt Init */\n    HAL_NVIC_SetPriority(TIM7_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM7_IRQn);\n  /* USER CODE BEGIN TIM7_MspInit 1 */\n\n  /* USER CODE END TIM7_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM10)\n  {\n  /* USER CODE BEGIN TIM10_MspInit 0 */\n\n  /* USER CODE END TIM10_MspInit 0 */\n    /* TIM10 clock enable */\n    __HAL_RCC_TIM10_CLK_ENABLE();\n\n    /* TIM10 interrupt Init */\n    HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);\n  /* USER CODE BEGIN TIM10_MspInit 1 */\n\n  /* USER CODE END TIM10_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM11)\n  {\n  /* USER CODE BEGIN TIM11_MspInit 0 */\n\n  /* USER CODE END TIM11_MspInit 0 */\n    /* TIM11 clock enable */\n    __HAL_RCC_TIM11_CLK_ENABLE();\n\n    /* TIM11 interrupt Init */\n    HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM11_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM11_IRQn);\n  /* USER CODE BEGIN TIM11_MspInit 1 */\n\n  /* USER CODE END TIM11_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM13)\n  {\n  /* USER CODE BEGIN TIM13_MspInit 0 */\n\n  /* USER CODE END TIM13_MspInit 0 */\n    /* TIM13 clock enable */\n    __HAL_RCC_TIM13_CLK_ENABLE();\n\n    /* TIM13 interrupt Init */\n    HAL_NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);\n  /* USER CODE BEGIN TIM13_MspInit 1 */\n\n  /* USER CODE END TIM13_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM14)\n  {\n  /* USER CODE BEGIN TIM14_MspInit 0 */\n\n  /* USER CODE END TIM14_MspInit 0 */\n    /* TIM14 clock enable */\n    __HAL_RCC_TIM14_CLK_ENABLE();\n\n    /* TIM14 interrupt Init */\n    HAL_NVIC_SetPriority(TIM8_TRG_COM_TIM14_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM8_TRG_COM_TIM14_IRQn);\n  /* USER CODE BEGIN TIM14_MspInit 1 */\n\n  /* USER CODE END TIM14_MspInit 1 */\n  }\n}\n\nvoid HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)\n{\n\n  if(tim_pwmHandle->Instance==TIM9)\n  {\n  /* USER CODE BEGIN TIM9_MspInit 0 */\n\n  /* USER CODE END TIM9_MspInit 0 */\n    /* TIM9 clock enable */\n    __HAL_RCC_TIM9_CLK_ENABLE();\n  /* USER CODE BEGIN TIM9_MspInit 1 */\n\n  /* USER CODE END TIM9_MspInit 1 */\n  }\n  else if(tim_pwmHandle->Instance==TIM12)\n  {\n  /* USER CODE BEGIN TIM12_MspInit 0 */\n\n  /* USER CODE END TIM12_MspInit 0 */\n    /* TIM12 clock enable */\n    __HAL_RCC_TIM12_CLK_ENABLE();\n  /* USER CODE BEGIN TIM12_MspInit 1 */\n\n  /* USER CODE END TIM12_MspInit 1 */\n  }\n}\nvoid HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(timHandle->Instance==TIM9)\n  {\n  /* USER CODE BEGIN TIM9_MspPostInit 0 */\n\n  /* USER CODE END TIM9_MspPostInit 0 */\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**TIM9 GPIO Configuration\n    PA2     ------> TIM9_CH1\n    PA3     ------> TIM9_CH2\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF3_TIM9;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n  /* USER CODE BEGIN TIM9_MspPostInit 1 */\n\n  /* USER CODE END TIM9_MspPostInit 1 */\n  }\n  else if(timHandle->Instance==TIM12)\n  {\n  /* USER CODE BEGIN TIM12_MspPostInit 0 */\n\n  /* USER CODE END TIM12_MspPostInit 0 */\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**TIM12 GPIO Configuration\n    PB14     ------> TIM12_CH1\n    PB15     ------> TIM12_CH2\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n    GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n  /* USER CODE BEGIN TIM12_MspPostInit 1 */\n\n  /* USER CODE END TIM12_MspPostInit 1 */\n  }\n\n}\n\nvoid HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef* tim_encoderHandle)\n{\n\n  if(tim_encoderHandle->Instance==TIM2)\n  {\n  /* USER CODE BEGIN TIM2_MspDeInit 0 */\n\n  /* USER CODE END TIM2_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM2_CLK_DISABLE();\n\n    /**TIM2 GPIO Configuration\n    PA15     ------> TIM2_CH1\n    PB3     ------> TIM2_CH2\n    */\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);\n\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3);\n\n    /* TIM2 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM2_IRQn);\n  /* USER CODE BEGIN TIM2_MspDeInit 1 */\n\n  /* USER CODE END TIM2_MspDeInit 1 */\n  }\n  else if(tim_encoderHandle->Instance==TIM3)\n  {\n  /* USER CODE BEGIN TIM3_MspDeInit 0 */\n\n  /* USER CODE END TIM3_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM3_CLK_DISABLE();\n\n    /**TIM3 GPIO Configuration\n    PC6     ------> TIM3_CH1\n    PC7     ------> TIM3_CH2\n    */\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_6|GPIO_PIN_7);\n\n    /* TIM3 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM3_IRQn);\n  /* USER CODE BEGIN TIM3_MspDeInit 1 */\n\n  /* USER CODE END TIM3_MspDeInit 1 */\n  }\n}\n\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)\n{\n\n  if(tim_baseHandle->Instance==TIM7)\n  {\n  /* USER CODE BEGIN TIM7_MspDeInit 0 */\n\n  /* USER CODE END TIM7_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM7_CLK_DISABLE();\n\n    /* TIM7 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM7_IRQn);\n  /* USER CODE BEGIN TIM7_MspDeInit 1 */\n\n  /* USER CODE END TIM7_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM10)\n  {\n  /* USER CODE BEGIN TIM10_MspDeInit 0 */\n\n  /* USER CODE END TIM10_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM10_CLK_DISABLE();\n\n    /* TIM10 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM1_UP_TIM10_IRQn);\n  /* USER CODE BEGIN TIM10_MspDeInit 1 */\n\n  /* USER CODE END TIM10_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM11)\n  {\n  /* USER CODE BEGIN TIM11_MspDeInit 0 */\n\n  /* USER CODE END TIM11_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM11_CLK_DISABLE();\n\n    /* TIM11 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM1_TRG_COM_TIM11_IRQn);\n  /* USER CODE BEGIN TIM11_MspDeInit 1 */\n\n  /* USER CODE END TIM11_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM13)\n  {\n  /* USER CODE BEGIN TIM13_MspDeInit 0 */\n\n  /* USER CODE END TIM13_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM13_CLK_DISABLE();\n\n    /* TIM13 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM8_UP_TIM13_IRQn);\n  /* USER CODE BEGIN TIM13_MspDeInit 1 */\n\n  /* USER CODE END TIM13_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM14)\n  {\n  /* USER CODE BEGIN TIM14_MspDeInit 0 */\n\n  /* USER CODE END TIM14_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM14_CLK_DISABLE();\n\n    /* TIM14 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM8_TRG_COM_TIM14_IRQn);\n  /* USER CODE BEGIN TIM14_MspDeInit 1 */\n\n  /* USER CODE END TIM14_MspDeInit 1 */\n  }\n}\n\nvoid HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle)\n{\n\n  if(tim_pwmHandle->Instance==TIM9)\n  {\n  /* USER CODE BEGIN TIM9_MspDeInit 0 */\n\n  /* USER CODE END TIM9_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM9_CLK_DISABLE();\n  /* USER CODE BEGIN TIM9_MspDeInit 1 */\n\n  /* USER CODE END TIM9_MspDeInit 1 */\n  }\n  else if(tim_pwmHandle->Instance==TIM12)\n  {\n  /* USER CODE BEGIN TIM12_MspDeInit 0 */\n\n  /* USER CODE END TIM12_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM12_CLK_DISABLE();\n  /* USER CODE BEGIN TIM12_MspDeInit 1 */\n\n  /* USER CODE END TIM12_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\nvoid HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\n{\n    if (htim->Instance->SR & 0x01) // count overflow\n    {\n        if (htim->Instance->CR1 & 0x10) // count up\n        {\n            if (htim->Instance == TIM2)\n                encCntLoop[0]--;\n            else if (htim->Instance == TIM3)\n                encCntLoop[1]--;\n        } else                          // count down\n        {\n            if (htim->Instance == TIM2)\n                encCntLoop[0]++;\n            else if (htim->Instance == TIM3)\n                encCntLoop[1]++;\n        }\n\n        htim->Instance->SR = htim->Instance->SR & 0xFE; // clear flag\n    }\n}\n\nint64_t GetCntLoop(TIM_TypeDef *tim)\n{\n    if (tim == TIM2)\n    {\n        return encCntLoop[0];\n    } else if (tim == TIM3)\n    {\n        return encCntLoop[1];\n    }\n}\n\nvoid ClearCntLoop(TIM_TypeDef *tim)\n{\n    if (tim == TIM2)\n    {\n        encCntLoop[0] = 0;\n    } else if (tim == TIM3)\n    {\n        encCntLoop[1] = 0;\n    }\n}\n\nint64_t GetEncoderCount(TIM_TypeDef *tim)\n{\n    if (tim == TIM2)\n    {\n        return encCntLoop[0] * 65536 + TIM2->CNT;\n    } else if (tim == TIM3)\n    {\n        return encCntLoop[1] * 65536 + TIM3->CNT;\n    }\n}\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Core/Src/usart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usart.c\n  * @brief   This file provides code for the configuration\n  *          of the USART instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usart.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\nUART_HandleTypeDef huart4;\nUART_HandleTypeDef huart5;\nUART_HandleTypeDef huart1;\nDMA_HandleTypeDef hdma_uart4_rx;\nDMA_HandleTypeDef hdma_uart4_tx;\nDMA_HandleTypeDef hdma_uart5_rx;\nDMA_HandleTypeDef hdma_uart5_tx;\n\n/* UART4 init function */\nvoid MX_UART4_Init(void)\n{\n\n  /* USER CODE BEGIN UART4_Init 0 */\n\n  /* USER CODE END UART4_Init 0 */\n\n  /* USER CODE BEGIN UART4_Init 1 */\n\n  /* USER CODE END UART4_Init 1 */\n  huart4.Instance = UART4;\n  huart4.Init.BaudRate = 115200;\n  huart4.Init.WordLength = UART_WORDLENGTH_8B;\n  huart4.Init.StopBits = UART_STOPBITS_1;\n  huart4.Init.Parity = UART_PARITY_NONE;\n  huart4.Init.Mode = UART_MODE_TX_RX;\n  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;\n  huart4.Init.OverSampling = UART_OVERSAMPLING_16;\n  if (HAL_UART_Init(&huart4) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN UART4_Init 2 */\n\n  /* USER CODE END UART4_Init 2 */\n\n}\n/* UART5 init function */\nvoid MX_UART5_Init(void)\n{\n\n  /* USER CODE BEGIN UART5_Init 0 */\n\n  /* USER CODE END UART5_Init 0 */\n\n  /* USER CODE BEGIN UART5_Init 1 */\n\n  /* USER CODE END UART5_Init 1 */\n  huart5.Instance = UART5;\n  huart5.Init.BaudRate = 115200;\n  huart5.Init.WordLength = UART_WORDLENGTH_8B;\n  huart5.Init.StopBits = UART_STOPBITS_1;\n  huart5.Init.Parity = UART_PARITY_NONE;\n  huart5.Init.Mode = UART_MODE_TX_RX;\n  huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;\n  huart5.Init.OverSampling = UART_OVERSAMPLING_16;\n  if (HAL_UART_Init(&huart5) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN UART5_Init 2 */\n\n  /* USER CODE END UART5_Init 2 */\n\n}\n/* USART1 init function */\n\nvoid MX_USART1_UART_Init(void)\n{\n\n  /* USER CODE BEGIN USART1_Init 0 */\n\n  /* USER CODE END USART1_Init 0 */\n\n  /* USER CODE BEGIN USART1_Init 1 */\n\n  /* USER CODE END USART1_Init 1 */\n  huart1.Instance = USART1;\n  huart1.Init.BaudRate = 115200;\n  huart1.Init.WordLength = UART_WORDLENGTH_8B;\n  huart1.Init.StopBits = UART_STOPBITS_1;\n  huart1.Init.Parity = UART_PARITY_NONE;\n  huart1.Init.Mode = UART_MODE_TX_RX;\n  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;\n  huart1.Init.OverSampling = UART_OVERSAMPLING_16;\n  if (HAL_UART_Init(&huart1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN USART1_Init 2 */\n\n  /* USER CODE END USART1_Init 2 */\n\n}\n\nvoid HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(uartHandle->Instance==UART4)\n  {\n  /* USER CODE BEGIN UART4_MspInit 0 */\n\n  /* USER CODE END UART4_MspInit 0 */\n    /* UART4 clock enable */\n    __HAL_RCC_UART4_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**UART4 GPIO Configuration\n    PA0-WKUP     ------> UART4_TX\n    PA1     ------> UART4_RX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* UART4 DMA Init */\n    /* UART4_RX Init */\n    hdma_uart4_rx.Instance = DMA1_Stream2;\n    hdma_uart4_rx.Init.Channel = DMA_CHANNEL_4;\n    hdma_uart4_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n    hdma_uart4_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_uart4_rx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_uart4_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_uart4_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_uart4_rx.Init.Mode = DMA_CIRCULAR;\n    hdma_uart4_rx.Init.Priority = DMA_PRIORITY_LOW;\n    hdma_uart4_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n    if (HAL_DMA_Init(&hdma_uart4_rx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart4_rx);\n\n    /* UART4_TX Init */\n    hdma_uart4_tx.Instance = DMA1_Stream4;\n    hdma_uart4_tx.Init.Channel = DMA_CHANNEL_4;\n    hdma_uart4_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n    hdma_uart4_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_uart4_tx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_uart4_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_uart4_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_uart4_tx.Init.Mode = DMA_NORMAL;\n    hdma_uart4_tx.Init.Priority = DMA_PRIORITY_LOW;\n    hdma_uart4_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n    if (HAL_DMA_Init(&hdma_uart4_tx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart4_tx);\n\n    /* UART4 interrupt Init */\n    HAL_NVIC_SetPriority(UART4_IRQn, 6, 0);\n    HAL_NVIC_EnableIRQ(UART4_IRQn);\n  /* USER CODE BEGIN UART4_MspInit 1 */\n\n  /* USER CODE END UART4_MspInit 1 */\n  }\n  else if(uartHandle->Instance==UART5)\n  {\n  /* USER CODE BEGIN UART5_MspInit 0 */\n\n  /* USER CODE END UART5_MspInit 0 */\n    /* UART5 clock enable */\n    __HAL_RCC_UART5_CLK_ENABLE();\n\n    __HAL_RCC_GPIOC_CLK_ENABLE();\n    __HAL_RCC_GPIOD_CLK_ENABLE();\n    /**UART5 GPIO Configuration\n    PC12     ------> UART5_TX\n    PD2     ------> UART5_RX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_12;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF8_UART5;\n    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_2;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_PULLUP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF8_UART5;\n    HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);\n\n    /* UART5 DMA Init */\n    /* UART5_RX Init */\n    hdma_uart5_rx.Instance = DMA1_Stream0;\n    hdma_uart5_rx.Init.Channel = DMA_CHANNEL_4;\n    hdma_uart5_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n    hdma_uart5_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_uart5_rx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_uart5_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_uart5_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_uart5_rx.Init.Mode = DMA_CIRCULAR;\n    hdma_uart5_rx.Init.Priority = DMA_PRIORITY_LOW;\n    hdma_uart5_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n    if (HAL_DMA_Init(&hdma_uart5_rx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmarx,hdma_uart5_rx);\n\n    /* UART5_TX Init */\n    hdma_uart5_tx.Instance = DMA1_Stream7;\n    hdma_uart5_tx.Init.Channel = DMA_CHANNEL_4;\n    hdma_uart5_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n    hdma_uart5_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_uart5_tx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_uart5_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_uart5_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_uart5_tx.Init.Mode = DMA_NORMAL;\n    hdma_uart5_tx.Init.Priority = DMA_PRIORITY_LOW;\n    hdma_uart5_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;\n    if (HAL_DMA_Init(&hdma_uart5_tx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmatx,hdma_uart5_tx);\n\n    /* UART5 interrupt Init */\n    HAL_NVIC_SetPriority(UART5_IRQn, 6, 0);\n    HAL_NVIC_EnableIRQ(UART5_IRQn);\n  /* USER CODE BEGIN UART5_MspInit 1 */\n\n  /* USER CODE END UART5_MspInit 1 */\n  }\n  else if(uartHandle->Instance==USART1)\n  {\n  /* USER CODE BEGIN USART1_MspInit 0 */\n\n  /* USER CODE END USART1_MspInit 0 */\n    /* USART1 clock enable */\n    __HAL_RCC_USART1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**USART1 GPIO Configuration\n    PA9     ------> USART1_TX\n    PA10     ------> USART1_RX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n  /* USER CODE BEGIN USART1_MspInit 1 */\n\n  /* USER CODE END USART1_MspInit 1 */\n  }\n}\n\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)\n{\n\n  if(uartHandle->Instance==UART4)\n  {\n  /* USER CODE BEGIN UART4_MspDeInit 0 */\n\n  /* USER CODE END UART4_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_UART4_CLK_DISABLE();\n\n    /**UART4 GPIO Configuration\n    PA0-WKUP     ------> UART4_TX\n    PA1     ------> UART4_RX\n    */\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);\n\n    /* UART4 DMA DeInit */\n    HAL_DMA_DeInit(uartHandle->hdmarx);\n    HAL_DMA_DeInit(uartHandle->hdmatx);\n\n    /* UART4 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(UART4_IRQn);\n  /* USER CODE BEGIN UART4_MspDeInit 1 */\n\n  /* USER CODE END UART4_MspDeInit 1 */\n  }\n  else if(uartHandle->Instance==UART5)\n  {\n  /* USER CODE BEGIN UART5_MspDeInit 0 */\n\n  /* USER CODE END UART5_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_UART5_CLK_DISABLE();\n\n    /**UART5 GPIO Configuration\n    PC12     ------> UART5_TX\n    PD2     ------> UART5_RX\n    */\n    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_12);\n\n    HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2);\n\n    /* UART5 DMA DeInit */\n    HAL_DMA_DeInit(uartHandle->hdmarx);\n    HAL_DMA_DeInit(uartHandle->hdmatx);\n\n    /* UART5 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(UART5_IRQn);\n  /* USER CODE BEGIN UART5_MspDeInit 1 */\n\n  /* USER CODE END UART5_MspDeInit 1 */\n  }\n  else if(uartHandle->Instance==USART1)\n  {\n  /* USER CODE BEGIN USART1_MspDeInit 0 */\n\n  /* USER CODE END USART1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_USART1_CLK_DISABLE();\n\n    /**USART1 GPIO Configuration\n    PA9     ------> USART1_TX\n    PA10     ------> USART1_RX\n    */\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);\n\n  /* USER CODE BEGIN USART1_MspDeInit 1 */\n\n  /* USER CODE END USART1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f405xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F405xx Device Peripheral Access Layer Header File.\n  *\n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - peripherals registers declarations and bits definition\n  *           - Macros to access peripheral’s registers hardware\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS_Device\n  * @{\n  */\n\n/** @addtogroup stm32f405xx\n  * @{\n  */\n    \n#ifndef __STM32F405xx_H\n#define __STM32F405xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n\n/**\n  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \n  */\n#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */\n#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */\n#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\n#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */\n#define __FPU_PRESENT             1U       /*!< FPU present                                   */\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F4XX Interrupt Number Definition, according to the selected device \n *        in @ref Library_configuration_section \n */\ntypedef enum\n{\n/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\n/******  STM32 specific Interrupt Numbers **********************************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\n  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\n  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\n  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\n  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\n  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\n  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\n  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\n  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\n  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\n  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\n  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\n  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\n  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\n  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\n  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\n  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */\n  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\n  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\n  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\n  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */\n  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\n  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\n  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\n  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\n  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\n  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\n  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\n  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\n  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\n  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\n  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\n  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\n  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\n  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\n  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\n  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\n  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\n  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\n  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\n  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\n  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\n  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\n  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\n  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\n  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\n  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\n  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\n  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\n  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\n  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */\n  FPU_IRQn                    = 81      /*!< FPU global interrupt                                               */\n} IRQn_Type;\n/* Legacy define */\n#define  HASH_RNG_IRQn      RNG_IRQn\n\n/**\n  * @}\n  */\n\n#include \"core_cm4.h\"             /* Cortex-M4 processor and core peripherals */\n#include \"system_stm32f4xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */   \n\n/** \n  * @brief Analog to Digital Converter  \n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\n  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */\n  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\n  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\n  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\n  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\n  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\n  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\n  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\n  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\n  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\n  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\n  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\n  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\n  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\n  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\n  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\n  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\n  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\n  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\n  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\n  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\n                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\n} ADC_Common_TypeDef;\n\n\n/** \n  * @brief Controller Area Network TxMailBox \n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\n  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\n  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\n  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\n} CAN_TxMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FIFOMailBox \n  */\n  \ntypedef struct\n{\n  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\n  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\n  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\n  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\n} CAN_FIFOMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FilterRegister \n  */\n  \ntypedef struct\n{\n  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\n  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\n} CAN_FilterRegister_TypeDef;\n\n/** \n  * @brief Controller Area Network \n  */\n  \ntypedef struct\n{\n  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\n  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\n  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\n  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\n  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\n  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\n  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\n  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\n  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\n  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\n  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\n  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\n  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\n  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\n  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\n  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\n  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\n  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\n  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\n  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\n  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ \n  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\n} CAN_TypeDef;\n\n/** \n  * @brief CRC calculation unit \n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\n  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\n  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\n  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\n  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\n} CRC_TypeDef;\n\n/** \n  * @brief Digital to Analog Converter\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\n  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\n  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\n  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\n  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\n  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\n  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\n  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\n  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\n  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\n  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\n  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\n} DAC_TypeDef;\n\n/** \n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\n  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\n  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\n  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\n}DBGMCU_TypeDef;\n\n\n/** \n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\n  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\n  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\n  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\n  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\n  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\n} DMA_Stream_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\n  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\n  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\n  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\n} DMA_TypeDef;\n\n/** \n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\n  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\n  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\n  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\n  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\n  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\n} EXTI_TypeDef;\n\n/** \n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\n  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\n  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\n  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\n  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\n  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\n  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\n} FLASH_TypeDef;\n\n\n\n/** \n  * @brief Flexible Static Memory Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   \n} FSMC_Bank1_TypeDef;\n\n/** \n  * @brief Flexible Static Memory Controller Bank1E\n  */\n\ntypedef struct\n{\n  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\n} FSMC_Bank1E_TypeDef;\n\n/** \n  * @brief Flexible Static Memory Controller Bank2\n  */\n  \ntypedef struct\n{\n  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\n  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\n  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\n  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\n  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\n  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\n  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */\n  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */\n  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\n  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\n  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\n  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\n  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */\n  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\n} FSMC_Bank2_3_TypeDef;\n\n/** \n  * @brief Flexible Static Memory Controller Bank4\n  */\n\ntypedef struct\n{\n  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\n  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\n  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\n  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\n  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\n} FSMC_Bank4_TypeDef; \n\n/** \n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\n  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\n  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\n  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\n  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\n  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\n  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */\n  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\n  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\n} GPIO_TypeDef;\n\n/** \n  * @brief System configuration controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\n  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\n  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */\n  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\n} SYSCFG_TypeDef;\n\n/** \n  * @brief Inter-integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\n  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\n  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\n  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\n  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\n  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\n  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\n  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\n} I2C_TypeDef;\n\n/** \n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\n  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\n  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\n  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\n} IWDG_TypeDef;\n\n\n/** \n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\n  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\n} PWR_TypeDef;\n\n/** \n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\n  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\n  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\n  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\n  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\n  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\n  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\n  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\n  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\n  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\n  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\n  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\n  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\n  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\n  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\n  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\n  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\n  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\n  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\n  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\n  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\n  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\n  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\n  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\n  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\n  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\n  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\n  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\n  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\n  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\n} RCC_TypeDef;\n\n/** \n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\n  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\n  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\n  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\n  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\n  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\n  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\n  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\n  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\n  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\n  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\n  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\n  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\n  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\n  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\n  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\n  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\n  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\n  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\n  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\n  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\n  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\n  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\n  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\n  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\n  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\n  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\n  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\n  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\n  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\n  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\n  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\n  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\n  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\n  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\n  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\n  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\n  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\n  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\n  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\n} RTC_TypeDef;\n\n/** \n  * @brief SD host Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */\n  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */\n  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */\n  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */\n  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\n  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\n  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\n  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\n  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\n  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */\n  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */\n  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */\n  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\n  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\n  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */\n  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */\n  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */\n  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\n  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */\n  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */\n} SDIO_TypeDef;\n\n/** \n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\n  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\n  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\n  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\n  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\n  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\n  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\n  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\n  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\n} SPI_TypeDef;\n\n\n/** \n  * @brief TIM\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\n  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\n  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\n  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\n  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\n  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\n  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\n  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\n  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\n  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\n  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\n  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\n  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\n  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\n  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\n  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\n  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\n  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\n  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\n} TIM_TypeDef;\n\n/** \n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n \ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/** \n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/** \n  * @brief RNG\n  */\n  \ntypedef struct \n{\n  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\n  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\n  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\n} RNG_TypeDef;\n\n/** \n  * @brief USB_OTG_Core_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */\n  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */\n  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */\n  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */\n  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */\n  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */\n  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */\n  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */\n  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */\n  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */\n  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */\n  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */\n  uint32_t Reserved30[2];             /*!< Reserved                                     030h */\n  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */\n  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */\n  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */\n  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */\n  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */\n} USB_OTG_GlobalTypeDef;\n\n/** \n  * @brief USB_OTG_device_Registers\n  */\ntypedef struct \n{\n  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */\n  __IO uint32_t DCTL;            /*!< dev Control Register         804h */\n  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */\n  uint32_t Reserved0C;           /*!< Reserved                     80Ch */\n  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */\n  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */\n  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */\n  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */\n  uint32_t  Reserved20;          /*!< Reserved                     820h */\n  uint32_t Reserved9;            /*!< Reserved                     824h */\n  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */\n  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */\n  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */\n  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */\n  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */\n  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */\n  uint32_t Reserved40;           /*!< dedicated EP mask            840h */\n  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */\n  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */\n  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */\n} USB_OTG_DeviceTypeDef;\n\n/** \n  * @brief USB_OTG_IN_Endpoint-Specific_Register\n  */\ntypedef struct \n{\n  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */\n  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */\n  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */\n  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\n  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\n} USB_OTG_INEndpointTypeDef;\n\n/** \n  * @brief USB_OTG_OUT_Endpoint-Specific_Registers\n  */\ntypedef struct \n{\n  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */\n  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */\n  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */\n  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */\n  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */\n  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */\n  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\n} USB_OTG_OUTEndpointTypeDef;\n\n/** \n  * @brief USB_OTG_Host_Mode_Register_Structures\n  */\ntypedef struct \n{\n  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */\n  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */\n  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */\n  uint32_t Reserved40C;           /*!< Reserved                             40Ch */\n  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */\n  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */\n  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */\n} USB_OTG_HostTypeDef;\n\n/** \n  * @brief USB_OTG_Host_Channel_Specific_Registers\n  */\ntypedef struct\n{\n  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */\n  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */\n  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */\n  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */\n  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */\n  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */\n  uint32_t Reserved[2];           /*!< Reserved                                      */\n} USB_OTG_HostChannelTypeDef;\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */\n#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\n#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */\n#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */\n#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */\n#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */\n#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */\n#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */\n#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */\n#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */\n#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */\n#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */\n#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */\n\n/* Legacy defines */\n#define SRAM_BASE             SRAM1_BASE\n#define SRAM_BB_BASE          SRAM1_BB_BASE\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)\n\n/*!< APB1 peripherals */\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)\n#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)\n#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)\n#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)\n#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)\n#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)\n#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)\n#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)\n#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)\n#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)\n#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)\n\n/*!< APB2 peripherals */\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)\n#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)\n#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)\n#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)\n#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)\n/* Legacy define */\n#define ADC_BASE               ADC123_COMMON_BASE\n#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)\n#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)\n#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)\n#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)\n#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)\n\n/*!< AHB1 peripherals */\n#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)\n#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)\n#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)\n#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)\n#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)\n#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)\n#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)\n#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)\n#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)\n#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)\n#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)\n#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)\n#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)\n#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)\n#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)\n#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)\n#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)\n#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)\n#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)\n#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)\n#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)\n#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)\n#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)\n#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)\n\n/*!< AHB2 peripherals */\n#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)\n\n/*!< FSMC Bankx registers base address */\n#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)\n#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)\n#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)\n#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)\n\n\n/*!< Debug MCU registers base address */\n#define DBGMCU_BASE           0xE0042000UL\n/*!< USB registers base address */\n#define USB_OTG_HS_PERIPH_BASE               0x40040000UL\n#define USB_OTG_FS_PERIPH_BASE               0x50000000UL\n\n#define USB_OTG_GLOBAL_BASE                  0x000UL\n#define USB_OTG_DEVICE_BASE                  0x800UL\n#define USB_OTG_IN_ENDPOINT_BASE             0x900UL\n#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL\n#define USB_OTG_EP_REG_SIZE                  0x20UL\n#define USB_OTG_HOST_BASE                    0x400UL\n#define USB_OTG_HOST_PORT_BASE               0x440UL\n#define USB_OTG_HOST_CHANNEL_BASE            0x500UL\n#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL\n#define USB_OTG_PCGCCTL_BASE                 0xE00UL\n#define USB_OTG_FIFO_BASE                    0x1000UL\n#define USB_OTG_FIFO_SIZE                    0x1000UL\n\n#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */\n#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_declaration\n  * @{\n  */  \n#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\n#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\n#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\n#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\n#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\n#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\n#define RTC                 ((RTC_TypeDef *) RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\n#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\n#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\n#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\n#define USART2              ((USART_TypeDef *) USART2_BASE)\n#define USART3              ((USART_TypeDef *) USART3_BASE)\n#define UART4               ((USART_TypeDef *) UART4_BASE)\n#define UART5               ((USART_TypeDef *) UART5_BASE)\n#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\n#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\n#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\n#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\n#define PWR                 ((PWR_TypeDef *) PWR_BASE)\n#define DAC1                ((DAC_TypeDef *) DAC_BASE)\n#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\n#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\n#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\n#define USART1              ((USART_TypeDef *) USART1_BASE)\n#define USART6              ((USART_TypeDef *) USART6_BASE)\n#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\n#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\n#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)\n/* Legacy define */\n#define ADC                  ADC123_COMMON\n#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\n#define SPI1                ((SPI_TypeDef *) SPI1_BASE)\n#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\n#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\n#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\n#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\n#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\n#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\n#define CRC                 ((CRC_TypeDef *) CRC_BASE)\n#define RCC                 ((RCC_TypeDef *) RCC_BASE)\n#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\n#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\n#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\n#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\n#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\n#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\n#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\n#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\n#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\n#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\n#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\n#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\n#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\n#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\n#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\n#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\n#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\n#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\n#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\n#define RNG                 ((RNG_TypeDef *) RNG_BASE)\n#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\n#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\n#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)\n#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\n#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\n#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n  \n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n    \n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Analog to Digital Converter                         */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos            (0U)                                         \n#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */\n#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */\n#define ADC_SR_EOC_Pos            (1U)                                         \n#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */\n#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */\n#define ADC_SR_JEOC_Pos           (2U)                                         \n#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */\n#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */\n#define ADC_SR_JSTRT_Pos          (3U)                                         \n#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */\n#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */\n#define ADC_SR_STRT_Pos           (4U)                                         \n#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */\n#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */\n#define ADC_SR_OVR_Pos            (5U)                                         \n#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */\n#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos         (0U)                                         \n#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */\n#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\n#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */\n#define ADC_CR1_EOCIE_Pos         (5U)                                         \n#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */\n#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */\n#define ADC_CR1_AWDIE_Pos         (6U)                                         \n#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */\n#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */\n#define ADC_CR1_JEOCIE_Pos        (7U)                                         \n#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */\n#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */\n#define ADC_CR1_SCAN_Pos          (8U)                                         \n#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */\n#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */\n#define ADC_CR1_AWDSGL_Pos        (9U)                                         \n#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */\n#define ADC_CR1_JAUTO_Pos         (10U)                                        \n#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */\n#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */\n#define ADC_CR1_DISCEN_Pos        (11U)                                        \n#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */\n#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */\n#define ADC_CR1_JDISCEN_Pos       (12U)                                        \n#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */\n#define ADC_CR1_DISCNUM_Pos       (13U)                                        \n#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\n#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */\n#define ADC_CR1_JAWDEN_Pos        (22U)                                        \n#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */\n#define ADC_CR1_AWDEN_Pos         (23U)                                        \n#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */\n#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */\n#define ADC_CR1_RES_Pos           (24U)                                        \n#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */\n#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */\n#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */\n#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */\n#define ADC_CR1_OVRIE_Pos         (26U)                                        \n#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */\n#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */\n  \n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos          (0U)                                         \n#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */\n#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */\n#define ADC_CR2_CONT_Pos          (1U)                                         \n#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */\n#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */\n#define ADC_CR2_DMA_Pos           (8U)                                         \n#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */\n#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */\n#define ADC_CR2_DDS_Pos           (9U)                                         \n#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */\n#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */\n#define ADC_CR2_EOCS_Pos          (10U)                                        \n#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */\n#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */\n#define ADC_CR2_ALIGN_Pos         (11U)                                        \n#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */\n#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */\n#define ADC_CR2_JEXTSEL_Pos       (16U)                                        \n#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */\n#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */\n#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */\n#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */\n#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */\n#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */\n#define ADC_CR2_JEXTEN_Pos        (20U)                                        \n#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */\n#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\n#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */\n#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART_Pos      (22U)                                        \n#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */\n#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */\n#define ADC_CR2_EXTSEL_Pos        (24U)                                        \n#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */\n#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\n#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */\n#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */\n#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */\n#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */\n#define ADC_CR2_EXTEN_Pos         (28U)                                        \n#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */\n#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\n#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */\n#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */\n#define ADC_CR2_SWSTART_Pos       (30U)                                        \n#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */\n#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos       (0U)                                         \n#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\n#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */\n#define ADC_SMPR1_SMP11_Pos       (3U)                                         \n#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\n#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */\n#define ADC_SMPR1_SMP12_Pos       (6U)                                         \n#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\n#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */\n#define ADC_SMPR1_SMP13_Pos       (9U)                                         \n#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\n#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */\n#define ADC_SMPR1_SMP14_Pos       (12U)                                        \n#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\n#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */\n#define ADC_SMPR1_SMP15_Pos       (15U)                                        \n#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\n#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */\n#define ADC_SMPR1_SMP16_Pos       (18U)                                        \n#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\n#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */\n#define ADC_SMPR1_SMP17_Pos       (21U)                                        \n#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\n#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */\n#define ADC_SMPR1_SMP18_Pos       (24U)                                        \n#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */\n#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\n#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */\n#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */\n#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos        (0U)                                         \n#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\n#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */\n#define ADC_SMPR2_SMP1_Pos        (3U)                                         \n#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\n#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */\n#define ADC_SMPR2_SMP2_Pos        (6U)                                         \n#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\n#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */\n#define ADC_SMPR2_SMP3_Pos        (9U)                                         \n#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\n#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */\n#define ADC_SMPR2_SMP4_Pos        (12U)                                        \n#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\n#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */\n#define ADC_SMPR2_SMP5_Pos        (15U)                                        \n#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\n#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */\n#define ADC_SMPR2_SMP6_Pos        (18U)                                        \n#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\n#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */\n#define ADC_SMPR2_SMP7_Pos        (21U)                                        \n#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\n#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */\n#define ADC_SMPR2_SMP8_Pos        (24U)                                        \n#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\n#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */\n#define ADC_SMPR2_SMP9_Pos        (27U)                                        \n#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\n#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         \n#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         \n#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         \n#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         \n#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos            (0U)                                         \n#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */\n#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos            (0U)                                         \n#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */\n#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos         (0U)                                         \n#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */\n#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\n#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */\n#define ADC_SQR1_SQ14_Pos         (5U)                                         \n#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\n#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */\n#define ADC_SQR1_SQ15_Pos         (10U)                                        \n#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\n#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */\n#define ADC_SQR1_SQ16_Pos         (15U)                                        \n#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\n#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR1_L_Pos            (20U)                                        \n#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */\n#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */\n#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */\n#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */\n#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */\n#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos          (0U)                                         \n#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\n#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR2_SQ8_Pos          (5U)                                         \n#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\n#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR2_SQ9_Pos          (10U)                                        \n#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\n#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR2_SQ10_Pos         (15U)                                        \n#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\n#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */\n#define ADC_SQR2_SQ11_Pos         (20U)                                        \n#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\n#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */\n#define ADC_SQR2_SQ12_Pos         (25U)                                        \n#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\n#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos          (0U)                                         \n#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */\n#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\n#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */\n#define ADC_SQR3_SQ2_Pos          (5U)                                         \n#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\n#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */\n#define ADC_SQR3_SQ3_Pos          (10U)                                        \n#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\n#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */\n#define ADC_SQR3_SQ4_Pos          (15U)                                        \n#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\n#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */\n#define ADC_SQR3_SQ5_Pos          (20U)                                        \n#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\n#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */\n#define ADC_SQR3_SQ6_Pos          (25U)                                        \n#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\n#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos         (0U)                                         \n#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \n#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */\n#define ADC_JSQR_JSQ2_Pos         (5U)                                         \n#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\n#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */\n#define ADC_JSQR_JSQ3_Pos         (10U)                                        \n#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\n#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */\n#define ADC_JSQR_JSQ4_Pos         (15U)                                        \n#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\n#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */\n#define ADC_JSQR_JL_Pos           (20U)                                        \n#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */\n#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */\n#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */\n#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos        (0U)                                         \n#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos        (0U)                                         \n#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos        (0U)                                         \n#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos        (0U)                                         \n#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos           (0U)                                         \n#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */\n#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */\n#define ADC_DR_ADC2DATA_Pos       (16U)                                        \n#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */\n\n/*******************  Bit definition for ADC_CSR register  ********************/\n#define ADC_CSR_AWD1_Pos          (0U)                                         \n#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */\n#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */\n#define ADC_CSR_EOC1_Pos          (1U)                                         \n#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */\n#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */\n#define ADC_CSR_JEOC1_Pos         (2U)                                         \n#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */\n#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */\n#define ADC_CSR_JSTRT1_Pos        (3U)                                         \n#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */\n#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */\n#define ADC_CSR_STRT1_Pos         (4U)                                         \n#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */\n#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */\n#define ADC_CSR_OVR1_Pos          (5U)                                         \n#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */\n#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */\n#define ADC_CSR_AWD2_Pos          (8U)                                         \n#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */\n#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */\n#define ADC_CSR_EOC2_Pos          (9U)                                         \n#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */\n#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */\n#define ADC_CSR_JEOC2_Pos         (10U)                                        \n#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */\n#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */\n#define ADC_CSR_JSTRT2_Pos        (11U)                                        \n#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */\n#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */\n#define ADC_CSR_STRT2_Pos         (12U)                                        \n#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */\n#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */\n#define ADC_CSR_OVR2_Pos          (13U)                                        \n#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */\n#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */\n#define ADC_CSR_AWD3_Pos          (16U)                                        \n#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */\n#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */\n#define ADC_CSR_EOC3_Pos          (17U)                                        \n#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */\n#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */\n#define ADC_CSR_JEOC3_Pos         (18U)                                        \n#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */\n#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */\n#define ADC_CSR_JSTRT3_Pos        (19U)                                        \n#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */\n#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */\n#define ADC_CSR_STRT3_Pos         (20U)                                        \n#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */\n#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */\n#define ADC_CSR_OVR3_Pos          (21U)                                        \n#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */\n#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */\n\n/* Legacy defines */\n#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1\n#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2\n#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3\n\n/*******************  Bit definition for ADC_CCR register  ********************/\n#define ADC_CCR_MULTI_Pos         (0U)                                         \n#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */\n#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  \n#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */\n#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */\n#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */\n#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */\n#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */\n#define ADC_CCR_DELAY_Pos         (8U)                                         \n#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */\n#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  \n#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */\n#define ADC_CCR_DDS_Pos           (13U)                                        \n#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */\n#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */\n#define ADC_CCR_DMA_Pos           (14U)                                        \n#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */\n#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  \n#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */\n#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */\n#define ADC_CCR_ADCPRE_Pos        (16U)                                        \n#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */\n#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  \n#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */\n#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */\n#define ADC_CCR_VBATE_Pos         (22U)                                        \n#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */\n#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */\n#define ADC_CCR_TSVREFE_Pos       (23U)                                        \n#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */\n#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */\n\n/*******************  Bit definition for ADC_CDR register  ********************/\n#define ADC_CDR_DATA1_Pos         (0U)                                         \n#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */\n#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */\n#define ADC_CDR_DATA2_Pos         (16U)                                        \n#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */\n#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */\n\n/* Legacy defines */\n#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1\n#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n/*!<CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos       (0U)                                            \n#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */\n#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */\n#define CAN_MCR_SLEEP_Pos      (1U)                                            \n#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */\n#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos       (2U)                                            \n#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */\n#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos       (3U)                                            \n#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */\n#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos       (4U)                                            \n#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */\n#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos       (5U)                                            \n#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */\n#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos       (6U)                                            \n#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */\n#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos       (7U)                                            \n#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */\n#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos      (15U)                                           \n#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */\n#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */\n#define CAN_MCR_DBF_Pos        (16U)                                           \n#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */\n#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos       (0U)                                            \n#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */\n#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos       (1U)                                            \n#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */\n#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos       (2U)                                            \n#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */\n#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */\n#define CAN_MSR_WKUI_Pos       (3U)                                            \n#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */\n#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos      (4U)                                            \n#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */\n#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos        (8U)                                            \n#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */\n#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */\n#define CAN_MSR_RXM_Pos        (9U)                                            \n#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */\n#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */\n#define CAN_MSR_SAMP_Pos       (10U)                                           \n#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */\n#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */\n#define CAN_MSR_RX_Pos         (11U)                                           \n#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */\n#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos      (0U)                                            \n#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */\n#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos      (1U)                                            \n#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */\n#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos      (2U)                                            \n#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */\n#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos      (3U)                                            \n#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */\n#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos      (7U)                                            \n#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos      (8U)                                            \n#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */\n#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos      (9U)                                            \n#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */\n#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos      (10U)                                           \n#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */\n#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos      (11U)                                           \n#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */\n#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos      (15U)                                           \n#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos      (16U)                                           \n#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */\n#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos      (17U)                                           \n#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */\n#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos      (18U)                                           \n#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */\n#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos      (19U)                                           \n#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */\n#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos      (23U)                                           \n#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos       (24U)                                           \n#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */\n#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */\n\n#define CAN_TSR_TME_Pos        (26U)                                           \n#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */\n#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */\n#define CAN_TSR_TME0_Pos       (26U)                                           \n#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */\n#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos       (27U)                                           \n#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */\n#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos       (28U)                                           \n#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */\n#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos        (29U)                                           \n#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */\n#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos       (29U)                                           \n#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */\n#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos       (30U)                                           \n#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */\n#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos       (31U)                                           \n#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */\n#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos      (0U)                                            \n#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */\n#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos     (3U)                                            \n#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */\n#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos     (4U)                                            \n#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos     (5U)                                            \n#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos      (0U)                                            \n#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */\n#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos     (3U)                                            \n#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */\n#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos     (4U)                                            \n#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos     (5U)                                            \n#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos      (0U)                                            \n#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */\n#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos     (1U)                                            \n#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */\n#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos      (2U)                                            \n#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */\n#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos     (3U)                                            \n#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */\n#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos     (4U)                                            \n#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */\n#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos      (5U)                                            \n#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */\n#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos     (6U)                                            \n#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */\n#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)                                            \n#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */\n#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos      (9U)                                            \n#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */\n#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos      (10U)                                           \n#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */\n#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos      (11U)                                           \n#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */\n#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos      (15U)                                           \n#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */\n#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos      (16U)                                           \n#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */\n#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos      (17U)                                           \n#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */\n#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */\n#define CAN_IER_EWGIE_Pos      (8U)                                            \n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos       (0U)                                            \n#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */\n#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */\n#define CAN_ESR_EPVF_Pos       (1U)                                            \n#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */\n#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */\n#define CAN_ESR_BOFF_Pos       (2U)                                            \n#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */\n#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos        (4U)                                            \n#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */\n#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */\n#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */\n#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos        (16U)                                           \n#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */\n#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos        (24U)                                           \n#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */\n#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos        (0U)                                            \n#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */\n#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos        (16U)                                           \n#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */\n#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */\n#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */\n#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */\n#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos        (20U)                                           \n#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */\n#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */\n#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */\n#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos        (24U)                                           \n#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */\n#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */\n#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos       (30U)                                           \n#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */\n#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos       (31U)                                           \n#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */\n#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */\n\n\n/*!<Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos      (0U)                                            \n#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos       (1U)                                            \n#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos       (2U)                                            \n#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI0R_EXID_Pos      (3U)                                            \n#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI0R_STID_Pos      (21U)                                           \n#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos      (0U)                                            \n#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT0R_TGT_Pos      (8U)                                            \n#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos     (16U)                                           \n#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos    (0U)                                            \n#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos    (8U)                                            \n#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos    (16U)                                           \n#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos    (24U)                                           \n#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos    (0U)                                            \n#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos    (8U)                                            \n#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos    (16U)                                           \n#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos    (24U)                                           \n#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos      (0U)                                            \n#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos       (1U)                                            \n#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos       (2U)                                            \n#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI1R_EXID_Pos      (3U)                                            \n#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_TI1R_STID_Pos      (21U)                                           \n#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos      (0U)                                            \n#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT1R_TGT_Pos      (8U)                                            \n#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos     (16U)                                           \n#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos    (0U)                                            \n#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos    (8U)                                            \n#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos    (16U)                                           \n#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos    (24U)                                           \n#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos    (0U)                                            \n#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos    (8U)                                            \n#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos    (16U)                                           \n#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos    (24U)                                           \n#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos      (0U)                                            \n#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos       (1U)                                            \n#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos       (2U)                                            \n#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_TI2R_EXID_Pos      (3U)                                            \n#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_TI2R_STID_Pos      (21U)                                           \n#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/  \n#define CAN_TDT2R_DLC_Pos      (0U)                                            \n#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_TDT2R_TGT_Pos      (8U)                                            \n#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */\n#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos     (16U)                                           \n#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos    (0U)                                            \n#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos    (8U)                                            \n#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos    (16U)                                           \n#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos    (24U)                                           \n#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos    (0U)                                            \n#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos    (8U)                                            \n#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos    (16U)                                           \n#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos    (24U)                                           \n#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos       (1U)                                            \n#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos       (2U)                                            \n#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI0R_EXID_Pos      (3U)                                            \n#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */\n#define CAN_RI0R_STID_Pos      (21U)                                           \n#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos      (0U)                                            \n#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT0R_FMI_Pos      (8U)                                            \n#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT0R_TIME_Pos     (16U)                                           \n#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos    (0U)                                            \n#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos    (8U)                                            \n#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos    (16U)                                           \n#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos    (24U)                                           \n#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos    (0U)                                            \n#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos    (8U)                                            \n#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos    (16U)                                           \n#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos    (24U)                                           \n#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos       (1U)                                            \n#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */\n#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos       (2U)                                            \n#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */\n#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */\n#define CAN_RI1R_EXID_Pos      (3U)                                            \n#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */\n#define CAN_RI1R_STID_Pos      (21U)                                           \n#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */\n#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos      (0U)                                            \n#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */\n#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */\n#define CAN_RDT1R_FMI_Pos      (8U)                                            \n#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */\n#define CAN_RDT1R_TIME_Pos     (16U)                                           \n#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos    (0U)                                            \n#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos    (8U)                                            \n#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos    (16U)                                           \n#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos    (24U)                                           \n#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos    (0U)                                            \n#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos    (8U)                                            \n#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos    (16U)                                           \n#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos    (24U)                                           \n#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */\n\n/*!<CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos      (0U)                                            \n#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */\n#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos     (8U)                                            \n#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos       (0U)                                            \n#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */\n#define CAN_FM1R_FBM0_Pos      (0U)                                            \n#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */\n#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */\n#define CAN_FM1R_FBM1_Pos      (1U)                                            \n#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */\n#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */\n#define CAN_FM1R_FBM2_Pos      (2U)                                            \n#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */\n#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */\n#define CAN_FM1R_FBM3_Pos      (3U)                                            \n#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */\n#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */\n#define CAN_FM1R_FBM4_Pos      (4U)                                            \n#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */\n#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */\n#define CAN_FM1R_FBM5_Pos      (5U)                                            \n#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */\n#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */\n#define CAN_FM1R_FBM6_Pos      (6U)                                            \n#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */\n#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */\n#define CAN_FM1R_FBM7_Pos      (7U)                                            \n#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */\n#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */\n#define CAN_FM1R_FBM8_Pos      (8U)                                            \n#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */\n#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */\n#define CAN_FM1R_FBM9_Pos      (9U)                                            \n#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */\n#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */\n#define CAN_FM1R_FBM10_Pos     (10U)                                           \n#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */\n#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */\n#define CAN_FM1R_FBM11_Pos     (11U)                                           \n#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */\n#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */\n#define CAN_FM1R_FBM12_Pos     (12U)                                           \n#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */\n#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */\n#define CAN_FM1R_FBM13_Pos     (13U)                                           \n#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */\n#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */\n#define CAN_FM1R_FBM14_Pos     (14U)                                           \n#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */\n#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */\n#define CAN_FM1R_FBM15_Pos     (15U)                                           \n#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */\n#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */\n#define CAN_FM1R_FBM16_Pos     (16U)                                           \n#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */\n#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */\n#define CAN_FM1R_FBM17_Pos     (17U)                                           \n#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */\n#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */\n#define CAN_FM1R_FBM18_Pos     (18U)                                           \n#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */\n#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */\n#define CAN_FM1R_FBM19_Pos     (19U)                                           \n#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */\n#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */\n#define CAN_FM1R_FBM20_Pos     (20U)                                           \n#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */\n#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */\n#define CAN_FM1R_FBM21_Pos     (21U)                                           \n#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */\n#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */\n#define CAN_FM1R_FBM22_Pos     (22U)                                           \n#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */\n#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */\n#define CAN_FM1R_FBM23_Pos     (23U)                                           \n#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */\n#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */\n#define CAN_FM1R_FBM24_Pos     (24U)                                           \n#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */\n#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */\n#define CAN_FM1R_FBM25_Pos     (25U)                                           \n#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */\n#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */\n#define CAN_FM1R_FBM26_Pos     (26U)                                           \n#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */\n#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */\n#define CAN_FM1R_FBM27_Pos     (27U)                                           \n#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */\n#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos       (0U)                                            \n#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */\n#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos      (0U)                                            \n#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */\n#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */\n#define CAN_FS1R_FSC1_Pos      (1U)                                            \n#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */\n#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */\n#define CAN_FS1R_FSC2_Pos      (2U)                                            \n#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */\n#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */\n#define CAN_FS1R_FSC3_Pos      (3U)                                            \n#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */\n#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */\n#define CAN_FS1R_FSC4_Pos      (4U)                                            \n#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */\n#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */\n#define CAN_FS1R_FSC5_Pos      (5U)                                            \n#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */\n#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */\n#define CAN_FS1R_FSC6_Pos      (6U)                                            \n#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */\n#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */\n#define CAN_FS1R_FSC7_Pos      (7U)                                            \n#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */\n#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */\n#define CAN_FS1R_FSC8_Pos      (8U)                                            \n#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */\n#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */\n#define CAN_FS1R_FSC9_Pos      (9U)                                            \n#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */\n#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */\n#define CAN_FS1R_FSC10_Pos     (10U)                                           \n#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */\n#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */\n#define CAN_FS1R_FSC11_Pos     (11U)                                           \n#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */\n#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */\n#define CAN_FS1R_FSC12_Pos     (12U)                                           \n#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */\n#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */\n#define CAN_FS1R_FSC13_Pos     (13U)                                           \n#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */\n#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */\n#define CAN_FS1R_FSC14_Pos     (14U)                                           \n#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */\n#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */\n#define CAN_FS1R_FSC15_Pos     (15U)                                           \n#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */\n#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */\n#define CAN_FS1R_FSC16_Pos     (16U)                                           \n#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */\n#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */\n#define CAN_FS1R_FSC17_Pos     (17U)                                           \n#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */\n#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */\n#define CAN_FS1R_FSC18_Pos     (18U)                                           \n#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */\n#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */\n#define CAN_FS1R_FSC19_Pos     (19U)                                           \n#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */\n#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */\n#define CAN_FS1R_FSC20_Pos     (20U)                                           \n#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */\n#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */\n#define CAN_FS1R_FSC21_Pos     (21U)                                           \n#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */\n#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */\n#define CAN_FS1R_FSC22_Pos     (22U)                                           \n#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */\n#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */\n#define CAN_FS1R_FSC23_Pos     (23U)                                           \n#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */\n#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */\n#define CAN_FS1R_FSC24_Pos     (24U)                                           \n#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */\n#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */\n#define CAN_FS1R_FSC25_Pos     (25U)                                           \n#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */\n#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */\n#define CAN_FS1R_FSC26_Pos     (26U)                                           \n#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */\n#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */\n#define CAN_FS1R_FSC27_Pos     (27U)                                           \n#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */\n#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos      (0U)                                            \n#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos     (0U)                                            \n#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */\n#define CAN_FFA1R_FFA1_Pos     (1U)                                            \n#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */\n#define CAN_FFA1R_FFA2_Pos     (2U)                                            \n#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */\n#define CAN_FFA1R_FFA3_Pos     (3U)                                            \n#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */\n#define CAN_FFA1R_FFA4_Pos     (4U)                                            \n#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */\n#define CAN_FFA1R_FFA5_Pos     (5U)                                            \n#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */\n#define CAN_FFA1R_FFA6_Pos     (6U)                                            \n#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */\n#define CAN_FFA1R_FFA7_Pos     (7U)                                            \n#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */\n#define CAN_FFA1R_FFA8_Pos     (8U)                                            \n#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */\n#define CAN_FFA1R_FFA9_Pos     (9U)                                            \n#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */\n#define CAN_FFA1R_FFA10_Pos    (10U)                                           \n#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */\n#define CAN_FFA1R_FFA11_Pos    (11U)                                           \n#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */\n#define CAN_FFA1R_FFA12_Pos    (12U)                                           \n#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */\n#define CAN_FFA1R_FFA13_Pos    (13U)                                           \n#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */\n#define CAN_FFA1R_FFA14_Pos    (14U)                                           \n#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */\n#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */\n#define CAN_FFA1R_FFA15_Pos    (15U)                                           \n#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */\n#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */\n#define CAN_FFA1R_FFA16_Pos    (16U)                                           \n#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */\n#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */\n#define CAN_FFA1R_FFA17_Pos    (17U)                                           \n#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */\n#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */\n#define CAN_FFA1R_FFA18_Pos    (18U)                                           \n#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */\n#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */\n#define CAN_FFA1R_FFA19_Pos    (19U)                                           \n#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */\n#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */\n#define CAN_FFA1R_FFA20_Pos    (20U)                                           \n#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */\n#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */\n#define CAN_FFA1R_FFA21_Pos    (21U)                                           \n#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */\n#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */\n#define CAN_FFA1R_FFA22_Pos    (22U)                                           \n#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */\n#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */\n#define CAN_FFA1R_FFA23_Pos    (23U)                                           \n#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */\n#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */\n#define CAN_FFA1R_FFA24_Pos    (24U)                                           \n#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */\n#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */\n#define CAN_FFA1R_FFA25_Pos    (25U)                                           \n#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */\n#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */\n#define CAN_FFA1R_FFA26_Pos    (26U)                                           \n#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */\n#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */\n#define CAN_FFA1R_FFA27_Pos    (27U)                                           \n#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */\n#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos      (0U)                                            \n#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */\n#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */\n#define CAN_FA1R_FACT0_Pos     (0U)                                            \n#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */\n#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */\n#define CAN_FA1R_FACT1_Pos     (1U)                                            \n#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */\n#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */\n#define CAN_FA1R_FACT2_Pos     (2U)                                            \n#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */\n#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */\n#define CAN_FA1R_FACT3_Pos     (3U)                                            \n#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */\n#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */\n#define CAN_FA1R_FACT4_Pos     (4U)                                            \n#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */\n#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */\n#define CAN_FA1R_FACT5_Pos     (5U)                                            \n#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */\n#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */\n#define CAN_FA1R_FACT6_Pos     (6U)                                            \n#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */\n#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */\n#define CAN_FA1R_FACT7_Pos     (7U)                                            \n#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */\n#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */\n#define CAN_FA1R_FACT8_Pos     (8U)                                            \n#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */\n#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */\n#define CAN_FA1R_FACT9_Pos     (9U)                                            \n#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */\n#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */\n#define CAN_FA1R_FACT10_Pos    (10U)                                           \n#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */\n#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */\n#define CAN_FA1R_FACT11_Pos    (11U)                                           \n#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */\n#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */\n#define CAN_FA1R_FACT12_Pos    (12U)                                           \n#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */\n#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */\n#define CAN_FA1R_FACT13_Pos    (13U)                                           \n#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */\n#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */\n#define CAN_FA1R_FACT14_Pos    (14U)                                           \n#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */\n#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */\n#define CAN_FA1R_FACT15_Pos    (15U)                                           \n#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */\n#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */\n#define CAN_FA1R_FACT16_Pos    (16U)                                           \n#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */\n#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */\n#define CAN_FA1R_FACT17_Pos    (17U)                                           \n#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */\n#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */\n#define CAN_FA1R_FACT18_Pos    (18U)                                           \n#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */\n#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */\n#define CAN_FA1R_FACT19_Pos    (19U)                                           \n#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */\n#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */\n#define CAN_FA1R_FACT20_Pos    (20U)                                           \n#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */\n#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */\n#define CAN_FA1R_FACT21_Pos    (21U)                                           \n#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */\n#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */\n#define CAN_FA1R_FACT22_Pos    (22U)                                           \n#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */\n#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */\n#define CAN_FA1R_FACT23_Pos    (23U)                                           \n#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */\n#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */\n#define CAN_FA1R_FACT24_Pos    (24U)                                           \n#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */\n#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */\n#define CAN_FA1R_FACT25_Pos    (25U)                                           \n#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */\n#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */\n#define CAN_FA1R_FACT26_Pos    (26U)                                           \n#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */\n#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */\n#define CAN_FA1R_FACT27_Pos    (27U)                                           \n#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */\n#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */\n\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos       (0U)                                            \n#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R1_FB1_Pos       (1U)                                            \n#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R1_FB2_Pos       (2U)                                            \n#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R1_FB3_Pos       (3U)                                            \n#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R1_FB4_Pos       (4U)                                            \n#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R1_FB5_Pos       (5U)                                            \n#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R1_FB6_Pos       (6U)                                            \n#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R1_FB7_Pos       (7U)                                            \n#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R1_FB8_Pos       (8U)                                            \n#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R1_FB9_Pos       (9U)                                            \n#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R1_FB10_Pos      (10U)                                           \n#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R1_FB11_Pos      (11U)                                           \n#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R1_FB12_Pos      (12U)                                           \n#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R1_FB13_Pos      (13U)                                           \n#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R1_FB14_Pos      (14U)                                           \n#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R1_FB15_Pos      (15U)                                           \n#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R1_FB16_Pos      (16U)                                           \n#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R1_FB17_Pos      (17U)                                           \n#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R1_FB18_Pos      (18U)                                           \n#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R1_FB19_Pos      (19U)                                           \n#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R1_FB20_Pos      (20U)                                           \n#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R1_FB21_Pos      (21U)                                           \n#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R1_FB22_Pos      (22U)                                           \n#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R1_FB23_Pos      (23U)                                           \n#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R1_FB24_Pos      (24U)                                           \n#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R1_FB25_Pos      (25U)                                           \n#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R1_FB26_Pos      (26U)                                           \n#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R1_FB27_Pos      (27U)                                           \n#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R1_FB28_Pos      (28U)                                           \n#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R1_FB29_Pos      (29U)                                           \n#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R1_FB30_Pos      (30U)                                           \n#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R1_FB31_Pos      (31U)                                           \n#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos       (0U)                                            \n#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R1_FB1_Pos       (1U)                                            \n#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R1_FB2_Pos       (2U)                                            \n#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R1_FB3_Pos       (3U)                                            \n#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R1_FB4_Pos       (4U)                                            \n#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R1_FB5_Pos       (5U)                                            \n#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R1_FB6_Pos       (6U)                                            \n#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R1_FB7_Pos       (7U)                                            \n#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R1_FB8_Pos       (8U)                                            \n#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R1_FB9_Pos       (9U)                                            \n#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R1_FB10_Pos      (10U)                                           \n#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R1_FB11_Pos      (11U)                                           \n#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R1_FB12_Pos      (12U)                                           \n#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R1_FB13_Pos      (13U)                                           \n#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R1_FB14_Pos      (14U)                                           \n#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R1_FB15_Pos      (15U)                                           \n#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R1_FB16_Pos      (16U)                                           \n#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R1_FB17_Pos      (17U)                                           \n#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R1_FB18_Pos      (18U)                                           \n#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R1_FB19_Pos      (19U)                                           \n#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R1_FB20_Pos      (20U)                                           \n#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R1_FB21_Pos      (21U)                                           \n#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R1_FB22_Pos      (22U)                                           \n#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R1_FB23_Pos      (23U)                                           \n#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R1_FB24_Pos      (24U)                                           \n#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R1_FB25_Pos      (25U)                                           \n#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R1_FB26_Pos      (26U)                                           \n#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R1_FB27_Pos      (27U)                                           \n#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R1_FB28_Pos      (28U)                                           \n#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R1_FB29_Pos      (29U)                                           \n#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R1_FB30_Pos      (30U)                                           \n#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R1_FB31_Pos      (31U)                                           \n#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos       (0U)                                            \n#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R1_FB1_Pos       (1U)                                            \n#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R1_FB2_Pos       (2U)                                            \n#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R1_FB3_Pos       (3U)                                            \n#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R1_FB4_Pos       (4U)                                            \n#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R1_FB5_Pos       (5U)                                            \n#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R1_FB6_Pos       (6U)                                            \n#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R1_FB7_Pos       (7U)                                            \n#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R1_FB8_Pos       (8U)                                            \n#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R1_FB9_Pos       (9U)                                            \n#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R1_FB10_Pos      (10U)                                           \n#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R1_FB11_Pos      (11U)                                           \n#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R1_FB12_Pos      (12U)                                           \n#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R1_FB13_Pos      (13U)                                           \n#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R1_FB14_Pos      (14U)                                           \n#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R1_FB15_Pos      (15U)                                           \n#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R1_FB16_Pos      (16U)                                           \n#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R1_FB17_Pos      (17U)                                           \n#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R1_FB18_Pos      (18U)                                           \n#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R1_FB19_Pos      (19U)                                           \n#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R1_FB20_Pos      (20U)                                           \n#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R1_FB21_Pos      (21U)                                           \n#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R1_FB22_Pos      (22U)                                           \n#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R1_FB23_Pos      (23U)                                           \n#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R1_FB24_Pos      (24U)                                           \n#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R1_FB25_Pos      (25U)                                           \n#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R1_FB26_Pos      (26U)                                           \n#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R1_FB27_Pos      (27U)                                           \n#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R1_FB28_Pos      (28U)                                           \n#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R1_FB29_Pos      (29U)                                           \n#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R1_FB30_Pos      (30U)                                           \n#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R1_FB31_Pos      (31U)                                           \n#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos       (0U)                                            \n#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R1_FB1_Pos       (1U)                                            \n#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R1_FB2_Pos       (2U)                                            \n#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R1_FB3_Pos       (3U)                                            \n#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R1_FB4_Pos       (4U)                                            \n#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R1_FB5_Pos       (5U)                                            \n#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R1_FB6_Pos       (6U)                                            \n#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R1_FB7_Pos       (7U)                                            \n#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R1_FB8_Pos       (8U)                                            \n#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R1_FB9_Pos       (9U)                                            \n#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R1_FB10_Pos      (10U)                                           \n#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R1_FB11_Pos      (11U)                                           \n#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R1_FB12_Pos      (12U)                                           \n#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R1_FB13_Pos      (13U)                                           \n#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R1_FB14_Pos      (14U)                                           \n#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R1_FB15_Pos      (15U)                                           \n#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R1_FB16_Pos      (16U)                                           \n#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R1_FB17_Pos      (17U)                                           \n#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R1_FB18_Pos      (18U)                                           \n#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R1_FB19_Pos      (19U)                                           \n#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R1_FB20_Pos      (20U)                                           \n#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R1_FB21_Pos      (21U)                                           \n#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R1_FB22_Pos      (22U)                                           \n#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R1_FB23_Pos      (23U)                                           \n#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R1_FB24_Pos      (24U)                                           \n#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R1_FB25_Pos      (25U)                                           \n#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R1_FB26_Pos      (26U)                                           \n#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R1_FB27_Pos      (27U)                                           \n#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R1_FB28_Pos      (28U)                                           \n#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R1_FB29_Pos      (29U)                                           \n#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R1_FB30_Pos      (30U)                                           \n#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R1_FB31_Pos      (31U)                                           \n#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos       (0U)                                            \n#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R1_FB1_Pos       (1U)                                            \n#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R1_FB2_Pos       (2U)                                            \n#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R1_FB3_Pos       (3U)                                            \n#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R1_FB4_Pos       (4U)                                            \n#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R1_FB5_Pos       (5U)                                            \n#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R1_FB6_Pos       (6U)                                            \n#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R1_FB7_Pos       (7U)                                            \n#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R1_FB8_Pos       (8U)                                            \n#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R1_FB9_Pos       (9U)                                            \n#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R1_FB10_Pos      (10U)                                           \n#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R1_FB11_Pos      (11U)                                           \n#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R1_FB12_Pos      (12U)                                           \n#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R1_FB13_Pos      (13U)                                           \n#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R1_FB14_Pos      (14U)                                           \n#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R1_FB15_Pos      (15U)                                           \n#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R1_FB16_Pos      (16U)                                           \n#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R1_FB17_Pos      (17U)                                           \n#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R1_FB18_Pos      (18U)                                           \n#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R1_FB19_Pos      (19U)                                           \n#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R1_FB20_Pos      (20U)                                           \n#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R1_FB21_Pos      (21U)                                           \n#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R1_FB22_Pos      (22U)                                           \n#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R1_FB23_Pos      (23U)                                           \n#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R1_FB24_Pos      (24U)                                           \n#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R1_FB25_Pos      (25U)                                           \n#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R1_FB26_Pos      (26U)                                           \n#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R1_FB27_Pos      (27U)                                           \n#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R1_FB28_Pos      (28U)                                           \n#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R1_FB29_Pos      (29U)                                           \n#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R1_FB30_Pos      (30U)                                           \n#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R1_FB31_Pos      (31U)                                           \n#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos       (0U)                                            \n#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R1_FB1_Pos       (1U)                                            \n#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R1_FB2_Pos       (2U)                                            \n#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R1_FB3_Pos       (3U)                                            \n#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R1_FB4_Pos       (4U)                                            \n#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R1_FB5_Pos       (5U)                                            \n#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R1_FB6_Pos       (6U)                                            \n#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R1_FB7_Pos       (7U)                                            \n#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R1_FB8_Pos       (8U)                                            \n#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R1_FB9_Pos       (9U)                                            \n#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R1_FB10_Pos      (10U)                                           \n#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R1_FB11_Pos      (11U)                                           \n#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R1_FB12_Pos      (12U)                                           \n#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R1_FB13_Pos      (13U)                                           \n#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R1_FB14_Pos      (14U)                                           \n#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R1_FB15_Pos      (15U)                                           \n#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R1_FB16_Pos      (16U)                                           \n#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R1_FB17_Pos      (17U)                                           \n#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R1_FB18_Pos      (18U)                                           \n#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R1_FB19_Pos      (19U)                                           \n#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R1_FB20_Pos      (20U)                                           \n#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R1_FB21_Pos      (21U)                                           \n#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R1_FB22_Pos      (22U)                                           \n#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R1_FB23_Pos      (23U)                                           \n#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R1_FB24_Pos      (24U)                                           \n#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R1_FB25_Pos      (25U)                                           \n#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R1_FB26_Pos      (26U)                                           \n#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R1_FB27_Pos      (27U)                                           \n#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R1_FB28_Pos      (28U)                                           \n#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R1_FB29_Pos      (29U)                                           \n#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R1_FB30_Pos      (30U)                                           \n#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R1_FB31_Pos      (31U)                                           \n#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos       (0U)                                            \n#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R1_FB1_Pos       (1U)                                            \n#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R1_FB2_Pos       (2U)                                            \n#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R1_FB3_Pos       (3U)                                            \n#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R1_FB4_Pos       (4U)                                            \n#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R1_FB5_Pos       (5U)                                            \n#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R1_FB6_Pos       (6U)                                            \n#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R1_FB7_Pos       (7U)                                            \n#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R1_FB8_Pos       (8U)                                            \n#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R1_FB9_Pos       (9U)                                            \n#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R1_FB10_Pos      (10U)                                           \n#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R1_FB11_Pos      (11U)                                           \n#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R1_FB12_Pos      (12U)                                           \n#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R1_FB13_Pos      (13U)                                           \n#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R1_FB14_Pos      (14U)                                           \n#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R1_FB15_Pos      (15U)                                           \n#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R1_FB16_Pos      (16U)                                           \n#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R1_FB17_Pos      (17U)                                           \n#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R1_FB18_Pos      (18U)                                           \n#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R1_FB19_Pos      (19U)                                           \n#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R1_FB20_Pos      (20U)                                           \n#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R1_FB21_Pos      (21U)                                           \n#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R1_FB22_Pos      (22U)                                           \n#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R1_FB23_Pos      (23U)                                           \n#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R1_FB24_Pos      (24U)                                           \n#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R1_FB25_Pos      (25U)                                           \n#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R1_FB26_Pos      (26U)                                           \n#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R1_FB27_Pos      (27U)                                           \n#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R1_FB28_Pos      (28U)                                           \n#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R1_FB29_Pos      (29U)                                           \n#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R1_FB30_Pos      (30U)                                           \n#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R1_FB31_Pos      (31U)                                           \n#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos       (0U)                                            \n#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R1_FB1_Pos       (1U)                                            \n#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R1_FB2_Pos       (2U)                                            \n#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R1_FB3_Pos       (3U)                                            \n#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R1_FB4_Pos       (4U)                                            \n#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R1_FB5_Pos       (5U)                                            \n#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R1_FB6_Pos       (6U)                                            \n#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R1_FB7_Pos       (7U)                                            \n#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R1_FB8_Pos       (8U)                                            \n#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R1_FB9_Pos       (9U)                                            \n#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R1_FB10_Pos      (10U)                                           \n#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R1_FB11_Pos      (11U)                                           \n#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R1_FB12_Pos      (12U)                                           \n#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R1_FB13_Pos      (13U)                                           \n#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R1_FB14_Pos      (14U)                                           \n#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R1_FB15_Pos      (15U)                                           \n#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R1_FB16_Pos      (16U)                                           \n#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R1_FB17_Pos      (17U)                                           \n#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R1_FB18_Pos      (18U)                                           \n#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R1_FB19_Pos      (19U)                                           \n#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R1_FB20_Pos      (20U)                                           \n#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R1_FB21_Pos      (21U)                                           \n#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R1_FB22_Pos      (22U)                                           \n#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R1_FB23_Pos      (23U)                                           \n#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R1_FB24_Pos      (24U)                                           \n#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R1_FB25_Pos      (25U)                                           \n#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R1_FB26_Pos      (26U)                                           \n#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R1_FB27_Pos      (27U)                                           \n#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R1_FB28_Pos      (28U)                                           \n#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R1_FB29_Pos      (29U)                                           \n#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R1_FB30_Pos      (30U)                                           \n#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R1_FB31_Pos      (31U)                                           \n#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos       (0U)                                            \n#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R1_FB1_Pos       (1U)                                            \n#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R1_FB2_Pos       (2U)                                            \n#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R1_FB3_Pos       (3U)                                            \n#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R1_FB4_Pos       (4U)                                            \n#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R1_FB5_Pos       (5U)                                            \n#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R1_FB6_Pos       (6U)                                            \n#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R1_FB7_Pos       (7U)                                            \n#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R1_FB8_Pos       (8U)                                            \n#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R1_FB9_Pos       (9U)                                            \n#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R1_FB10_Pos      (10U)                                           \n#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R1_FB11_Pos      (11U)                                           \n#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R1_FB12_Pos      (12U)                                           \n#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R1_FB13_Pos      (13U)                                           \n#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R1_FB14_Pos      (14U)                                           \n#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R1_FB15_Pos      (15U)                                           \n#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R1_FB16_Pos      (16U)                                           \n#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R1_FB17_Pos      (17U)                                           \n#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R1_FB18_Pos      (18U)                                           \n#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R1_FB19_Pos      (19U)                                           \n#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R1_FB20_Pos      (20U)                                           \n#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R1_FB21_Pos      (21U)                                           \n#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R1_FB22_Pos      (22U)                                           \n#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R1_FB23_Pos      (23U)                                           \n#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R1_FB24_Pos      (24U)                                           \n#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R1_FB25_Pos      (25U)                                           \n#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R1_FB26_Pos      (26U)                                           \n#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R1_FB27_Pos      (27U)                                           \n#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R1_FB28_Pos      (28U)                                           \n#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R1_FB29_Pos      (29U)                                           \n#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R1_FB30_Pos      (30U)                                           \n#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R1_FB31_Pos      (31U)                                           \n#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos       (0U)                                            \n#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R1_FB1_Pos       (1U)                                            \n#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R1_FB2_Pos       (2U)                                            \n#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R1_FB3_Pos       (3U)                                            \n#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R1_FB4_Pos       (4U)                                            \n#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R1_FB5_Pos       (5U)                                            \n#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R1_FB6_Pos       (6U)                                            \n#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R1_FB7_Pos       (7U)                                            \n#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R1_FB8_Pos       (8U)                                            \n#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R1_FB9_Pos       (9U)                                            \n#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R1_FB10_Pos      (10U)                                           \n#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R1_FB11_Pos      (11U)                                           \n#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R1_FB12_Pos      (12U)                                           \n#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R1_FB13_Pos      (13U)                                           \n#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R1_FB14_Pos      (14U)                                           \n#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R1_FB15_Pos      (15U)                                           \n#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R1_FB16_Pos      (16U)                                           \n#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R1_FB17_Pos      (17U)                                           \n#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R1_FB18_Pos      (18U)                                           \n#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R1_FB19_Pos      (19U)                                           \n#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R1_FB20_Pos      (20U)                                           \n#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R1_FB21_Pos      (21U)                                           \n#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R1_FB22_Pos      (22U)                                           \n#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R1_FB23_Pos      (23U)                                           \n#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R1_FB24_Pos      (24U)                                           \n#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R1_FB25_Pos      (25U)                                           \n#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R1_FB26_Pos      (26U)                                           \n#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R1_FB27_Pos      (27U)                                           \n#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R1_FB28_Pos      (28U)                                           \n#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R1_FB29_Pos      (29U)                                           \n#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R1_FB30_Pos      (30U)                                           \n#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R1_FB31_Pos      (31U)                                           \n#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos      (0U)                                            \n#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R1_FB1_Pos      (1U)                                            \n#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R1_FB2_Pos      (2U)                                            \n#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R1_FB3_Pos      (3U)                                            \n#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R1_FB4_Pos      (4U)                                            \n#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R1_FB5_Pos      (5U)                                            \n#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R1_FB6_Pos      (6U)                                            \n#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R1_FB7_Pos      (7U)                                            \n#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R1_FB8_Pos      (8U)                                            \n#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R1_FB9_Pos      (9U)                                            \n#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R1_FB10_Pos     (10U)                                           \n#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R1_FB11_Pos     (11U)                                           \n#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R1_FB12_Pos     (12U)                                           \n#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R1_FB13_Pos     (13U)                                           \n#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R1_FB14_Pos     (14U)                                           \n#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R1_FB15_Pos     (15U)                                           \n#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R1_FB16_Pos     (16U)                                           \n#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R1_FB17_Pos     (17U)                                           \n#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R1_FB18_Pos     (18U)                                           \n#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R1_FB19_Pos     (19U)                                           \n#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R1_FB20_Pos     (20U)                                           \n#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R1_FB21_Pos     (21U)                                           \n#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R1_FB22_Pos     (22U)                                           \n#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R1_FB23_Pos     (23U)                                           \n#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R1_FB24_Pos     (24U)                                           \n#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R1_FB25_Pos     (25U)                                           \n#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R1_FB26_Pos     (26U)                                           \n#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R1_FB27_Pos     (27U)                                           \n#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R1_FB28_Pos     (28U)                                           \n#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R1_FB29_Pos     (29U)                                           \n#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R1_FB30_Pos     (30U)                                           \n#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R1_FB31_Pos     (31U)                                           \n#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos      (0U)                                            \n#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R1_FB1_Pos      (1U)                                            \n#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R1_FB2_Pos      (2U)                                            \n#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R1_FB3_Pos      (3U)                                            \n#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R1_FB4_Pos      (4U)                                            \n#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R1_FB5_Pos      (5U)                                            \n#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R1_FB6_Pos      (6U)                                            \n#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R1_FB7_Pos      (7U)                                            \n#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R1_FB8_Pos      (8U)                                            \n#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R1_FB9_Pos      (9U)                                            \n#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R1_FB10_Pos     (10U)                                           \n#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R1_FB11_Pos     (11U)                                           \n#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R1_FB12_Pos     (12U)                                           \n#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R1_FB13_Pos     (13U)                                           \n#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R1_FB14_Pos     (14U)                                           \n#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R1_FB15_Pos     (15U)                                           \n#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R1_FB16_Pos     (16U)                                           \n#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R1_FB17_Pos     (17U)                                           \n#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R1_FB18_Pos     (18U)                                           \n#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R1_FB19_Pos     (19U)                                           \n#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R1_FB20_Pos     (20U)                                           \n#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R1_FB21_Pos     (21U)                                           \n#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R1_FB22_Pos     (22U)                                           \n#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R1_FB23_Pos     (23U)                                           \n#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R1_FB24_Pos     (24U)                                           \n#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R1_FB25_Pos     (25U)                                           \n#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R1_FB26_Pos     (26U)                                           \n#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R1_FB27_Pos     (27U)                                           \n#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R1_FB28_Pos     (28U)                                           \n#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R1_FB29_Pos     (29U)                                           \n#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R1_FB30_Pos     (30U)                                           \n#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R1_FB31_Pos     (31U)                                           \n#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos      (0U)                                            \n#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R1_FB1_Pos      (1U)                                            \n#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R1_FB2_Pos      (2U)                                            \n#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R1_FB3_Pos      (3U)                                            \n#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R1_FB4_Pos      (4U)                                            \n#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R1_FB5_Pos      (5U)                                            \n#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R1_FB6_Pos      (6U)                                            \n#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R1_FB7_Pos      (7U)                                            \n#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R1_FB8_Pos      (8U)                                            \n#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R1_FB9_Pos      (9U)                                            \n#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R1_FB10_Pos     (10U)                                           \n#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R1_FB11_Pos     (11U)                                           \n#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R1_FB12_Pos     (12U)                                           \n#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R1_FB13_Pos     (13U)                                           \n#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R1_FB14_Pos     (14U)                                           \n#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R1_FB15_Pos     (15U)                                           \n#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R1_FB16_Pos     (16U)                                           \n#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R1_FB17_Pos     (17U)                                           \n#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R1_FB18_Pos     (18U)                                           \n#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R1_FB19_Pos     (19U)                                           \n#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R1_FB20_Pos     (20U)                                           \n#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R1_FB21_Pos     (21U)                                           \n#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R1_FB22_Pos     (22U)                                           \n#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R1_FB23_Pos     (23U)                                           \n#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R1_FB24_Pos     (24U)                                           \n#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R1_FB25_Pos     (25U)                                           \n#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R1_FB26_Pos     (26U)                                           \n#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R1_FB27_Pos     (27U)                                           \n#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R1_FB28_Pos     (28U)                                           \n#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R1_FB29_Pos     (29U)                                           \n#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R1_FB30_Pos     (30U)                                           \n#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R1_FB31_Pos     (31U)                                           \n#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos      (0U)                                            \n#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R1_FB1_Pos      (1U)                                            \n#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R1_FB2_Pos      (2U)                                            \n#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R1_FB3_Pos      (3U)                                            \n#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R1_FB4_Pos      (4U)                                            \n#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R1_FB5_Pos      (5U)                                            \n#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R1_FB6_Pos      (6U)                                            \n#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R1_FB7_Pos      (7U)                                            \n#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R1_FB8_Pos      (8U)                                            \n#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R1_FB9_Pos      (9U)                                            \n#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R1_FB10_Pos     (10U)                                           \n#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R1_FB11_Pos     (11U)                                           \n#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R1_FB12_Pos     (12U)                                           \n#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R1_FB13_Pos     (13U)                                           \n#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R1_FB14_Pos     (14U)                                           \n#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R1_FB15_Pos     (15U)                                           \n#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R1_FB16_Pos     (16U)                                           \n#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R1_FB17_Pos     (17U)                                           \n#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R1_FB18_Pos     (18U)                                           \n#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R1_FB19_Pos     (19U)                                           \n#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R1_FB20_Pos     (20U)                                           \n#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R1_FB21_Pos     (21U)                                           \n#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R1_FB22_Pos     (22U)                                           \n#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R1_FB23_Pos     (23U)                                           \n#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R1_FB24_Pos     (24U)                                           \n#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R1_FB25_Pos     (25U)                                           \n#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R1_FB26_Pos     (26U)                                           \n#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R1_FB27_Pos     (27U)                                           \n#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R1_FB28_Pos     (28U)                                           \n#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R1_FB29_Pos     (29U)                                           \n#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R1_FB30_Pos     (30U)                                           \n#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R1_FB31_Pos     (31U)                                           \n#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos       (0U)                                            \n#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F0R2_FB1_Pos       (1U)                                            \n#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F0R2_FB2_Pos       (2U)                                            \n#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F0R2_FB3_Pos       (3U)                                            \n#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F0R2_FB4_Pos       (4U)                                            \n#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F0R2_FB5_Pos       (5U)                                            \n#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F0R2_FB6_Pos       (6U)                                            \n#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F0R2_FB7_Pos       (7U)                                            \n#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F0R2_FB8_Pos       (8U)                                            \n#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F0R2_FB9_Pos       (9U)                                            \n#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F0R2_FB10_Pos      (10U)                                           \n#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F0R2_FB11_Pos      (11U)                                           \n#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F0R2_FB12_Pos      (12U)                                           \n#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F0R2_FB13_Pos      (13U)                                           \n#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F0R2_FB14_Pos      (14U)                                           \n#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F0R2_FB15_Pos      (15U)                                           \n#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F0R2_FB16_Pos      (16U)                                           \n#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F0R2_FB17_Pos      (17U)                                           \n#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F0R2_FB18_Pos      (18U)                                           \n#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F0R2_FB19_Pos      (19U)                                           \n#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F0R2_FB20_Pos      (20U)                                           \n#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F0R2_FB21_Pos      (21U)                                           \n#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F0R2_FB22_Pos      (22U)                                           \n#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F0R2_FB23_Pos      (23U)                                           \n#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F0R2_FB24_Pos      (24U)                                           \n#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F0R2_FB25_Pos      (25U)                                           \n#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F0R2_FB26_Pos      (26U)                                           \n#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F0R2_FB27_Pos      (27U)                                           \n#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F0R2_FB28_Pos      (28U)                                           \n#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F0R2_FB29_Pos      (29U)                                           \n#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F0R2_FB30_Pos      (30U)                                           \n#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F0R2_FB31_Pos      (31U)                                           \n#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos       (0U)                                            \n#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F1R2_FB1_Pos       (1U)                                            \n#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F1R2_FB2_Pos       (2U)                                            \n#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F1R2_FB3_Pos       (3U)                                            \n#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F1R2_FB4_Pos       (4U)                                            \n#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F1R2_FB5_Pos       (5U)                                            \n#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F1R2_FB6_Pos       (6U)                                            \n#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F1R2_FB7_Pos       (7U)                                            \n#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F1R2_FB8_Pos       (8U)                                            \n#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F1R2_FB9_Pos       (9U)                                            \n#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F1R2_FB10_Pos      (10U)                                           \n#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F1R2_FB11_Pos      (11U)                                           \n#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F1R2_FB12_Pos      (12U)                                           \n#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F1R2_FB13_Pos      (13U)                                           \n#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F1R2_FB14_Pos      (14U)                                           \n#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F1R2_FB15_Pos      (15U)                                           \n#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F1R2_FB16_Pos      (16U)                                           \n#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F1R2_FB17_Pos      (17U)                                           \n#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F1R2_FB18_Pos      (18U)                                           \n#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F1R2_FB19_Pos      (19U)                                           \n#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F1R2_FB20_Pos      (20U)                                           \n#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F1R2_FB21_Pos      (21U)                                           \n#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F1R2_FB22_Pos      (22U)                                           \n#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F1R2_FB23_Pos      (23U)                                           \n#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F1R2_FB24_Pos      (24U)                                           \n#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F1R2_FB25_Pos      (25U)                                           \n#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F1R2_FB26_Pos      (26U)                                           \n#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F1R2_FB27_Pos      (27U)                                           \n#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F1R2_FB28_Pos      (28U)                                           \n#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F1R2_FB29_Pos      (29U)                                           \n#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F1R2_FB30_Pos      (30U)                                           \n#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F1R2_FB31_Pos      (31U)                                           \n#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos       (0U)                                            \n#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F2R2_FB1_Pos       (1U)                                            \n#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F2R2_FB2_Pos       (2U)                                            \n#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F2R2_FB3_Pos       (3U)                                            \n#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F2R2_FB4_Pos       (4U)                                            \n#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F2R2_FB5_Pos       (5U)                                            \n#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F2R2_FB6_Pos       (6U)                                            \n#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F2R2_FB7_Pos       (7U)                                            \n#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F2R2_FB8_Pos       (8U)                                            \n#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F2R2_FB9_Pos       (9U)                                            \n#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F2R2_FB10_Pos      (10U)                                           \n#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F2R2_FB11_Pos      (11U)                                           \n#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F2R2_FB12_Pos      (12U)                                           \n#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F2R2_FB13_Pos      (13U)                                           \n#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F2R2_FB14_Pos      (14U)                                           \n#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F2R2_FB15_Pos      (15U)                                           \n#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F2R2_FB16_Pos      (16U)                                           \n#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F2R2_FB17_Pos      (17U)                                           \n#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F2R2_FB18_Pos      (18U)                                           \n#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F2R2_FB19_Pos      (19U)                                           \n#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F2R2_FB20_Pos      (20U)                                           \n#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F2R2_FB21_Pos      (21U)                                           \n#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F2R2_FB22_Pos      (22U)                                           \n#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F2R2_FB23_Pos      (23U)                                           \n#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F2R2_FB24_Pos      (24U)                                           \n#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F2R2_FB25_Pos      (25U)                                           \n#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F2R2_FB26_Pos      (26U)                                           \n#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F2R2_FB27_Pos      (27U)                                           \n#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F2R2_FB28_Pos      (28U)                                           \n#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F2R2_FB29_Pos      (29U)                                           \n#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F2R2_FB30_Pos      (30U)                                           \n#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F2R2_FB31_Pos      (31U)                                           \n#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos       (0U)                                            \n#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F3R2_FB1_Pos       (1U)                                            \n#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F3R2_FB2_Pos       (2U)                                            \n#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F3R2_FB3_Pos       (3U)                                            \n#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F3R2_FB4_Pos       (4U)                                            \n#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F3R2_FB5_Pos       (5U)                                            \n#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F3R2_FB6_Pos       (6U)                                            \n#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F3R2_FB7_Pos       (7U)                                            \n#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F3R2_FB8_Pos       (8U)                                            \n#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F3R2_FB9_Pos       (9U)                                            \n#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F3R2_FB10_Pos      (10U)                                           \n#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F3R2_FB11_Pos      (11U)                                           \n#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F3R2_FB12_Pos      (12U)                                           \n#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F3R2_FB13_Pos      (13U)                                           \n#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F3R2_FB14_Pos      (14U)                                           \n#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F3R2_FB15_Pos      (15U)                                           \n#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F3R2_FB16_Pos      (16U)                                           \n#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F3R2_FB17_Pos      (17U)                                           \n#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F3R2_FB18_Pos      (18U)                                           \n#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F3R2_FB19_Pos      (19U)                                           \n#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F3R2_FB20_Pos      (20U)                                           \n#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F3R2_FB21_Pos      (21U)                                           \n#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F3R2_FB22_Pos      (22U)                                           \n#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F3R2_FB23_Pos      (23U)                                           \n#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F3R2_FB24_Pos      (24U)                                           \n#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F3R2_FB25_Pos      (25U)                                           \n#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F3R2_FB26_Pos      (26U)                                           \n#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F3R2_FB27_Pos      (27U)                                           \n#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F3R2_FB28_Pos      (28U)                                           \n#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F3R2_FB29_Pos      (29U)                                           \n#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F3R2_FB30_Pos      (30U)                                           \n#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F3R2_FB31_Pos      (31U)                                           \n#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos       (0U)                                            \n#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F4R2_FB1_Pos       (1U)                                            \n#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F4R2_FB2_Pos       (2U)                                            \n#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F4R2_FB3_Pos       (3U)                                            \n#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F4R2_FB4_Pos       (4U)                                            \n#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F4R2_FB5_Pos       (5U)                                            \n#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F4R2_FB6_Pos       (6U)                                            \n#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F4R2_FB7_Pos       (7U)                                            \n#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F4R2_FB8_Pos       (8U)                                            \n#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F4R2_FB9_Pos       (9U)                                            \n#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F4R2_FB10_Pos      (10U)                                           \n#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F4R2_FB11_Pos      (11U)                                           \n#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F4R2_FB12_Pos      (12U)                                           \n#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F4R2_FB13_Pos      (13U)                                           \n#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F4R2_FB14_Pos      (14U)                                           \n#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F4R2_FB15_Pos      (15U)                                           \n#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F4R2_FB16_Pos      (16U)                                           \n#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F4R2_FB17_Pos      (17U)                                           \n#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F4R2_FB18_Pos      (18U)                                           \n#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F4R2_FB19_Pos      (19U)                                           \n#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F4R2_FB20_Pos      (20U)                                           \n#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F4R2_FB21_Pos      (21U)                                           \n#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F4R2_FB22_Pos      (22U)                                           \n#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F4R2_FB23_Pos      (23U)                                           \n#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F4R2_FB24_Pos      (24U)                                           \n#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F4R2_FB25_Pos      (25U)                                           \n#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F4R2_FB26_Pos      (26U)                                           \n#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F4R2_FB27_Pos      (27U)                                           \n#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F4R2_FB28_Pos      (28U)                                           \n#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F4R2_FB29_Pos      (29U)                                           \n#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F4R2_FB30_Pos      (30U)                                           \n#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F4R2_FB31_Pos      (31U)                                           \n#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos       (0U)                                            \n#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F5R2_FB1_Pos       (1U)                                            \n#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F5R2_FB2_Pos       (2U)                                            \n#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F5R2_FB3_Pos       (3U)                                            \n#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F5R2_FB4_Pos       (4U)                                            \n#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F5R2_FB5_Pos       (5U)                                            \n#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F5R2_FB6_Pos       (6U)                                            \n#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F5R2_FB7_Pos       (7U)                                            \n#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F5R2_FB8_Pos       (8U)                                            \n#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F5R2_FB9_Pos       (9U)                                            \n#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F5R2_FB10_Pos      (10U)                                           \n#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F5R2_FB11_Pos      (11U)                                           \n#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F5R2_FB12_Pos      (12U)                                           \n#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F5R2_FB13_Pos      (13U)                                           \n#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F5R2_FB14_Pos      (14U)                                           \n#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F5R2_FB15_Pos      (15U)                                           \n#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F5R2_FB16_Pos      (16U)                                           \n#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F5R2_FB17_Pos      (17U)                                           \n#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F5R2_FB18_Pos      (18U)                                           \n#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F5R2_FB19_Pos      (19U)                                           \n#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F5R2_FB20_Pos      (20U)                                           \n#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F5R2_FB21_Pos      (21U)                                           \n#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F5R2_FB22_Pos      (22U)                                           \n#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F5R2_FB23_Pos      (23U)                                           \n#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F5R2_FB24_Pos      (24U)                                           \n#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F5R2_FB25_Pos      (25U)                                           \n#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F5R2_FB26_Pos      (26U)                                           \n#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F5R2_FB27_Pos      (27U)                                           \n#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F5R2_FB28_Pos      (28U)                                           \n#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F5R2_FB29_Pos      (29U)                                           \n#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F5R2_FB30_Pos      (30U)                                           \n#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F5R2_FB31_Pos      (31U)                                           \n#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos       (0U)                                            \n#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F6R2_FB1_Pos       (1U)                                            \n#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F6R2_FB2_Pos       (2U)                                            \n#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F6R2_FB3_Pos       (3U)                                            \n#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F6R2_FB4_Pos       (4U)                                            \n#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F6R2_FB5_Pos       (5U)                                            \n#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F6R2_FB6_Pos       (6U)                                            \n#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F6R2_FB7_Pos       (7U)                                            \n#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F6R2_FB8_Pos       (8U)                                            \n#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F6R2_FB9_Pos       (9U)                                            \n#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F6R2_FB10_Pos      (10U)                                           \n#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F6R2_FB11_Pos      (11U)                                           \n#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F6R2_FB12_Pos      (12U)                                           \n#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F6R2_FB13_Pos      (13U)                                           \n#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F6R2_FB14_Pos      (14U)                                           \n#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F6R2_FB15_Pos      (15U)                                           \n#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F6R2_FB16_Pos      (16U)                                           \n#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F6R2_FB17_Pos      (17U)                                           \n#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F6R2_FB18_Pos      (18U)                                           \n#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F6R2_FB19_Pos      (19U)                                           \n#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F6R2_FB20_Pos      (20U)                                           \n#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F6R2_FB21_Pos      (21U)                                           \n#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F6R2_FB22_Pos      (22U)                                           \n#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F6R2_FB23_Pos      (23U)                                           \n#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F6R2_FB24_Pos      (24U)                                           \n#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F6R2_FB25_Pos      (25U)                                           \n#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F6R2_FB26_Pos      (26U)                                           \n#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F6R2_FB27_Pos      (27U)                                           \n#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F6R2_FB28_Pos      (28U)                                           \n#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F6R2_FB29_Pos      (29U)                                           \n#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F6R2_FB30_Pos      (30U)                                           \n#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F6R2_FB31_Pos      (31U)                                           \n#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos       (0U)                                            \n#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F7R2_FB1_Pos       (1U)                                            \n#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F7R2_FB2_Pos       (2U)                                            \n#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F7R2_FB3_Pos       (3U)                                            \n#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F7R2_FB4_Pos       (4U)                                            \n#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F7R2_FB5_Pos       (5U)                                            \n#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F7R2_FB6_Pos       (6U)                                            \n#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F7R2_FB7_Pos       (7U)                                            \n#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F7R2_FB8_Pos       (8U)                                            \n#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F7R2_FB9_Pos       (9U)                                            \n#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F7R2_FB10_Pos      (10U)                                           \n#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F7R2_FB11_Pos      (11U)                                           \n#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F7R2_FB12_Pos      (12U)                                           \n#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F7R2_FB13_Pos      (13U)                                           \n#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F7R2_FB14_Pos      (14U)                                           \n#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F7R2_FB15_Pos      (15U)                                           \n#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F7R2_FB16_Pos      (16U)                                           \n#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F7R2_FB17_Pos      (17U)                                           \n#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F7R2_FB18_Pos      (18U)                                           \n#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F7R2_FB19_Pos      (19U)                                           \n#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F7R2_FB20_Pos      (20U)                                           \n#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F7R2_FB21_Pos      (21U)                                           \n#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F7R2_FB22_Pos      (22U)                                           \n#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F7R2_FB23_Pos      (23U)                                           \n#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F7R2_FB24_Pos      (24U)                                           \n#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F7R2_FB25_Pos      (25U)                                           \n#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F7R2_FB26_Pos      (26U)                                           \n#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F7R2_FB27_Pos      (27U)                                           \n#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F7R2_FB28_Pos      (28U)                                           \n#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F7R2_FB29_Pos      (29U)                                           \n#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F7R2_FB30_Pos      (30U)                                           \n#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F7R2_FB31_Pos      (31U)                                           \n#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos       (0U)                                            \n#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F8R2_FB1_Pos       (1U)                                            \n#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F8R2_FB2_Pos       (2U)                                            \n#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F8R2_FB3_Pos       (3U)                                            \n#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F8R2_FB4_Pos       (4U)                                            \n#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F8R2_FB5_Pos       (5U)                                            \n#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F8R2_FB6_Pos       (6U)                                            \n#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F8R2_FB7_Pos       (7U)                                            \n#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F8R2_FB8_Pos       (8U)                                            \n#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F8R2_FB9_Pos       (9U)                                            \n#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F8R2_FB10_Pos      (10U)                                           \n#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F8R2_FB11_Pos      (11U)                                           \n#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F8R2_FB12_Pos      (12U)                                           \n#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F8R2_FB13_Pos      (13U)                                           \n#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F8R2_FB14_Pos      (14U)                                           \n#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F8R2_FB15_Pos      (15U)                                           \n#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F8R2_FB16_Pos      (16U)                                           \n#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F8R2_FB17_Pos      (17U)                                           \n#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F8R2_FB18_Pos      (18U)                                           \n#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F8R2_FB19_Pos      (19U)                                           \n#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F8R2_FB20_Pos      (20U)                                           \n#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F8R2_FB21_Pos      (21U)                                           \n#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F8R2_FB22_Pos      (22U)                                           \n#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F8R2_FB23_Pos      (23U)                                           \n#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F8R2_FB24_Pos      (24U)                                           \n#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F8R2_FB25_Pos      (25U)                                           \n#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F8R2_FB26_Pos      (26U)                                           \n#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F8R2_FB27_Pos      (27U)                                           \n#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F8R2_FB28_Pos      (28U)                                           \n#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F8R2_FB29_Pos      (29U)                                           \n#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F8R2_FB30_Pos      (30U)                                           \n#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F8R2_FB31_Pos      (31U)                                           \n#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos       (0U)                                            \n#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */\n#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */\n#define CAN_F9R2_FB1_Pos       (1U)                                            \n#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */\n#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */\n#define CAN_F9R2_FB2_Pos       (2U)                                            \n#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */\n#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */\n#define CAN_F9R2_FB3_Pos       (3U)                                            \n#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */\n#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */\n#define CAN_F9R2_FB4_Pos       (4U)                                            \n#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */\n#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */\n#define CAN_F9R2_FB5_Pos       (5U)                                            \n#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */\n#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */\n#define CAN_F9R2_FB6_Pos       (6U)                                            \n#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */\n#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */\n#define CAN_F9R2_FB7_Pos       (7U)                                            \n#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */\n#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */\n#define CAN_F9R2_FB8_Pos       (8U)                                            \n#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */\n#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */\n#define CAN_F9R2_FB9_Pos       (9U)                                            \n#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */\n#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */\n#define CAN_F9R2_FB10_Pos      (10U)                                           \n#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */\n#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */\n#define CAN_F9R2_FB11_Pos      (11U)                                           \n#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */\n#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */\n#define CAN_F9R2_FB12_Pos      (12U)                                           \n#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */\n#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */\n#define CAN_F9R2_FB13_Pos      (13U)                                           \n#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */\n#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */\n#define CAN_F9R2_FB14_Pos      (14U)                                           \n#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */\n#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */\n#define CAN_F9R2_FB15_Pos      (15U)                                           \n#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */\n#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */\n#define CAN_F9R2_FB16_Pos      (16U)                                           \n#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */\n#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */\n#define CAN_F9R2_FB17_Pos      (17U)                                           \n#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */\n#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */\n#define CAN_F9R2_FB18_Pos      (18U)                                           \n#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */\n#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */\n#define CAN_F9R2_FB19_Pos      (19U)                                           \n#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */\n#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */\n#define CAN_F9R2_FB20_Pos      (20U)                                           \n#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */\n#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */\n#define CAN_F9R2_FB21_Pos      (21U)                                           \n#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */\n#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */\n#define CAN_F9R2_FB22_Pos      (22U)                                           \n#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */\n#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */\n#define CAN_F9R2_FB23_Pos      (23U)                                           \n#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */\n#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */\n#define CAN_F9R2_FB24_Pos      (24U)                                           \n#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */\n#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */\n#define CAN_F9R2_FB25_Pos      (25U)                                           \n#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */\n#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */\n#define CAN_F9R2_FB26_Pos      (26U)                                           \n#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */\n#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */\n#define CAN_F9R2_FB27_Pos      (27U)                                           \n#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */\n#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */\n#define CAN_F9R2_FB28_Pos      (28U)                                           \n#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */\n#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */\n#define CAN_F9R2_FB29_Pos      (29U)                                           \n#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */\n#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */\n#define CAN_F9R2_FB30_Pos      (30U)                                           \n#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */\n#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */\n#define CAN_F9R2_FB31_Pos      (31U)                                           \n#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */\n#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos      (0U)                                            \n#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F10R2_FB1_Pos      (1U)                                            \n#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F10R2_FB2_Pos      (2U)                                            \n#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F10R2_FB3_Pos      (3U)                                            \n#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F10R2_FB4_Pos      (4U)                                            \n#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F10R2_FB5_Pos      (5U)                                            \n#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F10R2_FB6_Pos      (6U)                                            \n#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F10R2_FB7_Pos      (7U)                                            \n#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F10R2_FB8_Pos      (8U)                                            \n#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F10R2_FB9_Pos      (9U)                                            \n#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F10R2_FB10_Pos     (10U)                                           \n#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F10R2_FB11_Pos     (11U)                                           \n#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F10R2_FB12_Pos     (12U)                                           \n#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F10R2_FB13_Pos     (13U)                                           \n#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F10R2_FB14_Pos     (14U)                                           \n#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F10R2_FB15_Pos     (15U)                                           \n#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F10R2_FB16_Pos     (16U)                                           \n#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F10R2_FB17_Pos     (17U)                                           \n#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F10R2_FB18_Pos     (18U)                                           \n#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F10R2_FB19_Pos     (19U)                                           \n#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F10R2_FB20_Pos     (20U)                                           \n#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F10R2_FB21_Pos     (21U)                                           \n#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F10R2_FB22_Pos     (22U)                                           \n#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F10R2_FB23_Pos     (23U)                                           \n#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F10R2_FB24_Pos     (24U)                                           \n#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F10R2_FB25_Pos     (25U)                                           \n#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F10R2_FB26_Pos     (26U)                                           \n#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F10R2_FB27_Pos     (27U)                                           \n#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F10R2_FB28_Pos     (28U)                                           \n#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F10R2_FB29_Pos     (29U)                                           \n#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F10R2_FB30_Pos     (30U)                                           \n#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F10R2_FB31_Pos     (31U)                                           \n#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos      (0U)                                            \n#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F11R2_FB1_Pos      (1U)                                            \n#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F11R2_FB2_Pos      (2U)                                            \n#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F11R2_FB3_Pos      (3U)                                            \n#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F11R2_FB4_Pos      (4U)                                            \n#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F11R2_FB5_Pos      (5U)                                            \n#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F11R2_FB6_Pos      (6U)                                            \n#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F11R2_FB7_Pos      (7U)                                            \n#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F11R2_FB8_Pos      (8U)                                            \n#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F11R2_FB9_Pos      (9U)                                            \n#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F11R2_FB10_Pos     (10U)                                           \n#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F11R2_FB11_Pos     (11U)                                           \n#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F11R2_FB12_Pos     (12U)                                           \n#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F11R2_FB13_Pos     (13U)                                           \n#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F11R2_FB14_Pos     (14U)                                           \n#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F11R2_FB15_Pos     (15U)                                           \n#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F11R2_FB16_Pos     (16U)                                           \n#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F11R2_FB17_Pos     (17U)                                           \n#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F11R2_FB18_Pos     (18U)                                           \n#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F11R2_FB19_Pos     (19U)                                           \n#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F11R2_FB20_Pos     (20U)                                           \n#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F11R2_FB21_Pos     (21U)                                           \n#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F11R2_FB22_Pos     (22U)                                           \n#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F11R2_FB23_Pos     (23U)                                           \n#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F11R2_FB24_Pos     (24U)                                           \n#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F11R2_FB25_Pos     (25U)                                           \n#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F11R2_FB26_Pos     (26U)                                           \n#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F11R2_FB27_Pos     (27U)                                           \n#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F11R2_FB28_Pos     (28U)                                           \n#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F11R2_FB29_Pos     (29U)                                           \n#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F11R2_FB30_Pos     (30U)                                           \n#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F11R2_FB31_Pos     (31U)                                           \n#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos      (0U)                                            \n#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F12R2_FB1_Pos      (1U)                                            \n#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F12R2_FB2_Pos      (2U)                                            \n#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F12R2_FB3_Pos      (3U)                                            \n#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F12R2_FB4_Pos      (4U)                                            \n#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F12R2_FB5_Pos      (5U)                                            \n#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F12R2_FB6_Pos      (6U)                                            \n#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F12R2_FB7_Pos      (7U)                                            \n#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F12R2_FB8_Pos      (8U)                                            \n#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F12R2_FB9_Pos      (9U)                                            \n#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F12R2_FB10_Pos     (10U)                                           \n#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F12R2_FB11_Pos     (11U)                                           \n#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F12R2_FB12_Pos     (12U)                                           \n#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F12R2_FB13_Pos     (13U)                                           \n#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F12R2_FB14_Pos     (14U)                                           \n#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F12R2_FB15_Pos     (15U)                                           \n#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F12R2_FB16_Pos     (16U)                                           \n#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F12R2_FB17_Pos     (17U)                                           \n#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F12R2_FB18_Pos     (18U)                                           \n#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F12R2_FB19_Pos     (19U)                                           \n#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F12R2_FB20_Pos     (20U)                                           \n#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F12R2_FB21_Pos     (21U)                                           \n#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F12R2_FB22_Pos     (22U)                                           \n#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F12R2_FB23_Pos     (23U)                                           \n#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F12R2_FB24_Pos     (24U)                                           \n#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F12R2_FB25_Pos     (25U)                                           \n#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F12R2_FB26_Pos     (26U)                                           \n#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F12R2_FB27_Pos     (27U)                                           \n#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F12R2_FB28_Pos     (28U)                                           \n#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F12R2_FB29_Pos     (29U)                                           \n#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F12R2_FB30_Pos     (30U)                                           \n#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F12R2_FB31_Pos     (31U)                                           \n#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos      (0U)                                            \n#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */\n#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */\n#define CAN_F13R2_FB1_Pos      (1U)                                            \n#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */\n#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */\n#define CAN_F13R2_FB2_Pos      (2U)                                            \n#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */\n#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */\n#define CAN_F13R2_FB3_Pos      (3U)                                            \n#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */\n#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */\n#define CAN_F13R2_FB4_Pos      (4U)                                            \n#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */\n#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */\n#define CAN_F13R2_FB5_Pos      (5U)                                            \n#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */\n#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */\n#define CAN_F13R2_FB6_Pos      (6U)                                            \n#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */\n#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */\n#define CAN_F13R2_FB7_Pos      (7U)                                            \n#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */\n#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */\n#define CAN_F13R2_FB8_Pos      (8U)                                            \n#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */\n#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */\n#define CAN_F13R2_FB9_Pos      (9U)                                            \n#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */\n#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */\n#define CAN_F13R2_FB10_Pos     (10U)                                           \n#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */\n#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */\n#define CAN_F13R2_FB11_Pos     (11U)                                           \n#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */\n#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */\n#define CAN_F13R2_FB12_Pos     (12U)                                           \n#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */\n#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */\n#define CAN_F13R2_FB13_Pos     (13U)                                           \n#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */\n#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */\n#define CAN_F13R2_FB14_Pos     (14U)                                           \n#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */\n#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */\n#define CAN_F13R2_FB15_Pos     (15U)                                           \n#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */\n#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */\n#define CAN_F13R2_FB16_Pos     (16U)                                           \n#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */\n#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */\n#define CAN_F13R2_FB17_Pos     (17U)                                           \n#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */\n#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */\n#define CAN_F13R2_FB18_Pos     (18U)                                           \n#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */\n#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */\n#define CAN_F13R2_FB19_Pos     (19U)                                           \n#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */\n#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */\n#define CAN_F13R2_FB20_Pos     (20U)                                           \n#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */\n#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */\n#define CAN_F13R2_FB21_Pos     (21U)                                           \n#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */\n#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */\n#define CAN_F13R2_FB22_Pos     (22U)                                           \n#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */\n#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */\n#define CAN_F13R2_FB23_Pos     (23U)                                           \n#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */\n#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */\n#define CAN_F13R2_FB24_Pos     (24U)                                           \n#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */\n#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */\n#define CAN_F13R2_FB25_Pos     (25U)                                           \n#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */\n#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */\n#define CAN_F13R2_FB26_Pos     (26U)                                           \n#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */\n#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */\n#define CAN_F13R2_FB27_Pos     (27U)                                           \n#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */\n#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */\n#define CAN_F13R2_FB28_Pos     (28U)                                           \n#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */\n#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */\n#define CAN_F13R2_FB29_Pos     (29U)                                           \n#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */\n#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */\n#define CAN_F13R2_FB30_Pos     (30U)                                           \n#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */\n#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */\n#define CAN_F13R2_FB31_Pos     (31U)                                           \n#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */\n#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                          CRC calculation unit                              */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos       (0U)                                               \n#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */\n\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos     (0U)                                               \n#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */\n#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */\n\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos    (0U)                                               \n#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */\n#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Digital to Analog Converter                           */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */\n/********************  Bit definition for DAC_CR register  ********************/\n#define DAC_CR_EN1_Pos              (0U)                                       \n#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */\n#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */\n#define DAC_CR_BOFF1_Pos            (1U)                                       \n#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */\n#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */\n#define DAC_CR_TEN1_Pos             (2U)                                       \n#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */\n#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */\n\n#define DAC_CR_TSEL1_Pos            (3U)                                       \n#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */\n#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\n#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */\n#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */\n#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */\n\n#define DAC_CR_WAVE1_Pos            (6U)                                       \n#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */\n#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */\n#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */\n\n#define DAC_CR_MAMP1_Pos            (8U)                                       \n#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */\n#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\n#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */\n#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */\n#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */\n#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */\n\n#define DAC_CR_DMAEN1_Pos           (12U)                                      \n#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */\n#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */\n#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      \n#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */\n#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/\n#define DAC_CR_EN2_Pos              (16U)                                      \n#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */\n#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */\n#define DAC_CR_BOFF2_Pos            (17U)                                      \n#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */\n#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */\n#define DAC_CR_TEN2_Pos             (18U)                                      \n#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */\n#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */\n\n#define DAC_CR_TSEL2_Pos            (19U)                                      \n#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */\n#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\n#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */\n#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */\n#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */\n\n#define DAC_CR_WAVE2_Pos            (22U)                                      \n#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */\n#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\n#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */\n#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */\n\n#define DAC_CR_MAMP2_Pos            (24U)                                      \n#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */\n#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\n#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */\n#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */\n#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */\n#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */\n\n#define DAC_CR_DMAEN2_Pos           (28U)                                      \n#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */\n#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */\n#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      \n#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */\n#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/\n\n/*****************  Bit definition for DAC_SWTRIGR register  ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       \n#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */\n#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       \n#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */\n#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */\n\n/*****************  Bit definition for DAC_DHR12R1 register  ******************/\n#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       \n#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L1 register  ******************/\n#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       \n#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R1 register  ******************/\n#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       \n#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12R2 register  ******************/\n#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       \n#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12L2 register  ******************/\n#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       \n#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8R2 register  ******************/\n#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       \n#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12RD register  ******************/\n#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       \n#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */\n#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */\n#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      \n#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */\n#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */\n\n/*****************  Bit definition for DAC_DHR12LD register  ******************/\n#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       \n#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */\n#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */\n#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      \n#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */\n#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */\n\n/******************  Bit definition for DAC_DHR8RD register  ******************/\n#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       \n#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */\n#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */\n#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       \n#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */\n#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */\n\n/*******************  Bit definition for DAC_DOR1 register  *******************/\n#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       \n#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */\n\n/*******************  Bit definition for DAC_DOR2 register  *******************/\n#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       \n#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */\n#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */\n\n/********************  Bit definition for DAC_SR register  ********************/\n#define DAC_SR_DMAUDR1_Pos          (13U)                                      \n#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */\n#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */\n#define DAC_SR_DMAUDR2_Pos          (29U)                                      \n#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */\n#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for DMA_SxCR register  *****************/\n#define DMA_SxCR_CHSEL_Pos       (25U)                                         \n#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */\n#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            \n#define DMA_SxCR_CHSEL_0         0x02000000U                                   \n#define DMA_SxCR_CHSEL_1         0x04000000U                                   \n#define DMA_SxCR_CHSEL_2         0x08000000U                                   \n#define DMA_SxCR_MBURST_Pos      (23U)                                         \n#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */\n#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           \n#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */\n#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */\n#define DMA_SxCR_PBURST_Pos      (21U)                                         \n#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */\n#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           \n#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */\n#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */\n#define DMA_SxCR_CT_Pos          (19U)                                         \n#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */\n#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               \n#define DMA_SxCR_DBM_Pos         (18U)                                         \n#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */\n#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              \n#define DMA_SxCR_PL_Pos          (16U)                                         \n#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */\n#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               \n#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */\n#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */\n#define DMA_SxCR_PINCOS_Pos      (15U)                                         \n#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */\n#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           \n#define DMA_SxCR_MSIZE_Pos       (13U)                                         \n#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */\n#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            \n#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */\n#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */\n#define DMA_SxCR_PSIZE_Pos       (11U)                                         \n#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */\n#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            \n#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */\n#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */\n#define DMA_SxCR_MINC_Pos        (10U)                                         \n#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */\n#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             \n#define DMA_SxCR_PINC_Pos        (9U)                                          \n#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */\n#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             \n#define DMA_SxCR_CIRC_Pos        (8U)                                          \n#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */\n#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             \n#define DMA_SxCR_DIR_Pos         (6U)                                          \n#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */\n#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              \n#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */\n#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */\n#define DMA_SxCR_PFCTRL_Pos      (5U)                                          \n#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */\n#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           \n#define DMA_SxCR_TCIE_Pos        (4U)                                          \n#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */\n#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             \n#define DMA_SxCR_HTIE_Pos        (3U)                                          \n#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */\n#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             \n#define DMA_SxCR_TEIE_Pos        (2U)                                          \n#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */\n#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             \n#define DMA_SxCR_DMEIE_Pos       (1U)                                          \n#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */\n#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            \n#define DMA_SxCR_EN_Pos          (0U)                                          \n#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */\n#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               \n\n/* Legacy defines */\n#define DMA_SxCR_ACK_Pos         (20U)                                         \n#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */\n#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              \n\n/********************  Bits definition for DMA_SxCNDTR register  **************/\n#define DMA_SxNDT_Pos            (0U)                                          \n#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */\n#define DMA_SxNDT                DMA_SxNDT_Msk                                 \n#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */\n#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */\n#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */\n#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */\n#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */\n#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */\n#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */\n#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */\n#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */\n#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */\n#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */\n#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */\n#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */\n#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */\n#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */\n#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */\n\n/********************  Bits definition for DMA_SxFCR register  ****************/ \n#define DMA_SxFCR_FEIE_Pos       (7U)                                          \n#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */\n#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            \n#define DMA_SxFCR_FS_Pos         (3U)                                          \n#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */\n#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              \n#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */\n#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */\n#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */\n#define DMA_SxFCR_DMDIS_Pos      (2U)                                          \n#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */\n#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           \n#define DMA_SxFCR_FTH_Pos        (0U)                                          \n#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */\n#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             \n#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */\n#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */\n\n/********************  Bits definition for DMA_LISR register  *****************/ \n#define DMA_LISR_TCIF3_Pos       (27U)                                         \n#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */\n#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            \n#define DMA_LISR_HTIF3_Pos       (26U)                                         \n#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */\n#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            \n#define DMA_LISR_TEIF3_Pos       (25U)                                         \n#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */\n#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            \n#define DMA_LISR_DMEIF3_Pos      (24U)                                         \n#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */\n#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           \n#define DMA_LISR_FEIF3_Pos       (22U)                                         \n#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */\n#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            \n#define DMA_LISR_TCIF2_Pos       (21U)                                         \n#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */\n#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            \n#define DMA_LISR_HTIF2_Pos       (20U)                                         \n#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */\n#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            \n#define DMA_LISR_TEIF2_Pos       (19U)                                         \n#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */\n#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            \n#define DMA_LISR_DMEIF2_Pos      (18U)                                         \n#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */\n#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           \n#define DMA_LISR_FEIF2_Pos       (16U)                                         \n#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */\n#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            \n#define DMA_LISR_TCIF1_Pos       (11U)                                         \n#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */\n#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            \n#define DMA_LISR_HTIF1_Pos       (10U)                                         \n#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */\n#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            \n#define DMA_LISR_TEIF1_Pos       (9U)                                          \n#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */\n#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            \n#define DMA_LISR_DMEIF1_Pos      (8U)                                          \n#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */\n#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           \n#define DMA_LISR_FEIF1_Pos       (6U)                                          \n#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */\n#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            \n#define DMA_LISR_TCIF0_Pos       (5U)                                          \n#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */\n#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            \n#define DMA_LISR_HTIF0_Pos       (4U)                                          \n#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */\n#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            \n#define DMA_LISR_TEIF0_Pos       (3U)                                          \n#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */\n#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            \n#define DMA_LISR_DMEIF0_Pos      (2U)                                          \n#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */\n#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           \n#define DMA_LISR_FEIF0_Pos       (0U)                                          \n#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */\n#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            \n\n/********************  Bits definition for DMA_HISR register  *****************/ \n#define DMA_HISR_TCIF7_Pos       (27U)                                         \n#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */\n#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            \n#define DMA_HISR_HTIF7_Pos       (26U)                                         \n#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */\n#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            \n#define DMA_HISR_TEIF7_Pos       (25U)                                         \n#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */\n#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            \n#define DMA_HISR_DMEIF7_Pos      (24U)                                         \n#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */\n#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           \n#define DMA_HISR_FEIF7_Pos       (22U)                                         \n#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */\n#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            \n#define DMA_HISR_TCIF6_Pos       (21U)                                         \n#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */\n#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            \n#define DMA_HISR_HTIF6_Pos       (20U)                                         \n#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */\n#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            \n#define DMA_HISR_TEIF6_Pos       (19U)                                         \n#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */\n#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            \n#define DMA_HISR_DMEIF6_Pos      (18U)                                         \n#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */\n#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           \n#define DMA_HISR_FEIF6_Pos       (16U)                                         \n#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */\n#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            \n#define DMA_HISR_TCIF5_Pos       (11U)                                         \n#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */\n#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            \n#define DMA_HISR_HTIF5_Pos       (10U)                                         \n#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */\n#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            \n#define DMA_HISR_TEIF5_Pos       (9U)                                          \n#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */\n#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            \n#define DMA_HISR_DMEIF5_Pos      (8U)                                          \n#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */\n#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           \n#define DMA_HISR_FEIF5_Pos       (6U)                                          \n#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */\n#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            \n#define DMA_HISR_TCIF4_Pos       (5U)                                          \n#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */\n#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            \n#define DMA_HISR_HTIF4_Pos       (4U)                                          \n#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */\n#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            \n#define DMA_HISR_TEIF4_Pos       (3U)                                          \n#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */\n#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            \n#define DMA_HISR_DMEIF4_Pos      (2U)                                          \n#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */\n#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           \n#define DMA_HISR_FEIF4_Pos       (0U)                                          \n#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */\n#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            \n\n/********************  Bits definition for DMA_LIFCR register  ****************/ \n#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         \n#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */\n#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          \n#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         \n#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */\n#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          \n#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         \n#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */\n#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          \n#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         \n#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */\n#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         \n#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         \n#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */\n#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          \n#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         \n#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */\n#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          \n#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         \n#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */\n#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          \n#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         \n#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */\n#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          \n#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         \n#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */\n#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         \n#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         \n#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */\n#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          \n#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         \n#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */\n#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          \n#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         \n#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */\n#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          \n#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          \n#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */\n#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          \n#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          \n#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */\n#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         \n#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          \n#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */\n#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          \n#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          \n#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */\n#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          \n#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          \n#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */\n#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          \n#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          \n#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */\n#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          \n#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          \n#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */\n#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         \n#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          \n#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */\n#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          \n\n/********************  Bits definition for DMA_HIFCR  register  ****************/ \n#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         \n#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */\n#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          \n#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         \n#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */\n#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          \n#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         \n#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */\n#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          \n#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         \n#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */\n#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         \n#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         \n#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */\n#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          \n#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         \n#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */\n#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          \n#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         \n#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */\n#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          \n#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         \n#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */\n#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          \n#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         \n#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */\n#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         \n#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         \n#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */\n#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          \n#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         \n#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */\n#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          \n#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         \n#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */\n#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          \n#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          \n#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */\n#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          \n#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          \n#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */\n#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         \n#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          \n#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */\n#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          \n#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          \n#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */\n#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          \n#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          \n#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */\n#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          \n#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          \n#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */\n#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          \n#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          \n#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */\n#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         \n#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          \n#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */\n#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          \n\n/******************  Bit definition for DMA_SxPAR register  ********************/\n#define DMA_SxPAR_PA_Pos         (0U)                                          \n#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */\n#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_SxM0AR register  ********************/\n#define DMA_SxM0AR_M0A_Pos       (0U)                                          \n#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */\n\n/******************  Bit definition for DMA_SxM1AR register  ********************/\n#define DMA_SxM1AR_M1A_Pos       (0U)                                          \n#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */\n#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos          (0U)                                         \n#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos          (1U)                                         \n#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos          (2U)                                         \n#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos          (3U)                                         \n#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos          (4U)                                         \n#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos          (5U)                                         \n#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos          (6U)                                         \n#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos          (7U)                                         \n#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos          (8U)                                         \n#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos          (9U)                                         \n#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos         (10U)                                        \n#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos         (11U)                                        \n#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos         (12U)                                        \n#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos         (13U)                                        \n#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos         (14U)                                        \n#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos         (15U)                                        \n#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos         (16U)                                        \n#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos         (17U)                                        \n#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos         (18U)                                        \n#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */\n#define EXTI_IMR_MR19_Pos         (19U)                                        \n#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */\n#define EXTI_IMR_MR20_Pos         (20U)                                        \n#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */\n#define EXTI_IMR_MR21_Pos         (21U)                                        \n#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */\n#define EXTI_IMR_MR22_Pos         (22U)                                        \n#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_IMR_IM0                        EXTI_IMR_MR0\n#define  EXTI_IMR_IM1                        EXTI_IMR_MR1\n#define  EXTI_IMR_IM2                        EXTI_IMR_MR2\n#define  EXTI_IMR_IM3                        EXTI_IMR_MR3\n#define  EXTI_IMR_IM4                        EXTI_IMR_MR4\n#define  EXTI_IMR_IM5                        EXTI_IMR_MR5\n#define  EXTI_IMR_IM6                        EXTI_IMR_MR6\n#define  EXTI_IMR_IM7                        EXTI_IMR_MR7\n#define  EXTI_IMR_IM8                        EXTI_IMR_MR8\n#define  EXTI_IMR_IM9                        EXTI_IMR_MR9\n#define  EXTI_IMR_IM10                       EXTI_IMR_MR10\n#define  EXTI_IMR_IM11                       EXTI_IMR_MR11\n#define  EXTI_IMR_IM12                       EXTI_IMR_MR12\n#define  EXTI_IMR_IM13                       EXTI_IMR_MR13\n#define  EXTI_IMR_IM14                       EXTI_IMR_MR14\n#define  EXTI_IMR_IM15                       EXTI_IMR_MR15\n#define  EXTI_IMR_IM16                       EXTI_IMR_MR16\n#define  EXTI_IMR_IM17                       EXTI_IMR_MR17\n#define  EXTI_IMR_IM18                       EXTI_IMR_MR18\n#define  EXTI_IMR_IM19                       EXTI_IMR_MR19\n#define  EXTI_IMR_IM20                       EXTI_IMR_MR20\n#define  EXTI_IMR_IM21                       EXTI_IMR_MR21\n#define  EXTI_IMR_IM22                       EXTI_IMR_MR22\n#define EXTI_IMR_IM_Pos           (0U)                                         \n#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */\n#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */\n\n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos          (0U)                                         \n#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */\n#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos          (1U)                                         \n#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */\n#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos          (2U)                                         \n#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */\n#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos          (3U)                                         \n#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */\n#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos          (4U)                                         \n#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */\n#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos          (5U)                                         \n#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */\n#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos          (6U)                                         \n#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */\n#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos          (7U)                                         \n#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */\n#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos          (8U)                                         \n#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */\n#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos          (9U)                                         \n#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */\n#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos         (10U)                                        \n#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */\n#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos         (11U)                                        \n#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */\n#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos         (12U)                                        \n#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */\n#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos         (13U)                                        \n#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */\n#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos         (14U)                                        \n#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */\n#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos         (15U)                                        \n#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */\n#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos         (16U)                                        \n#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */\n#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos         (17U)                                        \n#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */\n#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos         (18U)                                        \n#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */\n#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */\n#define EXTI_EMR_MR19_Pos         (19U)                                        \n#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */\n#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */\n#define EXTI_EMR_MR20_Pos         (20U)                                        \n#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */\n#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */\n#define EXTI_EMR_MR21_Pos         (21U)                                        \n#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */\n#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */\n#define EXTI_EMR_MR22_Pos         (22U)                                        \n#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */\n#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */\n\n/* Reference Defines */\n#define  EXTI_EMR_EM0                        EXTI_EMR_MR0\n#define  EXTI_EMR_EM1                        EXTI_EMR_MR1\n#define  EXTI_EMR_EM2                        EXTI_EMR_MR2\n#define  EXTI_EMR_EM3                        EXTI_EMR_MR3\n#define  EXTI_EMR_EM4                        EXTI_EMR_MR4\n#define  EXTI_EMR_EM5                        EXTI_EMR_MR5\n#define  EXTI_EMR_EM6                        EXTI_EMR_MR6\n#define  EXTI_EMR_EM7                        EXTI_EMR_MR7\n#define  EXTI_EMR_EM8                        EXTI_EMR_MR8\n#define  EXTI_EMR_EM9                        EXTI_EMR_MR9\n#define  EXTI_EMR_EM10                       EXTI_EMR_MR10\n#define  EXTI_EMR_EM11                       EXTI_EMR_MR11\n#define  EXTI_EMR_EM12                       EXTI_EMR_MR12\n#define  EXTI_EMR_EM13                       EXTI_EMR_MR13\n#define  EXTI_EMR_EM14                       EXTI_EMR_MR14\n#define  EXTI_EMR_EM15                       EXTI_EMR_MR15\n#define  EXTI_EMR_EM16                       EXTI_EMR_MR16\n#define  EXTI_EMR_EM17                       EXTI_EMR_MR17\n#define  EXTI_EMR_EM18                       EXTI_EMR_MR18\n#define  EXTI_EMR_EM19                       EXTI_EMR_MR19\n#define  EXTI_EMR_EM20                       EXTI_EMR_MR20\n#define  EXTI_EMR_EM21                       EXTI_EMR_MR21\n#define  EXTI_EMR_EM22                       EXTI_EMR_MR22\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos         (0U)                                         \n#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos         (1U)                                         \n#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos         (2U)                                         \n#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos         (3U)                                         \n#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos         (4U)                                         \n#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos         (5U)                                         \n#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos         (6U)                                         \n#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos         (7U)                                         \n#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos         (8U)                                         \n#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos         (9U)                                         \n#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos        (10U)                                        \n#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos        (11U)                                        \n#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos        (12U)                                        \n#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos        (13U)                                        \n#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos        (14U)                                        \n#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos        (15U)                                        \n#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos        (16U)                                        \n#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos        (17U)                                        \n#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos        (18U)                                        \n#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */\n#define EXTI_RTSR_TR19_Pos        (19U)                                        \n#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */\n#define EXTI_RTSR_TR20_Pos        (20U)                                        \n#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */\n#define EXTI_RTSR_TR21_Pos        (21U)                                        \n#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */\n#define EXTI_RTSR_TR22_Pos        (22U)                                        \n#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos         (0U)                                         \n#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */\n#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos         (1U)                                         \n#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */\n#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos         (2U)                                         \n#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */\n#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos         (3U)                                         \n#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */\n#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos         (4U)                                         \n#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */\n#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos         (5U)                                         \n#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */\n#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos         (6U)                                         \n#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */\n#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos         (7U)                                         \n#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */\n#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos         (8U)                                         \n#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */\n#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos         (9U)                                         \n#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */\n#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos        (10U)                                        \n#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */\n#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos        (11U)                                        \n#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */\n#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos        (12U)                                        \n#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */\n#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos        (13U)                                        \n#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */\n#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos        (14U)                                        \n#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */\n#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos        (15U)                                        \n#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */\n#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos        (16U)                                        \n#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */\n#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos        (17U)                                        \n#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */\n#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos        (18U)                                        \n#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */\n#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */\n#define EXTI_FTSR_TR19_Pos        (19U)                                        \n#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */\n#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */\n#define EXTI_FTSR_TR20_Pos        (20U)                                        \n#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */\n#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */\n#define EXTI_FTSR_TR21_Pos        (21U)                                        \n#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */\n#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */\n#define EXTI_FTSR_TR22_Pos        (22U)                                        \n#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */\n#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos     (0U)                                         \n#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos     (1U)                                         \n#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos     (2U)                                         \n#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos     (3U)                                         \n#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos     (4U)                                         \n#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos     (5U)                                         \n#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos     (6U)                                         \n#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos     (7U)                                         \n#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos     (8U)                                         \n#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos     (9U)                                         \n#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos    (10U)                                        \n#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos    (11U)                                        \n#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos    (12U)                                        \n#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos    (13U)                                        \n#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos    (14U)                                        \n#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos    (15U)                                        \n#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos    (16U)                                        \n#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos    (17U)                                        \n#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos    (18U)                                        \n#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */\n#define EXTI_SWIER_SWIER19_Pos    (19U)                                        \n#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */\n#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */\n#define EXTI_SWIER_SWIER20_Pos    (20U)                                        \n#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */\n#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */\n#define EXTI_SWIER_SWIER21_Pos    (21U)                                        \n#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */\n#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */\n#define EXTI_SWIER_SWIER22_Pos    (22U)                                        \n#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */\n#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos           (0U)                                         \n#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */\n#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos           (1U)                                         \n#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */\n#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos           (2U)                                         \n#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */\n#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos           (3U)                                         \n#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */\n#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos           (4U)                                         \n#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */\n#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos           (5U)                                         \n#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */\n#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos           (6U)                                         \n#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */\n#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos           (7U)                                         \n#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */\n#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos           (8U)                                         \n#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */\n#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos           (9U)                                         \n#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */\n#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos          (10U)                                        \n#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */\n#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos          (11U)                                        \n#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */\n#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos          (12U)                                        \n#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */\n#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos          (13U)                                        \n#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */\n#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos          (14U)                                        \n#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */\n#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos          (15U)                                        \n#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */\n#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos          (16U)                                        \n#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */\n#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos          (17U)                                        \n#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */\n#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos          (18U)                                        \n#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */\n#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */\n#define EXTI_PR_PR19_Pos          (19U)                                        \n#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */\n#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */\n#define EXTI_PR_PR20_Pos          (20U)                                        \n#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */\n#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */\n#define EXTI_PR_PR21_Pos          (21U)                                        \n#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */\n#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */\n#define EXTI_PR_PR22_Pos          (22U)                                        \n#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */\n#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    FLASH                                   */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bits definition for FLASH_ACR register  *****************/\n#define FLASH_ACR_LATENCY_Pos          (0U)\n#define FLASH_ACR_LATENCY_Msk          (0x7UL << FLASH_ACR_LATENCY_Pos)         /*!< 0x00000007 */\n#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk\n#define FLASH_ACR_LATENCY_0WS          0x00000000U\n#define FLASH_ACR_LATENCY_1WS          0x00000001U\n#define FLASH_ACR_LATENCY_2WS          0x00000002U\n#define FLASH_ACR_LATENCY_3WS          0x00000003U\n#define FLASH_ACR_LATENCY_4WS          0x00000004U\n#define FLASH_ACR_LATENCY_5WS          0x00000005U\n#define FLASH_ACR_LATENCY_6WS          0x00000006U\n#define FLASH_ACR_LATENCY_7WS          0x00000007U\n\n\n#define FLASH_ACR_PRFTEN_Pos           (8U)                                    \n#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */\n#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    \n#define FLASH_ACR_ICEN_Pos             (9U)                                    \n#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */\n#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      \n#define FLASH_ACR_DCEN_Pos             (10U)                                   \n#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */\n#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      \n#define FLASH_ACR_ICRST_Pos            (11U)                                   \n#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */\n#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     \n#define FLASH_ACR_DCRST_Pos            (12U)                                   \n#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */\n#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     \n#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   \n#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */\n#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             \n#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    \n#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */\n#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             \n\n/*******************  Bits definition for FLASH_SR register  ******************/\n#define FLASH_SR_EOP_Pos               (0U)                                    \n#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */\n#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        \n#define FLASH_SR_SOP_Pos               (1U)                                    \n#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */\n#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        \n#define FLASH_SR_WRPERR_Pos            (4U)                                    \n#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */\n#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     \n#define FLASH_SR_PGAERR_Pos            (5U)                                    \n#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */\n#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     \n#define FLASH_SR_PGPERR_Pos            (6U)                                    \n#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */\n#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     \n#define FLASH_SR_PGSERR_Pos            (7U)                                    \n#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */\n#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     \n#define FLASH_SR_BSY_Pos               (16U)                                   \n#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */\n#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        \n\n/*******************  Bits definition for FLASH_CR register  ******************/\n#define FLASH_CR_PG_Pos                (0U)                                    \n#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */\n#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         \n#define FLASH_CR_SER_Pos               (1U)                                    \n#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */\n#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        \n#define FLASH_CR_MER_Pos               (2U)                                    \n#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */\n#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        \n#define FLASH_CR_SNB_Pos               (3U)                                    \n#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */\n#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        \n#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */\n#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */\n#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */\n#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */\n#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */\n#define FLASH_CR_PSIZE_Pos             (8U)                                    \n#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */\n#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      \n#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */\n#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */\n#define FLASH_CR_STRT_Pos              (16U)                                   \n#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */\n#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       \n#define FLASH_CR_EOPIE_Pos             (24U)                                   \n#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */\n#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      \n#define FLASH_CR_LOCK_Pos              (31U)                                   \n#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */\n#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       \n\n/*******************  Bits definition for FLASH_OPTCR register  ***************/\n#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    \n#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */\n#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 \n#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    \n#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */\n#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 \n\n#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             \n#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             \n#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    \n#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */\n#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 \n#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    \n#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */\n#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  \n#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    \n#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */\n#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               \n#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    \n#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */\n#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              \n#define FLASH_OPTCR_RDP_Pos            (8U)                                    \n#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */\n#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     \n#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */\n#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */\n#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */\n#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */\n#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */\n#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */\n#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */\n#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */\n#define FLASH_OPTCR_nWRP_Pos           (16U)                                   \n#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */\n#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    \n#define FLASH_OPTCR_nWRP_0             0x00010000U                             \n#define FLASH_OPTCR_nWRP_1             0x00020000U                             \n#define FLASH_OPTCR_nWRP_2             0x00040000U                             \n#define FLASH_OPTCR_nWRP_3             0x00080000U                             \n#define FLASH_OPTCR_nWRP_4             0x00100000U                             \n#define FLASH_OPTCR_nWRP_5             0x00200000U                             \n#define FLASH_OPTCR_nWRP_6             0x00400000U                             \n#define FLASH_OPTCR_nWRP_7             0x00800000U                             \n#define FLASH_OPTCR_nWRP_8             0x01000000U                             \n#define FLASH_OPTCR_nWRP_9             0x02000000U                             \n#define FLASH_OPTCR_nWRP_10            0x04000000U                             \n#define FLASH_OPTCR_nWRP_11            0x08000000U                             \n                                             \n/******************  Bits definition for FLASH_OPTCR1 register  ***************/\n#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   \n#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */\n#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   \n#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */\n#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */\n#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */\n#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */\n#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */\n#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */\n#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */\n#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */\n#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */\n#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */\n#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */\n#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                   Flexible Static Memory Controller                        */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for FSMC_BCR1 register  *******************/\n#define FSMC_BCR1_MBKEN_Pos          (0U)                                      \n#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR1_MUXEN_Pos          (1U)                                      \n#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR1_MTYP_Pos           (2U)                                      \n#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR1_MWID_Pos           (4U)                                      \n#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR1_FACCEN_Pos         (6U)                                      \n#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR1_BURSTEN_Pos        (8U)                                      \n#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR1_WAITPOL_Pos        (9U)                                      \n#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR1_WRAPMOD_Pos        (10U)                                     \n#define FSMC_BCR1_WRAPMOD_Msk        (0x1UL << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR1_WAITCFG_Pos        (11U)                                     \n#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR1_WREN_Pos           (12U)                                     \n#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR1_WAITEN_Pos         (13U)                                     \n#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR1_EXTMOD_Pos         (14U)                                     \n#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)                                     \n#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR1_CPSIZE_Pos         (16U)                                     \n#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR1_CBURSTRW_Pos       (19U)                                     \n#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR2 register  *******************/\n#define FSMC_BCR2_MBKEN_Pos          (0U)                                      \n#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */\n#define FSMC_BCR2_MUXEN_Pos          (1U)                                      \n#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR2_MTYP_Pos           (2U)                                      \n#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR2_MWID_Pos           (4U)                                      \n#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR2_FACCEN_Pos         (6U)                                      \n#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR2_BURSTEN_Pos        (8U)                                      \n#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR2_WAITPOL_Pos        (9U)                                      \n#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR2_WRAPMOD_Pos        (10U)                                     \n#define FSMC_BCR2_WRAPMOD_Msk        (0x1UL << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR2_WAITCFG_Pos        (11U)                                     \n#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR2_WREN_Pos           (12U)                                     \n#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR2_WAITEN_Pos         (13U)                                     \n#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR2_EXTMOD_Pos         (14U)                                     \n#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)                                     \n#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR2_CPSIZE_Pos         (16U)                                     \n#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR2_CBURSTRW_Pos       (19U)                                     \n#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR3 register  *******************/\n#define FSMC_BCR3_MBKEN_Pos          (0U)                                      \n#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */\n#define FSMC_BCR3_MUXEN_Pos          (1U)                                      \n#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR3_MTYP_Pos           (2U)                                      \n#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR3_MWID_Pos           (4U)                                      \n#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR3_FACCEN_Pos         (6U)                                      \n#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR3_BURSTEN_Pos        (8U)                                      \n#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR3_WAITPOL_Pos        (9U)                                      \n#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR3_WRAPMOD_Pos        (10U)                                     \n#define FSMC_BCR3_WRAPMOD_Msk        (0x1UL << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR3_WAITCFG_Pos        (11U)                                     \n#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR3_WREN_Pos           (12U)                                     \n#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR3_WAITEN_Pos         (13U)                                     \n#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR3_EXTMOD_Pos         (14U)                                     \n#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)                                     \n#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR3_CPSIZE_Pos         (16U)                                     \n#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR3_CBURSTRW_Pos       (19U)                                     \n#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BCR4 register  *******************/\n#define FSMC_BCR4_MBKEN_Pos          (0U)                                      \n#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */\n#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */\n#define FSMC_BCR4_MUXEN_Pos          (1U)                                      \n#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */\n#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */\n\n#define FSMC_BCR4_MTYP_Pos           (2U)                                      \n#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */\n#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */\n#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */\n#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */\n\n#define FSMC_BCR4_MWID_Pos           (4U)                                      \n#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */\n#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */\n#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */\n#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_BCR4_FACCEN_Pos         (6U)                                      \n#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */\n#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */\n#define FSMC_BCR4_BURSTEN_Pos        (8U)                                      \n#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */\n#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */\n#define FSMC_BCR4_WAITPOL_Pos        (9U)                                      \n#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */\n#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */\n#define FSMC_BCR4_WRAPMOD_Pos        (10U)                                     \n#define FSMC_BCR4_WRAPMOD_Msk        (0x1UL << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */\n#define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */\n#define FSMC_BCR4_WAITCFG_Pos        (11U)                                     \n#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */\n#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */\n#define FSMC_BCR4_WREN_Pos           (12U)                                     \n#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */\n#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */\n#define FSMC_BCR4_WAITEN_Pos         (13U)                                     \n#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */\n#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */\n#define FSMC_BCR4_EXTMOD_Pos         (14U)                                     \n#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */\n#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */\n#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)                                     \n#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */\n#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */\n#define FSMC_BCR4_CPSIZE_Pos         (16U)                                     \n#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */\n#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */\n#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */\n#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */\n#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */\n#define FSMC_BCR4_CBURSTRW_Pos       (19U)                                     \n#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */\n#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */\n\n/******************  Bit definition for FSMC_BTR1 register  ******************/\n#define FSMC_BTR1_ADDSET_Pos         (0U)                                      \n#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR1_ADDHLD_Pos         (4U)                                      \n#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR1_DATAST_Pos         (8U)                                      \n#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR1_BUSTURN_Pos        (16U)                                     \n#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR1_CLKDIV_Pos         (20U)                                     \n#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR1_DATLAT_Pos         (24U)                                     \n#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR1_ACCMOD_Pos         (28U)                                     \n#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR2 register  *******************/\n#define FSMC_BTR2_ADDSET_Pos         (0U)                                      \n#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR2_ADDHLD_Pos         (4U)                                      \n#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR2_DATAST_Pos         (8U)                                      \n#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR2_BUSTURN_Pos        (16U)                                     \n#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR2_CLKDIV_Pos         (20U)                                     \n#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR2_DATLAT_Pos         (24U)                                     \n#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR2_ACCMOD_Pos         (28U)                                     \n#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/*******************  Bit definition for FSMC_BTR3 register  *******************/\n#define FSMC_BTR3_ADDSET_Pos         (0U)                                      \n#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR3_ADDHLD_Pos         (4U)                                      \n#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR3_DATAST_Pos         (8U)                                      \n#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR3_BUSTURN_Pos        (16U)                                     \n#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR3_CLKDIV_Pos         (20U)                                     \n#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR3_DATLAT_Pos         (24U)                                     \n#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR3_ACCMOD_Pos         (28U)                                     \n#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BTR4 register  *******************/\n#define FSMC_BTR4_ADDSET_Pos         (0U)                                      \n#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */\n#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */\n#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */\n#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */\n#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */\n\n#define FSMC_BTR4_ADDHLD_Pos         (4U)                                      \n#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */\n#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */\n#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */\n#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */\n#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */\n\n#define FSMC_BTR4_DATAST_Pos         (8U)                                      \n#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */\n#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */\n#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */\n#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */\n#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */\n#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */\n#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */\n#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */\n#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */\n\n#define FSMC_BTR4_BUSTURN_Pos        (16U)                                     \n#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */\n#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\n#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */\n#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */\n#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */\n#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */\n\n#define FSMC_BTR4_CLKDIV_Pos         (20U)                                     \n#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */\n#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */\n#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */\n#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */\n#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */\n#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */\n\n#define FSMC_BTR4_DATLAT_Pos         (24U)                                     \n#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */\n#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */\n#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */\n#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */\n#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */\n#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */\n\n#define FSMC_BTR4_ACCMOD_Pos         (28U)                                     \n#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */\n#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */\n#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR1 register  ******************/\n#define FSMC_BWTR1_ADDSET_Pos        (0U)                                      \n#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR1_ADDHLD_Pos        (4U)                                      \n#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR1_DATAST_Pos        (8U)                                      \n#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR1_BUSTURN_Pos       (16U)                                     \n#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR1_ACCMOD_Pos        (28U)                                     \n#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR2 register  ******************/\n#define FSMC_BWTR2_ADDSET_Pos        (0U)                                      \n#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR2_ADDHLD_Pos        (4U)                                      \n#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR2_DATAST_Pos        (8U)                                      \n#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR2_BUSTURN_Pos       (16U)                                     \n#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR2_ACCMOD_Pos        (28U)                                     \n#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR3 register  ******************/\n#define FSMC_BWTR3_ADDSET_Pos        (0U)                                      \n#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR3_ADDHLD_Pos        (4U)                                      \n#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR3_DATAST_Pos        (8U)                                      \n#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */\n#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */\n#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */\n#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */\n#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */\n#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */\n#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */\n#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */\n#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */\n\n#define FSMC_BWTR3_BUSTURN_Pos       (16U)                                     \n#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR3_ACCMOD_Pos        (28U)                                     \n#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_BWTR4 register  ******************/\n#define FSMC_BWTR4_ADDSET_Pos        (0U)                                      \n#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */\n#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */\n#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */\n#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */\n#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */\n#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */\n\n#define FSMC_BWTR4_ADDHLD_Pos        (4U)                                      \n#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */\n#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\n#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */\n#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */\n#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */\n#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */\n\n#define FSMC_BWTR4_DATAST_Pos        (8U)                                      \n#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */\n#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */\n#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */\n#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */\n#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */\n#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */\n#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */\n#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */\n#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */\n#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */\n\n#define FSMC_BWTR4_BUSTURN_Pos       (16U)                                     \n#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */\n#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */\n#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */\n#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */\n#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */\n#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */\n\n#define FSMC_BWTR4_ACCMOD_Pos        (28U)                                     \n#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */\n#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */\n#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */\n#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */\n\n/******************  Bit definition for FSMC_PCR2 register  *******************/\n#define FSMC_PCR2_PWAITEN_Pos        (1U)                                      \n#define FSMC_PCR2_PWAITEN_Msk        (0x1UL << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR2_PBKEN_Pos          (2U)                                      \n#define FSMC_PCR2_PBKEN_Msk          (0x1UL << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR2_PTYP_Pos           (3U)                                      \n#define FSMC_PCR2_PTYP_Msk           (0x1UL << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR2_PWID_Pos           (4U)                                      \n#define FSMC_PCR2_PWID_Msk           (0x3UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR2_PWID_0             (0x1UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR2_PWID_1             (0x2UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR2_ECCEN_Pos          (6U)                                      \n#define FSMC_PCR2_ECCEN_Msk          (0x1UL << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR2_TCLR_Pos           (9U)                                      \n#define FSMC_PCR2_TCLR_Msk           (0xFUL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR2_TCLR_0             (0x1UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR2_TCLR_1             (0x2UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR2_TCLR_2             (0x4UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR2_TCLR_3             (0x8UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR2_TAR_Pos            (13U)                                     \n#define FSMC_PCR2_TAR_Msk            (0xFUL << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR2_TAR_0              (0x1UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR2_TAR_1              (0x2UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR2_TAR_2              (0x4UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR2_TAR_3              (0x8UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR2_ECCPS_Pos          (17U)                                     \n#define FSMC_PCR2_ECCPS_Msk          (0x7UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */\n#define FSMC_PCR2_ECCPS_0            (0x1UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR2_ECCPS_1            (0x2UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR2_ECCPS_2            (0x4UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR3 register  *******************/\n#define FSMC_PCR3_PWAITEN_Pos        (1U)                                      \n#define FSMC_PCR3_PWAITEN_Msk        (0x1UL << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR3_PBKEN_Pos          (2U)                                      \n#define FSMC_PCR3_PBKEN_Msk          (0x1UL << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR3_PTYP_Pos           (3U)                                      \n#define FSMC_PCR3_PTYP_Msk           (0x1UL << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR3_PWID_Pos           (4U)                                      \n#define FSMC_PCR3_PWID_Msk           (0x3UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR3_PWID_0             (0x1UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR3_PWID_1             (0x2UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR3_ECCEN_Pos          (6U)                                      \n#define FSMC_PCR3_ECCEN_Msk          (0x1UL << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR3_TCLR_Pos           (9U)                                      \n#define FSMC_PCR3_TCLR_Msk           (0xFUL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR3_TCLR_0             (0x1UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR3_TCLR_1             (0x2UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR3_TCLR_2             (0x4UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR3_TCLR_3             (0x8UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR3_TAR_Pos            (13U)                                     \n#define FSMC_PCR3_TAR_Msk            (0xFUL << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR3_TAR_0              (0x1UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR3_TAR_1              (0x2UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR3_TAR_2              (0x4UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR3_TAR_3              (0x8UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR3_ECCPS_Pos          (17U)                                     \n#define FSMC_PCR3_ECCPS_Msk          (0x7UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR3_ECCPS_0            (0x1UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR3_ECCPS_1            (0x2UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR3_ECCPS_2            (0x4UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */\n\n/******************  Bit definition for FSMC_PCR4 register  *******************/\n#define FSMC_PCR4_PWAITEN_Pos        (1U)                                      \n#define FSMC_PCR4_PWAITEN_Msk        (0x1UL << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */\n#define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */\n#define FSMC_PCR4_PBKEN_Pos          (2U)                                      \n#define FSMC_PCR4_PBKEN_Msk          (0x1UL << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */\n#define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */\n#define FSMC_PCR4_PTYP_Pos           (3U)                                      \n#define FSMC_PCR4_PTYP_Msk           (0x1UL << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */\n#define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */\n\n#define FSMC_PCR4_PWID_Pos           (4U)                                      \n#define FSMC_PCR4_PWID_Msk           (0x3UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */\n#define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */\n#define FSMC_PCR4_PWID_0             (0x1UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */\n#define FSMC_PCR4_PWID_1             (0x2UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */\n\n#define FSMC_PCR4_ECCEN_Pos          (6U)                                      \n#define FSMC_PCR4_ECCEN_Msk          (0x1UL << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */\n#define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */\n\n#define FSMC_PCR4_TCLR_Pos           (9U)                                      \n#define FSMC_PCR4_TCLR_Msk           (0xFUL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */\n#define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */\n#define FSMC_PCR4_TCLR_0             (0x1UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */\n#define FSMC_PCR4_TCLR_1             (0x2UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */\n#define FSMC_PCR4_TCLR_2             (0x4UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */\n#define FSMC_PCR4_TCLR_3             (0x8UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */\n\n#define FSMC_PCR4_TAR_Pos            (13U)                                     \n#define FSMC_PCR4_TAR_Msk            (0xFUL << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */\n#define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */\n#define FSMC_PCR4_TAR_0              (0x1UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */\n#define FSMC_PCR4_TAR_1              (0x2UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */\n#define FSMC_PCR4_TAR_2              (0x4UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */\n#define FSMC_PCR4_TAR_3              (0x8UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */\n\n#define FSMC_PCR4_ECCPS_Pos          (17U)                                     \n#define FSMC_PCR4_ECCPS_Msk          (0x7UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */\n#define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */\n#define FSMC_PCR4_ECCPS_0            (0x1UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */\n#define FSMC_PCR4_ECCPS_1            (0x2UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */\n#define FSMC_PCR4_ECCPS_2            (0x4UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */\n\n/*******************  Bit definition for FSMC_SR2 register  *******************/\n#define FSMC_SR2_IRS_Pos             (0U)                                      \n#define FSMC_SR2_IRS_Msk             (0x1UL << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR2_ILS_Pos             (1U)                                      \n#define FSMC_SR2_ILS_Msk             (0x1UL << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR2_IFS_Pos             (2U)                                      \n#define FSMC_SR2_IFS_Msk             (0x1UL << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR2_IREN_Pos            (3U)                                      \n#define FSMC_SR2_IREN_Msk            (0x1UL << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR2_ILEN_Pos            (4U)                                      \n#define FSMC_SR2_ILEN_Msk            (0x1UL << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR2_IFEN_Pos            (5U)                                      \n#define FSMC_SR2_IFEN_Msk            (0x1UL << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR2_FEMPT_Pos           (6U)                                      \n#define FSMC_SR2_FEMPT_Msk           (0x1UL << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR3 register  *******************/\n#define FSMC_SR3_IRS_Pos             (0U)                                      \n#define FSMC_SR3_IRS_Msk             (0x1UL << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status                */\n#define FSMC_SR3_ILS_Pos             (1U)                                      \n#define FSMC_SR3_ILS_Msk             (0x1UL << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status                      */\n#define FSMC_SR3_IFS_Pos             (2U)                                      \n#define FSMC_SR3_IFS_Msk             (0x1UL << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status               */\n#define FSMC_SR3_IREN_Pos            (3U)                                      \n#define FSMC_SR3_IREN_Msk            (0x1UL << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */\n#define FSMC_SR3_ILEN_Pos            (4U)                                      \n#define FSMC_SR3_ILEN_Msk            (0x1UL << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */\n#define FSMC_SR3_IFEN_Pos            (5U)                                      \n#define FSMC_SR3_IFEN_Msk            (0x1UL << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */\n#define FSMC_SR3_FEMPT_Pos           (6U)                                      \n#define FSMC_SR3_FEMPT_Msk           (0x1UL << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */\n\n/*******************  Bit definition for FSMC_SR4 register  *******************/\n#define FSMC_SR4_IRS_Pos             (0U)                                      \n#define FSMC_SR4_IRS_Msk             (0x1UL << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */\n#define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status                 */\n#define FSMC_SR4_ILS_Pos             (1U)                                      \n#define FSMC_SR4_ILS_Msk             (0x1UL << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */\n#define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status                       */\n#define FSMC_SR4_IFS_Pos             (2U)                                      \n#define FSMC_SR4_IFS_Msk             (0x1UL << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */\n#define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status                */\n#define FSMC_SR4_IREN_Pos            (3U)                                      \n#define FSMC_SR4_IREN_Msk            (0x1UL << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */\n#define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit   */\n#define FSMC_SR4_ILEN_Pos            (4U)                                      \n#define FSMC_SR4_ILEN_Msk            (0x1UL << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */\n#define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit         */\n#define FSMC_SR4_IFEN_Pos            (5U)                                      \n#define FSMC_SR4_IFEN_Msk            (0x1UL << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */\n#define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit  */\n#define FSMC_SR4_FEMPT_Pos           (6U)                                      \n#define FSMC_SR4_FEMPT_Msk           (0x1UL << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */\n#define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */\n\n/******************  Bit definition for FSMC_PMEM2 register  ******************/\n#define FSMC_PMEM2_MEMSET2_Pos       (0U)                                      \n#define FSMC_PMEM2_MEMSET2_Msk       (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\n#define FSMC_PMEM2_MEMSET2_0         (0x01UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM2_MEMSET2_1         (0x02UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM2_MEMSET2_2         (0x04UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM2_MEMSET2_3         (0x08UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM2_MEMSET2_4         (0x10UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM2_MEMSET2_5         (0x20UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM2_MEMSET2_6         (0x40UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM2_MEMSET2_7         (0x80UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM2_MEMWAIT2_Pos      (8U)                                      \n#define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\n#define FSMC_PMEM2_MEMWAIT2_0        (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM2_MEMWAIT2_1        (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM2_MEMWAIT2_2        (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM2_MEMWAIT2_3        (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM2_MEMWAIT2_4        (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM2_MEMWAIT2_5        (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM2_MEMWAIT2_6        (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM2_MEMWAIT2_7        (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM2_MEMHOLD2_Pos      (16U)                                     \n#define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\n#define FSMC_PMEM2_MEMHOLD2_0        (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM2_MEMHOLD2_1        (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM2_MEMHOLD2_2        (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM2_MEMHOLD2_3        (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM2_MEMHOLD2_4        (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM2_MEMHOLD2_5        (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM2_MEMHOLD2_6        (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM2_MEMHOLD2_7        (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM2_MEMHIZ2_Pos       (24U)                                     \n#define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\n#define FSMC_PMEM2_MEMHIZ2_0         (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM2_MEMHIZ2_1         (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM2_MEMHIZ2_2         (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM2_MEMHIZ2_3         (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM2_MEMHIZ2_4         (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM2_MEMHIZ2_5         (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM2_MEMHIZ2_6         (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM2_MEMHIZ2_7         (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM3 register  ******************/\n#define FSMC_PMEM3_MEMSET3_Pos       (0U)                                      \n#define FSMC_PMEM3_MEMSET3_Msk       (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\n#define FSMC_PMEM3_MEMSET3_0         (0x01UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM3_MEMSET3_1         (0x02UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM3_MEMSET3_2         (0x04UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM3_MEMSET3_3         (0x08UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM3_MEMSET3_4         (0x10UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM3_MEMSET3_5         (0x20UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM3_MEMSET3_6         (0x40UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM3_MEMSET3_7         (0x80UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM3_MEMWAIT3_Pos      (8U)                                      \n#define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\n#define FSMC_PMEM3_MEMWAIT3_0        (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM3_MEMWAIT3_1        (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM3_MEMWAIT3_2        (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM3_MEMWAIT3_3        (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM3_MEMWAIT3_4        (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM3_MEMWAIT3_5        (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM3_MEMWAIT3_6        (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM3_MEMWAIT3_7        (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM3_MEMHOLD3_Pos      (16U)                                     \n#define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\n#define FSMC_PMEM3_MEMHOLD3_0        (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM3_MEMHOLD3_1        (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM3_MEMHOLD3_2        (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM3_MEMHOLD3_3        (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM3_MEMHOLD3_4        (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM3_MEMHOLD3_5        (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM3_MEMHOLD3_6        (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM3_MEMHOLD3_7        (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM3_MEMHIZ3_Pos       (24U)                                     \n#define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\n#define FSMC_PMEM3_MEMHIZ3_0         (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM3_MEMHIZ3_1         (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM3_MEMHIZ3_2         (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM3_MEMHIZ3_3         (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM3_MEMHIZ3_4         (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM3_MEMHIZ3_5         (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM3_MEMHIZ3_6         (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM3_MEMHIZ3_7         (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PMEM4 register  ******************/\n#define FSMC_PMEM4_MEMSET4_Pos       (0U)                                      \n#define FSMC_PMEM4_MEMSET4_Msk       (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\n#define FSMC_PMEM4_MEMSET4_0         (0x01UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PMEM4_MEMSET4_1         (0x02UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PMEM4_MEMSET4_2         (0x04UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PMEM4_MEMSET4_3         (0x08UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PMEM4_MEMSET4_4         (0x10UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PMEM4_MEMSET4_5         (0x20UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PMEM4_MEMSET4_6         (0x40UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PMEM4_MEMSET4_7         (0x80UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PMEM4_MEMWAIT4_Pos      (8U)                                      \n#define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\n#define FSMC_PMEM4_MEMWAIT4_0        (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PMEM4_MEMWAIT4_1        (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PMEM4_MEMWAIT4_2        (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PMEM4_MEMWAIT4_3        (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PMEM4_MEMWAIT4_4        (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PMEM4_MEMWAIT4_5        (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PMEM4_MEMWAIT4_6        (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PMEM4_MEMWAIT4_7        (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PMEM4_MEMHOLD4_Pos      (16U)                                     \n#define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\n#define FSMC_PMEM4_MEMHOLD4_0        (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PMEM4_MEMHOLD4_1        (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PMEM4_MEMHOLD4_2        (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PMEM4_MEMHOLD4_3        (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PMEM4_MEMHOLD4_4        (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PMEM4_MEMHOLD4_5        (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PMEM4_MEMHOLD4_6        (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PMEM4_MEMHOLD4_7        (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PMEM4_MEMHIZ4_Pos       (24U)                                     \n#define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\n#define FSMC_PMEM4_MEMHIZ4_0         (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PMEM4_MEMHIZ4_1         (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PMEM4_MEMHIZ4_2         (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PMEM4_MEMHIZ4_3         (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PMEM4_MEMHIZ4_4         (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PMEM4_MEMHIZ4_5         (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PMEM4_MEMHIZ4_6         (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PMEM4_MEMHIZ4_7         (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT2 register  ******************/\n#define FSMC_PATT2_ATTSET2_Pos       (0U)                                      \n#define FSMC_PATT2_ATTSET2_Msk       (0xFFUL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\n#define FSMC_PATT2_ATTSET2_0         (0x01UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT2_ATTSET2_1         (0x02UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT2_ATTSET2_2         (0x04UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT2_ATTSET2_3         (0x08UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT2_ATTSET2_4         (0x10UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT2_ATTSET2_5         (0x20UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT2_ATTSET2_6         (0x40UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT2_ATTSET2_7         (0x80UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT2_ATTWAIT2_Pos      (8U)                                      \n#define FSMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\n#define FSMC_PATT2_ATTWAIT2_0        (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT2_ATTWAIT2_1        (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT2_ATTWAIT2_2        (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT2_ATTWAIT2_3        (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT2_ATTWAIT2_4        (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT2_ATTWAIT2_5        (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT2_ATTWAIT2_6        (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT2_ATTWAIT2_7        (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT2_ATTHOLD2_Pos      (16U)                                     \n#define FSMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\n#define FSMC_PATT2_ATTHOLD2_0        (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT2_ATTHOLD2_1        (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT2_ATTHOLD2_2        (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT2_ATTHOLD2_3        (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT2_ATTHOLD2_4        (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT2_ATTHOLD2_5        (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT2_ATTHOLD2_6        (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT2_ATTHOLD2_7        (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT2_ATTHIZ2_Pos       (24U)                                     \n#define FSMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\n#define FSMC_PATT2_ATTHIZ2_0         (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT2_ATTHIZ2_1         (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT2_ATTHIZ2_2         (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT2_ATTHIZ2_3         (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT2_ATTHIZ2_4         (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT2_ATTHIZ2_5         (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT2_ATTHIZ2_6         (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT2_ATTHIZ2_7         (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT3 register  ******************/\n#define FSMC_PATT3_ATTSET3_Pos       (0U)                                      \n#define FSMC_PATT3_ATTSET3_Msk       (0xFFUL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\n#define FSMC_PATT3_ATTSET3_0         (0x01UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT3_ATTSET3_1         (0x02UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT3_ATTSET3_2         (0x04UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT3_ATTSET3_3         (0x08UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT3_ATTSET3_4         (0x10UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT3_ATTSET3_5         (0x20UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT3_ATTSET3_6         (0x40UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT3_ATTSET3_7         (0x80UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT3_ATTWAIT3_Pos      (8U)                                      \n#define FSMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\n#define FSMC_PATT3_ATTWAIT3_0        (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT3_ATTWAIT3_1        (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT3_ATTWAIT3_2        (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT3_ATTWAIT3_3        (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT3_ATTWAIT3_4        (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT3_ATTWAIT3_5        (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT3_ATTWAIT3_6        (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT3_ATTWAIT3_7        (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT3_ATTHOLD3_Pos      (16U)                                     \n#define FSMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\n#define FSMC_PATT3_ATTHOLD3_0        (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT3_ATTHOLD3_1        (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT3_ATTHOLD3_2        (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT3_ATTHOLD3_3        (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT3_ATTHOLD3_4        (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT3_ATTHOLD3_5        (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT3_ATTHOLD3_6        (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT3_ATTHOLD3_7        (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT3_ATTHIZ3_Pos       (24U)                                     \n#define FSMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\n#define FSMC_PATT3_ATTHIZ3_0         (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT3_ATTHIZ3_1         (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT3_ATTHIZ3_2         (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT3_ATTHIZ3_3         (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT3_ATTHIZ3_4         (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT3_ATTHIZ3_5         (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT3_ATTHIZ3_6         (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT3_ATTHIZ3_7         (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PATT4 register  ******************/\n#define FSMC_PATT4_ATTSET4_Pos       (0U)                                      \n#define FSMC_PATT4_ATTSET4_Msk       (0xFFUL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */\n#define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\n#define FSMC_PATT4_ATTSET4_0         (0x01UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */\n#define FSMC_PATT4_ATTSET4_1         (0x02UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */\n#define FSMC_PATT4_ATTSET4_2         (0x04UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */\n#define FSMC_PATT4_ATTSET4_3         (0x08UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */\n#define FSMC_PATT4_ATTSET4_4         (0x10UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */\n#define FSMC_PATT4_ATTSET4_5         (0x20UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */\n#define FSMC_PATT4_ATTSET4_6         (0x40UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */\n#define FSMC_PATT4_ATTSET4_7         (0x80UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */\n\n#define FSMC_PATT4_ATTWAIT4_Pos      (8U)                                      \n#define FSMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */\n#define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\n#define FSMC_PATT4_ATTWAIT4_0        (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */\n#define FSMC_PATT4_ATTWAIT4_1        (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */\n#define FSMC_PATT4_ATTWAIT4_2        (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */\n#define FSMC_PATT4_ATTWAIT4_3        (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */\n#define FSMC_PATT4_ATTWAIT4_4        (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */\n#define FSMC_PATT4_ATTWAIT4_5        (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */\n#define FSMC_PATT4_ATTWAIT4_6        (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */\n#define FSMC_PATT4_ATTWAIT4_7        (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */\n\n#define FSMC_PATT4_ATTHOLD4_Pos      (16U)                                     \n#define FSMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */\n#define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\n#define FSMC_PATT4_ATTHOLD4_0        (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */\n#define FSMC_PATT4_ATTHOLD4_1        (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */\n#define FSMC_PATT4_ATTHOLD4_2        (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */\n#define FSMC_PATT4_ATTHOLD4_3        (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */\n#define FSMC_PATT4_ATTHOLD4_4        (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */\n#define FSMC_PATT4_ATTHOLD4_5        (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */\n#define FSMC_PATT4_ATTHOLD4_6        (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */\n#define FSMC_PATT4_ATTHOLD4_7        (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */\n\n#define FSMC_PATT4_ATTHIZ4_Pos       (24U)                                     \n#define FSMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */\n#define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\n#define FSMC_PATT4_ATTHIZ4_0         (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */\n#define FSMC_PATT4_ATTHIZ4_1         (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */\n#define FSMC_PATT4_ATTHIZ4_2         (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */\n#define FSMC_PATT4_ATTHIZ4_3         (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */\n#define FSMC_PATT4_ATTHIZ4_4         (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */\n#define FSMC_PATT4_ATTHIZ4_5         (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */\n#define FSMC_PATT4_ATTHIZ4_6         (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */\n#define FSMC_PATT4_ATTHIZ4_7         (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_PIO4 register  *******************/\n#define FSMC_PIO4_IOSET4_Pos         (0U)                                      \n#define FSMC_PIO4_IOSET4_Msk         (0xFFUL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */\n#define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */\n#define FSMC_PIO4_IOSET4_0           (0x01UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */\n#define FSMC_PIO4_IOSET4_1           (0x02UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */\n#define FSMC_PIO4_IOSET4_2           (0x04UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */\n#define FSMC_PIO4_IOSET4_3           (0x08UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */\n#define FSMC_PIO4_IOSET4_4           (0x10UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */\n#define FSMC_PIO4_IOSET4_5           (0x20UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */\n#define FSMC_PIO4_IOSET4_6           (0x40UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */\n#define FSMC_PIO4_IOSET4_7           (0x80UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */\n\n#define FSMC_PIO4_IOWAIT4_Pos        (8U)                                      \n#define FSMC_PIO4_IOWAIT4_Msk        (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */\n#define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\n#define FSMC_PIO4_IOWAIT4_0          (0x01UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */\n#define FSMC_PIO4_IOWAIT4_1          (0x02UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */\n#define FSMC_PIO4_IOWAIT4_2          (0x04UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */\n#define FSMC_PIO4_IOWAIT4_3          (0x08UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */\n#define FSMC_PIO4_IOWAIT4_4          (0x10UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */\n#define FSMC_PIO4_IOWAIT4_5          (0x20UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */\n#define FSMC_PIO4_IOWAIT4_6          (0x40UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */\n#define FSMC_PIO4_IOWAIT4_7          (0x80UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */\n\n#define FSMC_PIO4_IOHOLD4_Pos        (16U)                                     \n#define FSMC_PIO4_IOHOLD4_Msk        (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */\n#define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\n#define FSMC_PIO4_IOHOLD4_0          (0x01UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */\n#define FSMC_PIO4_IOHOLD4_1          (0x02UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */\n#define FSMC_PIO4_IOHOLD4_2          (0x04UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */\n#define FSMC_PIO4_IOHOLD4_3          (0x08UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */\n#define FSMC_PIO4_IOHOLD4_4          (0x10UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */\n#define FSMC_PIO4_IOHOLD4_5          (0x20UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */\n#define FSMC_PIO4_IOHOLD4_6          (0x40UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */\n#define FSMC_PIO4_IOHOLD4_7          (0x80UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */\n\n#define FSMC_PIO4_IOHIZ4_Pos         (24U)                                     \n#define FSMC_PIO4_IOHIZ4_Msk         (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */\n#define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\n#define FSMC_PIO4_IOHIZ4_0           (0x01UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */\n#define FSMC_PIO4_IOHIZ4_1           (0x02UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */\n#define FSMC_PIO4_IOHIZ4_2           (0x04UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */\n#define FSMC_PIO4_IOHIZ4_3           (0x08UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */\n#define FSMC_PIO4_IOHIZ4_4           (0x10UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */\n#define FSMC_PIO4_IOHIZ4_5           (0x20UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */\n#define FSMC_PIO4_IOHIZ4_6           (0x40UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */\n#define FSMC_PIO4_IOHIZ4_7           (0x80UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */\n\n/******************  Bit definition for FSMC_ECCR2 register  ******************/\n#define FSMC_ECCR2_ECC2_Pos          (0U)                                      \n#define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */\n\n/******************  Bit definition for FSMC_ECCR3 register  ******************/\n#define FSMC_ECCR3_ECC3_Pos          (0U)                                      \n#define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */\n#define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            General Purpose I/O                             */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bits definition for GPIO_MODER register  *****************/\n#define GPIO_MODER_MODER0_Pos            (0U)                                  \n#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */\n#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 \n#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */\n#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */\n#define GPIO_MODER_MODER1_Pos            (2U)                                  \n#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */\n#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 \n#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */\n#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */\n#define GPIO_MODER_MODER2_Pos            (4U)                                  \n#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */\n#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 \n#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */\n#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */\n#define GPIO_MODER_MODER3_Pos            (6U)                                  \n#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */\n#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 \n#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */\n#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */\n#define GPIO_MODER_MODER4_Pos            (8U)                                  \n#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */\n#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 \n#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */\n#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */\n#define GPIO_MODER_MODER5_Pos            (10U)                                 \n#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */\n#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 \n#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */\n#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */\n#define GPIO_MODER_MODER6_Pos            (12U)                                 \n#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */\n#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 \n#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */\n#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */\n#define GPIO_MODER_MODER7_Pos            (14U)                                 \n#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */\n#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 \n#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */\n#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */\n#define GPIO_MODER_MODER8_Pos            (16U)                                 \n#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */\n#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 \n#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */\n#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */\n#define GPIO_MODER_MODER9_Pos            (18U)                                 \n#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */\n#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 \n#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */\n#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */\n#define GPIO_MODER_MODER10_Pos           (20U)                                 \n#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */\n#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                \n#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */\n#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */\n#define GPIO_MODER_MODER11_Pos           (22U)                                 \n#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */\n#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                \n#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */\n#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */\n#define GPIO_MODER_MODER12_Pos           (24U)                                 \n#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */\n#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                \n#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */\n#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */\n#define GPIO_MODER_MODER13_Pos           (26U)                                 \n#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */\n#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                \n#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */\n#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */\n#define GPIO_MODER_MODER14_Pos           (28U)                                 \n#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */\n#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                \n#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */\n#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */\n#define GPIO_MODER_MODER15_Pos           (30U)                                 \n#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */\n#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                \n#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */\n#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos                                  \n#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk\n#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0                 \n#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0\n#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1\n#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos                                  \n#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk\n#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1                  \n#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0\n#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1\n#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos\n#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk\n#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2                 \n#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0\n#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1\n#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos                                \n#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk\n#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3\n#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0\n#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1\n#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos\n#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk\n#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4\n#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0\n#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1\n#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos\n#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk\n#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5\n#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0\n#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1\n#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos\n#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk\n#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6\n#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0\n#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1\n#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos\n#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk\n#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7\n#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0\n#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1\n#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos\n#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER8_Msk\n#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8\n#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0\n#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1\n#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos\n#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk\n#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9\n#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0\n#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1\n#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos\n#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk\n#define GPIO_MODER_MODE10                GPIO_MODER_MODER10\n#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0\n#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1\n#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos\n#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk\n#define GPIO_MODER_MODE11                GPIO_MODER_MODER11\n#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0\n#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1\n#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos\n#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk\n#define GPIO_MODER_MODE12                GPIO_MODER_MODER12\n#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0\n#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1\n#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos\n#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk\n#define GPIO_MODER_MODE13                GPIO_MODER_MODER13\n#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0\n#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1\n#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos\n#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk\n#define GPIO_MODER_MODE14                GPIO_MODER_MODER14\n#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0\n#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1\n#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos\n#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk\n#define GPIO_MODER_MODE15                GPIO_MODER_MODER15\n#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0\n#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1\n\n/******************  Bits definition for GPIO_OTYPER register  ****************/\n#define GPIO_OTYPER_OT0_Pos              (0U)                                  \n#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */\n#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   \n#define GPIO_OTYPER_OT1_Pos              (1U)                                  \n#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */\n#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   \n#define GPIO_OTYPER_OT2_Pos              (2U)                                  \n#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */\n#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   \n#define GPIO_OTYPER_OT3_Pos              (3U)                                  \n#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */\n#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   \n#define GPIO_OTYPER_OT4_Pos              (4U)                                  \n#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */\n#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   \n#define GPIO_OTYPER_OT5_Pos              (5U)                                  \n#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */\n#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   \n#define GPIO_OTYPER_OT6_Pos              (6U)                                  \n#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */\n#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   \n#define GPIO_OTYPER_OT7_Pos              (7U)                                  \n#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */\n#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   \n#define GPIO_OTYPER_OT8_Pos              (8U)                                  \n#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */\n#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   \n#define GPIO_OTYPER_OT9_Pos              (9U)                                  \n#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */\n#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   \n#define GPIO_OTYPER_OT10_Pos             (10U)                                 \n#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */\n#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  \n#define GPIO_OTYPER_OT11_Pos             (11U)                                 \n#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */\n#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  \n#define GPIO_OTYPER_OT12_Pos             (12U)                                 \n#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */\n#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  \n#define GPIO_OTYPER_OT13_Pos             (13U)                                 \n#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */\n#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  \n#define GPIO_OTYPER_OT14_Pos             (14U)                                 \n#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */\n#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  \n#define GPIO_OTYPER_OT15_Pos             (15U)                                 \n#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */\n#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  \n\n/* Legacy defines */\n#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0\n#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1\n#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2\n#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3\n#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4\n#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5\n#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6\n#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7\n#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8\n#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9\n#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10\n#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11\n#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12\n#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13\n#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14\n#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15\n\n/******************  Bits definition for GPIO_OSPEEDR register  ***************/\n#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  \n#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */\n#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              \n#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */\n#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */\n#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  \n#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */\n#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              \n#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */\n#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */\n#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  \n#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */\n#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              \n#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */\n#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */\n#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  \n#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */\n#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              \n#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */\n#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */\n#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  \n#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */\n#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              \n#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */\n#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */\n#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 \n#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */\n#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              \n#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */\n#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */\n#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 \n#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */\n#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              \n#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */\n#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */\n#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 \n#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */\n#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              \n#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */\n#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */\n#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 \n#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */\n#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              \n#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */\n#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */\n#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 \n#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */\n#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              \n#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */\n#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */\n#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 \n#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */\n#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             \n#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */\n#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */\n#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 \n#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */\n#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             \n#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */\n#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */\n#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 \n#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */\n#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             \n#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */\n#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */\n#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 \n#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */\n#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             \n#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */\n#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */\n#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 \n#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */\n#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             \n#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */\n#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */\n#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 \n#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */\n#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             \n#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */\n#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0\n#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0\n#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1\n#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1\n#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0\n#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1\n#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2\n#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0\n#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1\n#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3\n#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0\n#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1\n#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4\n#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0\n#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1\n#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5\n#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0\n#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1\n#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6\n#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0\n#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1\n#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7\n#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0\n#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1\n#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8\n#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0\n#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1\n#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9\n#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0\n#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1\n#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10\n#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0\n#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1\n#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11\n#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0\n#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1\n#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12\n#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0\n#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1\n#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13\n#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0\n#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1\n#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14\n#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0\n#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1\n#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15\n#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0\n#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1\n\n/******************  Bits definition for GPIO_PUPDR register  *****************/\n#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  \n#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */\n#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  \n#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */\n#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */\n#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  \n#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */\n#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  \n#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */\n#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */\n#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  \n#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */\n#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  \n#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */\n#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */\n#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  \n#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */\n#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  \n#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */\n#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */\n#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  \n#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */\n#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  \n#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */\n#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */\n#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 \n#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */\n#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  \n#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */\n#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */\n#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 \n#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */\n#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  \n#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */\n#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */\n#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 \n#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */\n#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  \n#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */\n#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */\n#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 \n#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */\n#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  \n#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */\n#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */\n#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 \n#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */\n#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  \n#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */\n#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */\n#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 \n#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */\n#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 \n#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */\n#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */\n#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 \n#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */\n#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 \n#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */\n#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */\n#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 \n#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */\n#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 \n#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */\n#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */\n#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 \n#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */\n#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 \n#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */\n#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */\n#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 \n#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */\n#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 \n#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */\n#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */\n#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 \n#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */\n#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 \n#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */\n#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0\n#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0\n#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1\n#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1\n#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0\n#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1\n#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2\n#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0\n#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1\n#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3\n#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0\n#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1\n#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4\n#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0\n#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1\n#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5\n#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0\n#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1\n#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6\n#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0\n#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1\n#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7\n#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0\n#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1\n#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8\n#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0\n#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1\n#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9\n#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0\n#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1\n#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10\n#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0\n#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1\n#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11\n#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0\n#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1\n#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12\n#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0\n#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1\n#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13\n#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0\n#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1\n#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14\n#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0\n#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1\n#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15\n#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0\n#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1\n\n/******************  Bits definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_ID0_Pos                 (0U)                                  \n#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */\n#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      \n#define GPIO_IDR_ID1_Pos                 (1U)                                  \n#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */\n#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      \n#define GPIO_IDR_ID2_Pos                 (2U)                                  \n#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */\n#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      \n#define GPIO_IDR_ID3_Pos                 (3U)                                  \n#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */\n#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      \n#define GPIO_IDR_ID4_Pos                 (4U)                                  \n#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */\n#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      \n#define GPIO_IDR_ID5_Pos                 (5U)                                  \n#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */\n#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      \n#define GPIO_IDR_ID6_Pos                 (6U)                                  \n#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */\n#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      \n#define GPIO_IDR_ID7_Pos                 (7U)                                  \n#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */\n#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      \n#define GPIO_IDR_ID8_Pos                 (8U)                                  \n#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */\n#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      \n#define GPIO_IDR_ID9_Pos                 (9U)                                  \n#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */\n#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      \n#define GPIO_IDR_ID10_Pos                (10U)                                 \n#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */\n#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     \n#define GPIO_IDR_ID11_Pos                (11U)                                 \n#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */\n#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     \n#define GPIO_IDR_ID12_Pos                (12U)                                 \n#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */\n#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     \n#define GPIO_IDR_ID13_Pos                (13U)                                 \n#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */\n#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     \n#define GPIO_IDR_ID14_Pos                (14U)                                 \n#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */\n#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     \n#define GPIO_IDR_ID15_Pos                (15U)                                 \n#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */\n#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     \n\n/* Legacy defines */\n#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0\n#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1\n#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2\n#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3\n#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4\n#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5\n#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6\n#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7\n#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8\n#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9\n#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10\n#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11\n#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12\n#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13\n#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14\n#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15\n\n/******************  Bits definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_OD0_Pos                 (0U)                                  \n#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */\n#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      \n#define GPIO_ODR_OD1_Pos                 (1U)                                  \n#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */\n#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      \n#define GPIO_ODR_OD2_Pos                 (2U)                                  \n#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */\n#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      \n#define GPIO_ODR_OD3_Pos                 (3U)                                  \n#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */\n#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      \n#define GPIO_ODR_OD4_Pos                 (4U)                                  \n#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */\n#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      \n#define GPIO_ODR_OD5_Pos                 (5U)                                  \n#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */\n#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      \n#define GPIO_ODR_OD6_Pos                 (6U)                                  \n#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */\n#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      \n#define GPIO_ODR_OD7_Pos                 (7U)                                  \n#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */\n#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      \n#define GPIO_ODR_OD8_Pos                 (8U)                                  \n#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */\n#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      \n#define GPIO_ODR_OD9_Pos                 (9U)                                  \n#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */\n#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      \n#define GPIO_ODR_OD10_Pos                (10U)                                 \n#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */\n#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     \n#define GPIO_ODR_OD11_Pos                (11U)                                 \n#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */\n#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     \n#define GPIO_ODR_OD12_Pos                (12U)                                 \n#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */\n#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     \n#define GPIO_ODR_OD13_Pos                (13U)                                 \n#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */\n#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     \n#define GPIO_ODR_OD14_Pos                (14U)                                 \n#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */\n#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     \n#define GPIO_ODR_OD15_Pos                (15U)                                 \n#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */\n#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     \n/* Legacy defines */\n#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0\n#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1\n#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2\n#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3\n#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4\n#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5\n#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6\n#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7\n#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8\n#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9\n#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10\n#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11\n#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12\n#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13\n#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14\n#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15\n\n/******************  Bits definition for GPIO_BSRR register  ******************/\n#define GPIO_BSRR_BS0_Pos                (0U)                                  \n#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     \n#define GPIO_BSRR_BS1_Pos                (1U)                                  \n#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     \n#define GPIO_BSRR_BS2_Pos                (2U)                                  \n#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     \n#define GPIO_BSRR_BS3_Pos                (3U)                                  \n#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     \n#define GPIO_BSRR_BS4_Pos                (4U)                                  \n#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     \n#define GPIO_BSRR_BS5_Pos                (5U)                                  \n#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     \n#define GPIO_BSRR_BS6_Pos                (6U)                                  \n#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     \n#define GPIO_BSRR_BS7_Pos                (7U)                                  \n#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     \n#define GPIO_BSRR_BS8_Pos                (8U)                                  \n#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     \n#define GPIO_BSRR_BS9_Pos                (9U)                                  \n#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     \n#define GPIO_BSRR_BS10_Pos               (10U)                                 \n#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    \n#define GPIO_BSRR_BS11_Pos               (11U)                                 \n#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    \n#define GPIO_BSRR_BS12_Pos               (12U)                                 \n#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    \n#define GPIO_BSRR_BS13_Pos               (13U)                                 \n#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    \n#define GPIO_BSRR_BS14_Pos               (14U)                                 \n#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    \n#define GPIO_BSRR_BS15_Pos               (15U)                                 \n#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    \n#define GPIO_BSRR_BR0_Pos                (16U)                                 \n#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     \n#define GPIO_BSRR_BR1_Pos                (17U)                                 \n#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     \n#define GPIO_BSRR_BR2_Pos                (18U)                                 \n#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     \n#define GPIO_BSRR_BR3_Pos                (19U)                                 \n#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     \n#define GPIO_BSRR_BR4_Pos                (20U)                                 \n#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     \n#define GPIO_BSRR_BR5_Pos                (21U)                                 \n#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     \n#define GPIO_BSRR_BR6_Pos                (22U)                                 \n#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     \n#define GPIO_BSRR_BR7_Pos                (23U)                                 \n#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     \n#define GPIO_BSRR_BR8_Pos                (24U)                                 \n#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     \n#define GPIO_BSRR_BR9_Pos                (25U)                                 \n#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     \n#define GPIO_BSRR_BR10_Pos               (26U)                                 \n#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    \n#define GPIO_BSRR_BR11_Pos               (27U)                                 \n#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    \n#define GPIO_BSRR_BR12_Pos               (28U)                                 \n#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    \n#define GPIO_BSRR_BR13_Pos               (29U)                                 \n#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    \n#define GPIO_BSRR_BR14_Pos               (30U)                                 \n#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    \n#define GPIO_BSRR_BR15_Pos               (31U)                                 \n#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    \n\n/* Legacy defines */\n#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0\n#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1\n#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2\n#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3\n#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4\n#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5\n#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6\n#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7\n#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8\n#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9\n#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10\n#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11\n#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12\n#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13\n#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14\n#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15\n#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0\n#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1\n#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2\n#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3\n#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4\n#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5\n#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6\n#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7\n#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8\n#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9\n#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10\n#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11\n#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12\n#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13\n#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14\n#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15\n#define GPIO_BRR_BR0                     GPIO_BSRR_BR0\n#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos\n#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk\n#define GPIO_BRR_BR1                     GPIO_BSRR_BR1\n#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos\n#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk\n#define GPIO_BRR_BR2                     GPIO_BSRR_BR2\n#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos\n#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk\n#define GPIO_BRR_BR3                     GPIO_BSRR_BR3\n#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos\n#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk\n#define GPIO_BRR_BR4                     GPIO_BSRR_BR4\n#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos\n#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk\n#define GPIO_BRR_BR5                     GPIO_BSRR_BR5\n#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos\n#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk\n#define GPIO_BRR_BR6                     GPIO_BSRR_BR6\n#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos\n#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk\n#define GPIO_BRR_BR7                     GPIO_BSRR_BR7\n#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos\n#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk\n#define GPIO_BRR_BR8                     GPIO_BSRR_BR8\n#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos\n#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk\n#define GPIO_BRR_BR9                     GPIO_BSRR_BR9\n#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos\n#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk\n#define GPIO_BRR_BR10                    GPIO_BSRR_BR10\n#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos\n#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk\n#define GPIO_BRR_BR11                    GPIO_BSRR_BR11\n#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos\n#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk\n#define GPIO_BRR_BR12                    GPIO_BSRR_BR12\n#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos\n#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk\n#define GPIO_BRR_BR13                    GPIO_BSRR_BR13\n#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos\n#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk\n#define GPIO_BRR_BR14                    GPIO_BSRR_BR14\n#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos\n#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk\n#define GPIO_BRR_BR15                    GPIO_BSRR_BR15\n#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos\n#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk \n/****************** Bit definition for GPIO_LCKR register *********************/\n#define GPIO_LCKR_LCK0_Pos               (0U)                                  \n#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    \n#define GPIO_LCKR_LCK1_Pos               (1U)                                  \n#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    \n#define GPIO_LCKR_LCK2_Pos               (2U)                                  \n#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    \n#define GPIO_LCKR_LCK3_Pos               (3U)                                  \n#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    \n#define GPIO_LCKR_LCK4_Pos               (4U)                                  \n#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    \n#define GPIO_LCKR_LCK5_Pos               (5U)                                  \n#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    \n#define GPIO_LCKR_LCK6_Pos               (6U)                                  \n#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    \n#define GPIO_LCKR_LCK7_Pos               (7U)                                  \n#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    \n#define GPIO_LCKR_LCK8_Pos               (8U)                                  \n#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    \n#define GPIO_LCKR_LCK9_Pos               (9U)                                  \n#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    \n#define GPIO_LCKR_LCK10_Pos              (10U)                                 \n#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   \n#define GPIO_LCKR_LCK11_Pos              (11U)                                 \n#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   \n#define GPIO_LCKR_LCK12_Pos              (12U)                                 \n#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   \n#define GPIO_LCKR_LCK13_Pos              (13U)                                 \n#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   \n#define GPIO_LCKR_LCK14_Pos              (14U)                                 \n#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   \n#define GPIO_LCKR_LCK15_Pos              (15U)                                 \n#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   \n#define GPIO_LCKR_LCKK_Pos               (16U)                                 \n#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    \n/****************** Bit definition for GPIO_AFRL register *********************/\n#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  \n#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  \n#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  \n#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  \n#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  \n#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */\n#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  \n#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */\n#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */\n#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */\n#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */\n#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 \n#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */\n#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  \n#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */\n#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */\n#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */\n#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */\n#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 \n#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */\n#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  \n#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */\n#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */\n#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */\n#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */\n#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 \n#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */\n#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  \n#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */\n#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */\n#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */\n#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */\n#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 \n#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */\n#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  \n#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */\n#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */\n#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */\n#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */\n#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 \n#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */\n#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  \n#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */\n#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */\n#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */\n#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0\n#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0\n#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1\n#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2\n#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3\n#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1\n#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0\n#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1\n#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2\n#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3\n#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2\n#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0\n#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1\n#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2\n#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3\n#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3\n#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0\n#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1\n#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2\n#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3\n#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4\n#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0\n#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1\n#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2\n#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3\n#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5\n#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0\n#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1\n#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2\n#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3\n#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6\n#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0\n#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1\n#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2\n#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3\n#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7\n#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0\n#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1\n#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2\n#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3\n\n/****************** Bit definition for GPIO_AFRH register *********************/\n#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  \n#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */\n#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  \n#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */\n#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */\n#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */\n#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */\n#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  \n#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */\n#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  \n#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */\n#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */\n#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */\n#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */\n#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  \n#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */\n#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 \n#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */\n#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */\n#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */\n#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */\n#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 \n#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */\n#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 \n#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */\n#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */\n#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */\n#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */\n#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 \n#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */\n#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 \n#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */\n#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */\n#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */\n#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */\n#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 \n#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */\n#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 \n#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */\n#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */\n#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */\n#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */\n#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 \n#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */\n#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 \n#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */\n#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */\n#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */\n#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */\n#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 \n#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */\n#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 \n#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */\n#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */\n#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */\n#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */\n\n/* Legacy defines */\n#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8\n#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0\n#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1\n#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2\n#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3\n#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9\n#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0\n#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1\n#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2\n#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3\n#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10\n#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0\n#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1\n#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2\n#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3\n#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11\n#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0\n#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1\n#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2\n#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3\n#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12\n#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0\n#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1\n#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2\n#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3\n#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13\n#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0\n#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1\n#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2\n#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3\n#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14\n#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0\n#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1\n#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2\n#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3\n#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15\n#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0\n#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1\n#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2\n#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos            (0U)                                         \n#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */\n#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */\n#define I2C_CR1_SMBUS_Pos         (1U)                                         \n#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */\n#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */\n#define I2C_CR1_SMBTYPE_Pos       (3U)                                         \n#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */\n#define I2C_CR1_ENARP_Pos         (4U)                                         \n#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */\n#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */\n#define I2C_CR1_ENPEC_Pos         (5U)                                         \n#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */\n#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */\n#define I2C_CR1_ENGC_Pos          (6U)                                         \n#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */\n#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */\n#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         \n#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */\n#define I2C_CR1_START_Pos         (8U)                                         \n#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */\n#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */\n#define I2C_CR1_STOP_Pos          (9U)                                         \n#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */\n#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */\n#define I2C_CR1_ACK_Pos           (10U)                                        \n#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */\n#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */\n#define I2C_CR1_POS_Pos           (11U)                                        \n#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */\n#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos           (12U)                                        \n#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */\n#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */\n#define I2C_CR1_ALERT_Pos         (13U)                                        \n#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */\n#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */\n#define I2C_CR1_SWRST_Pos         (15U)                                        \n#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */\n#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos          (0U)                                         \n#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */\n#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\n#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos       (8U)                                         \n#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */\n#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */\n#define I2C_CR2_ITEVTEN_Pos       (9U)                                         \n#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */\n#define I2C_CR2_ITBUFEN_Pos       (10U)                                        \n#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos         (11U)                                        \n#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */\n#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */\n#define I2C_CR2_LAST_Pos          (12U)                                        \n#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */\n#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */\n#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */\n\n#define I2C_OAR1_ADD0_Pos         (0U)                                         \n#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */\n#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */\n#define I2C_OAR1_ADD1_Pos         (1U)                                         \n#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */\n#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */\n#define I2C_OAR1_ADD2_Pos         (2U)                                         \n#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */\n#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */\n#define I2C_OAR1_ADD3_Pos         (3U)                                         \n#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */\n#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */\n#define I2C_OAR1_ADD4_Pos         (4U)                                         \n#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */\n#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */\n#define I2C_OAR1_ADD5_Pos         (5U)                                         \n#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */\n#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */\n#define I2C_OAR1_ADD6_Pos         (6U)                                         \n#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */\n#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */\n#define I2C_OAR1_ADD7_Pos         (7U)                                         \n#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */\n#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */\n#define I2C_OAR1_ADD8_Pos         (8U)                                         \n#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */\n#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */\n#define I2C_OAR1_ADD9_Pos         (9U)                                         \n#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */\n#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos      (15U)                                        \n#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos       (0U)                                         \n#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos         (1U)                                         \n#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */\n#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)                                         \n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos            (0U)                                         \n#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */\n#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */\n#define I2C_SR1_ADDR_Pos          (1U)                                         \n#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */\n#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos           (2U)                                         \n#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */\n#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */\n#define I2C_SR1_ADD10_Pos         (3U)                                         \n#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */\n#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */\n#define I2C_SR1_STOPF_Pos         (4U)                                         \n#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */\n#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */\n#define I2C_SR1_RXNE_Pos          (6U)                                         \n#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */\n#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */\n#define I2C_SR1_TXE_Pos           (7U)                                         \n#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */\n#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */\n#define I2C_SR1_BERR_Pos          (8U)                                         \n#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */\n#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */\n#define I2C_SR1_ARLO_Pos          (9U)                                         \n#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */\n#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */\n#define I2C_SR1_AF_Pos            (10U)                                        \n#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */\n#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */\n#define I2C_SR1_OVR_Pos           (11U)                                        \n#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */\n#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */\n#define I2C_SR1_PECERR_Pos        (12U)                                        \n#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */\n#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */\n#define I2C_SR1_TIMEOUT_Pos       (14U)                                        \n#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */\n#define I2C_SR1_SMBALERT_Pos      (15U)                                        \n#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos           (0U)                                         \n#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */\n#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */\n#define I2C_SR2_BUSY_Pos          (1U)                                         \n#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */\n#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */\n#define I2C_SR2_TRA_Pos           (2U)                                         \n#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */\n#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */\n#define I2C_SR2_GENCALL_Pos       (4U)                                         \n#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */\n#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */\n#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         \n#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */\n#define I2C_SR2_SMBHOST_Pos       (6U)                                         \n#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */\n#define I2C_SR2_DUALF_Pos         (7U)                                         \n#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */\n#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */\n#define I2C_SR2_PEC_Pos           (8U)                                         \n#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */\n#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos           (0U)                                         \n#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */\n#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos          (14U)                                        \n#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */\n#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */\n#define I2C_CCR_FS_Pos            (15U)                                        \n#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */\n#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos       (0U)                                         \n#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */\n#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                           Independent WATCHDOG                             */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos     (0U)                                               \n#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos      (0U)                                               \n#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */\n#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */\n#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */\n#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */\n#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos     (0U)                                               \n#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */\n#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos     (0U)                                               \n#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */\n#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */\n#define IWDG_SR_RVU_Pos     (1U)                                               \n#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */\n#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos        (0U)                                            \n#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */\n#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */\n#define PWR_CR_PDDS_Pos        (1U)                                            \n#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */\n#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */\n#define PWR_CR_CWUF_Pos        (2U)                                            \n#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */\n#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */\n#define PWR_CR_CSBF_Pos        (3U)                                            \n#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */\n#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */\n#define PWR_CR_PVDE_Pos        (4U)                                            \n#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */\n#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */\n\n#define PWR_CR_PLS_Pos         (5U)                                            \n#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */\n#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */\n#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */\n#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */\n#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */\n#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */\n#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */\n#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */\n#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */\n#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */\n#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */\n#define PWR_CR_DBP_Pos         (8U)                                            \n#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */\n#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */\n#define PWR_CR_FPDS_Pos        (9U)                                            \n#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */\n#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */\n#define PWR_CR_VOS_Pos         (14U)                                           \n#define PWR_CR_VOS_Msk         (0x1UL << PWR_CR_VOS_Pos)                        /*!< 0x00004000 */\n#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS bit (Regulator voltage scaling output selection) */\n\n/* Legacy define */\n#define  PWR_CR_PMODE                        PWR_CR_VOS\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos        (0U)                                            \n#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */\n#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */\n#define PWR_CSR_SBF_Pos        (1U)                                            \n#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */\n#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */\n#define PWR_CSR_PVDO_Pos       (2U)                                            \n#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */\n#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */\n#define PWR_CSR_BRR_Pos        (3U)                                            \n#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */\n#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */\n#define PWR_CSR_EWUP_Pos       (8U)                                            \n#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */\n#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */\n#define PWR_CSR_BRE_Pos        (9U)                                            \n#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */\n#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */\n#define PWR_CSR_VOSRDY_Pos     (14U)                                           \n#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */\n#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */\n\n/* Legacy define */\n#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                   (0U)                                \n#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */\n#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    \n#define RCC_CR_HSIRDY_Pos                  (1U)                                \n#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   \n\n#define RCC_CR_HSITRIM_Pos                 (3U)                                \n#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  \n#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */\n#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */\n#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */\n#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */\n#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */\n\n#define RCC_CR_HSICAL_Pos                  (8U)                                \n#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   \n#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */\n#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */\n#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */\n#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */\n#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */\n#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */\n#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */\n#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */\n\n#define RCC_CR_HSEON_Pos                   (16U)                               \n#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */\n#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    \n#define RCC_CR_HSERDY_Pos                  (17U)                               \n#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */\n#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   \n#define RCC_CR_HSEBYP_Pos                  (18U)                               \n#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   \n#define RCC_CR_CSSON_Pos                   (19U)                               \n#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */\n#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    \n#define RCC_CR_PLLON_Pos                   (24U)                               \n#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */\n#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    \n#define RCC_CR_PLLRDY_Pos                  (25U)                               \n#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   \n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */\n\n#define RCC_CR_PLLI2SON_Pos                (26U)                               \n#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */\n#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 \n#define RCC_CR_PLLI2SRDY_Pos               (27U)                               \n#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */\n#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                \n\n/********************  Bit definition for RCC_PLLCFGR register  ***************/\n#define RCC_PLLCFGR_PLLM_Pos               (0U)                                \n#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */\n#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                \n#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */\n#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */\n#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */\n#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */\n#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */\n#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */\n\n#define RCC_PLLCFGR_PLLN_Pos               (6U)                                \n#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */\n#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                \n#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */\n#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */\n#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */\n#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */\n#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */\n#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */\n#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */\n#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */\n#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */\n\n#define RCC_PLLCFGR_PLLP_Pos               (16U)                               \n#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */\n#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                \n#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */\n#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */\n\n#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               \n#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              \n#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               \n#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\n#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          \n#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         \n\n#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               \n#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */\n#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                \n#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */\n#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */\n#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */\n#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */\n\n\n/********************  Bit definition for RCC_CFGR register  ******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                    (0U)                                \n#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */\n#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                   (2U)                                \n#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */\n#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */\n#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */\n#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                  (4U)                                \n#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */\n#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */\n#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */\n#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */\n#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */\n#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */\n#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                 (10U)                               \n#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */\n#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */\n#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */\n#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */\n\n#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                 (13U)                               \n#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */\n#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */\n#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */\n#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */\n\n#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */\n#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */\n#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */\n#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */\n#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */\n\n/*!< RTCPRE configuration */\n#define RCC_CFGR_RTCPRE_Pos                (16U)                               \n#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */\n#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 \n#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */\n#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */\n#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */\n#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */\n#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */\n\n/*!< MCO1 configuration */\n#define RCC_CFGR_MCO1_Pos                  (21U)                               \n#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */\n#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   \n#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */\n#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */\n\n#define RCC_CFGR_I2SSRC_Pos                (23U)                               \n#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */\n#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 \n\n#define RCC_CFGR_MCO1PRE_Pos               (24U)                               \n#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */\n#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                \n#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */\n#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */\n#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO2PRE_Pos               (27U)                               \n#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */\n#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                \n#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */\n#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */\n#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */\n\n#define RCC_CFGR_MCO2_Pos                  (30U)                               \n#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */\n#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   \n#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */\n#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */\n\n/********************  Bit definition for RCC_CIR register  *******************/\n#define RCC_CIR_LSIRDYF_Pos                (0U)                                \n#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 \n#define RCC_CIR_LSERDYF_Pos                (1U)                                \n#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 \n#define RCC_CIR_HSIRDYF_Pos                (2U)                                \n#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 \n#define RCC_CIR_HSERDYF_Pos                (3U)                                \n#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 \n#define RCC_CIR_PLLRDYF_Pos                (4U)                                \n#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 \n#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                \n#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */\n#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              \n\n#define RCC_CIR_CSSF_Pos                   (7U)                                \n#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */\n#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    \n#define RCC_CIR_LSIRDYIE_Pos               (8U)                                \n#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                \n#define RCC_CIR_LSERDYIE_Pos               (9U)                                \n#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                \n#define RCC_CIR_HSIRDYIE_Pos               (10U)                               \n#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                \n#define RCC_CIR_HSERDYIE_Pos               (11U)                               \n#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                \n#define RCC_CIR_PLLRDYIE_Pos               (12U)                               \n#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                \n#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               \n#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */\n#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             \n\n#define RCC_CIR_LSIRDYC_Pos                (16U)                               \n#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 \n#define RCC_CIR_LSERDYC_Pos                (17U)                               \n#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 \n#define RCC_CIR_HSIRDYC_Pos                (18U)                               \n#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 \n#define RCC_CIR_HSERDYC_Pos                (19U)                               \n#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 \n#define RCC_CIR_PLLRDYC_Pos                (20U)                               \n#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 \n#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               \n#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */\n#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              \n\n#define RCC_CIR_CSSC_Pos                   (23U)                               \n#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */\n#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    \n\n/********************  Bit definition for RCC_AHB1RSTR register  **************/\n#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                \n#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\n#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           \n#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                \n#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\n#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           \n#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                \n#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\n#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           \n#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                \n#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\n#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           \n#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                \n#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\n#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           \n#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                \n#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\n#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           \n#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                \n#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\n#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           \n#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                \n#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           \n#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                \n#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\n#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           \n#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               \n#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */\n#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             \n#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               \n#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */\n#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            \n#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               \n#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */\n#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            \n#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               \n#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */\n#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            \n\n/********************  Bit definition for RCC_AHB2RSTR register  **************/\n#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                \n#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */\n#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             \n#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                \n#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\n#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           \n/********************  Bit definition for RCC_AHB3RSTR register  **************/\n#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)                                \n#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */\n#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk            \n\n\n/********************  Bit definition for RCC_APB1RSTR register  **************/\n#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                \n#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            \n#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                \n#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            \n#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                \n#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            \n#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                \n#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */\n#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            \n#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                \n#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */\n#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            \n#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                \n#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */\n#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            \n#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                \n#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\n#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           \n#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                \n#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\n#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           \n#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                \n#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\n#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           \n#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               \n#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            \n#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               \n#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            \n#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               \n#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */\n#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            \n#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               \n#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          \n#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               \n#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          \n#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               \n#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\n#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           \n#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               \n#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\n#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           \n#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               \n#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            \n#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               \n#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            \n#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               \n#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */\n#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            \n#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               \n#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            \n#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               \n#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */\n#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            \n#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               \n#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             \n#define RCC_APB1RSTR_DACRST_Pos            (29U)                               \n#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */\n#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             \n\n/********************  Bit definition for RCC_APB2RSTR register  **************/\n#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                \n#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */\n#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            \n#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                \n#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */\n#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            \n#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                \n#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          \n#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                \n#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          \n#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                \n#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */\n#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             \n#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               \n#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */\n#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            \n#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               \n#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            \n#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               \n#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          \n#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               \n#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */\n#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            \n#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               \n#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\n#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           \n#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               \n#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\n#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           \n\n/* Old SPI1RST bit definition, maintained for legacy purpose */\n#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\n\n/********************  Bit definition for RCC_AHB1ENR register  ***************/\n#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                \n#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */\n#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             \n#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                \n#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */\n#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             \n#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                \n#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             \n#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                \n#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */\n#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             \n#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                \n#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */\n#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             \n#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                \n#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */\n#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             \n#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                \n#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */\n#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             \n#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                \n#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             \n#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                \n#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */\n#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             \n#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               \n#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */\n#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               \n#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               \n#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           \n#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               \n#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */\n#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        \n#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               \n#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */\n#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              \n#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               \n#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */\n#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              \n#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               \n#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */\n#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             \n#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               \n#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         \n/********************  Bit definition for RCC_AHB2ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */\n\n#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                \n#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */\n#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               \n#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                \n#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */\n#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             \n\n/********************  Bit definition for RCC_AHB3ENR register  ***************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)\n */\n#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */\n\n#define RCC_AHB3ENR_FSMCEN_Pos             (0U)                                \n#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */\n#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk              \n\n/********************  Bit definition for RCC_APB1ENR register  ***************/\n#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                \n#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              \n#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                \n#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              \n#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                \n#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              \n#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                \n#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */\n#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              \n#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                \n#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */\n#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              \n#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                \n#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */\n#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              \n#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                \n#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */\n#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             \n#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                \n#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */\n#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             \n#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                \n#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */\n#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             \n#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               \n#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              \n#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               \n#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              \n#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               \n#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */\n#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              \n#define RCC_APB1ENR_USART2EN_Pos           (17U)                               \n#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            \n#define RCC_APB1ENR_USART3EN_Pos           (18U)                               \n#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            \n#define RCC_APB1ENR_UART4EN_Pos            (19U)                               \n#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */\n#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             \n#define RCC_APB1ENR_UART5EN_Pos            (20U)                               \n#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */\n#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             \n#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               \n#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              \n#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               \n#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              \n#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               \n#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */\n#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              \n#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               \n#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              \n#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               \n#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */\n#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              \n#define RCC_APB1ENR_PWREN_Pos              (28U)                               \n#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               \n#define RCC_APB1ENR_DACEN_Pos              (29U)                               \n#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */\n#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               \n\n/********************  Bit definition for RCC_APB2ENR register  ***************/\n#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                \n#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */\n#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              \n#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                \n#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */\n#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              \n#define RCC_APB2ENR_USART1EN_Pos           (4U)                                \n#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            \n#define RCC_APB2ENR_USART6EN_Pos           (5U)                                \n#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            \n#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                \n#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */\n#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              \n#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                \n#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              \n#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               \n#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              \n#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               \n#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */\n#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              \n#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               \n#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              \n#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               \n#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */\n#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            \n#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               \n#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */\n#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              \n#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               \n#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */\n#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             \n#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               \n#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */\n#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             \n\n/********************  Bit definition for RCC_AHB1LPENR register  *************/\n#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                \n#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         \n#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                \n#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\n#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                \n#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\n#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         \n#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                \n#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\n#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                \n#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\n#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         \n#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                \n#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\n#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                \n#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                \n#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         \n#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                \n#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\n#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         \n#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               \n#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\n#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           \n#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               \n#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\n#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         \n#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               \n#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\n#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         \n#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               \n#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         \n#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               \n#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\n#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       \n#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               \n#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          \n#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               \n#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          \n\n#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               \n#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\n#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         \n#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               \n#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\n#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     \n\n/********************  Bit definition for RCC_AHB2LPENR register  *************/\n#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                \n#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\n#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           \n#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                \n#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\n#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         \n\n/********************  Bit definition for RCC_AHB3LPENR register  *************/\n#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)                                \n#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */\n#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk          \n\n/********************  Bit definition for RCC_APB1LPENR register  *************/\n#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                \n#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          \n#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                \n#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          \n#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                \n#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\n#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          \n#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                \n#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\n#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          \n#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                \n#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          \n#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                \n#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          \n#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                \n#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\n#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         \n#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                \n#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\n#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         \n#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                \n#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         \n#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               \n#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          \n#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               \n#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          \n#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               \n#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\n#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          \n#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               \n#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        \n#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               \n#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        \n#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               \n#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\n#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         \n#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               \n#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\n#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         \n#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               \n#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\n#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          \n#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               \n#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\n#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          \n#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               \n#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\n#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          \n#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               \n#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\n#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          \n#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               \n#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */\n#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          \n#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               \n#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\n#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           \n#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               \n#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\n#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           \n\n/********************  Bit definition for RCC_APB2LPENR register  *************/\n#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                \n#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\n#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          \n#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                \n#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\n#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          \n#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                \n#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\n#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        \n#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                \n#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\n#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        \n#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                \n#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\n#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          \n#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                \n#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\n#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          \n#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               \n#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\n#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          \n#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               \n#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */\n#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          \n#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               \n#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\n#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          \n#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               \n#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\n#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        \n#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               \n#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\n#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          \n#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               \n#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\n#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         \n#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               \n#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\n#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         \n\n/********************  Bit definition for RCC_BDCR register  ******************/\n#define RCC_BDCR_LSEON_Pos                 (0U)                                \n#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  \n#define RCC_BDCR_LSERDY_Pos                (1U)                                \n#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 \n#define RCC_BDCR_LSEBYP_Pos                (2U)                                \n#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 \n\n#define RCC_BDCR_RTCSEL_Pos                (8U)                                \n#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 \n#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */\n\n#define RCC_BDCR_RTCEN_Pos                 (15U)                               \n#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  \n#define RCC_BDCR_BDRST_Pos                 (16U)                               \n#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  \n\n/********************  Bit definition for RCC_CSR register  *******************/\n#define RCC_CSR_LSION_Pos                  (0U)                                \n#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */\n#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   \n#define RCC_CSR_LSIRDY_Pos                 (1U)                                \n#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  \n#define RCC_CSR_RMVF_Pos                   (24U)                               \n#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */\n#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    \n#define RCC_CSR_BORRSTF_Pos                (25U)                               \n#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */\n#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 \n#define RCC_CSR_PINRSTF_Pos                (26U)\n#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk\n#define RCC_CSR_PORRSTF_Pos                (27U)                               \n#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 \n#define RCC_CSR_SFTRSTF_Pos                (28U)                               \n#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 \n#define RCC_CSR_IWDGRSTF_Pos               (29U)\n#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk\n#define RCC_CSR_WWDGRSTF_Pos               (30U)                               \n#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                \n#define RCC_CSR_LPWRRSTF_Pos               (31U)                               \n#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk\n/* Legacy defines */\n#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF\n#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF\n\n/********************  Bit definition for RCC_SSCGR register  *****************/\n#define RCC_SSCGR_MODPER_Pos               (0U)                                \n#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */\n#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                \n#define RCC_SSCGR_INCSTEP_Pos              (13U)                               \n#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */\n#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               \n#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               \n#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */\n#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             \n#define RCC_SSCGR_SSCGEN_Pos               (31U)                               \n#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */\n#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                \n\n/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\n#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                \n#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\n#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          \n#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\n#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\n#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\n#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\n#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\n#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\n#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\n#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\n\n#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               \n#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          \n#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\n#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    RNG                                     */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bits definition for RNG_CR register  *******************/\n#define RNG_CR_RNGEN_Pos    (2U)                                               \n#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */\n#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   \n#define RNG_CR_IE_Pos       (3U)                                               \n#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */\n#define RNG_CR_IE           RNG_CR_IE_Msk                                      \n\n/********************  Bits definition for RNG_SR register  *******************/\n#define RNG_SR_DRDY_Pos     (0U)                                               \n#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */\n#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    \n#define RNG_SR_CECS_Pos     (1U)                                               \n#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */\n#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    \n#define RNG_SR_SECS_Pos     (2U)                                               \n#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */\n#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    \n#define RNG_SR_CEIS_Pos     (5U)                                               \n#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */\n#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    \n#define RNG_SR_SEIS_Pos     (6U)                                               \n#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */\n#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    \n\n/******************************************************************************/\n/*                                                                            */\n/*                           Real-Time Clock (RTC)                            */\n/*                                                                            */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)\n */\n#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */\n#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */\n/********************  Bits definition for RTC_TR register  *******************/\n#define RTC_TR_PM_Pos                 (22U)                                    \n#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */\n#define RTC_TR_PM                     RTC_TR_PM_Msk                            \n#define RTC_TR_HT_Pos                 (20U)                                    \n#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */\n#define RTC_TR_HT                     RTC_TR_HT_Msk                            \n#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */\n#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */\n#define RTC_TR_HU_Pos                 (16U)                                    \n#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */\n#define RTC_TR_HU                     RTC_TR_HU_Msk                            \n#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */\n#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */\n#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */\n#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */\n#define RTC_TR_MNT_Pos                (12U)                                    \n#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */\n#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           \n#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */\n#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */\n#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */\n#define RTC_TR_MNU_Pos                (8U)                                     \n#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */\n#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           \n#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */\n#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */\n#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */\n#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */\n#define RTC_TR_ST_Pos                 (4U)                                     \n#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */\n#define RTC_TR_ST                     RTC_TR_ST_Msk                            \n#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */\n#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */\n#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */\n#define RTC_TR_SU_Pos                 (0U)                                     \n#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */\n#define RTC_TR_SU                     RTC_TR_SU_Msk                            \n#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */\n#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */\n#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */\n#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_DR register  *******************/\n#define RTC_DR_YT_Pos                 (20U)                                    \n#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */\n#define RTC_DR_YT                     RTC_DR_YT_Msk                            \n#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */\n#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */\n#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */\n#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */\n#define RTC_DR_YU_Pos                 (16U)                                    \n#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */\n#define RTC_DR_YU                     RTC_DR_YU_Msk                            \n#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */\n#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */\n#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */\n#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */\n#define RTC_DR_WDU_Pos                (13U)                                    \n#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */\n#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           \n#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */\n#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */\n#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */\n#define RTC_DR_MT_Pos                 (12U)                                    \n#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */\n#define RTC_DR_MT                     RTC_DR_MT_Msk                            \n#define RTC_DR_MU_Pos                 (8U)                                     \n#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */\n#define RTC_DR_MU                     RTC_DR_MU_Msk                            \n#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */\n#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */\n#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */\n#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */\n#define RTC_DR_DT_Pos                 (4U)                                     \n#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */\n#define RTC_DR_DT                     RTC_DR_DT_Msk                            \n#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */\n#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */\n#define RTC_DR_DU_Pos                 (0U)                                     \n#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */\n#define RTC_DR_DU                     RTC_DR_DU_Msk                            \n#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */\n#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */\n#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */\n#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_CR register  *******************/\n#define RTC_CR_COE_Pos                (23U)                                    \n#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */\n#define RTC_CR_COE                    RTC_CR_COE_Msk                           \n#define RTC_CR_OSEL_Pos               (21U)                                    \n#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */\n#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          \n#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */\n#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */\n#define RTC_CR_POL_Pos                (20U)                                    \n#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */\n#define RTC_CR_POL                    RTC_CR_POL_Msk                           \n#define RTC_CR_COSEL_Pos              (19U)                                    \n#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */\n#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         \n#define RTC_CR_BKP_Pos                 (18U)                                   \n#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */\n#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          \n#define RTC_CR_SUB1H_Pos              (17U)                                    \n#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */\n#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         \n#define RTC_CR_ADD1H_Pos              (16U)                                    \n#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */\n#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         \n#define RTC_CR_TSIE_Pos               (15U)                                    \n#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */\n#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          \n#define RTC_CR_WUTIE_Pos              (14U)                                    \n#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */\n#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         \n#define RTC_CR_ALRBIE_Pos             (13U)                                    \n#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */\n#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        \n#define RTC_CR_ALRAIE_Pos             (12U)                                    \n#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */\n#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        \n#define RTC_CR_TSE_Pos                (11U)                                    \n#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */\n#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           \n#define RTC_CR_WUTE_Pos               (10U)                                    \n#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */\n#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          \n#define RTC_CR_ALRBE_Pos              (9U)                                     \n#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */\n#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         \n#define RTC_CR_ALRAE_Pos              (8U)                                     \n#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */\n#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         \n#define RTC_CR_DCE_Pos                (7U)                                     \n#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */\n#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           \n#define RTC_CR_FMT_Pos                (6U)                                     \n#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */\n#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           \n#define RTC_CR_BYPSHAD_Pos            (5U)                                     \n#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */\n#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       \n#define RTC_CR_REFCKON_Pos            (4U)                                     \n#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */\n#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       \n#define RTC_CR_TSEDGE_Pos             (3U)                                     \n#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */\n#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        \n#define RTC_CR_WUCKSEL_Pos            (0U)                                     \n#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */\n#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       \n#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */\n#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */\n#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */\n\n/* Legacy defines */\n#define RTC_CR_BCK                     RTC_CR_BKP\n\n/********************  Bits definition for RTC_ISR register  ******************/\n#define RTC_ISR_RECALPF_Pos           (16U)                                    \n#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */\n#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      \n#define RTC_ISR_TAMP1F_Pos            (13U)                                    \n#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */\n#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       \n#define RTC_ISR_TAMP2F_Pos            (14U)                                    \n#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */\n#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       \n#define RTC_ISR_TSOVF_Pos             (12U)                                    \n#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */\n#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        \n#define RTC_ISR_TSF_Pos               (11U)                                    \n#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */\n#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          \n#define RTC_ISR_WUTF_Pos              (10U)                                    \n#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */\n#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         \n#define RTC_ISR_ALRBF_Pos             (9U)                                     \n#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */\n#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        \n#define RTC_ISR_ALRAF_Pos             (8U)                                     \n#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */\n#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        \n#define RTC_ISR_INIT_Pos              (7U)                                     \n#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */\n#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         \n#define RTC_ISR_INITF_Pos             (6U)                                     \n#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */\n#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        \n#define RTC_ISR_RSF_Pos               (5U)                                     \n#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */\n#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          \n#define RTC_ISR_INITS_Pos             (4U)                                     \n#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */\n#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        \n#define RTC_ISR_SHPF_Pos              (3U)                                     \n#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */\n#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         \n#define RTC_ISR_WUTWF_Pos             (2U)                                     \n#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */\n#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        \n#define RTC_ISR_ALRBWF_Pos            (1U)                                     \n#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */\n#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       \n#define RTC_ISR_ALRAWF_Pos            (0U)                                     \n#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */\n#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       \n\n/********************  Bits definition for RTC_PRER register  *****************/\n#define RTC_PRER_PREDIV_A_Pos         (16U)                                    \n#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */\n#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    \n#define RTC_PRER_PREDIV_S_Pos         (0U)                                     \n#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */\n#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    \n\n/********************  Bits definition for RTC_WUTR register  *****************/\n#define RTC_WUTR_WUT_Pos              (0U)                                     \n#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */\n#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         \n\n/********************  Bits definition for RTC_CALIBR register  ***************/\n#define RTC_CALIBR_DCS_Pos            (7U)                                     \n#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */\n#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       \n#define RTC_CALIBR_DC_Pos             (0U)                                     \n#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */\n#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        \n\n/********************  Bits definition for RTC_ALRMAR register  ***************/\n#define RTC_ALRMAR_MSK4_Pos           (31U)                                    \n#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      \n#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    \n#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     \n#define RTC_ALRMAR_DT_Pos             (28U)                                    \n#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        \n#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMAR_DU_Pos             (24U)                                    \n#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        \n#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMAR_MSK3_Pos           (23U)                                    \n#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      \n#define RTC_ALRMAR_PM_Pos             (22U)                                    \n#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        \n#define RTC_ALRMAR_HT_Pos             (20U)                                    \n#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        \n#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMAR_HU_Pos             (16U)                                    \n#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        \n#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMAR_MSK2_Pos           (15U)                                    \n#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      \n#define RTC_ALRMAR_MNT_Pos            (12U)                                    \n#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       \n#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMAR_MNU_Pos            (8U)                                     \n#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       \n#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMAR_MSK1_Pos           (7U)                                     \n#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      \n#define RTC_ALRMAR_ST_Pos             (4U)                                     \n#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        \n#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMAR_SU_Pos             (0U)                                     \n#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        \n#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_ALRMBR register  ***************/\n#define RTC_ALRMBR_MSK4_Pos           (31U)                                    \n#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */\n#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      \n#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    \n#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */\n#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     \n#define RTC_ALRMBR_DT_Pos             (28U)                                    \n#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */\n#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        \n#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */\n#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */\n#define RTC_ALRMBR_DU_Pos             (24U)                                    \n#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */\n#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        \n#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */\n#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */\n#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */\n#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */\n#define RTC_ALRMBR_MSK3_Pos           (23U)                                    \n#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */\n#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      \n#define RTC_ALRMBR_PM_Pos             (22U)                                    \n#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */\n#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        \n#define RTC_ALRMBR_HT_Pos             (20U)                                    \n#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */\n#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        \n#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */\n#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */\n#define RTC_ALRMBR_HU_Pos             (16U)                                    \n#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */\n#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        \n#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */\n#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */\n#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */\n#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */\n#define RTC_ALRMBR_MSK2_Pos           (15U)                                    \n#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */\n#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      \n#define RTC_ALRMBR_MNT_Pos            (12U)                                    \n#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */\n#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       \n#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */\n#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */\n#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */\n#define RTC_ALRMBR_MNU_Pos            (8U)                                     \n#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */\n#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       \n#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */\n#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */\n#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */\n#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */\n#define RTC_ALRMBR_MSK1_Pos           (7U)                                     \n#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */\n#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      \n#define RTC_ALRMBR_ST_Pos             (4U)                                     \n#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */\n#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        \n#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */\n#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */\n#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */\n#define RTC_ALRMBR_SU_Pos             (0U)                                     \n#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */\n#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        \n#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */\n#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */\n#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */\n#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_WPR register  ******************/\n#define RTC_WPR_KEY_Pos               (0U)                                     \n#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */\n#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          \n\n/********************  Bits definition for RTC_SSR register  ******************/\n#define RTC_SSR_SS_Pos                (0U)                                     \n#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */\n#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           \n\n/********************  Bits definition for RTC_SHIFTR register  ***************/\n#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     \n#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */\n#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     \n#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    \n#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */\n#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     \n\n/********************  Bits definition for RTC_TSTR register  *****************/\n#define RTC_TSTR_PM_Pos               (22U)                                    \n#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */\n#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          \n#define RTC_TSTR_HT_Pos               (20U)                                    \n#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */\n#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          \n#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */\n#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */\n#define RTC_TSTR_HU_Pos               (16U)                                    \n#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */\n#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          \n#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */\n#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */\n#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */\n#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */\n#define RTC_TSTR_MNT_Pos              (12U)                                    \n#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */\n#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         \n#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */\n#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */\n#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */\n#define RTC_TSTR_MNU_Pos              (8U)                                     \n#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */\n#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         \n#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */\n#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */\n#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */\n#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */\n#define RTC_TSTR_ST_Pos               (4U)                                     \n#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */\n#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          \n#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */\n#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */\n#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */\n#define RTC_TSTR_SU_Pos               (0U)                                     \n#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */\n#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          \n#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */\n#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */\n#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */\n#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSDR register  *****************/\n#define RTC_TSDR_WDU_Pos              (13U)                                    \n#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */\n#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         \n#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */\n#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */\n#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */\n#define RTC_TSDR_MT_Pos               (12U)                                    \n#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */\n#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          \n#define RTC_TSDR_MU_Pos               (8U)                                     \n#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */\n#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          \n#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */\n#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */\n#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */\n#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */\n#define RTC_TSDR_DT_Pos               (4U)                                     \n#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */\n#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          \n#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */\n#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */\n#define RTC_TSDR_DU_Pos               (0U)                                     \n#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */\n#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          \n#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */\n#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */\n#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */\n#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */\n\n/********************  Bits definition for RTC_TSSSR register  ****************/\n#define RTC_TSSSR_SS_Pos              (0U)                                     \n#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */\n#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         \n\n/********************  Bits definition for RTC_CAL register  *****************/\n#define RTC_CALR_CALP_Pos             (15U)                                    \n#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */\n#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        \n#define RTC_CALR_CALW8_Pos            (14U)                                    \n#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */\n#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       \n#define RTC_CALR_CALW16_Pos           (13U)                                    \n#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */\n#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      \n#define RTC_CALR_CALM_Pos             (0U)                                     \n#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */\n#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        \n#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */\n#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */\n#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */\n#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */\n#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */\n#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */\n#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */\n#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */\n#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */\n\n/********************  Bits definition for RTC_TAFCR register  ****************/\n#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    \n#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */\n#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               \n#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    \n#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */\n#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    \n#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)                                    \n#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */\n#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk                  \n#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    \n#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */\n#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  \n#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    \n#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */\n#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   \n#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */\n#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */\n#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    \n#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */\n#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    \n#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */\n#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */\n#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     \n#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */\n#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   \n#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */\n#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */\n#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */\n#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     \n#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */\n#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     \n#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     \n#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */\n#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   \n#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     \n#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */\n#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     \n#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     \n#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */\n#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     \n#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     \n#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */\n#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   \n#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     \n#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */\n#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     \n\n/* Legacy defines */\n#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL\n\n/********************  Bits definition for RTC_ALRMASSR register  *************/\n#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    \n#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  \n#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMASSR_SS_Pos           (0U)                                     \n#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      \n\n/********************  Bits definition for RTC_ALRMBSSR register  *************/\n#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    \n#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */\n#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  \n#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */\n#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */\n#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */\n#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */\n#define RTC_ALRMBSSR_SS_Pos           (0U)                                     \n#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */\n#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      \n\n/********************  Bits definition for RTC_BKP0R register  ****************/\n#define RTC_BKP0R_Pos                 (0U)                                     \n#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP0R                     RTC_BKP0R_Msk                            \n\n/********************  Bits definition for RTC_BKP1R register  ****************/\n#define RTC_BKP1R_Pos                 (0U)                                     \n#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP1R                     RTC_BKP1R_Msk                            \n\n/********************  Bits definition for RTC_BKP2R register  ****************/\n#define RTC_BKP2R_Pos                 (0U)                                     \n#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP2R                     RTC_BKP2R_Msk                            \n\n/********************  Bits definition for RTC_BKP3R register  ****************/\n#define RTC_BKP3R_Pos                 (0U)                                     \n#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP3R                     RTC_BKP3R_Msk                            \n\n/********************  Bits definition for RTC_BKP4R register  ****************/\n#define RTC_BKP4R_Pos                 (0U)                                     \n#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP4R                     RTC_BKP4R_Msk                            \n\n/********************  Bits definition for RTC_BKP5R register  ****************/\n#define RTC_BKP5R_Pos                 (0U)                                     \n#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP5R                     RTC_BKP5R_Msk                            \n\n/********************  Bits definition for RTC_BKP6R register  ****************/\n#define RTC_BKP6R_Pos                 (0U)                                     \n#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP6R                     RTC_BKP6R_Msk                            \n\n/********************  Bits definition for RTC_BKP7R register  ****************/\n#define RTC_BKP7R_Pos                 (0U)                                     \n#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP7R                     RTC_BKP7R_Msk                            \n\n/********************  Bits definition for RTC_BKP8R register  ****************/\n#define RTC_BKP8R_Pos                 (0U)                                     \n#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP8R                     RTC_BKP8R_Msk                            \n\n/********************  Bits definition for RTC_BKP9R register  ****************/\n#define RTC_BKP9R_Pos                 (0U)                                     \n#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */\n#define RTC_BKP9R                     RTC_BKP9R_Msk                            \n\n/********************  Bits definition for RTC_BKP10R register  ***************/\n#define RTC_BKP10R_Pos                (0U)                                     \n#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP10R                    RTC_BKP10R_Msk                           \n\n/********************  Bits definition for RTC_BKP11R register  ***************/\n#define RTC_BKP11R_Pos                (0U)                                     \n#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP11R                    RTC_BKP11R_Msk                           \n\n/********************  Bits definition for RTC_BKP12R register  ***************/\n#define RTC_BKP12R_Pos                (0U)                                     \n#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP12R                    RTC_BKP12R_Msk                           \n\n/********************  Bits definition for RTC_BKP13R register  ***************/\n#define RTC_BKP13R_Pos                (0U)                                     \n#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP13R                    RTC_BKP13R_Msk                           \n\n/********************  Bits definition for RTC_BKP14R register  ***************/\n#define RTC_BKP14R_Pos                (0U)                                     \n#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP14R                    RTC_BKP14R_Msk                           \n\n/********************  Bits definition for RTC_BKP15R register  ***************/\n#define RTC_BKP15R_Pos                (0U)                                     \n#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP15R                    RTC_BKP15R_Msk                           \n\n/********************  Bits definition for RTC_BKP16R register  ***************/\n#define RTC_BKP16R_Pos                (0U)                                     \n#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP16R                    RTC_BKP16R_Msk                           \n\n/********************  Bits definition for RTC_BKP17R register  ***************/\n#define RTC_BKP17R_Pos                (0U)                                     \n#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP17R                    RTC_BKP17R_Msk                           \n\n/********************  Bits definition for RTC_BKP18R register  ***************/\n#define RTC_BKP18R_Pos                (0U)                                     \n#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP18R                    RTC_BKP18R_Msk                           \n\n/********************  Bits definition for RTC_BKP19R register  ***************/\n#define RTC_BKP19R_Pos                (0U)                                     \n#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */\n#define RTC_BKP19R                    RTC_BKP19R_Msk                           \n\n/******************** Number of backup registers ******************************/\n#define RTC_BKP_NUMBER                       0x000000014U\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                          SD host Interface                                 */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SDIO_POWER register  ******************/\n#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    \n#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */\n#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */\n#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */\n#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */\n\n/******************  Bit definition for SDIO_CLKCR register  ******************/\n#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    \n#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */\n#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */\n#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    \n#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */\n#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */\n#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    \n#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */\n#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */\n#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   \n#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */\n#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */\n\n#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   \n#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */\n#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\n#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */\n#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */\n\n#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   \n#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */\n#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */\n#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   \n#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */\n#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */\n\n/*******************  Bit definition for SDIO_ARG register  *******************/\n#define SDIO_ARG_CMDARG_Pos            (0U)                                    \n#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */\n#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */\n\n/*******************  Bit definition for SDIO_CMD register  *******************/\n#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    \n#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */\n#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */\n\n#define SDIO_CMD_WAITRESP_Pos          (6U)                                    \n#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */\n#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */\n#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */\n#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */\n\n#define SDIO_CMD_WAITINT_Pos           (8U)                                    \n#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */\n#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */\n#define SDIO_CMD_WAITPEND_Pos          (9U)                                    \n#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */\n#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\n#define SDIO_CMD_CPSMEN_Pos            (10U)                                   \n#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */\n#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */\n#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   \n#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */\n#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */\n#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)                                   \n#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */\n#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */\n#define SDIO_CMD_NIEN_Pos              (13U)                                   \n#define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */\n#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */\n#define SDIO_CMD_CEATACMD_Pos          (14U)                                   \n#define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */\n#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */\n\n/*****************  Bit definition for SDIO_RESPCMD register  *****************/\n#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    \n#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */\n#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */\n\n/******************  Bit definition for SDIO_RESP0 register  ******************/\n#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    \n#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP1 register  ******************/\n#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    \n#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP2 register  ******************/\n#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    \n#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP3 register  ******************/\n#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    \n#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_RESP4 register  ******************/\n#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    \n#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */\n\n/******************  Bit definition for SDIO_DTIMER register  *****************/\n#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    \n#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */\n\n/******************  Bit definition for SDIO_DLEN register  *******************/\n#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    \n#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */\n\n/******************  Bit definition for SDIO_DCTRL register  ******************/\n#define SDIO_DCTRL_DTEN_Pos            (0U)                                    \n#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */\n#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */\n#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    \n#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */\n#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */\n#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    \n#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */\n#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */\n#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    \n#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */\n#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */\n\n#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    \n#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */\n#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */\n#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */\n#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */\n#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */\n#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */\n\n#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    \n#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */\n#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */\n#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    \n#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */\n#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */\n#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   \n#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */\n#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */\n#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   \n#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */\n#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */\n\n/******************  Bit definition for SDIO_DCOUNT register  *****************/\n#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    \n#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\n#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */\n\n/******************  Bit definition for SDIO_STA register  ********************/\n#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    \n#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */\n#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */\n#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    \n#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */\n#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */\n#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    \n#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */\n#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */\n#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    \n#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */\n#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */\n#define SDIO_STA_TXUNDERR_Pos          (4U)                                    \n#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */\n#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */\n#define SDIO_STA_RXOVERR_Pos           (5U)                                    \n#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */\n#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */\n#define SDIO_STA_CMDREND_Pos           (6U)                                    \n#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */\n#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */\n#define SDIO_STA_CMDSENT_Pos           (7U)                                    \n#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */\n#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */\n#define SDIO_STA_DATAEND_Pos           (8U)                                    \n#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */\n#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */\n#define SDIO_STA_STBITERR_Pos          (9U)                                    \n#define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */\n#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */\n#define SDIO_STA_DBCKEND_Pos           (10U)                                   \n#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */\n#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */\n#define SDIO_STA_CMDACT_Pos            (11U)                                   \n#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */\n#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */\n#define SDIO_STA_TXACT_Pos             (12U)                                   \n#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */\n#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */\n#define SDIO_STA_RXACT_Pos             (13U)                                   \n#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */\n#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */\n#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   \n#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */\n#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\n#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   \n#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */\n#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\n#define SDIO_STA_TXFIFOF_Pos           (16U)                                   \n#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */\n#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */\n#define SDIO_STA_RXFIFOF_Pos           (17U)                                   \n#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */\n#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */\n#define SDIO_STA_TXFIFOE_Pos           (18U)                                   \n#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */\n#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */\n#define SDIO_STA_RXFIFOE_Pos           (19U)                                   \n#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */\n#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */\n#define SDIO_STA_TXDAVL_Pos            (20U)                                   \n#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */\n#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */\n#define SDIO_STA_RXDAVL_Pos            (21U)                                   \n#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */\n#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */\n#define SDIO_STA_SDIOIT_Pos            (22U)                                   \n#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */\n#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */\n#define SDIO_STA_CEATAEND_Pos          (23U)                                   \n#define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */\n#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */\n\n/*******************  Bit definition for SDIO_ICR register  *******************/\n#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    \n#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */\n#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */\n#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    \n#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */\n#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */\n#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    \n#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */\n#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */\n#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    \n#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */\n#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */\n#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    \n#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */\n#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */\n#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    \n#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */\n#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */\n#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    \n#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */\n#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */\n#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    \n#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */\n#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */\n#define SDIO_ICR_DATAENDC_Pos          (8U)                                    \n#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */\n#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */\n#define SDIO_ICR_STBITERRC_Pos         (9U)                                    \n#define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */\n#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */\n#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   \n#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */\n#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */\n#define SDIO_ICR_SDIOITC_Pos           (22U)                                   \n#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */\n#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */\n#define SDIO_ICR_CEATAENDC_Pos         (23U)                                   \n#define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */\n#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */\n\n/******************  Bit definition for SDIO_MASK register  *******************/\n#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    \n#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */\n#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */\n#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    \n#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */\n#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */\n#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    \n#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */\n#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */\n#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    \n#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */\n#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */\n#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    \n#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */\n#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */\n#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    \n#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */\n#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */\n#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    \n#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */\n#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */\n#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    \n#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */\n#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */\n#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    \n#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */\n#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */\n#define SDIO_MASK_STBITERRIE_Pos       (9U)                                    \n#define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */\n#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */\n#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   \n#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */\n#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */\n#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   \n#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */\n#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */\n#define SDIO_MASK_TXACTIE_Pos          (12U)                                   \n#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */\n#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */\n#define SDIO_MASK_RXACTIE_Pos          (13U)                                   \n#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */\n#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */\n#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   \n#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */\n#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */\n#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   \n#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */\n#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */\n#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   \n#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */\n#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */\n#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   \n#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */\n#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */\n#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   \n#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */\n#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   \n#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */\n#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */\n#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   \n#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */\n#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */\n#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   \n#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */\n#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */\n#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   \n#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */\n#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */\n#define SDIO_MASK_CEATAENDIE_Pos       (23U)                                   \n#define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */\n#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */\n\n/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\n#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    \n#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\n#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */\n\n/******************  Bit definition for SDIO_FIFO register  *******************/\n#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    \n#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\n#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos            (0U)                                       \n#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */\n#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */\n#define SPI_CR1_CPOL_Pos            (1U)                                       \n#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */\n#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */\n#define SPI_CR1_MSTR_Pos            (2U)                                       \n#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */\n#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */\n\n#define SPI_CR1_BR_Pos              (3U)                                       \n#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */\n#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */\n#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */\n#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos             (6U)                                       \n#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */\n#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */\n#define SPI_CR1_LSBFIRST_Pos        (7U)                                       \n#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */\n#define SPI_CR1_SSI_Pos             (8U)                                       \n#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */\n#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */\n#define SPI_CR1_SSM_Pos             (9U)                                       \n#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */\n#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */\n#define SPI_CR1_RXONLY_Pos          (10U)                                      \n#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */\n#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */\n#define SPI_CR1_DFF_Pos             (11U)                                      \n#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */\n#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */\n#define SPI_CR1_CRCNEXT_Pos         (12U)                                      \n#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */\n#define SPI_CR1_CRCEN_Pos           (13U)                                      \n#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */\n#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */\n#define SPI_CR1_BIDIOE_Pos          (14U)                                      \n#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos        (15U)                                      \n#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos         (0U)                                       \n#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */\n#define SPI_CR2_TXDMAEN_Pos         (1U)                                       \n#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */\n#define SPI_CR2_SSOE_Pos            (2U)                                       \n#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */\n#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */\n#define SPI_CR2_FRF_Pos             (4U)                                       \n#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */\n#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */\n#define SPI_CR2_ERRIE_Pos           (5U)                                       \n#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */\n#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */\n#define SPI_CR2_RXNEIE_Pos          (6U)                                       \n#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos           (7U)                                       \n#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */\n#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos             (0U)                                       \n#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */\n#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos              (1U)                                       \n#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */\n#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */\n#define SPI_SR_CHSIDE_Pos           (2U)                                       \n#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */\n#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */\n#define SPI_SR_UDR_Pos              (3U)                                       \n#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */\n#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */\n#define SPI_SR_CRCERR_Pos           (4U)                                       \n#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */\n#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */\n#define SPI_SR_MODF_Pos             (5U)                                       \n#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */\n#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */\n#define SPI_SR_OVR_Pos              (6U)                                       \n#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */\n#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */\n#define SPI_SR_BSY_Pos              (7U)                                       \n#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */\n#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */\n#define SPI_SR_FRE_Pos              (8U)                                       \n#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */\n#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos               (0U)                                       \n#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */\n#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       \n#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       \n#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       \n#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */\n\n/******************  Bit definition for SPI_I2SCFGR register  *****************/\n#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       \n#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */\n#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */\n\n#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       \n#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */\n#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */\n#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */\n#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */\n\n#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       \n#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */\n#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */\n\n#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       \n#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */\n#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */\n#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */\n#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */\n\n#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       \n#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */\n#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */\n\n#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       \n#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */\n#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */\n#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */\n#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */\n\n#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      \n#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */\n#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */\n#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      \n#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */\n\n/******************  Bit definition for SPI_I2SPR register  *******************/\n#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       \n#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */\n#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */\n#define SPI_I2SPR_ODD_Pos           (8U)                                       \n#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */\n#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */\n#define SPI_I2SPR_MCKOE_Pos         (9U)                                       \n#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */\n#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 SYSCFG                                     */\n/*                                                                            */\n/******************************************************************************/\n/******************  Bit definition for SYSCFG_MEMRMP register  ***************/\n#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              \n#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */\n#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */\n#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */\n#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */\n/******************  Bit definition for SYSCFG_PMC register  ******************/\n#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             \n#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */\n#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */\n/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\n#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL    \n\n/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\n#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              \n#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */\n#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              \n#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */\n#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              \n#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */\n#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             \n#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */\n/**\n  * @brief   EXTI0 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */\n#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */\n\n/**\n  * @brief   EXTI1 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */\n#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */\n\n/**\n  * @brief   EXTI2 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */\n#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */\n\n/**\n  * @brief   EXTI3 configuration  \n  */\n#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */\n#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\n#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              \n#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */\n#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              \n#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */\n#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              \n#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */\n#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             \n#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */\n\n/**\n  * @brief   EXTI4 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */\n#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */\n\n/**\n  * @brief   EXTI5 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */\n#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */\n\n/**\n  * @brief   EXTI6 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */\n#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */\n\n/**\n  * @brief   EXTI7 configuration  \n  */\n#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */\n#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\n#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              \n#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */\n#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              \n#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */\n#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              \n#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */\n#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             \n#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */\n\n/**\n  * @brief   EXTI8 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */\n#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */\n\n/**\n  * @brief   EXTI9 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */\n#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */\n\n/**\n  * @brief   EXTI10 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */\n#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */\n\n/**\n  * @brief   EXTI11 configuration  \n  */\n#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */\n#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */\n\n/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\n#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              \n#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */\n#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              \n#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */\n#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              \n#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */\n#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             \n#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */\n\n/**\n  * @brief   EXTI12 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */\n#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */\n\n/**\n  * @brief   EXTI13 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */\n#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */\n\n/**\n  * @brief   EXTI14 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */\n#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */\n\n/**\n  * @brief   EXTI15 configuration  \n  */\n#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */\n#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */\n\n/******************  Bit definition for SYSCFG_CMPCR register  ****************/\n#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              \n#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\n#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */\n#define SYSCFG_CMPCR_READY_Pos               (8U)                              \n#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */\n#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                    TIM                                     */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  ********************/\n#define TIM_CR1_CEN_Pos           (0U)                                         \n#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */\n#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */\n#define TIM_CR1_UDIS_Pos          (1U)                                         \n#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */\n#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */\n#define TIM_CR1_URS_Pos           (2U)                                         \n#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */\n#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */\n#define TIM_CR1_OPM_Pos           (3U)                                         \n#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */\n#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */\n#define TIM_CR1_DIR_Pos           (4U)                                         \n#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */\n#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */\n\n#define TIM_CR1_CMS_Pos           (5U)                                         \n#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */\n#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR1_ARPE_Pos          (7U)                                         \n#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */\n#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */\n\n#define TIM_CR1_CKD_Pos           (8U)                                         \n#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */\n#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */\n#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */\n\n/*******************  Bit definition for TIM_CR2 register  ********************/\n#define TIM_CR2_CCPC_Pos          (0U)                                         \n#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */\n#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */\n#define TIM_CR2_CCUS_Pos          (2U)                                         \n#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */\n#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos          (3U)                                         \n#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */\n#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */\n\n#define TIM_CR2_MMS_Pos           (4U)                                         \n#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */\n#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */\n#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */\n#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */\n\n#define TIM_CR2_TI1S_Pos          (7U)                                         \n#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */\n#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos          (8U)                                         \n#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */\n#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */\n#define TIM_CR2_OIS1N_Pos         (9U)                                         \n#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */\n#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos          (10U)                                        \n#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */\n#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */\n#define TIM_CR2_OIS2N_Pos         (11U)                                        \n#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */\n#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos          (12U)                                        \n#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */\n#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */\n#define TIM_CR2_OIS3N_Pos         (13U)                                        \n#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */\n#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos          (14U)                                        \n#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */\n#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */\n\n/*******************  Bit definition for TIM_SMCR register  *******************/\n#define TIM_SMCR_SMS_Pos          (0U)                                         \n#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */\n#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */\n#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */\n#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */\n#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */\n\n#define TIM_SMCR_TS_Pos           (4U)                                         \n#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */\n#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */\n#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */\n#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */\n#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */\n\n#define TIM_SMCR_MSM_Pos          (7U)                                         \n#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */\n#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */\n\n#define TIM_SMCR_ETF_Pos          (8U)                                         \n#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */\n#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */\n#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */\n#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */\n#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */\n\n#define TIM_SMCR_ETPS_Pos         (12U)                                        \n#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */\n#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */\n#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */\n\n#define TIM_SMCR_ECE_Pos          (14U)                                        \n#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */\n#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */\n#define TIM_SMCR_ETP_Pos          (15U)                                        \n#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */\n#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  *******************/\n#define TIM_DIER_UIE_Pos          (0U)                                         \n#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */\n#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos        (1U)                                         \n#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */\n#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */\n#define TIM_DIER_CC2IE_Pos        (2U)                                         \n#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */\n#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */\n#define TIM_DIER_CC3IE_Pos        (3U)                                         \n#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */\n#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */\n#define TIM_DIER_CC4IE_Pos        (4U)                                         \n#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */\n#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */\n#define TIM_DIER_COMIE_Pos        (5U)                                         \n#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */\n#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */\n#define TIM_DIER_TIE_Pos          (6U)                                         \n#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */\n#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */\n#define TIM_DIER_BIE_Pos          (7U)                                         \n#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */\n#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */\n#define TIM_DIER_UDE_Pos          (8U)                                         \n#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */\n#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */\n#define TIM_DIER_CC1DE_Pos        (9U)                                         \n#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */\n#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos        (10U)                                        \n#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */\n#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos        (11U)                                        \n#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */\n#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos        (12U)                                        \n#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */\n#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos        (13U)                                        \n#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */\n#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */\n#define TIM_DIER_TDE_Pos          (14U)                                        \n#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */\n#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */\n\n/********************  Bit definition for TIM_SR register  ********************/\n#define TIM_SR_UIF_Pos            (0U)                                         \n#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */\n#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */\n#define TIM_SR_CC1IF_Pos          (1U)                                         \n#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */\n#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */\n#define TIM_SR_CC2IF_Pos          (2U)                                         \n#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */\n#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */\n#define TIM_SR_CC3IF_Pos          (3U)                                         \n#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */\n#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */\n#define TIM_SR_CC4IF_Pos          (4U)                                         \n#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */\n#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */\n#define TIM_SR_COMIF_Pos          (5U)                                         \n#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */\n#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */\n#define TIM_SR_TIF_Pos            (6U)                                         \n#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */\n#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */\n#define TIM_SR_BIF_Pos            (7U)                                         \n#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */\n#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */\n#define TIM_SR_CC1OF_Pos          (9U)                                         \n#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */\n#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos          (10U)                                        \n#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */\n#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos          (11U)                                        \n#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */\n#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos          (12U)                                        \n#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */\n#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  ********************/\n#define TIM_EGR_UG_Pos            (0U)                                         \n#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */\n#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */\n#define TIM_EGR_CC1G_Pos          (1U)                                         \n#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */\n#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */\n#define TIM_EGR_CC2G_Pos          (2U)                                         \n#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */\n#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */\n#define TIM_EGR_CC3G_Pos          (3U)                                         \n#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */\n#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */\n#define TIM_EGR_CC4G_Pos          (4U)                                         \n#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */\n#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */\n#define TIM_EGR_COMG_Pos          (5U)                                         \n#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */\n#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos            (6U)                                         \n#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */\n#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */\n#define TIM_EGR_BG_Pos            (7U)                                         \n#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */\n#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */\n\n/******************  Bit definition for TIM_CCMR1 register  *******************/\n#define TIM_CCMR1_CC1S_Pos        (0U)                                         \n#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR1_OC1FE_Pos       (2U)                                         \n#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */\n#define TIM_CCMR1_OC1PE_Pos       (3U)                                         \n#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */\n\n#define TIM_CCMR1_OC1M_Pos        (4U)                                         \n#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\n#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR1_OC1CE_Pos       (7U)                                         \n#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */\n\n#define TIM_CCMR1_CC2S_Pos        (8U)                                         \n#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR1_OC2FE_Pos       (10U)                                        \n#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */\n#define TIM_CCMR1_OC2PE_Pos       (11U)                                        \n#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */\n\n#define TIM_CCMR1_OC2M_Pos        (12U)                                        \n#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\n#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR1_OC2CE_Pos       (15U)                                        \n#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         \n#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR1_IC1F_Pos        (4U)                                         \n#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\n#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        \n#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\n#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR1_IC2F_Pos        (12U)                                        \n#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\n#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */\n\n/******************  Bit definition for TIM_CCMR2 register  *******************/\n#define TIM_CCMR2_CC3S_Pos        (0U)                                         \n#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\n#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */\n#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */\n\n#define TIM_CCMR2_OC3FE_Pos       (2U)                                         \n#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */\n#define TIM_CCMR2_OC3PE_Pos       (3U)                                         \n#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */\n\n#define TIM_CCMR2_OC3M_Pos        (4U)                                         \n#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */\n\n#define TIM_CCMR2_OC3CE_Pos       (7U)                                         \n#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos        (8U)                                         \n#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */\n#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */\n\n#define TIM_CCMR2_OC4FE_Pos       (10U)                                        \n#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */\n#define TIM_CCMR2_OC4PE_Pos       (11U)                                        \n#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos        (12U)                                        \n#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */\n\n#define TIM_CCMR2_OC4CE_Pos       (15U)                                        \n#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */\n\n/*----------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         \n#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */\n#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */\n\n#define TIM_CCMR2_IC3F_Pos        (4U)                                         \n#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */\n#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */\n#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */\n#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */\n\n#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        \n#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */\n#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */\n\n#define TIM_CCMR2_IC4F_Pos        (12U)                                        \n#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */\n#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */\n#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */\n#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */\n\n/*******************  Bit definition for TIM_CCER register  *******************/\n#define TIM_CCER_CC1E_Pos         (0U)                                         \n#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */\n#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */\n#define TIM_CCER_CC1P_Pos         (1U)                                         \n#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */\n#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */\n#define TIM_CCER_CC1NE_Pos        (2U)                                         \n#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */\n#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */\n#define TIM_CCER_CC1NP_Pos        (3U)                                         \n#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */\n#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos         (4U)                                         \n#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */\n#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */\n#define TIM_CCER_CC2P_Pos         (5U)                                         \n#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */\n#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */\n#define TIM_CCER_CC2NE_Pos        (6U)                                         \n#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */\n#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */\n#define TIM_CCER_CC2NP_Pos        (7U)                                         \n#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */\n#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos         (8U)                                         \n#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */\n#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */\n#define TIM_CCER_CC3P_Pos         (9U)                                         \n#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */\n#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */\n#define TIM_CCER_CC3NE_Pos        (10U)                                        \n#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */\n#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */\n#define TIM_CCER_CC3NP_Pos        (11U)                                        \n#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */\n#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos         (12U)                                        \n#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */\n#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */\n#define TIM_CCER_CC4P_Pos         (13U)                                        \n#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */\n#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */\n#define TIM_CCER_CC4NP_Pos        (15U)                                        \n#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */\n#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  ********************/\n#define TIM_CNT_CNT_Pos           (0U)                                             \n#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */\n\n/*******************  Bit definition for TIM_PSC register  ********************/\n#define TIM_PSC_PSC_Pos           (0U)                                         \n#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */\n#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */\n\n/*******************  Bit definition for TIM_ARR register  ********************/\n#define TIM_ARR_ARR_Pos           (0U)                                         \n#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  ********************/\n#define TIM_RCR_REP_Pos           (0U)                                         \n#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */\n#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  *******************/\n#define TIM_CCR1_CCR1_Pos         (0U)                                         \n#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */\n\n/*******************  Bit definition for TIM_CCR2 register  *******************/\n#define TIM_CCR2_CCR2_Pos         (0U)                                         \n#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */\n\n/*******************  Bit definition for TIM_CCR3 register  *******************/\n#define TIM_CCR3_CCR3_Pos         (0U)                                         \n#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */\n\n/*******************  Bit definition for TIM_CCR4 register  *******************/\n#define TIM_CCR4_CCR4_Pos         (0U)                                         \n#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */\n\n/*******************  Bit definition for TIM_BDTR register  *******************/\n#define TIM_BDTR_DTG_Pos          (0U)                                         \n#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */\n#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */\n#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */\n#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */\n#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */\n#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */\n#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */\n#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */\n#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */\n\n#define TIM_BDTR_LOCK_Pos         (8U)                                         \n#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */\n#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */\n#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */\n\n#define TIM_BDTR_OSSI_Pos         (10U)                                        \n#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */\n#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos         (11U)                                        \n#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */\n#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */\n#define TIM_BDTR_BKE_Pos          (12U)                                        \n#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */\n#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */\n#define TIM_BDTR_BKP_Pos          (13U)                                        \n#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */\n#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */\n#define TIM_BDTR_AOE_Pos          (14U)                                        \n#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */\n#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */\n#define TIM_BDTR_MOE_Pos          (15U)                                        \n#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */\n#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */\n\n/*******************  Bit definition for TIM_DCR register  ********************/\n#define TIM_DCR_DBA_Pos           (0U)                                         \n#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */\n#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */\n#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */\n#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */\n#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */\n#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */\n\n#define TIM_DCR_DBL_Pos           (8U)                                         \n#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */\n#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */\n#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */\n#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */\n#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */\n#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */\n\n/*******************  Bit definition for TIM_DMAR register  *******************/\n#define TIM_DMAR_DMAB_Pos         (0U)                                         \n#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */\n\n/*******************  Bit definition for TIM_OR register  *********************/\n#define TIM_OR_TI1_RMP_Pos        (0U)                                          \n#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */\n#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\n#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */\n#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */\n\n#define TIM_OR_TI4_RMP_Pos        (6U)                                         \n#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */\n#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\n#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */\n#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */\n#define TIM_OR_ITR1_RMP_Pos       (10U)                                        \n#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */\n#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\n#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */\n#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos               (0U)                                     \n#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */\n#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */\n#define USART_SR_FE_Pos               (1U)                                     \n#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */\n#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */\n#define USART_SR_NE_Pos               (2U)                                     \n#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */\n#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */\n#define USART_SR_ORE_Pos              (3U)                                     \n#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */\n#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */\n#define USART_SR_IDLE_Pos             (4U)                                     \n#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */\n#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */\n#define USART_SR_RXNE_Pos             (5U)                                     \n#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */\n#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */\n#define USART_SR_TC_Pos               (6U)                                     \n#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */\n#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */\n#define USART_SR_TXE_Pos              (7U)                                     \n#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */\n#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */\n#define USART_SR_LBD_Pos              (8U)                                     \n#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */\n#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */\n#define USART_SR_CTS_Pos              (9U)                                     \n#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */\n#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos               (0U)                                     \n#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */\n#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos    (0U)                                     \n#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     \n#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos             (0U)                                     \n#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */\n#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */\n#define USART_CR1_RWU_Pos             (1U)                                     \n#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */\n#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */\n#define USART_CR1_RE_Pos              (2U)                                     \n#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */\n#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */\n#define USART_CR1_TE_Pos              (3U)                                     \n#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */\n#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */\n#define USART_CR1_IDLEIE_Pos          (4U)                                     \n#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */\n#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */\n#define USART_CR1_RXNEIE_Pos          (5U)                                     \n#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */\n#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */\n#define USART_CR1_TCIE_Pos            (6U)                                     \n#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */\n#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos           (7U)                                     \n#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */\n#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */\n#define USART_CR1_PEIE_Pos            (8U)                                     \n#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */\n#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */\n#define USART_CR1_PS_Pos              (9U)                                     \n#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */\n#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */\n#define USART_CR1_PCE_Pos             (10U)                                    \n#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */\n#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */\n#define USART_CR1_WAKE_Pos            (11U)                                    \n#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */\n#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */\n#define USART_CR1_M_Pos               (12U)                                    \n#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */\n#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */\n#define USART_CR1_UE_Pos              (13U)                                    \n#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */\n#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */\n#define USART_CR1_OVER8_Pos           (15U)                                    \n#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */\n#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos             (0U)                                     \n#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */\n#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */\n#define USART_CR2_LBDL_Pos            (5U)                                     \n#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */\n#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */\n#define USART_CR2_LBDIE_Pos           (6U)                                     \n#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */\n#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos            (8U)                                     \n#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */\n#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */\n#define USART_CR2_CPHA_Pos            (9U)                                     \n#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */\n#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */\n#define USART_CR2_CPOL_Pos            (10U)                                    \n#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */\n#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */\n#define USART_CR2_CLKEN_Pos           (11U)                                    \n#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */\n#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */\n\n#define USART_CR2_STOP_Pos            (12U)                                    \n#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */\n#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */\n#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */\n\n#define USART_CR2_LINEN_Pos           (14U)                                    \n#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */\n#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos             (0U)                                     \n#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */\n#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */\n#define USART_CR3_IREN_Pos            (1U)                                     \n#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */\n#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */\n#define USART_CR3_IRLP_Pos            (2U)                                     \n#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */\n#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */\n#define USART_CR3_HDSEL_Pos           (3U)                                     \n#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */\n#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */\n#define USART_CR3_NACK_Pos            (4U)                                     \n#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */\n#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */\n#define USART_CR3_SCEN_Pos            (5U)                                     \n#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */\n#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */\n#define USART_CR3_DMAR_Pos            (6U)                                     \n#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */\n#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */\n#define USART_CR3_DMAT_Pos            (7U)                                     \n#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */\n#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */\n#define USART_CR3_RTSE_Pos            (8U)                                     \n#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */\n#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */\n#define USART_CR3_CTSE_Pos            (9U)                                     \n#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */\n#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */\n#define USART_CR3_CTSIE_Pos           (10U)                                    \n#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */\n#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */\n#define USART_CR3_ONEBIT_Pos          (11U)                                    \n#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */\n#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos            (0U)                                     \n#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */\n#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */\n#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */\n#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */\n#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */\n#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */\n#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */\n#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */\n#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */\n\n#define USART_GTPR_GT_Pos             (8U)                                     \n#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */\n#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Window WATCHDOG                                 */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos           (0U)                                           \n#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */\n#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */\n#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */\n#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */\n#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */\n#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */\n#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */\n#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */\n/* Legacy defines */\n#define  WWDG_CR_T0                          WWDG_CR_T_0\n#define  WWDG_CR_T1                          WWDG_CR_T_1\n#define  WWDG_CR_T2                          WWDG_CR_T_2\n#define  WWDG_CR_T3                          WWDG_CR_T_3\n#define  WWDG_CR_T4                          WWDG_CR_T_4\n#define  WWDG_CR_T5                          WWDG_CR_T_5\n#define  WWDG_CR_T6                          WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos        (7U)                                           \n#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */\n#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos          (0U)                                           \n#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */\n#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */\n#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */\n#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */\n#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */\n#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */\n#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */\n#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */\n/* Legacy defines */\n#define  WWDG_CFR_W0                         WWDG_CFR_W_0\n#define  WWDG_CFR_W1                         WWDG_CFR_W_1\n#define  WWDG_CFR_W2                         WWDG_CFR_W_2\n#define  WWDG_CFR_W3                         WWDG_CFR_W_3\n#define  WWDG_CFR_W4                         WWDG_CFR_W_4\n#define  WWDG_CFR_W5                         WWDG_CFR_W_5\n#define  WWDG_CFR_W6                         WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos      (7U)                                           \n#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */\n#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos        (9U)                                           \n#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */\n#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos        (0U)                                           \n#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */\n#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                                DBG                                         */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for DBGMCU_IDCODE register  *************/\n#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      \n#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  \n#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     \n#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  \n\n/********************  Bit definition for DBGMCU_CR register  *****************/\n#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      \n#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   \n#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      \n#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    \n#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      \n#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk \n#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      \n#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  \n\n#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      \n#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  \n#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\n#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\n#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\n#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\n#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\n#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\n#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      \n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     \n#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     \n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     \n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\n#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\n#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     \n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\n#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk \n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     \n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk \n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     \n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */\n#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk \n/* Old IWDGSTOP bit definition, maintained for legacy purpose */\n#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\n\n/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      \n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\n#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      \n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\n#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\n#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\n#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk \n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     \n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\n#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk \n\n/******************************************************************************/\n/*                                                                            */\n/*                                       USB_OTG                              */\n/*                                                                            */\n/******************************************************************************/\n/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/\n#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          \n#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */\n#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          \n#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\n#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */\n#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          \n#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          \n#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */\n#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         \n#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */\n#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         \n#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\n#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */\n#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         \n#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\n#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */\n#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         \n#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */\n#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         \n#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */\n#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)                         \n#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */\n\n/********************  Bit definition forUSB_OTG_HCFG register  ********************/\n\n#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          \n#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\n#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */\n#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          \n#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */\n\n/********************  Bit definition for USB_OTG_DCFG register  ********************/\n\n#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          \n#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\n#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */\n#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          \n#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */\n\n#define USB_OTG_DCFG_DAD_Pos                     (4U)                          \n#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\n#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */\n#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\n\n#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         \n#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\n#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */\n#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\n\n#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)                         \n#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */\n#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */\n\n#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)                         \n#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */\n#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */\n\n#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         \n#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\n#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */\n#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\n#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\n\n/********************  Bit definition for USB_OTG_PCGCR register  ********************/\n#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          \n#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */\n#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          \n#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */\n#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          \n#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */\n\n/********************  Bit definition for USB_OTG_GOTGINT register  ********************/\n#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          \n#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\n#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */\n#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          \n#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\n#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */\n#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          \n#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\n#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */\n#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         \n#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\n#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */\n#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         \n#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\n#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */\n#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         \n#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\n#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */\n\n/********************  Bit definition for USB_OTG_DCTL register  ********************/\n#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          \n#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\n#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */\n#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          \n#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */\n#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          \n#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\n#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */\n#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          \n#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\n#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */\n\n#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          \n#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\n#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */\n#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\n#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\n#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\n#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          \n#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\n#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */\n#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          \n#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\n#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */\n#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          \n#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\n#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */\n#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         \n#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\n#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */\n#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         \n#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\n#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */\n\n/********************  Bit definition for USB_OTG_HFIR register  ********************/\n#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          \n#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */\n\n/********************  Bit definition for USB_OTG_HFNUM register  ********************/\n#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          \n#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */\n#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         \n#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */\n\n/********************  Bit definition for USB_OTG_DSTS register  ********************/\n#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          \n#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */\n\n#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          \n#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\n#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */\n#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\n#define USB_OTG_DSTS_EERR_Pos                    (3U)                          \n#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\n#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */\n#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          \n#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\n#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */\n\n/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/\n#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          \n#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\n#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */\n#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          \n#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\n#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */\n#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\n#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\n#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\n#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\n#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\n#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          \n#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */\n#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          \n#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\n#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */\n#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          \n#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\n#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */\n\n/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/\n\n#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          \n#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\n#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */\n#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\n#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\n#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\n#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          \n#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\n#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\n#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          \n#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\n#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */\n#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          \n#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\n#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */\n#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         \n#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\n#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */\n#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\n#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\n#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\n#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\n#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         \n#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\n#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */\n#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         \n#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\n#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */\n#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         \n#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\n#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */\n#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         \n#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\n#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         \n#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         \n#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\n#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */\n#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         \n#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\n#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */\n#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         \n#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\n#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */\n#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         \n#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\n#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */\n#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         \n#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\n#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */\n#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         \n#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\n#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */\n#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         \n#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\n#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */\n#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         \n#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */\n\n/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/\n#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          \n#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\n#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */\n#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          \n#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\n#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */\n#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          \n#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\n#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */\n#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          \n#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\n#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */\n#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          \n#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\n#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */\n\n\n#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          \n#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\n#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */\n#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\n#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\n#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         \n#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\n#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */\n#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         \n#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\n#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */\n\n/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/\n#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          \n#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          \n#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          \n#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          \n#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          \n#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          \n#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          \n#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          \n#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/\n#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          \n#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */\n#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         \n#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */\n#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         \n#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */\n#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\n#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\n\n/********************  Bit definition for USB_OTG_HAINT register  ********************/\n#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          \n#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */\n\n/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/\n#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          \n#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */\n#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          \n#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */\n#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)\n#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */\n#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          \n#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */\n#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          \n#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */\n#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          \n#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */\n#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          \n#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */\n#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          \n#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */\n#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          \n#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */\n#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)\n#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */\n#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)\n#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */\n#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)\n#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */\n/********************  Bit definition for USB_OTG_GINTSTS register  ********************/\n#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          \n#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\n#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */\n#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          \n#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */\n#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          \n#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */\n#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          \n#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */\n#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          \n#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */\n#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          \n#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */\n#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          \n#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */\n#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          \n#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */\n#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         \n#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */\n#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         \n#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */\n#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         \n#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */\n#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         \n#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */\n#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         \n#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */\n#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         \n#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */\n#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         \n#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */\n#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         \n#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */\n#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         \n#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         \n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */\n#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         \n#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */\n#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         \n#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */\n#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         \n#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */\n#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         \n#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */\n#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         \n#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */\n#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         \n#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */\n#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         \n#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */\n#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         \n#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */\n\n/********************  Bit definition for USB_OTG_GINTMSK register  ********************/\n#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          \n#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\n#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */\n#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          \n#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\n#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */\n#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          \n#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\n#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */\n#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          \n#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\n#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */\n#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          \n#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\n#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */\n#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          \n#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\n#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */\n#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          \n#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\n#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */\n#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         \n#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\n#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */\n#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         \n#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\n#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */\n#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         \n#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\n#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */\n#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         \n#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\n#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */\n#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         \n#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\n#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */\n#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         \n#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\n#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */\n#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         \n#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\n#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */\n#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         \n#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\n#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */\n#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         \n#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\n#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */\n#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         \n#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\n#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         \n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\n#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */\n#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         \n#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\n#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */\n#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         \n#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\n#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */\n#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         \n#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\n#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */\n#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         \n#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\n#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */\n#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         \n#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\n#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */\n#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         \n#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\n#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */\n#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         \n#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\n#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */\n#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         \n#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\n#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */\n\n/********************  Bit definition for USB_OTG_DAINT register  ********************/\n#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          \n#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */\n#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         \n#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */\n\n/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/\n#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          \n#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */\n\n/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/\n#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          \n#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\n#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */\n#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          \n#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\n#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         \n#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\n#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */\n#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         \n#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\n#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/\n#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          \n#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */\n#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         \n#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/\n#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          \n#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/\n#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          \n#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */\n\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_NPTXFSA_Pos                      (0U)                          \n#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */\n#define USB_OTG_NPTXFD_Pos                       (16U)                         \n#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */\n#define USB_OTG_TX0FSA_Pos                       (0U)                          \n#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */\n#define USB_OTG_TX0FD_Pos                        (16U)                         \n#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */\n\n/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/\n#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          \n#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\n#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\n\n/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/\n#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          \n#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\n\n#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         \n#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\n#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\n\n#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         \n#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\n#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/\n#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          \n#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\n#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\n#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          \n#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\n#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */\n\n#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          \n#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\n#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */\n#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\n#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\n#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         \n#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\n#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */\n\n#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         \n#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */\n#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\n#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\n#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         \n#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\n#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */\n\n/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          \n#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\n\n/********************  Bit definition for USB_OTG_DEACHINT register  ********************/\n#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          \n#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */\n#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         \n#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */\n\n/********************  Bit definition for USB_OTG_GCCFG register  ********************/\n#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         \n#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\n#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */\n#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)                         \n#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */\n#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/ \n#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)                         \n#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */\n#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)                         \n#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */\n#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */\n#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)                         \n#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */\n#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */\n#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)                         \n#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */\n#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/ \n\n/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/\n#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          \n#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */\n#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         \n#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\n#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\n\n/********************  Bit definition for USB_OTG_CID register  ********************/\n#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          \n#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */\n\n/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/\n#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          \n#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */\n#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          \n#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */\n#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          \n#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          \n#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          \n#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */\n#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          \n#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */\n#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          \n#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */\n#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         \n#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */\n\n/********************  Bit definition for USB_OTG_HPRT register  ********************/\n#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          \n#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\n#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */\n#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          \n#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\n#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */\n#define USB_OTG_HPRT_PENA_Pos                    (2U)                          \n#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\n#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */\n#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          \n#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\n#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */\n#define USB_OTG_HPRT_POCA_Pos                    (4U)                          \n#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\n#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */\n#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          \n#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\n#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */\n#define USB_OTG_HPRT_PRES_Pos                    (6U)                          \n#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\n#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */\n#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          \n#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\n#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */\n#define USB_OTG_HPRT_PRST_Pos                    (8U)                          \n#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\n#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */\n\n#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         \n#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\n#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */\n#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\n#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         \n#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */\n\n#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         \n#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\n#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */\n#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\n#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\n#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\n#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\n\n#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         \n#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\n#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */\n#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\n#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\n\n/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/\n#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          \n#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */\n#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          \n#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */\n#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          \n#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          \n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          \n#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          \n#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */\n#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          \n#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */\n#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          \n#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\n#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         \n#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\n#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */\n#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         \n#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */\n#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         \n#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */\n\n/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/\n#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          \n#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */\n#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         \n#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */\n\n/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/\n#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          \n#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */\n#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         \n#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */\n#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         \n#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\n#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */\n#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         \n#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */\n\n#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         \n#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */\n#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         \n#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */\n\n#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         \n#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\n#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */\n#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\n#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\n#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\n#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\n#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         \n#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */\n#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         \n#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */\n#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         \n#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */\n#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         \n#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */\n#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         \n#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */\n\n/********************  Bit definition for USB_OTG_HCCHAR register  ********************/\n#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          \n#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */\n\n#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         \n#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\n#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */\n#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\n#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         \n#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */\n#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         \n#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\n#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */\n\n#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         \n#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */\n#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\n\n#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         \n#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\n#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */\n#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\n#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\n\n#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         \n#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\n#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */\n#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\n#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\n#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\n#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\n#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\n#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\n#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\n#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         \n#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */\n#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         \n#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */\n#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         \n#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */\n\n/********************  Bit definition for USB_OTG_HCSPLT register  ********************/\n\n#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          \n#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\n#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */\n#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\n\n#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          \n#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\n#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */\n#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\n#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\n#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\n\n#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         \n#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\n#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */\n#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\n#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\n#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         \n#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\n#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */\n#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         \n#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */\n\n/********************  Bit definition for USB_OTG_HCINT register  ********************/\n#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          \n#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */\n#define USB_OTG_HCINT_CHH_Pos                    (1U)                          \n#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */\n#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          \n#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */\n#define USB_OTG_HCINT_STALL_Pos                  (3U)                          \n#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */\n#define USB_OTG_HCINT_NAK_Pos                    (4U)                          \n#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */\n#define USB_OTG_HCINT_ACK_Pos                    (5U)                          \n#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */\n#define USB_OTG_HCINT_NYET_Pos                   (6U)                          \n#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */\n#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          \n#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */\n#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          \n#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */\n#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          \n#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */\n#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         \n#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */\n\n/********************  Bit definition for USB_OTG_DIEPINT register  ********************/\n#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          \n#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          \n#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */\n#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          \n#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\n#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */\n#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          \n#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\n#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */\n#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)\n#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */\n#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */\n#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          \n#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\n#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */\n#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          \n#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\n#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */\n#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          \n#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\n#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\n#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          \n#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\n#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */\n#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         \n#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\n#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\n#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         \n#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\n#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */\n#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         \n#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */\n\n/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/\n#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          \n#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\n#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */\n#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          \n#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\n#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */\n#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          \n#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */\n#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          \n#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\n#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */\n#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          \n#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\n#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */\n#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          \n#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\n#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */\n#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          \n#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\n#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */\n#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          \n#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\n#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */\n#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          \n#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\n#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */\n#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          \n#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\n#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */\n#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         \n#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\n#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */\n\n/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/\n\n#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          \n#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         \n#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         \n#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */\n/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/\n#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          \n#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */\n#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         \n#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */\n#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         \n#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\n#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */\n#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         \n#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\n#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */\n#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\n#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/\n#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          \n#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_HCDMA register  ********************/\n#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          \n#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\n#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */\n\n/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/\n#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          \n#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\n\n/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/\n#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          \n#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\n#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */\n#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         \n#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\n#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */\n\n/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/\n\n#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          \n#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\n#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */\n#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         \n#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */\n#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         \n#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\n#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         \n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\n#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\n#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         \n#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */\n#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         \n#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\n#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */\n#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\n#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\n#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         \n#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\n#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */\n#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         \n#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\n#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */\n#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         \n#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\n#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */\n#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         \n#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\n#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */\n#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         \n#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\n#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */\n#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         \n#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\n#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */\n\n/********************  Bit definition for USB_OTG_DOEPINT register  ********************/\n#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          \n#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\n#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */\n#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          \n#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\n#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */\n#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)\n#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\n#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */\n#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          \n#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\n#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */\n#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          \n#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\n#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */\n#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          \n#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\n#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */\n#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          \n#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\n#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */\n#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)\n#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\n#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */\n#define USB_OTG_DOEPINT_NAK_Pos                  (13U)\n#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\n#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */\n#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         \n#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\n#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */\n#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)\n#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\n#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */\n/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/\n\n#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          \n#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\n#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */\n#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         \n#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\n#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */\n\n#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         \n#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */\n#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\n#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\n\n/********************  Bit definition for PCGCCTL register  ********************/\n#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          \n#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\n#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */\n#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          \n#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\n#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */\n#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          \n#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\n#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */\n\n/* Legacy define */\n/********************  Bit definition for OTG register  ********************/\n#define USB_OTG_CHNUM_Pos                        (0U)                          \n#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */\n#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */\n#define USB_OTG_BCNT_Pos                         (4U)                          \n#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */\n#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */\n\n#define USB_OTG_DPID_Pos                         (15U)                         \n#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */\n#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */\n#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */\n#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */\n\n#define USB_OTG_PKTSTS_Pos                       (17U)                         \n#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */\n#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */\n#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */\n#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */\n#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */\n#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */\n\n#define USB_OTG_EPNUM_Pos                        (0U)                          \n#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */\n#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */\n#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */\n#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */\n#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */\n#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */\n\n#define USB_OTG_FRMNUM_Pos                       (21U)                         \n#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */\n#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */\n#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */\n#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */\n#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */\n#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n\n/******************************* ADC Instances ********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2) || \\\n                                       ((INSTANCE) == ADC3))\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\n\n/******************************* CAN Instances ********************************/\n#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \\\n                                       ((INSTANCE) == CAN2))\n/******************************* CRC Instances ********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/******************************* DAC Instances ********************************/\n#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)\n\n\n/******************************** DMA Instances *******************************/\n#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \\\n                                              ((INSTANCE) == DMA1_Stream1) || \\\n                                              ((INSTANCE) == DMA1_Stream2) || \\\n                                              ((INSTANCE) == DMA1_Stream3) || \\\n                                              ((INSTANCE) == DMA1_Stream4) || \\\n                                              ((INSTANCE) == DMA1_Stream5) || \\\n                                              ((INSTANCE) == DMA1_Stream6) || \\\n                                              ((INSTANCE) == DMA1_Stream7) || \\\n                                              ((INSTANCE) == DMA2_Stream0) || \\\n                                              ((INSTANCE) == DMA2_Stream1) || \\\n                                              ((INSTANCE) == DMA2_Stream2) || \\\n                                              ((INSTANCE) == DMA2_Stream3) || \\\n                                              ((INSTANCE) == DMA2_Stream4) || \\\n                                              ((INSTANCE) == DMA2_Stream5) || \\\n                                              ((INSTANCE) == DMA2_Stream6) || \\\n                                              ((INSTANCE) == DMA2_Stream7))\n\n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE) || \\\n                                        ((INSTANCE) == GPIOF) || \\\n                                        ((INSTANCE) == GPIOG) || \\\n                                        ((INSTANCE) == GPIOH) || \\\n                                        ((INSTANCE) == GPIOI))\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2) || \\\n                                       ((INSTANCE) == I2C3))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/******************************** I2S Instances *******************************/\n\n#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n/*************************** I2S Extended Instances ***************************/\n#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \\\n                                           ((INSTANCE) == I2S3ext))\n/* Legacy Defines */\n#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE\n\n/******************************* RNG Instances ********************************/\n#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2) || \\\n                                       ((INSTANCE) == SPI3))\n\n\n/****************** TIM Instances : All supported instances *******************/\n#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                    ((INSTANCE) == TIM2) || \\\n                                    ((INSTANCE) == TIM3) || \\\n                                    ((INSTANCE) == TIM4) || \\\n                                    ((INSTANCE) == TIM5) || \\\n                                    ((INSTANCE) == TIM6) || \\\n                                    ((INSTANCE) == TIM7) || \\\n                                    ((INSTANCE) == TIM8) || \\\n                                    ((INSTANCE) == TIM9) || \\\n                                    ((INSTANCE) == TIM10)|| \\\n                                    ((INSTANCE) == TIM11)|| \\\n                                    ((INSTANCE) == TIM12)|| \\\n                                    ((INSTANCE) == TIM13)|| \\\n                                    ((INSTANCE) == TIM14))\n\n/************* TIM Instances : at least 1 capture/compare channel *************/\n#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \\\n                                         ((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM3)  || \\\n                                         ((INSTANCE) == TIM4)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM8)  || \\\n                                         ((INSTANCE) == TIM9)  || \\\n                                         ((INSTANCE) == TIM10) || \\\n                                         ((INSTANCE) == TIM11) || \\\n                                         ((INSTANCE) == TIM12) || \\\n                                         ((INSTANCE) == TIM13) || \\\n                                         ((INSTANCE) == TIM14))\n\n/************ TIM Instances : at least 2 capture/compare channels *************/\n#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8) || \\\n                                       ((INSTANCE) == TIM9) || \\\n                                       ((INSTANCE) == TIM12)) \n\n/************ TIM Instances : at least 3 capture/compare channels *************/\n#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/************ TIM Instances : at least 4 capture/compare channels *************/\n#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : Advanced-control timers *****************/\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                           ((INSTANCE) == TIM8))\n\n/******************* TIM Instances : Timer input XOR function *****************/\n#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : DMA requests generation (UDE) *************/\n#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                       ((INSTANCE) == TIM2) || \\\n                                       ((INSTANCE) == TIM3) || \\\n                                       ((INSTANCE) == TIM4) || \\\n                                       ((INSTANCE) == TIM5) || \\\n                                       ((INSTANCE) == TIM6) || \\\n                                       ((INSTANCE) == TIM7) || \\\n                                       ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (CCxDE) *****************/\n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/************ TIM Instances : DMA requests generation (COMDE) *****************/\n#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM2) || \\\n                                          ((INSTANCE) == TIM3) || \\\n                                          ((INSTANCE) == TIM4) || \\\n                                          ((INSTANCE) == TIM5) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** TIM Instances : DMA burst feature ***********************/\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                             ((INSTANCE) == TIM2) || \\\n                                             ((INSTANCE) == TIM3) || \\\n                                             ((INSTANCE) == TIM4) || \\\n                                             ((INSTANCE) == TIM5) || \\\n                                             ((INSTANCE) == TIM8))\n\n/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\n#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                          ((INSTANCE) == TIM2)  || \\\n                                          ((INSTANCE) == TIM3)  || \\\n                                          ((INSTANCE) == TIM4)  || \\\n                                          ((INSTANCE) == TIM5)  || \\\n                                          ((INSTANCE) == TIM6)  || \\\n                                          ((INSTANCE) == TIM7)  || \\\n                                          ((INSTANCE) == TIM8))\n\n/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                         ((INSTANCE) == TIM2) || \\\n                                         ((INSTANCE) == TIM3) || \\\n                                         ((INSTANCE) == TIM4) || \\\n                                         ((INSTANCE) == TIM5) || \\\n                                         ((INSTANCE) == TIM8) || \\\n                                         ((INSTANCE) == TIM9) || \\\n                                         ((INSTANCE) == TIM12))\n/********************** TIM Instances : 32 bit Counter ************************/\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \\\n                                              ((INSTANCE) == TIM5))\n\n/***************** TIM Instances : external trigger input availabe ************/\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                        ((INSTANCE) == TIM2) || \\\n                                        ((INSTANCE) == TIM3) || \\\n                                        ((INSTANCE) == TIM4) || \\\n                                        ((INSTANCE) == TIM5) || \\\n                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : remapping capability **********************/\n#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \\\n                                         ((INSTANCE) == TIM5)  || \\\n                                         ((INSTANCE) == TIM11))\n\n/******************* TIM Instances : output(s) available **********************/\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n    ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM5) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM8) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM9) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM10) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM11) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM12) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM13) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM14) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1))))\n\n/************ TIM Instances : complementary output(s) available ***************/\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))            \\\n    ||                                          \\\n    (((INSTANCE) == TIM8) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3))))\n\n/****************** TIM Instances : supporting counting mode selection ********/\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting clock division *****************/\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \\\n                                                  ((INSTANCE) == TIM2) || \\\n                                                  ((INSTANCE) == TIM3) || \\\n                                                  ((INSTANCE) == TIM4) || \\\n                                                  ((INSTANCE) == TIM5) || \\\n                                                  ((INSTANCE) == TIM8) || \\\n                                                  ((INSTANCE) == TIM9) || \\\n                                                  ((INSTANCE) == TIM10)|| \\\n                                                  ((INSTANCE) == TIM11)|| \\\n                                                  ((INSTANCE) == TIM12)|| \\\n                                                  ((INSTANCE) == TIM13)|| \\\n                                                  ((INSTANCE) == TIM14))\n\n/****************** TIM Instances : supporting commutation event generation ***/\n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \\\n                                                     ((INSTANCE) == TIM8))\n\n\n/****************** TIM Instances : supporting OCxREF clear *******************/\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM2) || \\\n                                                       ((INSTANCE) == TIM3) || \\\n                                                       ((INSTANCE) == TIM4) || \\\n                                                       ((INSTANCE) == TIM5) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8))\n\n/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \\\n                                                        ((INSTANCE) == TIM2) || \\\n                                                        ((INSTANCE) == TIM3) || \\\n                                                        ((INSTANCE) == TIM4) || \\\n                                                        ((INSTANCE) == TIM5) || \\\n                                                        ((INSTANCE) == TIM8) || \\\n                                                        ((INSTANCE) == TIM9) || \\\n                                                        ((INSTANCE) == TIM12))\n\n/****************** TIM Instances : supporting repetition counter *************/\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                       ((INSTANCE) == TIM8))\n\n/****************** TIM Instances : supporting encoder interface **************/\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                      ((INSTANCE) == TIM2) || \\\n                                                      ((INSTANCE) == TIM3) || \\\n                                                      ((INSTANCE) == TIM4) || \\\n                                                      ((INSTANCE) == TIM5) || \\\n                                                      ((INSTANCE) == TIM8) || \\\n                                                      ((INSTANCE) == TIM9) || \\\n                                                      ((INSTANCE) == TIM12))\n/****************** TIM Instances : supporting Hall sensor interface **********/\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                                          ((INSTANCE) == TIM2) || \\\n                                                          ((INSTANCE) == TIM3) || \\\n                                                          ((INSTANCE) == TIM4) || \\\n                                                          ((INSTANCE) == TIM5) || \\\n                                                          ((INSTANCE) == TIM8))\n/****************** TIM Instances : supporting the break function *************/\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \\\n                                          ((INSTANCE) == TIM8))\n\n/******************** USART Instances : Synchronous mode **********************/\n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3) || \\\n                                     ((INSTANCE) == USART6))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3) || \\\n                                               ((INSTANCE) == UART4)  || \\\n                                               ((INSTANCE) == UART5)  || \\\n                                               ((INSTANCE) == USART6))\n\n/* Legacy defines */\n#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/****************** UART Instances : Hardware Flow control ********************/\n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3) || \\\n                                           ((INSTANCE) == USART6))\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE\n\n/********************* UART Instances : Smart card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3) || \\\n                                         ((INSTANCE) == USART6))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3) || \\\n                                    ((INSTANCE) == UART4)  || \\\n                                    ((INSTANCE) == UART5)  || \\\n                                    ((INSTANCE) == USART6))\n\n\n/*********************** PCD Instances ****************************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/*********************** HCD Instances ****************************************/\n#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\\n                                       ((INSTANCE) == USB_OTG_HS))\n\n/****************************** SDIO Instances ********************************/\n#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/****************************** WWDG Instances ********************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Exported Constants ************************/\n#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U\n#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */\n#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */\n#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */\n\n/*\n * @brief Specific devices reset values definitions\n */\n#define RCC_PLLCFGR_RST_VALUE              0x24003010U\n#define RCC_PLLI2SCFGR_RST_VALUE           0x20003000U\n\n#define RCC_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/\n#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */\n#define RCC_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */\n#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */\n#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */\n#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */\n\n#define RCC_PLLN_MIN_VALUE                 50U\n#define RCC_PLLN_MAX_VALUE                432U\n\n#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */\n#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */\n#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */\n#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */\n#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */\n\n#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */\n#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */\n#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */\n#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */\n\n#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U\n#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */\n#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */\n#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */\n/******************************************************************************/\n/*  For a painless codes migration between the STM32F4xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */\n/*  product lines within the same STM32F4 Family                              */\n/******************************************************************************/\n/* Aliases for __IRQn */\n#define FMC_IRQn              FSMC_IRQn\n\n/* Aliases for __IRQHandler */\n#define FMC_IRQHandler        FSMC_IRQHandler\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F405xx_H */\n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.\n  *            \n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *           - Configuration section that allows to select:\n  *              - The STM32F4xx device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e. \n  *                code will be based on direct access to peripherals registers \n  *                rather than drivers API), this option is controlled by \n  *                \"#define USE_HAL_DRIVER\"\n  *  \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx\n  * @{\n  */\n    \n#ifndef __STM32F4xx_H\n#define __STM32F4xx_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n   \n/** @addtogroup Library_configuration_section\n  * @{\n  */\n  \n/**\n  * @brief STM32 Family\n  */\n#if !defined  (STM32F4)\n#define STM32F4\n#endif /* STM32F4 */\n\n/* Uncomment the line below according to the target STM32 device used in your\n   application \n  */\n#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \\\n    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \\\n    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \\\n    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \\\n    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \\\n    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)\n  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */\n  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */\n  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */\n  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */\n  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */\n  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */\n  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, \n                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */\n  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, \n                                   STM32F439NI, STM32F439IG and STM32F439II Devices */\n  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */\n  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */\n  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */\n  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */\n  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */\n  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */\n  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, \n                                   and STM32F446ZE Devices */\n  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, \n                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */\n  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG \n                                   and STM32F479NG Devices */\n  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */\n  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */\n  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */\n  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */\n  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,\n                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */\n  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */\n#endif\n   \n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will \n   be based on direct access to peripherals registers \n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS version number V2.6.6\n  */\n#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */\n#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x06U) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */\n#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\\\n                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\\\n                                         |(__STM32F4xx_CMSIS_VERSION))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32F405xx)\n  #include \"stm32f405xx.h\"\n#elif defined(STM32F415xx)\n  #include \"stm32f415xx.h\"\n#elif defined(STM32F407xx)\n  #include \"stm32f407xx.h\"\n#elif defined(STM32F417xx)\n  #include \"stm32f417xx.h\"\n#elif defined(STM32F427xx)\n  #include \"stm32f427xx.h\"\n#elif defined(STM32F437xx)\n  #include \"stm32f437xx.h\"\n#elif defined(STM32F429xx)\n  #include \"stm32f429xx.h\"\n#elif defined(STM32F439xx)\n  #include \"stm32f439xx.h\"\n#elif defined(STM32F401xC)\n  #include \"stm32f401xc.h\"\n#elif defined(STM32F401xE)\n  #include \"stm32f401xe.h\"\n#elif defined(STM32F410Tx)\n  #include \"stm32f410tx.h\"\n#elif defined(STM32F410Cx)\n  #include \"stm32f410cx.h\"\n#elif defined(STM32F410Rx)\n  #include \"stm32f410rx.h\"\n#elif defined(STM32F411xE)\n  #include \"stm32f411xe.h\"\n#elif defined(STM32F446xx)\n  #include \"stm32f446xx.h\"\n#elif defined(STM32F469xx)\n  #include \"stm32f469xx.h\"\n#elif defined(STM32F479xx)\n  #include \"stm32f479xx.h\"\n#elif defined(STM32F412Cx)\n  #include \"stm32f412cx.h\"\n#elif defined(STM32F412Zx)\n  #include \"stm32f412zx.h\"\n#elif defined(STM32F412Rx)\n  #include \"stm32f412rx.h\"\n#elif defined(STM32F412Vx)\n  #include \"stm32f412vx.h\"\n#elif defined(STM32F413xx)\n  #include \"stm32f413xx.h\"\n#elif defined(STM32F423xx)\n  #include \"stm32f423xx.h\"\n#else\n #error \"Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */ \ntypedef enum \n{\n  RESET = 0U, \n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum \n{\n  DISABLE = 0U, \n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  SUCCESS = 0U,\n  ERROR = !SUCCESS\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macro\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) \n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f4xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F4xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n  \n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f4xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       \n  ******************************************************************************  \n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>\n  *\n  * Redistribution and use in source and binary forms, with or without modification,\n  * are permitted provided that the following conditions are met:\n  *   1. Redistributions of source code must retain the above copyright notice,\n  *      this list of conditions and the following disclaimer.\n  *   2. Redistributions in binary form must reproduce the above copyright notice,\n  *      this list of conditions and the following disclaimer in the documentation\n  *      and/or other materials provided with the distribution.\n  *   3. Neither the name of STMicroelectronics nor the names of its contributors\n  *      may be used to endorse or promote products derived from this software\n  *      without specific prior written permission.\n  *\n  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************  \n  */ \n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f4xx_system\n  * @{\n  */  \n  \n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F4XX_H\n#define __SYSTEM_STM32F4XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup STM32F4xx_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F4xx_System_Exported_types\n  * @{\n  */\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetSysClockFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\n\nextern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F4xx_System_Exported_Functions\n  * @{\n  */\n  \nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F4XX_H */\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */  \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_armcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armcc.h\n * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_ARMCC_H\n#define __CMSIS_ARMCC_H\n\n\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)\n  #error \"Please use Arm Compiler Toolchain V4.0.677 or later!\"\n#endif\n\n/* CMSIS compiler control architecture macros */\n#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \\\n     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )\n  #define __ARM_ARCH_6M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))\n  #define __ARM_ARCH_7M__           1\n#endif\n\n#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))\n  #define __ARM_ARCH_7EM__          1\n#endif\n\n  /* __ARM_ARCH_8M_BASE__  not applicable */\n  /* __ARM_ARCH_8M_MAIN__  not applicable */\n\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   static __forceinline\n#endif           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __declspec(noreturn)\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        __packed struct\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         __packed union\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();     */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();    */\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_INLINE uint32_t __get_CONTROL(void)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  return(__regControl);\n}\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_INLINE void __set_CONTROL(uint32_t control)\n{\n  register uint32_t __regControl         __ASM(\"control\");\n  __regControl = control;\n}\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_INLINE uint32_t __get_IPSR(void)\n{\n  register uint32_t __regIPSR          __ASM(\"ipsr\");\n  return(__regIPSR);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_INLINE uint32_t __get_APSR(void)\n{\n  register uint32_t __regAPSR          __ASM(\"apsr\");\n  return(__regAPSR);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_INLINE uint32_t __get_xPSR(void)\n{\n  register uint32_t __regXPSR          __ASM(\"xpsr\");\n  return(__regXPSR);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_INLINE uint32_t __get_PSP(void)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  return(__regProcessStackPointer);\n}\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  register uint32_t __regProcessStackPointer  __ASM(\"psp\");\n  __regProcessStackPointer = topOfProcStack;\n}\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_INLINE uint32_t __get_MSP(void)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  return(__regMainStackPointer);\n}\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  register uint32_t __regMainStackPointer     __ASM(\"msp\");\n  __regMainStackPointer = topOfMainStack;\n}\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_INLINE uint32_t __get_PRIMASK(void)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  return(__regPriMask);\n}\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\n{\n  register uint32_t __regPriMask         __ASM(\"primask\");\n  __regPriMask = (priMask);\n}\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_INLINE uint32_t  __get_BASEPRI(void)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  return(__regBasePri);\n}\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\n{\n  register uint32_t __regBasePri         __ASM(\"basepri\");\n  __regBasePri = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  register uint32_t __regBasePriMax      __ASM(\"basepri_max\");\n  __regBasePriMax = (basePri & 0xFFU);\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_INLINE uint32_t __get_FAULTMASK(void)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  return(__regFaultMask);\n}\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  register uint32_t __regFaultMask       __ASM(\"faultmask\");\n  __regFaultMask = (faultMask & (uint32_t)1U);\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_INLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  return(__regfpscr);\n#else\n   return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n  register uint32_t __regfpscr         __ASM(\"fpscr\");\n  __regfpscr = (fpscr);\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP                             __nop\n\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI                             __wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE                             __wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV                             __sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB() do {\\\n                   __schedule_barrier();\\\n                   __isb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB() do {\\\n                   __schedule_barrier();\\\n                   __dsb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB() do {\\\n                   __schedule_barrier();\\\n                   __dmb(0xF);\\\n                   __schedule_barrier();\\\n                } while (0U)\n\n                  \n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV                             __rev\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rev16_text\"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\n{\n  rev16 r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".revsh_text\"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)\n{\n  revsh r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n#define __ROR                             __ror\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __breakpoint(value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n  #define __RBIT                          __rbit\n#else\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n  return result;\n}\n#endif\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ                             __clz\n\n\n#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))\n#else\n  #define __LDREXB(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint8_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))\n#else\n  #define __LDREXH(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint16_t) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))\n#else\n  #define __LDREXW(ptr)          _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") ((uint32_t ) __ldrex(ptr))  _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXB(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXB(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXH(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXH(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)\n  #define __STREXW(value, ptr)                                                 __strex(value, ptr)\n#else\n  #define __STREXW(value, ptr)   _Pragma(\"push\") _Pragma(\"diag_suppress 3731\") __strex(value, ptr)        _Pragma(\"pop\")\n#endif\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX                           __clrex\n\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT                            __ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT                            __usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n#ifndef __NO_EMBEDDED_ASM\n__attribute__((section(\".rrx_text\"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)\n{\n  rrx r0, r0\n  bx lr\n}\n#endif\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRBT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRHT(value, ptr)               __strt(value, ptr)\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n#define __STRT(value, ptr)                __strt(value, ptr)\n\n#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \\\n           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )\n\n#define __SADD8                           __sadd8\n#define __QADD8                           __qadd8\n#define __SHADD8                          __shadd8\n#define __UADD8                           __uadd8\n#define __UQADD8                          __uqadd8\n#define __UHADD8                          __uhadd8\n#define __SSUB8                           __ssub8\n#define __QSUB8                           __qsub8\n#define __SHSUB8                          __shsub8\n#define __USUB8                           __usub8\n#define __UQSUB8                          __uqsub8\n#define __UHSUB8                          __uhsub8\n#define __SADD16                          __sadd16\n#define __QADD16                          __qadd16\n#define __SHADD16                         __shadd16\n#define __UADD16                          __uadd16\n#define __UQADD16                         __uqadd16\n#define __UHADD16                         __uhadd16\n#define __SSUB16                          __ssub16\n#define __QSUB16                          __qsub16\n#define __SHSUB16                         __shsub16\n#define __USUB16                          __usub16\n#define __UQSUB16                         __uqsub16\n#define __UHSUB16                         __uhsub16\n#define __SASX                            __sasx\n#define __QASX                            __qasx\n#define __SHASX                           __shasx\n#define __UASX                            __uasx\n#define __UQASX                           __uqasx\n#define __UHASX                           __uhasx\n#define __SSAX                            __ssax\n#define __QSAX                            __qsax\n#define __SHSAX                           __shsax\n#define __USAX                            __usax\n#define __UQSAX                           __uqsax\n#define __UHSAX                           __uhsax\n#define __USAD8                           __usad8\n#define __USADA8                          __usada8\n#define __SSAT16                          __ssat16\n#define __USAT16                          __usat16\n#define __UXTB16                          __uxtb16\n#define __UXTAB16                         __uxtab16\n#define __SXTB16                          __sxtb16\n#define __SXTAB16                         __sxtab16\n#define __SMUAD                           __smuad\n#define __SMUADX                          __smuadx\n#define __SMLAD                           __smlad\n#define __SMLADX                          __smladx\n#define __SMLALD                          __smlald\n#define __SMLALDX                         __smlaldx\n#define __SMUSD                           __smusd\n#define __SMUSDX                          __smusdx\n#define __SMLSD                           __smlsd\n#define __SMLSDX                          __smlsdx\n#define __SMLSLD                          __smlsld\n#define __SMLSLDX                         __smlsldx\n#define __SEL                             __sel\n#define __QADD                            __qadd\n#define __QSUB                            __qsub\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \\\n                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))\n\n#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCC_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n#ifndef __ARM_COMPAT_H\n#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF);\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF);\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF);\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.0.4\n * @date     09. April 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr) \n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_iccarm.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_iccarm.h\n * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file\n * @version  V5.0.7\n * @date     19. June 2018\n ******************************************************************************/\n\n//------------------------------------------------------------------------------\n//\n// Copyright (c) 2017-2018 IAR Systems\n//\n// Licensed under the Apache License, Version 2.0 (the \"License\")\n// you may not use this file except in compliance with the License.\n// You may obtain a copy of the License at\n//     http://www.apache.org/licenses/LICENSE-2.0\n//\n// Unless required by applicable law or agreed to in writing, software\n// distributed under the License is distributed on an \"AS IS\" BASIS,\n// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n// See the License for the specific language governing permissions and\n// limitations under the License.\n//\n//------------------------------------------------------------------------------\n\n\n#ifndef __CMSIS_ICCARM_H__\n#define __CMSIS_ICCARM_H__\n\n#ifndef __ICCARM__\n  #error This file should only be compiled by ICCARM\n#endif\n\n#pragma system_include\n\n#define __IAR_FT _Pragma(\"inline=forced\") __intrinsic\n\n#if (__VER__ >= 8000000)\n  #define __ICCARM_V8 1\n#else\n  #define __ICCARM_V8 0\n#endif\n\n#ifndef __ALIGNED\n  #if __ICCARM_V8\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #elif (__VER__ >= 7080000)\n    /* Needs IAR language extensions */\n    #define __ALIGNED(x) __attribute__((aligned(x)))\n  #else\n    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n#endif\n\n\n/* Define compiler macros for CPU architecture, used in CMSIS 5.\n */\n#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__\n/* Macros already defined */\n#else\n  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'\n    #if __ARM_ARCH == 6\n      #define __ARM_ARCH_6M__ 1\n    #elif __ARM_ARCH == 7\n      #if __ARM_FEATURE_DSP\n        #define __ARM_ARCH_7EM__ 1\n      #else\n        #define __ARM_ARCH_7M__ 1\n      #endif\n    #endif /* __ARM_ARCH */\n  #endif /* __ARM_ARCH_PROFILE == 'M' */\n#endif\n\n/* Alternativ core deduction for older ICCARM's */\n#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \\\n    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)\n  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)\n    #define __ARM_ARCH_6M__ 1\n  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)\n    #define __ARM_ARCH_7M__ 1\n  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)\n    #define __ARM_ARCH_7EM__  1\n  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)\n    #define __ARM_ARCH_8M_BASE__ 1\n  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)\n    #define __ARM_ARCH_8M_MAIN__ 1\n  #else\n    #error \"Unknown target.\"\n  #endif\n#endif\n\n\n\n#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1\n  #define __IAR_M0_FAMILY  1\n#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1\n  #define __IAR_M0_FAMILY  1\n#else\n  #define __IAR_M0_FAMILY  0\n#endif\n\n\n#ifndef __ASM\n  #define __ASM __asm\n#endif\n\n#ifndef __INLINE\n  #define __INLINE inline\n#endif\n\n#ifndef   __NO_RETURN\n  #if __ICCARM_V8\n    #define __NO_RETURN __attribute__((__noreturn__))\n  #else\n    #define __NO_RETURN _Pragma(\"object_attribute=__noreturn\")\n  #endif\n#endif\n\n#ifndef   __PACKED\n  #if __ICCARM_V8\n    #define __PACKED __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED __packed\n  #endif\n#endif\n\n#ifndef   __PACKED_STRUCT\n  #if __ICCARM_V8\n    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_STRUCT __packed struct\n  #endif\n#endif\n\n#ifndef   __PACKED_UNION\n  #if __ICCARM_V8\n    #define __PACKED_UNION union __attribute__((packed, aligned(1)))\n  #else\n    /* Needs IAR language extensions */\n    #define __PACKED_UNION __packed union\n  #endif\n#endif\n\n#ifndef   __RESTRICT\n  #define __RESTRICT            __restrict\n#endif\n\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE       static inline\n#endif\n\n#ifndef   __FORCEINLINE\n  #define __FORCEINLINE         _Pragma(\"inline=forced\")\n#endif\n\n#ifndef   __STATIC_FORCEINLINE\n  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE\n#endif\n\n#ifndef __UNALIGNED_UINT16_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint16_t __iar_uint16_read(void const *ptr)\n{\n  return *(__packed uint16_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)\n#endif\n\n\n#ifndef __UNALIGNED_UINT16_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)\n{\n  *(__packed uint16_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32_READ\n#pragma language=save\n#pragma language=extended\n__IAR_FT uint32_t __iar_uint32_read(void const *ptr)\n{\n  return *(__packed uint32_t*)(ptr);\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)\n#endif\n\n#ifndef __UNALIGNED_UINT32_WRITE\n#pragma language=save\n#pragma language=extended\n__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)\n{\n  *(__packed uint32_t*)(ptr) = val;;\n}\n#pragma language=restore\n#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)\n#endif\n\n#ifndef __UNALIGNED_UINT32   /* deprecated */\n#pragma language=save\n#pragma language=extended\n__packed struct  __iar_u32 { uint32_t v; };\n#pragma language=restore\n#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)\n#endif\n\n#ifndef   __USED\n  #if __ICCARM_V8\n    #define __USED __attribute__((used))\n  #else\n    #define __USED _Pragma(\"__root\")\n  #endif\n#endif\n\n#ifndef   __WEAK\n  #if __ICCARM_V8\n    #define __WEAK __attribute__((weak))\n  #else\n    #define __WEAK _Pragma(\"__weak\")\n  #endif\n#endif\n\n\n#ifndef __ICCARM_INTRINSICS_VERSION__\n  #define __ICCARM_INTRINSICS_VERSION__  0\n#endif\n\n#if __ICCARM_INTRINSICS_VERSION__ == 2\n\n  #if defined(__CLZ)\n    #undef __CLZ\n  #endif\n  #if defined(__REVSH)\n    #undef __REVSH\n  #endif\n  #if defined(__RBIT)\n    #undef __RBIT\n  #endif\n  #if defined(__SSAT)\n    #undef __SSAT\n  #endif\n  #if defined(__USAT)\n    #undef __USAT\n  #endif\n\n  #include \"iccarm_builtin.h\"\n\n  #define __disable_fault_irq __iar_builtin_disable_fiq\n  #define __disable_irq       __iar_builtin_disable_interrupt\n  #define __enable_fault_irq  __iar_builtin_enable_fiq\n  #define __enable_irq        __iar_builtin_enable_interrupt\n  #define __arm_rsr           __iar_builtin_rsr\n  #define __arm_wsr           __iar_builtin_wsr\n\n\n  #define __get_APSR()                (__arm_rsr(\"APSR\"))\n  #define __get_BASEPRI()             (__arm_rsr(\"BASEPRI\"))\n  #define __get_CONTROL()             (__arm_rsr(\"CONTROL\"))\n  #define __get_FAULTMASK()           (__arm_rsr(\"FAULTMASK\"))\n\n  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n    #define __get_FPSCR()             (__arm_rsr(\"FPSCR\"))\n    #define __set_FPSCR(VALUE)        (__arm_wsr(\"FPSCR\", (VALUE)))\n  #else\n    #define __get_FPSCR()             ( 0 )\n    #define __set_FPSCR(VALUE)        ((void)VALUE)\n  #endif\n\n  #define __get_IPSR()                (__arm_rsr(\"IPSR\"))\n  #define __get_MSP()                 (__arm_rsr(\"MSP\"))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __get_MSPLIM()            (0U)\n  #else\n    #define __get_MSPLIM()            (__arm_rsr(\"MSPLIM\"))\n  #endif\n  #define __get_PRIMASK()             (__arm_rsr(\"PRIMASK\"))\n  #define __get_PSP()                 (__arm_rsr(\"PSP\"))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __get_PSPLIM()            (0U)\n  #else\n    #define __get_PSPLIM()            (__arm_rsr(\"PSPLIM\"))\n  #endif\n\n  #define __get_xPSR()                (__arm_rsr(\"xPSR\"))\n\n  #define __set_BASEPRI(VALUE)        (__arm_wsr(\"BASEPRI\", (VALUE)))\n  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr(\"BASEPRI_MAX\", (VALUE)))\n  #define __set_CONTROL(VALUE)        (__arm_wsr(\"CONTROL\", (VALUE)))\n  #define __set_FAULTMASK(VALUE)      (__arm_wsr(\"FAULTMASK\", (VALUE)))\n  #define __set_MSP(VALUE)            (__arm_wsr(\"MSP\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure MSPLIM is RAZ/WI\n    #define __set_MSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_MSPLIM(VALUE)       (__arm_wsr(\"MSPLIM\", (VALUE)))\n  #endif\n  #define __set_PRIMASK(VALUE)        (__arm_wsr(\"PRIMASK\", (VALUE)))\n  #define __set_PSP(VALUE)            (__arm_wsr(\"PSP\", (VALUE)))\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __set_PSPLIM(VALUE)       ((void)(VALUE))\n  #else\n    #define __set_PSPLIM(VALUE)       (__arm_wsr(\"PSPLIM\", (VALUE)))\n  #endif\n\n  #define __TZ_get_CONTROL_NS()       (__arm_rsr(\"CONTROL_NS\"))\n  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr(\"CONTROL_NS\", (VALUE)))\n  #define __TZ_get_PSP_NS()           (__arm_rsr(\"PSP_NS\"))\n  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr(\"PSP_NS\", (VALUE)))\n  #define __TZ_get_MSP_NS()           (__arm_rsr(\"MSP_NS\"))\n  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr(\"MSP_NS\", (VALUE)))\n  #define __TZ_get_SP_NS()            (__arm_rsr(\"SP_NS\"))\n  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr(\"SP_NS\", (VALUE)))\n  #define __TZ_get_PRIMASK_NS()       (__arm_rsr(\"PRIMASK_NS\"))\n  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr(\"PRIMASK_NS\", (VALUE)))\n  #define __TZ_get_BASEPRI_NS()       (__arm_rsr(\"BASEPRI_NS\"))\n  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr(\"BASEPRI_NS\", (VALUE)))\n  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr(\"FAULTMASK_NS\"))\n  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr(\"FAULTMASK_NS\", (VALUE)))\n\n  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n    #define __TZ_get_PSPLIM_NS()      (0U)\n    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))\n  #else\n    #define __TZ_get_PSPLIM_NS()      (__arm_rsr(\"PSPLIM_NS\"))\n    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr(\"PSPLIM_NS\", (VALUE)))\n  #endif\n\n  #define __TZ_get_MSPLIM_NS()        (__arm_rsr(\"MSPLIM_NS\"))\n  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr(\"MSPLIM_NS\", (VALUE)))\n\n  #define __NOP     __iar_builtin_no_operation\n\n  #define __CLZ     __iar_builtin_CLZ\n  #define __CLREX   __iar_builtin_CLREX\n\n  #define __DMB     __iar_builtin_DMB\n  #define __DSB     __iar_builtin_DSB\n  #define __ISB     __iar_builtin_ISB\n\n  #define __LDREXB  __iar_builtin_LDREXB\n  #define __LDREXH  __iar_builtin_LDREXH\n  #define __LDREXW  __iar_builtin_LDREX\n\n  #define __RBIT    __iar_builtin_RBIT\n  #define __REV     __iar_builtin_REV\n  #define __REV16   __iar_builtin_REV16\n\n  __IAR_FT int16_t __REVSH(int16_t val)\n  {\n    return (int16_t) __iar_builtin_REVSH(val);\n  }\n\n  #define __ROR     __iar_builtin_ROR\n  #define __RRX     __iar_builtin_RRX\n\n  #define __SEV     __iar_builtin_SEV\n\n  #if !__IAR_M0_FAMILY\n    #define __SSAT    __iar_builtin_SSAT\n  #endif\n\n  #define __STREXB  __iar_builtin_STREXB\n  #define __STREXH  __iar_builtin_STREXH\n  #define __STREXW  __iar_builtin_STREX\n\n  #if !__IAR_M0_FAMILY\n    #define __USAT    __iar_builtin_USAT\n  #endif\n\n  #define __WFE     __iar_builtin_WFE\n  #define __WFI     __iar_builtin_WFI\n\n  #if __ARM_MEDIA__\n    #define __SADD8   __iar_builtin_SADD8\n    #define __QADD8   __iar_builtin_QADD8\n    #define __SHADD8  __iar_builtin_SHADD8\n    #define __UADD8   __iar_builtin_UADD8\n    #define __UQADD8  __iar_builtin_UQADD8\n    #define __UHADD8  __iar_builtin_UHADD8\n    #define __SSUB8   __iar_builtin_SSUB8\n    #define __QSUB8   __iar_builtin_QSUB8\n    #define __SHSUB8  __iar_builtin_SHSUB8\n    #define __USUB8   __iar_builtin_USUB8\n    #define __UQSUB8  __iar_builtin_UQSUB8\n    #define __UHSUB8  __iar_builtin_UHSUB8\n    #define __SADD16  __iar_builtin_SADD16\n    #define __QADD16  __iar_builtin_QADD16\n    #define __SHADD16 __iar_builtin_SHADD16\n    #define __UADD16  __iar_builtin_UADD16\n    #define __UQADD16 __iar_builtin_UQADD16\n    #define __UHADD16 __iar_builtin_UHADD16\n    #define __SSUB16  __iar_builtin_SSUB16\n    #define __QSUB16  __iar_builtin_QSUB16\n    #define __SHSUB16 __iar_builtin_SHSUB16\n    #define __USUB16  __iar_builtin_USUB16\n    #define __UQSUB16 __iar_builtin_UQSUB16\n    #define __UHSUB16 __iar_builtin_UHSUB16\n    #define __SASX    __iar_builtin_SASX\n    #define __QASX    __iar_builtin_QASX\n    #define __SHASX   __iar_builtin_SHASX\n    #define __UASX    __iar_builtin_UASX\n    #define __UQASX   __iar_builtin_UQASX\n    #define __UHASX   __iar_builtin_UHASX\n    #define __SSAX    __iar_builtin_SSAX\n    #define __QSAX    __iar_builtin_QSAX\n    #define __SHSAX   __iar_builtin_SHSAX\n    #define __USAX    __iar_builtin_USAX\n    #define __UQSAX   __iar_builtin_UQSAX\n    #define __UHSAX   __iar_builtin_UHSAX\n    #define __USAD8   __iar_builtin_USAD8\n    #define __USADA8  __iar_builtin_USADA8\n    #define __SSAT16  __iar_builtin_SSAT16\n    #define __USAT16  __iar_builtin_USAT16\n    #define __UXTB16  __iar_builtin_UXTB16\n    #define __UXTAB16 __iar_builtin_UXTAB16\n    #define __SXTB16  __iar_builtin_SXTB16\n    #define __SXTAB16 __iar_builtin_SXTAB16\n    #define __SMUAD   __iar_builtin_SMUAD\n    #define __SMUADX  __iar_builtin_SMUADX\n    #define __SMMLA   __iar_builtin_SMMLA\n    #define __SMLAD   __iar_builtin_SMLAD\n    #define __SMLADX  __iar_builtin_SMLADX\n    #define __SMLALD  __iar_builtin_SMLALD\n    #define __SMLALDX __iar_builtin_SMLALDX\n    #define __SMUSD   __iar_builtin_SMUSD\n    #define __SMUSDX  __iar_builtin_SMUSDX\n    #define __SMLSD   __iar_builtin_SMLSD\n    #define __SMLSDX  __iar_builtin_SMLSDX\n    #define __SMLSLD  __iar_builtin_SMLSLD\n    #define __SMLSLDX __iar_builtin_SMLSLDX\n    #define __SEL     __iar_builtin_SEL\n    #define __QADD    __iar_builtin_QADD\n    #define __QSUB    __iar_builtin_QSUB\n    #define __PKHBT   __iar_builtin_PKHBT\n    #define __PKHTB   __iar_builtin_PKHTB\n  #endif\n\n#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #define __CLZ  __cmsis_iar_clz_not_active\n    #define __SSAT __cmsis_iar_ssat_not_active\n    #define __USAT __cmsis_iar_usat_not_active\n    #define __RBIT __cmsis_iar_rbit_not_active\n    #define __get_APSR  __cmsis_iar_get_APSR_not_active\n  #endif\n\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active\n    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active\n  #endif\n\n  #ifdef __INTRINSICS_INCLUDED\n  #error intrinsics.h is already included previously!\n  #endif\n\n  #include <intrinsics.h>\n\n  #if __IAR_M0_FAMILY\n   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */\n    #undef __CLZ\n    #undef __SSAT\n    #undef __USAT\n    #undef __RBIT\n    #undef __get_APSR\n\n    __STATIC_INLINE uint8_t __CLZ(uint32_t data)\n    {\n      if (data == 0U) { return 32U; }\n\n      uint32_t count = 0U;\n      uint32_t mask = 0x80000000U;\n\n      while ((data & mask) == 0U)\n      {\n        count += 1U;\n        mask = mask >> 1U;\n      }\n      return count;\n    }\n\n    __STATIC_INLINE uint32_t __RBIT(uint32_t v)\n    {\n      uint8_t sc = 31U;\n      uint32_t r = v;\n      for (v >>= 1U; v; v >>= 1U)\n      {\n        r <<= 1U;\n        r |= v & 1U;\n        sc--;\n      }\n      return (r << sc);\n    }\n\n    __STATIC_INLINE  uint32_t __get_APSR(void)\n    {\n      uint32_t res;\n      __asm(\"MRS      %0,APSR\" : \"=r\" (res));\n      return res;\n    }\n\n  #endif\n\n  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))\n    #undef __get_FPSCR\n    #undef __set_FPSCR\n    #define __get_FPSCR()       (0)\n    #define __set_FPSCR(VALUE)  ((void)VALUE)\n  #endif\n\n  #pragma diag_suppress=Pe940\n  #pragma diag_suppress=Pe177\n\n  #define __enable_irq    __enable_interrupt\n  #define __disable_irq   __disable_interrupt\n  #define __NOP           __no_operation\n\n  #define __get_xPSR      __get_PSR\n\n  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)\n\n    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)\n    {\n      return __LDREX((unsigned long *)ptr);\n    }\n\n    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)\n    {\n      return __STREX(value, (unsigned long *)ptr);\n    }\n  #endif\n\n\n  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n  #if (__CORTEX_M >= 0x03)\n\n    __IAR_FT uint32_t __RRX(uint32_t value)\n    {\n      uint32_t result;\n      __ASM(\"RRX      %0, %1\" : \"=r\"(result) : \"r\" (value) : \"cc\");\n      return(result);\n    }\n\n    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_MAX,%0\"::\"r\" (value));\n    }\n\n\n    #define __enable_fault_irq  __enable_fiq\n    #define __disable_fault_irq __disable_fiq\n\n\n  #endif /* (__CORTEX_M >= 0x03) */\n\n  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)\n  {\n    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));\n  }\n\n  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n   __IAR_FT uint32_t __get_MSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,MSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_MSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure MSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      MSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __get_PSPLIM(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __set_PSPLIM(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,CONTROL_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      CONTROL_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSP_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_SP_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,SP_NS\" : \"=r\" (res));\n      return res;\n    }\n    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      SP_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,PRIMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      PRIMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,BASEPRI_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      BASEPRI_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,FAULTMASK_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      FAULTMASK_NS,%0\" :: \"r\" (value));\n    }\n\n    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)\n    {\n      uint32_t res;\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      res = 0U;\n    #else\n      __asm volatile(\"MRS      %0,PSPLIM_NS\" : \"=r\" (res));\n    #endif\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)\n    {\n    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))\n      // without main extensions, the non-secure PSPLIM is RAZ/WI\n      (void)value;\n    #else\n      __asm volatile(\"MSR      PSPLIM_NS,%0\" :: \"r\" (value));\n    #endif\n    }\n\n    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)\n    {\n      uint32_t res;\n      __asm volatile(\"MRS      %0,MSPLIM_NS\" : \"=r\" (res));\n      return res;\n    }\n\n    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)\n    {\n      __asm volatile(\"MSR      MSPLIM_NS,%0\" :: \"r\" (value));\n    }\n\n  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */\n\n#define __BKPT(value)    __asm volatile (\"BKPT     %0\" : : \"i\"(value))\n\n#if __IAR_M0_FAMILY\n  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)\n  {\n    if ((sat >= 1U) && (sat <= 32U))\n    {\n      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n      const int32_t min = -1 - max ;\n      if (val > max)\n      {\n        return max;\n      }\n      else if (val < min)\n      {\n        return min;\n      }\n    }\n    return val;\n  }\n\n  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)\n  {\n    if (sat <= 31U)\n    {\n      const uint32_t max = ((1U << sat) - 1U);\n      if (val > (int32_t)max)\n      {\n        return max;\n      }\n      else if (val < 0)\n      {\n        return 0U;\n      }\n    }\n    return (uint32_t)val;\n  }\n#endif\n\n#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */\n\n  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRBT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRHT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)\n  {\n    uint32_t res;\n    __ASM(\"LDRT %0, [%1]\" : \"=r\" (res) : \"r\" (addr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)\n  {\n    __ASM(\"STRBT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)\n  {\n    __ASM(\"STRHT %1, [%0]\" : : \"r\" (addr), \"r\" ((uint32_t)value) : \"memory\");\n  }\n\n  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)\n  {\n    __ASM(\"STRT %1, [%0]\" : : \"r\" (addr), \"r\" (value) : \"memory\");\n  }\n\n#endif /* (__CORTEX_M >= 0x03) */\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n\n  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDA %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)\n  {\n    __ASM volatile (\"STLB %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)\n  {\n    __ASM volatile (\"STLH %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)\n  {\n    __ASM volatile (\"STL %1, [%0]\" :: \"r\" (ptr), \"r\" (value) : \"memory\");\n  }\n\n  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXB %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint8_t)res);\n  }\n\n  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEXH %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return ((uint16_t)res);\n  }\n\n  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"LDAEX %0, [%1]\" : \"=r\" (res) : \"r\" (ptr) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXB %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEXH %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n  {\n    uint32_t res;\n    __ASM volatile (\"STLEX %0, %2, [%1]\" : \"=r\" (res) : \"r\" (ptr), \"r\" (value) : \"memory\");\n    return res;\n  }\n\n#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */\n\n#undef __IAR_FT\n#undef __IAR_M0_FAMILY\n#undef __ICCARM_V8\n\n#pragma diag_default=Pe940\n#pragma diag_default=Pe177\n\n#endif /* __CMSIS_ICCARM_H__ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.2\n * @date     19. April 2017\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_armv8mbl.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mbl.h\n * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     22. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MBL_H_GENERIC\n#define __CORE_ARMV8MBL_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MBL\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MBL_H_DEPENDANT\n#define __CORE_ARMV8MBL_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MBL_REV\n    #define __ARMv8MBL_REV               0x0000U\n    #warning \"__ARMv8MBL_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MBL */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MBL_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_armv8mml.h",
    "content": "/**************************************************************************//**\n * @file     core_armv8mml.h\n * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     06. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_ARMV8MML_H_GENERIC\n#define __CORE_ARMV8MML_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_ARMv8MML\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS Armv8MML definitions */\n#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \\\n                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined(__ARM_FEATURE_DSP)\n    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_ARMV8MML_H_DEPENDANT\n#define __CORE_ARMV8MML_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __ARMv8MML_REV\n    #define __ARMv8MML_REV               0x0000U\n    #warning \"__ARMv8MML_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group ARMv8MML */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[809U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */\n        uint32_t RESERVED4[4U];\n  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */\n#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI Periodic Synchronization Control Register Definitions */\n#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */\n#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */\n\n/* TPI Software Lock Status Register Definitions */\n#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */\n#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */\n\n#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */\n#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */\n\n#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */\n#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */\n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_ARMV8MML_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm0.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0.h\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\n * @version  V5.0.5\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0_H_GENERIC\n#define __CORE_CM0_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M0\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0 definitions */\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0_H_DEPENDANT\n#define __CORE_CM0_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0_REV\n    #define __CM0_REV               0x0000U\n    #warning \"__CM0_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M0 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm0plus.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0plus.h\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0PLUS_H_GENERIC\n#define __CORE_CM0PLUS_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex-M0+\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0+ definitions */\n#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\n                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\n#define __CORE_CM0PLUS_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0PLUS_REV\n    #define __CM0PLUS_REV             0x0000U\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex-M0+ */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0+ header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n    uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm1.h",
    "content": "/**************************************************************************//**\n * @file     core_cm1.h\n * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\n * @version  V1.0.0\n * @date     23. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM1_H_GENERIC\n#define __CORE_CM1_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M1\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM1 definitions */\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM1_H_DEPENDANT\n#define __CORE_CM1_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM1_REV\n    #define __CM1_REV               0x0100U\n    #warning \"__CM1_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\n\n#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M1 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm23.h",
    "content": "/**************************************************************************//**\n * @file     core_cm23.h\n * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     22. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM23_H_GENERIC\n#define __CORE_CM23_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M23\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM23_H_DEPENDANT\n#define __CORE_CM23_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM23_REV\n    #define __CM23_REV                0x0000U\n    #warning \"__CM23_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M23 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\t\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm33.h",
    "content": "/**************************************************************************//**\n * @file     core_cm33.h\n * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File\n * @version  V5.0.9\n * @date     06. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM33_H_GENERIC\n#define __CORE_CM33_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M33\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM33 definitions */\n#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined (__TARGET_FPU_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined (__ARM_PCS_VFP)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined (__ARMVFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)\n    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)\n      #define __DSP_USED       1U\n    #else\n      #error \"Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)\"\n      #define __DSP_USED         0U\n    #endif\n  #else\n    #define __DSP_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined (__TI_VFP_SUPPORT__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined (__FPU_VFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM33_H_DEPENDANT\n#define __CORE_CM33_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM33_REV\n    #define __CM33_REV                0x0000U\n    #warning \"__CM33_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DSP_PRESENT\n    #define __DSP_PRESENT             0U\n    #warning \"__DSP_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M33 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */\n#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */\n    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */\n    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */\n#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */\n\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED6[580U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */\n        uint32_t RESERVED3[92U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */\n#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */\n\n#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */\n#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */\n\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */\n#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */\n#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Non-Secure Access Control Register Definitions */\n#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */\n#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */\n\n#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */\n#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */\n\n#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */\n#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */\n        uint32_t RESERVED6[4U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Stimulus Port Register Definitions */\n#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */\n#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */\n\n#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */\n#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */\n#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */\n\n#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */\n#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n        uint32_t RESERVED32[934U];\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n        uint32_t RESERVED33[1U];\n  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */\n#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */\n  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */\n  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */\n  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */\n        uint32_t RESERVED0[1];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#else\n        uint32_t RESERVED0[3];\n#endif\n  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */\n  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/* Secure Fault Status Register Definitions */\n#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */\n#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */\n\n#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */\n#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */\n\n#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */\n#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */\n\n#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */\n#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */\n\n#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */\n#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */\n\n#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */\n#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */\n\n#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */\n#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */\n\n#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */\n#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */\n#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */\n\n#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */\n#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */\n\n#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */\n#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */\n\n#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */\n#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */\n\n#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */\n#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */\n\n#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */\n#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */\n#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */\n#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */\n  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */\n  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Set Priority Grouping (non-secure)\n  \\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB_NS->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping (non-secure)\n  \\details Reads the priority grouping field from the non-secure NVIC when in secure state.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)\n{\n  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM33_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm4.h",
    "content": "/**************************************************************************//**\n * @file     core_cm4.h\n * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM4_H_GENERIC\n#define __CORE_CM4_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M4\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM4 definitions */\n#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM4_H_DEPENDANT\n#define __CORE_CM4_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM4_REV\n    #define __CM4_REV               0x0000U\n    #warning \"__CM4_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M4 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */\n#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */\n\n#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */\n#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = FPU->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM4_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_cm7.h",
    "content": "/**************************************************************************//**\n * @file     core_cm7.h\n * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM7_H_GENERIC\n#define __CORE_CM7_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M7\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/* CMSIS CM7 definitions */\n#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\n*/\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #warning \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)\n      #define __FPU_USED       1U\n    #else\n      #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n      #define __FPU_USED       0U\n    #endif\n  #else\n    #define __FPU_USED         0U\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM7_H_DEPENDANT\n#define __CORE_CM7_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM7_REV\n    #define __CM7_REV               0x0000U\n    #warning \"__CM7_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ICACHE_PRESENT\n    #define __ICACHE_PRESENT          0U\n    #warning \"__ICACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DCACHE_PRESENT\n    #define __DCACHE_PRESENT          0U\n    #warning \"__DCACHE_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __DTCM_PRESENT\n    #define __DTCM_PRESENT            0U\n    #warning \"__DTCM_PRESENT        not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M7 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core FPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */\n#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */\n    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */\n#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */\n    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */\n#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */\n\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */\n  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */\n  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */\n  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED3[93U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */\n        uint32_t RESERVED4[15U];\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */\n        uint32_t RESERVED5[1U];\n  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */\n        uint32_t RESERVED6[1U];\n  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */\n  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */\n  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */\n  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */\n  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */\n  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */\n  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */\n  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */\n        uint32_t RESERVED7[6U];\n  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */\n  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */\n  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */\n  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */\n  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */\n\n#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */\n\n#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */\n\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */\n#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */\n#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/* SCB Cache Level ID Register Definitions */\n#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */\n#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */\n\n#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */\n#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */\n\n/* SCB Cache Type Register Definitions */\n#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */\n#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */\n\n#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */\n#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */\n\n#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */\n#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */\n\n#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */\n#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */\n\n#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */\n#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */\n\n/* SCB Cache Size ID Register Definitions */\n#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */\n#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */\n\n#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */\n#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */\n\n#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */\n#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */\n\n#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */\n#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */\n\n#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */\n#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */\n\n#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */\n#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */\n\n#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */\n#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */\n\n/* SCB Cache Size Selection Register Definitions */\n#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */\n#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */\n\n#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */\n#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */\n\n/* SCB Software Triggered Interrupt Register Definitions */\n#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */\n#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */\n\n/* SCB D-Cache Invalidate by Set-way Register Definitions */\n#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */\n#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */\n\n#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */\n#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */\n\n/* SCB D-Cache Clean by Set-way Register Definitions */\n#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */\n#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */\n\n#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */\n#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */\n\n/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\n#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */\n#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */\n\n#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */\n#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */\n\n/* Instruction Tightly-Coupled Memory Control Register Definitions */\n#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */\n#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */\n\n#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */\n#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */\n\n#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */\n#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */\n\n#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */\n#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */\n\n/* Data Tightly-Coupled Memory Control Register Definitions */\n#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */\n#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */\n\n#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */\n#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */\n\n#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */\n#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */\n\n#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */\n#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */\n\n/* AHBP Control Register Definitions */\n#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */\n#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */\n\n#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */\n#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */\n\n/* L1 Cache Control Register Definitions */\n#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */\n#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */\n\n#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */\n#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */\n\n#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */\n#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */\n\n/* AHBS Control Register Definitions */\n#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */\n#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */\n\n#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */\n#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */\n\n#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/\n#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */\n\n/* Auxiliary Bus Fault Status Register Definitions */\n#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/\n#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */\n\n#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/\n#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */\n\n#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/\n#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */\n\n#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/\n#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */\n\n#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/\n#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */\n\n#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/\n#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */\n#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */\n\n#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */\n#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */\n\n#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */\n#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED3[981U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_FPU     Floating Point Unit (FPU)\n  \\brief    Type definitions for the Floating Point Unit (FPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Floating Point Unit (FPU).\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */\n  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */\n  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */\n  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */\n  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */\n  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */\n} FPU_Type;\n\n/* Floating-Point Context Control Register Definitions */\n#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */\n#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */\n\n#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */\n#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */\n\n#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */\n#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */\n\n#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */\n#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */\n\n#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */\n#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */\n\n#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */\n#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */\n\n#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */\n#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */\n\n#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */\n#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */\n\n#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */\n#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */\n\n/* Floating-Point Context Address Register Definitions */\n#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */\n#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */\n\n/* Floating-Point Default Status Control Register Definitions */\n#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */\n#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */\n\n#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */\n#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */\n\n#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */\n#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */\n\n#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */\n#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */\n\n/* Media and FP Feature Register 0 Definitions */\n#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */\n#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */\n\n#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */\n#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */\n\n#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */\n#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */\n\n#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */\n#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */\n\n#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */\n#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */\n\n#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */\n#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */\n\n#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */\n#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */\n\n#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */\n#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */\n\n/* Media and FP Feature Register 1 Definitions */\n#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */\n#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */\n\n#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */\n#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */\n\n#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */\n#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */\n\n#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */\n#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */\n\n/* Media and FP Feature Register 2 Definitions */\n\n/*@} end of group CMSIS_FPU */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */\n#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */\n#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */\n#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n  uint32_t mvfr0;\n\n  mvfr0 = SCB->MVFR0;\n  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)\n  {\n    return 2U;           /* Double + Single precision FPU */\n  }\n  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)\n  {\n    return 1U;           /* Single precision FPU */\n  }\n  else\n  {\n    return 0U;           /* No FPU */\n  }\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################  Cache functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_CacheFunctions Cache Functions\n  \\brief    Functions that configure Instruction and Data cache.\n  @{\n */\n\n/* Cache Size ID Register Macros */\n#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\n#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )\n\n\n/**\n  \\brief   Enable I-Cache\n  \\details Turns on I-Cache\n  */\n__STATIC_INLINE void SCB_EnableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable I-Cache\n  \\details Turns off I-Cache\n  */\n__STATIC_INLINE void SCB_DisableICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */\n    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate I-Cache\n  \\details Invalidates I-Cache\n  */\n__STATIC_INLINE void SCB_InvalidateICache (void)\n{\n  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)\n    __DSB();\n    __ISB();\n    SCB->ICIALLU = 0UL;\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Enable D-Cache\n  \\details Turns on D-Cache\n  */\n__STATIC_INLINE void SCB_EnableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n    __DSB();\n\n    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Disable D-Cache\n  \\details Turns off D-Cache\n  */\n__STATIC_INLINE void SCB_DisableDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Invalidate D-Cache\n  \\details Invalidates D-Cache\n  */\n__STATIC_INLINE void SCB_InvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\n                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean D-Cache\n  \\details Cleans D-Cache\n  */\n__STATIC_INLINE void SCB_CleanDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n   __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\n                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   Clean & Invalidate D-Cache\n  \\details Cleans and Invalidates D-Cache\n  */\n__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n    uint32_t ccsidr;\n    uint32_t sets;\n    uint32_t ways;\n\n    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */\n    __DSB();\n\n    ccsidr = SCB->CCSIDR;\n\n                                            /* clean & invalidate D-Cache */\n    sets = (uint32_t)(CCSIDR_SETS(ccsidr));\n    do {\n      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\n      do {\n        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\n                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );\n        #if defined ( __CC_ARM )\n          __schedule_barrier();\n        #endif\n      } while (ways-- != 0U);\n    } while(sets-- != 0U);\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Invalidate by address\n  \\details Invalidates D-Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t)addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCIMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean by address\n  \\details Cleans D-Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t) addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCCMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/**\n  \\brief   D-Cache Clean and Invalidate by address\n  \\details Cleans and invalidates D_Cache for the given address\n  \\param[in]   addr    address (aligned to 32-byte boundary)\n  \\param[in]   dsize   size of memory block (in number of bytes)\n*/\n__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\n{\n  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)\n     int32_t op_size = dsize;\n    uint32_t op_addr = (uint32_t) addr;\n     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\n\n    __DSB();\n\n    while (op_size > 0) {\n      SCB->DCCIMVAC = op_addr;\n      op_addr += (uint32_t)linesize;\n      op_size -=           linesize;\n    }\n\n    __DSB();\n    __ISB();\n  #endif\n}\n\n\n/*@} end of CMSIS_Core_CacheFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM7_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_sc000.h",
    "content": "/**************************************************************************//**\n * @file     core_sc000.h\n * @brief    CMSIS SC000 Core Peripheral Access Layer Header File\n * @version  V5.0.5\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC000_H_GENERIC\n#define __CORE_SC000_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC000 definitions */\n#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC000_H_DEPENDANT\n#define __CORE_SC000_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC000_REV\n    #define __SC000_REV             0x0000U\n    #warning \"__SC000_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC000 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n        uint32_t RESERVED1[154U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the SC000 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC000_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/core_sc300.h",
    "content": "/**************************************************************************//**\n * @file     core_sc300.h\n * @brief    CMSIS SC300 Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_SC300_H_GENERIC\n#define __CORE_SC300_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup SC3000\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS SC300 definitions */\n#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \\\n                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_SC300_H_DEPENDANT\n#define __CORE_SC300_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __SC300_REV\n    #define __SC300_REV               0x0000U\n    #warning \"__SC300_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group SC300 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n        uint32_t RESERVED1[129U];\n  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n        uint32_t RESERVED1[1U];\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_SC300_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/mpu_armv7.h",
    "content": "/******************************************************************************\n * @file     mpu_armv7.h\n * @brief    CMSIS MPU API for Armv7-M MPU\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n \n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n \n#ifndef ARM_MPU_ARMV7_H\n#define ARM_MPU_ARMV7_H\n\n#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes\n#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes\n#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes\n#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes\n#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes\n#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte\n#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes\n#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes\n#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes\n#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes\n#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes\n#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes\n#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes\n#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes\n#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes\n#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte\n#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes\n#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes\n#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes\n#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes\n#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes\n#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes\n#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes\n#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes\n#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes\n#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte\n#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes\n#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes\n\n#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access\n#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only\n#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only\n#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access\n#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only\n#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access\n\n/** MPU Region Base Address Register Value\n*\n* \\param Region The region to be configured, number 0 to 15.\n* \\param BaseAddress The base address for the region.\n*/\n#define ARM_MPU_RBAR(Region, BaseAddress) \\\n  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \\\n   ((Region) & MPU_RBAR_REGION_Msk)    |  \\\n   (MPU_RBAR_VALID_Msk))\n\n/**\n* MPU Memory Access Attributes\n* \n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n*/  \n#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \\\n  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \\\n   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \\\n   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \\\n   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))\n\n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param AccessAttributes  Memory access attribution, see \\ref ARM_MPU_ACCESS_.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/\n#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \\\n  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \\\n   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \\\n   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))\n  \n/**\n* MPU Region Attribute and Size Register Value\n* \n* \\param DisableExec       Instruction access disable bit, 1= disable instruction fetches.\n* \\param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.\n* \\param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.\n* \\param IsShareable       Region is shareable between multiple bus masters.\n* \\param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.\n* \\param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.\n* \\param SubRegionDisable  Sub-region disable field.\n* \\param Size              Region size of the region to be configured, for example 4K, 8K.\n*/                         \n#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \\\n  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)\n\n/**\n* MPU Memory Access Attribute for strongly ordered memory.\n*  - TEX: 000b\n*  - Shareable\n*  - Non-cacheable\n*  - Non-bufferable\n*/ \n#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)\n\n/**\n* MPU Memory Access Attribute for device memory.\n*  - TEX: 000b (if non-shareable) or 010b (if shareable)\n*  - Shareable or non-shareable\n*  - Non-cacheable\n*  - Bufferable (if shareable) or non-bufferable (if non-shareable)\n*\n* \\param IsShareable Configures the device memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))\n\n/**\n* MPU Memory Access Attribute for normal memory.\n*  - TEX: 1BBb (reflecting outer cacheability rules)\n*  - Shareable or non-shareable\n*  - Cacheable or non-cacheable (reflecting inner cacheability rules)\n*  - Bufferable or non-bufferable (reflecting inner cacheability rules)\n*\n* \\param OuterCp Configures the outer cache policy.\n* \\param InnerCp Configures the inner cache policy.\n* \\param IsShareable Configures the memory as shareable or non-shareable.\n*/ \n#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))\n\n/**\n* MPU Memory Access Attribute non-cacheable policy.\n*/\n#define ARM_MPU_CACHEP_NOCACHE 0U\n\n/**\n* MPU Memory Access Attribute write-back, write and read allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_WRA 1U\n\n/**\n* MPU Memory Access Attribute write-through, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WT_NWA 2U\n\n/**\n* MPU Memory Access Attribute write-back, no write allocate policy.\n*/\n#define ARM_MPU_CACHEP_WB_NWA 3U\n\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR; //!< The region base address register value (RBAR)\n  uint32_t RASR; //!< The region attribute and size register value (RASR) \\ref MPU_RASR\n} ARM_MPU_Region_t;\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  MPU->RNR = rnr;\n  MPU->RASR = 0U;\n}\n\n/** Configure an MPU region.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)\n{\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rsar Value for RSAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)\n{\n  MPU->RNR = rnr;\n  MPU->RBAR = rbar;\n  MPU->RASR = rasr;\n}\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  while (cnt > MPU_TYPE_RALIASES) {\n    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);\n    table += MPU_TYPE_RALIASES;\n    cnt -= MPU_TYPE_RALIASES;\n  }\n  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);\n}\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/mpu_armv8.h",
    "content": "/******************************************************************************\n * @file     mpu_armv8.h\n * @brief    CMSIS MPU API for Armv8-M MPU\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header    /* treat file as system include file */\n#endif\n\n#ifndef ARM_MPU_ARMV8_H\n#define ARM_MPU_ARMV8_H\n\n/** \\brief Attribute for device memory (outer only) */\n#define ARM_MPU_ATTR_DEVICE                           ( 0U )\n\n/** \\brief Attribute for non-cacheable, normal memory */\n#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )\n\n/** \\brief Attribute for normal memory (outer and inner)\n* \\param NT Non-Transient: Set to 1 for non-transient data.\n* \\param WB Write-Back: Set to 1 to use write-back update policy.\n* \\param RA Read Allocation: Set to 1 to use cache allocation on read miss.\n* \\param WA Write Allocation: Set to 1 to use cache allocation on write miss.\n*/\n#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \\\n  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))\n\n/** \\brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)\n\n/** \\brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)\n\n/** \\brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)\n\n/** \\brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */\n#define ARM_MPU_ATTR_DEVICE_GRE    (3U)\n\n/** \\brief Memory Attribute\n* \\param O Outer memory attributes\n* \\param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes\n*/\n#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))\n\n/** \\brief Normal memory non-shareable  */\n#define ARM_MPU_SH_NON   (0U)\n\n/** \\brief Normal memory outer shareable  */\n#define ARM_MPU_SH_OUTER (2U)\n\n/** \\brief Normal memory inner shareable  */\n#define ARM_MPU_SH_INNER (3U)\n\n/** \\brief Memory access permissions\n* \\param RO Read-Only: Set to 1 for read-only memory.\n* \\param NP Non-Privileged: Set to 1 for non-privileged memory.\n*/\n#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))\n\n/** \\brief Region Base Address Register value\n* \\param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.\n* \\param SH Defines the Shareability domain for this memory region.\n* \\param RO Read-Only: Set to 1 for a read-only memory region.\n* \\param NP Non-Privileged: Set to 1 for a non-privileged memory region.\n* \\oaram XN eXecute Never: Set to 1 for a non-executable memory region.\n*/\n#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \\\n  ((BASE & MPU_RBAR_BASE_Msk) | \\\n  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \\\n  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \\\n  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))\n\n/** \\brief Region Limit Address Register value\n* \\param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.\n* \\param IDX The attribute index to be associated with this memory region.\n*/\n#define ARM_MPU_RLAR(LIMIT, IDX) \\\n  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \\\n  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \\\n  (MPU_RLAR_EN_Msk))\n\n/**\n* Struct for a single MPU Region\n*/\ntypedef struct {\n  uint32_t RBAR;                   /*!< Region Base Address Register value */\n  uint32_t RLAR;                   /*!< Region Limit Address Register value */\n} ARM_MPU_Region_t;\n    \n/** Enable the MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n\n#ifdef MPU_NS\n/** Enable the Non-secure MPU.\n* \\param MPU_Control Default access permissions for unconfigured regions.\n*/\n__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)\n{\n  __DSB();\n  __ISB();\n  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n}\n\n/** Disable the Non-secure MPU.\n*/\n__STATIC_INLINE void ARM_MPU_Disable_NS(void)\n{\n  __DSB();\n  __ISB();\n#ifdef SCB_SHCSR_MEMFAULTENA_Msk\n  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n#endif\n  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;\n}\n#endif\n\n/** Set the memory attribute encoding to the given MPU.\n* \\param mpu Pointer to the MPU to be configured.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)\n{\n  const uint8_t reg = idx / 4U;\n  const uint32_t pos = ((idx % 4U) * 8U);\n  const uint32_t mask = 0xFFU << pos;\n  \n  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {\n    return; // invalid index\n  }\n  \n  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));\n}\n\n/** Set the memory attribute encoding.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU, idx, attr);\n}\n\n#ifdef MPU_NS\n/** Set the memory attribute encoding to the Non-secure MPU.\n* \\param idx The attribute index to be set [0-7]\n* \\param attr The attribute value to be set.\n*/\n__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)\n{\n  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);\n}\n#endif\n\n/** Clear and disable the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)\n{\n  mpu->RNR = rnr;\n  mpu->RLAR = 0U;\n}\n\n/** Clear and disable the given MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)\n{\n  ARM_MPU_ClrRegionEx(MPU, rnr);\n}\n\n#ifdef MPU_NS\n/** Clear and disable the given Non-secure MPU region.\n* \\param rnr Region number to be cleared.\n*/\n__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)\n{  \n  ARM_MPU_ClrRegionEx(MPU_NS, rnr);\n}\n#endif\n\n/** Configure the given MPU region of the given MPU.\n* \\param mpu Pointer to MPU to be used.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  mpu->RNR = rnr;\n  mpu->RBAR = rbar;\n  mpu->RLAR = rlar;\n}\n\n/** Configure the given MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);\n}\n\n#ifdef MPU_NS\n/** Configure the given Non-secure MPU region.\n* \\param rnr Region number to be configured.\n* \\param rbar Value for RBAR register.\n* \\param rlar Value for RLAR register.\n*/   \n__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)\n{\n  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  \n}\n#endif\n\n/** Memcopy with strictly ordered memory access, e.g. for register targets.\n* \\param dst Destination data is copied to.\n* \\param src Source data is copied from.\n* \\param len Amount of data words to be copied.\n*/\n__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)\n{\n  uint32_t i;\n  for (i = 0U; i < len; ++i) \n  {\n    dst[i] = src[i];\n  }\n}\n\n/** Load the given number of MPU regions from a table to the given MPU.\n* \\param mpu Pointer to the MPU registers to be used.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;\n  if (cnt == 1U) {\n    mpu->RNR = rnr;\n    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);\n  } else {\n    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);\n    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;\n    \n    mpu->RNR = rnrBase;\n    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {\n      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;\n      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);\n      table += c;\n      cnt -= c;\n      rnrOffset = 0U;\n      rnrBase += MPU_TYPE_RALIASES;\n      mpu->RNR = rnrBase;\n    }\n    \n    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);\n  }\n}\n\n/** Load the given number of MPU regions from a table.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU, rnr, table, cnt);\n}\n\n#ifdef MPU_NS\n/** Load the given number of MPU regions from a table to the Non-secure MPU.\n* \\param rnr First region number to be configured.\n* \\param table Pointer to the MPU configuration table.\n* \\param cnt Amount of regions to be configured.\n*/\n__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) \n{\n  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/CMSIS/Include/tz_context.h",
    "content": "/******************************************************************************\n * @file     tz_context.h\n * @brief    Context Management for Armv8-M TrustZone\n * @version  V1.0.1\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2017-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef TZ_CONTEXT_H\n#define TZ_CONTEXT_H\n \n#include <stdint.h>\n \n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n \n/// \\details TZ Memory ID identifies an allocated memory slot.\ntypedef uint32_t TZ_MemoryId_t;\n  \n/// Initialize secure context memory system\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_InitContextSystem_S (void);\n \n/// Allocate context memory for calling secure software modules in TrustZone\n/// \\param[in]  module   identifies software modules called from non-secure mode\n/// \\return value != 0 id TrustZone memory slot identifier\n/// \\return value 0    no memory available or internal error\nTZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);\n \n/// Free context memory that was previously allocated with \\ref TZ_AllocModuleContext_S\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);\n \n/// Load secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_LoadContext_S (TZ_MemoryId_t id);\n \n/// Store secure context (called on RTOS thread context switch)\n/// \\param[in]  id  TrustZone memory slot identifier\n/// \\return execution status (1: success, 0: error)\nuint32_t TZ_StoreContext_S (TZ_MemoryId_t id);\n \n#endif  // TZ_CONTEXT_H\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32_hal_legacy.h\n  * @author  MCD Application Team\n  * @brief   This file contains aliases definition for the STM32Cube HAL constants\n  *          macros and functions maintained for legacy purpose.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32_HAL_LEGACY\n#define STM32_HAL_LEGACY\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR\n#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR\n#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF\n#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR\n#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR\n/**\n  * @}\n  */\n\n/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B\n#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B\n#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B\n#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B\n#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN\n#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED\n#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV\n#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV\n#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV\n#define REGULAR_GROUP                   ADC_REGULAR_GROUP\n#define INJECTED_GROUP                  ADC_INJECTED_GROUP\n#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP\n#define AWD_EVENT                       ADC_AWD_EVENT\n#define AWD1_EVENT                      ADC_AWD1_EVENT\n#define AWD2_EVENT                      ADC_AWD2_EVENT\n#define AWD3_EVENT                      ADC_AWD3_EVENT\n#define OVR_EVENT                       ADC_OVR_EVENT\n#define JQOVF_EVENT                     ADC_JQOVF_EVENT\n#define ALL_CHANNELS                    ADC_ALL_CHANNELS\n#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS\n#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS\n#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR\n#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT\n#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1\n#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2\n#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4\n#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6\n#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8\n#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO\n#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2\n#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO\n#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4\n#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO\n#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11\n#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1\n#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE\n#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING\n#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING\n#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING\n#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5\n\n#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY\n#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY\n#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC\n#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC\n#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL\n#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL\n#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1\n\n#if defined(STM32H7)\n#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT\n#endif /* STM32H7 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE\n#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE\n#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1\n#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2\n#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3\n#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4\n#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5\n#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6\n#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7\n#if defined(STM32L0)\n#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */\n#endif\n#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR\n#if defined(STM32F373xC) || defined(STM32F378xx)\n#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1\n#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR\n#endif /* STM32F373xC || STM32F378xx */\n\n#if defined(STM32L0) || defined(STM32L4)\n#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON\n\n#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1\n#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2\n#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3\n#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4\n#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5\n#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6\n\n#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT\n#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT\n#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT\n#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT\n#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1\n#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2\n#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1\n#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2\n#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1\n#if defined(STM32L0)\n/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */\n/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */\n/* to the second dedicated IO (only for COMP2).                               */\n#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2\n#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2\n#else\n#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2\n#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3\n#endif\n#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4\n#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5\n\n#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW\n#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH\n\n/* Note: Literal \"COMP_FLAG_LOCK\" kept for legacy purpose.                    */\n/*       To check COMP lock state, use macro \"__HAL_COMP_IS_LOCKED()\".        */\n#if defined(COMP_CSR_LOCK)\n#define COMP_FLAG_LOCK                 COMP_CSR_LOCK\n#elif defined(COMP_CSR_COMP1LOCK)\n#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK\n#elif defined(COMP_CSR_COMPxLOCK)\n#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK\n#endif\n\n#if defined(STM32L4)\n#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1\n#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1\n#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1\n#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2\n#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2\n#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2\n#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE\n#endif\n\n#if defined(STM32L0)\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED\n#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER\n#else\n#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED\n#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED\n#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER\n#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER\n#endif\n\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig\n/**\n  * @}\n  */\n\n/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE\n#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1\n#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2\n#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1\n#define DAC_WAVE_NONE                                   0x00000000U\n#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0\n#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1\n#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE\n#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE\n#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE\n\n#if defined(STM32G4) || defined(STM32H7)\n#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL\n#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL\n#endif\n\n#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)\n#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID\n#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2\n#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4\n#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5\n#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4\n#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2\n#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32\n#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6\n#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7\n#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67\n#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67\n#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76\n#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6\n#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7\n#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6\n\n#define IS_HAL_REMAPDMA                          IS_DMA_REMAP\n#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE\n#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE\n\n#if defined(STM32L4)\n\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\n#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\n#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE\n#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT\n#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT\n#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT\n\n#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT\n#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING\n#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING\n#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING\n\n#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)\n#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI\n#endif\n\n#endif /* STM32L4 */\n\n#if defined(STM32G0)\n#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1\n#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2\n#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM\n#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM\n\n#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM\n#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM\n#endif\n\n#if defined(STM32H7)\n\n#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1\n#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2\n\n#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX\n#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX\n\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT\n#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT\n#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT\n#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT\n#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0\n#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO\n\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT\n#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT\n#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP\n#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0\n#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2\n#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT\n#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT\n#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT\n#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT\n#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT\n#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT\n#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT\n#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT\n\n#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT\n#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING\n#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING\n#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING\n\n#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT\n#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT\n#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT\n\n#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT\n#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT\n\n#endif /* STM32H7 */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE\n#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD\n#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD\n#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD\n#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS\n#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES\n#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES\n#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE\n#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE\n#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE\n#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE\n#define OBEX_PCROP                    OPTIONBYTE_PCROP\n#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG\n#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE\n#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE\n#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE\n#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD\n#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD\n#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE\n#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD\n#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD\n#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE\n#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD\n#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD\n#define PAGESIZE                      FLASH_PAGE_SIZE\n#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE\n#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD\n#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD\n#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1\n#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2\n#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3\n#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4\n#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST\n#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST\n#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA\n#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB\n#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA\n#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB\n#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE\n#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN\n#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE\n#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN\n#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE\n#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD\n#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG\n#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS\n#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP\n#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV\n#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR\n#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG\n#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION\n#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA\n#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE\n#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE\n#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS\n#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS\n#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST\n#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR\n#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO\n#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION\n#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS\n#define OB_WDG_SW                     OB_IWDG_SW\n#define OB_WDG_HW                     OB_IWDG_HW\n#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET\n#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET\n#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET\n#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET\n#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR\n#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0\n#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1\n#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2\n#if defined(STM32G0)\n#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE\n#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH\n#else\n#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE\n#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE\n#endif\n#if defined(STM32H7)\n#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1\n#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1\n#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1\n#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2\n#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2\n#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2\n#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE\n#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL\n#endif /* STM32H7 */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#if defined(STM32H7)\n#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE\n#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE\n#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET\n#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET\n#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE\n#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE\n#endif /* STM32H7 */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8\n#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9\n#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1\n#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2\n#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3\n#if defined(STM32G4)\n\n#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster\n#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster\n#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD\n#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD\n#endif /* STM32G4 */\n/**\n  * @}\n  */\n\n\n/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose\n  * @{\n  */\n#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)\n#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE\n#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8\n#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16\n#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)\n#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE\n#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE\n#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8\n#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef\n#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef\n/**\n  * @}\n  */\n\n/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define GET_GPIO_SOURCE                           GPIO_GET_INDEX\n#define GET_GPIO_INDEX                            GPIO_GET_INDEX\n\n#if defined(STM32F4)\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO\n#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO\n#endif\n\n#if defined(STM32F7)\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\n#endif\n\n#if defined(STM32L4)\n#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1\n#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1\n#endif\n\n#if defined(STM32H7)\n#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1\n#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1\n#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1\n#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2\n#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2\n#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2\n\n#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \\\n    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)\n#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS\n#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS\n#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS\n#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */\n#endif /* STM32H7 */\n\n#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1\n#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1\n#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1\n\n#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)\n#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW\n#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM\n#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH\n#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH\n#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/\n\n#if defined(STM32L1)\n#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW\n#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM\n#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH\n#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH\n#endif /* STM32L1 */\n\n#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)\n#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW\n#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM\n#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH\n#endif /* STM32F0 || STM32F3 || STM32F1 */\n\n#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1\n/**\n  * @}\n  */\n\n/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7\n#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7\n#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7\n\n#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER\n#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER\n#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD\n#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD\n#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER\n#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER\n#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE\n#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE\n\n#if defined(STM32G4)\n#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig\n#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable\n#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable\n#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset\n#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A\n#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B\n#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL\n#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL\n#endif /* STM32G4 */\n\n#if defined(STM32H7)\n#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9\n\n#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9\n#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1\n#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2\n#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3\n#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4\n#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5\n#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6\n#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7\n#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8\n#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9\n#endif /* STM32H7 */\n\n#if defined(STM32F3)\n/** @brief Constants defining available sources associated to external events.\n  */\n#define HRTIM_EVENTSRC_1              (0x00000000U)\n#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)\n#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)\n#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)\n\n/** @brief Constants defining the DLL calibration periods (in micro seconds)\n  */\n#define HRTIM_CALIBRATIONRATE_7300             0x00000000U\n#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)\n#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)\n#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)\n\n#endif /* STM32F3 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE\n#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE\n#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE\n#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE\n#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE\n#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE\n#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE\n#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE\n#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)\n#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX\n#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX\n#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX\n#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX\n#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX\n#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE\n#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD\n#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE\n#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE\n#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION\n#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS\n#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS\n#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS\n\n#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING\n#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING\n#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING\n\n#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION\n#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS\n#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS\n#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS\n\n/* The following 3 definition have also been present in a temporary version of lptim.h */\n/* They need to be renamed also to the right name, just in case */\n#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS\n#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS\n#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b\n#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b\n#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b\n#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b\n\n#define NAND_AddressTypedef             NAND_AddressTypeDef\n\n#define __ARRAY_ADDRESS                 ARRAY_ADDRESS\n#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE\n#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE\n#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE\n#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef\n#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS\n#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING\n#define NOR_ERROR                      HAL_NOR_STATUS_ERROR\n#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT\n\n#define __NOR_WRITE                    NOR_WRITE\n#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT\n/**\n  * @}\n  */\n\n/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0\n#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1\n#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2\n#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3\n\n#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0\n#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1\n#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2\n#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3\n\n#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0\n#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1\n\n#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0\n#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1\n\n#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0\n#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1\n\n#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1\n\n#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO\n#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0\n#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1\n\n#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)\n#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID\n#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID\n#endif\n\n#if defined(STM32L4) || defined(STM32L5)\n#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER\n#elif defined(STM32G4)\n#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS\n\n#if defined(STM32H7)\n#define I2S_IT_TXE               I2S_IT_TXP\n#define I2S_IT_RXNE              I2S_IT_RXP\n\n#define I2S_FLAG_TXE             I2S_FLAG_TXP\n#define I2S_FLAG_RXNE            I2S_FLAG_RXP\n#endif\n\n#if defined(STM32F7)\n#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n/* Compact Flash-ATA registers description */\n#define CF_DATA                       ATA_DATA\n#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT\n#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER\n#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW\n#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH\n#define CF_CARD_HEAD                  ATA_CARD_HEAD\n#define CF_STATUS_CMD                 ATA_STATUS_CMD\n#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE\n#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA\n\n/* Compact Flash-ATA commands */\n#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD\n#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD\n#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD\n#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD\n\n#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef\n#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS\n#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING\n#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR\n#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT\n/**\n  * @}\n  */\n\n/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define FORMAT_BIN                  RTC_FORMAT_BIN\n#define FORMAT_BCD                  RTC_FORMAT_BCD\n\n#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE\n#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE\n#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE\n#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE\n\n#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE\n#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE\n#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE\n#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT\n#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT\n\n#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT\n#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1\n#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1\n#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2\n\n#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE\n#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1\n#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1\n\n#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT\n#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1\n#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1\n\n#if defined(STM32H7)\n#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X\n#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT\n\n#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1\n#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2\n#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3\n#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL\n#endif /* STM32H7 */\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE\n#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE\n\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE\n#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE\n#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE\n\n#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE\n#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE\n\n#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE\n#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE\n#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE\n#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE\n#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE\n#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE\n#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE\n#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE\n#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE\n#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE\n#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE\n#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE\n#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE\n\n#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE\n#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE\n\n#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE\n#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE\n\n#if defined(STM32H7)\n\n#define SPI_FLAG_TXE                    SPI_FLAG_TXP\n#define SPI_FLAG_RXNE                   SPI_FLAG_RXP\n\n#define SPI_IT_TXE                      SPI_IT_TXP\n#define SPI_IT_RXNE                     SPI_IT_RXP\n\n#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET\n#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET\n#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET\n#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET\n\n#endif /* STM32H7 */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK\n#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK\n\n#define TIM_DMABase_CR1                  TIM_DMABASE_CR1\n#define TIM_DMABase_CR2                  TIM_DMABASE_CR2\n#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR\n#define TIM_DMABase_DIER                 TIM_DMABASE_DIER\n#define TIM_DMABase_SR                   TIM_DMABASE_SR\n#define TIM_DMABase_EGR                  TIM_DMABASE_EGR\n#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1\n#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2\n#define TIM_DMABase_CCER                 TIM_DMABASE_CCER\n#define TIM_DMABase_CNT                  TIM_DMABASE_CNT\n#define TIM_DMABase_PSC                  TIM_DMABASE_PSC\n#define TIM_DMABase_ARR                  TIM_DMABASE_ARR\n#define TIM_DMABase_RCR                  TIM_DMABASE_RCR\n#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1\n#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2\n#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3\n#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4\n#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR\n#define TIM_DMABase_DCR                  TIM_DMABASE_DCR\n#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR\n#define TIM_DMABase_OR1                  TIM_DMABASE_OR1\n#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3\n#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5\n#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6\n#define TIM_DMABase_OR2                  TIM_DMABASE_OR2\n#define TIM_DMABase_OR3                  TIM_DMABASE_OR3\n#define TIM_DMABase_OR                   TIM_DMABASE_OR\n\n#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE\n#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1\n#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2\n#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3\n#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4\n#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM\n#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER\n#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK\n#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2\n\n#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER\n#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS\n#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS\n#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS\n#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS\n#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS\n#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS\n#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS\n#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS\n#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS\n#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS\n#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS\n#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS\n#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS\n#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS\n#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS\n#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS\n#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS\n\n#if defined(STM32L0)\n#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO\n#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO\n#endif\n\n#if defined(STM32F3)\n#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE\n#endif\n\n#if defined(STM32H7)\n#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1\n#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2\n#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1\n#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2\n#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1\n#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2\n#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1\n#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1\n#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2\n#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1\n#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2\n#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2\n#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1\n#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2\n#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING\n#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING\n/**\n  * @}\n  */\n\n/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE\n#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE\n#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE\n#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE\n\n#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE\n#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE\n\n#define __DIV_SAMPLING16                UART_DIV_SAMPLING16\n#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16\n#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16\n#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16\n\n#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8\n#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8\n#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8\n#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8\n\n#define __DIV_LPUART                    UART_DIV_LPUART\n\n#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE\n#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE\n#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE\n\n#define USARTNACK_ENABLED               USART_NACK_ENABLE\n#define USARTNACK_DISABLED              USART_NACK_DISABLE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define CFR_BASE                    WWDG_CFR_BASE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define CAN_FilterFIFO0             CAN_FILTER_FIFO0\n#define CAN_FilterFIFO1             CAN_FILTER_FIFO1\n#define CAN_IT_RQCP0                CAN_IT_TME\n#define CAN_IT_RQCP1                CAN_IT_TME\n#define CAN_IT_RQCP2                CAN_IT_TME\n#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE\n#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE\n#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)\n#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)\n#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n#define VLAN_TAG                ETH_VLAN_TAG\n#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD\n#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD\n#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD\n#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK\n#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK\n#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK\n#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK\n\n#define ETH_MMCCR              0x00000100U\n#define ETH_MMCRIR             0x00000104U\n#define ETH_MMCTIR             0x00000108U\n#define ETH_MMCRIMR            0x0000010CU\n#define ETH_MMCTIMR            0x00000110U\n#define ETH_MMCTGFSCCR         0x0000014CU\n#define ETH_MMCTGFMSCCR        0x00000150U\n#define ETH_MMCTGFCR           0x00000168U\n#define ETH_MMCRFCECR          0x00000194U\n#define ETH_MMCRFAECR          0x00000198U\n#define ETH_MMCRGUFCR          0x000001C4U\n\n#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */\n#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */\n#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */\n#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */\n#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */\n#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */\n#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */\n#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */\n#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */\n#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */\n#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */\n#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */\n#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */\n#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */\n#if defined(STM32F1)\n#else\n#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */\n#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */\n#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */\n#endif\n#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */\n#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */\n#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */\n#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */\n#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */\n#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */\n#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR\n#define DCMI_IT_OVF             DCMI_IT_OVR\n#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI\n#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI\n\n#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop\n#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop\n#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop\n\n/**\n  * @}\n  */\n\n#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \\\n  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \\\n  || defined(STM32H7)\n/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose\n  * @{\n  */\n#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888\n#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888\n#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565\n#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555\n#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444\n\n#define CM_ARGB8888             DMA2D_INPUT_ARGB8888\n#define CM_RGB888               DMA2D_INPUT_RGB888\n#define CM_RGB565               DMA2D_INPUT_RGB565\n#define CM_ARGB1555             DMA2D_INPUT_ARGB1555\n#define CM_ARGB4444             DMA2D_INPUT_ARGB4444\n#define CM_L8                   DMA2D_INPUT_L8\n#define CM_AL44                 DMA2D_INPUT_AL44\n#define CM_AL88                 DMA2D_INPUT_AL88\n#define CM_L4                   DMA2D_INPUT_L4\n#define CM_A8                   DMA2D_INPUT_A8\n#define CM_A4                   DMA2D_INPUT_A4\n/**\n  * @}\n  */\n#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */\n\n/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback\n/**\n  * @}\n  */\n\n/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef\n#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef\n#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish\n#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish\n#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish\n#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish\n\n/*HASH Algorithm Selection*/\n\n#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1\n#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224\n#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256\n#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5\n\n#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH\n#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC\n\n#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY\n#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY\n\n#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)\n\n#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt\n#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End\n#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT\n#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT\n\n#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt\n#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End\n#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT\n#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT\n\n#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt\n#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End\n#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT\n#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT\n\n#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt\n#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End\n#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT\n#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT\n\n#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode\n#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode\n#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode\n#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode\n#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode\n#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode\n#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\\\n                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))\n#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect\n#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())\n#if defined(STM32L0)\n#else\n#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())\n#endif\n#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())\n#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\\\n                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())\n#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)\n#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode\n#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode\n#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode\n#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode\n#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram\n#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown\n#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown\n#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock\n#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock\n#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase\n#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program\n\n/**\n  * @}\n */\n\n/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter\n#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter\n#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter\n#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter\n\n#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\\\n                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))\n\n#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)\n#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT\n#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT\n#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT\n#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT\n#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */\n#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)\n#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA\n#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA\n#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA\n#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA\n#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */\n\n#if defined(STM32F4)\n#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT\n#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT\n#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT\n#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT\n#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA\n#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA\n#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA\n#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA\n#endif /* STM32F4 */\n/**\n  * @}\n */\n\n/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose\n  * @{\n  */\n\n#if defined(STM32G0)\n#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD\n#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD\n#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD\n#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler\n#endif\n#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD\n#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg\n#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown\n#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor\n#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg\n#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown\n#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor\n#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler\n#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD\n#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler\n#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback\n#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive\n#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive\n#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC\n#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC\n#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM\n\n#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL\n#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING\n#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING\n#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING\n#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING\n#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING\n#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING\n\n#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB\n#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB\n#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER\n#define CR_PMODE_BB                                   CR_VOS_BB\n\n#define DBP_BitNumber                                 DBP_BIT_NUMBER\n#define PVDE_BitNumber                                PVDE_BIT_NUMBER\n#define PMODE_BitNumber                               PMODE_BIT_NUMBER\n#define EWUP_BitNumber                                EWUP_BIT_NUMBER\n#define FPDS_BitNumber                                FPDS_BIT_NUMBER\n#define ODEN_BitNumber                                ODEN_BIT_NUMBER\n#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER\n#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER\n#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER\n#define BRE_BitNumber                                 BRE_BIT_NUMBER\n\n#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL\n\n/**\n  * @}\n */\n\n/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT\n#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback\n#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo\n/**\n  * @}\n  */\n\n/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt\n#define HAL_TIM_DMAError                                TIM_DMAError\n#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt\n#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt\n#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)\n#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro\n#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT\n#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback\n#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent\n#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT\n#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA\n#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback\n/**\n  * @}\n  */\n\n/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback\n#define HAL_LTDC_Relaod           HAL_LTDC_Reload\n#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig\n#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macros ------------------------------------------------------------*/\n\n/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define AES_IT_CC                      CRYP_IT_CC\n#define AES_IT_ERR                     CRYP_IT_ERR\n#define AES_FLAG_CCF                   CRYP_FLAG_CCF\n/**\n  * @}\n  */\n\n/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE\n#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH\n#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH\n#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM\n#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC\n#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM\n#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC\n#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI\n#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK\n#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG\n#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG\n#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE\n#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE\n#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE\n\n#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY\n#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48\n#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS\n#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER\n#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __ADC_ENABLE                                     __HAL_ADC_ENABLE\n#define __ADC_DISABLE                                    __HAL_ADC_DISABLE\n#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS\n#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS\n#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE\n#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE\n#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR\n#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED\n#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR\n#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED\n#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING\n#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE\n\n#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION\n#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK\n#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT\n#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR\n#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION\n#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE\n#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS\n#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS\n#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM\n#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT\n#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS\n#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN\n#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ\n#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET\n#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET\n#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL\n#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL\n#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET\n#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET\n#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD\n\n#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION\n#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION\n#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION\n#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER\n#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI\n#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE\n#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE\n#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER\n#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER\n#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE\n\n#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT\n#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT\n#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL\n#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM\n#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET\n#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE\n#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE\n#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER\n\n#define __HAL_ADC_SQR1                                   ADC_SQR1\n#define __HAL_ADC_SMPR1                                  ADC_SMPR1\n#define __HAL_ADC_SMPR2                                  ADC_SMPR2\n#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK\n#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK\n#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK\n#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS\n#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS\n#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV\n#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection\n#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq\n#define __HAL_ADC_JSQR                                   ADC_JSQR\n\n#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL\n#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS\n#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF\n#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT\n#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS\n#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN\n#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR\n#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT\n#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT\n#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT\n#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1\n#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1\n#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2\n#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2\n#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3\n#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3\n#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4\n#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4\n#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5\n#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5\n#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6\n#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6\n#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7\n#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7\n#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8\n#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8\n\n#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9\n#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9\n#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10\n#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10\n#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11\n#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11\n#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12\n#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12\n#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13\n#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13\n#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14\n#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14\n#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2\n#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2\n\n\n#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15\n#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15\n#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16\n#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16\n#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17\n#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17\n#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC\n#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC\n#if defined(STM32H7)\n#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1\n#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1\n#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1\n#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1\n#else\n#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG\n#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG\n#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG\n#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG\n#endif /* STM32H7 */\n#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT\n#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT\n#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT\n#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT\n#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT\n#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT\n#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1\n#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1\n#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1\n#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1\n#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2\n#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#if defined(STM32F3)\n#define COMP_START                                       __HAL_COMP_ENABLE\n#define COMP_STOP                                        __HAL_COMP_DISABLE\n#define COMP_LOCK                                        __HAL_COMP_LOCK\n\n#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\n# endif\n# if defined(STM32F302xE) || defined(STM32F302xC)\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\n                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\n                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\n                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\n                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())\n# endif\n# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \\\n                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \\\n                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \\\n                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \\\n                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \\\n                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \\\n                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())\n# endif\n# if defined(STM32F373xC) ||defined(STM32F378xx)\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\n# endif\n#else\n#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())\n#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \\\n                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())\n#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \\\n                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())\n#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \\\n                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())\n#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \\\n                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())\n#endif\n\n#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE\n\n#if defined(STM32L0) || defined(STM32L4)\n/* Note: On these STM32 families, the only argument of this macro             */\n/*       is COMP_FLAG_LOCK.                                                   */\n/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */\n/*       argument.                                                            */\n#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))\n#endif\n/**\n  * @}\n  */\n\n#if defined(STM32L0) || defined(STM32L4)\n/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\n#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */\n/**\n  * @}\n  */\n#endif\n\n/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \\\n                           ((WAVE) == DAC_WAVE_NOISE)|| \\\n                           ((WAVE) == DAC_WAVE_TRIANGLE))\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define IS_WRPAREA          IS_OB_WRPAREA\n#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM\n#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM\n#define IS_TYPEERASE        IS_FLASH_TYPEERASE\n#define IS_NBSECTORS        IS_FLASH_NBSECTORS\n#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2\n#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START\n#if defined(STM32F1)\n#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE\n#else\n#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE\n#endif /* STM32F1 */\n#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME\n#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD\n#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST\n#define __HAL_I2C_SPEED                 I2C_SPEED\n#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE\n#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ\n#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS\n#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE\n#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ\n#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB\n#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB\n#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE\n#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT\n\n#if defined(STM32H7)\n#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE\n#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE\n\n#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE\n#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION\n#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE\n#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION\n\n#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE\n\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS\n#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT\n#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT\n#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD\n#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX\n#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX\n#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX\n#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX\n#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L\n#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H\n#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM\n#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES\n#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX\n#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT\n#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION\n#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT\n#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\n#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\n#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\n#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE\n#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE\n#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE\n#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE\n#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE\n#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine\n#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig\n#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig\n#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)\n#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT\n#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE\n#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE\n#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\n#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE\n#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)\n#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention\n#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention\n#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2\n#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2\n#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE\n#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB\n#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB\n\n#if defined (STM32F4)\n#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()\n#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()\n#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()\n#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()\n#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()\n#else\n#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG\n#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT\n#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT\n#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT\n#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG\n#endif /* STM32F4 */\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose\n  * @{\n  */\n\n#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI\n#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI\n\n#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback\n#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\\\n                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())\n\n#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE\n#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE\n#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE\n#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE\n#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET\n#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET\n#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE\n#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE\n#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET\n#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET\n#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE\n#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE\n#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE\n#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE\n#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET\n#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET\n#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE\n#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE\n#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET\n#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET\n#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE\n#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE\n#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE\n#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE\n#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET\n#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET\n#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE\n#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE\n#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE\n#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE\n#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET\n#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET\n#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE\n#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE\n#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET\n#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET\n#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET\n#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET\n#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET\n#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET\n#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET\n#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET\n#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET\n#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET\n#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET\n#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET\n#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET\n#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET\n#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE\n#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE\n#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET\n#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET\n#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE\n#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE\n#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE\n#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE\n#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET\n#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET\n#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE\n#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE\n#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET\n#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET\n#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE\n#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE\n#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET\n#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET\n#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE\n#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE\n#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE\n#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE\n#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET\n#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET\n#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE\n#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE\n#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET\n#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET\n#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE\n#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE\n#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE\n#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE\n#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET\n#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET\n#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE\n#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE\n#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET\n#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET\n#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE\n#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE\n#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE\n#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE\n#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET\n#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET\n#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE\n#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE\n#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET\n#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET\n#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE\n#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE\n#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE\n#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE\n#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET\n#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET\n#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE\n#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE\n#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE\n#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE\n#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET\n#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET\n#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE\n#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE\n#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE\n#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE\n#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET\n#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET\n#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE\n#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE\n#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET\n#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET\n#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE\n#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE\n#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE\n#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE\n#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE\n#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE\n#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE\n#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE\n#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE\n#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE\n#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET\n#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET\n#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE\n#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE\n#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET\n#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET\n#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE\n#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE\n#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE\n#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE\n#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE\n#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE\n#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET\n#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET\n#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE\n#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE\n#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE\n#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE\n#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE\n#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE\n#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET\n#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET\n#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE\n#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE\n#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE\n#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE\n#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET\n#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET\n#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE\n#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE\n#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE\n#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE\n#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET\n#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET\n#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE\n#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE\n#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE\n#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE\n#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET\n#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET\n#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE\n#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE\n#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE\n#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE\n#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET\n#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET\n#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE\n#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE\n#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE\n#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE\n#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET\n#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET\n#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE\n#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE\n#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE\n#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE\n#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET\n#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET\n#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE\n#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE\n#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE\n#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE\n#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET\n#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET\n#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE\n#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE\n#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE\n#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE\n#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET\n#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET\n#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE\n#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE\n#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE\n#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE\n#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET\n#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET\n#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE\n#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE\n#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE\n#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE\n#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET\n#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET\n#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE\n#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE\n#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE\n#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE\n#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET\n#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET\n#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE\n#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE\n#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE\n#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE\n#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET\n#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET\n#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE\n#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE\n#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE\n#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE\n#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET\n#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET\n#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE\n#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE\n#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE\n#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE\n#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET\n#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET\n#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE\n#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE\n#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE\n#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE\n#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET\n#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET\n#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE\n#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE\n#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE\n#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE\n#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET\n#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET\n#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE\n#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE\n#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE\n#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE\n#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET\n#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET\n#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE\n#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE\n#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE\n#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE\n#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET\n#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET\n\n#if defined(STM32WB)\n#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE\n#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE\n#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET\n#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET\n#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED\n#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED\n#define QSPI_IRQHandler QUADSPI_IRQHandler\n#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */\n\n#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE\n#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE\n#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE\n#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE\n#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET\n#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET\n#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE\n#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE\n#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE\n#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE\n#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET\n#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET\n#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE\n#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE\n#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE\n#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE\n#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET\n#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET\n#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE\n#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE\n#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE\n#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE\n#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE\n#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE\n#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET\n#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET\n#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE\n#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE\n#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE\n#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE\n#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET\n#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET\n#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE\n#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE\n#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE\n#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE\n#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET\n#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET\n#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE\n#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE\n#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE\n#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE\n#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET\n#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET\n#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE\n#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE\n#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE\n#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE\n#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE\n#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE\n#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE\n#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE\n#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE\n#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE\n#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET\n#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET\n#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE\n#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE\n#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE\n#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE\n#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET\n#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET\n#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE\n#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE\n#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE\n#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE\n#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET\n#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET\n#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE\n#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE\n#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET\n#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET\n#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE\n#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE\n#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET\n#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET\n#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE\n#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE\n#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET\n#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET\n#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE\n#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE\n#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET\n#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET\n#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE\n#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE\n#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET\n#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET\n#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE\n#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE\n#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE\n#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE\n#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET\n#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET\n#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE\n#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE\n#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE\n#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE\n#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET\n#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET\n#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE\n#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE\n#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE\n#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE\n#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET\n#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET\n#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE\n#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE\n#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE\n#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE\n#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET\n#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET\n#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE\n#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE\n#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE\n#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE\n#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET\n#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET\n#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE\n#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE\n#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE\n#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE\n#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET\n#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET\n#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE\n#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE\n#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE\n#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE\n#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET\n#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET\n#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE\n#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE\n#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE\n#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE\n#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET\n#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET\n#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE\n#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE\n#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE\n#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE\n#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET\n#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET\n#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE\n#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE\n#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE\n#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE\n#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET\n#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET\n#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE\n#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE\n#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET\n#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET\n#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE\n#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE\n#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE\n#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE\n#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET\n#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET\n#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE\n#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE\n#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE\n#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE\n#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET\n#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET\n#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE\n#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE\n#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE\n#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE\n#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET\n#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET\n#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE\n#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE\n#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE\n#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE\n#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET\n#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET\n#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE\n#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE\n#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE\n#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE\n#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET\n#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET\n#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE\n#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE\n#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE\n#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE\n#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET\n#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET\n#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE\n#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE\n#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE\n#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE\n#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET\n#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET\n#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE\n#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE\n#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE\n#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE\n#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET\n#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET\n#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE\n#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE\n#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET\n#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET\n#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE\n#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE\n#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET\n#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET\n#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE\n#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE\n#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET\n#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE\n#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE\n#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE\n#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE\n#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET\n\n#if defined(STM32H7)\n#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE\n#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE\n#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE\n#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE\n\n#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/\n#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/\n\n\n#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED\n#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED\n#endif\n\n#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE\n#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE\n#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE\n#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE\n#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET\n#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET\n\n#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE\n#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE\n#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET\n#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET\n#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE\n#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE\n#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE\n#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE\n#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET\n#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET\n#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE\n#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE\n#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE\n#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE\n#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE\n#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE\n#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET\n#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET\n#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE\n#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE\n\n#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET\n#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\n#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE\n#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE\n#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE\n#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE\n#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE\n#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE\n#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE\n#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE\n#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE\n#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE\n#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE\n#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE\n#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE\n#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE\n#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE\n#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE\n#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE\n#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET\n#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET\n#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE\n#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE\n#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE\n#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE\n#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE\n#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET\n#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET\n#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE\n#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE\n#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE\n#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE\n#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET\n#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET\n#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE\n#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE\n#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE\n#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE\n#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET\n#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET\n#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE\n#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE\n#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE\n#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE\n#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE\n#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE\n#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE\n#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE\n#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE\n#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE\n#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE\n#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE\n#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE\n#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE\n#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE\n#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE\n#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE\n#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE\n#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE\n#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE\n#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE\n#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET\n#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET\n#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE\n#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE\n#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE\n#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE\n#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET\n#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET\n#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE\n#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE\n#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE\n#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE\n#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET\n#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET\n#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE\n#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE\n#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE\n#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE\n#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET\n#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET\n#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE\n#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE\n#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE\n#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE\n#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET\n#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE\n#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE\n#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE\n#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE\n#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE\n#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE\n#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET\n#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET\n#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE\n#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE\n#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE\n#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE\n#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET\n#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET\n#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE\n#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE\n#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE\n#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE\n#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET\n#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET\n#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE\n#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE\n#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\n#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\n#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\n#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\n#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\n#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\n#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE\n#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED\n#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED\n#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET\n#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE\n#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED\n#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED\n#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE\n#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE\n#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE\n#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE\n#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE\n#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE\n#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE\n#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE\n#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE\n#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET\n#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET\n#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE\n#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE\n#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET\n#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET\n#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\n#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\n#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE\n#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE\n#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET\n#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET\n#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE\n#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE\n\n/* alias define maintained for legacy */\n#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET\n#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET\n\n#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE\n#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE\n#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE\n#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE\n#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE\n#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE\n#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE\n#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE\n#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE\n#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE\n#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE\n#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE\n#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE\n#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE\n#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE\n#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE\n#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE\n#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE\n#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE\n#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE\n\n#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET\n#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET\n#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET\n#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET\n#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET\n#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET\n#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET\n#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET\n#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET\n#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET\n#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET\n#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET\n#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET\n#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET\n#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET\n#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET\n#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET\n#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET\n#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET\n#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET\n\n#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED\n#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED\n#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED\n#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED\n#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED\n#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED\n#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED\n#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED\n#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED\n#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED\n#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED\n#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED\n#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED\n#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED\n#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED\n#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED\n#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED\n#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED\n#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED\n#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED\n#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED\n#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED\n#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED\n#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED\n#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED\n#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED\n#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED\n#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED\n#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED\n#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED\n#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED\n#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED\n#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED\n#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED\n#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED\n#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED\n#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED\n#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED\n#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED\n#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED\n#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED\n#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED\n#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED\n#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED\n#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED\n#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED\n#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED\n#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED\n#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED\n#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED\n#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED\n#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED\n#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED\n#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED\n#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED\n#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED\n#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED\n#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED\n#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED\n#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED\n#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED\n#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED\n#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED\n#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED\n#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED\n#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED\n#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED\n#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED\n#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED\n#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED\n#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED\n#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED\n#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED\n#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED\n#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED\n#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED\n#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED\n#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED\n#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED\n#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED\n#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED\n#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED\n#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED\n#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED\n#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED\n#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED\n#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED\n#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED\n#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED\n#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED\n#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED\n#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED\n#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED\n#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED\n#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED\n#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED\n#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED\n#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED\n#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED\n#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED\n#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED\n#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED\n#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED\n#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED\n#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED\n#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED\n#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED\n#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED\n#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED\n#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED\n#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED\n#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED\n#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED\n#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED\n#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED\n#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED\n\n#if defined(STM32L1)\n#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE\n#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE\n#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE\n#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE\n#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET\n#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET\n#endif /* STM32L1 */\n\n#if defined(STM32F4)\n#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET\n#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE\n#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE\n#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE\n#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE\n#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED\n#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED\n#define Sdmmc1ClockSelection               SdioClockSelection\n#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO\n#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48\n#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK\n#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG\n#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE\n#endif\n\n#if defined(STM32F7) || defined(STM32L4)\n#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET\n#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE\n#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE\n#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED\n#define SdioClockSelection                 Sdmmc1ClockSelection\n#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1\n#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG\n#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE\n#endif\n\n#if defined(STM32F7)\n#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48\n#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK\n#endif\n\n#if defined(STM32H7)\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()\n\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()\n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()\n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()\n#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()\n#endif\n\n#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG\n#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG\n\n#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE\n\n#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE\n#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE\n#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK\n#define IS_RCC_HCLK_DIV             IS_RCC_PCLK\n#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK\n\n#define RCC_IT_HSI14                RCC_IT_HSI14RDY\n\n#define RCC_IT_CSSLSE               RCC_IT_LSECSS\n#define RCC_IT_CSSHSE               RCC_IT_CSS\n\n#define RCC_PLLMUL_3                RCC_PLL_MUL3\n#define RCC_PLLMUL_4                RCC_PLL_MUL4\n#define RCC_PLLMUL_6                RCC_PLL_MUL6\n#define RCC_PLLMUL_8                RCC_PLL_MUL8\n#define RCC_PLLMUL_12               RCC_PLL_MUL12\n#define RCC_PLLMUL_16               RCC_PLL_MUL16\n#define RCC_PLLMUL_24               RCC_PLL_MUL24\n#define RCC_PLLMUL_32               RCC_PLL_MUL32\n#define RCC_PLLMUL_48               RCC_PLL_MUL48\n\n#define RCC_PLLDIV_2                RCC_PLL_DIV2\n#define RCC_PLLDIV_3                RCC_PLL_DIV3\n#define RCC_PLLDIV_4                RCC_PLL_DIV4\n\n#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE\n#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG\n#define RCC_MCO_NODIV               RCC_MCODIV_1\n#define RCC_MCO_DIV1                RCC_MCODIV_1\n#define RCC_MCO_DIV2                RCC_MCODIV_2\n#define RCC_MCO_DIV4                RCC_MCODIV_4\n#define RCC_MCO_DIV8                RCC_MCODIV_8\n#define RCC_MCO_DIV16               RCC_MCODIV_16\n#define RCC_MCO_DIV32               RCC_MCODIV_32\n#define RCC_MCO_DIV64               RCC_MCODIV_64\n#define RCC_MCO_DIV128              RCC_MCODIV_128\n#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK\n#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI\n#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE\n#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK\n#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI\n#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14\n#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48\n#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE\n#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK\n#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK\n#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2\n\n#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)\n#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE\n#else\n#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK\n#endif\n\n#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1\n#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL\n#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI\n#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL\n#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL\n#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5\n#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2\n#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3\n\n#define HSION_BitNumber        RCC_HSION_BIT_NUMBER\n#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER\n#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER\n#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER\n#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER\n#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER\n#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER\n#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER\n#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER\n#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER\n#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER\n#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER\n#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER\n#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER\n#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER\n#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER\n#define LSION_BitNumber        RCC_LSION_BIT_NUMBER\n#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER\n#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER\n#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER\n#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER\n#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER\n#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER\n#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER\n#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER\n#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER\n#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS\n#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS\n#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS\n#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS\n#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE\n#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE\n\n#define CR_HSION_BB            RCC_CR_HSION_BB\n#define CR_CSSON_BB            RCC_CR_CSSON_BB\n#define CR_PLLON_BB            RCC_CR_PLLON_BB\n#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB\n#define CR_MSION_BB            RCC_CR_MSION_BB\n#define CSR_LSION_BB           RCC_CSR_LSION_BB\n#define CSR_LSEON_BB           RCC_CSR_LSEON_BB\n#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB\n#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB\n#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB\n#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB\n#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB\n#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB\n#define CR_HSEON_BB            RCC_CR_HSEON_BB\n#define CSR_RMVF_BB            RCC_CSR_RMVF_BB\n#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB\n#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB\n\n#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE\n#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE\n#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE\n#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE\n#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE\n\n#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT\n\n#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN\n#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF\n\n#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48\n#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ\n#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP\n#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ\n#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE\n#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48\n\n#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE\n#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE\n#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED\n#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED\n#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET\n#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET\n#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE\n#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED\n#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED\n#define DfsdmClockSelection         Dfsdm1ClockSelection\n#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1\n#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2\n#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK\n#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG\n#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE\n#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2\n#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1\n#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1\n#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1\n\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2\n#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2\n#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2\n#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)\n#else\n#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG\n#endif\n#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT\n#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT\n\n#if defined (STM32F1)\n#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()\n\n#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()\n\n#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()\n\n#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()\n\n#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()\n#else\n#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \\\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \\\n                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))\n#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \\\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \\\n                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))\n#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \\\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \\\n                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))\n#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \\\n                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \\\n                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))\n#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \\\n                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \\\n                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))\n#endif   /* STM32F1 */\n\n#define IS_ALARM                                  IS_RTC_ALARM\n#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK\n#define IS_TAMPER                                 IS_RTC_TAMPER\n#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE\n#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER\n#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT\n#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE\n#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION\n#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE\n#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ\n#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION\n#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER\n#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK\n#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER\n\n#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE\n#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE\n#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS\n\n#if defined(STM32F4) || defined(STM32F2)\n#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED\n#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY\n#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED\n#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION\n#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND\n#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT\n#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED\n#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE\n#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE\n#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE\n#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL\n#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT\n#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT\n#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG\n#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG\n#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT\n#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT\n#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS\n#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT\n#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND\n/* alias CMSIS */\n#define  SDMMC1_IRQn                SDIO_IRQn\n#define  SDMMC1_IRQHandler          SDIO_IRQHandler\n#endif\n\n#if defined(STM32F7) || defined(STM32L4)\n#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED\n#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY\n#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED\n#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION\n#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND\n#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT\n#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED\n#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE\n#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE\n#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE\n#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE\n#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT\n#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT\n#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG\n#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG\n#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT\n#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT\n#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS\n#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT\n#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND\n/* alias CMSIS for compatibilities */\n#define  SDIO_IRQn                  SDMMC1_IRQn\n#define  SDIO_IRQHandler            SDMMC1_IRQHandler\n#endif\n\n#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)\n#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef\n#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef\n#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef\n#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef\n#endif\n\n#if defined(STM32H7) || defined(STM32L5)\n#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback\n#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback\n#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback\n#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback\n#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback\n#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback\n#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback\n#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback\n#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT\n#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT\n#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE\n#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE\n#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE\n#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE\n\n#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE\n#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE\n\n#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1\n#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2\n#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START\n#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH\n#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR\n#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE\n#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE\n#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX\n#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX\n#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE\n#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION\n#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE\n#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION\n\n#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD\n\n#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE\n#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE\n\n/**\n  * @}\n  */\n\n\n/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT\n#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT\n#define __USART_ENABLE                  __HAL_USART_ENABLE\n#define __USART_DISABLE                 __HAL_USART_DISABLE\n\n#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE\n#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE\n\n#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)\n#define USART_OVERSAMPLING_16               0x00000000U\n#define USART_OVERSAMPLING_8                USART_CR1_OVER8\n\n#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \\\n                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))\n#endif /* STM32F0 || STM32F3 || STM32F7 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE\n\n#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE\n#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE\n#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE\n#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE\n\n#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE\n#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE\n#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE\n#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE\n\n#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT\n#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT\n#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG\n#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG\n#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE\n#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\n\n#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT\n#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT\n#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG\n#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG\n#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE\n#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\n#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT\n\n#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT\n#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT\n#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG\n#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG\n#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE\n#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE\n#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE\n#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT\n\n#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup\n#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup\n\n#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo\n#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo\n/**\n  * @}\n  */\n\n/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE\n#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE\n\n#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE\n#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT\n\n#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE\n\n#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN\n#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER\n#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER\n#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER\n#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD\n#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD\n#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION\n#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION\n#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER\n#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER\n#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE\n#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE\n\n#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1\n/**\n  * @}\n  */\n\n/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT\n#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT\n#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG\n#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG\n#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER\n#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER\n#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER\n\n#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE\n#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE\n#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define __HAL_LTDC_LAYER LTDC_LAYER\n#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE\n#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE\n#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE\n#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE\n#define SAI_STREOMODE                     SAI_STEREOMODE\n#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY\n#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL\n#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL\n#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL\n#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL\n#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL\n#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE\n#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1\n#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE\n/**\n  * @}\n  */\n\n/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#if defined(STM32H7)\n#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow\n#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT\n#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose\n  * @{\n  */\n#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)\n#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT\n#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA\n#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart\n#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT\n#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA\n#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose\n  * @{\n  */\n#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)\n#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE\n#endif /* STM32L4 || STM32F4 || STM32F7 */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32_HAL_LEGACY */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal.h\n  * @author  MCD Application Team\n  * @brief   This file contains all the functions prototypes for the HAL \n  *          module driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_H\n#define __STM32F4xx_HAL_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_conf.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup HAL\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup HAL_Exported_Constants HAL Exported Constants\n  * @{\n  */\n\n/** @defgroup HAL_TICK_FREQ Tick Frequency\n  * @{\n  */\ntypedef enum\n{\n  HAL_TICK_FREQ_10HZ         = 100U,\n  HAL_TICK_FREQ_100HZ        = 10U,\n  HAL_TICK_FREQ_1KHZ         = 1U,\n  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ\n} HAL_TickFreqTypeDef;\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n   \n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup HAL_Exported_Macros HAL Exported Macros\n  * @{\n  */\n\n/** @brief  Freeze/Unfreeze Peripherals in Debug mode \n  */\n#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))\n#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))\n#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))\n#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))\n#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))\n#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))\n#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))\n\n#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))\n#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))\n#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))\n#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))\n#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))\n#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))\n#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))\n#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))\n\n/** @brief  Main Flash memory mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))\n\n/** @brief  System Flash memory mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\\\n                                                        }while(0);\n\n/** @brief  Embedded SRAM mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                 }while(0);\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\n/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                 }while(0);\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\\\n                                                }while(0);\n\n/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000\n  */\n#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\\\n                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\\\n                                                      }while(0);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ \n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable\n  * @{\n  */\n/** @brief  SYSCFG Break Lockup lock\n  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input\n  * @note   The selected configuration is locked and can be unlocked by system reset\n  */\n#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \\\n                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \\\n                                              }while(0)\n/**\n * @}\n */\n\n/** @defgroup PVD_Lock_Enable PVD Lock\n  * @{\n  */\n/** @brief  SYSCFG Break PVD lock\n  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register\n  * @note   The selected configuration is locked and can be unlocked by system reset\n  */\n#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \\\n                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \\\n                                                }while(0)\n/**\n * @}\n */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/** @defgroup HAL_Private_Macros HAL Private Macros\n  * @{\n  */\n#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \\\n                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \\\n                           ((FREQ) == HAL_TICK_FREQ_1KHZ))\n/**\n  * @}\n  */\n\n/* Exported variables --------------------------------------------------------*/\n\n/** @addtogroup HAL_Exported_Variables\n  * @{\n  */\nextern __IO uint32_t uwTick;\nextern uint32_t uwTickPrio;\nextern HAL_TickFreqTypeDef uwTickFreq;\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup HAL_Exported_Functions\n  * @{\n  */\n/** @addtogroup HAL_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization and Configuration functions  ******************************/\nHAL_StatusTypeDef HAL_Init(void);\nHAL_StatusTypeDef HAL_DeInit(void);\nvoid HAL_MspInit(void);\nvoid HAL_MspDeInit(void);\nHAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);\n/**\n  * @}\n  */\n\n/** @addtogroup HAL_Exported_Functions_Group2\n  * @{\n  */\n/* Peripheral Control functions  ************************************************/\nvoid HAL_IncTick(void);\nvoid HAL_Delay(uint32_t Delay);\nuint32_t HAL_GetTick(void);\nuint32_t HAL_GetTickPrio(void);\nHAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);\nHAL_TickFreqTypeDef HAL_GetTickFreq(void);\nvoid HAL_SuspendTick(void);\nvoid HAL_ResumeTick(void);\nuint32_t HAL_GetHalVersion(void);\nuint32_t HAL_GetREVID(void);\nuint32_t HAL_GetDEVID(void);\nvoid HAL_DBGMCU_EnableDBGSleepMode(void);\nvoid HAL_DBGMCU_DisableDBGSleepMode(void);\nvoid HAL_DBGMCU_EnableDBGStopMode(void);\nvoid HAL_DBGMCU_DisableDBGStopMode(void);\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void);\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void);\nvoid HAL_EnableCompensationCell(void);\nvoid HAL_DisableCompensationCell(void);\nuint32_t HAL_GetUIDw0(void);\nuint32_t HAL_GetUIDw1(void);\nuint32_t HAL_GetUIDw2(void);\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\nvoid HAL_EnableMemorySwappingBank(void);\nvoid HAL_DisableMemorySwappingBank(void);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ \n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup HAL_Private_Variables HAL Private Variables\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup HAL_Private_Constants HAL Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n  \n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_adc.h\n  * @author  MCD Application Team\n  * @brief   Header file containing functions prototypes of ADC HAL library.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_ADC_H\n#define __STM32F4xx_ADC_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/* Include low level driver */\n#include \"stm32f4xx_ll_adc.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup ADC\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup ADC_Exported_Types ADC Exported Types\n  * @{\n  */\n\n/** \n  * @brief  Structure definition of ADC and regular group initialization \n  * @note   Parameters of this structure are shared within 2 scopes:\n  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.\n  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.\n  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.\n  *         ADC state can be either:\n  *          - For all parameters: ADC disabled\n  *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.\n  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.\n  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed\n  *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).\n  */\ntypedef struct\n{\n  uint32_t ClockPrescaler;               /*!< Select ADC clock prescaler. The clock is common for \n                                              all the ADCs.\n                                              This parameter can be a value of @ref ADC_ClockPrescaler */\n  uint32_t Resolution;                   /*!< Configures the ADC resolution.\n                                              This parameter can be a value of @ref ADC_Resolution */\n  uint32_t DataAlign;                    /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)\n                                              or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).\n                                              This parameter can be a value of @ref ADC_Data_align */\n  uint32_t ScanConvMode;                 /*!< Configures the sequencer of regular and injected groups.\n                                              This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.\n                                              If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).\n                                                           Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).\n                                              If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).\n                                                           Scan direction is upward: from rank1 to rank 'n'.\n                                              This parameter can be set to ENABLE or DISABLE */\n  uint32_t EOCSelection;                 /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.\n                                              This parameter can be a value of @ref ADC_EOCSelection.\n                                              Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.\n                                                    Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)\n                                                    or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.\n                                              Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).\n                                                    If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */\n  FunctionalState ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,\n                                              after the selected trigger occurred (software start or external trigger).\n                                              This parameter can be set to ENABLE or DISABLE. */\n  uint32_t NbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the regular group sequencer.\n                                              To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\n                                              This parameter must be a number between Min_Data = 1 and Max_Data = 16. */\n  FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\n                                              Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\n                                              Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\n                                              This parameter can be set to ENABLE or DISABLE. */\n  uint32_t NbrOfDiscConversion;          /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.\n                                              If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.\n                                              This parameter must be a number between Min_Data = 1 and Max_Data = 8. */\n  uint32_t ExternalTrigConv;             /*!< Selects the external event used to trigger the conversion start of regular group.\n                                              If set to ADC_SOFTWARE_START, external triggers are disabled.\n                                              If set to external trigger source, triggering is on event rising edge by default.\n                                              This parameter can be a value of @ref ADC_External_trigger_Source_Regular */\n  uint32_t ExternalTrigConvEdge;         /*!< Selects the external trigger edge of regular group.\n                                              If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.\n                                              This parameter can be a value of @ref ADC_External_trigger_edge_Regular */\n  FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)\n\t\t\t\t\t\t\t\t\t\t\t  or in Continuous mode (DMA transfer unlimited, whatever number of conversions).\n\t\t\t\t\t\t\t\t\t\t\t  Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.\n\t\t\t\t\t\t\t\t\t\t\t  Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).\n\t\t\t\t\t\t\t\t\t\t\t  This parameter can be set to ENABLE or DISABLE. */\n}ADC_InitTypeDef;\n\n\n\n/** \n  * @brief  Structure definition of ADC channel for regular group   \n  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.\n  *         ADC can be either disabled or enabled without conversion on going on regular group.\n  */ \ntypedef struct \n{\n  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.\n                                        This parameter can be a value of @ref ADC_channels */\n  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.\n                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16 */\n  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.\n                                        Unit: ADC clock cycles\n                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\n                                        This parameter can be a value of @ref ADC_sampling_times\n                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\n                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\n                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\n                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\n                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\n  uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */\n}ADC_ChannelConfTypeDef;\n\n/** \n  * @brief ADC Configuration multi-mode structure definition  \n  */ \ntypedef struct\n{\n  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.\n                                   This parameter can be a value of @ref ADC_analog_watchdog_selection */\n  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.\n                                   This parameter must be a 12-bit value. */     \n  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.\n                                   This parameter must be a 12-bit value. */\n  uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog. \n                                   This parameter has an effect only if watchdog mode is configured on single channel \n                                   This parameter can be a value of @ref ADC_channels */      \n  FunctionalState ITMode;     /*!< Specifies whether the analog watchdog is configured\n                                   is interrupt mode or in polling mode.\n                                   This parameter can be set to ENABLE or DISABLE */\n  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */\n}ADC_AnalogWDGConfTypeDef;\n\n/** \n  * @brief  HAL ADC state machine: ADC states definition (bitfields)\n  */ \n/* States of ADC global scope */\n#define HAL_ADC_STATE_RESET             0x00000000U    /*!< ADC not yet initialized or disabled */\n#define HAL_ADC_STATE_READY             0x00000001U    /*!< ADC peripheral ready for use */\n#define HAL_ADC_STATE_BUSY_INTERNAL     0x00000002U    /*!< ADC is busy to internal process (initialization, calibration) */\n#define HAL_ADC_STATE_TIMEOUT           0x00000004U    /*!< TimeOut occurrence */\n\n/* States of ADC errors */\n#define HAL_ADC_STATE_ERROR_INTERNAL    0x00000010U    /*!< Internal error occurrence */\n#define HAL_ADC_STATE_ERROR_CONFIG      0x00000020U    /*!< Configuration error occurrence */\n#define HAL_ADC_STATE_ERROR_DMA         0x00000040U    /*!< DMA error occurrence */\n\n/* States of ADC group regular */\n#define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,\n                                                            external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\n#define HAL_ADC_STATE_REG_EOC           0x00000200U    /*!< Conversion data available on group regular */\n#define HAL_ADC_STATE_REG_OVR           0x00000400U    /*!< Overrun occurrence */\n\n/* States of ADC group injected */\n#define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,\n                                                            external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */\n#define HAL_ADC_STATE_INJ_EOC           0x00002000U    /*!< Conversion data available on group injected */\n\n/* States of ADC analog watchdogs */\n#define HAL_ADC_STATE_AWD1              0x00010000U    /*!< Out-of-window occurrence of analog watchdog 1 */\n#define HAL_ADC_STATE_AWD2              0x00020000U    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */\n#define HAL_ADC_STATE_AWD3              0x00040000U    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */\n\n/* States of ADC multi-mode */\n#define HAL_ADC_STATE_MULTIMODE_SLAVE   0x00100000U    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */\n\n\n/** \n  * @brief  ADC handle Structure definition\n  */ \n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\ntypedef struct __ADC_HandleTypeDef\n#else\ntypedef struct\n#endif\n{\n  ADC_TypeDef                   *Instance;                   /*!< Register base address */\n\n  ADC_InitTypeDef               Init;                        /*!< ADC required parameters */\n\n  __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */\n\n  DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */\n\n  HAL_LockTypeDef               Lock;                        /*!< ADC locking object */\n\n  __IO uint32_t                 State;                       /*!< ADC communication state */\n\n  __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */\n  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */\n  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */\n  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */\n  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */\n  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */\n  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n}ADC_HandleTypeDef;\n\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  HAL ADC Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */\n  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */\n  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */\n  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */\n  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */\n  HAL_ADC_MSPINIT_CB_ID                 = 0x05U,  /*!< ADC Msp Init callback ID          */\n  HAL_ADC_MSPDEINIT_CB_ID               = 0x06U   /*!< ADC Msp DeInit callback ID        */\n} HAL_ADC_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL ADC Callback pointer definition\n  */\ntypedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */\n\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup ADC_Exported_Constants ADC Exported Constants\n  * @{\n  */\n\n/** @defgroup ADC_Error_Code ADC Error Code\n  * @{\n  */\n#define HAL_ADC_ERROR_NONE        0x00U   /*!< No error                                              */\n#define HAL_ADC_ERROR_INTERNAL    0x01U   /*!< ADC IP internal error: if problem of clocking, \n                                               enable/disable, erroneous state                       */\n#define HAL_ADC_ERROR_OVR         0x02U   /*!< Overrun error                                         */\n#define HAL_ADC_ERROR_DMA         0x04U   /*!< DMA transfer error                                    */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n\n/** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler\n  * @{\n  */ \n#define ADC_CLOCK_SYNC_PCLK_DIV2    0x00000000U\n#define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)\n#define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)\n#define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases\n  * @{\n  */ \n#define ADC_TWOSAMPLINGDELAY_5CYCLES    0x00000000U\n#define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)\n#define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)\n#define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)\n#define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\n#define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)\n#define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))\n#define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))\n#define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))\n#define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))\n#define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_Resolution ADC Resolution\n  * @{\n  */ \n#define ADC_RESOLUTION_12B  0x00000000U\n#define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)\n#define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)\n#define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular\n  * @{\n  */ \n#define ADC_EXTERNALTRIGCONVEDGE_NONE           0x00000000U\n#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)\n#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)\n#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular\n  * @{\n  */\n/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */\n/*       compatibility with other STM32 devices.                              */\n#define ADC_EXTERNALTRIGCONV_T1_CC1    0x00000000U\n#define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)\n#define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)\n#define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)\n#define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))\n#define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)\n#define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))\n#define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))\n#define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))\n#define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))\n#define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)\n#define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_Data_align ADC Data Align\n  * @{\n  */ \n#define ADC_DATAALIGN_RIGHT      0x00000000U\n#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_channels  ADC Common Channels\n  * @{\n  */ \n#define ADC_CHANNEL_0           0x00000000U\n#define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)\n#define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)\n#define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\n#define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)\n#define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))\n#define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))\n#define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))\n#define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)\n#define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))\n#define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))\n\n#define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)\n#define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_sampling_times  ADC Sampling Times\n  * @{\n  */ \n#define ADC_SAMPLETIME_3CYCLES    0x00000000U\n#define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)\n#define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)\n#define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))\n#define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)\n#define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))\n#define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))\n#define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)\n/**\n  * @}\n  */ \n\n  /** @defgroup ADC_EOCSelection ADC EOC Selection\n  * @{\n  */ \n#define ADC_EOC_SEQ_CONV              0x00000000U\n#define ADC_EOC_SINGLE_CONV           0x00000001U\n#define ADC_EOC_SINGLE_SEQ_CONV       0x00000002U  /*!< reserved for future use */\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_Event_type ADC Event Type\n  * @{\n  */ \n#define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)\n#define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)\n/**\n  * @}\n  */\n\n/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection\n  * @{\n  */ \n#define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))\n#define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))\n#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\n#define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)\n#define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)\n#define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))\n#define ADC_ANALOGWATCHDOG_NONE               0x00000000U\n/**\n  * @}\n  */ \n    \n/** @defgroup ADC_interrupts_definition ADC Interrupts Definition\n  * @{\n  */ \n#define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)\n#define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)\n#define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)\n#define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)\n/**\n  * @}\n  */ \n    \n/** @defgroup ADC_flags_definition ADC Flags Definition\n  * @{\n  */ \n#define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)\n#define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)\n#define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)\n#define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)\n#define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)\n#define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)\n/**\n  * @}\n  */ \n\n/** @defgroup ADC_channels_type ADC Channels Type\n  * @{\n  */ \n#define ADC_ALL_CHANNELS      0x00000001U\n#define ADC_REGULAR_CHANNELS  0x00000002U /*!< reserved for future use */\n#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\n  * @{\n  */\n\n/** @brief Reset ADC handle state\n  * @param  __HANDLE__ ADC handle\n  * @retval None\n  */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \\\n  do{                                                                          \\\n     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \\\n     (__HANDLE__)->MspInitCallback = NULL;                                     \\\n     (__HANDLE__)->MspDeInitCallback = NULL;                                   \\\n    } while(0)\n#else\n#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \\\n  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)\n#endif\n\n/**\n  * @brief  Enable the ADC peripheral.\n  * @param  __HANDLE__ ADC handle\n  * @retval None\n  */\n#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)\n\n/**\n  * @brief  Disable the ADC peripheral.\n  * @param  __HANDLE__ ADC handle\n  * @retval None\n  */\n#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)\n\n/**\n  * @brief  Enable the ADC end of conversion interrupt.\n  * @param  __HANDLE__ specifies the ADC Handle.\n  * @param  __INTERRUPT__ ADC Interrupt.\n  * @retval None\n  */\n#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))\n\n/**\n  * @brief  Disable the ADC end of conversion interrupt.\n  * @param  __HANDLE__ specifies the ADC Handle.\n  * @param  __INTERRUPT__ ADC interrupt.\n  * @retval None\n  */\n#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))\n\n/** @brief  Check if the specified ADC interrupt source is enabled or disabled.\n  * @param  __HANDLE__ specifies the ADC Handle.\n  * @param  __INTERRUPT__ specifies the ADC interrupt source to check.\n  * @retval The new state of __IT__ (TRUE or FALSE).\n  */\n#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))\n\n/**\n  * @brief  Clear the ADC's pending flags.\n  * @param  __HANDLE__ specifies the ADC Handle.\n  * @param  __FLAG__ ADC flag.\n  * @retval None\n  */\n#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))\n\n/**\n  * @brief  Get the selected ADC's flag status.\n  * @param  __HANDLE__ specifies the ADC Handle.\n  * @param  __FLAG__ ADC flag.\n  * @retval None\n  */\n#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\n\n/**\n  * @}\n  */\n\n/* Include ADC HAL Extension module */\n#include \"stm32f4xx_hal_adc_ex.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup ADC_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup ADC_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization/de-initialization functions ***********************************/\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);\nvoid HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);\nvoid HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);\n\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n/* Callbacks Register/UnRegister functions  ***********************************/\nHAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @addtogroup ADC_Exported_Functions_Group2\n  * @{\n  */\n/* I/O operation functions ******************************************************/\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\n\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);\n\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);\n\nvoid HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);\n\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);\n\nuint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);\n\nvoid HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);\nvoid HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);\nvoid HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);\nvoid HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);\n/**\n  * @}\n  */\n\n/** @addtogroup ADC_Exported_Functions_Group3\n  * @{\n  */\n/* Peripheral Control functions *************************************************/\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);\n/**\n  * @}\n  */\n\n/** @addtogroup ADC_Exported_Functions_Group4\n  * @{\n  */\n/* Peripheral State functions ***************************************************/\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup ADC_Private_Constants ADC Private Constants\n  * @{\n  */\n/* Delay for ADC stabilization time.                                        */\n/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */\n/* Unit: us                                                                 */\n#define ADC_STAB_DELAY_US               3U\n/* Delay for temperature sensor stabilization time.                         */\n/* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */\n/* Unit: us                                                                 */\n#define ADC_TEMPSENSOR_DELAY_US         10U\n/**\n  * @}\n  */\n\n/* Private macro ------------------------------------------------------------*/\n\n/** @defgroup ADC_Private_Macros ADC Private Macros\n  * @{\n  */\n/* Macro reserved for internal HAL driver usage, not intended to be used in\n   code of final user */\n\n/**\n  * @brief Verification of ADC state: enabled or disabled\n  * @param __HANDLE__ ADC handle\n  * @retval SET (ADC enabled) or RESET (ADC disabled)\n  */\n#define ADC_IS_ENABLE(__HANDLE__)                                              \\\n  ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \\\n  ) ? SET : RESET)\n\n/**\n  * @brief Test if conversion trigger of regular group is software start\n  *        or external trigger.\n  * @param __HANDLE__ ADC handle\n  * @retval SET (software start) or RESET (external trigger)\n  */\n#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \\\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)\n\n/**\n  * @brief Test if conversion trigger of injected group is software start\n  *        or external trigger.\n  * @param __HANDLE__ ADC handle\n  * @retval SET (software start) or RESET (external trigger)\n  */\n#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \\\n  (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)\n\n/**\n  * @brief Simultaneously clears and sets specific bits of the handle State\n  * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),\n  *        the first parameter is the ADC handle State, the second parameter is the\n  *        bit field to clear, the third and last parameter is the bit field to set.\n  * @retval None\n  */\n#define ADC_STATE_CLR_SET MODIFY_REG\n\n/**\n  * @brief Clear ADC error code (set it to error code: \"no error\")\n  * @param __HANDLE__ ADC handle\n  * @retval None\n  */\n#define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \\\n  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)\n\n    \n#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \\\n                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \\\n                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \\\n                                              ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))\n#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \\\n                                      ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))\n#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \\\n                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \\\n                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \\\n                                       ((RESOLUTION) == ADC_RESOLUTION_6B))\n#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \\\n                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \\\n                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \\\n                                    ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))\n#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \\\n                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \\\n                                  ((REGTRIG) == ADC_SOFTWARE_START))\n#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \\\n                                  ((ALIGN) == ADC_DATAALIGN_LEFT))\n#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \\\n                                  ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \\\n                                  ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \\\n                                  ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \\\n                                  ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \\\n                                  ((TIME) == ADC_SAMPLETIME_112CYCLES) || \\\n                                  ((TIME) == ADC_SAMPLETIME_144CYCLES) || \\\n                                  ((TIME) == ADC_SAMPLETIME_480CYCLES))\n#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \\\n                                           ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \\\n                                           ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))\n#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \\\n                                  ((EVENT) == ADC_OVR_EVENT))\n#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \\\n                                          ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))\n#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \\\n                                            ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \\\n                                            ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))\n#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)\n\n#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))\n#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))\n#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))\n#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \\\n   ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \\\n    (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \\\n    (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= 0x00FFU)) || \\\n    (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= 0x003FU)))\n\n/**\n  * @brief  Set ADC Regular channel sequence length.\n  * @param  _NbrOfConversion_ Regular channel sequence length. \n  * @retval None\n  */\n#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)\n\n/**\n  * @brief  Set the ADC's sample time for channel numbers between 10 and 18.\n  * @param  _SAMPLETIME_ Sample time parameter.\n  * @param  _CHANNELNB_ Channel number.  \n  * @retval None\n  */\n#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))\n\n/**\n  * @brief  Set the ADC's sample time for channel numbers between 0 and 9.\n  * @param  _SAMPLETIME_ Sample time parameter.\n  * @param  _CHANNELNB_ Channel number.  \n  * @retval None\n  */\n#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))\n\n/**\n  * @brief  Set the selected regular channel rank for rank between 1 and 6.\n  * @param  _CHANNELNB_ Channel number.\n  * @param  _RANKNB_ Rank number.    \n  * @retval None\n  */\n#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))\n\n/**\n  * @brief  Set the selected regular channel rank for rank between 7 and 12.\n  * @param  _CHANNELNB_ Channel number.\n  * @param  _RANKNB_ Rank number.    \n  * @retval None\n  */\n#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))\n\n/**\n  * @brief  Set the selected regular channel rank for rank between 13 and 16.\n  * @param  _CHANNELNB_ Channel number.\n  * @param  _RANKNB_ Rank number.    \n  * @retval None\n  */\n#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))\n\n/**\n  * @brief  Enable ADC continuous conversion mode.\n  * @param  _CONTINUOUS_MODE_ Continuous mode.\n  * @retval None\n  */\n#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)\n\n/**\n  * @brief  Configures the number of discontinuous conversions for the regular group channels.\n  * @param  _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions.\n  * @retval None\n  */\n#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos)\n\n/**\n  * @brief  Enable ADC scan mode.\n  * @param  _SCANCONV_MODE_ Scan conversion mode.\n  * @retval None\n  */\n#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)\n\n/**\n  * @brief  Enable the ADC end of conversion selection.\n  * @param  _EOCSelection_MODE_ End of conversion selection mode.\n  * @retval None\n  */\n#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)\n\n/**\n  * @brief  Enable the ADC DMA continuous request.\n  * @param  _DMAContReq_MODE_ DMA continuous request mode.\n  * @retval None\n  */\n#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)\n\n/**\n  * @brief Return resolution bits in CR1 register.\n  * @param __HANDLE__ ADC handle\n  * @retval None\n  */\n#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup ADC_Private_Functions ADC Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__STM32F4xx_ADC_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_adc_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of ADC HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_ADC_EX_H\n#define __STM32F4xx_ADC_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup ADCEx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup ADCEx_Exported_Types ADC Exported Types\n  * @{\n  */\n   \n/** \n  * @brief  ADC Configuration injected Channel structure definition\n  * @note   Parameters of this structure are shared within 2 scopes:\n  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset\n  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,\n  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.\n  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.\n  *         ADC state can be either:\n  *          - For all parameters: ADC disabled\n  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.\n  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.\n  */\ntypedef struct \n{\n  uint32_t InjectedChannel;                      /*!< Selection of ADC channel to configure\n                                                      This parameter can be a value of @ref ADC_channels\n                                                      Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */\n  uint32_t InjectedRank;                         /*!< Rank in the injected group sequencer\n                                                      This parameter must be a value of @ref ADCEx_injected_rank\n                                                      Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */\n  uint32_t InjectedSamplingTime;                 /*!< Sampling time value to be set for the selected channel.\n                                                      Unit: ADC clock cycles\n                                                      Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).\n                                                      This parameter can be a value of @ref ADC_sampling_times\n                                                      Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.\n                                                               If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.\n                                                      Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),\n                                                            sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)\n                                                            Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */\n  uint32_t InjectedOffset;                       /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).\n                                                      Offset value must be a positive number.\n                                                      Depending of ADC resolution selected (12, 10, 8 or 6 bits),\n                                                      this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */\n  uint32_t InjectedNbrOfConversion;              /*!< Specifies the number of ranks that will be converted within the injected group sequencer.\n                                                      To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.\n                                                      This parameter must be a number between Min_Data = 1 and Max_Data = 4.\n                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \n                                                               configure a channel on injected group can impact the configuration of other channels previously set. */\n  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).\n                                                      Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.\n                                                      Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.\n                                                      This parameter can be set to ENABLE or DISABLE.\n                                                      Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.\n                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \n                                                               configure a channel on injected group can impact the configuration of other channels previously set. */\n  FunctionalState AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one\n                                                      This parameter can be set to ENABLE or DISABLE.      \n                                                      Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)\n                                                      Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)\n                                                      Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.\n                                                            To maintain JAUTO always enabled, DMA must be configured in circular mode.\n                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\n                                                               configure a channel on injected group can impact the configuration of other channels previously set. */\n  uint32_t ExternalTrigInjecConv;                /*!< Selects the external event used to trigger the conversion start of injected group.\n                                                      If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.\n                                                      If set to external trigger source, triggering is on event rising edge.\n                                                      This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected\n                                                      Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).\n                                                            If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)\n                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to\n                                                               configure a channel on injected group can impact the configuration of other channels previously set. */\n  uint32_t ExternalTrigInjecConvEdge;            /*!< Selects the external trigger edge of injected group.\n                                                      This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.\n                                                      If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.\n                                                      Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to \n                                                               configure a channel on injected group can impact the configuration of other channels previously set. */\n}ADC_InjectionConfTypeDef; \n\n/** \n  * @brief ADC Configuration multi-mode structure definition  \n  */ \ntypedef struct\n{\n  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multi mode. \n                                   This parameter can be a value of @ref ADCEx_Common_mode */\n  uint32_t DMAAccessMode;     /*!< Configures the Direct memory access mode for multi ADC mode.\n                                   This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */\n  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.\n                                   This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */\n}ADC_MultiModeTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup ADCEx_Exported_Constants ADC Exported Constants\n  * @{\n  */\n\n/** @defgroup ADCEx_Common_mode ADC Common Mode\n  * @{\n  */ \n#define ADC_MODE_INDEPENDENT                  0x00000000U\n#define ADC_DUALMODE_REGSIMULT_INJECSIMULT    ((uint32_t)ADC_CCR_MULTI_0)\n#define ADC_DUALMODE_REGSIMULT_ALTERTRIG      ((uint32_t)ADC_CCR_MULTI_1)\n#define ADC_DUALMODE_INJECSIMULT              ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\n#define ADC_DUALMODE_REGSIMULT                ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\n#define ADC_DUALMODE_INTERL                   ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\n#define ADC_DUALMODE_ALTERTRIG                ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\n#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT  ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))\n#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig    ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))\n#define ADC_TRIPLEMODE_INJECSIMULT            ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))\n#define ADC_TRIPLEMODE_REGSIMULT              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))\n#define ADC_TRIPLEMODE_INTERL                 ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))\n#define ADC_TRIPLEMODE_ALTERTRIG              ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))\n/**\n  * @}\n  */ \n\n/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode\n  * @{\n  */ \n#define ADC_DMAACCESSMODE_DISABLED  0x00000000U                /*!< DMA mode disabled */\n#define ADC_DMAACCESSMODE_1         ((uint32_t)ADC_CCR_DMA_0)  /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/\n#define ADC_DMAACCESSMODE_2         ((uint32_t)ADC_CCR_DMA_1)  /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/\n#define ADC_DMAACCESSMODE_3         ((uint32_t)ADC_CCR_DMA)    /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */\n/**\n  * @}\n  */ \n\n/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected\n  * @{\n  */ \n#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE           0x00000000U\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)\n#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)\n#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)\n/**\n  * @}\n  */ \n\n/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected\n  * @{\n  */ \n#define ADC_EXTERNALTRIGINJECCONV_T1_CC4           0x00000000U\n#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)ADC_CR2_JEXTSEL_0)\n#define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)ADC_CR2_JEXTSEL_1)\n#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC2           ((uint32_t)ADC_CR2_JEXTSEL_2)\n#define ADC_EXTERNALTRIGINJECCONV_T3_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T4_CC1           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))\n#define ADC_EXTERNALTRIGINJECCONV_T4_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T4_CC3           ((uint32_t)ADC_CR2_JEXTSEL_3)\n#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T5_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))\n#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO          ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T8_CC2           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))\n#define ADC_EXTERNALTRIGINJECCONV_T8_CC3           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))\n#define ADC_EXTERNALTRIGINJECCONV_T8_CC4           ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))\n#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)ADC_CR2_JEXTSEL)\n#define ADC_INJECTED_SOFTWARE_START                ((uint32_t)ADC_CR2_JEXTSEL + 1U)\n/**\n  * @}\n  */ \n\n/** @defgroup ADCEx_injected_rank ADC Injected Rank\n  * @{\n  */ \n#define ADC_INJECTED_RANK_1    0x00000001U\n#define ADC_INJECTED_RANK_2    0x00000002U\n#define ADC_INJECTED_RANK_3    0x00000003U\n#define ADC_INJECTED_RANK_4    0x00000004U\n/**\n  * @}\n  */\n\n/** @defgroup ADCEx_channels  ADC Specific Channels\n  * @{\n  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \\\n    defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \\\n    defined(STM32F412Cx)\n#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_16)\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||\n          STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\\\n    defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) \n#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */\n#define ADC_CHANNEL_TEMPSENSOR  ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)\n#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */ \n\n\n/**\n  * @}\n  */ \n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup ADC_Exported_Macros ADC Exported Macros\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)\n/**\n  * @brief Disable internal path of ADC channel Vbat\n  * @note  Use case of this macro:\n  *        On devices STM32F42x and STM32F43x, ADC internal channels\n  *        Vbat and VrefInt share the same internal path, only\n  *        one of them can be enabled.This macro is to be used when ADC \n  *        channels Vbat and VrefInt are selected, and must be called \n  *        before starting conversion of ADC channel VrefInt in order \n  *        to disable ADC channel Vbat.\n  * @retval None\n  */\n#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\n/**\n  * @}\n  */ \n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup ADCEx_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup ADCEx_Exported_Functions_Group1\n  * @{\n  */\n\n/* I/O operation functions ******************************************************/\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);\nvoid HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);\n\n/* Peripheral Control functions *************************************************/\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup ADCEx_Private_Constants ADC Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup ADCEx_Private_Macros ADC Private Macros\n  * @{\n  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \\\n    defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \\\n    defined(STM32F412Cx)\n#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18)\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE ||\n          STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n      \n#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \\\n    defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18)  || \\\n                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR))\n#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT)                 || \\\n                           ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT)   || \\\n                           ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)     || \\\n                           ((MODE) == ADC_DUALMODE_INJECSIMULT)             || \\\n                           ((MODE) == ADC_DUALMODE_REGSIMULT)               || \\\n                           ((MODE) == ADC_DUALMODE_INTERL)                  || \\\n                           ((MODE) == ADC_DUALMODE_ALTERTRIG)               || \\\n                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \\\n                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig)   || \\\n                           ((MODE) == ADC_TRIPLEMODE_INJECSIMULT)           || \\\n                           ((MODE) == ADC_TRIPLEMODE_REGSIMULT)             || \\\n                           ((MODE) == ADC_TRIPLEMODE_INTERL)                || \\\n                           ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))\n#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \\\n                                      ((MODE) == ADC_DMAACCESSMODE_1)        || \\\n                                      ((MODE) == ADC_DMAACCESSMODE_2)        || \\\n                                      ((MODE) == ADC_DMAACCESSMODE_3))\n#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE)    || \\\n                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING)  || \\\n                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \\\n                                          ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))\n#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4)  || \\\n                                        ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \\\n                                        ((INJTRIG) == ADC_INJECTED_SOFTWARE_START))\n#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U))\n#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U))\n\n/**\n  * @brief  Set the selected injected Channel rank.\n  * @param  _CHANNELNB_ Channel number.\n  * @param  _RANKNB_ Rank number. \n  * @param  _JSQR_JL_ Sequence length.\n  * @retval None\n  */\n#define   ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_)  (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))\n\n/**\n  * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1\n  * if available (ADC2, ADC3 availability depends on STM32 product)\n  * @param __HANDLE__ ADC handle\n  * @retval Common control register ADC123 or ADC1\n  */\n#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define ADC_COMMON_REGISTER(__HANDLE__)                ADC123_COMMON\n#else\n#define ADC_COMMON_REGISTER(__HANDLE__)                ADC1_COMMON\n#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup ADCEx_Private_Functions ADC Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__STM32F4xx_ADC_EX_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_can.h\n  * @author  MCD Application Team\n  * @brief   Header file of CAN HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_CAN_H\n#define STM32F4xx_HAL_CAN_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n#if defined (CAN1)\n/** @addtogroup CAN\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup CAN_Exported_Types CAN Exported Types\n  * @{\n  */\n/**\n  * @brief  HAL State structures definition\n  */\ntypedef enum\n{\n  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */\n  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */\n  HAL_CAN_STATE_LISTENING         = 0x02U,  /*!< CAN receive process is ongoing      */\n  HAL_CAN_STATE_SLEEP_PENDING     = 0x03U,  /*!< CAN sleep request is pending        */\n  HAL_CAN_STATE_SLEEP_ACTIVE      = 0x04U,  /*!< CAN sleep mode is active            */\n  HAL_CAN_STATE_ERROR             = 0x05U   /*!< CAN error state                     */\n\n} HAL_CAN_StateTypeDef;\n\n/**\n  * @brief  CAN init structure definition\n  */\ntypedef struct\n{\n  uint32_t Prescaler;                  /*!< Specifies the length of a time quantum.\n                                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */\n\n  uint32_t Mode;                       /*!< Specifies the CAN operating mode.\n                                            This parameter can be a value of @ref CAN_operating_mode */\n\n  uint32_t SyncJumpWidth;              /*!< Specifies the maximum number of time quanta the CAN hardware\n                                            is allowed to lengthen or shorten a bit to perform resynchronization.\n                                            This parameter can be a value of @ref CAN_synchronisation_jump_width */\n\n  uint32_t TimeSeg1;                   /*!< Specifies the number of time quanta in Bit Segment 1.\n                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */\n\n  uint32_t TimeSeg2;                   /*!< Specifies the number of time quanta in Bit Segment 2.\n                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */\n\n  FunctionalState TimeTriggeredMode;   /*!< Enable or disable the time triggered communication mode.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n  FunctionalState AutoBusOff;          /*!< Enable or disable the automatic bus-off management.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n  FunctionalState AutoWakeUp;          /*!< Enable or disable the automatic wake-up mode.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n  FunctionalState AutoRetransmission;  /*!< Enable or disable the non-automatic retransmission mode.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n  FunctionalState ReceiveFifoLocked;   /*!< Enable or disable the Receive FIFO Locked mode.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n  FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.\n                                            This parameter can be set to ENABLE or DISABLE. */\n\n} CAN_InitTypeDef;\n\n/**\n  * @brief  CAN filter configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit\n                                       configuration, first one for a 16-bit configuration).\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\n\n  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit\n                                       configuration, second one for a 16-bit configuration).\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\n\n  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,\n                                       according to the mode (MSBs for a 32-bit configuration,\n                                       first one for a 16-bit configuration).\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\n\n  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,\n                                       according to the mode (LSBs for a 32-bit configuration,\n                                       second one for a 16-bit configuration).\n                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\n\n  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.\n                                       This parameter can be a value of @ref CAN_filter_FIFO */\n\n  uint32_t FilterBank;            /*!< Specifies the filter bank which will be initialized.\n                                       For single CAN instance(14 dedicated filter banks),\n                                       this parameter must be a number between Min_Data = 0 and Max_Data = 13.\n                                       For dual CAN instances(28 filter banks shared),\n                                       this parameter must be a number between Min_Data = 0 and Max_Data = 27. */\n\n  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.\n                                       This parameter can be a value of @ref CAN_filter_mode */\n\n  uint32_t FilterScale;           /*!< Specifies the filter scale.\n                                       This parameter can be a value of @ref CAN_filter_scale */\n\n  uint32_t FilterActivation;      /*!< Enable or disable the filter.\n                                       This parameter can be a value of @ref CAN_filter_activation */\n\n  uint32_t SlaveStartFilterBank;  /*!< Select the start filter bank for the slave CAN instance.\n                                       For single CAN instances, this parameter is meaningless.\n                                       For dual CAN instances, all filter banks with lower index are assigned to master\n                                       CAN instance, whereas all filter banks with greater index are assigned to slave\n                                       CAN instance.\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */\n\n} CAN_FilterTypeDef;\n\n/**\n  * @brief  CAN Tx message header structure definition\n  */\ntypedef struct\n{\n  uint32_t StdId;    /*!< Specifies the standard identifier.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */\n\n  uint32_t ExtId;    /*!< Specifies the extended identifier.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */\n\n  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.\n                          This parameter can be a value of @ref CAN_identifier_type */\n\n  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.\n                          This parameter can be a value of @ref CAN_remote_transmission_request */\n\n  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */\n\n  FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start\n                          of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].\n                          @note: Time Triggered Communication Mode must be enabled.\n                          @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.\n                          This parameter can be set to ENABLE or DISABLE. */\n\n} CAN_TxHeaderTypeDef;\n\n/**\n  * @brief  CAN Rx message header structure definition\n  */\ntypedef struct\n{\n  uint32_t StdId;    /*!< Specifies the standard identifier.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */\n\n  uint32_t ExtId;    /*!< Specifies the extended identifier.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */\n\n  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.\n                          This parameter can be a value of @ref CAN_identifier_type */\n\n  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.\n                          This parameter can be a value of @ref CAN_remote_transmission_request */\n\n  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */\n\n  uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.\n                          @note: Time Triggered Communication Mode must be enabled.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */\n\n  uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.\n                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */\n\n} CAN_RxHeaderTypeDef;\n\n/**\n  * @brief  CAN handle Structure definition\n  */\ntypedef struct __CAN_HandleTypeDef\n{\n  CAN_TypeDef                 *Instance;                 /*!< Register base address */\n\n  CAN_InitTypeDef             Init;                      /*!< CAN required parameters */\n\n  __IO HAL_CAN_StateTypeDef   State;                     /*!< CAN communication state */\n\n  __IO uint32_t               ErrorCode;                 /*!< CAN Error code.\n                                                              This parameter can be a value of @ref CAN_Error_Code */\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n  void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback    */\n  void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback    */\n  void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback    */\n  void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 0 abort callback       */\n  void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 1 abort callback       */\n  void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 2 abort callback       */\n  void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback    */\n  void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 0 full callback           */\n  void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback    */\n  void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 1 full callback           */\n  void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Sleep callback                    */\n  void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Wake Up from Rx msg callback      */\n  void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Error callback                    */\n\n  void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan);           /*!< CAN Msp Init callback                 */\n  void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan);         /*!< CAN Msp DeInit callback               */\n\n#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */\n} CAN_HandleTypeDef;\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n/**\n  * @brief  HAL CAN common Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID       = 0x00U,    /*!< CAN Tx Mailbox 0 complete callback ID         */\n  HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID       = 0x01U,    /*!< CAN Tx Mailbox 1 complete callback ID         */\n  HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID       = 0x02U,    /*!< CAN Tx Mailbox 2 complete callback ID         */\n  HAL_CAN_TX_MAILBOX0_ABORT_CB_ID          = 0x03U,    /*!< CAN Tx Mailbox 0 abort callback ID            */\n  HAL_CAN_TX_MAILBOX1_ABORT_CB_ID          = 0x04U,    /*!< CAN Tx Mailbox 1 abort callback ID            */\n  HAL_CAN_TX_MAILBOX2_ABORT_CB_ID          = 0x05U,    /*!< CAN Tx Mailbox 2 abort callback ID            */\n  HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID       = 0x06U,    /*!< CAN Rx FIFO 0 message pending callback ID     */\n  HAL_CAN_RX_FIFO0_FULL_CB_ID              = 0x07U,    /*!< CAN Rx FIFO 0 full callback ID                */\n  HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID       = 0x08U,    /*!< CAN Rx FIFO 1 message pending callback ID     */\n  HAL_CAN_RX_FIFO1_FULL_CB_ID              = 0x09U,    /*!< CAN Rx FIFO 1 full callback ID                */\n  HAL_CAN_SLEEP_CB_ID                      = 0x0AU,    /*!< CAN Sleep callback ID                         */\n  HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID         = 0x0BU,    /*!< CAN Wake Up from Rx msg callback ID          */\n  HAL_CAN_ERROR_CB_ID                      = 0x0CU,    /*!< CAN Error callback ID                         */\n\n  HAL_CAN_MSPINIT_CB_ID                    = 0x0DU,    /*!< CAN MspInit callback ID                       */\n  HAL_CAN_MSPDEINIT_CB_ID                  = 0x0EU,    /*!< CAN MspDeInit callback ID                     */\n\n} HAL_CAN_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL CAN Callback pointer definition\n  */\ntypedef  void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function   */\n\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup CAN_Exported_Constants CAN Exported Constants\n  * @{\n  */\n\n/** @defgroup CAN_Error_Code CAN Error Code\n  * @{\n  */\n#define HAL_CAN_ERROR_NONE            (0x00000000U)  /*!< No error                                             */\n#define HAL_CAN_ERROR_EWG             (0x00000001U)  /*!< Protocol Error Warning                               */\n#define HAL_CAN_ERROR_EPV             (0x00000002U)  /*!< Error Passive                                        */\n#define HAL_CAN_ERROR_BOF             (0x00000004U)  /*!< Bus-off error                                        */\n#define HAL_CAN_ERROR_STF             (0x00000008U)  /*!< Stuff error                                          */\n#define HAL_CAN_ERROR_FOR             (0x00000010U)  /*!< Form error                                           */\n#define HAL_CAN_ERROR_ACK             (0x00000020U)  /*!< Acknowledgment error                                 */\n#define HAL_CAN_ERROR_BR              (0x00000040U)  /*!< Bit recessive error                                  */\n#define HAL_CAN_ERROR_BD              (0x00000080U)  /*!< Bit dominant error                                   */\n#define HAL_CAN_ERROR_CRC             (0x00000100U)  /*!< CRC error                                            */\n#define HAL_CAN_ERROR_RX_FOV0         (0x00000200U)  /*!< Rx FIFO0 overrun error                               */\n#define HAL_CAN_ERROR_RX_FOV1         (0x00000400U)  /*!< Rx FIFO1 overrun error                               */\n#define HAL_CAN_ERROR_TX_ALST0        (0x00000800U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */\n#define HAL_CAN_ERROR_TX_TERR0        (0x00001000U)  /*!< TxMailbox 0 transmit failure due to transmit error    */\n#define HAL_CAN_ERROR_TX_ALST1        (0x00002000U)  /*!< TxMailbox 1 transmit failure due to arbitration lost */\n#define HAL_CAN_ERROR_TX_TERR1        (0x00004000U)  /*!< TxMailbox 1 transmit failure due to transmit error    */\n#define HAL_CAN_ERROR_TX_ALST2        (0x00008000U)  /*!< TxMailbox 2 transmit failure due to arbitration lost */\n#define HAL_CAN_ERROR_TX_TERR2        (0x00010000U)  /*!< TxMailbox 2 transmit failure due to transmit error    */\n#define HAL_CAN_ERROR_TIMEOUT         (0x00020000U)  /*!< Timeout error                                        */\n#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U)  /*!< Peripheral not initialized                           */\n#define HAL_CAN_ERROR_NOT_READY       (0x00080000U)  /*!< Peripheral not ready                                 */\n#define HAL_CAN_ERROR_NOT_STARTED     (0x00100000U)  /*!< Peripheral not started                               */\n#define HAL_CAN_ERROR_PARAM           (0x00200000U)  /*!< Parameter error                                      */\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error                               */\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n#define HAL_CAN_ERROR_INTERNAL        (0x00800000U)  /*!< Internal error                                       */\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_InitStatus CAN InitStatus\n  * @{\n  */\n#define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */\n#define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK     */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_operating_mode CAN Operating Mode\n  * @{\n  */\n#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */\n#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */\n#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */\n#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */\n/**\n  * @}\n  */\n\n\n/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width\n  * @{\n  */\n#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */\n#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */\n#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */\n#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1\n  * @{\n  */\n#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */\n#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */\n#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */\n#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */\n#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */\n#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */\n#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */\n#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */\n#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */\n#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */\n#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */\n#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */\n#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */\n#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */\n#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */\n#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2\n  * @{\n  */\n#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */\n#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */\n#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */\n#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */\n#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */\n#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */\n#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */\n#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_filter_mode CAN Filter Mode\n  * @{\n  */\n#define CAN_FILTERMODE_IDMASK       (0x00000000U)  /*!< Identifier mask mode */\n#define CAN_FILTERMODE_IDLIST       (0x00000001U)  /*!< Identifier list mode */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_filter_scale CAN Filter Scale\n  * @{\n  */\n#define CAN_FILTERSCALE_16BIT       (0x00000000U)  /*!< Two 16-bit filters */\n#define CAN_FILTERSCALE_32BIT       (0x00000001U)  /*!< One 32-bit filter  */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_filter_activation CAN Filter Activation\n  * @{\n  */\n#define CAN_FILTER_DISABLE          (0x00000000U)  /*!< Disable filter */\n#define CAN_FILTER_ENABLE           (0x00000001U)  /*!< Enable filter  */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_filter_FIFO CAN Filter FIFO\n  * @{\n  */\n#define CAN_FILTER_FIFO0            (0x00000000U)  /*!< Filter FIFO 0 assignment for filter x */\n#define CAN_FILTER_FIFO1            (0x00000001U)  /*!< Filter FIFO 1 assignment for filter x */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_identifier_type CAN Identifier Type\n  * @{\n  */\n#define CAN_ID_STD                  (0x00000000U)  /*!< Standard Id */\n#define CAN_ID_EXT                  (0x00000004U)  /*!< Extended Id */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request\n  * @{\n  */\n#define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame   */\n#define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number\n  * @{\n  */\n#define CAN_RX_FIFO0                (0x00000000U)  /*!< CAN receive FIFO 0 */\n#define CAN_RX_FIFO1                (0x00000001U)  /*!< CAN receive FIFO 1 */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes\n  * @{\n  */\n#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */\n#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */\n#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */\n/**\n  * @}\n  */\n\n/** @defgroup CAN_flags CAN Flags\n  * @{\n  */\n/* Transmit Flags */\n#define CAN_FLAG_RQCP0              (0x00000500U)  /*!< Request complete MailBox 0 flag   */\n#define CAN_FLAG_TXOK0              (0x00000501U)  /*!< Transmission OK MailBox 0 flag    */\n#define CAN_FLAG_ALST0              (0x00000502U)  /*!< Arbitration Lost MailBox 0 flag   */\n#define CAN_FLAG_TERR0              (0x00000503U)  /*!< Transmission error MailBox 0 flag */\n#define CAN_FLAG_RQCP1              (0x00000508U)  /*!< Request complete MailBox1 flag    */\n#define CAN_FLAG_TXOK1              (0x00000509U)  /*!< Transmission OK MailBox 1 flag    */\n#define CAN_FLAG_ALST1              (0x0000050AU)  /*!< Arbitration Lost MailBox 1 flag   */\n#define CAN_FLAG_TERR1              (0x0000050BU)  /*!< Transmission error MailBox 1 flag */\n#define CAN_FLAG_RQCP2              (0x00000510U)  /*!< Request complete MailBox2 flag    */\n#define CAN_FLAG_TXOK2              (0x00000511U)  /*!< Transmission OK MailBox 2 flag    */\n#define CAN_FLAG_ALST2              (0x00000512U)  /*!< Arbitration Lost MailBox 2 flag   */\n#define CAN_FLAG_TERR2              (0x00000513U)  /*!< Transmission error MailBox 2 flag */\n#define CAN_FLAG_TME0               (0x0000051AU)  /*!< Transmit mailbox 0 empty flag     */\n#define CAN_FLAG_TME1               (0x0000051BU)  /*!< Transmit mailbox 1 empty flag     */\n#define CAN_FLAG_TME2               (0x0000051CU)  /*!< Transmit mailbox 2 empty flag     */\n#define CAN_FLAG_LOW0               (0x0000051DU)  /*!< Lowest priority mailbox 0 flag    */\n#define CAN_FLAG_LOW1               (0x0000051EU)  /*!< Lowest priority mailbox 1 flag    */\n#define CAN_FLAG_LOW2               (0x0000051FU)  /*!< Lowest priority mailbox 2 flag    */\n\n/* Receive Flags */\n#define CAN_FLAG_FF0                (0x00000203U)  /*!< RX FIFO 0 Full flag               */\n#define CAN_FLAG_FOV0               (0x00000204U)  /*!< RX FIFO 0 Overrun flag            */\n#define CAN_FLAG_FF1                (0x00000403U)  /*!< RX FIFO 1 Full flag               */\n#define CAN_FLAG_FOV1               (0x00000404U)  /*!< RX FIFO 1 Overrun flag            */\n\n/* Operating Mode Flags */\n#define CAN_FLAG_INAK               (0x00000100U)  /*!< Initialization acknowledge flag   */\n#define CAN_FLAG_SLAK               (0x00000101U)  /*!< Sleep acknowledge flag            */\n#define CAN_FLAG_ERRI               (0x00000102U)  /*!< Error flag                        */\n#define CAN_FLAG_WKU                (0x00000103U)  /*!< Wake up interrupt flag            */\n#define CAN_FLAG_SLAKI              (0x00000104U)  /*!< Sleep acknowledge interrupt flag  */\n\n/* Error Flags */\n#define CAN_FLAG_EWG                (0x00000300U)  /*!< Error warning flag                */\n#define CAN_FLAG_EPV                (0x00000301U)  /*!< Error passive flag                */\n#define CAN_FLAG_BOF                (0x00000302U)  /*!< Bus-Off flag                      */\n/**\n  * @}\n  */\n\n\n/** @defgroup CAN_Interrupts CAN Interrupts\n  * @{\n  */\n/* Transmit Interrupt */\n#define CAN_IT_TX_MAILBOX_EMPTY     ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */\n\n/* Receive Interrupts */\n#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */\n#define CAN_IT_RX_FIFO0_FULL        ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */\n#define CAN_IT_RX_FIFO0_OVERRUN     ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */\n#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */\n#define CAN_IT_RX_FIFO1_FULL        ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */\n#define CAN_IT_RX_FIFO1_OVERRUN     ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */\n\n/* Operating Mode Interrupts */\n#define CAN_IT_WAKEUP               ((uint32_t)CAN_IER_WKUIE)   /*!< Wake-up interrupt                */\n#define CAN_IT_SLEEP_ACK            ((uint32_t)CAN_IER_SLKIE)   /*!< Sleep acknowledge interrupt      */\n\n/* Error Interrupts */\n#define CAN_IT_ERROR_WARNING        ((uint32_t)CAN_IER_EWGIE)   /*!< Error warning interrupt          */\n#define CAN_IT_ERROR_PASSIVE        ((uint32_t)CAN_IER_EPVIE)   /*!< Error passive interrupt          */\n#define CAN_IT_BUSOFF               ((uint32_t)CAN_IER_BOFIE)   /*!< Bus-off interrupt                */\n#define CAN_IT_LAST_ERROR_CODE      ((uint32_t)CAN_IER_LECIE)   /*!< Last error code interrupt        */\n#define CAN_IT_ERROR                ((uint32_t)CAN_IER_ERRIE)   /*!< Error Interrupt                  */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macros -----------------------------------------------------------*/\n/** @defgroup CAN_Exported_Macros CAN Exported Macros\n  * @{\n  */\n\n/** @brief  Reset CAN handle state\n  * @param  __HANDLE__ CAN handle.\n  * @retval None\n  */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{                                              \\\n                                                     (__HANDLE__)->State = HAL_CAN_STATE_RESET;   \\\n                                                     (__HANDLE__)->MspInitCallback = NULL;        \\\n                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \\\n                                                   } while(0)\n#else\n#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)\n#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */\n\n/**\n  * @brief  Enable the specified CAN interrupts.\n  * @param  __HANDLE__ CAN handle.\n  * @param  __INTERRUPT__ CAN Interrupt sources to enable.\n  *           This parameter can be any combination of @arg CAN_Interrupts\n  * @retval None\n  */\n#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))\n\n/**\n  * @brief  Disable the specified CAN interrupts.\n  * @param  __HANDLE__ CAN handle.\n  * @param  __INTERRUPT__ CAN Interrupt sources to disable.\n  *           This parameter can be any combination of @arg CAN_Interrupts\n  * @retval None\n  */\n#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))\n\n/** @brief  Check if the specified CAN interrupt source is enabled or disabled.\n  * @param  __HANDLE__ specifies the CAN Handle.\n  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.\n  *           This parameter can be a value of @arg CAN_Interrupts\n  * @retval The state of __IT__ (TRUE or FALSE).\n  */\n#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))\n\n/** @brief  Check whether the specified CAN flag is set or not.\n  * @param  __HANDLE__ specifies the CAN Handle.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of @arg CAN_flags\n  * @retval The state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \\\n  ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)\n\n/** @brief  Clear the specified CAN pending flag.\n  * @param  __HANDLE__ specifies the CAN Handle.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag\n  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag\n  *            @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag\n  *            @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag\n  *            @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag\n  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag\n  *            @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag\n  *            @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag\n  *            @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag\n  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag\n  *            @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag\n  *            @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag\n  *            @arg CAN_FLAG_FF0:   RX FIFO 0 Full Flag\n  *            @arg CAN_FLAG_FOV0:  RX FIFO 0 Overrun Flag\n  *            @arg CAN_FLAG_FF1:   RX FIFO 1 Full Flag\n  *            @arg CAN_FLAG_FOV1:  RX FIFO 1 Overrun Flag\n  *            @arg CAN_FLAG_WKUI:  Wake up Interrupt Flag\n  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag\n  * @retval None\n  */\n#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\n  ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \\\n   (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)\n\n/**\n * @}\n */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup CAN_Exported_Functions CAN Exported Functions\n  * @{\n  */\n\n/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions\n * @{\n */\n\n/* Initialization and de-initialization functions *****************************/\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n/* Callbacks Register/UnRegister functions  ***********************************/\nHAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));\nHAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);\n\n#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */\n/**\n * @}\n */\n\n/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions\n *  @brief    Configuration functions\n * @{\n */\n\n/* Configuration functions ****************************************************/\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);\n\n/**\n * @}\n */\n\n/** @addtogroup CAN_Exported_Functions_Group3 Control functions\n *  @brief    Control functions\n * @{\n */\n\n/* Control functions **********************************************************/\nHAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);\nuint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);\nHAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);\nuint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);\nuint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);\nuint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);\nHAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);\nuint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);\n\n/**\n * @}\n */\n\n/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management\n *  @brief    Interrupts management\n * @{\n */\n/* Interrupts management ******************************************************/\nHAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);\nHAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);\n\n/**\n * @}\n */\n\n/** @addtogroup CAN_Exported_Functions_Group5 Callback functions\n *  @brief    Callback functions\n * @{\n */\n/* Callbacks functions ********************************************************/\n\nvoid HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);\nvoid HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);\n\n/**\n * @}\n */\n\n/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions\n *  @brief   CAN Peripheral State functions\n * @{\n */\n/* Peripheral State and Error functions ***************************************/\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);\nHAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);\n\n/**\n * @}\n */\n\n/**\n * @}\n */\n\n/* Private types -------------------------------------------------------------*/\n/** @defgroup CAN_Private_Types CAN Private Types\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup CAN_Private_Variables CAN Private Variables\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup CAN_Private_Constants CAN Private Constants\n  * @{\n  */\n#define CAN_FLAG_MASK  (0x000000FFU)\n/**\n  * @}\n  */\n\n/* Private Macros -----------------------------------------------------------*/\n/** @defgroup CAN_Private_Macros CAN Private Macros\n  * @{\n  */\n\n#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \\\n                           ((MODE) == CAN_MODE_LOOPBACK)|| \\\n                           ((MODE) == CAN_MODE_SILENT) || \\\n                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))\n#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \\\n                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))\n#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \\\n                         ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \\\n                         ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \\\n                         ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \\\n                         ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \\\n                         ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \\\n                         ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \\\n                         ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))\n#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \\\n                         ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \\\n                         ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \\\n                         ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))\n#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))\n#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)\n#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)\n#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)\n#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \\\n                                  ((MODE) == CAN_FILTERMODE_IDLIST))\n#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \\\n                                    ((SCALE) == CAN_FILTERSCALE_32BIT))\n#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \\\n                                              ((ACTIVATION) == CAN_FILTER_ENABLE))\n#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \\\n                                  ((FIFO) == CAN_FILTER_FIFO1))\n#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \\\n                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \\\n                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))\n#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))\n#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)\n#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)\n#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)\n#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \\\n                                ((IDTYPE) == CAN_ID_EXT))\n#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))\n#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))\n#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY     | CAN_IT_RX_FIFO0_MSG_PENDING      | \\\n                                CAN_IT_RX_FIFO0_FULL        | CAN_IT_RX_FIFO0_OVERRUN          | \\\n                                CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL             | \\\n                                CAN_IT_RX_FIFO1_OVERRUN     | CAN_IT_WAKEUP                    | \\\n                                CAN_IT_SLEEP_ACK            | CAN_IT_ERROR_WARNING             | \\\n                                CAN_IT_ERROR_PASSIVE        | CAN_IT_BUSOFF                    | \\\n                                CAN_IT_LAST_ERROR_CODE      | CAN_IT_ERROR))\n\n/**\n  * @}\n  */\n/* End of private macros -----------------------------------------------------*/\n\n/**\n  * @}\n  */\n\n\n#endif /* CAN1 */\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32F4xx_HAL_CAN_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_cortex.h\n  * @author  MCD Application Team\n  * @brief   Header file of CORTEX HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_CORTEX_H\n#define __STM32F4xx_HAL_CORTEX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup CORTEX\n  * @{\n  */ \n/* Exported types ------------------------------------------------------------*/\n/** @defgroup CORTEX_Exported_Types Cortex Exported Types\n  * @{\n  */\n\n#if (__MPU_PRESENT == 1U)\n/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition\n  * @brief  MPU Region initialization structure \n  * @{\n  */\ntypedef struct\n{\n  uint8_t                Enable;                /*!< Specifies the status of the region. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */\n  uint8_t                Number;                /*!< Specifies the number of the region to protect. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */\n  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */\n  uint8_t                Size;                  /*!< Specifies the size of the region to protect. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */\n  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. \n                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         \n  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.\n                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 \n  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */\n  uint8_t                DisableExec;           /*!< Specifies the instruction access status. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */\n  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */\n  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */\n  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. \n                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */\n}MPU_Region_InitTypeDef;\n/**\n  * @}\n  */\n#endif /* __MPU_PRESENT */\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants\n  * @{\n  */\n\n/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group\n  * @{\n  */\n#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority\n                                                      4 bits for subpriority */\n#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority\n                                                      3 bits for subpriority */\n#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority\n                                                      2 bits for subpriority */\n#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority\n                                                      1 bits for subpriority */\n#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority\n                                                      0 bits for subpriority */\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source \n  * @{\n  */\n#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U\n#define SYSTICK_CLKSOURCE_HCLK         0x00000004U\n\n/**\n  * @}\n  */\n\n#if (__MPU_PRESENT == 1)\n/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control\n  * @{\n  */\n#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U\n#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk\n#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk\n#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)\n\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable\n  * @{\n  */\n#define  MPU_REGION_ENABLE     ((uint8_t)0x01)\n#define  MPU_REGION_DISABLE    ((uint8_t)0x00)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access\n  * @{\n  */\n#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)\n#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable\n  * @{\n  */\n#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)\n#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable\n  * @{\n  */\n#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)\n#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable\n  * @{\n  */\n#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)\n#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels\n  * @{\n  */\n#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)\n#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)\n#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size\n  * @{\n  */\n#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)\n#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)\n#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)\n#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)\n#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)\n#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)\n#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)\n#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)\n#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)\n#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)\n#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)\n#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)\n#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)\n#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)\n#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)\n#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)\n#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)\n#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)\n#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)\n#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)\n#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)\n#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)\n#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)\n#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)\n#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)\n#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)\n#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)\n#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)\n/**\n  * @}\n  */\n   \n/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes \n  * @{\n  */\n#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)\n#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)\n#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)\n#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)\n#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)\n#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number\n  * @{\n  */\n#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)\n#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)\n#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)\n#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)\n#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)\n#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)\n#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)\n#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)\n/**\n  * @}\n  */\n#endif /* __MPU_PRESENT */\n\n/**\n  * @}\n  */\n\n\n/* Exported Macros -----------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup CORTEX_Exported_Functions\n  * @{\n  */\n  \n/** @addtogroup CORTEX_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization and de-initialization functions *****************************/\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn);\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn);\nvoid HAL_NVIC_SystemReset(void);\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);\n/**\n  * @}\n  */\n\n/** @addtogroup CORTEX_Exported_Functions_Group2\n  * @{\n  */\n/* Peripheral Control functions ***********************************************/\nuint32_t HAL_NVIC_GetPriorityGrouping(void);\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);\nvoid HAL_SYSTICK_IRQHandler(void);\nvoid HAL_SYSTICK_Callback(void);\n\n#if (__MPU_PRESENT == 1U)\nvoid HAL_MPU_Enable(uint32_t MPU_Control);\nvoid HAL_MPU_Disable(void);\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);\n#endif /* __MPU_PRESENT */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup CORTEX_Private_Macros CORTEX Private Macros\n  * @{\n  */\n#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \\\n                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \\\n                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \\\n                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \\\n                                       ((GROUP) == NVIC_PRIORITYGROUP_4))\n\n#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)\n\n#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)\n\n#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)\n\n#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \\\n                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))\n\n#if (__MPU_PRESENT == 1U)\n#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \\\n                                     ((STATE) == MPU_REGION_DISABLE))\n\n#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \\\n                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))\n\n#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \\\n                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))\n\n#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \\\n                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))\n\n#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \\\n                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))\n\n#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \\\n                                ((TYPE) == MPU_TEX_LEVEL1)  || \\\n                                ((TYPE) == MPU_TEX_LEVEL2))\n\n#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \\\n                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \\\n                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \\\n                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \\\n                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \\\n                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))\n\n#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER1) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER2) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER3) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER4) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER5) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER6) || \\\n                                         ((NUMBER) == MPU_REGION_NUMBER7))\n\n#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \\\n                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \\\n                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \\\n                                     ((SIZE) == MPU_REGION_SIZE_4GB))\n\n#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)\n#endif /* __MPU_PRESENT */\n\n/**                                                                          \n  * @}                                                                  \n  */\n\n/* Private functions ---------------------------------------------------------*/\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n  \n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_CORTEX_H */\n \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_def.h\n  * @author  MCD Application Team\n  * @brief   This file contains HAL common defines, enumeration, macros and \n  *          structures definitions. \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_DEF\n#define __STM32F4xx_HAL_DEF\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n#include \"Legacy/stm32_hal_legacy.h\"\n#include <stddef.h>\n\n/* Exported types ------------------------------------------------------------*/\n\n/** \n  * @brief  HAL Status structures definition  \n  */  \ntypedef enum \n{\n  HAL_OK       = 0x00U,\n  HAL_ERROR    = 0x01U,\n  HAL_BUSY     = 0x02U,\n  HAL_TIMEOUT  = 0x03U\n} HAL_StatusTypeDef;\n\n/** \n  * @brief  HAL Lock structures definition  \n  */\ntypedef enum \n{\n  HAL_UNLOCKED = 0x00U,\n  HAL_LOCKED   = 0x01U  \n} HAL_LockTypeDef;\n\n/* Exported macro ------------------------------------------------------------*/\n\n#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */\n\n#define HAL_MAX_DELAY      0xFFFFFFFFU\n\n#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))\n#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)\n\n#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \\\n                        do{                                                      \\\n                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \\\n                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \\\n                          } while(0U)\n\n/** @brief Reset the Handle's State field.\n  * @param __HANDLE__ specifies the Peripheral Handle.\n  * @note  This macro can be used for the following purpose: \n  *          - When the Handle is declared as local variable; before passing it as parameter\n  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro \n  *            to set to 0 the Handle's \"State\" field.\n  *            Otherwise, \"State\" field may have any random value and the first time the function \n  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed\n  *            (i.e. HAL_PPP_MspInit() will not be executed).\n  *          - When there is a need to reconfigure the low level hardware: instead of calling\n  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().\n  *            In this later function, when the Handle's \"State\" field is set to 0, it will execute the function\n  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.\n  * @retval None\n  */\n#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)\n\n#if (USE_RTOS == 1U)\n  /* Reserved for future use */\n  #error \"USE_RTOS should be 0 in the current HAL release\"\n#else\n  #define __HAL_LOCK(__HANDLE__)                                           \\\n                                do{                                        \\\n                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \\\n                                    {                                      \\\n                                       return HAL_BUSY;                    \\\n                                    }                                      \\\n                                    else                                   \\\n                                    {                                      \\\n                                       (__HANDLE__)->Lock = HAL_LOCKED;    \\\n                                    }                                      \\\n                                  }while (0U)\n\n  #define __HAL_UNLOCK(__HANDLE__)                                          \\\n                                  do{                                       \\\n                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \\\n                                    }while (0U)\n#endif /* USE_RTOS */\n\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */\n  #ifndef __weak\n    #define __weak  __attribute__((weak))\n  #endif\n  #ifndef __packed\n    #define __packed  __attribute__((packed))\n  #endif\n#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\n  #ifndef __weak\n    #define __weak   __attribute__((weak))\n  #endif /* __weak */\n  #ifndef __packed\n    #define __packed __attribute__((__packed__))\n  #endif /* __packed */\n#endif /* __GNUC__ */\n\n\n/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive \"#pragma data_alignment=4\" must be used instead */\n#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */\n  #ifndef __ALIGN_BEGIN\n    #define __ALIGN_BEGIN\n  #endif\n  #ifndef __ALIGN_END\n    #define __ALIGN_END      __attribute__ ((aligned (4)))\n  #endif\n#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */\n  #ifndef __ALIGN_END\n#define __ALIGN_END    __attribute__ ((aligned (4)))\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN  \n    #define __ALIGN_BEGIN\n  #endif /* __ALIGN_BEGIN */\n#else\n  #ifndef __ALIGN_END\n    #define __ALIGN_END\n  #endif /* __ALIGN_END */\n  #ifndef __ALIGN_BEGIN      \n    #if defined   (__CC_ARM)      /* ARM Compiler V5*/\n#define __ALIGN_BEGIN    __align(4)\n    #elif defined (__ICCARM__)    /* IAR Compiler */\n      #define __ALIGN_BEGIN \n    #endif /* __CC_ARM */\n  #endif /* __ALIGN_BEGIN */\n#endif /* __GNUC__ */\n\n\n/** \n  * @brief  __RAM_FUNC definition\n  */ \n#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))\n/* ARM Compiler V4/V5 and V6\n   --------------------------\n   RAM functions are defined using the toolchain options. \n   Functions that are executed in RAM should reside in a separate source module.\n   Using the 'Options for File' dialog you can simply change the 'Code / Const' \n   area of a module to a memory space in physical RAM.\n   Available memory areas are declared in the 'Target' tab of the 'Options for Target'\n   dialog. \n*/\n#define __RAM_FUNC\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n   RAM functions are defined using a specific toolchain keyword \"__ramfunc\". \n*/\n#define __RAM_FUNC __ramfunc\n\n#elif defined   (  __GNUC__  )\n/* GNU Compiler\n   ------------\n  RAM functions are defined using a specific toolchain attribute \n   \"__attribute__((section(\".RamFunc\")))\".\n*/\n#define __RAM_FUNC __attribute__((section(\".RamFunc\")))\n\n#endif\n\n/** \n  * @brief  __NOINLINE definition\n  */ \n#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )\n/* ARM V4/V5 and V6 & GNU Compiler\n   -------------------------------\n*/\n#define __NOINLINE __attribute__ ( (noinline) )\n\n#elif defined ( __ICCARM__ )\n/* ICCARM Compiler\n   ---------------\n*/\n#define __NOINLINE _Pragma(\"optimize = no_inline\")\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ___STM32F4xx_HAL_DEF */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_dma.h\n  * @author  MCD Application Team\n  * @brief   Header file of DMA HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_DMA_H\n#define __STM32F4xx_HAL_DMA_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup DMA\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n\n/** @defgroup DMA_Exported_Types DMA Exported Types\n  * @brief    DMA Exported Types \n  * @{\n  */\n   \n/** \n  * @brief  DMA Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. \n                                      This parameter can be a value of @ref DMA_Channel_selection                    */\n\n  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, \n                                      from memory to memory or from peripheral to memory.\n                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */\n\n  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.\n                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */\n\n  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.\n                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */\n\n  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.\n                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */\n\n  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.\n                                      This parameter can be a value of @ref DMA_Memory_data_size                     */\n\n  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.\n                                      This parameter can be a value of @ref DMA_mode\n                                      @note The circular buffer mode cannot be used if the memory-to-memory\n                                            data transfer is configured on the selected Stream                        */\n\n  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.\n                                      This parameter can be a value of @ref DMA_Priority_level                       */\n\n  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.\n                                      This parameter can be a value of @ref DMA_FIFO_direct_mode\n                                      @note The Direct mode (FIFO mode disabled) cannot be used if the \n                                            memory-to-memory data transfer is configured on the selected stream       */\n\n  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.\n                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */\n\n  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. \n                                      It specifies the amount of data to be transferred in a single non interruptible\n                                      transaction.\n                                      This parameter can be a value of @ref DMA_Memory_burst \n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\n\n  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. \n                                      It specifies the amount of data to be transferred in a single non interruptible \n                                      transaction. \n                                      This parameter can be a value of @ref DMA_Peripheral_burst\n                                      @note The burst mode is possible only if the address Increment mode is enabled. */\n}DMA_InitTypeDef;\n\n\n/** \n  * @brief  HAL DMA State structures definition\n  */\ntypedef enum\n{\n  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */\n  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */\n  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */\n  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */\n  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */\n  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */\n}HAL_DMA_StateTypeDef;\n\n/** \n  * @brief  HAL DMA Error Code structure definition\n  */\ntypedef enum\n{\n  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */\n  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */\n}HAL_DMA_LevelCompleteTypeDef;\n\n/** \n  * @brief  HAL DMA Error Code structure definition\n  */\ntypedef enum\n{\n  HAL_DMA_XFER_CPLT_CB_ID         = 0x00U,  /*!< Full transfer     */\n  HAL_DMA_XFER_HALFCPLT_CB_ID     = 0x01U,  /*!< Half Transfer     */\n  HAL_DMA_XFER_M1CPLT_CB_ID       = 0x02U,  /*!< M1 Full Transfer  */\n  HAL_DMA_XFER_M1HALFCPLT_CB_ID   = 0x03U,  /*!< M1 Half Transfer  */\n  HAL_DMA_XFER_ERROR_CB_ID        = 0x04U,  /*!< Error             */\n  HAL_DMA_XFER_ABORT_CB_ID        = 0x05U,  /*!< Abort             */\n  HAL_DMA_XFER_ALL_CB_ID          = 0x06U   /*!< All               */\n}HAL_DMA_CallbackIDTypeDef;\n\n/** \n  * @brief  DMA handle Structure definition\n  */\ntypedef struct __DMA_HandleTypeDef\n{\n  DMA_Stream_TypeDef         *Instance;                                                        /*!< Register base address                  */\n\n  DMA_InitTypeDef            Init;                                                             /*!< DMA communication parameters           */ \n\n  HAL_LockTypeDef            Lock;                                                             /*!< DMA locking object                     */  \n\n  __IO HAL_DMA_StateTypeDef  State;                                                            /*!< DMA transfer state                     */\n\n  void                       *Parent;                                                          /*!< Parent object state                    */ \n\n  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback         */\n\n  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback    */\n\n  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback */\n  \n  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */\n  \n  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback            */\n  \n  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback            */  \n\n  __IO uint32_t              ErrorCode;                                                        /*!< DMA Error code                          */\n  \n  uint32_t                   StreamBaseAddress;                                                /*!< DMA Stream Base Address                */\n\n  uint32_t                   StreamIndex;                                                      /*!< DMA Stream Index                       */\n \n}DMA_HandleTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup DMA_Exported_Constants DMA Exported Constants\n  * @brief    DMA Exported constants \n  * @{\n  */\n\n/** @defgroup DMA_Error_Code DMA Error Code\n  * @brief    DMA Error Code \n  * @{\n  */ \n#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */\n#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */\n#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */\n#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */\n#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */\n#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */\n#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */\n#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Channel_selection DMA Channel selection\n  * @brief    DMA channel selection \n  * @{\n  */ \n#define DMA_CHANNEL_0                 0x00000000U    /*!< DMA Channel 0 */\n#define DMA_CHANNEL_1                 0x02000000U    /*!< DMA Channel 1 */\n#define DMA_CHANNEL_2                 0x04000000U    /*!< DMA Channel 2 */\n#define DMA_CHANNEL_3                 0x06000000U    /*!< DMA Channel 3 */\n#define DMA_CHANNEL_4                 0x08000000U    /*!< DMA Channel 4 */\n#define DMA_CHANNEL_5                 0x0A000000U    /*!< DMA Channel 5 */\n#define DMA_CHANNEL_6                 0x0C000000U    /*!< DMA Channel 6 */\n#define DMA_CHANNEL_7                 0x0E000000U    /*!< DMA Channel 7 */\n#if defined (DMA_SxCR_CHSEL_3)\n#define DMA_CHANNEL_8                 0x10000000U    /*!< DMA Channel 8 */\n#define DMA_CHANNEL_9                 0x12000000U    /*!< DMA Channel 9 */\n#define DMA_CHANNEL_10                0x14000000U    /*!< DMA Channel 10 */\n#define DMA_CHANNEL_11                0x16000000U    /*!< DMA Channel 11 */\n#define DMA_CHANNEL_12                0x18000000U    /*!< DMA Channel 12 */\n#define DMA_CHANNEL_13                0x1A000000U    /*!< DMA Channel 13 */\n#define DMA_CHANNEL_14                0x1C000000U    /*!< DMA Channel 14 */\n#define DMA_CHANNEL_15                0x1E000000U    /*!< DMA Channel 15 */\n#endif /* DMA_SxCR_CHSEL_3 */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction\n  * @brief    DMA data transfer direction \n  * @{\n  */ \n#define DMA_PERIPH_TO_MEMORY          0x00000000U                 /*!< Peripheral to memory direction */\n#define DMA_MEMORY_TO_PERIPH          ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */\n#define DMA_MEMORY_TO_MEMORY          ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */\n/**\n  * @}\n  */\n        \n/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode\n  * @brief    DMA peripheral incremented mode \n  * @{\n  */ \n#define DMA_PINC_ENABLE               ((uint32_t)DMA_SxCR_PINC)   /*!< Peripheral increment mode enable  */\n#define DMA_PINC_DISABLE              0x00000000U                 /*!< Peripheral increment mode disable */\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode\n  * @brief    DMA memory incremented mode \n  * @{\n  */ \n#define DMA_MINC_ENABLE               ((uint32_t)DMA_SxCR_MINC)   /*!< Memory increment mode enable  */\n#define DMA_MINC_DISABLE              0x00000000U                 /*!< Memory increment mode disable */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size\n  * @brief    DMA peripheral data size \n  * @{\n  */ \n#define DMA_PDATAALIGN_BYTE           0x00000000U                  /*!< Peripheral data alignment: Byte     */\n#define DMA_PDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */\n#define DMA_PDATAALIGN_WORD           ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word     */\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_Memory_data_size DMA Memory data size\n  * @brief    DMA memory data size \n  * @{ \n  */\n#define DMA_MDATAALIGN_BYTE           0x00000000U                  /*!< Memory data alignment: Byte     */\n#define DMA_MDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */\n#define DMA_MDATAALIGN_WORD           ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word     */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_mode DMA mode\n  * @brief    DMA mode \n  * @{\n  */ \n#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */\n#define DMA_CIRCULAR                  ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */\n#define DMA_PFCTRL                    ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Priority_level DMA Priority level\n  * @brief    DMA priority levels \n  * @{\n  */\n#define DMA_PRIORITY_LOW              0x00000000U                 /*!< Priority level: Low       */\n#define DMA_PRIORITY_MEDIUM           ((uint32_t)DMA_SxCR_PL_0)   /*!< Priority level: Medium    */\n#define DMA_PRIORITY_HIGH             ((uint32_t)DMA_SxCR_PL_1)   /*!< Priority level: High      */\n#define DMA_PRIORITY_VERY_HIGH        ((uint32_t)DMA_SxCR_PL)     /*!< Priority level: Very High */\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode\n  * @brief    DMA FIFO direct mode\n  * @{\n  */\n#define DMA_FIFOMODE_DISABLE          0x00000000U                 /*!< FIFO mode disable */\n#define DMA_FIFOMODE_ENABLE           ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable  */\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level\n  * @brief    DMA FIFO level \n  * @{\n  */\n#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U                  /*!< FIFO threshold 1 quart full configuration  */\n#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */\n#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */\n#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_Memory_burst DMA Memory burst\n  * @brief    DMA memory burst \n  * @{\n  */ \n#define DMA_MBURST_SINGLE             0x00000000U\n#define DMA_MBURST_INC4               ((uint32_t)DMA_SxCR_MBURST_0)  \n#define DMA_MBURST_INC8               ((uint32_t)DMA_SxCR_MBURST_1)  \n#define DMA_MBURST_INC16              ((uint32_t)DMA_SxCR_MBURST)  \n/**\n  * @}\n  */ \n\n/** @defgroup DMA_Peripheral_burst DMA Peripheral burst\n  * @brief    DMA peripheral burst \n  * @{\n  */ \n#define DMA_PBURST_SINGLE             0x00000000U\n#define DMA_PBURST_INC4               ((uint32_t)DMA_SxCR_PBURST_0)\n#define DMA_PBURST_INC8               ((uint32_t)DMA_SxCR_PBURST_1)\n#define DMA_PBURST_INC16              ((uint32_t)DMA_SxCR_PBURST)\n/**\n  * @}\n  */\n\n/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions\n  * @brief    DMA interrupts definition \n  * @{\n  */\n#define DMA_IT_TC                     ((uint32_t)DMA_SxCR_TCIE)\n#define DMA_IT_HT                     ((uint32_t)DMA_SxCR_HTIE)\n#define DMA_IT_TE                     ((uint32_t)DMA_SxCR_TEIE)\n#define DMA_IT_DME                    ((uint32_t)DMA_SxCR_DMEIE)\n#define DMA_IT_FE                     0x00000080U\n/**\n  * @}\n  */\n\n/** @defgroup DMA_flag_definitions DMA flag definitions\n  * @brief    DMA flag definitions \n  * @{\n  */ \n#define DMA_FLAG_FEIF0_4              0x00000001U\n#define DMA_FLAG_DMEIF0_4             0x00000004U\n#define DMA_FLAG_TEIF0_4              0x00000008U\n#define DMA_FLAG_HTIF0_4              0x00000010U\n#define DMA_FLAG_TCIF0_4              0x00000020U\n#define DMA_FLAG_FEIF1_5              0x00000040U\n#define DMA_FLAG_DMEIF1_5             0x00000100U\n#define DMA_FLAG_TEIF1_5              0x00000200U\n#define DMA_FLAG_HTIF1_5              0x00000400U\n#define DMA_FLAG_TCIF1_5              0x00000800U\n#define DMA_FLAG_FEIF2_6              0x00010000U\n#define DMA_FLAG_DMEIF2_6             0x00040000U\n#define DMA_FLAG_TEIF2_6              0x00080000U\n#define DMA_FLAG_HTIF2_6              0x00100000U\n#define DMA_FLAG_TCIF2_6              0x00200000U\n#define DMA_FLAG_FEIF3_7              0x00400000U\n#define DMA_FLAG_DMEIF3_7             0x01000000U\n#define DMA_FLAG_TEIF3_7              0x02000000U\n#define DMA_FLAG_HTIF3_7              0x04000000U\n#define DMA_FLAG_TCIF3_7              0x08000000U\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n \n/* Exported macro ------------------------------------------------------------*/\n\n/** @brief Reset DMA handle state\n  * @param  __HANDLE__ specifies the DMA handle.\n  * @retval None\n  */\n#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)\n\n/**\n  * @brief  Return the current DMA Stream FIFO filled level.\n  * @param  __HANDLE__ DMA handle\n  * @retval The FIFO filling state.\n  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full \n  *                                              and not empty.\n  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.\n  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.\n  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.\n  *           - DMA_FIFOStatus_Empty: when FIFO is empty\n  *           - DMA_FIFOStatus_Full: when FIFO is full\n  */\n#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))\n\n/**\n  * @brief  Enable the specified DMA Stream.\n  * @param  __HANDLE__ DMA handle\n  * @retval None\n  */\n#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)\n\n/**\n  * @brief  Disable the specified DMA Stream.\n  * @param  __HANDLE__ DMA handle\n  * @retval None\n  */\n#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)\n\n/* Interrupt & Flag management */\n\n/**\n  * @brief  Return the current DMA Stream transfer complete flag.\n  * @param  __HANDLE__ DMA handle\n  * @retval The specified transfer complete flag index.\n  */\n#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \\\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\\\n   DMA_FLAG_TCIF3_7)\n\n/**\n  * @brief  Return the current DMA Stream half transfer complete flag.\n  * @param  __HANDLE__ DMA handle\n  * @retval The specified half transfer complete flag index.\n  */      \n#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\\\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\\\n   DMA_FLAG_HTIF3_7)\n\n/**\n  * @brief  Return the current DMA Stream transfer error flag.\n  * @param  __HANDLE__ DMA handle\n  * @retval The specified transfer error flag index.\n  */\n#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\\\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\\\n   DMA_FLAG_TEIF3_7)\n\n/**\n  * @brief  Return the current DMA Stream FIFO error flag.\n  * @param  __HANDLE__ DMA handle\n  * @retval The specified FIFO error flag index.\n  */\n#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\\\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\\\n   DMA_FLAG_FEIF3_7)\n\n/**\n  * @brief  Return the current DMA Stream direct mode error flag.\n  * @param  __HANDLE__ DMA handle\n  * @retval The specified direct mode error flag index.\n  */\n#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\\\n(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\\\n ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\\\n   DMA_FLAG_DMEIF3_7)\n\n/**\n  * @brief  Get the DMA Stream pending flags.\n  * @param  __HANDLE__ DMA handle\n  * @param  __FLAG__ Get the specified flag.\n  *          This parameter can be any combination of the following values:\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \n  * @retval The state of FLAG (SET or RESET).\n  */\n#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\\\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\\\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\\\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))\n\n/**\n  * @brief  Clear the DMA Stream pending flags.\n  * @param  __HANDLE__ DMA handle\n  * @param  __FLAG__ specifies the flag to clear.\n  *          This parameter can be any combination of the following values:\n  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.\n  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.\n  *            @arg DMA_FLAG_TEIFx: Transfer error flag.\n  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.\n  *            @arg DMA_FLAG_FEIFx: FIFO error flag.\n  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   \n  * @retval None\n  */\n#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \\\n(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\\\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\\\n ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))\n\n/**\n  * @brief  Enable the specified DMA Stream interrupts.\n  * @param  __HANDLE__ DMA handle\n  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \n  *        This parameter can be any combination of the following values:\n  *           @arg DMA_IT_TC: Transfer complete interrupt mask.\n  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.\n  *           @arg DMA_IT_TE: Transfer error interrupt mask.\n  *           @arg DMA_IT_FE: FIFO error interrupt mask.\n  *           @arg DMA_IT_DME: Direct mode error interrupt.\n  * @retval None\n  */\n#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \\\n((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))\n\n/**\n  * @brief  Disable the specified DMA Stream interrupts.\n  * @param  __HANDLE__ DMA handle\n  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. \n  *         This parameter can be any combination of the following values:\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\n  * @retval None\n  */\n#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\n((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))\n\n/**\n  * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.\n  * @param  __HANDLE__ DMA handle\n  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.\n  *         This parameter can be one of the following values:\n  *            @arg DMA_IT_TC: Transfer complete interrupt mask.\n  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.\n  *            @arg DMA_IT_TE: Transfer error interrupt mask.\n  *            @arg DMA_IT_FE: FIFO error interrupt mask.\n  *            @arg DMA_IT_DME: Direct mode error interrupt.\n  * @retval The state of DMA_IT.\n  */\n#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \\\n                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \\\n                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))\n\n/**\n  * @brief  Writes the number of data units to be transferred on the DMA Stream.\n  * @param  __HANDLE__ DMA handle\n  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) \n  *          Number of data items depends only on the Peripheral data format.\n  *            \n  * @note   If Peripheral data format is Bytes: number of data units is equal \n  *         to total number of bytes to be transferred.\n  *           \n  * @note   If Peripheral data format is Half-Word: number of data units is  \n  *         equal to total number of bytes to be transferred / 2.\n  *           \n  * @note   If Peripheral data format is Word: number of data units is equal \n  *         to total  number of bytes to be transferred / 4.\n  *      \n  * @retval The number of remaining data units in the current DMAy Streamx transfer.\n  */\n#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))\n\n/**\n  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.\n  * @param  __HANDLE__ DMA handle\n  *   \n  * @retval The number of remaining data units in the current DMA Stream transfer.\n  */\n#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)\n\n\n/* Include DMA HAL Extension module */\n#include \"stm32f4xx_hal_dma_ex.h\"   \n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup DMA_Exported_Functions DMA Exported Functions\n  * @brief    DMA Exported functions \n  * @{\n  */\n\n/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions\n  * @brief   Initialization and de-initialization functions \n  * @{\n  */\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); \nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions\n  * @brief   I/O operation functions  \n  * @{\n  */\nHAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);\nvoid              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);\nHAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);\nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));\nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);\n\n/**\n  * @}\n  */ \n\n/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions\n  * @brief    Peripheral State functions \n  * @{\n  */\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);\nuint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);\n/**\n  * @}\n  */ \n/**\n  * @}\n  */ \n/* Private Constants -------------------------------------------------------------*/\n/** @defgroup DMA_Private_Constants DMA Private Constants\n  * @brief    DMA private defines and constants \n  * @{\n  */\n/**\n  * @}\n  */ \n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup DMA_Private_Macros DMA Private Macros\n  * @brief    DMA private macros \n  * @{\n  */\n#if defined (DMA_SxCR_CHSEL_3)\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_1) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_2) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_3) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_4) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_5) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_6) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_7) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_8) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_9) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_10)|| \\\n                                 ((CHANNEL) == DMA_CHANNEL_11)|| \\\n                                 ((CHANNEL) == DMA_CHANNEL_12)|| \\\n                                 ((CHANNEL) == DMA_CHANNEL_13)|| \\\n                                 ((CHANNEL) == DMA_CHANNEL_14)|| \\\n                                 ((CHANNEL) == DMA_CHANNEL_15))\n#else\n#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_1) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_2) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_3) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_4) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_5) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_6) || \\\n                                 ((CHANNEL) == DMA_CHANNEL_7))\n#endif /* DMA_SxCR_CHSEL_3 */\n\n#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \\\n                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \\\n                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) \n\n#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))\n\n#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \\\n                                            ((STATE) == DMA_PINC_DISABLE))\n\n#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \\\n                                        ((STATE) == DMA_MINC_DISABLE))\n\n#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \\\n                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \\\n                                           ((SIZE) == DMA_PDATAALIGN_WORD))\n\n#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \\\n                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \\\n                                       ((SIZE) == DMA_MDATAALIGN_WORD ))\n\n#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \\\n                           ((MODE) == DMA_CIRCULAR) || \\\n                           ((MODE) == DMA_PFCTRL)) \n\n#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \\\n                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \\\n                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \\\n                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) \n\n#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \\\n                                       ((STATE) == DMA_FIFOMODE_ENABLE))\n\n#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \\\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \\\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \\\n                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))\n\n#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \\\n                                    ((BURST) == DMA_MBURST_INC4)   || \\\n                                    ((BURST) == DMA_MBURST_INC8)   || \\\n                                    ((BURST) == DMA_MBURST_INC16))\n\n#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \\\n                                        ((BURST) == DMA_PBURST_INC4)   || \\\n                                        ((BURST) == DMA_PBURST_INC8)   || \\\n                                        ((BURST) == DMA_PBURST_INC16))\n/**\n  * @}\n  */ \n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup DMA_Private_Functions DMA Private Functions\n  * @brief    DMA private  functions \n  * @{\n  */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_DMA_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_dma_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of DMA HAL extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_DMA_EX_H\n#define __STM32F4xx_HAL_DMA_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup DMAEx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup DMAEx_Exported_Types DMAEx Exported Types\n  * @brief DMAEx Exported types\n  * @{\n  */\n   \n/** \n  * @brief  HAL DMA Memory definition  \n  */ \ntypedef enum\n{\n  MEMORY0      = 0x00U,    /*!< Memory 0     */\n  MEMORY1      = 0x01U     /*!< Memory 1     */\n}HAL_DMA_MemoryTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions\n  * @brief   DMAEx Exported functions\n  * @{\n  */\n\n/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions\n  * @brief   Extended features functions\n  * @{\n  */\n\n/* IO operation functions *******************************************************/\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);\n\n/**\n  * @}\n  */\n/**\n  * @}\n  */\n         \n/* Private functions ---------------------------------------------------------*/\n/** @defgroup DMAEx_Private_Functions DMAEx Private Functions\n  * @brief DMAEx Private functions\n  * @{\n  */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__STM32F4xx_HAL_DMA_EX_H*/\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_exti.h\n  * @author  MCD Application Team\n  * @brief   Header file of EXTI HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32f4xx_HAL_EXTI_H\n#define STM32f4xx_HAL_EXTI_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup EXTI EXTI\n  * @brief EXTI HAL module driver\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n\n/** @defgroup EXTI_Exported_Types EXTI Exported Types\n  * @{\n  */\ntypedef enum\n{\n  HAL_EXTI_COMMON_CB_ID          = 0x00U\n} EXTI_CallbackIDTypeDef;\n\n/**\n  * @brief  EXTI Handle structure definition\n  */\ntypedef struct\n{\n  uint32_t Line;                    /*!<  Exti line number */\n  void (* PendingCallback)(void);   /*!<  Exti pending callback */\n} EXTI_HandleTypeDef;\n\n/**\n  * @brief  EXTI Configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t Line;      /*!< The Exti line to be configured. This parameter\n                           can be a value of @ref EXTI_Line */\n  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.\n                           This parameter can be a combination of @ref EXTI_Mode */\n  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter\n                           can be a value of @ref EXTI_Trigger */\n  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.\n                           This parameter is only possible for line 0 to 15. It\n                           can be a value of @ref EXTI_GPIOSel */\n} EXTI_ConfigTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup EXTI_Exported_Constants EXTI Exported Constants\n  * @{\n  */\n\n/** @defgroup EXTI_Line  EXTI Line\n  * @{\n  */\n#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */\n#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */\n#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */\n#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */\n#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */\n#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */\n#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */\n#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */\n#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */\n#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */\n#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */\n#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */\n#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */\n#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */\n#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */\n#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */\n#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */\n#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */\n#if defined(EXTI_IMR_IM18)\n#define EXTI_LINE_18                       (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */\n#else\n#define EXTI_LINE_18                       (EXTI_RESERVED   | 0x12u)    /*!< No interrupt supported in this line */\n#endif /* EXTI_IMR_IM18 */\n#if defined(EXTI_IMR_IM19)\n#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */\n#else\n#define EXTI_LINE_19                       (EXTI_RESERVED   | 0x13u)    /*!< No interrupt supported in this line */\n#endif /* EXTI_IMR_IM19 */\n#if defined(EXTI_IMR_IM20)\n#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */\n#else\n#define EXTI_LINE_20                       (EXTI_RESERVED   | 0x14u)    /*!< No interrupt supported in this line */\n#endif /* EXTI_IMR_IM20 */\n#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */\n#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the RTC Wakeup event */\n#if defined(EXTI_IMR_IM23)\n#define EXTI_LINE_23                       (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */\n#endif /* EXTI_IMR_IM23 */\n\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_Mode  EXTI Mode\n  * @{\n  */\n#define EXTI_MODE_NONE                      0x00000000u\n#define EXTI_MODE_INTERRUPT                 0x00000001u\n#define EXTI_MODE_EVENT                     0x00000002u\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_Trigger  EXTI Trigger\n  * @{\n  */\n\n#define EXTI_TRIGGER_NONE                   0x00000000u\n#define EXTI_TRIGGER_RISING                 0x00000001u\n#define EXTI_TRIGGER_FALLING                0x00000002u\n#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_GPIOSel  EXTI GPIOSel\n  * @brief\n  * @{\n  */\n#define EXTI_GPIOA                          0x00000000u\n#define EXTI_GPIOB                          0x00000001u\n#define EXTI_GPIOC                          0x00000002u\n#if defined (GPIOD)\n#define EXTI_GPIOD                          0x00000003u\n#endif /* GPIOD */\n#if defined (GPIOE)\n#define EXTI_GPIOE                          0x00000004u\n#endif /* GPIOE */\n#if defined (GPIOF)\n#define EXTI_GPIOF                          0x00000005u\n#endif /* GPIOF */\n#if defined (GPIOG)\n#define EXTI_GPIOG                          0x00000006u\n#endif /* GPIOG */\n#if defined (GPIOH)\n#define EXTI_GPIOH                          0x00000007u\n#endif /* GPIOH */\n#if defined (GPIOI)\n#define EXTI_GPIOI                          0x00000008u\n#endif /* GPIOI */\n#if defined (GPIOJ)\n#define EXTI_GPIOJ                          0x00000009u\n#endif /* GPIOJ */\n#if defined (GPIOK)\n#define EXTI_GPIOK                          0x0000000Au\n#endif /* GPIOK */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup EXTI_Exported_Macros EXTI Exported Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private constants --------------------------------------------------------*/\n/** @defgroup EXTI_Private_Constants EXTI Private Constants\n  * @{\n  */\n/**\n  * @brief  EXTI Line property definition\n  */\n#define EXTI_PROPERTY_SHIFT                  24u\n#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)\n#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)\n#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)\n#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)\n\n/**\n  * @brief  EXTI bit usage\n  */\n#define EXTI_PIN_MASK                       0x0000001Fu\n\n/**\n  * @brief  EXTI Mask for interrupt & event mode\n  */\n#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)\n\n/**\n  * @brief  EXTI Mask for trigger possibilities\n  */\n#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)\n\n/**\n  * @brief  EXTI Line number\n  */\n#if defined(EXTI_IMR_IM23)\n#define EXTI_LINE_NB                        24UL\n#else\n#define EXTI_LINE_NB                        23UL\n#endif /* EXTI_IMR_IM23 */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup EXTI_Private_Macros EXTI Private Macros\n  * @{\n  */\n#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \\\n                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \\\n                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \\\n                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))\n\n#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \\\n                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))\n\n#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)\n\n#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)\n\n#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)\n\n#if !defined (GPIOD)\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOH))\n#elif !defined (GPIOE)\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOD) || \\\n                                         ((__PORT__) == EXTI_GPIOH))\n#elif !defined (GPIOF)\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOD) || \\\n                                         ((__PORT__) == EXTI_GPIOE) || \\\n                                         ((__PORT__) == EXTI_GPIOH))\n#elif !defined (GPIOI)\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOD) || \\\n                                         ((__PORT__) == EXTI_GPIOE) || \\\n                                         ((__PORT__) == EXTI_GPIOF) || \\\n                                         ((__PORT__) == EXTI_GPIOG) || \\\n                                         ((__PORT__) == EXTI_GPIOH))\n#elif !defined (GPIOJ)\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOD) || \\\n                                         ((__PORT__) == EXTI_GPIOE) || \\\n                                         ((__PORT__) == EXTI_GPIOF) || \\\n                                         ((__PORT__) == EXTI_GPIOG) || \\\n                                         ((__PORT__) == EXTI_GPIOH) || \\\n                                         ((__PORT__) == EXTI_GPIOI))\n#else\n#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \\\n                                         ((__PORT__) == EXTI_GPIOB) || \\\n                                         ((__PORT__) == EXTI_GPIOC) || \\\n                                         ((__PORT__) == EXTI_GPIOD) || \\\n                                         ((__PORT__) == EXTI_GPIOE) || \\\n                                         ((__PORT__) == EXTI_GPIOF) || \\\n                                         ((__PORT__) == EXTI_GPIOG) || \\\n                                         ((__PORT__) == EXTI_GPIOH) || \\\n                                         ((__PORT__) == EXTI_GPIOI) || \\\n                                         ((__PORT__) == EXTI_GPIOJ) || \\\n                                         ((__PORT__) == EXTI_GPIOK))\n#endif /* GPIOD */\n\n#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup EXTI_Exported_Functions EXTI Exported Functions\n  * @brief    EXTI Exported Functions\n  * @{\n  */\n\n/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions\n  * @brief    Configuration functions\n  * @{\n  */\n/* Configuration functions ****************************************************/\nHAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\nHAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);\nHAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);\nHAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));\nHAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);\n/**\n  * @}\n  */\n\n/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions\n  * @brief    IO operation functions\n  * @{\n  */\n/* IO operation functions *****************************************************/\nvoid HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);\nuint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\nvoid HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);\nvoid HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32f4xx_HAL_EXTI_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash.h\n  * @author  MCD Application Team\n  * @brief   Header file of FLASH HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_FLASH_H\n#define __STM32F4xx_HAL_FLASH_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup FLASH\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup FLASH_Exported_Types FLASH Exported Types\n  * @{\n  */\n \n/**\n  * @brief  FLASH Procedure structure definition\n  */\ntypedef enum \n{\n  FLASH_PROC_NONE = 0U, \n  FLASH_PROC_SECTERASE,\n  FLASH_PROC_MASSERASE,\n  FLASH_PROC_PROGRAM\n} FLASH_ProcedureTypeDef;\n\n/** \n  * @brief  FLASH handle Structure definition  \n  */\ntypedef struct\n{\n  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/\n  \n  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/\n  \n  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/\n  \n  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/\n  \n  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/\n  \n  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/\n  \n  HAL_LockTypeDef             Lock;               /* FLASH locking object                */\n\n  __IO uint32_t               ErrorCode;          /* FLASH error code                    */\n\n}FLASH_ProcessTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup FLASH_Exported_Constants FLASH Exported Constants\n  * @{\n  */  \n/** @defgroup FLASH_Error_Code FLASH Error Code\n  * @brief    FLASH Error Code \n  * @{\n  */ \n#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */\n#define HAL_FLASH_ERROR_RD           0x00000001U    /*!< Read Protection error         */\n#define HAL_FLASH_ERROR_PGS          0x00000002U    /*!< Programming Sequence error    */\n#define HAL_FLASH_ERROR_PGP          0x00000004U    /*!< Programming Parallelism error */\n#define HAL_FLASH_ERROR_PGA          0x00000008U    /*!< Programming Alignment error   */\n#define HAL_FLASH_ERROR_WRP          0x00000010U    /*!< Write protection error        */\n#define HAL_FLASH_ERROR_OPERATION    0x00000020U    /*!< Operation Error               */\n/**\n  * @}\n  */\n  \n/** @defgroup FLASH_Type_Program FLASH Type Program\n  * @{\n  */ \n#define FLASH_TYPEPROGRAM_BYTE        0x00000000U  /*!< Program byte (8-bit) at a specified address           */\n#define FLASH_TYPEPROGRAM_HALFWORD    0x00000001U  /*!< Program a half-word (16-bit) at a specified address   */\n#define FLASH_TYPEPROGRAM_WORD        0x00000002U  /*!< Program a word (32-bit) at a specified address        */\n#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x00000003U  /*!< Program a double word (64-bit) at a specified address */\n/**\n  * @}\n  */\n\n/** @defgroup FLASH_Flag_definition FLASH Flag definition\n  * @brief Flag definition\n  * @{\n  */ \n#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */\n#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */\n#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */\n#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */\n#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */\n#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */\n#if defined(FLASH_SR_RDERR)\n#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< Read Protection error flag (PCROP)        */\n#endif /* FLASH_SR_RDERR */\n#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ \n/**\n  * @}\n  */\n  \n/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition\n  * @brief FLASH Interrupt definition\n  * @{\n  */ \n#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */\n#define FLASH_IT_ERR                   0x02000000U             /*!< Error Interrupt source                  */\n/**\n  * @}\n  */  \n\n/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism\n  * @{\n  */\n#define FLASH_PSIZE_BYTE           0x00000000U\n#define FLASH_PSIZE_HALF_WORD      0x00000100U\n#define FLASH_PSIZE_WORD           0x00000200U\n#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U\n#define CR_PSIZE_MASK              0xFFFFFCFFU\n/**\n  * @}\n  */ \n\n/** @defgroup FLASH_Keys FLASH Keys\n  * @{\n  */ \n#define RDP_KEY                  ((uint16_t)0x00A5)\n#define FLASH_KEY1               0x45670123U\n#define FLASH_KEY2               0xCDEF89ABU\n#define FLASH_OPT_KEY1           0x08192A3BU\n#define FLASH_OPT_KEY2           0x4C5D6E7FU\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n  \n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup FLASH_Exported_Macros FLASH Exported Macros\n  * @{\n  */\n/**\n  * @brief  Set the FLASH Latency.\n  * @param  __LATENCY__ FLASH Latency\n  *         The value of this parameter depend on device used within the same series\n  * @retval none\n  */ \n#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))\n\n/**\n  * @brief  Get the FLASH Latency.\n  * @retval FLASH Latency\n  *          The value of this parameter depend on device used within the same series\n  */ \n#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))\n\n/**\n  * @brief  Enable the FLASH prefetch buffer.\n  * @retval none\n  */ \n#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)\n\n/**\n  * @brief  Disable the FLASH prefetch buffer.\n  * @retval none\n  */ \n#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))\n\n/**\n  * @brief  Enable the FLASH instruction cache.\n  * @retval none\n  */ \n#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)\n\n/**\n  * @brief  Disable the FLASH instruction cache.\n  * @retval none\n  */ \n#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))\n\n/**\n  * @brief  Enable the FLASH data cache.\n  * @retval none\n  */ \n#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)\n\n/**\n  * @brief  Disable the FLASH data cache.\n  * @retval none\n  */ \n#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))\n\n/**\n  * @brief  Resets the FLASH instruction Cache.\n  * @note   This function must be used only when the Instruction Cache is disabled.  \n  * @retval None\n  */\n#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \\\n                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \\\n                                                 }while(0U)\n\n/**\n  * @brief  Resets the FLASH data Cache.\n  * @note   This function must be used only when the data Cache is disabled.  \n  * @retval None\n  */\n#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \\\n                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \\\n                                          }while(0U)\n/**\n  * @brief  Enable the specified FLASH interrupt.\n  * @param  __INTERRUPT__  FLASH interrupt \n  *         This parameter can be any combination of the following values:\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\n  *     @arg FLASH_IT_ERR: Error Interrupt    \n  * @retval none\n  */  \n#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))\n\n/**\n  * @brief  Disable the specified FLASH interrupt.\n  * @param  __INTERRUPT__  FLASH interrupt \n  *         This parameter can be any combination of the following values:\n  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt\n  *     @arg FLASH_IT_ERR: Error Interrupt    \n  * @retval none\n  */  \n#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))\n\n/**\n  * @brief  Get the specified FLASH flag status. \n  * @param  __FLAG__ specifies the FLASH flags to check.\n  *          This parameter can be any combination of the following values:\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag \n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag \n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag\n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\n  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag\n  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)\n  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag\n  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices                             \n  * @retval The new state of __FLAG__ (SET or RESET).\n  */\n#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))\n\n/**\n  * @brief  Clear the specified FLASH flags.\n  * @param  __FLAG__ specifies the FLASH flags to clear.\n  *          This parameter can be any combination of the following values:\n  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag \n  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag \n  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag \n  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag \n  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag\n  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag\n  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)\n  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices   \n  * @retval none\n  */\n#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))\n/**\n  * @}\n  */\n\n/* Include FLASH HAL Extension module */\n#include \"stm32f4xx_hal_flash_ex.h\"\n#include \"stm32f4xx_hal_flash_ramfunc.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup FLASH_Exported_Functions\n  * @{\n  */\n/** @addtogroup FLASH_Exported_Functions_Group1\n  * @{\n  */\n/* Program operation functions  ***********************************************/\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);\n/* FLASH IRQ handler method */\nvoid HAL_FLASH_IRQHandler(void);\n/* Callbacks in non blocking modes */ \nvoid HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);\nvoid HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);\n/**\n  * @}\n  */\n\n/** @addtogroup FLASH_Exported_Functions_Group2\n  * @{\n  */\n/* Peripheral Control functions  **********************************************/\nHAL_StatusTypeDef HAL_FLASH_Unlock(void);\nHAL_StatusTypeDef HAL_FLASH_Lock(void);\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void);\n/* Option bytes control */\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void);\n/**\n  * @}\n  */\n\n/** @addtogroup FLASH_Exported_Functions_Group3\n  * @{\n  */\n/* Peripheral State functions  ************************************************/\nuint32_t HAL_FLASH_GetError(void);\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup FLASH_Private_Variables FLASH Private Variables\n  * @{\n  */\n\n/**\n  * @}\n  */\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup FLASH_Private_Constants FLASH Private Constants\n  * @{\n  */\n\n/** \n  * @brief   ACR register byte 0 (Bits[7:0]) base address  \n  */ \n#define ACR_BYTE0_ADDRESS           0x40023C00U \n/** \n  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  \n  */ \n#define OPTCR_BYTE0_ADDRESS         0x40023C14U\n/** \n  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  \n  */ \n#define OPTCR_BYTE1_ADDRESS         0x40023C15U\n/** \n  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  \n  */ \n#define OPTCR_BYTE2_ADDRESS         0x40023C16U\n/** \n  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  \n  */ \n#define OPTCR_BYTE3_ADDRESS         0x40023C17U\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup FLASH_Private_Macros FLASH Private Macros\n  * @{\n  */\n\n/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters\n  * @{\n  */\n#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \\\n                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \\\n                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \\\n                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  \n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup FLASH_Private_Functions FLASH Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_FLASH_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of FLASH HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_FLASH_EX_H\n#define __STM32F4xx_HAL_FLASH_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup FLASHEx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup FLASHEx_Exported_Types FLASH Exported Types\n  * @{\n  */\n\n/**\n  * @brief  FLASH Erase structure definition\n  */\ntypedef struct\n{\n  uint32_t TypeErase;   /*!< Mass erase or sector Erase.\n                             This parameter can be a value of @ref FLASHEx_Type_Erase */\n\n  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.\n                             This parameter must be a value of @ref FLASHEx_Banks */\n\n  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled\n                             This parameter must be a value of @ref FLASHEx_Sectors */\n\n  uint32_t NbSectors;   /*!< Number of sectors to be erased.\n                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/\n\n  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism\n                             This parameter must be a value of @ref FLASHEx_Voltage_Range */\n\n} FLASH_EraseInitTypeDef;\n\n/**\n  * @brief  FLASH Option Bytes Program structure definition\n  */\ntypedef struct\n{\n  uint32_t OptionType;   /*!< Option byte to be configured.\n                              This parameter can be a value of @ref FLASHEx_Option_Type */\n\n  uint32_t WRPState;     /*!< Write protection activation or deactivation.\n                              This parameter can be a value of @ref FLASHEx_WRP_State */\n\n  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.\n                              The value of this parameter depend on device used within the same series */\n\n  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.\n                              This parameter must be a value of @ref FLASHEx_Banks */        \n\n  uint32_t RDPLevel;     /*!< Set the read protection level.\n                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */\n\n  uint32_t BORLevel;     /*!< Set the BOR Level.\n                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */\n\n  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */\n\n} FLASH_OBProgramInitTypeDef;\n\n/**\n  * @brief  FLASH Advanced Option Bytes Program structure definition\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\ntypedef struct\n{\n  uint32_t OptionType;     /*!< Option byte to be configured for extension.\n                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */\n\n  uint32_t PCROPState;     /*!< PCROP activation or deactivation.\n                                This parameter can be a value of @ref FLASHEx_PCROP_State */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.\n                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\\\n          STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.\n                                This parameter must be a value of @ref FLASHEx_Banks */\n\n  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.\n                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */\n\n  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.\n                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */\n\n  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.\n                                This parameter can be a value of @ref FLASHEx_Dual_Boot */\n\n#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n}FLASH_AdvOBProgramInitTypeDef;\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||\n          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants\n  * @{\n  */\n\n/** @defgroup FLASHEx_Type_Erase FLASH Type Erase\n  * @{\n  */ \n#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */\n#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range\n  * @{\n  */ \n#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */\n#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */\n#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */\n#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_WRP_State FLASH WRP State\n  * @{\n  */ \n#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */\n#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_Option_Type FLASH Option Type\n  * @{\n  */ \n#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */\n#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */\n#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */\n#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection\n  * @{\n  */\n#define OB_RDP_LEVEL_0   ((uint8_t)0xAA)\n#define OB_RDP_LEVEL_1   ((uint8_t)0x55)\n#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 \n                                              it s no more possible to go back to level 1 or 0 */\n/**\n  * @}\n  */ \n  \n/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog\n  * @{\n  */ \n#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */\n#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */\n/**\n  * @}\n  */ \n  \n/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP\n  * @{\n  */ \n#define OB_STOP_NO_RST                 ((uint8_t)0x40) /*!< No reset generated when entering in STOP */\n#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP    */\n/**\n  * @}\n  */ \n\n\n/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY\n  * @{\n  */ \n#define OB_STDBY_NO_RST                ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */\n#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY    */\n/**\n  * @}\n  */    \n\n/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level\n  * @{\n  */  \n#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */\n#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */\n#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */\n#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */\n/**\n  * @}\n  */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup FLASHEx_PCROP_State FLASH PCROP State\n  * @{\n  */ \n#define OB_PCROP_STATE_DISABLE       0x00000000U  /*!< Disable PCROP */\n#define OB_PCROP_STATE_ENABLE        0x00000001U  /*!< Enable PCROP  */\n/**\n  * @}\n  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type\n  * @{\n  */ \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define OPTIONBYTE_PCROP        0x00000001U  /*!< PCROP option byte configuration      */\n#define OPTIONBYTE_BOOTCONFIG   0x00000002U  /*!< BOOTConfig option byte configuration */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n#define OPTIONBYTE_PCROP        0x00000001U  /*!<PCROP option byte configuration */\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/** @defgroup FLASH_Latency FLASH Latency\n  * @{\n  */\n/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */\n#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */\n#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */\n#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */\n#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */\n#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */\n#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */\n#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */\n#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */\n#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */\n#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */\n#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */\n#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */\n#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */\n#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */\n#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/*--------------------------------------------------------------------------------------------------------------*/\n\n/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/ \n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n     \n#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */\n#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */\n#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */\n#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */\n#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */\n#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */\n#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */\n#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */\n#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n/*--------------------------------------------------------------------------------------------------------------*/\n\n/**\n  * @}\n  */ \n  \n\n/** @defgroup FLASHEx_Banks FLASH Banks\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define FLASH_BANK_1     1U /*!< Bank 1   */\n#define FLASH_BANK_2     2U /*!< Bank 2   */\n#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n#define FLASH_BANK_1     1U /*!< Bank 1   */\n#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx\n          STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */ \n    \n/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */\n#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx\n          STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */ \n\n/** @defgroup FLASHEx_Sectors FLASH Sectors\n  * @{\n  */\n/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/   \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */\n#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */\n#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */\n#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */\n#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */\n#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */\n#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */\n#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */\n#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */\n#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */\n#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */\n#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */\n#define FLASH_SECTOR_16    16U /*!< Sector Number 16  */\n#define FLASH_SECTOR_17    17U /*!< Sector Number 17  */\n#define FLASH_SECTOR_18    18U /*!< Sector Number 18  */\n#define FLASH_SECTOR_19    19U /*!< Sector Number 19  */\n#define FLASH_SECTOR_20    20U /*!< Sector Number 20  */\n#define FLASH_SECTOR_21    21U /*!< Sector Number 21  */\n#define FLASH_SECTOR_22    22U /*!< Sector Number 22  */\n#define FLASH_SECTOR_23    23U /*!< Sector Number 23  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/   \n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */\n#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */\n#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */\n#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */\n#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */\n#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */\n#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */\n#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */\n#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */\n#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */\n#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */\n#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */\n#endif /* STM32F413xx || STM32F423xx */\n/*-----------------------------------------------------------------------------------------------------*/      \n\n/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ \n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */\n#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */\n#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */\n#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */\n#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */\n#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */\n#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */\n#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*--------------------------------------------- STM32F401xC -------------------------------------------*/ \n#if defined(STM32F401xC)\n#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */\n#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */\n#endif /* STM32F401xC */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*--------------------------------------------- STM32F410xx -------------------------------------------*/ \n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)\n#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */\n#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */\n#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */\n#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */\n#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */\n#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */\n#define FLASH_SECTOR_6     6U /*!< Sector Number 6   */\n#define FLASH_SECTOR_7     7U /*!< Sector Number 7   */\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/**\n  * @}\n  */ \n\n/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection\n  * @{\n  */\n/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) \n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */\n#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */\n#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */\n#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */\n#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */\n#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */\n#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */\n#define OB_WRP_SECTOR_12      0x00000001U << 12U /*!< Write protection of Sector12    */\n#define OB_WRP_SECTOR_13      0x00000002U << 12U /*!< Write protection of Sector13    */\n#define OB_WRP_SECTOR_14      0x00000004U << 12U /*!< Write protection of Sector14    */\n#define OB_WRP_SECTOR_15      0x00000008U << 12U /*!< Write protection of Sector15    */\n#define OB_WRP_SECTOR_16      0x00000010U << 12U /*!< Write protection of Sector16    */\n#define OB_WRP_SECTOR_17      0x00000020U << 12U /*!< Write protection of Sector17    */\n#define OB_WRP_SECTOR_18      0x00000040U << 12U /*!< Write protection of Sector18    */\n#define OB_WRP_SECTOR_19      0x00000080U << 12U /*!< Write protection of Sector19    */\n#define OB_WRP_SECTOR_20      0x00000100U << 12U /*!< Write protection of Sector20    */\n#define OB_WRP_SECTOR_21      0x00000200U << 12U /*!< Write protection of Sector21    */\n#define OB_WRP_SECTOR_22      0x00000400U << 12U /*!< Write protection of Sector22    */\n#define OB_WRP_SECTOR_23      0x00000800U << 12U /*!< Write protection of Sector23    */\n#define OB_WRP_SECTOR_All     0x00000FFFU << 12U /*!< Write protection of all Sectors */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/ \n#if defined(STM32F413xx) || defined(STM32F423xx)  \n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */\n#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */\n#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */\n#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */\n#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */\n#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */\n#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */\n#define OB_WRP_SECTOR_12      0x00001000U /*!< Write protection of Sector12    */\n#define OB_WRP_SECTOR_13      0x00002000U /*!< Write protection of Sector13    */\n#define OB_WRP_SECTOR_14      0x00004000U /*!< Write protection of Sector14    */\n#define OB_WRP_SECTOR_15      0x00004000U /*!< Write protection of Sector15    */      \n#define OB_WRP_SECTOR_All     0x00007FFFU /*!< Write protection of all Sectors */\n#endif /* STM32F413xx || STM32F423xx */\n/*-----------------------------------------------------------------------------------------------------*/    \n      \n/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ \n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */\n#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */\n#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */\n#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */\n#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */\n#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */\n#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */\n#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*--------------------------------------------- STM32F401xC -------------------------------------------*/\n#if defined(STM32F401xC)\n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */\n#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */\n#endif /* STM32F401xC */\n/*-----------------------------------------------------------------------------------------------------*/\n \n/*--------------------------------------------- STM32F410xx -------------------------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)\n#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */\n#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */\n#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */\n#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */\n#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */\n#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */\n#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */\n#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */\n#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx */\n/*-----------------------------------------------------------------------------------------------------*/\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection\n  * @{\n  */\n/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/   \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) \n#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */\n#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */\n#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */\n#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */\n#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */\n#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */\n#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */\n#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */\n#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */\n#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */\n#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */\n#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */\n#define OB_PCROP_SECTOR_12       0x00000001U /*!< PC Read/Write protection of Sector12     */\n#define OB_PCROP_SECTOR_13       0x00000002U /*!< PC Read/Write protection of Sector13     */\n#define OB_PCROP_SECTOR_14       0x00000004U /*!< PC Read/Write protection of Sector14     */\n#define OB_PCROP_SECTOR_15       0x00000008U /*!< PC Read/Write protection of Sector15     */\n#define OB_PCROP_SECTOR_16       0x00000010U /*!< PC Read/Write protection of Sector16     */\n#define OB_PCROP_SECTOR_17       0x00000020U /*!< PC Read/Write protection of Sector17     */\n#define OB_PCROP_SECTOR_18       0x00000040U /*!< PC Read/Write protection of Sector18     */\n#define OB_PCROP_SECTOR_19       0x00000080U /*!< PC Read/Write protection of Sector19     */\n#define OB_PCROP_SECTOR_20       0x00000100U /*!< PC Read/Write protection of Sector20     */\n#define OB_PCROP_SECTOR_21       0x00000200U /*!< PC Read/Write protection of Sector21     */\n#define OB_PCROP_SECTOR_22       0x00000400U /*!< PC Read/Write protection of Sector22     */\n#define OB_PCROP_SECTOR_23       0x00000800U /*!< PC Read/Write protection of Sector23     */\n#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/*-----------------------------------------------------------------------------------------------------*/\n      \n/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)  \n#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */\n#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */\n#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */\n#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */\n#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */\n#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */\n#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */\n#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */\n#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */\n#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */\n#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */\n#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */\n#define OB_PCROP_SECTOR_12       0x00001000U /*!< PC Read/Write protection of Sector12     */\n#define OB_PCROP_SECTOR_13       0x00002000U /*!< PC Read/Write protection of Sector13     */\n#define OB_PCROP_SECTOR_14       0x00004000U /*!< PC Read/Write protection of Sector14     */\n#define OB_PCROP_SECTOR_15       0x00004000U /*!< PC Read/Write protection of Sector15     */      \n#define OB_PCROP_SECTOR_All      0x00007FFFU /*!< PC Read/Write protection of all Sectors  */\n#endif /* STM32F413xx || STM32F423xx */\n/*-----------------------------------------------------------------------------------------------------*/      \n\n/*--------------------------------------------- STM32F401xC -------------------------------------------*/\n#if defined(STM32F401xC)\n#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */\n#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */\n#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */\n#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */\n#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */\n#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */\n#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */\n#endif /* STM32F401xC */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*--------------------------------------------- STM32F410xx -------------------------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */\n#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */\n#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */\n#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */\n#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */\n#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */\n#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */\n#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */\n#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */\n#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */\n#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */\n#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */\n#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */\n#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*-----------------------------------------------------------------------------------------------------*/\n\n/**\n  * @}\n  */\n  \n/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) \n#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */\n#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define OB_PCROP_DESELECTED     ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */\n#define OB_PCROP_SELECTED       ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n  \n/* Exported macro ------------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup FLASHEx_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup FLASHEx_Exported_Functions_Group1\n  * @{\n  */\n/* Extension Program operation functions  *************************************/\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);\nvoid              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\nHAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);\nvoid              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);\nHAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);\nHAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\nuint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup FLASHEx_Private_Constants FLASH Private Constants\n  * @{\n  */\n/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/ \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define FLASH_SECTOR_TOTAL  24U\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n/*-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define FLASH_SECTOR_TOTAL  16U\n#endif /* STM32F413xx || STM32F423xx */\n\n/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ \n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define FLASH_SECTOR_TOTAL  12U\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n/*--------------------------------------------- STM32F401xC -------------------------------------------*/ \n#if defined(STM32F401xC)\n#define FLASH_SECTOR_TOTAL  6U\n#endif /* STM32F401xC */\n\n/*--------------------------------------------- STM32F410xx -------------------------------------------*/ \n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define FLASH_SECTOR_TOTAL  5U\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)\n#define FLASH_SECTOR_TOTAL  8U\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx */\n\n/** \n  * @brief OPTCR1 register byte 2 (Bits[23:16]) base address  \n  */ \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)  \n#define OPTCR1_BYTE2_ADDRESS         0x40023C1AU\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup FLASHEx_Private_Macros FLASH Private Macros\n  * @{\n  */\n\n/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters\n  * @{\n  */\n\n#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \\\n                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  \n\n#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \\\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \\\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \\\n                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  \n\n#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \\\n                           ((VALUE) == OB_WRPSTATE_ENABLE))  \n\n#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))\n\n#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\\\n                                ((LEVEL) == OB_RDP_LEVEL_1) ||\\\n                                ((LEVEL) == OB_RDP_LEVEL_2))\n\n#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))\n\n#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))\n\n#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))\n\n#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\\\n                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \\\n                             ((VALUE) == OB_PCROP_STATE_ENABLE))  \n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \\\n                       ((VALUE) == OPTIONBYTE_BOOTCONFIG))  \n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  \n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_1)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_2)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_3)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_4)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_5)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_6)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_7)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_8)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_9)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_10) || \\\n                                   ((LATENCY) == FLASH_LATENCY_11) || \\\n                                   ((LATENCY) == FLASH_LATENCY_12) || \\\n                                   ((LATENCY) == FLASH_LATENCY_13) || \\\n                                   ((LATENCY) == FLASH_LATENCY_14) || \\\n                                   ((LATENCY) == FLASH_LATENCY_15))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_1)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_2)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_3)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_4)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_5)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_6)  || \\\n                                   ((LATENCY) == FLASH_LATENCY_7))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\\\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \\\n                             ((BANK) == FLASH_BANK_2)  || \\\n                             ((BANK) == FLASH_BANK_BOTH))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\\\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\\\n                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\\\n                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15))\n#endif /* STM32F413xx || STM32F423xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n#if defined(STM32F401xC)\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))\n#endif /* STM32F401xC */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_4))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)\n#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\\\n                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx */\n\n#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \\\n                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))\n\n#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))\n  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F413xx) || defined(STM32F423xx) \n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F413xx || STM32F423xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F401xC)\n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F401xC */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\\\n    defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n   \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))      \n#endif /* STM32F413xx || STM32F423xx */\n\n#if defined(STM32F401xC)\n#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F401xC */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\\\n    defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))\n#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) \n#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup FLASHEx_Private_Functions FLASH Private Functions\n  * @{\n  */\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);\nvoid FLASH_FlushCaches(void);\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_FLASH_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash_ramfunc.h\n  * @author  MCD Application Team\n  * @brief   Header file of FLASH RAMFUNC driver.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_FLASH_RAMFUNC_H\n#define __STM32F4xx_FLASH_RAMFUNC_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup FLASH_RAMFUNC\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup FLASH_RAMFUNC_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1\n  * @{\n  */   \n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  \n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __STM32F4xx_FLASH_RAMFUNC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_gpio.h\n  * @author  MCD Application Team\n  * @brief   Header file of GPIO HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_GPIO_H\n#define __STM32F4xx_HAL_GPIO_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup GPIO\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup GPIO_Exported_Types GPIO Exported Types\n  * @{\n  */\n\n/** \n  * @brief GPIO Init structure definition  \n  */ \ntypedef struct\n{\n  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.\n                           This parameter can be any value of @ref GPIO_pins_define */\n\n  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.\n                           This parameter can be a value of @ref GPIO_mode_define */\n\n  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.\n                           This parameter can be a value of @ref GPIO_pull_define */\n\n  uint32_t Speed;     /*!< Specifies the speed for the selected pins.\n                           This parameter can be a value of @ref GPIO_speed_define */\n\n  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. \n                            This parameter can be a value of @ref GPIO_Alternate_function_selection */\n}GPIO_InitTypeDef;\n\n/** \n  * @brief  GPIO Bit SET and Bit RESET enumeration \n  */\ntypedef enum\n{\n  GPIO_PIN_RESET = 0,\n  GPIO_PIN_SET\n}GPIO_PinState;\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup GPIO_Exported_Constants GPIO Exported Constants\n  * @{\n  */ \n\n/** @defgroup GPIO_pins_define GPIO pins define\n  * @{\n  */\n#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */\n#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */\n#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */\n#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */\n#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */\n#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */\n#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */\n#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */\n#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */\n#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */\n#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */\n#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */\n#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */\n#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */\n#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */\n#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */\n#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */\n\n#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_mode_define GPIO mode define\n  * @brief GPIO Configuration Mode \n  *        Elements values convention: 0xX0yz00YZ\n  *           - X  : GPIO mode or EXTI Mode\n  *           - y  : External IT or Event trigger detection \n  *           - z  : IO configuration on External IT or Event\n  *           - Y  : Output type (Push Pull or Open Drain)\n  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)\n  * @{\n  */\n#define  GPIO_MODE_INPUT                        MODE_INPUT                                               /*!< Input Floating Mode                   */\n#define  GPIO_MODE_OUTPUT_PP                    (MODE_PP | MODE_OUTPUT)                                  /*!< Output Push Pull Mode                 */\n#define  GPIO_MODE_OUTPUT_OD                    (MODE_OD | MODE_OUTPUT)                                  /*!< Output Open Drain Mode                */\n#define  GPIO_MODE_AF_PP                        (MODE_PP | MODE_AF)                                      /*!< Alternate Function Push Pull Mode     */\n#define  GPIO_MODE_AF_OD                        (MODE_OD | MODE_AF)                                      /*!< Alternate Function Open Drain Mode    */\n\n#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                              /*!< Analog Mode  */\n\n#define  GPIO_MODE_IT_RISING                    (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE)                 /*!< External Interrupt Mode with Rising edge trigger detection          */\n#define  GPIO_MODE_IT_FALLING                   (EXTI_MODE | GPIO_MODE_IT               | FALLING_EDGE)  /*!< External Interrupt Mode with Falling edge trigger detection         */\n#define  GPIO_MODE_IT_RISING_FALLING            (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE)  /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */\n\n#define  GPIO_MODE_EVT_RISING                   (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE)                /*!< External Event Mode with Rising edge trigger detection               */\n#define  GPIO_MODE_EVT_FALLING                  (EXTI_MODE | GPIO_MODE_EVT               | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection              */\n#define  GPIO_MODE_EVT_RISING_FALLING           (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection       */\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_speed_define  GPIO speed define\n  * @brief GPIO Output Maximum frequency\n  * @{\n  */\n#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */\n#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */\n#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */\n#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */\n/**\n  * @}\n  */\n\n /** @defgroup GPIO_pull_define GPIO pull define\n   * @brief GPIO Pull-Up or Pull-Down Activation\n   * @{\n   */  \n#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */\n#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */\n#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIO_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n\n/**\n  * @brief  Checks whether the specified EXTI line flag is set or not.\n  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.\n  *         This parameter can be GPIO_PIN_x where x can be(0..15)\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\n  */\n#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\n\n/**\n  * @brief  Clears the EXTI's line pending flags.\n  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\n  * @retval None\n  */\n#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\n\n/**\n  * @brief  Checks whether the specified EXTI line is asserted or not.\n  * @param  __EXTI_LINE__ specifies the EXTI line to check.\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\n  * @retval The new state of __EXTI_LINE__ (SET or RESET).\n  */\n#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))\n\n/**\n  * @brief  Clears the EXTI's line pending bits.\n  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.\n  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)\n  * @retval None\n  */\n#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))\n\n/**\n  * @brief  Generates a Software interrupt on selected EXTI line.\n  * @param  __EXTI_LINE__ specifies the EXTI line to check.\n  *          This parameter can be GPIO_PIN_x where x can be(0..15)\n  * @retval None\n  */\n#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))\n/**\n  * @}\n  */\n\n/* Include GPIO HAL Extension module */\n#include \"stm32f4xx_hal_gpio_ex.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup GPIO_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup GPIO_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization and de-initialization functions *****************************/\nvoid  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);\nvoid  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);\n/**\n  * @}\n  */\n\n/** @addtogroup GPIO_Exported_Functions_Group2\n  * @{\n  */\n/* IO operation functions *****************************************************/\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);\nvoid HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup GPIO_Private_Constants GPIO Private Constants\n  * @{\n  */\n#define GPIO_MODE             0x00000003U\n#define EXTI_MODE             0x10000000U\n#define GPIO_MODE_IT          0x00010000U\n#define GPIO_MODE_EVT         0x00020000U\n#define RISING_EDGE           0x00100000U\n#define FALLING_EDGE          0x00200000U\n#define GPIO_OUTPUT_TYPE      0x00000010U\n\n#define  MODE_INPUT           0x00000000U           /*!< Input Mode                   */\n#define  MODE_OUTPUT          0x00000001U           /*!< Output Mode                  */\n#define  MODE_AF              0x00000002U           /*!< Alternate Function Mode      */\n#define  MODE_ANALOG          0x00000003U           /*!< Analog Mode                  */\n\n#define  MODE_PP              0x00000000U           /*!< Push Pull Mode               */\n#define  MODE_OD              0x00000010U           /*!< Open Drain Mode              */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup GPIO_Private_Macros GPIO Private Macros\n  * @{\n  */\n#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))\n#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))\n#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\\\n                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\\\n                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\\\n                            ((MODE) == GPIO_MODE_AF_PP)              ||\\\n                            ((MODE) == GPIO_MODE_AF_OD)              ||\\\n                            ((MODE) == GPIO_MODE_IT_RISING)          ||\\\n                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\\\n                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\\\n                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\\\n                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\\\n                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\\\n                            ((MODE) == GPIO_MODE_ANALOG))\n#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \\\n                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))\n#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \\\n                            ((PULL) == GPIO_PULLDOWN))\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup GPIO_Private_Functions GPIO Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_GPIO_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_gpio_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of GPIO HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_GPIO_EX_H\n#define __STM32F4xx_HAL_GPIO_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup GPIOEx GPIOEx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants\n  * @{\n  */\n  \n/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection\n  * @{\n  */\n\n/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/\n#if defined(STM32F429xx) || defined(STM32F439xx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n\n/** \n  * @brief   AF 11 selection  \n  */ \n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 13 selection  \n  */ \n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */\n\n/** \n  * @brief   AF 14 selection  \n  */\n#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F429xx || STM32F439xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F427xx/STM32F437xx------------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */\n/** @brief  GPIO_Legacy \n  */\n#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3   /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n\n/** \n  * @brief   AF 11 selection  \n  */ \n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 13 selection  \n  */ \n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F427xx || STM32F437xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F407xx/STM32F417xx------------------*/\n#if defined(STM32F407xx) || defined(STM32F417xx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n\n/** \n  * @brief   AF 11 selection  \n  */ \n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 13 selection  \n  */ \n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F407xx || STM32F417xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F405xx/STM32F415xx------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F405xx || STM32F415xx */\n\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------------- STM32F401xx------------------------*/\n#if defined(STM32F401xC) || defined(STM32F401xE) \n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping        */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */\n\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F401xC || STM32F401xE */\n/*----------------------------------------------------------------------------*/\n\n/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   \n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */\n#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */\n\n/** \n  * @brief   AF 9 selection \n  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */  \n#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */\n#define GPIO_AF10_FMC           ((uint8_t)0x0A)  /* FMC Alternate Function mapping    */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n/*----------------------------------------------------------------------------*/\n\n/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)   \n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n#define GPIO_AF3_DFSDM2        ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */   \n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */\n#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping     */   \n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */\n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */\n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\n#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */\n\n/** \n  * @brief   AF 9 selection \n  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */\n\n/** \n  * @brief   AF 10 selection  \n  */\n#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */\n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */\n#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */\n#define GPIO_AF10_FSMC          ((uint8_t)0x0A)  /* FSMC Alternate Function mapping   */\n\n/** \n  * @brief   AF 11 selection  \n  */\n#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */\n#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */\n#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */\n   \n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */\n#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */\n\n/** \n  * @brief   AF 14 selection  \n  */ \n#define GPIO_AF14_RNG           ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */\n   \n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F413xx || STM32F423xx */\n\n/*---------------------------------------- STM32F411xx------------------------*/\n#if defined(STM32F411xE) \n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */\n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */\n#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */\n#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F411xE */\n\n/*---------------------------------------- STM32F410xx------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */\n#if defined(STM32F410Cx) || defined(STM32F410Rx)  \n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#endif /* STM32F410Cx || STM32F410Rx */   \n\n/** \n  * @brief   AF 6 selection  \n  */\n#define GPIO_AF6_SPI1          ((uint8_t)0x06)  /* SPI1 Alternate Function mapping  */\n#if defined(STM32F410Cx) || defined(STM32F410Rx)   \n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */\n#endif /* STM32F410Cx || STM32F410Rx */   \n#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */\n#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/*---------------------------------------- STM32F446xx -----------------------*/\n#if defined(STM32F446xx)\n/**\n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n#define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping   */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */\n#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping  */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2/I2S2 Alternate Function mapping  */\n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4 Alternate Function mapping       */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_UART5         ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */\n#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2/I2S2 Alternate Function mapping  */\n#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIFRX Alternate Function mapping      */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /* SPDIFRX Alternate Function mapping  */\n#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping  */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping   */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping  */\n\n/** \n  * @brief   AF 11 selection  \n  */ \n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 13 selection  \n  */ \n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n\n#endif /* STM32F446xx */\n/*----------------------------------------------------------------------------*/\n\n/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/\n#if defined(STM32F469xx) || defined(STM32F479xx)\n/** \n  * @brief   AF 0 selection  \n  */ \n#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */\n#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */\n#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */\n#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */\n#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */\n\n/** \n  * @brief   AF 1 selection  \n  */ \n#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */\n#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */\n\n/** \n  * @brief   AF 2 selection  \n  */ \n#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */\n#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */\n#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */\n\n/** \n  * @brief   AF 3 selection  \n  */ \n#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */\n#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */\n#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */\n#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */\n\n/** \n  * @brief   AF 4 selection  \n  */ \n#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */\n#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */\n#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */\n\n/** \n  * @brief   AF 5 selection  \n  */ \n#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */\n#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */\n#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */\n#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */\n#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */\n#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */\n#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */\n\n/** \n  * @brief   AF 6 selection  \n  */ \n#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */\n#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */\n#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */\n\n/** \n  * @brief   AF 7 selection  \n  */ \n#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */\n#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */\n#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */\n#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */\n\n/** \n  * @brief   AF 8 selection  \n  */ \n#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */\n#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */\n#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */\n#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */\n#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */\n\n/** \n  * @brief   AF 9 selection \n  */ \n#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */\n#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */\n#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */\n#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */\n#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */\n#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */\n#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */\n\n/** \n  * @brief   AF 10 selection  \n  */ \n#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */\n#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */\n#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */\n\n/** \n  * @brief   AF 11 selection  \n  */ \n#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */\n\n/** \n  * @brief   AF 12 selection  \n  */ \n#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */\n#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */\n#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */\n\n/** \n  * @brief   AF 13 selection  \n  */ \n#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */\n#define GPIO_AF13_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping  */\n\n/** \n  * @brief   AF 14 selection  \n  */\n#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */\n\n/** \n  * @brief   AF 15 selection  \n  */ \n#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */\n\n#endif /* STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Constants GPIO Private Constants\n  * @{\n  */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Macros GPIO Private Macros\n  * @{\n  */\n/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index\n  * @{\n  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U :\\\n                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U :\\\n                                               ((__GPIOx__) == (GPIOH))? 7U :\\\n                                               ((__GPIOx__) == (GPIOI))? 8U :\\\n                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) \n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) \n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n\n#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U :\\\n                                               ((__GPIOx__) == (GPIOF))? 5U :\\\n                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)\n#endif /* STM32F446xx || STM32F412Zx  || STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U :\\\n                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)\n#endif /* STM32F412Vx */\n#if defined(STM32F412Rx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U :\\\n                                               ((__GPIOx__) == (GPIOD))? 3U : 7U)\n#endif /* STM32F412Rx */\n#if defined(STM32F412Cx)\n#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\\\n                                               ((__GPIOx__) == (GPIOB))? 1U :\\\n                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)\n#endif /* STM32F412Cx */\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function\n  * @{\n  */  \n/*------------------------- STM32F429xx/STM32F439xx---------------------------*/\n#if defined(STM32F429xx) || defined(STM32F439xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \\\n                          ((AF) == GPIO_AF14_LTDC))\n\n#endif /* STM32F429xx || STM32F439xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F427xx/STM32F437xx------------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))\n\n#endif /* STM32F427xx || STM32F437xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F407xx/STM32F417xx------------------*/\n#if defined(STM32F407xx) || defined(STM32F417xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F407xx || STM32F417xx */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F405xx/STM32F415xx------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \\\n                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F405xx || STM32F415xx */\n\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------------- STM32F401xx------------------------*/\n#if defined(STM32F401xC) || defined(STM32F401xE)\n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF12_SDIO)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM9)       || \\\n                          ((AF) == GPIO_AF3_TIM10)      || ((AF) == GPIO_AF3_TIM11)      || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF7_USART1)     || \\\n                          ((AF) == GPIO_AF7_USART2)     || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF15_EVENTOUT))\n#endif /* STM32F401xC || STM32F401xE */\n/*----------------------------------------------------------------------------*/\n/*---------------------------------------- STM32F410xx------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) \n#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/*---------------------------------------- STM32F411xx------------------------*/\n#if defined(STM32F411xE) \n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \\\n                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \\\n                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \\\n                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \\\n                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))\n\n#endif /* STM32F411xE */\n/*----------------------------------------------------------------------------*/\n\n/*----------------------------------------------- STM32F446xx ----------------*/\n#if defined(STM32F446xx) \n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \\\n                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \\\n                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \\\n                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \\\n                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \\\n                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \\\n                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \\\n                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))\n\n#endif /* STM32F446xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------------------------------- STM32F469xx/STM32F479xx --------*/\n#if defined(STM32F469xx) || defined(STM32F479xx) \n#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \\\n                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \\\n                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \\\n                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \\\n                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \\\n                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \\\n                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \\\n                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \\\n                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \\\n                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \\\n                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \\\n                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \\\n                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \\\n                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \\\n                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \\\n                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \\\n                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \\\n                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \\\n                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \\\n                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \\\n                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \\\n                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \\\n                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))\n\n#endif /* STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  \n#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------STM32F413xx/STM32F423xx-----------------------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)  \n#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 13U))\n#endif /* STM32F413xx || STM32F423xx */\n/*----------------------------------------------------------------------------*/\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup GPIOEx_Private_Functions GPIO Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n  \n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_GPIO_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_i2c.h\n  * @author  MCD Application Team\n  * @brief   Header file of I2C HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_I2C_H\n#define __STM32F4xx_HAL_I2C_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup I2C\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup I2C_Exported_Types I2C Exported Types\n  * @{\n  */\n\n/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition\n  * @brief  I2C Configuration Structure definition\n  * @{\n  */\ntypedef struct\n{\n  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.\n                                  This parameter must be set to a value lower than 400kHz */\n\n  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.\n                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */\n\n  uint32_t OwnAddress1;      /*!< Specifies the first device own address.\n                                  This parameter can be a 7-bit or 10-bit address. */\n\n  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.\n                                  This parameter can be a value of @ref I2C_addressing_mode */\n\n  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.\n                                  This parameter can be a value of @ref I2C_dual_addressing_mode */\n\n  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected\n                                  This parameter can be a 7-bit address. */\n\n  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.\n                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */\n\n  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.\n                                  This parameter can be a value of @ref I2C_nostretch_mode */\n\n} I2C_InitTypeDef;\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_state_structure_definition HAL state structure definition\n  * @brief  HAL State structure definition\n  * @note  HAL I2C State value coding follow below described bitmap :\n  *          b7-b6  Error information\n  *             00 : No Error\n  *             01 : Abort (Abort user request on going)\n  *             10 : Timeout\n  *             11 : Error\n  *          b5     Peripheral initialization status\n  *             0  : Reset (Peripheral not initialized)\n  *             1  : Init done (Peripheral initialized and ready to use. HAL I2C Init function called)\n  *          b4     (not used)\n  *             x  : Should be set to 0\n  *          b3\n  *             0  : Ready or Busy (No Listen mode ongoing)\n  *             1  : Listen (Peripheral in Address Listen Mode)\n  *          b2     Intrinsic process state\n  *             0  : Ready\n  *             1  : Busy (Peripheral busy with some configuration or internal operations)\n  *          b1     Rx state\n  *             0  : Ready (no Rx operation ongoing)\n  *             1  : Busy (Rx operation ongoing)\n  *          b0     Tx state\n  *             0  : Ready (no Tx operation ongoing)\n  *             1  : Busy (Tx operation ongoing)\n  * @{\n  */\ntypedef enum\n{\n  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */\n  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */\n  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */\n  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */\n  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */\n  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */\n  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission\n                                                 process is ongoing                         */\n  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception\n                                                 process is ongoing                         */\n  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */\n  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */\n  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */\n\n} HAL_I2C_StateTypeDef;\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_mode_structure_definition HAL mode structure definition\n  * @brief  HAL Mode structure definition\n  * @note  HAL I2C Mode value coding follow below described bitmap :\\n\n  *          b7     (not used)\\n\n  *             x  : Should be set to 0\\n\n  *          b6\\n\n  *             0  : None\\n\n  *             1  : Memory (HAL I2C communication is in Memory Mode)\\n\n  *          b5\\n\n  *             0  : None\\n\n  *             1  : Slave (HAL I2C communication is in Slave Mode)\\n\n  *          b4\\n\n  *             0  : None\\n\n  *             1  : Master (HAL I2C communication is in Master Mode)\\n\n  *          b3-b2-b1-b0  (not used)\\n\n  *             xxxx : Should be set to 0000\n  * @{\n  */\ntypedef enum\n{\n  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */\n  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */\n  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */\n  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */\n\n} HAL_I2C_ModeTypeDef;\n\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Error_Code_definition I2C Error Code definition\n  * @brief  I2C Error Code definition\n  * @{\n  */\n#define HAL_I2C_ERROR_NONE              0x00000000U    /*!< No error              */\n#define HAL_I2C_ERROR_BERR              0x00000001U    /*!< BERR error            */\n#define HAL_I2C_ERROR_ARLO              0x00000002U    /*!< ARLO error            */\n#define HAL_I2C_ERROR_AF                0x00000004U    /*!< AF error              */\n#define HAL_I2C_ERROR_OVR               0x00000008U    /*!< OVR error             */\n#define HAL_I2C_ERROR_DMA               0x00000010U    /*!< DMA transfer error    */\n#define HAL_I2C_ERROR_TIMEOUT           0x00000020U    /*!< Timeout Error         */\n#define HAL_I2C_ERROR_SIZE              0x00000040U    /*!< Size Management error */\n#define HAL_I2C_ERROR_DMA_PARAM         0x00000080U    /*!< DMA Parameter Error   */\n#define HAL_I2C_WRONG_START             0x00000200U    /*!< Wrong start Error     */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n#define HAL_I2C_ERROR_INVALID_CALLBACK  0x00000100U    /*!< Invalid Callback error */\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition\n  * @brief  I2C handle Structure definition\n  * @{\n  */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\ntypedef struct __I2C_HandleTypeDef\n#else\ntypedef struct\n#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */\n{\n  I2C_TypeDef                *Instance;      /*!< I2C registers base address               */\n\n  I2C_InitTypeDef            Init;           /*!< I2C communication parameters             */\n\n  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer           */\n\n  uint16_t                   XferSize;       /*!< I2C transfer size                        */\n\n  __IO uint16_t              XferCount;      /*!< I2C transfer counter                     */\n\n  __IO uint32_t              XferOptions;    /*!< I2C transfer options                     */\n\n  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state and mode\n                                                  context for internal usage               */\n\n  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters             */\n\n  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters             */\n\n  HAL_LockTypeDef            Lock;           /*!< I2C locking object                       */\n\n  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                  */\n\n  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                   */\n\n  __IO uint32_t              ErrorCode;      /*!< I2C Error code                           */\n\n  __IO uint32_t              Devaddress;     /*!< I2C Target device address                */\n\n  __IO uint32_t              Memaddress;     /*!< I2C Target memory address                */\n\n  __IO uint32_t              MemaddSize;     /*!< I2C Target memory address  size          */\n\n  __IO uint32_t              EventCount;     /*!< I2C Event counter                        */\n\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */\n  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */\n  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */\n  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */\n  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */\n  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */\n  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */\n  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */\n  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */\n\n  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */\n\n  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */\n  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */\n\n#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */\n} I2C_HandleTypeDef;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  HAL I2C Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */\n  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */\n  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */\n  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */\n  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */\n  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */\n  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */\n  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */\n  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */\n\n  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */\n  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */\n\n} HAL_I2C_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL I2C Callback pointer definition\n  */\ntypedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */\ntypedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */\n\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup I2C_Exported_Constants I2C Exported Constants\n  * @{\n  */\n\n/** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode\n  * @{\n  */\n#define I2C_DUTYCYCLE_2                 0x00000000U\n#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY\n/**\n  * @}\n  */\n\n/** @defgroup I2C_addressing_mode I2C addressing mode\n  * @{\n  */\n#define I2C_ADDRESSINGMODE_7BIT         0x00004000U\n#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | 0x00004000U)\n/**\n  * @}\n  */\n\n/** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode\n  * @{\n  */\n#define I2C_DUALADDRESS_DISABLE        0x00000000U\n#define I2C_DUALADDRESS_ENABLE         I2C_OAR2_ENDUAL\n/**\n  * @}\n  */\n\n/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode\n  * @{\n  */\n#define I2C_GENERALCALL_DISABLE        0x00000000U\n#define I2C_GENERALCALL_ENABLE         I2C_CR1_ENGC\n/**\n  * @}\n  */\n\n/** @defgroup I2C_nostretch_mode I2C nostretch mode\n  * @{\n  */\n#define I2C_NOSTRETCH_DISABLE          0x00000000U\n#define I2C_NOSTRETCH_ENABLE           I2C_CR1_NOSTRETCH\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size\n  * @{\n  */\n#define I2C_MEMADD_SIZE_8BIT            0x00000001U\n#define I2C_MEMADD_SIZE_16BIT           0x00000010U\n/**\n  * @}\n  */\n\n/** @defgroup I2C_XferDirection_definition I2C XferDirection definition\n  * @{\n  */\n#define I2C_DIRECTION_RECEIVE           0x00000000U\n#define I2C_DIRECTION_TRANSMIT          0x00000001U\n/**\n  * @}\n  */\n\n/** @defgroup I2C_XferOptions_definition I2C XferOptions definition\n  * @{\n  */\n#define  I2C_FIRST_FRAME                0x00000001U\n#define  I2C_FIRST_AND_NEXT_FRAME       0x00000002U\n#define  I2C_NEXT_FRAME                 0x00000004U\n#define  I2C_FIRST_AND_LAST_FRAME       0x00000008U\n#define  I2C_LAST_FRAME_NO_STOP         0x00000010U\n#define  I2C_LAST_FRAME                 0x00000020U\n\n/* List of XferOptions in usage of :\n * 1- Restart condition in all use cases (direction change or not)\n */\n#define  I2C_OTHER_FRAME                (0x00AA0000U)\n#define  I2C_OTHER_AND_LAST_FRAME       (0xAA000000U)\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition\n  * @brief I2C Interrupt definition\n  *        Elements values convention: 0xXXXXXXXX\n  *           - XXXXXXXX  : Interrupt control mask\n  * @{\n  */\n#define I2C_IT_BUF                      I2C_CR2_ITBUFEN\n#define I2C_IT_EVT                      I2C_CR2_ITEVTEN\n#define I2C_IT_ERR                      I2C_CR2_ITERREN\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Flag_definition I2C Flag definition\n  * @{\n  */\n\n#define I2C_FLAG_OVR                    0x00010800U\n#define I2C_FLAG_AF                     0x00010400U\n#define I2C_FLAG_ARLO                   0x00010200U\n#define I2C_FLAG_BERR                   0x00010100U\n#define I2C_FLAG_TXE                    0x00010080U\n#define I2C_FLAG_RXNE                   0x00010040U\n#define I2C_FLAG_STOPF                  0x00010010U\n#define I2C_FLAG_ADD10                  0x00010008U\n#define I2C_FLAG_BTF                    0x00010004U\n#define I2C_FLAG_ADDR                   0x00010002U\n#define I2C_FLAG_SB                     0x00010001U\n#define I2C_FLAG_DUALF                  0x00100080U\n#define I2C_FLAG_GENCALL                0x00100010U\n#define I2C_FLAG_TRA                    0x00100004U\n#define I2C_FLAG_BUSY                   0x00100002U\n#define I2C_FLAG_MSL                    0x00100001U\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macros -----------------------------------------------------------*/\n\n/** @defgroup I2C_Exported_Macros I2C Exported Macros\n  * @{\n  */\n\n/** @brief Reset I2C handle state.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @retval None\n  */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \\\n                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \\\n                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\\n                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\\n                                                                  } while(0)\n#else\n#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)\n#endif\n\n/** @brief  Enable or disable the specified I2C interrupts.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.\n  *         This parameter can be one of the following values:\n  *            @arg I2C_IT_BUF: Buffer interrupt enable\n  *            @arg I2C_IT_EVT: Event interrupt enable\n  *            @arg I2C_IT_ERR: Error interrupt enable\n  * @retval None\n  */\n#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))\n#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\n\n/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg I2C_IT_BUF: Buffer interrupt enable\n  *            @arg I2C_IT_EVT: Event interrupt enable\n  *            @arg I2C_IT_ERR: Error interrupt enable\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\n  */\n#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\n\n/** @brief  Checks whether the specified I2C flag is set or not.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag\n  *            @arg I2C_FLAG_AF: Acknowledge failure flag\n  *            @arg I2C_FLAG_ARLO: Arbitration lost flag\n  *            @arg I2C_FLAG_BERR: Bus error flag\n  *            @arg I2C_FLAG_TXE: Data register empty flag\n  *            @arg I2C_FLAG_RXNE: Data register not empty flag\n  *            @arg I2C_FLAG_STOPF: Stop detection flag\n  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag\n  *            @arg I2C_FLAG_BTF: Byte transfer finished flag\n  *            @arg I2C_FLAG_ADDR: Address sent flag\n  *                                Address matched flag\n  *            @arg I2C_FLAG_SB: Start bit flag\n  *            @arg I2C_FLAG_DUALF: Dual flag\n  *            @arg I2C_FLAG_GENCALL: General call header flag\n  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag\n  *            @arg I2C_FLAG_BUSY: Bus busy flag\n  *            @arg I2C_FLAG_MSL: Master/Slave flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16U)) == 0x01U) ? \\\n                                                  (((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) : \\\n                                                  (((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET))\n\n/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @param  __FLAG__ specifies the flag to clear.\n  *         This parameter can be any combination of the following values:\n  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)\n  *            @arg I2C_FLAG_AF: Acknowledge failure flag\n  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)\n  *            @arg I2C_FLAG_BERR: Bus error flag\n  * @retval None\n  */\n#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))\n\n/** @brief  Clears the I2C ADDR pending flag.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.\n  * @retval None\n  */\n#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__)    \\\n  do{                                           \\\n    __IO uint32_t tmpreg = 0x00U;               \\\n    tmpreg = (__HANDLE__)->Instance->SR1;       \\\n    tmpreg = (__HANDLE__)->Instance->SR2;       \\\n    UNUSED(tmpreg);                             \\\n  } while(0)\n\n/** @brief  Clears the I2C STOPF pending flag.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @retval None\n  */\n#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__)           \\\n  do{                                                  \\\n    __IO uint32_t tmpreg = 0x00U;                      \\\n    tmpreg = (__HANDLE__)->Instance->SR1;              \\\n    SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);  \\\n    UNUSED(tmpreg);                                    \\\n  } while(0)\n\n/** @brief  Enable the specified I2C peripheral.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @retval None\n  */\n#define __HAL_I2C_ENABLE(__HANDLE__)                  SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)\n\n/** @brief  Disable the specified I2C peripheral.\n  * @param  __HANDLE__ specifies the I2C Handle.\n  * @retval None\n  */\n#define __HAL_I2C_DISABLE(__HANDLE__)                 CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)\n\n/**\n  * @}\n  */\n\n/* Include I2C HAL Extension module */\n#include \"stm32f4xx_hal_i2c_ex.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup I2C_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\n  * @{\n  */\n/* Initialization and de-initialization functions******************************/\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);\nHAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);\n\n/* Callbacks Register/UnRegister functions  ***********************************/\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\nHAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);\n\nHAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions\n  * @{\n  */\n/* IO operation functions  ****************************************************/\n/******* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);\n\n/******* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\n\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);\n\n/******* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);\n\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);\n/**\n  * @}\n  */\n\n/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\n * @{\n */\n/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);\nvoid HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);\nvoid HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);\n/**\n  * @}\n  */\n\n/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\n  * @{\n  */\n/* Peripheral State, Mode and Error functions  *********************************/\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);\nHAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);\nuint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup I2C_Private_Constants I2C Private Constants\n  * @{\n  */\n#define I2C_FLAG_MASK                    0x0000FFFFU\n#define I2C_MIN_PCLK_FREQ_STANDARD       2000000U     /*!< 2 MHz                     */\n#define I2C_MIN_PCLK_FREQ_FAST           4000000U     /*!< 4 MHz                     */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup I2C_Private_Macros I2C Private Macros\n  * @{\n  */\n\n#define I2C_MIN_PCLK_FREQ(__PCLK__, __SPEED__)             (((__SPEED__) <= 100000U) ? ((__PCLK__) < I2C_MIN_PCLK_FREQ_STANDARD) : ((__PCLK__) < I2C_MIN_PCLK_FREQ_FAST))\n#define I2C_CCR_CALCULATION(__PCLK__, __SPEED__, __COEFF__)     (((((__PCLK__) - 1U)/((__SPEED__) * (__COEFF__))) + 1U) & I2C_CCR_CCR)\n#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000U)\n#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000U) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))\n#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            ((I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U) < 4U)? 4U:I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 2U))\n#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 3U) : (I2C_CCR_CALCULATION((__PCLK__), (__SPEED__), 25U) | I2C_DUTYCYCLE_16_9))\n#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000U)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \\\n                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0U)? 1U : \\\n                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))\n\n#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (uint8_t)(~I2C_OAR1_ADD0)))\n#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))\n\n#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))\n#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0)))\n#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1))))\n\n#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))\n#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))\n\n/** @defgroup I2C_IS_RTC_Definitions I2C Private macros to check input parameters\n  * @{\n  */\n#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \\\n                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))\n#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \\\n                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))\n#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \\\n                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLE))\n#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \\\n                                   ((CALL) == I2C_GENERALCALL_ENABLE))\n#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \\\n                                    ((STRETCH) == I2C_NOSTRETCH_ENABLE))\n#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \\\n                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))\n#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 400000U))\n#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U)\n#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U)\n#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == I2C_FIRST_FRAME)              || \\\n                                                       ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME)     || \\\n                                                       ((REQUEST) == I2C_NEXT_FRAME)               || \\\n                                                       ((REQUEST) == I2C_FIRST_AND_LAST_FRAME)     || \\\n                                                       ((REQUEST) == I2C_LAST_FRAME)               || \\\n                                                       ((REQUEST) == I2C_LAST_FRAME_NO_STOP)       || \\\n                                                       IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))\n\n#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \\\n                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))\n\n#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)\n#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup I2C_Private_Functions I2C Private Functions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __STM32F4xx_HAL_I2C_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_i2c_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_i2c_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of I2C HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_I2C_EX_H\n#define __STM32F4xx_HAL_I2C_EX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup I2CEx\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup I2CEx_Exported_Constants I2C Exported Constants\n  * @{\n  */\n\n/** @defgroup I2CEx_Analog_Filter I2C Analog Filter\n  * @{\n  */\n#define I2C_ANALOGFILTER_ENABLE        0x00000000U\n#define I2C_ANALOGFILTER_DISABLE       I2C_FLTR_ANOFF\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup I2CEx_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup I2CEx_Exported_Functions_Group1\n  * @{\n  */\n/* Peripheral Control functions  ************************************************/\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup I2CEx_Private_Constants I2C Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup I2CEx_Private_Macros I2C Private Macros\n  * @{\n  */\n#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \\\n                                      ((FILTER) == I2C_ANALOGFILTER_DISABLE))\n#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_I2C_EX_H */\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pcd.h\n  * @author  MCD Application Team\n  * @brief   Header file of PCD HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_PCD_H\n#define STM32F4xx_HAL_PCD_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_usb.h\"\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup PCD\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup PCD_Exported_Types PCD Exported Types\n  * @{\n  */\n\n/**\n  * @brief  PCD State structure definition\n  */\ntypedef enum\n{\n  HAL_PCD_STATE_RESET   = 0x00,\n  HAL_PCD_STATE_READY   = 0x01,\n  HAL_PCD_STATE_ERROR   = 0x02,\n  HAL_PCD_STATE_BUSY    = 0x03,\n  HAL_PCD_STATE_TIMEOUT = 0x04\n} PCD_StateTypeDef;\n\n/* Device LPM suspend state */\ntypedef enum\n{\n  LPM_L0 = 0x00, /* on */\n  LPM_L1 = 0x01, /* LPM L1 sleep */\n  LPM_L2 = 0x02, /* suspend */\n  LPM_L3 = 0x03, /* off */\n} PCD_LPM_StateTypeDef;\n\ntypedef enum\n{\n  PCD_LPM_L0_ACTIVE = 0x00, /* on */\n  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */\n} PCD_LPM_MsgTypeDef;\n\ntypedef enum\n{\n  PCD_BCD_ERROR                     = 0xFF,\n  PCD_BCD_CONTACT_DETECTION         = 0xFE,\n  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,\n  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,\n  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,\n  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,\n\n} PCD_BCD_MsgTypeDef;\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\ntypedef USB_OTG_GlobalTypeDef  PCD_TypeDef;\ntypedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;\ntypedef USB_OTG_EPTypeDef      PCD_EPTypeDef;\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n/**\n  * @brief  PCD Handle Structure definition\n  */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\ntypedef struct __PCD_HandleTypeDef\n#else\ntypedef struct\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n{\n  PCD_TypeDef             *Instance;   /*!< Register base address             */\n  PCD_InitTypeDef         Init;        /*!< PCD required parameters           */\n  __IO uint8_t            USB_Address; /*!< USB Address                       */\n  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters            */\n  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters           */\n  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status             */\n  __IO PCD_StateTypeDef   State;       /*!< PCD communication state           */\n  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                    */\n  uint32_t                Setup[12];   /*!< Setup packet buffer               */\n  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                         */\n  uint32_t                BESL;\n\n\n  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .\n                                       This parameter can be set to ENABLE or DISABLE        */\n\n  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.\n                                       This parameter can be set to ENABLE or DISABLE        */\n  void                    *pData;      /*!< Pointer to upper stack Handler */\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */\n  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */\n  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */\n  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */\n  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */\n  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */\n  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */\n\n  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */\n  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */\n  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */\n  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */\n  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */\n  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */\n\n  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */\n  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n} PCD_HandleTypeDef;\n\n/**\n  * @}\n  */\n\n/* Include PCD HAL Extended module */\n#include \"stm32f4xx_hal_pcd_ex.h\"\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\n  * @{\n  */\n\n/** @defgroup PCD_Speed PCD Speed\n  * @{\n  */\n#define PCD_SPEED_HIGH               USBD_HS_SPEED\n#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED\n#define PCD_SPEED_FULL               USBD_FS_SPEED\n/**\n  * @}\n  */\n\n/** @defgroup PCD_PHY_Module PCD PHY Module\n  * @{\n  */\n#define PCD_PHY_ULPI                 1U\n#define PCD_PHY_EMBEDDED             2U\n#define PCD_PHY_UTMI                 3U\n/**\n  * @}\n  */\n\n/** @defgroup PCD_Error_Code_definition PCD Error Code definition\n  * @brief  PCD Error Code definition\n  * @{\n  */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macros -----------------------------------------------------------*/\n/** @defgroup PCD_Exported_Macros PCD Exported Macros\n  *  @brief macros to handle interrupts and specific clock configurations\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)\n#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)\n\n#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))\n#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))\n#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)\n\n\n#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)       *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK)\n\n#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)         *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK\n\n#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)      ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)\n\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)\n\n#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \\\n  do { \\\n    EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \\\n    EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \\\n  } while(0U)\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE\n\n#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \\\n  do { \\\n    EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \\\n    EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \\\n  } while(0U)\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PCD_Exported_Functions PCD Exported Functions\n  * @{\n  */\n\n/* Initialization/de-initialization functions  ********************************/\n/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\n  * @{\n  */\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition\n  * @brief  HAL USB OTG PCD Callback ID enumeration definition\n  * @{\n  */\ntypedef enum\n{\n  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */\n  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */\n  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */\n  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */\n  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */\n  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */\n  HAL_PCD_DISCONNECT_CB_ID   = 0x07,      /*!< USB PCD Disconnect callback ID   */\n\n  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */\n  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */\n\n} HAL_PCD_CallbackIDTypeDef;\n/**\n  * @}\n  */\n\n/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition\n  * @brief  HAL USB OTG PCD Callback pointer definition\n  * @{\n  */\n\ntypedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */\ntypedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */\ntypedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */\ntypedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */\ntypedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */\ntypedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */\ntypedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */\n\n/**\n  * @}\n  */\n\nHAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,\n                                           HAL_PCD_CallbackIDTypeDef CallbackID,\n                                           pPCD_CallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,\n                                             HAL_PCD_CallbackIDTypeDef CallbackID);\n\nHAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,\n                                                       pPCD_DataOutStageCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);\n\nHAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,\n                                                      pPCD_DataInStageCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);\n\nHAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,\n                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);\n\nHAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,\n                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);\n\nHAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,\n                                              pPCD_BcdCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);\n\nHAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,\n                                              pPCD_LpmCallbackTypeDef pCallback);\n\nHAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/* I/O operation functions  ***************************************************/\n/* Non-Blocking mode: Interrupt */\n/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions\n  * @{\n  */\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);\n\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);\n\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);\n/**\n  * @}\n  */\n\n/* Peripheral Control functions  **********************************************/\n/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions\n  * @{\n  */\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,\n                                  uint16_t ep_mps, uint8_t ep_type);\n\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,\n                                     uint8_t *pBuf, uint32_t len);\n\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,\n                                      uint8_t *pBuf, uint32_t len);\n\n\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);\n\nuint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);\n/**\n  * @}\n  */\n\n/* Peripheral State functions  ************************************************/\n/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions\n  * @{\n  */\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup PCD_Private_Constants PCD Private Constants\n  * @{\n  */\n/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 18)  /*!< USB FS EXTI Line WakeUp Interrupt */\n#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 20)  /*!< USB HS EXTI Line WakeUp Interrupt */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/**\n  * @}\n  */\n/**\n  * @}\n  */\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n#ifndef USB_OTG_DOEPINT_OTEPSPR\n#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */\n#endif\n\n#ifndef USB_OTG_DOEPMSK_OTEPSPRM\n#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */\n#endif\n\n#ifndef USB_OTG_DOEPINT_NAK\n#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */\n#endif\n\n#ifndef USB_OTG_DOEPMSK_NAKM\n#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */\n#endif\n\n#ifndef USB_OTG_DOEPINT_STPKTRX\n#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */\n#endif\n\n#ifndef USB_OTG_DOEPMSK_NYETM\n#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */\n#endif\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup PCD_Private_Macros PCD Private Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32F4xx_HAL_PCD_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pcd_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pcd_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of PCD HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_PCD_EX_H\n#define STM32F4xx_HAL_PCD_EX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup PCDEx\n  * @{\n  */\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n/* Exported macros -----------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions\n  * @{\n  */\n/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\n  * @{\n  */\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\nHAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);\nHAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);\nvoid HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);\n#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\nvoid HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);\nvoid HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* STM32F4xx_HAL_PCD_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pwr.h\n  * @author  MCD Application Team\n  * @brief   Header file of PWR HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_PWR_H\n#define __STM32F4xx_HAL_PWR_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup PWR\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n\n/** @defgroup PWR_Exported_Types PWR Exported Types\n  * @{\n  */\n   \n/**\n  * @brief  PWR PVD configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.\n                            This parameter can be a value of @ref PWR_PVD_detection_level */\n\n  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.\n                           This parameter can be a value of @ref PWR_PVD_Mode */\n}PWR_PVDTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PWR_Exported_Constants PWR Exported Constants\n  * @{\n  */\n  \n/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins\n  * @{\n  */\n#define PWR_WAKEUP_PIN1                 0x00000100U\n/**\n  * @}\n  */\n\n/** @defgroup PWR_PVD_detection_level PWR PVD detection level\n  * @{\n  */ \n#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0\n#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1\n#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2\n#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3\n#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4\n#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5\n#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6\n#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage \n                                                          (Compare internally to VREFINT) */\n/**\n  * @}\n  */   \n \n/** @defgroup PWR_PVD_Mode PWR PVD Mode\n  * @{\n  */\n#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */\n#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */\n#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */\n#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */\n#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */\n#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */\n#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */\n/**\n  * @}\n  */\n\n\n/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode\n  * @{\n  */\n#define PWR_MAINREGULATOR_ON                        0x00000000U\n#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS\n/**\n  * @}\n  */\n    \n/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry\n  * @{\n  */\n#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)\n#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry\n  * @{\n  */\n#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)\n#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_Flag PWR Flag\n  * @{\n  */\n#define PWR_FLAG_WU                     PWR_CSR_WUF\n#define PWR_FLAG_SB                     PWR_CSR_SBF\n#define PWR_FLAG_PVDO                   PWR_CSR_PVDO\n#define PWR_FLAG_BRR                    PWR_CSR_BRR\n#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n  \n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup PWR_Exported_Macro PWR Exported Macro\n  * @{\n  */\n\n/** @brief  Check PWR flag is set or not.\n  * @param  __FLAG__ specifies the flag to check.\n  *           This parameter can be one of the following values:\n  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event \n  *                  was received from the WKUP pin or from the RTC alarm (Alarm A \n  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.\n  *                  An additional wakeup event is detected if the WKUP pin is enabled \n  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  \n  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was\n  *                  resumed from StandBy mode.    \n  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled \n  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode \n  *                  For this reason, this bit is equal to 0 after Standby or reset\n  *                  until the PVDE bit is set.\n  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset \n  *                  when the device wakes up from Standby mode or by a system reset \n  *                  or power reset.  \n  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage \n  *                 scaling output selection is ready.\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))\n\n/** @brief  Clear the PWR's pending flags.\n  * @param  __FLAG__ specifies the flag to clear.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_FLAG_WU: Wake Up flag\n  *            @arg PWR_FLAG_SB: StandBy flag\n  */\n#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)\n\n/**\n  * @brief Enable the PVD Exti Line 16.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief Disable the PVD EXTI Line 16.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief Enable event on PVD Exti Line 16.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief Disable event on PVD Exti Line 16.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief Enable the PVD Extended Interrupt Rising Trigger.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\n\n/**\n  * @brief Disable the PVD Extended Interrupt Rising Trigger.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)\n\n/**\n  * @brief Enable the PVD Extended Interrupt Falling Trigger.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\n\n\n/**\n  * @brief Disable the PVD Extended Interrupt Falling Trigger.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)\n\n\n/**\n  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\\\n                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\\\n                                                            }while(0U)\n\n/**\n  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.\n  * This parameter can be:\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\\\n                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\\\n                                                            }while(0U) \n\n/**\n  * @brief checks whether the specified PVD Exti interrupt flag is set or not.\n  * @retval EXTI PVD Line Status.\n  */\n#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief Clear the PVD Exti flag.\n  * @retval None.\n  */\n#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))\n\n/**\n  * @brief  Generates a Software interrupt on PVD EXTI line.\n  * @retval None\n  */\n#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))\n\n/**\n  * @}\n  */\n\n/* Include PWR HAL Extension module */\n#include \"stm32f4xx_hal_pwr_ex.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PWR_Exported_Functions PWR Exported Functions\n  * @{\n  */\n  \n/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \n  * @{\n  */\n/* Initialization and de-initialization functions *****************************/\nvoid HAL_PWR_DeInit(void);\nvoid HAL_PWR_EnableBkUpAccess(void);\nvoid HAL_PWR_DisableBkUpAccess(void);\n/**\n  * @}\n  */\n\n/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions \n  * @{\n  */\n/* Peripheral Control functions  **********************************************/\n/* PVD configuration */\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);\nvoid HAL_PWR_EnablePVD(void);\nvoid HAL_PWR_DisablePVD(void);\n\n/* WakeUp pins configuration */\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);\n\n/* Low Power modes entry */\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);\nvoid HAL_PWR_EnterSTANDBYMode(void);\n\n/* Power PVD IRQ Handler */\nvoid HAL_PWR_PVD_IRQHandler(void);\nvoid HAL_PWR_PVDCallback(void);\n\n/* Cortex System Control functions  *******************************************/\nvoid HAL_PWR_EnableSleepOnExit(void);\nvoid HAL_PWR_DisableSleepOnExit(void);\nvoid HAL_PWR_EnableSEVOnPend(void);\nvoid HAL_PWR_DisableSEVOnPend(void);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup PWR_Private_Constants PWR Private Constants\n  * @{\n  */\n\n/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line\n  * @{\n  */\n#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */\n/**\n  * @}\n  */\n\n/** @defgroup PWR_register_alias_address PWR Register alias address\n  * @{\n  */\n/* ------------- PWR registers bit address in the alias region ---------------*/\n#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)\n#define PWR_CR_OFFSET            0x00U\n#define PWR_CSR_OFFSET           0x04U\n#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)\n#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)\n/**\n  * @}\n  */\n\n/** @defgroup PWR_CR_register_alias PWR CR Register alias address\n  * @{\n  */\n/* --- CR Register ---*/\n/* Alias word address of DBP bit */\n#define DBP_BIT_NUMBER   PWR_CR_DBP_Pos\n#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))\n\n/* Alias word address of PVDE bit */\n#define PVDE_BIT_NUMBER  PWR_CR_PVDE_Pos\n#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))\n\n/* Alias word address of VOS bit */\n#define VOS_BIT_NUMBER  PWR_CR_VOS_Pos\n#define CR_VOS_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))\n/**\n  * @}\n  */\n\n/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address\n  * @{\n  */\n/* --- CSR Register ---*/\n/* Alias word address of EWUP bit */\n#define EWUP_BIT_NUMBER  PWR_CSR_EWUP_Pos\n#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup PWR_Private_Macros PWR Private Macros\n  * @{\n  */\n\n/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters\n  * @{\n  */\n#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \\\n                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \\\n                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \\\n                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))\n#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \\\n                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \\\n                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \\\n                              ((MODE) == PWR_PVD_MODE_NORMAL))\n#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \\\n                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))\n#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))\n#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n  \n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __STM32F4xx_HAL_PWR_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pwr_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of PWR HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_PWR_EX_H\n#define __STM32F4xx_HAL_PWR_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup PWREx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/ \n/* Exported constants --------------------------------------------------------*/\n/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n   \n/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode\n  * @{\n  */\n#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS\n#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))\n/**\n  * @}\n  */ \n  \n/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag\n  * @{\n  */\n#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY\n#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY\n#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY\n/**\n  * @}\n  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale\n  * @{\n  */\n#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)   \n#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */\n#define PWR_REGULATOR_VOLTAGE_SCALE2         0x00000000U            /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */\n#else\n#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to\n                                                                       180 MHz by activating the over-drive mode. */\n#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to\n                                                                       168 MHz by activating the over-drive mode. */\n#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */\n#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ \n/**\n  * @}\n  */\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins\n  * @{\n  */\n#define PWR_WAKEUP_PIN2                 0x00000080U\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define PWR_WAKEUP_PIN3                 0x00000040U\n#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \\\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n/**\n  * @}\n  */   \n#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n\n/**\n  * @}\n  */ \n  \n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup PWREx_Exported_Constants PWREx Exported Constants\n  *  @{\n  */\n\n#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)\n/** @brief  macros configure the main internal regulator output voltage.\n  * @param  __REGULATOR__ specifies the regulator output voltage to achieve\n  *         a tradeoff between performance and power consumption when the device does\n  *         not operate at the maximum frequency (refer to the datasheets for more details).\n  *          This parameter can be one of the following values:\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\n  * @retval None\n  */\n#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\\n                                                            __IO uint32_t tmpreg = 0x00U;                        \\\n                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \\\n                                                            /* Delay after an RCC peripheral clock enabling */  \\\n                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \\\n                                                            UNUSED(tmpreg);                                     \\\n                                                          } while(0U)\n#else\n/** @brief  macros configure the main internal regulator output voltage.\n  * @param  __REGULATOR__ specifies the regulator output voltage to achieve\n  *         a tradeoff between performance and power consumption when the device does\n  *         not operate at the maximum frequency (refer to the datasheets for more details).\n  *          This parameter can be one of the following values:\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\n  * @retval None\n  */\n#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \\\n                                                            __IO uint32_t tmpreg = 0x00U;                        \\\n                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \\\n                                                            /* Delay after an RCC peripheral clock enabling */  \\\n                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \\\n                                                            UNUSED(tmpreg);                                     \\\n                                                          } while(0U)\n#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ \n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief Macros to enable or disable the Over drive mode.\n  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.\n  */\n#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)\n#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)\n\n/** @brief Macros to enable or disable the Over drive switching.\n  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. \n  */\n#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)\n#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)\n\n/** @brief Macros to enable or disable the Under drive mode.\n  * @note  This mode is enabled only with STOP low power mode.\n  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This \n  *        mode is only available when the main regulator or the low power regulator \n  *        is in low voltage mode.      \n  * @note  If the Under-drive mode was enabled, it is automatically disabled after \n  *        exiting Stop mode. \n  *        When the voltage regulator operates in Under-drive mode, an additional  \n  *        startup delay is induced when waking up from Stop mode.\n  */\n#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)\n#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))\n\n/** @brief  Check PWR flag is set or not.\n  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode\n  *                                 is ready \n  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode\n  *                                   switching is ready  \n  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode\n  *                                 is enabled in Stop mode\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))\n\n/** @brief Clear the Under-Drive Ready flag.\n  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.\n  */\n#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions\n  *  @{\n  */\n \n/** @addtogroup PWREx_Exported_Functions_Group1\n  * @{\n  */\nvoid HAL_PWREx_EnableFlashPowerDown(void);\nvoid HAL_PWREx_DisableFlashPowerDown(void); \nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); \nuint32_t HAL_PWREx_GetVoltageRange(void);\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\\\n    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void);\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void);\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void);\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void);\n#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\\\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup PWREx_Private_Constants PWREx Private Constants\n  * @{\n  */\n\n/** @defgroup PWREx_register_alias_address PWREx Register alias address\n  * @{\n  */\n/* ------------- PWR registers bit address in the alias region ---------------*/\n/* --- CR Register ---*/\n/* Alias word address of FPDS bit */\n#define FPDS_BIT_NUMBER          PWR_CR_FPDS_Pos\n#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))\n\n/* Alias word address of ODEN bit   */\n#define ODEN_BIT_NUMBER          PWR_CR_ODEN_Pos\n#define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))\n\n/* Alias word address of ODSWEN bit */\n#define ODSWEN_BIT_NUMBER        PWR_CR_ODSWEN_Pos\n#define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))\n    \n/* Alias word address of MRLVDS bit */\n#define MRLVDS_BIT_NUMBER        PWR_CR_MRLVDS_Pos\n#define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))\n\n/* Alias word address of LPLVDS bit */\n#define LPLVDS_BIT_NUMBER        PWR_CR_LPLVDS_Pos\n#define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))\n\n /**\n  * @}\n  */\n\n/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address\n  * @{\n  */  \n/* --- CSR Register ---*/\n/* Alias word address of BRE bit */\n#define BRE_BIT_NUMBER   PWR_CSR_BRE_Pos\n#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup PWREx_Private_Macros PWREx Private Macros\n  * @{\n  */\n\n/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \\\n                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)\n#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\\n                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))\n#else\n#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \\\n                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \\\n                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))\n#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ \n\n#if defined(STM32F446xx)\n#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))\n#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\\\n      defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n      defined(STM32F423xx)\n#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \\\n                                ((PIN) == PWR_WAKEUP_PIN3))\n#else\n#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)\n#endif /* STM32F446xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n  \n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* __STM32F4xx_HAL_PWR_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_rcc.h\n  * @author  MCD Application Team\n  * @brief   Header file of RCC HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_RCC_H\n#define __STM32F4xx_HAL_RCC_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/* Include RCC HAL Extended module */\n/* (include on top of file since RCC structures are defined in extended file) */\n#include \"stm32f4xx_hal_rcc_ex.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup RCC\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup RCC_Exported_Types RCC Exported Types\n  * @{\n  */\n\n/**\n  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t OscillatorType;       /*!< The oscillators to be configured.\n                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */\n\n  uint32_t HSEState;             /*!< The new state of the HSE.\n                                      This parameter can be a value of @ref RCC_HSE_Config                        */\n\n  uint32_t LSEState;             /*!< The new state of the LSE.\n                                      This parameter can be a value of @ref RCC_LSE_Config                        */\n\n  uint32_t HSIState;             /*!< The new state of the HSI.\n                                      This parameter can be a value of @ref RCC_HSI_Config                        */\n\n  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).\n                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */\n\n  uint32_t LSIState;             /*!< The new state of the LSI.\n                                      This parameter can be a value of @ref RCC_LSI_Config                        */\n\n  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */\n}RCC_OscInitTypeDef;\n\n/**\n  * @brief  RCC System, AHB and APB busses clock configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockType;             /*!< The clock to be configured.\n                                       This parameter can be a value of @ref RCC_System_Clock_Type      */\n\n  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.\n                                       This parameter can be a value of @ref RCC_System_Clock_Source    */\n\n  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).\n                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */\n\n  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\n\n  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).\n                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */\n\n}RCC_ClkInitTypeDef;\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup RCC_Exported_Constants RCC Exported Constants\n  * @{\n  */\n\n/** @defgroup RCC_Oscillator_Type Oscillator Type\n  * @{\n  */\n#define RCC_OSCILLATORTYPE_NONE            0x00000000U\n#define RCC_OSCILLATORTYPE_HSE             0x00000001U\n#define RCC_OSCILLATORTYPE_HSI             0x00000002U\n#define RCC_OSCILLATORTYPE_LSE             0x00000004U\n#define RCC_OSCILLATORTYPE_LSI             0x00000008U\n/**\n  * @}\n  */\n\n/** @defgroup RCC_HSE_Config HSE Config\n  * @{\n  */\n#define RCC_HSE_OFF                      0x00000000U\n#define RCC_HSE_ON                       RCC_CR_HSEON\n#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LSE_Config LSE Config\n  * @{\n  */\n#define RCC_LSE_OFF                    0x00000000U\n#define RCC_LSE_ON                     RCC_BDCR_LSEON\n#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_HSI_Config HSI Config\n  * @{\n  */\n#define RCC_HSI_OFF                      ((uint8_t)0x00)\n#define RCC_HSI_ON                       ((uint8_t)0x01)\n\n#define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LSI_Config LSI Config\n  * @{\n  */\n#define RCC_LSI_OFF                      ((uint8_t)0x00)\n#define RCC_LSI_ON                       ((uint8_t)0x01)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_PLL_Config PLL Config\n  * @{\n  */\n#define RCC_PLL_NONE                      ((uint8_t)0x00)\n#define RCC_PLL_OFF                       ((uint8_t)0x01)\n#define RCC_PLL_ON                        ((uint8_t)0x02)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider\n  * @{\n  */\n#define RCC_PLLP_DIV2                  0x00000002U\n#define RCC_PLLP_DIV4                  0x00000004U\n#define RCC_PLLP_DIV6                  0x00000006U\n#define RCC_PLLP_DIV8                  0x00000008U\n/**\n  * @}\n  */\n\n/** @defgroup RCC_PLL_Clock_Source PLL Clock Source\n  * @{\n  */\n#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI\n#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE\n/**\n  * @}\n  */\n\n/** @defgroup RCC_System_Clock_Type System Clock Type\n  * @{\n  */\n#define RCC_CLOCKTYPE_SYSCLK             0x00000001U\n#define RCC_CLOCKTYPE_HCLK               0x00000002U\n#define RCC_CLOCKTYPE_PCLK1              0x00000004U\n#define RCC_CLOCKTYPE_PCLK2              0x00000008U\n/**\n  * @}\n  */\n\n/** @defgroup RCC_System_Clock_Source System Clock Source\n  * @note     The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for\n  *           STM32F446xx devices.\n  * @{\n  */\n#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI\n#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE\n#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL\n#define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status\n  * @note     The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for\n  *           STM32F446xx devices.\n  * @{\n  */\n#define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */\n#define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */\n#define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */\n#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */\n/**\n  * @}\n  */\n\n/** @defgroup RCC_AHB_Clock_Source AHB Clock Source\n  * @{\n  */\n#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1\n#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2\n#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4\n#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8\n#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16\n#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64\n#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128\n#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256\n#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source\n  * @{\n  */\n#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1\n#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2\n#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4\n#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8\n#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16\n/**\n  * @}\n  */\n\n/** @defgroup RCC_RTC_Clock_Source RTC Clock Source\n  * @{\n  */\n#define RCC_RTCCLKSOURCE_NO_CLK          0x00000000U\n#define RCC_RTCCLKSOURCE_LSE             0x00000100U\n#define RCC_RTCCLKSOURCE_LSI             0x00000200U\n#define RCC_RTCCLKSOURCE_HSE_DIVX        0x00000300U\n#define RCC_RTCCLKSOURCE_HSE_DIV2        0x00020300U\n#define RCC_RTCCLKSOURCE_HSE_DIV3        0x00030300U\n#define RCC_RTCCLKSOURCE_HSE_DIV4        0x00040300U\n#define RCC_RTCCLKSOURCE_HSE_DIV5        0x00050300U\n#define RCC_RTCCLKSOURCE_HSE_DIV6        0x00060300U\n#define RCC_RTCCLKSOURCE_HSE_DIV7        0x00070300U\n#define RCC_RTCCLKSOURCE_HSE_DIV8        0x00080300U\n#define RCC_RTCCLKSOURCE_HSE_DIV9        0x00090300U\n#define RCC_RTCCLKSOURCE_HSE_DIV10       0x000A0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV11       0x000B0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV12       0x000C0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV13       0x000D0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV14       0x000E0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV15       0x000F0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV16       0x00100300U\n#define RCC_RTCCLKSOURCE_HSE_DIV17       0x00110300U\n#define RCC_RTCCLKSOURCE_HSE_DIV18       0x00120300U\n#define RCC_RTCCLKSOURCE_HSE_DIV19       0x00130300U\n#define RCC_RTCCLKSOURCE_HSE_DIV20       0x00140300U\n#define RCC_RTCCLKSOURCE_HSE_DIV21       0x00150300U\n#define RCC_RTCCLKSOURCE_HSE_DIV22       0x00160300U\n#define RCC_RTCCLKSOURCE_HSE_DIV23       0x00170300U\n#define RCC_RTCCLKSOURCE_HSE_DIV24       0x00180300U\n#define RCC_RTCCLKSOURCE_HSE_DIV25       0x00190300U\n#define RCC_RTCCLKSOURCE_HSE_DIV26       0x001A0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV27       0x001B0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV28       0x001C0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV29       0x001D0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV30       0x001E0300U\n#define RCC_RTCCLKSOURCE_HSE_DIV31       0x001F0300U\n/**\n  * @}\n  */\n\n/** @defgroup RCC_MCO_Index MCO Index\n  * @{\n  */\n#define RCC_MCO1                         0x00000000U\n#define RCC_MCO2                         0x00000001U\n/**\n  * @}\n  */\n\n/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source\n  * @{\n  */\n#define RCC_MCO1SOURCE_HSI               0x00000000U\n#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0\n#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1\n#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1\n/**\n  * @}\n  */\n\n/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler\n  * @{\n  */\n#define RCC_MCODIV_1                    0x00000000U\n#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2\n#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)\n#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)\n#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Interrupt Interrupts\n  * @{\n  */\n#define RCC_IT_LSIRDY                    ((uint8_t)0x01)\n#define RCC_IT_LSERDY                    ((uint8_t)0x02)\n#define RCC_IT_HSIRDY                    ((uint8_t)0x04)\n#define RCC_IT_HSERDY                    ((uint8_t)0x08)\n#define RCC_IT_PLLRDY                    ((uint8_t)0x10)\n#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)\n#define RCC_IT_CSS                       ((uint8_t)0x80)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Flag Flags\n  *        Elements values convention: 0XXYYYYYb\n  *           - YYYYY  : Flag position in the register\n  *           - 0XX  : Register index\n  *                 - 01: CR register\n  *                 - 10: BDCR register\n  *                 - 11: CSR register\n  * @{\n  */\n/* Flags in the CR register */\n#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)\n#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)\n#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)\n#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)\n\n/* Flags in the BDCR register */\n#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)\n\n/* Flags in the CSR register */\n#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)\n#define RCC_FLAG_BORRST                  ((uint8_t)0x79)\n#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)\n#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)\n#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)\n#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)\n#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)\n#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup RCC_Exported_Macros RCC Exported Macros\n  * @{\n  */\n\n/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\\\n                                        UNUSED(tmpreg); \\\n                                         } while(0U)\n#define __HAL_RCC_DMA1_CLK_ENABLE()  do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\\\n                                        UNUSED(tmpreg); \\\n                                         } while(0U)\n#define __HAL_RCC_DMA2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n\n#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))\n#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))\n#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))\n#define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))\n#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))\n#define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)\n#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)\n#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)\n#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)\n#define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)\n#define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)\n\n#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)\n#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)\n#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)\n#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)\n#define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)\n#define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM5_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_WWDG_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_SPI2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_USART2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_I2C1_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_I2C2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_PWR_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n\n#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))\n#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))\n#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))\n#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))\n#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))\n#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))\n#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)\n#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)\n#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)\n#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)\n#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)\n#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)\n#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)\n\n#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)\n#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)\n#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)\n#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)\n#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)\n#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)\n#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM1_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_USART1_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_USART6_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_ADC1_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_SPI1_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_TIM9_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n#define __HAL_RCC_TIM11_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\\\n                                        UNUSED(tmpreg); \\\n                                          } while(0U)\n\n#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))\n#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))\n#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))\n#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))\n#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))\n#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))\n#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))\n#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)\n#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)\n#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)\n#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)\n#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)\n#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)\n#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)\n#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)\n\n#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)\n#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)\n#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)\n#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)\n#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)\n#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)\n#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)\n#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset\n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))\n#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))\n#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))\n#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))\n#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))\n#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))\n\n#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)\n#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))\n#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))\n#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))\n#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))\n#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))\n#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset\n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))\n#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))\n#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))\n#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))\n#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))\n#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))\n#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))\n\n#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)\n#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))\n#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))\n#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))\n#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))\n#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))\n#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))\n#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset\n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))\n#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))\n#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))\n#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))\n#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))\n#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))\n#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))\n#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))\n\n#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)\n#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))\n#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))\n#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))\n#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))\n#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))\n#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))\n#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))\n#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))\n#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))\n#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))\n#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))\n#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))\n#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))\n\n#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))\n#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))\n#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))\n#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))\n#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))\n#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))\n#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))\n#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))\n#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))\n#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))\n#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))\n#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))\n\n#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))\n#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))\n#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))\n#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))\n#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))\n#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))\n#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))\n#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))\n#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))\n#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))\n#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))\n#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))\n#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))\n\n#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))\n#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))\n#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))\n#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))\n#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))\n#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))\n#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))\n#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_HSI_Configuration HSI Configuration\n  * @{\n  */\n\n/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).\n  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.\n  *         It is used (enabled by hardware) as system clock source after startup\n  *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure\n  *         of the HSE used directly or indirectly as system clock (if the Clock\n  *         Security System CSS is enabled).\n  * @note   HSI can not be stopped if it is used as system clock source. In this case,\n  *         you have to select another source of the system clock then stop the HSI.\n  * @note   After enabling the HSI, the application software should wait on HSIRDY\n  *         flag to be set indicating that HSI clock is stable and can be used as\n  *         system clock source.\n  *         This parameter can be: ENABLE or DISABLE.\n  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator\n  *         clock cycles.\n  */\n#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)\n#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)\n\n/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.\n  * @note   The calibration is used to compensate for the variations in voltage\n  *         and temperature that influence the frequency of the internal HSI RC.\n  * @param  __HSICalibrationValue__ specifies the calibration trimming value.\n  *         (default is RCC_HSICALIBRATION_DEFAULT).\n  *         This parameter must be a number between 0 and 0x1F.\n  */\n#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\\\n        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LSI_Configuration LSI Configuration\n  * @{\n  */\n\n/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).\n  * @note   After enabling the LSI, the application software should wait on\n  *         LSIRDY flag to be set indicating that LSI clock is stable and can\n  *         be used to clock the IWDG and/or the RTC.\n  * @note   LSI can not be disabled if the IWDG is running.\n  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator\n  *         clock cycles.\n  */\n#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)\n#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_HSE_Configuration HSE Configuration\n  * @{\n  */\n\n/**\n  * @brief  Macro to configure the External High Speed oscillator (HSE).\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.\n  *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.\n  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application\n  *         software should wait on HSERDY flag to be set indicating that HSE clock\n  *         is stable and can be used to clock the PLL and/or system clock.\n  * @note   HSE state can not be changed if it is used directly or through the\n  *         PLL as system clock. In this case, you have to select another source\n  *         of the system clock then change the HSE state (ex. disable it).\n  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.\n  * @note   This function reset the CSSON bit, so if the clock security system(CSS)\n  *         was previously enabled you have to enable it again after calling this\n  *         function.\n  * @param  __STATE__ specifies the new state of the HSE.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after\n  *                              6 HSE oscillator clock cycles.\n  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.\n  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.\n  */\n#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \\\n                    do {                                        \\\n                      if ((__STATE__) == RCC_HSE_ON)            \\\n                      {                                         \\\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\n                      }                                         \\\n                      else if ((__STATE__) == RCC_HSE_BYPASS)   \\\n                      {                                         \\\n                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \\\n                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \\\n                      }                                         \\\n                      else                                      \\\n                      {                                         \\\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \\\n                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \\\n                      }                                         \\\n                    } while(0U)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_LSE_Configuration LSE Configuration\n  * @{\n  */\n\n/**\n  * @brief  Macro to configure the External Low Speed oscillator (LSE).\n  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.\n  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.\n  * @note   As the LSE is in the Backup domain and write access is denied to\n  *         this domain after reset, you have to enable write access using\n  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE\n  *         (to be done once after reset).\n  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application\n  *         software should wait on LSERDY flag to be set indicating that LSE clock\n  *         is stable and can be used to clock the RTC.\n  * @param  __STATE__ specifies the new state of the LSE.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after\n  *                              6 LSE oscillator clock cycles.\n  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.\n  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.\n  */\n#define __HAL_RCC_LSE_CONFIG(__STATE__) \\\n                    do {                                       \\\n                      if((__STATE__) == RCC_LSE_ON)            \\\n                      {                                        \\\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\n                      }                                        \\\n                      else if((__STATE__) == RCC_LSE_BYPASS)   \\\n                      {                                        \\\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \\\n                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \\\n                      }                                        \\\n                      else                                     \\\n                      {                                        \\\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \\\n                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \\\n                      }                                        \\\n                    } while(0U)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration\n  * @{\n  */\n\n/** @brief  Macros to enable or disable the RTC clock.\n  * @note   These macros must be used only after the RTC clock source was selected.\n  */\n#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)\n#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)\n\n/** @brief  Macros to configure the RTC clock (RTCCLK).\n  * @note   As the RTC clock configuration bits are in the Backup domain and write\n  *         access is denied to this domain after reset, you have to enable write\n  *         access using the Power Backup Access macro before to configure\n  *         the RTC clock source (to be done once after reset).\n  * @note   Once the RTC clock is configured it can't be changed unless the\n  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by\n  *         a Power On Reset (POR).\n  * @param  __RTCCLKSource__ specifies the RTC clock source.\n  *         This parameter can be one of the following values:\n  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.\n  *            @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.\n  *            @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.\n  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\n  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to\n  *         work in STOP and STANDBY modes, and can be used as wake-up source.\n  *         However, when the HSE clock is used as RTC clock source, the RTC\n  *         cannot be used in STOP and STANDBY modes.\n  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as\n  *         RTC clock source).\n  */\n#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \\\n                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)\n\n#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \\\n                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \\\n                                                   } while(0U)\n\n/** @brief Macro to get the RTC clock source.\n  * @retval The clock source can be one of the following values:\n  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock\n  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock\n  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock\n  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\n  */\n#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))\n\n/**\n  * @brief   Get the RTC and HSE clock divider (RTCPRE).\n  * @retval Returned value can be one of the following values:\n *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()\n  */\n#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)\n\n/** @brief  Macros to force or release the Backup domain reset.\n  * @note   This function resets the RTC peripheral (including the backup registers)\n  *         and the RTC clock source selection in RCC_CSR register.\n  * @note   The BKPSRAM is not affected by this reset.\n  */\n#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)\n#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)\n/**\n  * @}\n  */\n\n/** @defgroup RCC_PLL_Configuration PLL Configuration\n  * @{\n  */\n\n/** @brief  Macros to enable or disable the main PLL.\n  * @note   After enabling the main PLL, the application software should wait on\n  *         PLLRDY flag to be set indicating that PLL clock is stable and can\n  *         be used as system clock source.\n  * @note   The main PLL can not be disabled if it is used as system clock source\n  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.\n  */\n#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)\n#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)\n\n/** @brief  Macro to configure the PLL clock source.\n  * @note   This function must be used only when the main PLL is disabled.\n  * @param  __PLLSOURCE__ specifies the PLL entry clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\n  *\n  */\n#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))\n\n/** @brief  Macro to configure the PLL multiplication factor.\n  * @note   This function must be used only when the main PLL is disabled.\n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 2 MHz to limit PLL jitter.\n  *\n  */\n#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Get_Clock_source Get Clock source\n  * @{\n  */\n/**\n  * @brief Macro to configure the system clock source.\n  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.\n  * This parameter can be one of the following values:\n  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.\n  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.\n  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.\n  *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This\n  *                parameter is available only for STM32F446xx devices.\n  */\n#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))\n\n/** @brief  Macro to get the clock source used as system clock.\n  * @retval The clock source used as system clock. The returned value can be one\n  *         of the following:\n  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.\n  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.\n  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.\n  *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter\n  *                is available only for STM32F446xx devices.\n  */\n#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)\n\n/** @brief  Macro to get the oscillator used as PLL clock source.\n  * @retval The oscillator used as PLL clock source. The returned value can be one\n  *         of the following:\n  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.\n  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.\n  */\n#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config\n  * @{\n  */\n\n/** @brief  Macro to configure the MCO1 clock.\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\n  */\n#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\n                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))\n\n/** @brief  Macro to configure the MCO2 clock.\n  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx\n  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\n  * @param  __MCODIV__ specifies the MCO clock prescaler.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\n  * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have\n  *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).\n  */\n#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \\\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management\n  * @brief macros to manage the specified RCC Flags and interrupts.\n  * @{\n  */\n\n/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable\n  *         the selected interrupts).\n  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.\n  *         This parameter can be any combination of the following values:\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\n  */\n#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))\n\n/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable\n  *        the selected interrupts).\n  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.\n  *         This parameter can be any combination of the following values:\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\n  */\n#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))\n\n/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]\n  *         bits to clear the selected interrupt pending bits.\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\n  *         This parameter can be any combination of the following values:\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\n  */\n#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))\n\n/** @brief  Check the RCC's interrupt has occurred or not.\n  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.\n  *            @arg RCC_IT_LSERDY: LSE ready interrupt.\n  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.\n  *            @arg RCC_IT_HSERDY: HSE ready interrupt.\n  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.\n  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.\n  *            @arg RCC_IT_CSS: Clock Security System interrupt\n  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).\n  */\n#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))\n\n/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,\n  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.\n  */\n#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)\n\n/** @brief  Check RCC flag is set or not.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.\n  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.\n  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.\n  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.\n  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.\n  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.\n  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.\n  *            @arg RCC_FLAG_PINRST: Pin reset.\n  *            @arg RCC_FLAG_PORRST: POR/PDR reset.\n  *            @arg RCC_FLAG_SFTRST: Software reset.\n  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.\n  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.\n  *            @arg RCC_FLAG_LPWRRST: Low Power reset.\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define RCC_FLAG_MASK  ((uint8_t)0x1FU)\n#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n /** @addtogroup RCC_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup RCC_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization and de-initialization functions  ******************************/\nHAL_StatusTypeDef HAL_RCC_DeInit(void);\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);\n/**\n  * @}\n  */\n\n/** @addtogroup RCC_Exported_Functions_Group2\n  * @{\n  */\n/* Peripheral Control functions  ************************************************/\nvoid     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);\nvoid     HAL_RCC_EnableCSS(void);\nvoid     HAL_RCC_DisableCSS(void);\nuint32_t HAL_RCC_GetSysClockFreq(void);\nuint32_t HAL_RCC_GetHCLKFreq(void);\nuint32_t HAL_RCC_GetPCLK1Freq(void);\nuint32_t HAL_RCC_GetPCLK2Freq(void);\nvoid     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);\nvoid     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);\n\n/* CSS NMI IRQ handler */\nvoid HAL_RCC_NMI_IRQHandler(void);\n\n/* User Callbacks in non blocking mode (IT mode) */\nvoid HAL_RCC_CSSCallback(void);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup RCC_Private_Constants RCC Private Constants\n  * @{\n  */\n\n/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion\n  * @brief RCC registers bit address in the alias region\n  * @{\n  */\n#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)\n/* --- CR Register --- */\n/* Alias word address of HSION bit */\n#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)\n#define RCC_HSION_BIT_NUMBER       0x00U\n#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))\n/* Alias word address of CSSON bit */\n#define RCC_CSSON_BIT_NUMBER       0x13U\n#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))\n/* Alias word address of PLLON bit */\n#define RCC_PLLON_BIT_NUMBER       0x18U\n#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))\n\n/* --- BDCR Register --- */\n/* Alias word address of RTCEN bit */\n#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)\n#define RCC_RTCEN_BIT_NUMBER       0x0FU\n#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))\n/* Alias word address of BDRST bit */\n#define RCC_BDRST_BIT_NUMBER       0x10U\n#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))\n\n/* --- CSR Register --- */\n/* Alias word address of LSION bit */\n#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)\n#define RCC_LSION_BIT_NUMBER        0x00U\n#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))\n\n/* CR register byte 3 (Bits[23:16]) base address */\n#define RCC_CR_BYTE2_ADDRESS       0x40023802U\n\n/* CIR register byte 2 (Bits[15:8]) base address */\n#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))\n\n/* CIR register byte 3 (Bits[23:16]) base address */\n#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))\n\n/* BDCR register base address */\n#define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)\n\n#define RCC_DBP_TIMEOUT_VALUE      2U\n#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT\n\n#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT\n#define HSI_TIMEOUT_VALUE          2U  /* 2 ms */\n#define LSI_TIMEOUT_VALUE          2U  /* 2 ms */\n#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup RCC_Private_Macros RCC Private Macros\n  * @{\n  */\n\n/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters\n  * @{\n  */\n#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)\n\n#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \\\n                         ((HSE) == RCC_HSE_BYPASS))\n\n#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \\\n                         ((LSE) == RCC_LSE_BYPASS))\n\n#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))\n\n#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))\n\n#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))\n\n#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \\\n                                  ((SOURCE) == RCC_PLLSOURCE_HSE))\n\n#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \\\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \\\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \\\n                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))\n\n#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \\\n                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))\n\n#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)\n\n#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))\n\n#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))\n\n#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \\\n                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \\\n                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \\\n                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \\\n                           ((HCLK) == RCC_SYSCLK_DIV512))\n\n#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))\n\n#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \\\n                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \\\n                           ((PCLK) == RCC_HCLK_DIV16))\n\n#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))\n\n#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \\\n                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))\n\n#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \\\n                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \\\n                             ((DIV) == RCC_MCODIV_5))\n#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_RCC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_rcc_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of RCC HAL Extension module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_RCC_EX_H\n#define __STM32F4xx_HAL_RCC_EX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup RCCEx\n  * @{\n  */ \n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup RCCEx_Exported_Types RCCEx Exported Types\n  * @{\n  */\n\n/**\n  * @brief  RCC PLL configuration structure definition\n  */\ntypedef struct\n{\n  uint32_t PLLState;   /*!< The new state of the PLL.\n                            This parameter can be a value of @ref RCC_PLL_Config                      */\n\n  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.\n                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */\n\n  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.\n                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */\n\n  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432 \n                            except for STM32F411xE devices where the Min_Data = 192 */\n\n  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).\n                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */\n\n  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n  uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.\n                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx\n                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. \n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7     */\n#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ \n}RCC_PLLInitTypeDef;\n\n#if defined(STM32F446xx)\n/** \n  * @brief  PLLI2S Clock structure definition  \n  */\ntypedef struct\n{\n  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */\n\n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */\n\n  uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.\n                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */\n\n  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. \n                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n                           \n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. \n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */\n}RCC_PLLI2SInitTypeDef;\n\n/** \n  * @brief  PLLSAI Clock structure definition  \n  */\ntypedef struct\n{\n  uint32_t PLLSAIM;    /*!< Specifies division factor for PLL VCO input clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */\n\n  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */\n\n  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.\n                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */\n                                                             \n  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI */\n}RCC_PLLSAIInitTypeDef;\n\n/** \n  * @brief  RCC extended clocks structure definition  \n  */\ntypedef struct\n{\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\n\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. \n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. \n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\n\n  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n\n  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */\n\n  uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */\n\n  uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */\n                                      \n  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */\n\n  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */\n\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. \n                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */\n\n  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */\n\n  uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_CEC_Clock_Source */\n\n  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */\n\n  uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */\n\n  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. \n                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\n  \n  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */\n}RCC_PeriphCLKInitTypeDef;\n#endif /* STM32F446xx */   \n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** \n  * @brief  RCC extended clocks structure definition\n  */\ntypedef struct\n{\n  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\n\n  uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */\n                                      \n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. \n                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */\n\n  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\n  \n  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */\n\n  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */\n}RCC_PeriphCLKInitTypeDef;\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** \n  * @brief  PLLI2S Clock structure definition  \n  */\ntypedef struct\n{\n  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */\n\n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */\n\n  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. \n                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n                           \n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. \n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */\n}RCC_PLLI2SInitTypeDef;\n\n/** \n  * @brief  RCC extended clocks structure definition\n  */\ntypedef struct\n{\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\n\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. \n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */\n  \n#if defined(STM32F413xx) || defined(STM32F423xx)\n  uint32_t PLLDivR;              /*!< Specifies the PLL division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLL is selected as Clock Source SAI */\n\n  uint32_t PLLI2SDivR;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n#endif /* STM32F413xx || STM32F423xx */  \n                                      \n  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */\n\n  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */\n\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. \n                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */\n\n  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */\n\n  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */\n\n  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.\n                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\n  \n  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.\n                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */\n\n  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.\n                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */\n  \n#if defined(STM32F413xx) || defined(STM32F423xx)\n  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock Selection.\n                                      This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */\n\n  uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.\n                                      This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */\n  \n  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */\n  \n  uint32_t SaiAClockSelection;     /*!< Specifies SAI1_A Clock Prescalers Selection\n                                        This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */\n\n  uint32_t SaiBClockSelection;     /*!< Specifies SAI1_B Clock Prescalers Selection\n                                        This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */\n#endif /* STM32F413xx || STM32F423xx */\n\n  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */\n\n  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */\n}RCC_PeriphCLKInitTypeDef;\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n\n/** \n  * @brief  PLLI2S Clock structure definition  \n  */\ntypedef struct\n{\n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. \n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. \n                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n}RCC_PLLI2SInitTypeDef;\n\n/** \n  * @brief  PLLSAI Clock structure definition  \n  */\ntypedef struct\n{\n  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ \n#if defined(STM32F469xx) || defined(STM32F479xx)\n  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.\n                            This parameter is only available in STM32F469xx/STM32F479xx devices.\n                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */  \n#endif /* STM32F469xx || STM32F479xx */\n                                 \n  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */\n                              \n  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */\n\n}RCC_PLLSAIInitTypeDef;\n\n/** \n  * @brief  RCC extended clocks structure definition  \n  */\ntypedef struct\n{\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\n\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. \n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. \n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */\n\n  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */\n\n  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.\n                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32\n                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */\n\n  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.\n                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */\n\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. \n                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */\n\n  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. \n                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */\n#if defined(STM32F469xx) || defined(STM32F479xx)\n  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. \n                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */\n\n  uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  \n#endif /* STM32F469xx || STM32F479xx */  \n}RCC_PeriphCLKInitTypeDef;\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n/** \n  * @brief  PLLI2S Clock structure definition  \n  */\ntypedef struct\n{\n#if defined(STM32F411xE)\n  uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 62  */\n#endif /* STM32F411xE */\n                                \n  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.\n                            This parameter must be a number between Min_Data = 50 and Max_Data = 432\n                            Except for STM32F411xE devices where the Min_Data = 192. \n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.\n                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. \n                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n}RCC_PLLI2SInitTypeDef;\n \n/** \n  * @brief  RCC extended clocks structure definition  \n  */\ntypedef struct\n{\n  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.\n                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */\n\n  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.\n                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */\n\n  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.\n                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) \n  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. \n                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n}RCC_PeriphCLKInitTypeDef;\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */\n/**\n  * @}\n  */ \n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants\n  * @{\n  */\n\n/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection\n  * @{\n  */\n/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n#define RCC_PERIPHCLK_I2S_APB1        0x00000001U\n#define RCC_PERIPHCLK_I2S_APB2        0x00000002U\n#define RCC_PERIPHCLK_TIM             0x00000004U\n#define RCC_PERIPHCLK_RTC             0x00000008U\n#define RCC_PERIPHCLK_FMPI2C1         0x00000010U\n#define RCC_PERIPHCLK_CLK48           0x00000020U\n#define RCC_PERIPHCLK_SDIO            0x00000040U\n#define RCC_PERIPHCLK_PLLI2S          0x00000080U\n#define RCC_PERIPHCLK_DFSDM1          0x00000100U\n#define RCC_PERIPHCLK_DFSDM1_AUDIO    0x00000200U\n#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define RCC_PERIPHCLK_DFSDM2          0x00000400U\n#define RCC_PERIPHCLK_DFSDM2_AUDIO    0x00000800U\n#define RCC_PERIPHCLK_LPTIM1          0x00001000U\n#define RCC_PERIPHCLK_SAIA            0x00002000U\n#define RCC_PERIPHCLK_SAIB            0x00004000U\n#endif /* STM32F413xx || STM32F423xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------- Peripheral Clock source for STM32F410xx ----------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define RCC_PERIPHCLK_I2S             0x00000001U\n#define RCC_PERIPHCLK_TIM             0x00000002U\n#define RCC_PERIPHCLK_RTC             0x00000004U\n#define RCC_PERIPHCLK_FMPI2C1         0x00000008U\n#define RCC_PERIPHCLK_LPTIM1          0x00000010U\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------- Peripheral Clock source for STM32F446xx ----------------*/\n#if defined(STM32F446xx)\n#define RCC_PERIPHCLK_I2S_APB1        0x00000001U\n#define RCC_PERIPHCLK_I2S_APB2        0x00000002U\n#define RCC_PERIPHCLK_SAI1            0x00000004U\n#define RCC_PERIPHCLK_SAI2            0x00000008U\n#define RCC_PERIPHCLK_TIM             0x00000010U\n#define RCC_PERIPHCLK_RTC             0x00000020U\n#define RCC_PERIPHCLK_CEC             0x00000040U\n#define RCC_PERIPHCLK_FMPI2C1         0x00000080U\n#define RCC_PERIPHCLK_CLK48           0x00000100U\n#define RCC_PERIPHCLK_SDIO            0x00000200U\n#define RCC_PERIPHCLK_SPDIFRX         0x00000400U\n#define RCC_PERIPHCLK_PLLI2S          0x00000800U\n#endif /* STM32F446xx */\n/*-----------------------------------------------------------------------------*/\n    \n/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define RCC_PERIPHCLK_I2S             0x00000001U\n#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U\n#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U\n#define RCC_PERIPHCLK_LTDC            0x00000008U\n#define RCC_PERIPHCLK_TIM             0x00000010U\n#define RCC_PERIPHCLK_RTC             0x00000020U\n#define RCC_PERIPHCLK_PLLI2S          0x00000040U\n#define RCC_PERIPHCLK_CLK48           0x00000080U\n#define RCC_PERIPHCLK_SDIO            0x00000100U\n#endif /* STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n#define RCC_PERIPHCLK_I2S             0x00000001U\n#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U\n#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U\n#define RCC_PERIPHCLK_LTDC            0x00000008U\n#define RCC_PERIPHCLK_TIM             0x00000010U\n#define RCC_PERIPHCLK_RTC             0x00000020U\n#define RCC_PERIPHCLK_PLLI2S          0x00000040U\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\n/*----------------------------------------------------------------------------*/\n\n/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) \n#define RCC_PERIPHCLK_I2S             0x00000001U\n#define RCC_PERIPHCLK_RTC             0x00000002U\n#define RCC_PERIPHCLK_PLLI2S          0x00000004U\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n#define RCC_PERIPHCLK_TIM             0x00000008U\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      \n/*----------------------------------------------------------------------------*/\n/**\n  * @}\n  */\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \\\n    defined(STM32F479xx) \n/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source\n  * @{\n  */\n#define RCC_I2SCLKSOURCE_PLLI2S         0x00000000U\n#define RCC_I2SCLKSOURCE_EXT            0x00000001U\n/**\n  * @}\n  */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */\n\n/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR\n  * @{\n  */\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) \n#define RCC_PLLSAIDIVR_2                0x00000000U\n#define RCC_PLLSAIDIVR_4                0x00010000U\n#define RCC_PLLSAIDIVR_8                0x00020000U\n#define RCC_PLLSAIDIVR_16               0x00030000U\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider\n  * @{\n  */\n#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx)\n#define RCC_PLLI2SP_DIV2                  0x00000002U\n#define RCC_PLLI2SP_DIV4                  0x00000004U\n#define RCC_PLLI2SP_DIV6                  0x00000006U\n#define RCC_PLLI2SP_DIV8                  0x00000008U\n#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider\n  * @{\n  */\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) \n#define RCC_PLLSAIP_DIV2                  0x00000002U\n#define RCC_PLLSAIP_DIV4                  0x00000004U\n#define RCC_PLLSAIP_DIV6                  0x00000006U\n#define RCC_PLLSAIP_DIV8                  0x00000008U\n#endif /* STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source\n  * @{\n  */\n#define RCC_SAIACLKSOURCE_PLLSAI             0x00000000U\n#define RCC_SAIACLKSOURCE_PLLI2S             0x00100000U\n#define RCC_SAIACLKSOURCE_EXT                0x00200000U\n/**\n  * @}\n  */ \n\n/** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source\n  * @{\n  */\n#define RCC_SAIBCLKSOURCE_PLLSAI             0x00000000U\n#define RCC_SAIBCLKSOURCE_PLLI2S             0x00400000U\n#define RCC_SAIBCLKSOURCE_EXT                0x00800000U\n/**\n  * @}\n  */ \n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n      \n#if defined(STM32F469xx) || defined(STM32F479xx)\n/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source\n  * @{\n  */\n#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U\n#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source\n  * @{\n  */\n#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U\n#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)\n/**\n  * @}\n  */    \n  \n/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source\n  * @{\n  */\n#define RCC_DSICLKSOURCE_DSIPHY             0x00000000U\n#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)\n/**\n  * @}\n  */\n#endif /* STM32F469xx || STM32F479xx */\n\n#if defined(STM32F446xx)\n/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source \n  * @{\n  */\n#define RCC_SAI1CLKSOURCE_PLLSAI             0x00000000U\n#define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)\n#define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)\n#define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)\n/**\n  * @}\n  */ \n\n/** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source\n  * @{\n  */\n#define RCC_SAI2CLKSOURCE_PLLSAI             0x00000000U\n#define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)\n#define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)\n#define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source\n  * @{\n  */\n#define RCC_I2SAPB1CLKSOURCE_PLLI2S          0x00000000U\n#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)\n#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)\n#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)\n/**\n  * @}\n  */ \n\n/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source\n  * @{\n  */\n#define RCC_I2SAPB2CLKSOURCE_PLLI2S          0x00000000U\n#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)\n#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)\n#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source\n  * @{\n  */\n#define RCC_FMPI2C1CLKSOURCE_PCLK1            0x00000000U\n#define RCC_FMPI2C1CLKSOURCE_SYSCLK           ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)\n#define RCC_FMPI2C1CLKSOURCE_HSI              ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source\n  * @{\n  */\n#define RCC_CECCLKSOURCE_HSI                0x00000000U\n#define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source\n  * @{\n  */\n#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U\n#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source\n  * @{\n  */\n#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U\n#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source\n  * @{\n  */\n#define RCC_SPDIFRXCLKSOURCE_PLLR           0x00000000U\n#define RCC_SPDIFRXCLKSOURCE_PLLI2SP        ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)\n/**\n  * @}\n  */\n\n#endif /* STM32F446xx */\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup RCCEx_SAI1_BlockA_Clock_Source  RCC SAI BlockA Clock Source\n  * @{\n  */\n#define RCC_SAIACLKSOURCE_PLLI2SR            0x00000000U\n#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)\n#define RCC_SAIACLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)\n#define RCC_SAIACLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)\n/**\n  * @}\n  */ \n\n/** @defgroup RCCEx_SAI1_BlockB_Clock_Source  RCC SAI BlockB Clock Source\n  * @{\n  */\n#define RCC_SAIBCLKSOURCE_PLLI2SR            0x00000000U\n#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)\n#define RCC_SAIBCLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)\n#define RCC_SAIBCLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)\n/**\n  * @}\n  */ \n      \n/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source\n  * @{\n  */\n#define RCC_LPTIM1CLKSOURCE_PCLK1           0x00000000U\n#define RCC_LPTIM1CLKSOURCE_HSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)\n#define RCC_LPTIM1CLKSOURCE_LSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)\n#define RCC_LPTIM1CLKSOURCE_LSE             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)\n/**\n  * @}\n  */\n      \n\n/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source  RCC DFSDM2 Audio Clock Source\n  * @{\n  */\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1       0x00000000U\n#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source  RCC DFSDM2 Kernel Clock Source\n  * @{\n  */\n#define RCC_DFSDM2CLKSOURCE_PCLK2           0x00000000U\n#define RCC_DFSDM2CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)\n/**\n  * @}\n  */\n\n#endif /* STM32F413xx || STM32F423xx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source\n  * @{\n  */\n#define RCC_PLLI2SCLKSOURCE_PLLSRC          0x00000000U \n#define RCC_PLLI2SCLKSOURCE_EXT             ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source\n  * @{\n  */\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1       0x00000000U\n#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source\n  * @{\n  */\n#define RCC_DFSDM1CLKSOURCE_PCLK2           0x00000000U\n#define RCC_DFSDM1CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source\n  * @{\n  */\n#define RCC_I2SAPB1CLKSOURCE_PLLI2S         0x00000000U\n#define RCC_I2SAPB1CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)\n#define RCC_I2SAPB1CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)\n#define RCC_I2SAPB1CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S1SRC)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source\n  * @{\n  */\n#define RCC_I2SAPB2CLKSOURCE_PLLI2S         0x00000000U\n#define RCC_I2SAPB2CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)\n#define RCC_I2SAPB2CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)\n#define RCC_I2SAPB2CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S2SRC)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source\n  * @{\n  */\n#define RCC_FMPI2C1CLKSOURCE_PCLK1          0x00000000U\n#define RCC_FMPI2C1CLKSOURCE_SYSCLK         ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)\n#define RCC_FMPI2C1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source\n  * @{\n  */\n#define RCC_CLK48CLKSOURCE_PLLQ             0x00000000U\n#define RCC_CLK48CLKSOURCE_PLLI2SQ          ((uint32_t)RCC_DCKCFGR2_CK48MSEL)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source\n  * @{\n  */\n#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U\n#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)\n/**\n  * @}\n  */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n\n/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source\n  * @{\n  */\n#define RCC_I2SAPBCLKSOURCE_PLLR            0x00000000U\n#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)\n#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source\n  * @{\n  */\n#define RCC_FMPI2C1CLKSOURCE_PCLK1              0x00000000U\n#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)\n#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source\n  * @{\n  */\n#define RCC_LPTIM1CLKSOURCE_PCLK1          0x00000000U\n#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)\n#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)\n#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)\n/**\n  * @}\n  */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection\n  * @{\n  */\n#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)\n#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)\n/**\n  * @}\n  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\\\n          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n/** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection\n  * @{\n  */\n#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)\n#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)\n/**\n  * @}\n  */\n#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\\\n          STM32F412Rx || STM32F412Cx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source\n  * @{\n  */\n#define RCC_MCO2SOURCE_SYSCLK            0x00000000U\n#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0\n#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1\n#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2\n/**\n  * @}\n  */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F413xx | STM32F423xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source\n  * @{\n  */\n#define RCC_MCO2SOURCE_SYSCLK            0x00000000U\n#define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0\n#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1\n#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2\n/**\n  * @}\n  */\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/**\n  * @}\n  */\n     \n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros\n  * @{\n  */\n/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CRC_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\n                                         UNUSED(tmpreg); \\\n                                         } while(0U)\n#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \\\n                                         __IO uint32_t tmpreg = 0x00U; \\\n                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\n                                         /* Delay after an RCC peripheral clock enabling */ \\\n                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\n                                         UNUSED(tmpreg); \\\n                                         } while(0U)\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\n#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\n#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\n#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))\n#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))\n#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))\n#define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\n#define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\n#define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\n#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\n#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\n#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))\n#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n\n/**\n  * @brief  Enable ETHERNET clock.\n  */\n#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \\\n                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \\\n                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \\\n                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \\\n                                      } while(0U)\n/**\n  * @brief  Disable ETHERNET clock.\n  */\n#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \\\n                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \\\n                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \\\n                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \\\n                                        } while(0U)\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) \n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) \n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\n#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) \n#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) \n#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)\n#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) \n#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) \n#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\n#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\n#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\n#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) \n#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)\n#define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \\\n                                                    __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\\n                                                    __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) \n\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) \n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) \n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\n#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) \n#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) \n#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)\n#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) \n#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) \n#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\n#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\n#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)\n#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) \n#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\n#define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \\\n                                                     __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\\n                                                     __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\n\n#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)\n#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_HASH_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\n#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))\n#endif /* STM32F437xx || STM32F439xx || STM32F479xx */\n\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n\n#define __HAL_RCC_RNG_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */ \n#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\n#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\n\n#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)\n#define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)\n#define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)\n\n#define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)\n#define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)\n#endif /* STM32F437xx || STM32F439xx || STM32F479xx */\n\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\n\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) \n#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)     \n/**\n  * @}\n  */   \n\n/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{  \n  */\n#define __HAL_RCC_FMC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n\n/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\n#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\n#endif /* STM32F469xx || STM32F479xx */  \n/**\n  * @}\n  */\n    \n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USART3_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART4_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART5_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DAC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART7_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART8_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\n#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\n#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\n#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\n#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\n#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\n#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\n#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\n#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\n#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\n#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\n#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\n#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) \n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) \n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) \n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) \n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) \n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)  \n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) \n#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) \n#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) \n#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) \n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\n#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) \n#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\n#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) \n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) \n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) \n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) \n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) \n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) \n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)  \n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) \n#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) \n#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) \n#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) \n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\n#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) \n#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\n#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) \n/**\n  * @}\n  */\n    \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\n#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\n#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\n#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\n#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))\n#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\n\n#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_LTDC_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))\n#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_DSI_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */  \n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\n#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)\n#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) \n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) \n#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) \n#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) \n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)\n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)  \n\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)\n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)\n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\n#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)\n#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\n#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)\n#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\n\n#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)\n#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)\n#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)\n#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\n#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))\n#define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))\n#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))\n#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\n#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))\n#define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))\n#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))\n#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\n\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\n\n#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) \n#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\n#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\n\n#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\n#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\n#endif /* STM32F437xx || STM32F439xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\n#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\n#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))  \n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\n#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\n\n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\n#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\n#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\n#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\n#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))\n#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\n#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\n\n#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\n#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\n#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))\n#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\n\n#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))\n#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))\n#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))\n#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))\n#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))\n#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))\n#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\n\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))\n#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))\n#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\n\n#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\n#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\n\n#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) \n#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\n#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\n\n#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\n#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\n#endif /* STM32F437xx || STM32F439xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\n#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */  \n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\n#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\n#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))\n/**\n  * @}\n  */\n                                        \n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */ \n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\n#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))\n#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\n\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\n#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))\n#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\n\n#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))\n\n#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))\n#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))\n#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))\n#endif /* STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CRC_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\n#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\n#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\n#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\n#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))\n#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n#if defined(STM32F407xx)|| defined(STM32F417xx)\n/**\n  * @brief  Enable ETHERNET clock.\n  */\n#define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \\\n                                       __IO uint32_t tmpreg = 0x00U; \\\n                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\n                                       /* Delay after an RCC peripheral clock enabling */ \\\n                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\\\n                                       UNUSED(tmpreg); \\\n                                       } while(0U)\n#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \\\n                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \\\n                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \\\n                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \\\n                                        } while(0U)\n\n/**\n  * @brief  Disable ETHERNET clock.\n  */\n#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))\n#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))\n#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))\n#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))  \n#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \\\n                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \\\n                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \\\n                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \\\n                                          } while(0U)\n#endif /* STM32F407xx || STM32F417xx */\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */  \n#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)\n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)\n#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\n#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)\n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)\n\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\n#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)\n#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)\n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)\n#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)\n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)\n#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\n#if defined(STM32F407xx)|| defined(STM32F417xx)\n/**\n  * @brief  Enable ETHERNET clock.\n  */\n#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)\n#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)\n#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)\n#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)\n#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \\\n                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \\\n                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())\n/**\n  * @brief  Disable ETHERNET clock.\n  */\n#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)\n#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)\n#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)\n#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)\n#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \\\n                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \\\n                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())\n#endif /* STM32F407xx || STM32F417xx */\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable \n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n\n#define __HAL_RCC_RNG_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\n\n#if defined(STM32F407xx)|| defined(STM32F417xx) \n#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\n#endif /* STM32F407xx || STM32F417xx */\n\n#if defined(STM32F415xx) || defined(STM32F417xx)\n#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_HASH_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))\n#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))\n#endif /* STM32F415xx || STM32F417xx */\n/**\n  * @}\n  */\n\n\n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) \n\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   \n#define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) \n\n#if defined(STM32F407xx)|| defined(STM32F417xx) \n#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) \n#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) \n#endif /* STM32F407xx || STM32F417xx */\n\n#if defined(STM32F415xx) || defined(STM32F417xx)\n#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) \n#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) \n\n#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) \n#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) \n#endif /* STM32F415xx || STM32F417xx */  \n/**\n  * @}\n  */  \n  \n/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{  \n  */\n#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) \n#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) \n/**\n  * @}\n  */   \n   \n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{  \n  */\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USART3_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART4_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART5_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DAC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\n#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\n#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\n#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\n#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\n#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\n#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\n#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\n#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\n#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\n#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\n/**\n  * @}\n  */\n \n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */ \n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) \n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) \n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) \n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) \n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) \n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) \n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) \n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) \n#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) \n#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) \n#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) \n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) \n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) \n#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) \n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) \n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) \n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) \n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) \n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) \n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) \n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) \n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) \n#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) \n#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) \n#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) \n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) \n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) \n#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) \n  /**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */ \n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\n#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\n#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  \n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)  \n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) \n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) \n#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) \n#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)\n  \n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  \n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)  \n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) \n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) \n#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) \n#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)\n/**\n  * @}\n  */\n    \n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))\n#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))\n#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU) \n#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)\n\n#if defined(STM32F407xx)|| defined(STM32F417xx)  \n#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\n#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\n#endif /* STM32F407xx || STM32F417xx */\n\n#if defined(STM32F415xx) || defined(STM32F417xx) \n#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))\n#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))\n\n#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))\n#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))\n#endif /* STM32F415xx || STM32F417xx */\n   \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n\n#define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))\n#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\n\n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\n#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\n#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\n                                          \n#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\n/**\n  * @}\n  */\n                                        \n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\n\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))\n#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))\n#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))\n#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\n\n#if defined(STM32F407xx)|| defined(STM32F417xx) \n#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\n#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\n#endif /* STM32F407xx || STM32F417xx */\n\n#if defined(STM32F415xx) || defined(STM32F417xx) \n#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))\n#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))\n\n#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))\n#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))\n#endif /* STM32F415xx || STM32F417xx */\n/**\n  * @}\n  */\n                                        \n/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))\n#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))\n/**\n  * @}\n  */\n                                        \n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\n/**\n  * @}\n  */\n                                        \n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\n\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\n/**\n  * @}\n  */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------------- STM32F401xE/STM32F401xC --------------------------*/\n#if defined(STM32F401xC) || defined(STM32F401xE)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.   \n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CRC_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)  \n#define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)  \n\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)  \n#define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)  \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  \n/**\n  * @}\n  */ \n  \n/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\n/**\n  * @}\n  */  \n  \n/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) \n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) \n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) \n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) \n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) \n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) \n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\n/**\n  * @}\n  */ \n  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  \n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   \n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  \n\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)\n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) \n#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) \n/**\n  * @}\n  */\n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */  \n#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)\n#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  \n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\n\n#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) \n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  \n#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\n\n#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)\n#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable \n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\n\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\n/**\n  * @}\n  */\n#endif /* STM32F401xC || STM32F401xE*/\n/*----------------------------------------------------------------------------*/\n\n/*-------------------------------- STM32F410xx -------------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable     \n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_CRC_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_RNG_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n#define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_CRC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)\n      \n#define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\n#define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable  \n  * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.\n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U) \n#define __HAL_RCC_DAC_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n                                        \n#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\n#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))\n#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\n#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))\n#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */  \n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) \n#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)\n#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) \n#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)  \n#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) \n\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) \n#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)\n#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) \n#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)  \n#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)  \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable  \n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @{\n  */  \n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\n#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)  \n#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)  \n  \n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)  \n#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)  \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n#define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))\n#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()\n#define __HAL_RCC_AHB2_RELEASE_RESET()\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET()\n#define __HAL_RCC_AHB3_RELEASE_RESET()\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))\n#define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\n\n#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\n#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\n#define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))                                        \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable  \n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable                                         \n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\n#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))\n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\n\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\n#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))\n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable                                         \n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @{\n  */\n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\n#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))                                \n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))                                        \n#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))\n/**\n  * @}\n  */\n\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/*----------------------------------------------------------------------------*/\n\n/*-------------------------------- STM32F411xx -------------------------------*/\n#if defined(STM32F411xE)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CRC_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))\n#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */  \n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) \n#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) \n\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) \n#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n\n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\n/**\n  * @}\n  */  \n\n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it. \n  * @{\n  */\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n/**\n  * @}\n  */ \n  \n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) \n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) \n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) \n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) \n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) \n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) \n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) \n/**\n  * @}\n  */ \n  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @{\n  */\n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  \n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   \n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  \n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) \n\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  \n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)   \n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  \n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)   \n/**\n  * @}\n  */  \n  \n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\n\n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\n#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\n\n#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable \n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n                                        \n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))                                        \n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable \n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @{\n  */\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable \n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @{\n  */\n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\n\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\n/**\n  * @}\n  */\n#endif /* STM32F411xE */\n/*----------------------------------------------------------------------------*/\n\n/*---------------------------------- STM32F446xx -----------------------------*/\n#if defined(STM32F446xx)\n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_CRC_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                        UNUSED(tmpreg); \\\n                                        } while(0U)\n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\n#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))\n#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))\n#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))\n#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) \n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) \n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) \n#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)  \n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) \n#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)  \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)  \n#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) \n\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) \n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) \n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) \n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) \n#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)  \n#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) \n#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)  \n#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  \n#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) \n/**\n  * @}\n  */  \n  \n/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n\n#define __HAL_RCC_RNG_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)\n#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)\n\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\n\n#define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) \n#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it. \n  * @{\n  */\n#define __HAL_RCC_FMC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))\n#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)\n#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)\n\n#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it. \n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USART3_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART4_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART5_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CEC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_DAC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\n#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\n#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\n#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\n#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))\n#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))\n#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\n#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\n#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\n#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))\n#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\n#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\n#define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))\n#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) \n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)\n#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)\n#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\n#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)\n#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)\n#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)\n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)\n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\n#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)\n#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)\n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) \n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\n#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)\n#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\n#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)\n#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)\n#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)\n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\n#define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)\n#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\n#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))\n#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))\n#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))\n#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) \n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) \n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  \n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\n#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) \n#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) \n#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)\n#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)\n\n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) \n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) \n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  \n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\n#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) \n#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) \n#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)\n#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\n#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))\n#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))\n\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n\n#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))\n#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\n\n#define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))\n#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))\n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))\n                                          \n#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))\n#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))\n#define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))\n#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\n#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\n#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\n#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))\n#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset \n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\n#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) \n#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))\n#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))\n\n#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\n#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\n#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable \n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))\n\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\n#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))\n#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\n\n#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))\n#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\n\n#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */ \n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))\n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))\n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\n#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))\n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\n#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))\n#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\n#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))\n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))\n\n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))\n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\n#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))\n#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))\n#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\n#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))\n/**\n  * @}\n  */\n\n#endif /* STM32F446xx */\n/*----------------------------------------------------------------------------*/\n\n/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) \n/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)                                        \n#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */                                       \n#define __HAL_RCC_CRC_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)                                        \n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) \n#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))\n#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */\n#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)\n#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */\n#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)\n\n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)\n#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */\n#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#if defined(STM32F423xx)\n#define __HAL_RCC_AES_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))\n#endif /* STM32F423xx */\n                                        \n#define __HAL_RCC_RNG_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))\n                                     \n#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\\\n                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\\\n                                              }while(0U)\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#if defined(STM32F423xx)\n#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)\n#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)\n#endif /* STM32F423xx */\n                                        \n#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)\n#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)\n          \n#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   \n#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   \n/**\n  * @}\n  */  \n\n/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable\n  * @brief  Enables or disables the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it. \n  * @{\n  */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))\n#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the AHB3 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) \n#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) \n\n#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)\n#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */\n\n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it. \n  * @{\n  */\n#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)                                        \n#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F413xx || STM32F423xx */  \n#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_USART3_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART5_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F413xx || STM32F423xx */\n                                        \n#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F413xx || STM32F423xx */\n#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DAC_CLK_ENABLE()    do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART7_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART8_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#endif /* STM32F413xx || STM32F423xx */\n                                        \n#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))\n#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))\n#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))\n#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))\n#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))\n#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))\n#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))\n#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) \n#if defined(STM32F413xx) || defined(STM32F423xx)                 \n#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))\n#endif /* STM32F413xx || STM32F423xx */\n#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))                                       \n#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))\n#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))\n#if defined(STM32F413xx) || defined(STM32F423xx)   \n#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))\n#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))\n#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))\n#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))\n#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))                                        \n#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))\n#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))\n#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n                                        \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB1 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) \n#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)\n#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)\n#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)\n#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)\n#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)\n#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)\n#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) \n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) \n#endif /* STM32F413xx || STM32F423xx */                                            \n#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)                                    \n#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)\n#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) \n#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)\n#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)\n#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)\n#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)\n#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) \n#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)\n#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) \n#endif /* STM32F413xx || STM32F423xx */                                         \n\n#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) \n#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)\n#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)\n#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)\n#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)\n#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)\n#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)\n#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)                                          \n#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) \n#endif /* STM32F413xx || STM32F423xx */                                         \n#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)                                        \n#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)\n#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)                                           \n#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) \n#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) \n#endif /* STM32F413xx || STM32F423xx */                                          \n#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)\n#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)\n#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)\n#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)                                        \n#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)\n#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) \n#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)\n#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)\n#endif /* STM32F413xx || STM32F423xx */                                         \n/**\n  * @}\n  */  \n/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable\n  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before \n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_UART10_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)                                          \n#endif /* STM32F413xx || STM32F423xx */                                   \n#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U) \n#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U)\n#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)                                        \n#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \\\n                                        __IO uint32_t tmpreg = 0x00U; \\\n                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        /* Delay after an RCC peripheral clock enabling */ \\\n                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\\\n                                        UNUSED(tmpreg); \\\n                                      } while(0U) \n#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)                                         \n#endif /* STM32F413xx || STM32F423xx */                                          \n#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \\\n                                      __IO uint32_t tmpreg = 0x00U; \\\n                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\\\n                                      /* Delay after an RCC peripheral clock enabling */ \\\n                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\\\n                                      UNUSED(tmpreg); \\\n                                      } while(0U)                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n \n#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))\n#define __HAL_RCC_UART10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                         \n#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))\n#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))\n#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))\n#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))\n#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))                                      \n#endif /* STM32F413xx || STM32F423xx */                                         \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status\n  * @brief  Get the enable or disable status of the APB2 peripheral clock.\n  * @note   After reset, the peripheral clock (used for registers read/write access)\n  *         is disabled and the application software has to enable this clock before\n  *         using it.\n  * @{\n  */\n#define __HAL_RCC_TIM8_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)\n#define __HAL_RCC_UART10_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)                                        \n#endif /* STM32F413xx || STM32F423xx */                                          \n#define __HAL_RCC_SDIO_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) \n#define __HAL_RCC_SPI4_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)\n#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)\n#define __HAL_RCC_TIM10_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)\n#define __HAL_RCC_SPI5_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)                                    \n#endif /* STM32F413xx || STM32F423xx */                                         \n#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)                                  \n#endif /* STM32F413xx || STM32F423xx */                                         \n\n#define __HAL_RCC_TIM8_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) \n#define __HAL_RCC_UART10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)                                         \n#endif /* STM32F413xx || STM32F423xx */                                         \n#define __HAL_RCC_SDIO_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) \n#define __HAL_RCC_SPI4_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)\n#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)\n#define __HAL_RCC_TIM10_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)\n#define __HAL_RCC_SPI5_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)                                       \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)                                       \n#endif /* STM32F413xx || STM32F423xx */                                         \n/**\n  * @}\n  */\n  \n/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset \n  * @brief  Force or release AHB1 peripheral reset.\n  * @{\n  */\n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */\n#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))\n\n#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))\n#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))\n#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */\n#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))\n#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))\n#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */\n#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset \n  * @brief  Force or release AHB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)\n\n#if defined(STM32F423xx)\n#define __HAL_RCC_AES_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))\n#define __HAL_RCC_AES_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))                                        \n#endif /* STM32F423xx */ \n                                        \n#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))\n#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))\n\n#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))\n#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset \n  * @brief  Force or release AHB3 peripheral reset.\n  * @{\n  */ \n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)\n#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) \n\n#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))\n#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))\n\n#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))\n#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ \n#if defined(STM32F412Cx)\n#define __HAL_RCC_AHB3_FORCE_RESET()\n#define __HAL_RCC_AHB3_RELEASE_RESET()\n\n#define __HAL_RCC_FSMC_FORCE_RESET()\n#define __HAL_RCC_QSPI_FORCE_RESET()\n\n#define __HAL_RCC_FSMC_RELEASE_RESET()\n#define __HAL_RCC_QSPI_RELEASE_RESET()\n#endif /* STM32F412Cx */\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset \n  * @brief  Force or release APB1 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) \n#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))                                        \n#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) \n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))                                        \n#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))                                        \n#endif /* STM32F413xx || STM32F423xx */                                          \n#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))                                        \n#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))\n#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))\n#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n\n#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))\n#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))\n#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))\n#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))\n#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))\n#define __HAL_RCC_TIM12_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))\n#define __HAL_RCC_TIM13_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))\n#define __HAL_RCC_TIM14_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) \n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SPI3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))\n#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))\n#define __HAL_RCC_UART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_I2C3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))                                        \n#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))\n#define __HAL_RCC_CAN1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))\n#define __HAL_RCC_CAN2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))\n#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))\n#define __HAL_RCC_UART7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))\n#define __HAL_RCC_UART8_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))                                      \n#endif /* STM32F413xx || STM32F423xx */                                         \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset\n  * @brief  Force or release APB2 peripheral reset.\n  * @{\n  */\n#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))\n#define __HAL_RCC_UART10_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))                                        \n#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))\n#endif /* STM32F413xx || STM32F423xx */                                         \n#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))\n#endif /* STM32F413xx || STM32F423xx */                                        \n\n#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))\n#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))\n#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))\n#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))\n#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))\n#endif /* STM32F413xx || STM32F423xx */                                        \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n\n#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))\n#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))\n#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))\n#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))\n#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))\n#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))\n#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#if defined(STM32F423xx)\n#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()      (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))                                        \n#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()     (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))\n#endif /* STM32F423xx */\n                                        \n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))\n#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))\n\n#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))\n#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))\n#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))\n\n#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))\n#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */\n\n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))                                        \n#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))                                       \n#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))                                        \n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))\n#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n\n#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))\n#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))\n#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))\n#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))\n#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))\n#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))\n#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))\n#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))\n#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))                                        \n#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))\n#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                \n#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))                                        \n#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))\n#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))\n#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))\n#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))\n#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))\n#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                     \n/**\n  * @}\n  */\n\n/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable\n  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.\n  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce\n  *         power consumption.\n  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.\n  * @note   By default, all peripheral clocks are enabled during SLEEP mode.\n  * @{\n  */\n#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))\n#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))  \n#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) \n#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))                                        \n#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))\n#endif /* STM32F413xx || STM32F423xx */\n                                        \n#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))\n#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))                                        \n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))\n#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))\n#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))\n#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))    \n#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))\n#endif /* STM32F413xx || STM32F423xx */                                        \n/**\n  * @}\n  */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------------------- PLL Configuration --------------------------*/\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\n  * @note   This function must be used only when the main PLL is disabled.\n  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  \n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 2 MHz to limit PLL jitter.\n  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\n  *         output frequency is between 100 and 432 MHz.\n  *   \n  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\n  *           \n  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  * @note   If the USB OTG FS is used in your application, you have to set the\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\n  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work\n  *         correctly.\n  *     \n  * @param  __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/\n            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.\n  *      \n  */\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \\\n                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \\\n                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \\\n                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \\\n                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \\\n                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))\n#else\n/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.\n  * @note   This function must be used only when the main PLL is disabled.\n  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry\n  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry\n  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  \n  * @param  __PLLM__ specifies the division factor for PLL VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 2 MHz to limit PLL jitter.\n  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432\n  *         Except for STM32F411xE devices where Min_Data = 192.\n  * @note   You have to set the PLLN parameter correctly to ensure that the VCO\n  *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices\n  *         where frequency is between 192 and 432 MHz.\n  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\n  *           \n  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  * @note   If the USB OTG FS is used in your application, you have to set the\n  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,\n  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work\n  *         correctly.\n  *      \n  */\n#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \\\n                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \\\n                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                | \\\n                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)    | \\\n                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))\n #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n/*----------------------------------------------------------------------------*/\n                             \n/*----------------------------PLLI2S Configuration ---------------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n\n/** @brief Macros to enable or disable the PLLI2S. \n  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.\n  */\n#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)\n#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \n          STM32F412Rx || STM32F412Cx */\n#if defined(STM32F446xx)\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   PLLI2S clock source is common with the main PLL (configured in \n  *         HAL_RCC_ClockConfig() API).\n  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 1 MHz to limit PLLI2S jitter.\n  *\n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLI2SP__ specifies division factor for SPDIFRX Clock.\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\n  * @note   the PLLI2SP parameter is only available with STM32F446xx Devices\n  *                 \n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\n  *         on the I2S clock frequency.\n  *   \n  * @param  __PLLI2SQ__ specifies the division factor for SAI clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  */\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \\\n                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\\\n                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\\\n                               ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\\\n                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\\\n                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))\n#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n      defined(STM32F413xx) || defined(STM32F423xx)\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   PLLI2S clock source is common with the main PLL (configured in \n  *         HAL_RCC_ClockConfig() API).\n  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 1 MHz to limit PLLI2S jitter.\n  *\n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\n  *         on the I2S clock frequency.\n  *\n  * @param  __PLLI2SQ__ specifies the division factor for SAI clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  */\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \\\n                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\\\n                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\\\n                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\\\n                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))\n#else\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   PLLI2S clock source is common with the main PLL (configured in \n  *         HAL_RCC_ClockConfig() API).\n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\n  *         on the I2S clock frequency.\n  *\n  */\n#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \\\n                               (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)  |\\\n                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))\n#endif /* STM32F446xx */\n\n#if defined(STM32F411xE)\n/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   PLLI2S clock source is common with the main PLL (configured in \n  *         HAL_RCC_ClockConfig() API).\n  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices\n  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 2 MHz to limit PLLI2S jitter.    \n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock\n  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\n  *         on the I2S clock frequency.\n  */\n#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\\\n                                                                                                  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\\\n                                                                                                  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))\n#endif /* STM32F411xE */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.\n  * @note   This macro must be used only when the PLLI2S is disabled.\n  * @note   PLLI2S clock source is common with the main PLL (configured in \n  *         HAL_RCC_ClockConfig() API)             \n  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  * @param  __PLLI2SQ__ specifies the division factor for SAI1 clock.\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. \n  * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx \n  *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro\n  * @param  __PLLI2SR__ specifies the division factor for I2S clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz\n  *         on the I2S clock frequency.\n  */\n#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U)  |\\\n                                                                                                 ((__PLLI2SQ__) << 24U) |\\\n                                                                                                 ((__PLLI2SR__) << 28U))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */   \n/*----------------------------------------------------------------------------*/\n\n/*------------------------------ PLLSAI Configuration ------------------------*/\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief Macros to Enable or Disable the PLLISAI. \n  * @note  The PLLSAI is only available with STM32F429x/439x Devices.\n  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. \n  */\n#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)\n#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)\n\n#if defined(STM32F446xx)\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\n  *\n  * @param  __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.\n  * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input\n  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency\n  *         of 1 MHz to limit PLLI2S jitter.\n  * @note   The PLLSAIM parameter is only used with STM32F446xx Devices\n  *             \n  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\n  * @note   the PLLSAIP parameter is only available with STM32F446xx Devices\n  *                 \n  * @param  __PLLSAIQ__ specifies the division factor for SAI clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  *           \n  * @param  __PLLSAIR__ specifies the division factor for LTDC clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  \n  */\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \\\n                               (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \\\n                               ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             | \\\n                               ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \\\n                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) \n#endif /* STM32F446xx */\n                                 \n#if defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\n  *             \n  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.\n  *         This parameter must be a number in the range {2, 4, 6, or 8}.\n  *                 \n  * @param  __PLLSAIQ__ specifies the division factor for SAI clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  *           \n  * @param  __PLLSAIR__ specifies the division factor for LTDC clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.  \n  */\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \\\n                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             |\\\n                                                   ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\\\n                                                   ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)             |\\\n                                                   ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))\n#endif /* STM32F469xx || STM32F479xx */                                 \n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.\n  *             \n  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.\n  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.\n  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO \n  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.\n  *\n  * @param  __PLLSAIQ__ specifies the division factor for SAI clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.\n  *           \n  * @param  __PLLSAIR__ specifies the division factor for LTDC clock\n  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.\n  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  \n  */\n#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \\\n                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)  | \\\n                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                      | \\\n                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)\n/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.\n  * @note   This function must be called before enabling the PLLI2S.\n  * @param  __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.\n  *          This parameter must be a number between 1 and 32.\n  *          SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ \n  */\n#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))\n\n/** @brief  Macro to configure the SAI clock Divider coming from PLL.\n  * @param  __PLLDivR__ specifies the PLL division factor for SAI1 clock.\n  *          This parameter must be a number between 1 and 32.\n  *          SAI1 clock frequency = f(PLLR) / __PLLDivR__ \n  */\n#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))                                 \n#endif /* STM32F413xx || STM32F423xx */  \n                                 \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.\n  * @note   This function must be called before enabling the PLLI2S.\n  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.\n  *          This parameter must be a number between 1 and 32.\n  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ \n  */\n#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))\n\n/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.\n  * @note   This function must be called before enabling the PLLSAI.\n  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .\n  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.\n  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  \n  */\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.\n  * \n  * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.\n  * @note   This function must be called before enabling the PLLSAI. \n  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .\n  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.\n  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ \n  */\n#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n/*----------------------------------------------------------------------------*/\n\n/*------------------------- Peripheral Clock selection -----------------------*/\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx)\n/** @brief  Macro to configure the I2S clock source (I2SCLK).\n  * @note   This function must be called before enabling the I2S APB clock.\n  * @param  __SOURCE__ specifies the I2S clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\n  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\n  *                                       used as I2S clock source.\n  */\n#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))\n\n\n/** @brief  Macro to get the I2S clock source (I2SCLK).\n  * @retval The clock source can be one of the following values:\n  *            @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.\n  *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin\n  *                                        used as I2S clock source\n  */\n#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))\n#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */\n                                 \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n                                 \n/** @brief  Macro to configure SAI1BlockA clock source selection.\n  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.      \n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI Block A clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \n  *                                           as SAI1 Block A clock. \n  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \n  *                                           as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin\n  *                                        used as SAI1 Block A clock.\n  */\n#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))\n\n/** @brief  Macro to configure SAI1BlockB clock source selection.\n  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI Block B clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used \n  *                                           as SAI1 Block B clock. \n  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used \n  *                                           as SAI1 Block B clock. \n  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin\n  *                                        used as SAI1 Block B clock.\n  */\n#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F446xx)\n/** @brief  Macro to configure SAI1 clock source selection.\n  * @note   This configuration is only available with STM32F446xx Devices.\n  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. \n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.\n  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  \n  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.\n  */\n#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get SAI1 clock source selection.\n  * @note   This configuration is only available with STM32F446xx Devices.      \n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. \n  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.\n  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  \n  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.\n  */\n#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))\n\n/** @brief  Macro to configure SAI2 clock source selection.\n  * @note   This configuration is only available with STM32F446xx Devices.      \n  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI2 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. \n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.\n  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  \n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.\n  */\n#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get SAI2 clock source selection.\n  * @note   This configuration is only available with STM32F446xx Devices.      \n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. \n  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.\n  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  \n  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.\n  */\n#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))\n\n/** @brief  Macro to configure I2S APB1 clock source selection.\n  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.\n  * @param  __SOURCE__ specifies the I2S APB1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \n  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  \n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get I2S APB1 clock source selection.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \n  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  \n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))\n\n/** @brief  Macro to configure I2S APB2 clock source selection.\n  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.\n  * @param  __SOURCE__ specifies the SAI Block A clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \n  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  \n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get I2S APB2 clock source selection.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. \n  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  \n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))\n\n/** @brief  Macro to configure the CEC clock.\n  * @param  __SOURCE__ specifies the CEC clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\n  */\n#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the CEC clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock\n  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock\n  */\n#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))\n\n/** @brief  Macro to configure the FMPI2C1 clock.\n  * @param  __SOURCE__ specifies the FMPI2C1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the FMPI2C1 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))\n\n/** @brief  Macro to configure the CLK48 clock.\n  * @param  __SOURCE__ specifies the CLK48 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. \n  */\n#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the CLK48 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. \n  */\n#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))\n\n/** @brief  Macro to configure the SDIO clock.\n  * @param  __SOURCE__ specifies the SDIO clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the SDIO clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))\n\n/** @brief  Macro to configure the SPDIFRX clock.\n  * @param  __SOURCE__ specifies the SPDIFRX clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  \n  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. \n  */\n#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the SPDIFRX clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  \n  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. \n  */\n#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))\n#endif /* STM32F446xx */\n      \n#if defined(STM32F469xx) || defined(STM32F479xx)\n      \n/** @brief  Macro to configure the CLK48 clock.\n  * @param  __SOURCE__ specifies the CLK48 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. \n  */\n#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the CLK48 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. \n  */\n#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))\n\n/** @brief  Macro to configure the SDIO clock.\n  * @param  __SOURCE__ specifies the SDIO clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the SDIO clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  \n      \n/** @brief  Macro to configure the DSI clock.\n  * @param  __SOURCE__ specifies the DSI clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \n  */\n#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the DSI clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. \n  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. \n  */\n#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))       \n      \n#endif /* STM32F469xx || STM32F479xx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n /** @brief  Macro to configure the DFSDM1 clock.\n  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. \n  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.\n  * @retval None\n  */\n#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))\n\n/** @brief  Macro to get the DFSDM1 clock source.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. \n  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.\n  */\n#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))\n\n/** @brief  Macro to configure DFSDM1 Audio clock source selection.\n  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/\n            STM32F413xx/STM32F423xx Devices.\n  * @param  __SOURCE__ specifies the DFSDM1 Audio clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock\n  */\n#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))\n\n/** @brief  Macro to Get DFSDM1 Audio clock source selection.\n  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/\n            STM32F413xx/STM32F423xx Devices.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock\n  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock\n  */\n#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n /** @brief  Macro to configure the DFSDM2 clock.\n  * @param  __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. \n  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.\n  * @retval None\n  */\n#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))\n\n/** @brief  Macro to get the DFSDM2 clock source.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. \n  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.\n  */\n#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))\n\n/** @brief  Macro to configure DFSDM1 Audio clock source selection.\n  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.\n  * @param  __SOURCE__ specifies the DFSDM2 Audio clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock\n  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock\n  */\n#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))\n\n/** @brief  Macro to Get DFSDM2 Audio clock source selection.\n  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock\n  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock\n  */\n#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))\n      \n/** @brief  Macro to configure SAI1BlockA clock source selection.\n  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.      \n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI Block A clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))\n      \n/** @brief  Macro to Get SAI1 BlockA clock source selection.\n  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      \n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.\n  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))\n\n/** @brief  Macro to configure SAI1 BlockB clock source selection.\n  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.\n  * @note   This function must be called before enabling PLLSAI, PLLI2S and  \n  *         the SAI clock.\n  * @param  __SOURCE__ specifies the SAI Block B clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))\n      \n/** @brief  Macro to Get SAI1 BlockB clock source selection.\n  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      \n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.\n  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))\n\n/** @brief  Macro to configure the LPTIM1 clock.\n  * @param  __SOURCE__ specifies the LPTIM1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\n  */\n#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the LPTIM1 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\n  */\n#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))      \n#endif /* STM32F413xx || STM32F423xx */\n      \n/** @brief  Macro to configure I2S APB1 clock source selection.\n  * @param  __SOURCE__ specifies the I2S APB1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.\n  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get I2S APB1 clock source selection.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.\n  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.\n  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))\n\n/** @brief  Macro to configure I2S APB2 clock source selection.\n  * @param  __SOURCE__ specifies the I2S APB2 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.\n  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))\n\n/** @brief  Macro to Get I2S APB2 clock source selection.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.\n  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.\n  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  */\n#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))\n\n/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).\n  * @note   This macro must be called before enabling the I2S APB clock.\n  * @param  __SOURCE__ specifies the I2S clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.\n  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin\n  *                                       used as I2S clock source.\n  */\n#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))\n      \n/** @brief  Macro to configure the FMPI2C1 clock.\n  * @param  __SOURCE__ specifies the FMPI2C1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the FMPI2C1 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))\n\n/** @brief  Macro to configure the CLK48 clock.\n  * @param  __SOURCE__ specifies the CLK48 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.\n  */\n#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the CLK48 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. \n  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock\n  */\n#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))\n\n/** @brief  Macro to configure the SDIO clock.\n  * @param  __SOURCE__ specifies the SDIO clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the SDIO clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. \n  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. \n  */\n#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))\n\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** @brief  Macro to configure I2S clock source selection.\n  * @param  __SOURCE__ specifies the I2S clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.\n  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.\n  */\n#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))\n\n/** @brief  Macro to Get I2S clock source selection.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.\n  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.\n  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.\n  */\n#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))\n\n/** @brief  Macro to configure the FMPI2C1 clock.\n  * @param  __SOURCE__ specifies the FMPI2C1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the FMPI2C1 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock\n  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock\n  */\n#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))\n\n/** @brief  Macro to configure the LPTIM1 clock.\n  * @param  __SOURCE__ specifies the LPTIM1 clock source.\n  *         This parameter can be one of the following values:\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\n  */\n#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))\n\n/** @brief  Macro to Get the LPTIM1 clock.\n  * @retval The clock source can be one of the following values:\n  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock\n  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock\n  */\n#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n      \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/** @brief  Macro to configure the Timers clocks prescalers \n  * @note   This feature is only available with STM32F429x/439x Devices.  \n  * @param  __PRESC__  specifies the Timers clocks prescalers selection\n  *         This parameter can be one of the following values:\n  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is \n  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, \n  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to \n  *                 division by 4 or more.       \n  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is \n  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, \n  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding \n  *                 to division by 8 or more.\n  */     \n#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\\\n          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\\\n          STM32F423xx */\n\n/*----------------------------------------------------------------------------*/\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/** @brief Enable PLLSAI_RDY interrupt.\n  */\n#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))\n\n/** @brief Disable PLLSAI_RDY interrupt.\n  */\n#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))\n\n/** @brief Clear the PLLSAI RDY interrupt pending bits.\n  */\n#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))\n\n/** @brief Check the PLLSAI RDY interrupt has occurred or not.\n  * @retval The new state (TRUE or FALSE).\n  */\n#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))\n\n/** @brief  Check PLLSAI RDY flag is set or not.\n  * @retval The new state (TRUE or FALSE).\n  */\n#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/** @brief  Macros to enable or disable the RCC MCO1 feature.\n  */\n#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)\n#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)\n\n/** @brief  Macros to enable or disable the RCC MCO2 feature.\n  */\n#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)\n#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)\n\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup RCCEx_Exported_Functions\n  *  @{\n  */\n\n/** @addtogroup RCCEx_Exported_Functions_Group1\n  *  @{\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);\n\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\nvoid HAL_RCCEx_SelectLSEMode(uint8_t Mode);\n#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n#if defined(RCC_PLLI2S_SUPPORT)\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);\n#endif /* RCC_PLLI2S_SUPPORT */\n#if defined(RCC_PLLSAI_SUPPORT)\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);\n#endif /* RCC_PLLSAI_SUPPORT */\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup RCCEx_Private_Constants RCCEx Private Constants\n  * @{\n  */\n\n/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion\n  * @brief RCC registers bit address in the alias region\n  * @{\n  */\n/* --- CR Register ---*/  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/* Alias word address of PLLSAION bit */\n#define RCC_PLLSAION_BIT_NUMBER       0x1CU\n#define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))\n\n#define PLLSAI_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms  */\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/* Alias word address of PLLI2SON bit */\n#define RCC_PLLI2SON_BIT_NUMBER    0x1AU\n#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\n          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n/* --- DCKCFGR Register ---*/\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\\\n    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/* Alias word address of TIMPRE bit */\n#define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8CU)\n#define RCC_TIMPRE_BIT_NUMBER          0x18U\n#define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\\\n          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\\\n          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n/* --- CFGR Register ---*/\n#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/* Alias word address of I2SSRC bit */\n#define RCC_I2SSRC_BIT_NUMBER      0x17U\n#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))\n      \n#define PLLI2S_TIMEOUT_VALUE       2U  /* Timeout value fixed to 2 ms  */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */\n      \n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n/* --- PLLI2SCFGR Register ---*/\n#define RCC_PLLI2SCFGR_OFFSET         (RCC_OFFSET + 0x84U)\n/* Alias word address of PLLI2SSRC bit */\n#define RCC_PLLI2SSRC_BIT_NUMBER      0x16U\n#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))\n      \n#define PLLI2S_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/* Alias word address of MCO1EN bit */\n#define RCC_MCO1EN_BIT_NUMBER      0x8U\n#define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))\n\n/* Alias word address of MCO2EN bit */\n#define RCC_MCO2EN_BIT_NUMBER      0x9U\n#define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#define PLL_TIMEOUT_VALUE          2U  /* 2 ms */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup RCCEx_Private_Macros RCCEx Private Macros\n  * @{\n  */\n/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters\n  * @{\n  */\n#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))\n#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))\n      \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) \n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) \n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F446xx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))\n#endif /* STM32F446xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))\n#endif /* STM32F469xx || STM32F479xx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n      \n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))\n#endif /* STM32F413xx || STM32F423xx */\n      \n#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))\n\n#define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))\n\n#define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))\n\n#define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))\n\n#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))\n\n#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))\n\n#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\\\n                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\\\n                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\\\n                                         ((VALUE) == RCC_PLLSAIDIVR_16))\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((2U <= (VALUE)) && ((VALUE) <= 63U))\n \n#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\\\n                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))\n#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx  */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))\n\n#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\\\n                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))\n\n#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))\n\n#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\n\n#define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\\\n                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\\\n                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F446xx)\n#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))\n  \n#define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\\\n                                           ((VALUE) == RCC_PLLI2SP_DIV4) ||\\\n                                           ((VALUE) == RCC_PLLI2SP_DIV6) ||\\\n                                           ((VALUE) == RCC_PLLI2SP_DIV8))\n\n#define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)\n  \n#define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\\\n                                           ((VALUE) == RCC_PLLSAIP_DIV4) ||\\\n                                           ((VALUE) == RCC_PLLSAIP_DIV6) ||\\\n                                           ((VALUE) == RCC_PLLSAIP_DIV8))\n\n#define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\\\n                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))\n\n#define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\\\n                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))\n \n#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))\n                                              \n #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))\n\n#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))\n\n#define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\\\n                                           ((SOURCE) == RCC_CECCLKSOURCE_LSE))\n\n#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\\\n                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))\n\n#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\\\n                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))\n\n#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\\\n                                           ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))  \n#endif /* STM32F446xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n#define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))\n\n#define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\\\n                                             ((VALUE) == RCC_PLLSAIP_DIV4) ||\\\n                                             ((VALUE) == RCC_PLLSAIP_DIV6) ||\\\n                                             ((VALUE) == RCC_PLLSAIP_DIV8))\n \n#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\\\n                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))\n\n#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\\\n                                             ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))\n\n#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\\\n                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))\n\n#define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\\\n                                             ((MODE) == RCC_LSE_HIGHDRIVE_MODE))\n#endif /* STM32F469xx || STM32F479xx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))\n    \n#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))\n\n#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \\\n                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))\n \n#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))\n                                              \n #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\\\n                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))\n\n#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\\\n                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))\n\n#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\\\n                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))\n\n#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\\\n                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))\n\n#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \\\n                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))\n\n#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \\\n                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \\\n                                            ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))\n\n#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \\\n                                                 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))\n\n#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  ||\\\n                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))\n\n#define IS_RCC_SAIACLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\\\n                                          ((SOURCE) == RCC_SAIACLKSOURCE_EXT)     ||\\\n                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLR)    ||\\\n                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))\n\n#define IS_RCC_SAIBCLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\\\n                                          ((SOURCE) == RCC_SAIBCLKSOURCE_EXT)     ||\\\n                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR)    ||\\\n                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))\n\n#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))\n\n#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))\n\n#endif /* STM32F413xx || STM32F423xx */\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \\\n    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \\\n    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)\n      \n#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \\\n                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\n\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\n          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \\\n          STM32F412Rx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      \n#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \\\n                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */  \n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_RCC_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_spi.h\n  * @author  MCD Application Team\n  * @brief   Header file of SPI HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_SPI_H\n#define STM32F4xx_HAL_SPI_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup SPI\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup SPI_Exported_Types SPI Exported Types\n  * @{\n  */\n\n/**\n  * @brief  SPI Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t Mode;                /*!< Specifies the SPI operating mode.\n                                     This parameter can be a value of @ref SPI_Mode */\n\n  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.\n                                     This parameter can be a value of @ref SPI_Direction */\n\n  uint32_t DataSize;            /*!< Specifies the SPI data size.\n                                     This parameter can be a value of @ref SPI_Data_Size */\n\n  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.\n                                     This parameter can be a value of @ref SPI_Clock_Polarity */\n\n  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.\n                                     This parameter can be a value of @ref SPI_Clock_Phase */\n\n  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by\n                                     hardware (NSS pin) or by software using the SSI bit.\n                                     This parameter can be a value of @ref SPI_Slave_Select_management */\n\n  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be\n                                     used to configure the transmit and receive SCK clock.\n                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler\n                                     @note The communication clock is derived from the master\n                                     clock. The slave clock does not need to be set. */\n\n  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.\n                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */\n\n  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.\n                                     This parameter can be a value of @ref SPI_TI_mode */\n\n  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.\n                                     This parameter can be a value of @ref SPI_CRC_Calculation */\n\n  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.\n                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */\n} SPI_InitTypeDef;\n\n/**\n  * @brief  HAL SPI State structure definition\n  */\ntypedef enum\n{\n  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */\n  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */\n  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */\n  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */\n  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */\n  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */\n  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */\n  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */\n} HAL_SPI_StateTypeDef;\n\n/**\n  * @brief  SPI handle Structure definition\n  */\ntypedef struct __SPI_HandleTypeDef\n{\n  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */\n\n  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */\n\n  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */\n\n  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */\n\n  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */\n\n  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */\n\n  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */\n\n  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */\n\n  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */\n\n  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */\n\n  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */\n\n  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */\n\n  HAL_LockTypeDef            Lock;           /*!< Locking object                           */\n\n  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */\n\n  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */\n\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */\n  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */\n  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */\n  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */\n  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */\n  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */\n  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */\n  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */\n  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */\n  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */\n\n#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */\n} SPI_HandleTypeDef;\n\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n/**\n  * @brief  HAL SPI Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */\n  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */\n  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */\n  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */\n  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */\n  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */\n  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */\n  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */\n  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */\n  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */\n\n} HAL_SPI_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL SPI Callback pointer definition\n  */\ntypedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */\n\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup SPI_Exported_Constants SPI Exported Constants\n  * @{\n  */\n\n/** @defgroup SPI_Error_Code SPI Error Code\n  * @{\n  */\n#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */\n#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */\n#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */\n#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */\n#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */\n#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */\n#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY Flag             */\n#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Mode SPI Mode\n  * @{\n  */\n#define SPI_MODE_SLAVE                  (0x00000000U)\n#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Direction SPI Direction Mode\n  * @{\n  */\n#define SPI_DIRECTION_2LINES            (0x00000000U)\n#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY\n#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Data_Size SPI Data Size\n  * @{\n  */\n#define SPI_DATASIZE_8BIT               (0x00000000U)\n#define SPI_DATASIZE_16BIT              SPI_CR1_DFF\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Clock_Polarity SPI Clock Polarity\n  * @{\n  */\n#define SPI_POLARITY_LOW                (0x00000000U)\n#define SPI_POLARITY_HIGH               SPI_CR1_CPOL\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Clock_Phase SPI Clock Phase\n  * @{\n  */\n#define SPI_PHASE_1EDGE                 (0x00000000U)\n#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Slave_Select_management SPI Slave Select Management\n  * @{\n  */\n#define SPI_NSS_SOFT                    SPI_CR1_SSM\n#define SPI_NSS_HARD_INPUT              (0x00000000U)\n#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)\n/**\n  * @}\n  */\n\n/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler\n  * @{\n  */\n#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)\n#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)\n#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)\n#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)\n#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)\n#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)\n#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)\n#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)\n/**\n  * @}\n  */\n\n/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission\n  * @{\n  */\n#define SPI_FIRSTBIT_MSB                (0x00000000U)\n#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST\n/**\n  * @}\n  */\n\n/** @defgroup SPI_TI_mode SPI TI Mode\n  * @{\n  */\n#define SPI_TIMODE_DISABLE              (0x00000000U)\n#define SPI_TIMODE_ENABLE               SPI_CR2_FRF\n/**\n  * @}\n  */\n\n/** @defgroup SPI_CRC_Calculation SPI CRC Calculation\n  * @{\n  */\n#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)\n#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition\n  * @{\n  */\n#define SPI_IT_TXE                      SPI_CR2_TXEIE\n#define SPI_IT_RXNE                     SPI_CR2_RXNEIE\n#define SPI_IT_ERR                      SPI_CR2_ERRIE\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Flags_definition SPI Flags Definition\n  * @{\n  */\n#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */\n#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */\n#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */\n#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */\n#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */\n#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */\n#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */\n#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\\\n                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macros -----------------------------------------------------------*/\n/** @defgroup SPI_Exported_Macros SPI Exported Macros\n  * @{\n  */\n\n/** @brief  Reset SPI handle state.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \\\n                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \\\n                                                                    (__HANDLE__)->MspInitCallback = NULL;            \\\n                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \\\n                                                                  } while(0)\n#else\n#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n\n/** @brief  Enable the specified SPI interrupts.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __INTERRUPT__ specifies the interrupt source to enable.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *            @arg SPI_IT_ERR: Error interrupt enable\n  * @retval None\n  */\n#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\n\n/** @brief  Disable the specified SPI interrupts.\n  * @param  __HANDLE__ specifies the SPI handle.\n  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __INTERRUPT__ specifies the interrupt source to disable.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *            @arg SPI_IT_ERR: Error interrupt enable\n  * @retval None\n  */\n#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))\n\n/** @brief  Check whether the specified SPI interrupt source is enabled or not.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *            @arg SPI_IT_ERR: Error interrupt enable\n  * @retval The new state of __IT__ (TRUE or FALSE).\n  */\n#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\\\n                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)\n\n/** @brief  Check whether the specified SPI flag is set or not.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\n  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\n  *            @arg SPI_FLAG_CRCERR: CRC error flag\n  *            @arg SPI_FLAG_MODF: Mode fault flag\n  *            @arg SPI_FLAG_OVR: Overrun flag\n  *            @arg SPI_FLAG_BSY: Busy flag\n  *            @arg SPI_FLAG_FRE: Frame format error flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))\n\n/** @brief  Clear the SPI CRCERR pending flag.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))\n\n/** @brief  Clear the SPI MODF pending flag.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \\\n  do{                                                    \\\n    __IO uint32_t tmpreg_modf = 0x00U;                   \\\n    tmpreg_modf = (__HANDLE__)->Instance->SR;            \\\n    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \\\n    UNUSED(tmpreg_modf);                                 \\\n  } while(0U)\n\n/** @brief  Clear the SPI OVR pending flag.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \\\n  do{                                              \\\n    __IO uint32_t tmpreg_ovr = 0x00U;              \\\n    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \\\n    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \\\n    UNUSED(tmpreg_ovr);                            \\\n  } while(0U)\n\n/** @brief  Clear the SPI FRE pending flag.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \\\n  do{                                              \\\n    __IO uint32_t tmpreg_fre = 0x00U;              \\\n    tmpreg_fre = (__HANDLE__)->Instance->SR;       \\\n    UNUSED(tmpreg_fre);                            \\\n  }while(0U)\n\n/** @brief  Enable the SPI peripheral.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\n\n/** @brief  Disable the SPI peripheral.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup SPI_Private_Macros SPI Private Macros\n  * @{\n  */\n\n/** @brief  Set the SPI transmit-only mode.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\n\n/** @brief  Set the SPI receive-only mode.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)\n\n/** @brief  Reset the CRC calculation of the SPI.\n  * @param  __HANDLE__ specifies the SPI Handle.\n  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.\n  * @retval None\n  */\n#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\\\n                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)\n\n/** @brief  Check whether the specified SPI flag is set or not.\n  * @param  __SR__  copy of SPI SR register.\n  * @param  __FLAG__ specifies the flag to check.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag\n  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag\n  *            @arg SPI_FLAG_CRCERR: CRC error flag\n  *            @arg SPI_FLAG_MODF: Mode fault flag\n  *            @arg SPI_FLAG_OVR: Overrun flag\n  *            @arg SPI_FLAG_BSY: Busy flag\n  *            @arg SPI_FLAG_FRE: Frame format error flag\n  * @retval SET or RESET.\n  */\n#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \\\n                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)\n\n/** @brief  Check whether the specified SPI Interrupt is set or not.\n  * @param  __CR2__  copy of SPI CR2 register.\n  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.\n  *         This parameter can be one of the following values:\n  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable\n  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable\n  *            @arg SPI_IT_ERR: Error interrupt enable\n  * @retval SET or RESET.\n  */\n#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \\\n                                                     (__INTERRUPT__)) ? SET : RESET)\n\n/** @brief  Checks if SPI Mode parameter is in allowed range.\n  * @param  __MODE__ specifies the SPI Mode.\n  *         This parameter can be a value of @ref SPI_Mode\n  * @retval None\n  */\n#define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \\\n                                    ((__MODE__) == SPI_MODE_MASTER))\n\n/** @brief  Checks if SPI Direction Mode parameter is in allowed range.\n  * @param  __MODE__ specifies the SPI Direction Mode.\n  *         This parameter can be a value of @ref SPI_Direction\n  * @retval None\n  */\n#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \\\n                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \\\n                                    ((__MODE__) == SPI_DIRECTION_1LINE))\n\n/** @brief  Checks if SPI Direction Mode parameter is 2 lines.\n  * @param  __MODE__ specifies the SPI Direction Mode.\n  * @retval None\n  */\n#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)\n\n/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.\n  * @param  __MODE__ specifies the SPI Direction Mode.\n  * @retval None\n  */\n#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \\\n                                                    ((__MODE__) == SPI_DIRECTION_1LINE))\n\n/** @brief  Checks if SPI Data Size parameter is in allowed range.\n  * @param  __DATASIZE__ specifies the SPI Data Size.\n  *         This parameter can be a value of @ref SPI_Data_Size\n  * @retval None\n  */\n#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \\\n                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT))\n\n/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.\n  * @param  __CPOL__ specifies the SPI serial clock steady state.\n  *         This parameter can be a value of @ref SPI_Clock_Polarity\n  * @retval None\n  */\n#define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \\\n                                    ((__CPOL__) == SPI_POLARITY_HIGH))\n\n/** @brief  Checks if SPI Clock Phase parameter is in allowed range.\n  * @param  __CPHA__ specifies the SPI Clock Phase.\n  *         This parameter can be a value of @ref SPI_Clock_Phase\n  * @retval None\n  */\n#define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \\\n                                    ((__CPHA__) == SPI_PHASE_2EDGE))\n\n/** @brief  Checks if SPI Slave Select parameter is in allowed range.\n  * @param  __NSS__ specifies the SPI Slave Select management parameter.\n  *         This parameter can be a value of @ref SPI_Slave_Select_management\n  * @retval None\n  */\n#define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \\\n                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \\\n                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))\n\n/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.\n  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.\n  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler\n  * @retval None\n  */\n#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \\\n                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))\n\n/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.\n  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).\n  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission\n  * @retval None\n  */\n#define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \\\n                                    ((__BIT__) == SPI_FIRSTBIT_LSB))\n\n/** @brief  Checks if SPI TI mode parameter is in allowed range.\n  * @param  __MODE__ specifies the SPI TI mode.\n  *         This parameter can be a value of @ref SPI_TI_mode\n  * @retval None\n  */\n#define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \\\n                                    ((__MODE__) == SPI_TIMODE_ENABLE))\n\n/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.\n  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.\n  *         This parameter can be a value of @ref SPI_CRC_Calculation\n  * @retval None\n  */\n#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \\\n                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))\n\n/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.\n  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.\n  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535\n  * @retval None\n  */\n#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \\\n                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \\\n                                              (((__POLYNOMIAL__)&0x1U) != 0U))\n\n/** @brief  Checks if DMA handle is valid.\n  * @param  __HANDLE__ specifies a DMA Handle.\n  * @retval None\n  */\n#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)\n\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup SPI_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group1\n  * @{\n  */\n/* Initialization/de-initialization functions  ********************************/\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);\n\n/* Callbacks Register/UnRegister functions  ***********************************/\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\nHAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group2\n  * @{\n  */\n/* I/O operation functions  ***************************************************/\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\n                                          uint32_t Timeout);\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\n                                             uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\n                                              uint16_t Size);\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);\n/* Transfer Abort functions */\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);\n\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);\nvoid HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Exported_Functions_Group3\n  * @{\n  */\n/* Peripheral State and Error functions ***************************************/\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);\nuint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32F4xx_HAL_SPI_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_tim.h\n  * @author  MCD Application Team\n  * @brief   Header file of TIM HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_TIM_H\n#define STM32F4xx_HAL_TIM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup TIM\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup TIM_Exported_Types TIM Exported Types\n  * @{\n  */\n\n/**\n  * @brief  TIM Time base Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\n\n  uint32_t CounterMode;       /*!< Specifies the counter mode.\n                                   This parameter can be a value of @ref TIM_Counter_Mode */\n\n  uint32_t Period;            /*!< Specifies the period value to be loaded into the active\n                                   Auto-Reload Register at the next update event.\n                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */\n\n  uint32_t ClockDivision;     /*!< Specifies the clock division.\n                                   This parameter can be a value of @ref TIM_ClockDivision */\n\n  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter\n                                    reaches zero, an update event is generated and counting restarts\n                                    from the RCR value (N).\n                                    This means in PWM mode that (N+1) corresponds to:\n                                        - the number of PWM periods in edge-aligned mode\n                                        - the number of half PWM period in center-aligned mode\n                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.\n                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */\n\n  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.\n                                   This parameter can be a value of @ref TIM_AutoReloadPreload */\n} TIM_Base_InitTypeDef;\n\n/**\n  * @brief  TIM Output Compare Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\n                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\n\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\n\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\n\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\n                               @note This parameter is valid only for timer instances supporting break feature. */\n\n  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.\n                               This parameter can be a value of @ref TIM_Output_Fast_State\n                               @note This parameter is valid only in PWM1 and PWM2 mode. */\n\n\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\n                               @note This parameter is valid only for timer instances supporting break feature. */\n\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\n                               @note This parameter is valid only for timer instances supporting break feature. */\n} TIM_OC_InitTypeDef;\n\n/**\n  * @brief  TIM One Pulse Mode Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t OCMode;        /*!< Specifies the TIM mode.\n                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */\n\n  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\n                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\n\n  uint32_t OCPolarity;    /*!< Specifies the output polarity.\n                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */\n\n  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity\n                               @note This parameter is valid only for timer instances supporting break feature. */\n\n  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.\n                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State\n                               @note This parameter is valid only for timer instances supporting break feature. */\n\n  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.\n                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State\n                               @note This parameter is valid only for timer instances supporting break feature. */\n\n  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.\n                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */\n\n  uint32_t ICSelection;   /*!< Specifies the input.\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\n\n  uint32_t ICFilter;      /*!< Specifies the input capture filter.\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n} TIM_OnePulse_InitTypeDef;\n\n/**\n  * @brief  TIM Input Capture Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.\n                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */\n\n  uint32_t ICSelection;  /*!< Specifies the input.\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\n\n  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.\n                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\n\n  uint32_t ICFilter;     /*!< Specifies the input capture filter.\n                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n} TIM_IC_InitTypeDef;\n\n/**\n  * @brief  TIM Encoder Configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.\n                               This parameter can be a value of @ref TIM_Encoder_Mode */\n\n  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.\n                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */\n\n  uint32_t IC1Selection;  /*!< Specifies the input.\n                               This parameter can be a value of @ref TIM_Input_Capture_Selection */\n\n  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\n\n  uint32_t IC1Filter;     /*!< Specifies the input capture filter.\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n\n  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.\n                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */\n\n  uint32_t IC2Selection;  /*!< Specifies the input.\n                              This parameter can be a value of @ref TIM_Input_Capture_Selection */\n\n  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.\n                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\n\n  uint32_t IC2Filter;     /*!< Specifies the input capture filter.\n                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n} TIM_Encoder_InitTypeDef;\n\n/**\n  * @brief  Clock Configuration Handle Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClockSource;     /*!< TIM clock sources\n                                 This parameter can be a value of @ref TIM_Clock_Source */\n  uint32_t ClockPolarity;   /*!< TIM clock polarity\n                                 This parameter can be a value of @ref TIM_Clock_Polarity */\n  uint32_t ClockPrescaler;  /*!< TIM clock prescaler\n                                 This parameter can be a value of @ref TIM_Clock_Prescaler */\n  uint32_t ClockFilter;     /*!< TIM clock filter\n                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n} TIM_ClockConfigTypeDef;\n\n/**\n  * @brief  TIM Clear Input Configuration Handle Structure definition\n  */\ntypedef struct\n{\n  uint32_t ClearInputState;      /*!< TIM clear Input state\n                                      This parameter can be ENABLE or DISABLE */\n  uint32_t ClearInputSource;     /*!< TIM clear Input sources\n                                      This parameter can be a value of @ref TIM_ClearInput_Source */\n  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity\n                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */\n  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler\n                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */\n  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter\n                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n} TIM_ClearInputConfigTypeDef;\n\n/**\n  * @brief  TIM Master configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection\n                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */\n  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection\n                                        This parameter can be a value of @ref TIM_Master_Slave_Mode\n                                        @note When the Master/slave mode is enabled, the effect of\n                                        an event on the trigger input (TRGI) is delayed to allow a\n                                        perfect synchronization between the current timer and its\n                                        slaves (through TRGO). It is not mandatory in case of timer\n                                        synchronization mode. */\n} TIM_MasterConfigTypeDef;\n\n/**\n  * @brief  TIM Slave configuration Structure definition\n  */\ntypedef struct\n{\n  uint32_t  SlaveMode;         /*!< Slave mode selection\n                                    This parameter can be a value of @ref TIM_Slave_Mode */\n  uint32_t  InputTrigger;      /*!< Input Trigger source\n                                    This parameter can be a value of @ref TIM_Trigger_Selection */\n  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity\n                                    This parameter can be a value of @ref TIM_Trigger_Polarity */\n  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler\n                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */\n  uint32_t  TriggerFilter;     /*!< Input trigger filter\n                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */\n\n} TIM_SlaveConfigTypeDef;\n\n/**\n  * @brief  TIM Break input(s) and Dead time configuration Structure definition\n  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable\n  *        filter and polarity.\n  */\ntypedef struct\n{\n  uint32_t OffStateRunMode;      /*!< TIM off state in run mode\n                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */\n  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode\n                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */\n  uint32_t LockLevel;            /*!< TIM Lock level\n                                      This parameter can be a value of @ref TIM_Lock_level */\n  uint32_t DeadTime;             /*!< TIM dead Time\n                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */\n  uint32_t BreakState;           /*!< TIM Break State\n                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */\n  uint32_t BreakPolarity;        /*!< TIM Break input polarity\n                                      This parameter can be a value of @ref TIM_Break_Polarity */\n  uint32_t BreakFilter;          /*!< Specifies the break input filter.\n                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state\n                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */\n} TIM_BreakDeadTimeConfigTypeDef;\n\n/**\n  * @brief  HAL State structures definition\n  */\ntypedef enum\n{\n  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */\n  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */\n  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */\n  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */\n  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */\n} HAL_TIM_StateTypeDef;\n\n/**\n  * @brief  TIM Channel States definition\n  */\ntypedef enum\n{\n  HAL_TIM_CHANNEL_STATE_RESET             = 0x00U,    /*!< TIM Channel initial state                         */\n  HAL_TIM_CHANNEL_STATE_READY             = 0x01U,    /*!< TIM Channel ready for use                         */\n  HAL_TIM_CHANNEL_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing on the TIM channel */\n} HAL_TIM_ChannelStateTypeDef;\n\n/**\n  * @brief  DMA Burst States definition\n  */\ntypedef enum\n{\n  HAL_DMA_BURST_STATE_RESET             = 0x00U,    /*!< DMA Burst initial state */\n  HAL_DMA_BURST_STATE_READY             = 0x01U,    /*!< DMA Burst ready for use */\n  HAL_DMA_BURST_STATE_BUSY              = 0x02U,    /*!< Ongoing DMA Burst       */\n} HAL_TIM_DMABurstStateTypeDef;\n\n/**\n  * @brief  HAL Active channel structures definition\n  */\ntypedef enum\n{\n  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */\n  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */\n  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */\n  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */\n  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */\n} HAL_TIM_ActiveChannel;\n\n/**\n  * @brief  TIM Time Base Handle Structure definition\n  */\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\ntypedef struct __TIM_HandleTypeDef\n#else\ntypedef struct\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n{\n  TIM_TypeDef                        *Instance;         /*!< Register base address                             */\n  TIM_Base_InitTypeDef               Init;              /*!< TIM Time Base required parameters                 */\n  HAL_TIM_ActiveChannel              Channel;           /*!< Active channel                                    */\n  DMA_HandleTypeDef                  *hdma[7];          /*!< DMA Handlers array\n                                                             This array is accessed by a @ref DMA_Handle_index */\n  HAL_LockTypeDef                    Lock;              /*!< Locking object                                    */\n  __IO HAL_TIM_StateTypeDef          State;             /*!< TIM operation state                               */\n  __IO HAL_TIM_ChannelStateTypeDef   ChannelState[4];   /*!< TIM channel operation state                       */\n  __IO HAL_TIM_ChannelStateTypeDef   ChannelNState[4];  /*!< TIM complementary channel operation state         */\n  __IO HAL_TIM_DMABurstStateTypeDef  DMABurstState;     /*!< DMA burst operation state                         */\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */\n  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */\n  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */\n  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */\n  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */\n  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */\n  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */\n  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */\n  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */\n  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */\n  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */\n  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */\n  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */\n  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */\n  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */\n  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */\n  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */\n  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */\n  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */\n  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */\n  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */\n  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */\n  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */\n  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */\n  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */\n  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */\n  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n} TIM_HandleTypeDef;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  HAL TIM Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_TIM_BASE_MSPINIT_CB_ID              = 0x00U   /*!< TIM Base MspInit Callback ID                              */\n  , HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U   /*!< TIM Base MspDeInit Callback ID                            */\n  , HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U   /*!< TIM IC MspInit Callback ID                                */\n  , HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U   /*!< TIM IC MspDeInit Callback ID                              */\n  , HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U   /*!< TIM OC MspInit Callback ID                                */\n  , HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U   /*!< TIM OC MspDeInit Callback ID                              */\n  , HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U   /*!< TIM PWM MspInit Callback ID                               */\n  , HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U   /*!< TIM PWM MspDeInit Callback ID                             */\n  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U   /*!< TIM One Pulse MspInit Callback ID                         */\n  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U   /*!< TIM One Pulse MspDeInit Callback ID                       */\n  , HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU   /*!< TIM Encoder MspInit Callback ID                           */\n  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU   /*!< TIM Encoder MspDeInit Callback ID                         */\n  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */\n  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU   /*!< TIM Hall Sensor MspDeInit Callback ID                     */\n  , HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU   /*!< TIM Period Elapsed Callback ID                             */\n  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU   /*!< TIM Period Elapsed half complete Callback ID               */\n  , HAL_TIM_TRIGGER_CB_ID                 = 0x10U   /*!< TIM Trigger Callback ID                                    */\n  , HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U   /*!< TIM Trigger half complete Callback ID                      */\n\n  , HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U   /*!< TIM Input Capture Callback ID                              */\n  , HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U   /*!< TIM Input Capture half complete Callback ID                */\n  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U   /*!< TIM Output Compare Delay Elapsed Callback ID               */\n  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U   /*!< TIM PWM Pulse Finished Callback ID           */\n  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U   /*!< TIM PWM Pulse Finished half complete Callback ID           */\n  , HAL_TIM_ERROR_CB_ID                   = 0x17U   /*!< TIM Error Callback ID                                      */\n  , HAL_TIM_COMMUTATION_CB_ID             = 0x18U   /*!< TIM Commutation Callback ID                                */\n  , HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U   /*!< TIM Commutation half complete Callback ID                  */\n  , HAL_TIM_BREAK_CB_ID                   = 0x1AU   /*!< TIM Break Callback ID                                      */\n} HAL_TIM_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL TIM Callback pointer definition\n  */\ntypedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */\n\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n/* End of exported types -----------------------------------------------------*/\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup TIM_Exported_Constants TIM Exported Constants\n  * @{\n  */\n\n/** @defgroup TIM_ClearInput_Source TIM Clear Input Source\n  * @{\n  */\n#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */\n#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_DMA_Base_address TIM DMA Base Address\n  * @{\n  */\n#define TIM_DMABASE_CR1                    0x00000000U\n#define TIM_DMABASE_CR2                    0x00000001U\n#define TIM_DMABASE_SMCR                   0x00000002U\n#define TIM_DMABASE_DIER                   0x00000003U\n#define TIM_DMABASE_SR                     0x00000004U\n#define TIM_DMABASE_EGR                    0x00000005U\n#define TIM_DMABASE_CCMR1                  0x00000006U\n#define TIM_DMABASE_CCMR2                  0x00000007U\n#define TIM_DMABASE_CCER                   0x00000008U\n#define TIM_DMABASE_CNT                    0x00000009U\n#define TIM_DMABASE_PSC                    0x0000000AU\n#define TIM_DMABASE_ARR                    0x0000000BU\n#define TIM_DMABASE_RCR                    0x0000000CU\n#define TIM_DMABASE_CCR1                   0x0000000DU\n#define TIM_DMABASE_CCR2                   0x0000000EU\n#define TIM_DMABASE_CCR3                   0x0000000FU\n#define TIM_DMABASE_CCR4                   0x00000010U\n#define TIM_DMABASE_BDTR                   0x00000011U\n#define TIM_DMABASE_DCR                    0x00000012U\n#define TIM_DMABASE_DMAR                   0x00000013U\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Event_Source TIM Event Source\n  * @{\n  */\n#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */\n#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */\n#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */\n#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */\n#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */\n#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */\n#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */\n#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity\n  * @{\n  */\n#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */\n#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */\n#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_ETR_Polarity TIM ETR Polarity\n  * @{\n  */\n#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */\n#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler\n  * @{\n  */\n#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */\n#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */\n#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */\n#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Counter_Mode TIM Counter Mode\n  * @{\n  */\n#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */\n#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */\n#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */\n#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */\n#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_ClockDivision TIM Clock Division\n  * @{\n  */\n#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */\n#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */\n#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_State TIM Output Compare State\n  * @{\n  */\n#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */\n#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload\n  * @{\n  */\n#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */\n#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Fast_State TIM Output Fast State\n  * @{\n  */\n#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */\n#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State\n  * @{\n  */\n#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */\n#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity\n  * @{\n  */\n#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */\n#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity\n  * @{\n  */\n#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */\n#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State\n  * @{\n  */\n#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */\n#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State\n  * @{\n  */\n#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */\n#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity\n  * @{\n  */\n#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */\n#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */\n#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity\n  * @{\n  */\n#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */\n#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection\n  * @{\n  */\n#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\n                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */\n#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be\n                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */\n#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler\n  * @{\n  */\n#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */\n#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */\n#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */\n#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode\n  * @{\n  */\n#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */\n#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Encoder_Mode TIM Encoder Mode\n  * @{\n  */\n#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */\n#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */\n#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Interrupt_definition TIM interrupt Definition\n  * @{\n  */\n#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */\n#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */\n#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */\n#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */\n#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */\n#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */\n#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */\n#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Commutation_Source  TIM Commutation Source\n  * @{\n  */\n#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */\n#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_DMA_sources TIM DMA Sources\n  * @{\n  */\n#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */\n#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */\n#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */\n#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */\n#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */\n#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */\n#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Flag_definition TIM Flag Definition\n  * @{\n  */\n#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */\n#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */\n#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */\n#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */\n#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */\n#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */\n#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */\n#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */\n#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */\n#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */\n#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */\n#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Channel TIM Channel\n  * @{\n  */\n#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */\n#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */\n#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */\n#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */\n#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Clock_Source TIM Clock Source\n  * @{\n  */\n#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */\n#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */\n#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */\n#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */\n#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */\n#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */\n#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */\n#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */\n#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */\n#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Clock_Polarity TIM Clock Polarity\n  * @{\n  */\n#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */\n#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */\n#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */\n#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */\n#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler\n  * @{\n  */\n#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */\n#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */\n#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */\n#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity\n  * @{\n  */\n#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */\n#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler\n  * @{\n  */\n#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */\n#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */\n#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */\n#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state\n  * @{\n  */\n#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\n#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state\n  * @{\n  */\n#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */\n#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */\n/**\n  * @}\n  */\n/** @defgroup TIM_Lock_level  TIM Lock level\n  * @{\n  */\n#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */\n#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */\n#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */\n#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable\n  * @{\n  */\n#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */\n#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Break_Polarity TIM Break Input Polarity\n  * @{\n  */\n#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */\n#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable\n  * @{\n  */\n#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */\n#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event\n                                                                                    (if none of the break inputs BRK and BRK2 is active) */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection\n  * @{\n  */\n#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */\n#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */\n#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */\n#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */\n#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */\n#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */\n#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */\n#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode\n  * @{\n  */\n#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */\n#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Slave_Mode TIM Slave mode\n  * @{\n  */\n#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */\n#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */\n#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */\n#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */\n#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes\n  * @{\n  */\n#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */\n#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */\n#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */\n#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */\n#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */\n#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */\n#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */\n#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Trigger_Selection TIM Trigger Selection\n  * @{\n  */\n#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */\n#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */\n#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */\n#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */\n#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */\n#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */\n#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */\n#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */\n#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity\n  * @{\n  */\n#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */\n#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */\n#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */\n#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */\n#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler\n  * @{\n  */\n#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */\n#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */\n#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */\n#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection\n  * @{\n  */\n#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */\n#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */\n/**\n  * @}\n  */\n\n/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length\n  * @{\n  */\n#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA   */\n#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA  */\n#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */\n/**\n  * @}\n  */\n\n/** @defgroup DMA_Handle_index TIM DMA Handle Index\n  * @{\n  */\n#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */\n#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */\n#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */\n#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */\n#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */\n#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */\n#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */\n/**\n  * @}\n  */\n\n/** @defgroup Channel_CC_State TIM Capture/Compare Channel State\n  * @{\n  */\n#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */\n#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */\n#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */\n#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* End of exported constants -------------------------------------------------*/\n\n/* Exported macros -----------------------------------------------------------*/\n/** @defgroup TIM_Exported_Macros TIM Exported Macros\n  * @{\n  */\n\n/** @brief  Reset TIM handle state.\n  * @param  __HANDLE__ TIM handle.\n  * @retval None\n  */\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \\\n                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \\\n                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \\\n                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;            \\\n                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;            \\\n                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;            \\\n                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;            \\\n                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;            \\\n                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;            \\\n                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;            \\\n                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;            \\\n                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;            \\\n                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;            \\\n                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;            \\\n                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;            \\\n                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;            \\\n                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;            \\\n                                                     } while(0)\n#else\n#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                               \\\n                                                      (__HANDLE__)->State            = HAL_TIM_STATE_RESET;         \\\n                                                      (__HANDLE__)->ChannelState[0]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[1]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[2]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelState[3]  = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \\\n                                                      (__HANDLE__)->DMABurstState    = HAL_DMA_BURST_STATE_RESET;   \\\n                                                     } while(0)\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @brief  Enable the TIM peripheral.\n  * @param  __HANDLE__ TIM handle\n  * @retval None\n  */\n#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))\n\n/**\n  * @brief  Enable the TIM main Output.\n  * @param  __HANDLE__ TIM handle\n  * @retval None\n  */\n#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))\n\n/**\n  * @brief  Disable the TIM peripheral.\n  * @param  __HANDLE__ TIM handle\n  * @retval None\n  */\n#define __HAL_TIM_DISABLE(__HANDLE__) \\\n  do { \\\n    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\\n    { \\\n      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\\n      { \\\n        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \\\n      } \\\n    } \\\n  } while(0)\n\n/**\n  * @brief  Disable the TIM main Output.\n  * @param  __HANDLE__ TIM handle\n  * @retval None\n  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled\n  */\n#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \\\n  do { \\\n    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \\\n    { \\\n      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \\\n      { \\\n        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \\\n      } \\\n    } \\\n  } while(0)\n\n/**\n  * @brief  Disable the TIM main Output.\n  * @param  __HANDLE__ TIM handle\n  * @retval None\n  * @note The Main Output Enable of a timer instance is disabled unconditionally\n  */\n#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)\n\n/** @brief  Enable the specified TIM interrupt.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_IT_UPDATE: Update interrupt\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\n  *            @arg TIM_IT_COM:   Commutation interrupt\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\n  *            @arg TIM_IT_BREAK: Break interrupt\n  * @retval None\n  */\n#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))\n\n/** @brief  Disable the specified TIM interrupt.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_IT_UPDATE: Update interrupt\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\n  *            @arg TIM_IT_COM:   Commutation interrupt\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\n  *            @arg TIM_IT_BREAK: Break interrupt\n  * @retval None\n  */\n#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))\n\n/** @brief  Enable the specified DMA request.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __DMA__ specifies the TIM DMA request to enable.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: Update DMA request\n  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\n  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\n  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\n  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\n  *            @arg TIM_DMA_COM:   Commutation DMA request\n  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\n  * @retval None\n  */\n#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))\n\n/** @brief  Disable the specified DMA request.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __DMA__ specifies the TIM DMA request to disable.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: Update DMA request\n  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request\n  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request\n  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request\n  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request\n  *            @arg TIM_DMA_COM:   Commutation DMA request\n  *            @arg TIM_DMA_TRIGGER: Trigger DMA request\n  * @retval None\n  */\n#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))\n\n/** @brief  Check whether the specified TIM interrupt flag is set or not.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __FLAG__ specifies the TIM interrupt flag to check.\n  *        This parameter can be one of the following values:\n  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\n  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\n  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\n  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\n  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\n  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\n  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\n  *            @arg TIM_FLAG_BREAK: Break interrupt flag\n  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\n  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\n  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\n  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))\n\n/** @brief  Clear the specified TIM interrupt flag.\n  * @param  __HANDLE__ specifies the TIM Handle.\n  * @param  __FLAG__ specifies the TIM interrupt flag to clear.\n  *        This parameter can be one of the following values:\n  *            @arg TIM_FLAG_UPDATE: Update interrupt flag\n  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag\n  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag\n  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag\n  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag\n  *            @arg TIM_FLAG_COM:  Commutation interrupt flag\n  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag\n  *            @arg TIM_FLAG_BREAK: Break interrupt flag\n  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag\n  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag\n  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag\n  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))\n\n/**\n  * @brief  Check whether the specified TIM interrupt source is enabled or not.\n  * @param  __HANDLE__ TIM handle\n  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_IT_UPDATE: Update interrupt\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\n  *            @arg TIM_IT_COM:   Commutation interrupt\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\n  *            @arg TIM_IT_BREAK: Break interrupt\n  * @retval The state of TIM_IT (SET or RESET).\n  */\n#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \\\n                                                             == (__INTERRUPT__)) ? SET : RESET)\n\n/** @brief Clear the TIM interrupt pending bits.\n  * @param  __HANDLE__ TIM handle\n  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_IT_UPDATE: Update interrupt\n  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt\n  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt\n  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt\n  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt\n  *            @arg TIM_IT_COM:   Commutation interrupt\n  *            @arg TIM_IT_TRIGGER: Trigger interrupt\n  *            @arg TIM_IT_BREAK: Break interrupt\n  * @retval None\n  */\n#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))\n\n/**\n  * @brief  Indicates whether or not the TIM Counter is used as downcounter.\n  * @param  __HANDLE__ TIM handle.\n  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)\n  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder\nmode.\n  */\n#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))\n\n/**\n  * @brief  Set the TIM Prescaler on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __PRESC__ specifies the Prescaler new value.\n  * @retval None\n  */\n#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))\n\n/**\n  * @brief  Set the TIM Counter Register value on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __COUNTER__ specifies the Counter register new value.\n  * @retval None\n  */\n#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))\n\n/**\n  * @brief  Get the TIM Counter Register value on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)\n  */\n#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)\n\n/**\n  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __AUTORELOAD__ specifies the Counter register new value.\n  * @retval None\n  */\n#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \\\n  do{                                                    \\\n    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \\\n    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \\\n  } while(0)\n\n/**\n  * @brief  Get the TIM Autoreload Register value on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)\n  */\n#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)\n\n/**\n  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CKD__ specifies the clock division value.\n  *          This parameter can be one of the following value:\n  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\n  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\n  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\n  * @retval None\n  */\n#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \\\n  do{                                                   \\\n    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \\\n    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \\\n    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \\\n  } while(0)\n\n/**\n  * @brief  Get the TIM Clock Division value on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @retval The clock division can be one of the following values:\n  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT\n  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT\n  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT\n  */\n#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)\n\n/**\n  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPSC_DIV1: no prescaler\n  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\n  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\n  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\n  * @retval None\n  */\n#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \\\n  do{                                                    \\\n    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \\\n    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \\\n  } while(0)\n\n/**\n  * @brief  Get the TIM Input Capture prescaler on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value\n  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value\n  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value\n  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value\n  * @retval The input capture prescaler can be one of the following values:\n  *            @arg TIM_ICPSC_DIV1: no prescaler\n  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events\n  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events\n  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events\n  */\n#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\\\n   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)\n\n/**\n  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  __COMPARE__ specifies the Capture Compare register new value.\n  * @retval None\n  */\n#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\\\n   ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))\n\n/**\n  * @brief  Get the TIM Capture Compare Register value on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channel associated with the capture compare register\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value\n  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value\n  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value\n  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value\n  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)\n  */\n#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\\\n   ((__HANDLE__)->Instance->CCR4))\n\n/**\n  * @brief  Set the TIM Output compare preload.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval None\n  */\n#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\\\n   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))\n\n/**\n  * @brief  Reset the TIM Output compare preload.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval None\n  */\n#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\\\n   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))\n\n/**\n  * @brief  Enable fast mode for a given channel.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @note  When fast mode is enabled an active edge on the trigger input acts\n  *        like a compare match on CCx output. Delay to sample the trigger\n  *        input and to activate CCx output is reduced to 3 clock cycles.\n  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.\n  * @retval None\n  */\n#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\\\n   ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))\n\n/**\n  * @brief  Disable fast mode for a given channel.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @note  When fast mode is disabled CCx output behaves normally depending\n  *        on counter and CCRx values even when the trigger is ON. The minimum\n  *        delay to activate CCx output when an active edge occurs on the\n  *        trigger input is 5 clock cycles.\n  * @retval None\n  */\n#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\\\n   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))\n\n/**\n  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.\n  * @param  __HANDLE__ TIM handle.\n  * @note  When the URS bit of the TIMx_CR1 register is set, only counter\n  *        overflow/underflow generates an update interrupt or DMA request (if\n  *        enabled)\n  * @retval None\n  */\n#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)\n\n/**\n  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.\n  * @param  __HANDLE__ TIM handle.\n  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the\n  *        following events generate an update interrupt or DMA request (if\n  *        enabled):\n  *           _ Counter overflow underflow\n  *           _ Setting the UG bit\n  *           _ Update generation through the slave mode controller\n  * @retval None\n  */\n#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)\n\n/**\n  * @brief  Set the TIM Capture x input polarity on runtime.\n  * @param  __HANDLE__ TIM handle.\n  * @param  __CHANNEL__ TIM Channels to be configured.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  __POLARITY__ Polarity for TIx source\n  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge\n  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge\n  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge\n  * @retval None\n  */\n#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \\\n  do{                                                                     \\\n    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \\\n    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \\\n  }while(0)\n\n/**\n  * @}\n  */\n/* End of exported macros ----------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup TIM_Private_Constants TIM Private Constants\n  * @{\n  */\n/* The counter of a timer instance is disabled only if all the CCx and CCxN\n   channels have been disabled */\n#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))\n#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))\n/**\n  * @}\n  */\n/* End of private constants --------------------------------------------------*/\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup TIM_Private_Macros TIM Private Macros\n  * @{\n  */\n#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \\\n                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))\n\n#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \\\n                                   ((__BASE__) == TIM_DMABASE_CR2)   || \\\n                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \\\n                                   ((__BASE__) == TIM_DMABASE_DIER)  || \\\n                                   ((__BASE__) == TIM_DMABASE_SR)    || \\\n                                   ((__BASE__) == TIM_DMABASE_EGR)   || \\\n                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \\\n                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \\\n                                   ((__BASE__) == TIM_DMABASE_CCER)  || \\\n                                   ((__BASE__) == TIM_DMABASE_CNT)   || \\\n                                   ((__BASE__) == TIM_DMABASE_PSC)   || \\\n                                   ((__BASE__) == TIM_DMABASE_ARR)   || \\\n                                   ((__BASE__) == TIM_DMABASE_RCR)   || \\\n                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \\\n                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \\\n                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \\\n                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \\\n                                   ((__BASE__) == TIM_DMABASE_BDTR))\n\n#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\n\n#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \\\n                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \\\n                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \\\n                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \\\n                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))\n\n#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \\\n                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \\\n                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))\n\n#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \\\n                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))\n\n#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \\\n                                            ((__STATE__) == TIM_OCFAST_ENABLE))\n\n#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \\\n                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))\n\n#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \\\n                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))\n\n#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \\\n                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))\n\n#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \\\n                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))\n\n#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \\\n                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))\n\n#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \\\n                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \\\n                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))\n\n#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \\\n                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \\\n                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))\n\n#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \\\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \\\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \\\n                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))\n\n#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \\\n                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))\n\n#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \\\n                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \\\n                                            ((__MODE__) == TIM_ENCODERMODE_TI12))\n\n#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))\n\n#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \\\n                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \\\n                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \\\n                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \\\n                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))\n\n#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \\\n                                            ((__CHANNEL__) == TIM_CHANNEL_2))\n\n#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \\\n                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \\\n                                                    ((__CHANNEL__) == TIM_CHANNEL_3))\n\n#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \\\n                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))\n\n#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \\\n                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \\\n                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \\\n                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \\\n                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))\n\n#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \\\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \\\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \\\n                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))\n\n#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)\n\n#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \\\n                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))\n\n#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \\\n                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \\\n                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \\\n                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))\n\n#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\n\n#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \\\n                                            ((__STATE__) == TIM_OSSR_DISABLE))\n\n#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \\\n                                            ((__STATE__) == TIM_OSSI_DISABLE))\n\n#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \\\n                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \\\n                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \\\n                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))\n\n#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)\n\n\n#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \\\n                                            ((__STATE__) == TIM_BREAK_DISABLE))\n\n#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \\\n                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))\n\n#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \\\n                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))\n\n#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \\\n                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \\\n                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \\\n                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \\\n                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \\\n                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \\\n                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \\\n                                        ((__SOURCE__) == TIM_TRGO_OC4REF))\n\n#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \\\n                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))\n\n#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \\\n                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \\\n                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \\\n                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \\\n                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))\n\n#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \\\n                                   ((__MODE__) == TIM_OCMODE_PWM2))\n\n#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \\\n                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \\\n                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \\\n                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \\\n                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \\\n                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))\n\n#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\n                                                 ((__SELECTION__) == TIM_TS_ITR1) || \\\n                                                 ((__SELECTION__) == TIM_TS_ITR2) || \\\n                                                 ((__SELECTION__) == TIM_TS_ITR3) || \\\n                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \\\n                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \\\n                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \\\n                                                 ((__SELECTION__) == TIM_TS_ETRF))\n\n#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \\\n                                                               ((__SELECTION__) == TIM_TS_ITR1) || \\\n                                                               ((__SELECTION__) == TIM_TS_ITR2) || \\\n                                                               ((__SELECTION__) == TIM_TS_ITR3) || \\\n                                                               ((__SELECTION__) == TIM_TS_NONE))\n\n#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \\\n                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \\\n                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \\\n                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \\\n                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))\n\n#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \\\n                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \\\n                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \\\n                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))\n\n#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)\n\n#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \\\n                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))\n\n#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER)   || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS)  || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \\\n                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))\n\n#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))\n\n#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)\n\n#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)\n\n#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)\n\n#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\\\n   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))\n\n#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\\\n   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))\n\n#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\\\n   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))\n\n#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\\\n   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))\n\n#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\\\n   (__HANDLE__)->ChannelState[3])\n\n#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\\\n   ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))\n\n#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \\\n  (__HANDLE__)->ChannelState[0]  = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelState[1]  = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelState[2]  = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelState[3]  = (__CHANNEL_STATE__);  \\\n } while(0)\n\n#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\\\n   (__HANDLE__)->ChannelNState[3])\n\n#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \\\n  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\\\n   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\\\n   ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))\n\n#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__,  __CHANNEL_STATE__) do { \\\n  (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__);  \\\n  (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__);  \\\n } while(0)\n\n/**\n  * @}\n  */\n/* End of private macros -----------------------------------------------------*/\n\n/* Include TIM HAL Extended module */\n#include \"stm32f4xx_hal_tim_ex.h\"\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup TIM_Exported_Functions TIM Exported Functions\n  * @{\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions\n  *  @brief   Time Base functions\n  * @{\n  */\n/* Time Base functions ********************************************************/\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions\n  *  @brief   TIM Output Compare functions\n  * @{\n  */\n/* Timer Output Compare functions *********************************************/\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions\n  *  @brief   TIM PWM functions\n  * @{\n  */\n/* Timer PWM functions ********************************************************/\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions\n  *  @brief   TIM Input Capture functions\n  * @{\n  */\n/* Timer Input Capture functions **********************************************/\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions\n  *  @brief   TIM One Pulse functions\n  * @{\n  */\n/* Timer One Pulse functions **************************************************/\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions\n  *  @brief   TIM Encoder functions\n  * @{\n  */\n/* Timer Encoder functions ****************************************************/\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\n                                            uint32_t *pData2, uint16_t Length);\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management\n  *  @brief   IRQ handler management\n  * @{\n  */\n/* Interrupt Handler functions  ***********************************************/\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\n  *  @brief   Peripheral Control functions\n  * @{\n  */\n/* Control functions  *********************************************************/\nHAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,\n                                                 uint32_t OutputChannel,  uint32_t InputChannel);\nHAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,\n                                           uint32_t Channel);\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\nHAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,\n                                                   uint32_t DataLength);\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);\nHAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,\n                                                  uint32_t  DataLength);\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\n  *  @brief   TIM Callbacks functions\n  * @{\n  */\n/* Callback in non blocking modes (Interrupt and DMA) *************************/\nvoid HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);\n\n/* Callbacks Register/UnRegister functions  ***********************************/\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\nHAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\n                                           pTIM_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\n  *  @brief  Peripheral State functions\n  * @{\n  */\n/* Peripheral State functions  ************************************************/\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);\n\n/* Peripheral Channel state functions  ************************************************/\nHAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);\nHAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel);\nHAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* End of exported functions -------------------------------------------------*/\n\n/* Private functions----------------------------------------------------------*/\n/** @defgroup TIM_Private_Functions TIM Private Functions\n  * @{\n  */\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\nvoid TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\n                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);\n\nvoid TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);\nvoid TIM_DMAError(DMA_HandleTypeDef *hdma);\nvoid TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);\nvoid TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);\nvoid TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\nvoid TIM_ResetCallback(TIM_HandleTypeDef *htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n/* End of private functions --------------------------------------------------*/\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* STM32F4xx_HAL_TIM_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_tim_ex.h\n  * @author  MCD Application Team\n  * @brief   Header file of TIM HAL Extended module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_HAL_TIM_EX_H\n#define STM32F4xx_HAL_TIM_EX_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup TIMEx\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types\n  * @{\n  */\n\n/**\n  * @brief  TIM Hall sensor Configuration Structure definition\n  */\n\ntypedef struct\n{\n  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.\n                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */\n\n  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.\n                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */\n\n  uint32_t IC1Filter;           /*!< Specifies the input capture filter.\n                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */\n\n  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.\n                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */\n} TIM_HallSensor_InitTypeDef;\n/**\n  * @}\n  */\n/* End of exported types -----------------------------------------------------*/\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants\n  * @{\n  */\n\n/** @defgroup TIMEx_Remap TIM Extended Remapping\n  * @{\n  */\n#if defined (TIM2)\n#if defined(TIM8)\n#define TIM_TIM2_TIM8_TRGO                     0x00000000U                              /*!< TIM2 ITR1 is connected to TIM8 TRGO */\n#else\n#define TIM_TIM2_ETH_PTP                       TIM_OR_ITR1_RMP_0                        /*!< TIM2 ITR1 is connected to PTP trigger output */\n#endif /*  TIM8 */\n#define TIM_TIM2_USBFS_SOF                     TIM_OR_ITR1_RMP_1                        /*!< TIM2 ITR1 is connected to OTG FS SOF */\n#define TIM_TIM2_USBHS_SOF                     (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0)  /*!< TIM2 ITR1 is connected to OTG HS SOF */\n#endif /* TIM2 */\n\n#define TIM_TIM5_GPIO                          0x00000000U                              /*!< TIM5 TI4 is connected to GPIO */\n#define TIM_TIM5_LSI                           TIM_OR_TI4_RMP_0                         /*!< TIM5 TI4 is connected to LSI */\n#define TIM_TIM5_LSE                           TIM_OR_TI4_RMP_1                         /*!< TIM5 TI4 is connected to LSE */\n#define TIM_TIM5_RTC                           (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0)    /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */\n\n#define TIM_TIM11_GPIO                         0x00000000U                              /*!< TIM11 TI1 is connected to GPIO */\n#define TIM_TIM11_HSE                          TIM_OR_TI1_RMP_1                         /*!< TIM11 TI1 is connected to HSE_RTC clock */\n#if defined(SPDIFRX)\n#define TIM_TIM11_SPDIFRX                      TIM_OR_TI1_RMP_0                         /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */\n#endif /* SPDIFRX*/\n\n#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)\n#define LPTIM_REMAP_MASK                       0x10000000U\n\n#define TIM_TIM9_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM9 ITR1 is connected to TIM3 TRGO */\n#define TIM_TIM9_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP)  /*!< TIM9 ITR1 is connected to LPTIM1 output */\n\n#define TIM_TIM5_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM5 ITR1 is connected to TIM3 TRGO */\n#define TIM_TIM5_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP)  /*!< TIM5 ITR1 is connected to LPTIM1 output */\n\n#define TIM_TIM1_TIM3_TRGO                     LPTIM_REMAP_MASK                             /*!< TIM1 ITR2 is connected to TIM3 TRGO */\n#define TIM_TIM1_LPTIM                         (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP)  /*!< TIM1 ITR2 is connected to LPTIM1 output */\n#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* End of exported constants -------------------------------------------------*/\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n/* End of exported macro -----------------------------------------------------*/\n\n/* Private macro -------------------------------------------------------------*/\n/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros\n  * @{\n  */\n#if defined(SPDIFRX)\n#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \\\n  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \\\n   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \\\n   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \\\n                              ((TIM_REMAP) == TIM_TIM11_SPDIFRX)       || \\\n                              ((TIM_REMAP) == TIM_TIM11_HSE))))\n#elif defined(TIM2)\n#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP)\n#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \\\n  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \\\n   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \\\n   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \\\n                              ((TIM_REMAP) == TIM_TIM11_HSE)))         || \\\n   (((INSTANCE) == TIM1)  && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM1_LPTIM)))        || \\\n   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM5_LPTIM)))        || \\\n   (((INSTANCE) == TIM9)  && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM9_LPTIM))))\n#elif defined(TIM8)\n#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \\\n  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \\\n   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \\\n   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \\\n                              ((TIM_REMAP) == TIM_TIM11_HSE))))\n#else\n#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \\\n  ((((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ETH_PTP)        || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBFS_SOF)      || \\\n                              ((TIM_REMAP) == TIM_TIM2_USBHS_SOF)))    || \\\n   (((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \\\n   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \\\n                              ((TIM_REMAP) == TIM_TIM11_HSE))))\n#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */\n#else\n#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)                                 \\\n  ((((INSTANCE) == TIM5)  && (((TIM_REMAP) == TIM_TIM5_GPIO)           || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSI)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_LSE)            || \\\n                              ((TIM_REMAP) == TIM_TIM5_RTC)))          || \\\n   (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO)          || \\\n                              ((TIM_REMAP) == TIM_TIM11_HSE))))\n#endif /* SPDIFRX */\n\n/**\n  * @}\n  */\n/* End of private macro ------------------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions\n  * @{\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\n  *  @brief    Timer Hall Sensor functions\n  * @{\n  */\n/*  Timer Hall Sensor functions  **********************************************/\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);\n\nvoid HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);\nvoid HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);\n\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\n  *  @brief   Timer Complementary Output Compare functions\n  * @{\n  */\n/*  Timer Complementary Output Compare functions  *****************************/\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\n  *  @brief    Timer Complementary PWM functions\n  * @{\n  */\n/*  Timer Complementary PWM functions  ****************************************/\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);\n\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);\n/* Non-Blocking mode: DMA */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\n  *  @brief    Timer Complementary One Pulse functions\n  * @{\n  */\n/*  Timer Complementary One Pulse functions  **********************************/\n/* Blocking mode: Polling */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\n\n/* Non-Blocking mode: Interrupt */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\n  *  @brief    Peripheral Control functions\n  * @{\n  */\n/* Extended Control functions  ************************************************/\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                              uint32_t  CommutationSource);\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                                 uint32_t  CommutationSource);\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                                  uint32_t  CommutationSource);\nHAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\n                                                        TIM_MasterConfigTypeDef *sMasterConfig);\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\n                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);\nHAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\n  * @brief    Extended Callbacks functions\n  * @{\n  */\n/* Extended Callback **********************************************************/\nvoid HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);\nvoid HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);\n/**\n  * @}\n  */\n\n/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\n  * @brief    Extended Peripheral State functions\n  * @{\n  */\n/* Extended Peripheral State functions  ***************************************/\nHAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);\nHAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* End of exported functions -------------------------------------------------*/\n\n/* Private functions----------------------------------------------------------*/\n/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions\n  * @{\n  */\nvoid TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);\nvoid TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);\n/**\n  * @}\n  */\n/* End of private functions --------------------------------------------------*/\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* STM32F4xx_HAL_TIM_EX_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_uart.h\n  * @author  MCD Application Team\n  * @brief   Header file of UART HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_HAL_UART_H\n#define __STM32F4xx_HAL_UART_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup UART\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n/** @defgroup UART_Exported_Types UART Exported Types\n  * @{\n  */\n\n/**\n  * @brief UART Init Structure definition\n  */\ntypedef struct\n{\n  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.\n                                           The baud rate is computed using the following formula:\n                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))\n                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5\n                                           Where OVR8 is the \"oversampling by 8 mode\" configuration bit in the CR1 register. */\n\n  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.\n                                           This parameter can be a value of @ref UART_Word_Length */\n\n  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.\n                                           This parameter can be a value of @ref UART_Stop_Bits */\n\n  uint32_t Parity;                    /*!< Specifies the parity mode.\n                                           This parameter can be a value of @ref UART_Parity\n                                           @note When parity is enabled, the computed parity is inserted\n                                                 at the MSB position of the transmitted data (9th bit when\n                                                 the word length is set to 9 data bits; 8th bit when the\n                                                 word length is set to 8 data bits). */\n\n  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.\n                                           This parameter can be a value of @ref UART_Mode */\n\n  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.\n                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */\n\n  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).\n                                           This parameter can be a value of @ref UART_Over_Sampling */\n} UART_InitTypeDef;\n\n/**\n  * @brief HAL UART State structures definition\n  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.\n  *        - gState contains UART state information related to global Handle management\n  *          and also information related to Tx operations.\n  *          gState value coding follow below described bitmap :\n  *          b7-b6  Error information\n  *             00 : No Error\n  *             01 : (Not Used)\n  *             10 : Timeout\n  *             11 : Error\n  *          b5     Peripheral initialization status\n  *             0  : Reset (Peripheral not initialized)\n  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)\n  *          b4-b3  (not used)\n  *             xx : Should be set to 00\n  *          b2     Intrinsic process state\n  *             0  : Ready\n  *             1  : Busy (Peripheral busy with some configuration or internal operations)\n  *          b1     (not used)\n  *             x  : Should be set to 0\n  *          b0     Tx state\n  *             0  : Ready (no Tx operation ongoing)\n  *             1  : Busy (Tx operation ongoing)\n  *        - RxState contains information related to Rx operations.\n  *          RxState value coding follow below described bitmap :\n  *          b7-b6  (not used)\n  *             xx : Should be set to 00\n  *          b5     Peripheral initialization status\n  *             0  : Reset (Peripheral not initialized)\n  *             1  : Init done (Peripheral initialized)\n  *          b4-b2  (not used)\n  *            xxx : Should be set to 000\n  *          b1     Rx state\n  *             0  : Ready (no Rx operation ongoing)\n  *             1  : Busy (Rx operation ongoing)\n  *          b0     (not used)\n  *             x  : Should be set to 0.\n  */\ntypedef enum\n{\n  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized\n                                                   Value is allowed for gState and RxState */\n  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use\n                                                   Value is allowed for gState and RxState */\n  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing\n                                                   Value is allowed for gState only */\n  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing\n                                                   Value is allowed for gState only */\n  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing\n                                                   Value is allowed for RxState only */\n  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing\n                                                   Not to be used for neither gState nor RxState.\n                                                   Value is result of combination (Or) between gState and RxState values */\n  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state\n                                                   Value is allowed for gState only */\n  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error\n                                                   Value is allowed for gState only */\n} HAL_UART_StateTypeDef;\n\n/**\n  * @brief HAL UART Reception type definition\n  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.\n  *        It is expected to admit following values :\n  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,\n  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,\n  */\ntypedef uint32_t HAL_UART_RxTypeTypeDef;\n\n/**\n  * @brief  UART handle Structure definition\n  */\ntypedef struct __UART_HandleTypeDef\n{\n  USART_TypeDef                 *Instance;        /*!< UART registers base address        */\n\n  UART_InitTypeDef              Init;             /*!< UART communication parameters      */\n\n  uint8_t                       *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */\n\n  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */\n\n  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */\n\n  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */\n\n  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */\n\n  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */\n\n  __IO HAL_UART_RxTypeTypeDef ReceptionType;      /*!< Type of ongoing reception          */\n\n  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */\n\n  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */\n\n  HAL_LockTypeDef               Lock;             /*!< Locking object                     */\n\n  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management\n                                                       and also related to Tx operations.\n                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */\n\n  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.\n                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */\n\n  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */\n  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */\n  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */\n  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */\n  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */\n  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */\n  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */\n  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */\n  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */\n  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */\n\n  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */\n  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */\n#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n} UART_HandleTypeDef;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  HAL UART Callback ID enumeration definition\n  */\ntypedef enum\n{\n  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */\n  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */\n  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */\n  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */\n  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */\n  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */\n  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */\n  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */\n  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */\n\n  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */\n  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */\n\n} HAL_UART_CallbackIDTypeDef;\n\n/**\n  * @brief  HAL UART Callback pointer definition\n  */\ntypedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */\ntypedef  void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos);   /*!< pointer to a UART Rx Event specific callback function */\n\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup UART_Exported_Constants UART Exported Constants\n  * @{\n  */\n\n/** @defgroup UART_Error_Code UART Error Code\n  * @{\n  */\n#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */\n#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */\n#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */\n#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */\n#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */\n#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @defgroup UART_Word_Length UART Word Length\n  * @{\n  */\n#define UART_WORDLENGTH_8B                  0x00000000U\n#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)\n/**\n  * @}\n  */\n\n/** @defgroup UART_Stop_Bits UART Number of Stop Bits\n  * @{\n  */\n#define UART_STOPBITS_1                     0x00000000U\n#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)\n/**\n  * @}\n  */\n\n/** @defgroup UART_Parity UART Parity\n  * @{\n  */\n#define UART_PARITY_NONE                    0x00000000U\n#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)\n#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))\n/**\n  * @}\n  */\n\n/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control\n  * @{\n  */\n#define UART_HWCONTROL_NONE                  0x00000000U\n#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)\n#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)\n#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))\n/**\n  * @}\n  */\n\n/** @defgroup UART_Mode UART Transfer Mode\n  * @{\n  */\n#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)\n#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)\n#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))\n/**\n  * @}\n  */\n\n/** @defgroup UART_State UART State\n  * @{\n  */\n#define UART_STATE_DISABLE                  0x00000000U\n#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)\n/**\n  * @}\n  */\n\n/** @defgroup UART_Over_Sampling UART Over Sampling\n  * @{\n  */\n#define UART_OVERSAMPLING_16                    0x00000000U\n#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)\n/**\n  * @}\n  */\n\n/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length\n  * @{\n  */\n#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U\n#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)\n/**\n  * @}\n  */\n\n/** @defgroup UART_WakeUp_functions  UART Wakeup Functions\n  * @{\n  */\n#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U\n#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)\n/**\n  * @}\n  */\n\n/** @defgroup UART_Flags   UART FLags\n  *        Elements values convention: 0xXXXX\n  *           - 0xXXXX  : Flag mask in the SR register\n  * @{\n  */\n#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)\n#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)\n#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)\n#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)\n#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)\n#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)\n#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)\n#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)\n#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)\n#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)\n/**\n  * @}\n  */\n\n/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions\n  *        Elements values convention: 0xY000XXXX\n  *           - XXXX  : Interrupt mask (16 bits) in the Y register\n  *           - Y  : Interrupt source register (2bits)\n  *                   - 0001: CR1 register\n  *                   - 0010: CR2 register\n  *                   - 0011: CR3 register\n  * @{\n  */\n\n#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))\n#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))\n#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))\n#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))\n#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))\n\n#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))\n\n#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))\n#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))\n/**\n  * @}\n  */\n\n/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values\n  * @{\n  */\n#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */\n#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup UART_Exported_Macros UART Exported Macros\n  * @{\n  */\n\n/** @brief Reset UART handle gstate & RxState\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\\n                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\\n                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\\n                                                       (__HANDLE__)->MspInitCallback = NULL;             \\\n                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \\\n                                                     } while(0U)\n#else\n#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \\\n                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \\\n                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \\\n                                                     } while(0U)\n#endif /*USE_HAL_UART_REGISTER_CALLBACKS */\n\n/** @brief  Flushes the UART DR register\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  */\n#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)\n\n/** @brief  Checks whether the specified UART flag is set or not.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @param  __FLAG__ specifies the flag to check.\n  *        This parameter can be one of the following values:\n  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)\n  *            @arg UART_FLAG_LBD:  LIN Break detection flag\n  *            @arg UART_FLAG_TXE:  Transmit data register empty flag\n  *            @arg UART_FLAG_TC:   Transmission Complete flag\n  *            @arg UART_FLAG_RXNE: Receive data register not empty flag\n  *            @arg UART_FLAG_IDLE: Idle Line detection flag\n  *            @arg UART_FLAG_ORE:  Overrun Error flag\n  *            @arg UART_FLAG_NE:   Noise Error flag\n  *            @arg UART_FLAG_FE:   Framing Error flag\n  *            @arg UART_FLAG_PE:   Parity Error flag\n  * @retval The new state of __FLAG__ (TRUE or FALSE).\n  */\n#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))\n\n/** @brief  Clears the specified UART pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @param  __FLAG__ specifies the flag to check.\n  *          This parameter can be any combination of the following values:\n  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).\n  *            @arg UART_FLAG_LBD:  LIN Break detection flag.\n  *            @arg UART_FLAG_TC:   Transmission Complete flag.\n  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.\n  *\n  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun\n  *          error) and IDLE (Idle line detected) flags are cleared by software\n  *          sequence: a read operation to USART_SR register followed by a read\n  *          operation to USART_DR register.\n  * @note   RXNE flag can be also cleared by a read to the USART_DR register.\n  * @note   TC flag can be also cleared by software sequence: a read operation to\n  *          USART_SR register followed by a write operation to USART_DR register.\n  * @note   TXE flag is cleared only by a write to the USART_DR register.\n  *\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))\n\n/** @brief  Clears the UART PE pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \\\n  do{                                           \\\n    __IO uint32_t tmpreg = 0x00U;               \\\n    tmpreg = (__HANDLE__)->Instance->SR;        \\\n    tmpreg = (__HANDLE__)->Instance->DR;        \\\n    UNUSED(tmpreg);                             \\\n  } while(0U)\n\n/** @brief  Clears the UART FE pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\n\n/** @brief  Clears the UART NE pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\n\n/** @brief  Clears the UART ORE pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\n\n/** @brief  Clears the UART IDLE pending flag.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @retval None\n  */\n#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)\n\n/** @brief  Enable the specified UART interrupt.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.\n  *          This parameter can be one of the following values:\n  *            @arg UART_IT_CTS:  CTS change interrupt\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\n  *            @arg UART_IT_TC:   Transmission complete interrupt\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\n  *            @arg UART_IT_PE:   Parity Error interrupt\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\n  * @retval None\n  */\n#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \\\n                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \\\n                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))\n\n/** @brief  Disable the specified UART interrupt.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.\n  *          This parameter can be one of the following values:\n  *            @arg UART_IT_CTS:  CTS change interrupt\n  *            @arg UART_IT_LBD:  LIN Break detection interrupt\n  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt\n  *            @arg UART_IT_TC:   Transmission complete interrupt\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\n  *            @arg UART_IT_PE:   Parity Error interrupt\n  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)\n  * @retval None\n  */\n#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \\\n                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \\\n                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))\n\n/** @brief  Checks whether the specified UART interrupt source is enabled or not.\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         UART Handle selects the USARTx or UARTy peripheral\n  *         (USART,UART availability and x,y values depending on device).\n  * @param  __IT__ specifies the UART interrupt source to check.\n  *          This parameter can be one of the following values:\n  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)\n  *            @arg UART_IT_LBD: LIN Break detection interrupt\n  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt\n  *            @arg UART_IT_TC:  Transmission complete interrupt\n  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt\n  *            @arg UART_IT_IDLE: Idle line detection interrupt\n  *            @arg UART_IT_ERR: Error interrupt\n  * @retval The new state of __IT__ (TRUE or FALSE).\n  */\n#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \\\n                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))\n\n/** @brief  Enable CTS flow control\n  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,\n  *         without need to call HAL_UART_Init() function.\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).\n  *         It is used to select the USART peripheral (USART availability and x value depending on device).\n  * @retval None\n  */\n#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \\\n  do{                                                      \\\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \\\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \\\n  } while(0U)\n\n/** @brief  Disable CTS flow control\n  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,\n  *         without need to call HAL_UART_Init() function.\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\n  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).\n  *         It is used to select the USART peripheral (USART availability and x value depending on device).\n  * @retval None\n  */\n#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \\\n  do{                                                       \\\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \\\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \\\n  } while(0U)\n\n/** @brief  Enable RTS flow control\n  *         This macro allows to enable RTS hardware flow control for a given UART instance,\n  *         without need to call HAL_UART_Init() function.\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).\n  *         It is used to select the USART peripheral (USART availability and x value depending on device).\n  * @retval None\n  */\n#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \\\n  do{                                                     \\\n    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \\\n    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \\\n  } while(0U)\n\n/** @brief  Disable RTS flow control\n  *         This macro allows to disable RTS hardware flow control for a given UART instance,\n  *         without need to call HAL_UART_Init() function.\n  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.\n  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need\n  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :\n  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )\n  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))\n  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).\n  * @param  __HANDLE__ specifies the UART Handle.\n  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).\n  *         It is used to select the USART peripheral (USART availability and x value depending on device).\n  * @retval None\n  */\n#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \\\n  do{                                                      \\\n    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\\\n    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \\\n  } while(0U)\n\n/** @brief  Macro to enable the UART's one bit sample method\n  * @param  __HANDLE__ specifies the UART Handle.\n  * @retval None\n  */\n#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)\n\n/** @brief  Macro to disable the UART's one bit sample method\n  * @param  __HANDLE__ specifies the UART Handle.\n  * @retval None\n  */\n#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))\n\n/** @brief  Enable UART\n  * @param  __HANDLE__ specifies the UART Handle.\n  * @retval None\n  */\n#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)\n\n/** @brief  Disable UART\n  * @param  __HANDLE__ specifies the UART Handle.\n  * @retval None\n  */\n#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup UART_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\n  * @{\n  */\n\n/* Initialization/de-initialization functions  **********************************/\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);\nHAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);\nvoid HAL_UART_MspInit(UART_HandleTypeDef *huart);\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef *huart);\n\n/* Callbacks Register/UnRegister functions  ***********************************/\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\nHAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);\n\nHAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);\nHAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @addtogroup UART_Exported_Functions_Group2 IO operation functions\n  * @{\n  */\n\n/* IO operation functions *******************************************************/\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);\n\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout);\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\n\n/* Transfer Abort functions */\nHAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);\n\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart);\nvoid HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);\nvoid HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);\n\nvoid HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);\n\n/**\n  * @}\n  */\n\n/** @addtogroup UART_Exported_Functions_Group3\n  * @{\n  */\n/* Peripheral Control functions  ************************************************/\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);\n/**\n  * @}\n  */\n\n/** @addtogroup UART_Exported_Functions_Group4\n  * @{\n  */\n/* Peripheral State functions  **************************************************/\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);\nuint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup UART_Private_Constants UART Private Constants\n  * @{\n  */\n/** @brief UART interruptions flag mask\n  *\n  */\n#define UART_IT_MASK                     0x0000FFFFU\n\n#define UART_CR1_REG_INDEX               1U\n#define UART_CR2_REG_INDEX               2U\n#define UART_CR3_REG_INDEX               3U\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup UART_Private_Macros UART Private Macros\n  * @{\n  */\n#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \\\n                                     ((LENGTH) == UART_WORDLENGTH_9B))\n#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))\n#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \\\n                                    ((STOPBITS) == UART_STOPBITS_2))\n#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \\\n                                ((PARITY) == UART_PARITY_EVEN) || \\\n                                ((PARITY) == UART_PARITY_ODD))\n#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\\\n                              (((CONTROL) == UART_HWCONTROL_NONE) || \\\n                               ((CONTROL) == UART_HWCONTROL_RTS) || \\\n                               ((CONTROL) == UART_HWCONTROL_CTS) || \\\n                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))\n#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))\n#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \\\n                              ((STATE) == UART_STATE_ENABLE))\n#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \\\n                                        ((SAMPLING) == UART_OVERSAMPLING_8))\n#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))\n#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \\\n                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))\n#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \\\n                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))\n#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)\n#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)\n\n#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))\n#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)\n#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U)\n/* UART BRR = mantissa + overflow + fraction\n            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */\n#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \\\n                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \\\n                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))\n\n#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))\n#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)\n#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U)\n/* UART BRR = mantissa + overflow + fraction\n            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */\n#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \\\n                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \\\n                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup UART_Private_Functions UART Private Functions\n  * @{\n  */\n\nHAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\nHAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_HAL_UART_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_adc.h\n  * @author  MCD Application Team\n  * @brief   Header file of ADC LL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F4xx_LL_ADC_H\n#define __STM32F4xx_LL_ADC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (ADC1) || defined (ADC2) || defined (ADC3)\n\n/** @defgroup ADC_LL ADC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n\n/* Private constants ---------------------------------------------------------*/\n/** @defgroup ADC_LL_Private_Constants ADC Private Constants\n  * @{\n  */\n\n/* Internal mask for ADC group regular sequencer:                             */\n/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */\n/* - sequencer register offset                                                */\n/* - sequencer rank bits position into the selected register                  */\n\n/* Internal register offset for ADC group regular sequencer configuration */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_SQR1_REGOFFSET                 0x00000000UL\n#define ADC_SQR2_REGOFFSET                 0x00000100UL\n#define ADC_SQR3_REGOFFSET                 0x00000200UL\n#define ADC_SQR4_REGOFFSET                 0x00000300UL\n\n#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)\n#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\n\n/* Definition of ADC group regular sequencer bits information to be inserted  */\n/* into ADC group regular sequencer ranks literals definition.                */\n#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */\n#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */\n#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */\n#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */\n#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */\n#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */\n#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */\n#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */\n#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */\n#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */\n#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */\n#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */\n#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */\n#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */\n#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */\n#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */\n\n/* Internal mask for ADC group injected sequencer:                            */\n/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */\n/* - data register offset                                                     */\n/* - offset register offset                                                   */\n/* - sequencer rank bits position into the selected register                  */\n\n/* Internal register offset for ADC group injected data register */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_JDR1_REGOFFSET                 0x00000000UL\n#define ADC_JDR2_REGOFFSET                 0x00000100UL\n#define ADC_JDR3_REGOFFSET                 0x00000200UL\n#define ADC_JDR4_REGOFFSET                 0x00000300UL\n\n/* Internal register offset for ADC group injected offset configuration */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_JOFR1_REGOFFSET                0x00000000UL\n#define ADC_JOFR2_REGOFFSET                0x00001000UL\n#define ADC_JOFR3_REGOFFSET                0x00002000UL\n#define ADC_JOFR4_REGOFFSET                0x00003000UL\n\n#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)\n#define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)\n#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)\n\n/* Internal mask for ADC group regular trigger:                               */\n/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */\n/* - regular trigger source                                                   */\n/* - regular trigger edge                                                     */\n#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\n\n/* Mask containing trigger source masks for each of possible                  */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \\\n                                             ((ADC_CR2_EXTSEL)                            >> (4UL * 1UL)) | \\\n                                             ((ADC_CR2_EXTSEL)                            >> (4UL * 2UL)) | \\\n                                             ((ADC_CR2_EXTSEL)                            >> (4UL * 3UL)))\n\n/* Mask containing trigger edge masks for each of possible                    */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4UL * 1UL)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4UL * 2UL)) | \\\n                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4UL * 3UL)))\n\n/* Definition of ADC group regular trigger bits information.                  */\n#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */\n#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */\n\n\n\n/* Internal mask for ADC group injected trigger:                              */\n/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */\n/* - injected trigger source                                                  */\n/* - injected trigger edge                                                    */\n#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */\n\n/* Mask containing trigger source masks for each of possible                  */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \\\n                                             ((ADC_CR2_JEXTSEL)                            >> (4UL * 1UL)) | \\\n                                             ((ADC_CR2_JEXTSEL)                            >> (4UL * 2UL)) | \\\n                                             ((ADC_CR2_JEXTSEL)                            >> (4UL * 3UL)))\n\n/* Mask containing trigger edge masks for each of possible                    */\n/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */\n/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */\n#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4UL * 1UL)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4UL * 2UL)) | \\\n                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4UL * 3UL)))\n\n/* Definition of ADC group injected trigger bits information.                 */\n#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */\n#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */\n\n/* Internal mask for ADC channel:                                             */\n/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */\n/* - channel identifier defined by number                                     */\n/* - channel differentiation between external channels (connected to          */\n/*   GPIO pins) and internal channels (connected to internal paths)           */\n/* - channel sampling time defined by SMPRx register offset                   */\n/*   and SMPx bits positions into SMPRx register                              */\n#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)\n#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */\n#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)\n/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */\n#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */\n\n/* Channel differentiation between external and internal channels */\n#define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000UL   /* Marker of internal channel */\n#define ADC_CHANNEL_ID_INTERNAL_CH_2       0x40000000UL   /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */\n#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U  /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */\n#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)\n\n/* Internal register offset for ADC channel sampling time configuration */\n/* (offset placed into a spare area of literal definition) */\n#define ADC_SMPR1_REGOFFSET                0x00000000UL\n#define ADC_SMPR2_REGOFFSET                0x02000000UL\n#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)\n\n#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000UL\n#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */\n\n/* Definition of channels ID number information to be inserted into           */\n/* channels literals definition.                                              */\n#define ADC_CHANNEL_0_NUMBER               0x00000000UL\n#define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )\n#define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )\n#define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )\n#define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )\n#define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )\n#define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )\n#define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )\n#define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )\n#define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)\n#define ADC_CHANNEL_18_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1                  )\n\n/* Definition of channels sampling time information to be inserted into       */\n/* channels literals definition.                                              */\n#define ADC_CHANNEL_0_SMP                  (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */\n#define ADC_CHANNEL_1_SMP                  (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */\n#define ADC_CHANNEL_2_SMP                  (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */\n#define ADC_CHANNEL_3_SMP                  (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */\n#define ADC_CHANNEL_4_SMP                  (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */\n#define ADC_CHANNEL_5_SMP                  (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */\n#define ADC_CHANNEL_6_SMP                  (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */\n#define ADC_CHANNEL_7_SMP                  (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */\n#define ADC_CHANNEL_8_SMP                  (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */\n#define ADC_CHANNEL_9_SMP                  (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */\n#define ADC_CHANNEL_10_SMP                 (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */\n#define ADC_CHANNEL_11_SMP                 (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */\n#define ADC_CHANNEL_12_SMP                 (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */\n#define ADC_CHANNEL_13_SMP                 (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */\n#define ADC_CHANNEL_14_SMP                 (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */\n#define ADC_CHANNEL_15_SMP                 (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */\n#define ADC_CHANNEL_16_SMP                 (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */\n#define ADC_CHANNEL_17_SMP                 (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */\n#define ADC_CHANNEL_18_SMP                 (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */\n\n/* Internal mask for ADC analog watchdog:                                     */\n/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */\n/* (concatenation of multiple bits used in different analog watchdogs,        */\n/* (feature of several watchdogs not available on all STM32 families)).       */\n/* - analog watchdog 1: monitored channel defined by number,                  */\n/*   selection of ADC group (ADC groups regular and-or injected).             */\n\n/* Internal register offset for ADC analog watchdog channel configuration */\n#define ADC_AWD_CR1_REGOFFSET              0x00000000UL\n\n#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)\n\n#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)\n#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)\n\n/* Internal register offset for ADC analog watchdog threshold configuration */\n#define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000UL\n#define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001UL\n#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)\n\n/* ADC registers bits positions */\n#define ADC_CR1_RES_BITOFFSET_POS          (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */\n#define ADC_TR_HT_BITOFFSET_POS            (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */\n\n/* ADC internal channels related definitions */\n/* Internal voltage reference VrefInt */\n#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\n#define VREFINT_CAL_VREF                   ( 3300UL)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */\n/* Temperature sensor */\n#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\n#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\n#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */\n#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */\n#define TEMPSENSOR_CAL_VREFANALOG          ( 3300UL)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */\n\n/**\n  * @}\n  */\n\n\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup ADC_LL_Private_Macros ADC Private Macros\n  * @{\n  */\n\n/**\n  * @brief  Driver macro reserved for internal use: isolate bits with the\n  *         selected mask and shift them to the register LSB\n  *         (shift mask on register position bit 0).\n  * @param  __BITS__ Bits in register 32 bits\n  * @param  __MASK__ Mask in register 32 bits\n  * @retval Bits in register 32 bits\n  */\n#define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \\\n  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))\n\n/**\n  * @brief  Driver macro reserved for internal use: set a pointer to\n  *         a register from a register basis from which an offset\n  *         is applied.\n  * @param  __REG__ Register basis from which the offset is applied.\n  * @param  __REG_OFFFSET__ Offset to be applied (unit number of registers).\n  * @retval Pointer to register address\n  */\n#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \\\n ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))\n\n/**\n  * @}\n  */\n\n\n/* Exported types ------------------------------------------------------------*/\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure\n  * @{\n  */\n\n/**\n  * @brief  Structure definition of some features of ADC common parameters\n  *         and multimode\n  *         (all ADC instances belonging to the same ADC common instance).\n  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()\n  *         is conditioned to ADC instances state (all ADC instances\n  *         sharing the same ADC common instance):\n  *         All ADC instances sharing the same ADC common instance must be\n  *         disabled.\n  */\ntypedef struct\n{\n  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.\n                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */\n\n  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */\n\n  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.\n                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n} LL_ADC_CommonInitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC instance.\n  * @note   These parameters have an impact on ADC scope: ADC instance.\n  *         Affects both group regular and group injected (availability\n  *         of ADC group injected depends on STM32 families).\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Instance .\n  * @note   The setting of these parameters by function @ref LL_ADC_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t Resolution;                  /*!< Set ADC resolution.\n                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */\n\n  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.\n                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */\n\n  uint32_t SequencersScanMode;          /*!< Set ADC scan selection.\n                                             This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */\n\n} LL_ADC_InitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC group regular.\n  * @note   These parameters have an impact on ADC scope: ADC group regular.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"REG\").\n  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE\n                                             @note On this STM32 series, setting of external trigger edge is performed\n                                                   using function @ref LL_ADC_REG_StartConversionExtTrig().\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */\n\n  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH\n                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */\n\n  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE\n                                             @note This parameter has an effect only if group regular sequencer is enabled\n                                                   (scan length of 2 ranks or more).\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */\n\n  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE\n                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */\n\n  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.\n                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */\n\n} LL_ADC_REG_InitTypeDef;\n\n/**\n  * @brief  Structure definition of some features of ADC group injected.\n  * @note   These parameters have an impact on ADC scope: ADC group injected.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"INJ\").\n  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  */\ntypedef struct\n{\n  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE\n                                             @note On this STM32 series, setting of external trigger edge is performed\n                                                   using function @ref LL_ADC_INJ_StartConversionExtTrig().\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */\n\n  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH\n                                             @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */\n\n  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE\n                                             @note This parameter has an effect only if group injected sequencer is enabled\n                                                   (scan length of 2 ranks or more).\n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */\n\n  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.\n                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO\n                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. \n                                             \n                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */\n\n} LL_ADC_INJ_InitTypeDef;\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/* Exported constants --------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants\n  * @{\n  */\n\n/** @defgroup ADC_LL_EC_FLAG ADC flags\n  * @brief    Flags defines which can be used with LL_ADC_ReadReg function\n  * @{\n  */\n#define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */\n#define LL_ADC_FLAG_EOCS                   ADC_SR_EOC         /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */\n#define LL_ADC_FLAG_OVR                    ADC_SR_OVR         /*!< ADC flag ADC group regular overrun */\n#define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */\n#define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as \"JEOC\" is corresponding to flag \"JEOS\" in other STM32 families) */\n#define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */\n#if defined(ADC_MULTIMODE_SUPPORT)\n#define LL_ADC_FLAG_EOCS_MST               ADC_CSR_EOC1       /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */\n#define LL_ADC_FLAG_EOCS_SLV1              ADC_CSR_EOC2       /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */\n#define LL_ADC_FLAG_EOCS_SLV2              ADC_CSR_EOC3       /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */\n#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR1    /*!< ADC flag ADC multimode master group regular overrun */ \n#define LL_ADC_FLAG_OVR_SLV1               ADC_CSR_OVR2   /*!< ADC flag ADC multimode slave 1 group regular overrun */\n#define LL_ADC_FLAG_OVR_SLV2               ADC_CSR_OVR3   /*!< ADC flag ADC multimode slave 2 group regular overrun */\n#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOC1     /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as \"JEOC\" is corresponding to flag \"JEOS\" in other STM32 families) */\n#define LL_ADC_FLAG_JEOS_SLV1              ADC_CSR_JEOC2  /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as \"JEOC\" is corresponding to flag \"JEOS\" in other STM32 families) */\n#define LL_ADC_FLAG_JEOS_SLV2              ADC_CSR_JEOC3  /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as \"JEOC\" is corresponding to flag \"JEOS\" in other STM32 families) */\n#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1       /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */\n#define LL_ADC_FLAG_AWD1_SLV1              ADC_CSR_AWD2       /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */\n#define LL_ADC_FLAG_AWD1_SLV2              ADC_CSR_AWD3       /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)\n  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions\n  * @{\n  */\n#define LL_ADC_IT_EOCS                     ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */\n#define LL_ADC_IT_OVR                      ADC_CR1_OVRIE      /*!< ADC interruption ADC group regular overrun */\n#define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as \"JEOC\" is corresponding to flag \"JEOS\" in other STM32 families) */\n#define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose\n  * @{\n  */\n/* List of ADC registers intended to be used (most commonly) with             */\n/* DMA transfer.                                                              */\n/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */\n#define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000UL   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */\n#if defined(ADC_MULTIMODE_SUPPORT)\n#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    0x00000001UL   /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source\n  * @{\n  */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        0x00000000UL                                           /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (                   ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV6        (ADC_CCR_ADCPRE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */\n#define LL_ADC_CLOCK_SYNC_PCLK_DIV8        (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels\n  * @{\n  */\n/* Note: Other measurement paths to internal channels may be available        */\n/*       (connections to other peripherals).                                  */\n/*       If they are not listed below, they do not require any specific       */\n/*       path enable. In this case, Access to measurement path is done        */\n/*       only by selecting the corresponding ADC internal channel.            */\n#define LL_ADC_PATH_INTERNAL_NONE          0x00000000UL            /*!< ADC measurement paths all disabled */\n#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */\n#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */\n#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATE)        /*!< ADC measurement path to internal channel Vbat */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution\n  * @{\n  */\n#define LL_ADC_RESOLUTION_12B              0x00000000UL                         /*!< ADC resolution 12 bits */\n#define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */\n#define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */\n#define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment\n  * @{\n  */\n#define LL_ADC_DATA_ALIGN_RIGHT            0x00000000UL            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/\n#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection\n  * @{\n  */\n#define LL_ADC_SEQ_SCAN_DISABLE            0x00000000UL    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/\n#define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups\n  * @{\n  */\n#define LL_ADC_GROUP_REGULAR               0x00000001UL   /*!< ADC group regular (available on all STM32 devices) */\n#define LL_ADC_GROUP_INJECTED              0x00000002UL   /*!< ADC group injected (not available on all STM32 devices)*/\n#define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003UL   /*!< ADC both groups regular and injected */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number\n  * @{\n  */\n#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */\n#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */\n#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */\n#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */\n#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */\n#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */\n#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */\n#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */\n#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */\n#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */\n#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */\n#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */\n#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */\n#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */\n#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */\n#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */\n#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */\n#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */\n#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */\n#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */\n#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)\n#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */\n#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */\n#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source\n  * @{\n  */\n#define LL_ADC_REG_TRIG_SOFTWARE           0x00000000UL                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                             /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM5_CH1       (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM5_CH2       (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM5_CH3       (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge\n  * @{\n  */\n#define LL_ADC_REG_TRIG_EXT_RISING         (                  ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to rising edge */\n#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CR2_EXTEN_1                  )     /*!< ADC group regular conversion trigger polarity set to falling edge */\n#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode\n* @{\n*/\n#define LL_ADC_REG_CONV_SINGLE             0x00000000UL             /*!< ADC conversions are performed in single mode: one conversion per trigger */\n#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data\n  * @{\n  */\n#define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000UL              /*!< ADC conversions are not transferred by DMA */\n#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */\n#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)\n  * @{\n  */\n#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000UL    /*!< ADC flag EOC (end of unitary conversion) selected */\n#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length\n  * @{\n  */\n#define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000UL                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */\n#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode\n  * @{\n  */\n#define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000UL                                                                  /*!< ADC group regular sequencer discontinuous mode disable */\n#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */\n#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */\n#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks\n  * @{\n  */\n#define LL_ADC_REG_RANK_1                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */\n#define LL_ADC_REG_RANK_2                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */\n#define LL_ADC_REG_RANK_3                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */\n#define LL_ADC_REG_RANK_4                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */\n#define LL_ADC_REG_RANK_5                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */\n#define LL_ADC_REG_RANK_6                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */\n#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */\n#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */\n#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */\n#define LL_ADC_REG_RANK_10                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */\n#define LL_ADC_REG_RANK_11                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */\n#define LL_ADC_REG_RANK_12                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */\n#define LL_ADC_REG_RANK_13                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */\n#define LL_ADC_REG_RANK_14                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */\n#define LL_ADC_REG_RANK_15                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */\n#define LL_ADC_REG_RANK_16                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source\n  * @{\n  */\n#define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000UL                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */\n#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CH2       (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_CH3       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */\n#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge\n  * @{\n  */\n#define LL_ADC_INJ_TRIG_EXT_RISING         (                   ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to rising edge */\n#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_CR2_JEXTEN_1                   )   /*!< ADC group injected conversion trigger polarity set to falling edge */\n#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode\n* @{\n*/\n#define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000UL            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */\n#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */\n/**\n  * @}\n  */\n\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length\n  * @{\n  */\n#define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000UL                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */\n#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode\n  * @{\n  */\n#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000UL            /*!< ADC group injected sequencer discontinuous mode disable */\n#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks\n  * @{\n  */\n#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */\n#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */\n#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */\n#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time\n  * @{\n  */\n#define LL_ADC_SAMPLINGTIME_3CYCLES        0x00000000UL                                              /*!< Sampling time 3 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_15CYCLES       (ADC_SMPR1_SMP10_0)                                      /*!< Sampling time 15 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_28CYCLES       (ADC_SMPR1_SMP10_1)                                      /*!< Sampling time 28 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_56CYCLES       (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 56 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_84CYCLES       (ADC_SMPR1_SMP10_2)                                      /*!< Sampling time 84 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_112CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 112 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_144CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)                  /*!< Sampling time 144 ADC clock cycles */\n#define LL_ADC_SAMPLINGTIME_480CYCLES      (ADC_SMPR1_SMP10)                                        /*!< Sampling time 480 ADC clock cycles */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number\n  * @{\n  */\n#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels\n  * @{\n  */\n#define LL_ADC_AWD_DISABLE                 0x00000000UL                                                                                   /*!< ADC analog watchdog monitoring disabled */\n#define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */\n#define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */\n#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */\n#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */\n#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */\n#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */\n#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */\n#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */\n#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */\n#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */\n#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */\n#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */\n#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */\n#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */\n#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */\n#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds\n  * @{\n  */\n#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */\n#define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */\n/**\n  * @}\n  */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode\n  * @{\n  */\n#define LL_ADC_MULTI_INDEPENDENT           0x00000000UL                                                             /*!< ADC dual mode disabled (ADC independent mode) */\n#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: group regular simultaneous */\n#define LL_ADC_MULTI_DUAL_REG_INTERL       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */\n#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                  ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */\n#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_MULTI_3                                     | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */\n#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                      ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */\n#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                    ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */\n#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                    ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */\n#if defined(ADC3)\n#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM  (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */\n#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT  (ADC_CCR_MULTI_4                                     | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */\n#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */\n#define LL_ADC_MULTI_TRIPLE_REG_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: group regular simultaneous */\n#define LL_ADC_MULTI_TRIPLE_REG_INTERL       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */\n#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN       (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */\n#endif\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer\n  * @{\n  */\n#define LL_ADC_MULTI_REG_DMA_EACH_ADC        0x00000000UL                                   /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */\n#define LL_ADC_MULTI_REG_DMA_LIMIT_1         (                              ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */\n#define LL_ADC_MULTI_REG_DMA_LIMIT_2         (              ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */\n#define LL_ADC_MULTI_REG_DMA_LIMIT_3         (              ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */\n#define LL_ADC_MULTI_REG_DMA_UNLMT_1         (ADC_CCR_DDS |                 ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */\n#define LL_ADC_MULTI_REG_DMA_UNLMT_2         (ADC_CCR_DDS | ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */\n#define LL_ADC_MULTI_REG_DMA_UNLMT_3         (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases\n  * @{\n  */\n#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  0x00000000UL                                                             /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/\n#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */\n#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave\n  * @{\n  */\n#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */\n#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */\n#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */\n/**\n  * @}\n  */\n\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n\n/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays\n  * @note   Only ADC IP HW delays are defined in ADC LL driver driver,\n  *         not timeout values.\n  *         For details on delays values, refer to descriptions in source code\n  *         above each literal definition.\n  * @{\n  */\n  \n/* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */\n/*       not timeout values.                                                  */\n/*       Timeout values for ADC operations are dependent to device clock      */\n/*       configuration (system clock versus ADC clock),                       */\n/*       and therefore must be defined in user application.                   */\n/*       Indications for estimation of ADC timeout delays, for this           */\n/*       STM32 series:                                                        */\n/*       - ADC enable time: maximum delay is 2us                              */\n/*         (refer to device datasheet, parameter \"tSTAB\")                     */\n/*       - ADC conversion time: duration depending on ADC clock and ADC       */\n/*         configuration.                                                     */\n/*         (refer to device reference manual, section \"Timing\")               */\n\n/* Delay for internal voltage reference stabilization time.                   */\n/* Delay set to maximum value (refer to device datasheet,                     */\n/* parameter \"tSTART\").                                                       */\n/* Unit: us                                                                   */\n#define LL_ADC_DELAY_VREFINT_STAB_US       (  10UL)  /*!< Delay for internal voltage reference stabilization time */\n\n/* Delay for temperature sensor stabilization time.                           */\n/* Literal set to maximum value (refer to device datasheet,                   */\n/* parameter \"tSTART\").                                                       */\n/* Unit: us                                                                   */\n#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10UL)  /*!< Delay for internal voltage reference stabilization time */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros\n  * @{\n  */\n\n/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros\n  * @{\n  */\n\n/**\n  * @brief  Write a value in ADC register\n  * @param  __INSTANCE__ ADC Instance\n  * @param  __REG__ Register to be written\n  * @param  __VALUE__ Value to be written in the register\n  * @retval None\n  */\n#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))\n\n/**\n  * @brief  Read a value in ADC register\n  * @param  __INSTANCE__ ADC Instance\n  * @param  __REG__ Register to be read\n  * @retval Register value\n  */\n#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro\n  * @{\n  */\n\n/**\n  * @brief  Helper macro to get ADC channel number in decimal format\n  *         from literals LL_ADC_CHANNEL_x.\n  * @note   Example:\n  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)\n  *           will return decimal number \"4\".\n  * @note   The input can be a value from functions where a channel\n  *         number is returned, either defined with number\n  *         or with bitfield (only one bit must be set).\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval Value between Min_Data=0 and Max_Data=18\n  */\n#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \\\n  (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)\n\n/**\n  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x\n  *         from number in decimal format.\n  * @note   Example:\n  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)\n  *           will return a data equivalent to \"LL_ADC_CHANNEL_4\".\n  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\\n\n  *         (1) For ADC channel read back from ADC register,\n  *             comparison with internal channel parameter to be done\n  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \\\n  (((__DECIMAL_NB__) <= 9UL)                                                                                     \\\n    ? (                                                                                                         \\\n       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \\\n       (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \\\n      )                                                                                                         \\\n      :                                                                                                         \\\n      (                                                                                                         \\\n       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \\\n       (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \\\n      )                                                                                                         \\\n  )\n\n/**\n  * @brief  Helper macro to determine whether the selected channel\n  *         corresponds to literal definitions of driver.\n  * @note   The different literal definitions of ADC channels are:\n  *         - ADC internal channel:\n  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...\n  *         - ADC external channel (channel connected to a GPIO pin):\n  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...\n  * @note   The channel parameter must be a value defined from literal\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),\n  *         must not be a value from functions where a channel number is\n  *         returned from ADC registers,\n  *         because internal and external channels share the same channel\n  *         number in ADC registers. The differentiation is made only with\n  *         parameters definitions of driver.\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval Value \"0\" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).\n  *         Value \"1\" if the channel corresponds to a parameter definition of a ADC internal channel.\n  */\n#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \\\n  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)\n\n/**\n  * @brief  Helper macro to convert a channel defined from parameter\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         to its equivalent parameter definition of a ADC external channel\n  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).\n  * @note   The channel parameter can be, additionally to a value\n  *         defined from parameter definition of a ADC internal channel\n  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         a value defined from parameter definition of\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\n  *         or a value from functions where a channel number is returned\n  *         from ADC registers.\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  */\n#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \\\n  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)\n\n/**\n  * @brief  Helper macro to determine whether the internal channel\n  *         selected is available on the ADC instance selected.\n  * @note   The channel parameter must be a value defined from parameter\n  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,\n  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),\n  *         must not be a value defined from parameter definition of\n  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)\n  *         or a value from functions where a channel number is\n  *         returned from ADC registers,\n  *         because internal and external channels share the same channel\n  *         number in ADC registers. The differentiation is made only with\n  *         parameters definitions of driver.\n  * @param  __ADC_INSTANCE__ ADC instance\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval Value \"0\" if the internal channel selected is not available on the ADC instance selected.\n  *         Value \"1\" if the internal channel selected is available on the ADC instance selected.\n  */\n#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \\\n  (                                                                            \\\n   ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \\\n   ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                             \\\n   ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                      \\\n  )\n/**\n  * @brief  Helper macro to define ADC analog watchdog parameter:\n  *         define a single channel to monitor with analog watchdog\n  *         from sequencer channel and groups definition.\n  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().\n  *         Example:\n  *           LL_ADC_SetAnalogWDMonitChannels(\n  *             ADC1, LL_ADC_AWD1,\n  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))\n  * @param  __CHANNEL__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\\n\n  *         (1) For ADC channel read back from ADC register,\n  *             comparison with internal channel parameter to be done\n  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  * @param  __GROUP__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_GROUP_REGULAR\n  *         @arg @ref LL_ADC_GROUP_INJECTED\n  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  */\n#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \\\n  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \\\n    ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \\\n      :                                                                                                   \\\n      ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \\\n       ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \\\n         :                                                                                                \\\n         (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \\\n  )\n\n/**\n  * @brief  Helper macro to set the value of ADC analog watchdog threshold high\n  *         or low in function of ADC resolution, when ADC resolution is\n  *         different of 12 bits.\n  * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().\n  *         Example, with a ADC resolution of 8 bits, to set the value of\n  *         analog watchdog threshold high (on 8 bits):\n  *           LL_ADC_SetAnalogWDThresholds\n  *            (< ADCx param >,\n  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)\n  *            );\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \\\n  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))\n\n/**\n  * @brief  Helper macro to get the value of ADC analog watchdog threshold high\n  *         or low in function of ADC resolution, when ADC resolution is \n  *         different of 12 bits.\n  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().\n  *         Example, with a ADC resolution of 8 bits, to get the value of\n  *         analog watchdog threshold high (on 8 bits):\n  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION\n  *            (LL_ADC_RESOLUTION_8B,\n  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)\n  *            );\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \\\n  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Helper macro to get the ADC multimode conversion data of ADC master\n  *         or ADC slave from raw value with both ADC conversion data concatenated.\n  * @note   This macro is intended to be used when multimode transfer by DMA\n  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().\n  *         In this case the transferred data need to processed with this macro\n  *         to separate the conversion data of ADC master and ADC slave.\n  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_MASTER\n  *         @arg @ref LL_ADC_MULTI_SLAVE\n  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \\\n  (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)\n#endif\n\n/**\n  * @brief  Helper macro to select the ADC common instance\n  *         to which is belonging the selected ADC instance.\n  * @note   ADC common register instance can be used for:\n  *         - Set parameters common to several ADC instances\n  *         - Multimode (for devices with several ADC instances)\n  *         Refer to functions having argument \"ADCxy_COMMON\" as parameter.\n  * @param  __ADCx__ ADC instance\n  * @retval ADC common register instance\n  */\n#if defined(ADC1) && defined(ADC2) && defined(ADC3)\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC123_COMMON)\n#elif defined(ADC1) && defined(ADC2)\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC12_COMMON)\n#else\n#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \\\n  (ADC1_COMMON)\n#endif\n\n/**\n  * @brief  Helper macro to check if all ADC instances sharing the same\n  *         ADC common instance are disabled.\n  * @note   This check is required by functions with setting conditioned to\n  *         ADC state:\n  *         All ADC instances of the ADC common group must be disabled.\n  *         Refer to functions having argument \"ADCxy_COMMON\" as parameter.\n  * @note   On devices with only 1 ADC common instance, parameter of this macro\n  *         is useless and can be ignored (parameter kept for compatibility\n  *         with devices featuring several ADC common instances).\n  * @param  __ADCXY_COMMON__ ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Value \"0\" if all ADC instances sharing the same ADC common instance\n  *         are disabled.\n  *         Value \"1\" if at least one ADC instance sharing the same ADC common instance\n  *         is enabled.\n  */\n#if defined(ADC1) && defined(ADC2) && defined(ADC3)\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1) |                                                    \\\n   LL_ADC_IsEnabled(ADC2) |                                                    \\\n   LL_ADC_IsEnabled(ADC3)  )\n#elif defined(ADC1) && defined(ADC2)\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1) |                                                    \\\n   LL_ADC_IsEnabled(ADC2)  )\n#else\n#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \\\n  (LL_ADC_IsEnabled(ADC1))\n#endif\n\n/**\n  * @brief  Helper macro to define the ADC conversion data full-scale digital\n  *         value corresponding to the selected ADC resolution.\n  * @note   ADC conversion data full-scale corresponds to voltage range\n  *         determined by analog voltage references Vref+ and Vref-\n  *         (refer to reference manual).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data equivalent voltage value (unit: mVolt)\n  */\n#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \\\n  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))\n\n/**\n  * @brief  Helper macro to convert the ADC conversion data from\n  *         a resolution to another resolution.\n  * @param  __DATA__ ADC conversion data to be converted \n  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data to the requested resolution\n  */\n#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \\\n  (((__DATA__)                                                                 \\\n    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))     \\\n   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))        \\\n  )\n\n/**\n  * @brief  Helper macro to calculate the voltage (unit: mVolt)\n  *         corresponding to a ADC conversion data (unit: digital value).\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV)\n  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)\n  *                       (unit: digital value).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval ADC conversion data equivalent voltage value (unit: mVolt)\n  */\n#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\\\n                                      __ADC_DATA__,\\\n                                      __ADC_RESOLUTION__)                      \\\n  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \\\n   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \\\n  )\n\n/**\n  * @brief  Helper macro to calculate analog reference voltage (Vref+)\n  *         (unit: mVolt) from ADC conversion data of internal voltage\n  *         reference VrefInt.\n  * @note   Computation is using VrefInt calibration value\n  *         stored in system memory for each device during production.\n  * @note   This voltage depends on user board environment: voltage level\n  *         connected to pin Vref+.\n  *         On devices with small package, the pin Vref+ is not present\n  *         and internally bonded to pin Vdda.\n  * @note   On this STM32 series, calibration data of internal voltage reference\n  *         VrefInt corresponds to a resolution of 12 bits,\n  *         this is the recommended ADC resolution to convert voltage of\n  *         internal voltage reference VrefInt.\n  *         Otherwise, this macro performs the processing to scale\n  *         ADC conversion data to 12 bits.\n  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)\n  *         of internal voltage reference VrefInt (unit: digital value).\n  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Analog reference voltage (unit: mV)\n  */\n#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\\\n                                         __ADC_RESOLUTION__)                   \\\n  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \\\n   / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \\\n                                      (__ADC_RESOLUTION__),                    \\\n                                      LL_ADC_RESOLUTION_12B))\n\n/* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */\n/*       Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/\n/*       Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().        */\n#if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)\n/**\n  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)\n  *         from ADC conversion data of internal temperature sensor.\n  * @note   Computation is using temperature sensor calibration values\n  *         stored in system memory for each device during production.\n  * @note   Calculation formula:\n  *           Temperature = ((TS_ADC_DATA - TS_CAL1)\n  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))\n  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP\n  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC\n  *                Avg_Slope = (TS_CAL2 - TS_CAL1)\n  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)\n  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature\n  *                            TEMP_DEGC_CAL1 (calibrated in factory)\n  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature\n  *                            TEMP_DEGC_CAL2 (calibrated in factory)\n  *         Caution: Calculation relevancy under reserve that calibration\n  *                  parameters are correct (address and data).\n  *                  To calculate temperature using temperature sensor\n  *                  datasheet typical values (generic values less, therefore\n  *                  less accurate than calibrated values),\n  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().\n  * @note   As calculation input, the analog reference voltage (Vref+) must be\n  *         defined as it impacts the ADC LSB equivalent voltage.\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @note   On this STM32 series, calibration data of temperature sensor\n  *         corresponds to a resolution of 12 bits,\n  *         this is the recommended ADC resolution to convert voltage of\n  *         temperature sensor.\n  *         Otherwise, this macro performs the processing to scale\n  *         ADC conversion data to 12 bits.\n  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit mV)\n  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal\n  *                                 temperature sensor (unit: digital value).\n  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature\n  *                                 sensor voltage has been measured.\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Temperature (unit: degree Celsius)\n  */\n#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\\\n                                  __TEMPSENSOR_ADC_DATA__,\\\n                                  __ADC_RESOLUTION__)                              \\\n  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \\\n                                                    (__ADC_RESOLUTION__),          \\\n                                                    LL_ADC_RESOLUTION_12B)         \\\n                   * (__VREFANALOG_VOLTAGE__))                                     \\\n                  / TEMPSENSOR_CAL_VREFANALOG)                                     \\\n        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \\\n     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \\\n    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \\\n   ) + TEMPSENSOR_CAL1_TEMP                                                        \\\n  )\n#endif\n\n/**\n  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)\n  *         from ADC conversion data of internal temperature sensor.\n  * @note   Computation is using temperature sensor typical values\n  *         (refer to device datasheet).\n  * @note   Calculation formula:\n  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)\n  *                         / Avg_Slope + CALx_TEMP\n  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC\n  *                                   (unit: digital value)\n  *                Avg_Slope        = temperature sensor slope\n  *                                   (unit: uV/Degree Celsius)\n  *                TS_TYP_CALx_VOLT = temperature sensor digital value at\n  *                                   temperature CALx_TEMP (unit: mV)\n  *         Caution: Calculation relevancy under reserve the temperature sensor\n  *                  of the current device has characteristics in line with\n  *                  datasheet typical values.\n  *                  If temperature sensor calibration values are available on\n  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),\n  *                  temperature calculation will be more accurate using\n  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().\n  * @note   As calculation input, the analog reference voltage (Vref+) must be\n  *         defined as it impacts the ADC LSB equivalent voltage.\n  * @note   Analog reference voltage (Vref+) must be either known from\n  *         user board environment or can be calculated using ADC measurement\n  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().\n  * @note   ADC measurement data must correspond to a resolution of 12bits\n  *         (full scale digital value 4095). If not the case, the data must be\n  *         preliminarily rescaled to an equivalent resolution of 12 bits.\n  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius).\n  *                                       On STM32F4, refer to device datasheet parameter \"Avg_Slope\".\n  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV).\n  *                                       On STM32F4, refer to device datasheet parameter \"V25\".\n  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV)\n  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit mV)\n  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit digital value).\n  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.\n  *         This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval Temperature (unit: degree Celsius)\n  */\n#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\\\n                                             __TEMPSENSOR_TYP_CALX_V__,\\\n                                             __TEMPSENSOR_CALX_TEMP__,\\\n                                             __VREFANALOG_VOLTAGE__,\\\n                                             __TEMPSENSOR_ADC_DATA__,\\\n                                             __ADC_RESOLUTION__)               \\\n  ((( (                                                                        \\\n       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \\\n                 * 1000)                                                       \\\n       -                                                                       \\\n       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \\\n                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \\\n                 * 1000)                                                       \\\n      )                                                                        \\\n    ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \\\n   ) + (__TEMPSENSOR_CALX_TEMP__)                                              \\\n  )\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions\n  * @{\n  */\n\n/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management\n  * @{\n  */\n/* Note: LL ADC functions to set DMA transfer are located into sections of    */\n/*       configuration of ADC instance, groups and multimode (if available):  */\n/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */\n\n/**\n  * @brief  Function to help to configure DMA transfer from ADC: retrieve the\n  *         ADC register address from ADC instance and a list of ADC registers\n  *         intended to be used (most commonly) with DMA transfer.\n  * @note   These ADC registers are data registers:\n  *         when ADC conversion data is available in ADC data registers,\n  *         ADC generates a DMA transfer request.\n  * @note   This macro is intended to be used with LL DMA driver, refer to\n  *         function \"LL_DMA_ConfigAddresses()\".\n  *         Example:\n  *           LL_DMA_ConfigAddresses(DMA1,\n  *                                  LL_DMA_CHANNEL_1,\n  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),\n  *                                  (uint32_t)&< array or variable >,\n  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);\n  * @note   For devices with several ADC: in multimode, some devices\n  *         use a different data register outside of ADC instance scope\n  *         (common data register). This macro manages this register difference,\n  *         only ADC instance has to be set as parameter.\n  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\\n\n  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\\n\n  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr\n  * @param  ADCx ADC instance\n  * @param  Register This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA\n  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)\n  *         \n  *         (1) Available on devices with several ADC instances.\n  * @retval ADC register address\n  */\n#if defined(ADC_MULTIMODE_SUPPORT)\n__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)\n{\n  uint32_t data_reg_addr = 0UL;\n  \n  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)\n  {\n    /* Retrieve address of register DR */\n    data_reg_addr = (uint32_t)&(ADCx->DR);\n  }\n  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */\n  {\n    /* Retrieve address of register CDR */\n    data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);\n  }\n  \n  return data_reg_addr;\n}\n#else\n__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)\n{\n  /* Retrieve address of register DR */\n  return (uint32_t)&(ADCx->DR);\n}\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances\n  * @{\n  */\n\n/**\n  * @brief  Set parameter common to several ADC: Clock source and prescaler.\n  * @rmtoll CCR      ADCPRE         LL_ADC_SetCommonClock\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  CommonClock This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);\n}\n\n/**\n  * @brief  Get parameter common to several ADC: Clock source and prescaler.\n  * @rmtoll CCR      ADCPRE         LL_ADC_GetCommonClock\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6\n  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));\n}\n\n/**\n  * @brief  Set parameter common to several ADC: measurement path to internal\n  *         channels (VrefInt, temperature sensor, ...).\n  * @note   One or several values can be selected.\n  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |\n  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)\n  * @note   Stabilization time of measurement path to internal channel:\n  *         After enabling internal paths, before starting ADC conversion,\n  *         a delay is required for internal voltage reference and\n  *         temperature sensor stabilization time.\n  *         Refer to device datasheet.\n  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.\n  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.\n  * @note   ADC internal channel sampling time constraint:\n  *         For ADC conversion of internal channels,\n  *         a sampling time minimum value is required.\n  *         Refer to device datasheet.\n  * @rmtoll CCR      TSVREFE        LL_ADC_SetCommonPathInternalCh\\n\n  *         CCR      VBATE          LL_ADC_SetCommonPathInternalCh\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  PathInternal This parameter can be a combination of the following values:\n  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\n  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);\n}\n\n/**\n  * @brief  Get parameter common to several ADC: measurement path to internal\n  *         channels (VrefInt, temperature sensor, ...).\n  * @note   One or several values can be selected.\n  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |\n  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)\n  * @rmtoll CCR      TSVREFE        LL_ADC_GetCommonPathInternalCh\\n\n  *         CCR      VBATE          LL_ADC_GetCommonPathInternalCh\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be a combination of the following values:\n  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT\n  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR\n  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance\n  * @{\n  */\n\n/**\n  * @brief  Set ADC resolution.\n  *         Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CR1      RES            LL_ADC_SetResolution\n  * @param  ADCx ADC instance\n  * @param  Resolution This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)\n{\n  MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);\n}\n\n/**\n  * @brief  Get ADC resolution.\n  *         Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CR1      RES            LL_ADC_GetResolution\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_RESOLUTION_12B\n  *         @arg @ref LL_ADC_RESOLUTION_10B\n  *         @arg @ref LL_ADC_RESOLUTION_8B\n  *         @arg @ref LL_ADC_RESOLUTION_6B\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));\n}\n\n/**\n  * @brief  Set ADC conversion data alignment.\n  * @note   Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment\n  * @param  ADCx ADC instance\n  * @param  DataAlignment This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT\n  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)\n{\n  MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);\n}\n\n/**\n  * @brief  Get ADC conversion data alignment.\n  * @note   Refer to reference manual for alignments formats\n  *         dependencies to ADC resolutions.\n  * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT\n  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));\n}\n\n/**\n  * @brief  Set ADC sequencers scan mode, for all ADC groups\n  *         (group regular, group injected).\n  * @note  According to sequencers scan mode :\n  *         - If disabled: ADC conversion is performed in unitary conversion\n  *           mode (one channel converted, that defined in rank 1).\n  *           Configuration of sequencers of all ADC groups\n  *           (sequencer scan length, ...) is discarded: equivalent to\n  *           scan length of 1 rank.\n  *         - If enabled: ADC conversions are performed in sequence conversions\n  *           mode, according to configuration of sequencers of\n  *           each ADC group (sequencer scan length, ...).\n  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()\n  *           and to function @ref LL_ADC_INJ_SetSequencerLength().\n  * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode\n  * @param  ADCx ADC instance\n  * @param  ScanMode This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)\n{\n  MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);\n}\n\n/**\n  * @brief  Get ADC sequencers scan mode, for all ADC groups\n  *         (group regular, group injected).\n  * @note  According to sequencers scan mode :\n  *         - If disabled: ADC conversion is performed in unitary conversion\n  *           mode (one channel converted, that defined in rank 1).\n  *           Configuration of sequencers of all ADC groups\n  *           (sequencer scan length, ...) is discarded: equivalent to\n  *           scan length of 1 rank.\n  *         - If enabled: ADC conversions are performed in sequence conversions\n  *           mode, according to configuration of sequencers of\n  *           each ADC group (sequencer scan length, ...).\n  *           Refer to function @ref LL_ADC_REG_SetSequencerLength()\n  *           and to function @ref LL_ADC_INJ_SetSequencerLength().\n  * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular\n  * @{\n  */\n\n/**\n  * @brief  Set ADC group regular conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   On this STM32 series, setting of external trigger edge is performed\n  *         using function @ref LL_ADC_REG_StartConversionExtTrig().\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource\\n\n  *         CR2      EXTEN          LL_ADC_REG_SetTriggerSource\n  * @param  ADCx ADC instance\n  * @param  TriggerSource This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n/* Note: On this STM32 series, ADC group regular external trigger edge        */\n/*       is used to perform a ADC conversion start.                           */\n/*       This function does not set external trigger edge.                    */\n/*       This feature is set using function                                   */\n/*       @ref LL_ADC_REG_StartConversionExtTrig().                            */\n  MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   To determine whether group regular trigger source is\n  *         internal (SW start) or external, without detail\n  *         of which peripheral is selected as external trigger,\n  *         (equivalent to \n  *         \"if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)\")\n  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource\\n\n  *         CR2      EXTEN          LL_ADC_REG_GetTriggerSource\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)\n{\n  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);\n  \n  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */\n  /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}.                             */\n  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));\n  \n  /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL           */\n  /* to match with triggers literals definition.                              */\n  return ((TriggerSource\n           & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)\n          | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)\n         );\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger source internal (SW start)\n            or external.\n  * @note   In case of group regular trigger source set to external trigger,\n  *         to determine which peripheral is selected as external trigger,\n  *         use function @ref LL_ADC_REG_GetTriggerSource().\n  * @rmtoll CR2      EXTEN          LL_ADC_REG_IsTriggerSourceSWStart\n  * @param  ADCx ADC instance\n  * @retval Value \"0\" if trigger source external trigger\n  *         Value \"1\" if trigger source SW start.\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));\n}\n\n/**\n  * @brief  Get ADC group regular conversion trigger polarity.\n  * @note   Applicable only for trigger source set to external trigger.\n  * @note   On this STM32 series, setting of external trigger edge is performed\n  *         using function @ref LL_ADC_REG_StartConversionExtTrig().\n  * @rmtoll CR2      EXTEN          LL_ADC_REG_GetTriggerEdge\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));\n}\n\n\n/**\n  * @brief  Set ADC group regular sequencer length and scan direction.\n  * @note   Description of ADC group regular sequencer features:\n  *         - For devices with sequencer fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerRanks()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are configurable.\n  *           This function performs configuration of:\n  *           - Sequence length: Number of ranks in the scan sequence.\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from rank 1 to rank n).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerRanks()\".\n  *         - For devices with sequencer not fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerChannels()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are defined by channel number.\n  *           This function performs configuration of:\n  *           - Sequence length: Number of ranks in the scan sequence is\n  *             defined by number of channels set in the sequence,\n  *             rank of each channel is fixed by channel HW number.\n  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from lowest channel number to\n  *             highest channel number).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerChannels()\".\n  * @note   On this STM32 series, group regular sequencer configuration\n  *         is conditioned to ADC instance sequencer mode.\n  *         If ADC instance sequencer mode is disabled, sequencers of\n  *         all groups (group regular, group injected) can be configured\n  *         but their execution is disabled (limited to rank 1).\n  *         Refer to function @ref LL_ADC_SetSequencersScanMode().\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength\n  * @param  ADCx ADC instance\n  * @param  SequencerNbRanks This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\n{\n  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);\n}\n\n/**\n  * @brief  Get ADC group regular sequencer length and scan direction.\n  * @note   Description of ADC group regular sequencer features:\n  *         - For devices with sequencer fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerRanks()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are configurable.\n  *           This function retrieves:\n  *           - Sequence length: Number of ranks in the scan sequence.\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from rank 1 to rank n).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerRanks()\".\n  *         - For devices with sequencer not fully configurable\n  *           (function \"LL_ADC_REG_SetSequencerChannels()\" available):\n  *           sequencer length and each rank affectation to a channel\n  *           are defined by channel number.\n  *           This function retrieves:\n  *           - Sequence length: Number of ranks in the scan sequence is\n  *             defined by number of channels set in the sequence,\n  *             rank of each channel is fixed by channel HW number.\n  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).\n  *           - Sequence direction: Unless specified in parameters, sequencer\n  *             scan direction is forward (from lowest channel number to\n  *             highest channel number).\n  *           Sequencer ranks are selected using\n  *           function \"LL_ADC_REG_SetSequencerChannels()\".\n  * @note   On this STM32 series, group regular sequencer configuration\n  *         is conditioned to ADC instance sequencer mode.\n  *         If ADC instance sequencer mode is disabled, sequencers of\n  *         all groups (group regular, group injected) can be configured\n  *         but their execution is disabled (limited to rank 1).\n  *         Refer to function @ref LL_ADC_SetSequencersScanMode().\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));\n}\n\n/**\n  * @brief  Set ADC group regular sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @note   It is not possible to enable both ADC group regular \n  *         continuous mode and sequencer discontinuous mode.\n  * @note   It is not possible to enable both ADC auto-injected mode\n  *         and ADC group regular sequencer discontinuous mode.\n  * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\\n\n  *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @param  SeqDiscont This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\n{\n  MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);\n}\n\n/**\n  * @brief  Get ADC group regular sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\\n\n  *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS\n  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));\n}\n\n/**\n  * @brief  Set ADC group regular sequence: channel on the selected\n  *         scan sequence rank.\n  * @note   This function performs configuration of:\n  *         - Channels ordering into each rank of scan sequence:\n  *           whatever channel can be placed into whatever rank.\n  * @note   On this STM32 series, ADC group regular sequencer is\n  *         fully configurable: sequencer length and each rank\n  *         affectation to a channel are configurable.\n  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   On this STM32 series, to measure internal channels (VrefInt,\n  *         TempSensor, ...), measurement paths to internal channels must be\n  *         enabled separately.\n  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\n  * @rmtoll SQR3     SQ1            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ2            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ3            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ4            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ5            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR3     SQ6            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ10           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ11           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR2     SQ12           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ13           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ14           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ15           LL_ADC_REG_SetSequencerRanks\\n\n  *         SQR1     SQ16           LL_ADC_REG_SetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_RANK_1\n  *         @arg @ref LL_ADC_REG_RANK_2\n  *         @arg @ref LL_ADC_REG_RANK_3\n  *         @arg @ref LL_ADC_REG_RANK_4\n  *         @arg @ref LL_ADC_REG_RANK_5\n  *         @arg @ref LL_ADC_REG_RANK_6\n  *         @arg @ref LL_ADC_REG_RANK_7\n  *         @arg @ref LL_ADC_REG_RANK_8\n  *         @arg @ref LL_ADC_REG_RANK_9\n  *         @arg @ref LL_ADC_REG_RANK_10\n  *         @arg @ref LL_ADC_REG_RANK_11\n  *         @arg @ref LL_ADC_REG_RANK_12\n  *         @arg @ref LL_ADC_REG_RANK_13\n  *         @arg @ref LL_ADC_REG_RANK_14\n  *         @arg @ref LL_ADC_REG_RANK_15\n  *         @arg @ref LL_ADC_REG_RANK_16\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\n{\n  /* Set bits with content of parameter \"Channel\" with bits position          */\n  /* in register and register position depending on parameter \"Rank\".         */\n  /* Parameters \"Rank\" and \"Channel\" are used with masks because containing   */\n  /* other bits reserved for other purpose.                                   */\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));\n  \n  MODIFY_REG(*preg,\n             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),\n             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));\n}\n\n/**\n  * @brief  Get ADC group regular sequence: channel on the selected\n  *         scan sequence rank.\n  * @note   On this STM32 series, ADC group regular sequencer is\n  *         fully configurable: sequencer length and each rank\n  *         affectation to a channel are configurable.\n  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  * @rmtoll SQR3     SQ1            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ2            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ3            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ4            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ5            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR3     SQ6            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ10           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ11           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR2     SQ12           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ13           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ14           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ15           LL_ADC_REG_GetSequencerRanks\\n\n  *         SQR1     SQ16           LL_ADC_REG_GetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_RANK_1\n  *         @arg @ref LL_ADC_REG_RANK_2\n  *         @arg @ref LL_ADC_REG_RANK_3\n  *         @arg @ref LL_ADC_REG_RANK_4\n  *         @arg @ref LL_ADC_REG_RANK_5\n  *         @arg @ref LL_ADC_REG_RANK_6\n  *         @arg @ref LL_ADC_REG_RANK_7\n  *         @arg @ref LL_ADC_REG_RANK_8\n  *         @arg @ref LL_ADC_REG_RANK_9\n  *         @arg @ref LL_ADC_REG_RANK_10\n  *         @arg @ref LL_ADC_REG_RANK_11\n  *         @arg @ref LL_ADC_REG_RANK_12\n  *         @arg @ref LL_ADC_REG_RANK_13\n  *         @arg @ref LL_ADC_REG_RANK_14\n  *         @arg @ref LL_ADC_REG_RANK_15\n  *         @arg @ref LL_ADC_REG_RANK_16\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\\n\n  *         (1) For ADC channel read back from ADC register,\n  *             comparison with internal channel parameter to be done\n  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));\n  \n  return (uint32_t) (READ_BIT(*preg,\n                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))\n                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)\n                    );\n}\n\n/**\n  * @brief  Set ADC continuous conversion mode on ADC group regular.\n  * @note   Description of ADC continuous conversion mode:\n  *         - single mode: one conversion per trigger\n  *         - continuous mode: after the first trigger, following\n  *           conversions launched successively automatically.\n  * @note   It is not possible to enable both ADC group regular \n  *         continuous mode and sequencer discontinuous mode.\n  * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode\n  * @param  ADCx ADC instance\n  * @param  Continuous This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_CONV_SINGLE\n  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)\n{\n  MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);\n}\n\n/**\n  * @brief  Get ADC continuous conversion mode on ADC group regular.\n  * @note   Description of ADC continuous conversion mode:\n  *         - single mode: one conversion per trigger\n  *         - continuous mode: after the first trigger, following\n  *           conversions launched successively automatically.\n  * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_CONV_SINGLE\n  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));\n}\n\n/**\n  * @brief  Set ADC group regular conversion data transfer: no transfer or\n  *         transfer by DMA, and DMA requests mode.\n  * @note   If transfer by DMA selected, specifies the DMA requests\n  *         mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *        (overrun flag and interruption if enabled).\n  * @note   For devices with several ADC instances: ADC multimode DMA\n  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().\n  * @note   To configure DMA source address (peripheral address),\n  *         use function @ref LL_ADC_DMA_GetRegAddr().\n  * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer\\n\n  *         CR2      DDS            LL_ADC_REG_SetDMATransfer\n  * @param  ADCx ADC instance\n  * @param  DMATransfer This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)\n{\n  MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);\n}\n\n/**\n  * @brief  Get ADC group regular conversion data transfer: no transfer or\n  *         transfer by DMA, and DMA requests mode.\n  * @note   If transfer by DMA selected, specifies the DMA requests\n  *         mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   For devices with several ADC instances: ADC multimode DMA\n  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().\n  * @note   To configure DMA source address (peripheral address),\n  *         use function @ref LL_ADC_DMA_GetRegAddr().\n  * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer\\n\n  *         CR2      DDS            LL_ADC_REG_GetDMATransfer\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED\n  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));\n}\n\n/**\n  * @brief  Specify which ADC flag between EOC (end of unitary conversion)\n  *         or EOS (end of sequence conversions) is used to indicate\n  *         the end of conversion.\n  * @note   This feature is aimed to be set when using ADC with\n  *         programming model by polling or interruption\n  *         (programming model by DMA usually uses DMA interruptions\n  *         to indicate end of conversion and data transfer).\n  * @note   For ADC group injected, end of conversion (flag&IT) is raised\n  *         only at the end of the sequence.\n  * @rmtoll CR2      EOCS           LL_ADC_REG_SetFlagEndOfConversion\n  * @param  ADCx ADC instance\n  * @param  EocSelection This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV\n  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)\n{\n  MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);\n}\n\n/**\n  * @brief  Get which ADC flag between EOC (end of unitary conversion)\n  *         or EOS (end of sequence conversions) is used to indicate\n  *         the end of conversion.\n  * @rmtoll CR2      EOCS           LL_ADC_REG_GetFlagEndOfConversion\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV\n  *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected\n  * @{\n  */\n\n/**\n  * @brief  Set ADC group injected conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   On this STM32 series, setting of external trigger edge is performed\n  *         using function @ref LL_ADC_INJ_StartConversionExtTrig().\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource\\n\n  *         CR2      JEXTEN         LL_ADC_INJ_SetTriggerSource\n  * @param  ADCx ADC instance\n  * @param  TriggerSource This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)\n{\n/* Note: On this STM32 series, ADC group injected external trigger edge       */\n/*       is used to perform a ADC conversion start.                           */\n/*       This function does not set external trigger edge.                    */\n/*       This feature is set using function                                   */\n/*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */\n  MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger source:\n  *         internal (SW start) or from external IP (timer event,\n  *         external interrupt line).\n  * @note   To determine whether group injected trigger source is\n  *         internal (SW start) or external, without detail\n  *         of which peripheral is selected as external trigger,\n  *         (equivalent to \n  *         \"if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)\")\n  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.\n  * @note   Availability of parameters of trigger sources from timer \n  *         depends on timers availability on the selected device.\n  * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource\\n\n  *         CR2      JEXTEN         LL_ADC_INJ_GetTriggerSource\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)\n{\n  uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);\n  \n  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */\n  /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}.                            */\n  uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));\n  \n  /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL         */\n  /* to match with triggers literals definition.                              */\n  return ((TriggerSource\n           & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)\n          | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)\n         );\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger source internal (SW start)\n            or external\n  * @note   In case of group injected trigger source set to external trigger,\n  *         to determine which peripheral is selected as external trigger,\n  *         use function @ref LL_ADC_INJ_GetTriggerSource.\n  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart\n  * @param  ADCx ADC instance\n  * @retval Value \"0\" if trigger source external trigger\n  *         Value \"1\" if trigger source SW start.\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger polarity.\n  *         Applicable only for trigger source set to external trigger.\n  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_GetTriggerEdge\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));\n}\n\n/**\n  * @brief  Set ADC group injected sequencer length and scan direction.\n  * @note   This function performs configuration of:\n  *         - Sequence length: Number of ranks in the scan sequence.\n  *         - Sequence direction: Unless specified in parameters, sequencer\n  *           scan direction is forward (from rank 1 to rank n).\n  * @note   On this STM32 series, group injected sequencer configuration\n  *         is conditioned to ADC instance sequencer mode.\n  *         If ADC instance sequencer mode is disabled, sequencers of\n  *         all groups (group regular, group injected) can be configured\n  *         but their execution is disabled (limited to rank 1).\n  *         Refer to function @ref LL_ADC_SetSequencersScanMode().\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength\n  * @param  ADCx ADC instance\n  * @param  SequencerNbRanks This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)\n{\n  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);\n}\n\n/**\n  * @brief  Get ADC group injected sequencer length and scan direction.\n  * @note   This function retrieves:\n  *         - Sequence length: Number of ranks in the scan sequence.\n  *         - Sequence direction: Unless specified in parameters, sequencer\n  *           scan direction is forward (from rank 1 to rank n).\n  * @note   On this STM32 series, group injected sequencer configuration\n  *         is conditioned to ADC instance sequencer mode.\n  *         If ADC instance sequencer mode is disabled, sequencers of\n  *         all groups (group regular, group injected) can be configured\n  *         but their execution is disabled (limited to rank 1).\n  *         Refer to function @ref LL_ADC_SetSequencersScanMode().\n  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:\n  *         ADC conversion on only 1 channel.\n  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS\n  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));\n}\n\n/**\n  * @brief  Set ADC group injected sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @note   It is not possible to enable both ADC group injected\n  *         auto-injected mode and sequencer discontinuous mode.\n  * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @param  SeqDiscont This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)\n{\n  MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);\n}\n\n/**\n  * @brief  Get ADC group injected sequencer discontinuous mode:\n  *         sequence subdivided and scan conversions interrupted every selected\n  *         number of ranks.\n  * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE\n  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));\n}\n\n/**\n  * @brief  Set ADC group injected sequence: channel on the selected\n  *         sequence rank.\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   On this STM32 series, to measure internal channels (VrefInt,\n  *         TempSensor, ...), measurement paths to internal channels must be\n  *         enabled separately.\n  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().\n  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)\n{\n  /* Set bits with content of parameter \"Channel\" with bits position          */\n  /* in register depending on parameter \"Rank\".                               */\n  /* Parameters \"Rank\" and \"Channel\" are used with masks because containing   */\n  /* other bits reserved for other purpose.                                   */\n  uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;\n  \n  MODIFY_REG(ADCx->JSQR,\n             ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),\n             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));\n}\n\n/**\n  * @brief  Get ADC group injected sequence: channel on the selected\n  *         sequence rank.\n  * @note   Depending on devices and packages, some channels may not be available.\n  *         Refer to device datasheet for channels availability.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\\n\n  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\\n\n  *         (1) For ADC channel read back from ADC register,\n  *             comparison with internal channel parameter to be done\n  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos)  + 1UL;\n  \n  return (uint32_t)(READ_BIT(ADCx->JSQR,\n                             ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))\n                    >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))\n                   );\n}\n\n/**\n  * @brief  Set ADC group injected conversion trigger:\n  *         independent or from ADC group regular.\n  * @note   This mode can be used to extend number of data registers\n  *         updated after one ADC conversion trigger and with data \n  *         permanently kept (not erased by successive conversions of scan of\n  *         ADC sequencer ranks), up to 5 data registers:\n  *         1 data register on ADC group regular, 4 data registers\n  *         on ADC group injected.            \n  * @note   If ADC group injected injected trigger source is set to an\n  *         external trigger, this feature must be must be set to\n  *         independent trigger.\n  *         ADC group injected automatic trigger is compliant only with \n  *         group injected trigger source set to SW start, without any \n  *         further action on  ADC group injected conversion start or stop: \n  *         in this case, ADC group injected is controlled only \n  *         from ADC group regular.\n  * @note   It is not possible to enable both ADC group injected\n  *         auto-injected mode and sequencer discontinuous mode.\n  * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto\n  * @param  ADCx ADC instance\n  * @param  TrigAuto This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\n  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)\n{\n  MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);\n}\n\n/**\n  * @brief  Get ADC group injected conversion trigger:\n  *         independent or from ADC group regular.\n  * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT\n  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));\n}\n\n/**\n  * @brief  Set ADC group injected offset.\n  * @note   It sets:\n  *         - ADC group injected rank to which the offset programmed\n  *           will be applied\n  *         - Offset level (offset to be subtracted from the raw\n  *           converted data).\n  *         Caution: Offset format is dependent to ADC resolution:\n  *         offset has to be left-aligned on bit 11, the LSB (right bits)\n  *         are set to 0.\n  * @note   Offset cannot be enabled or disabled.\n  *         To emulate offset disabled, set an offset value equal to 0.\n  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\\n\n  *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\\n\n  *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\\n\n  *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));\n  \n  MODIFY_REG(*preg,\n             ADC_JOFR1_JOFFSET1,\n             OffsetLevel);\n}\n\n/**\n  * @brief  Get ADC group injected offset.\n  * @note   It gives offset level (offset to be subtracted from the raw converted data).\n  *         Caution: Offset format is dependent to ADC resolution:\n  *         offset has to be left-aligned on bit 11, the LSB (right bits)\n  *         are set to 0.\n  * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\\n\n  *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\\n\n  *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\\n\n  *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_JOFR1_JOFFSET1)\n                   );\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels\n  * @{\n  */\n\n/**\n  * @brief  Set sampling time of the selected ADC channel\n  *         Unit: ADC clock cycles.\n  * @note   On this device, sampling time is on channel scope: independently\n  *         of channel mapped on ADC group regular or injected.\n  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be\n  *         converted:\n  *         sampling time constraints must be respected (sampling time can be\n  *         adjusted in function of ADC clock frequency and sampling time\n  *         setting).\n  *         Refer to device datasheet for timings values (parameters TS_vrefint,\n  *         TS_temp, ...).\n  * @note   Conversion time is the addition of sampling time and processing time.\n  *         Refer to reference manual for ADC processing time of\n  *         this STM32 series.\n  * @note   In case of ADC conversion of internal channel (VrefInt,\n  *         temperature sensor, ...), a sampling time minimum value\n  *         is required.\n  *         Refer to device datasheet.\n  * @rmtoll SMPR1    SMP18          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP17          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP16          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP15          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP14          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP13          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP12          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP11          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR1    SMP10          LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP9           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP8           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP7           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP6           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP5           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP4           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP3           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP2           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP1           LL_ADC_SetChannelSamplingTime\\n\n  *         SMPR2    SMP0           LL_ADC_SetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @param  SamplingTime This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)\n{\n  /* Set bits with content of parameter \"SamplingTime\" with bits position     */\n  /* in register and register position depending on parameter \"Channel\".      */\n  /* Parameter \"Channel\" is used with masks because containing                */\n  /* other bits reserved for other purpose.                                   */\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));\n  \n  MODIFY_REG(*preg,\n             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),\n             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));\n}\n\n/**\n  * @brief  Get sampling time of the selected ADC channel\n  *         Unit: ADC clock cycles.\n  * @note   On this device, sampling time is on channel scope: independently\n  *         of channel mapped on ADC group regular or injected.\n  * @note   Conversion time is the addition of sampling time and processing time.\n  *         Refer to reference manual for ADC processing time of\n  *         this STM32 series.\n  * @rmtoll SMPR1    SMP18          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP17          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP16          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP15          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP14          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP13          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP12          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP11          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR1    SMP10          LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP9           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP8           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP7           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP6           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP5           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP4           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP3           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP2           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP1           LL_ADC_GetChannelSamplingTime\\n\n  *         SMPR2    SMP0           LL_ADC_GetChannelSamplingTime\n  * @param  ADCx ADC instance\n  * @param  Channel This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_CHANNEL_0\n  *         @arg @ref LL_ADC_CHANNEL_1\n  *         @arg @ref LL_ADC_CHANNEL_2\n  *         @arg @ref LL_ADC_CHANNEL_3\n  *         @arg @ref LL_ADC_CHANNEL_4\n  *         @arg @ref LL_ADC_CHANNEL_5\n  *         @arg @ref LL_ADC_CHANNEL_6\n  *         @arg @ref LL_ADC_CHANNEL_7\n  *         @arg @ref LL_ADC_CHANNEL_8\n  *         @arg @ref LL_ADC_CHANNEL_9\n  *         @arg @ref LL_ADC_CHANNEL_10\n  *         @arg @ref LL_ADC_CHANNEL_11\n  *         @arg @ref LL_ADC_CHANNEL_12\n  *         @arg @ref LL_ADC_CHANNEL_13\n  *         @arg @ref LL_ADC_CHANNEL_14\n  *         @arg @ref LL_ADC_CHANNEL_15\n  *         @arg @ref LL_ADC_CHANNEL_16\n  *         @arg @ref LL_ADC_CHANNEL_17\n  *         @arg @ref LL_ADC_CHANNEL_18\n  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)\n  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)\n  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES\n  *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))\n                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)\n                   );\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog\n  * @{\n  */\n\n/**\n  * @brief  Set ADC analog watchdog monitored channels:\n  *         a single channel or all channels,\n  *         on ADC groups regular and-or injected.\n  * @note   Once monitored channels are selected, analog watchdog\n  *         is enabled.\n  * @note   In case of need to define a single channel to monitor\n  *         with analog watchdog from sequencer channel definition,\n  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().\n  * @note   On this STM32 series, there is only 1 kind of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\\n\n  *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\\n\n  *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n  * @param  ADCx ADC instance\n  * @param  AWDChannelGroup This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)\n  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)\n  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)\n  *         \n  *         (1) On STM32F4, parameter available only on ADC instance: ADC1.\\n\n  *         (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)\n{\n  MODIFY_REG(ADCx->CR1,\n             (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),\n             AWDChannelGroup);\n}\n\n/**\n  * @brief  Get ADC analog watchdog monitored channel.\n  * @note   Usage of the returned channel number:\n  *         - To reinject this channel into another function LL_ADC_xxx:\n  *           the returned channel number is only partly formatted on definition\n  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared\n  *           with parts of literals LL_ADC_CHANNEL_x or using\n  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Then the selected literal LL_ADC_CHANNEL_x can be used\n  *           as parameter for another function.\n  *         - To get the channel number in decimal format:\n  *           process the returned value with the helper macro\n  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().\n  *           Applicable only when the analog watchdog is set to monitor\n  *           one channel.\n  * @note   On this STM32 series, there is only 1 kind of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\\n\n  *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\\n\n  *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n  * @param  ADCx ADC instance\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_DISABLE\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ\n  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ \n  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ\n  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)\n{\n  return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));\n}\n\n/**\n  * @brief  Set ADC analog watchdog threshold value of threshold\n  *         high or low.\n  * @note   In case of ADC resolution different of 12 bits,\n  *         analog watchdog thresholds data require a specific shift.\n  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().\n  * @note   On this STM32 series, there is only 1 kind of analog watchdog\n  *         instance:\n  *         - AWD standard (instance AWD1):\n  *           - channels monitored: can monitor 1 channel or all channels.\n  *           - groups monitored: ADC groups regular and-or injected.\n  *           - resolution: resolution is not limited (corresponds to\n  *             ADC resolution configured).\n  * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\\n\n  *         LTR      LT             LL_ADC_SetAnalogWDThresholds\n  * @param  ADCx ADC instance\n  * @param  AWDThresholdsHighLow This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW\n  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);\n  \n  MODIFY_REG(*preg,\n             ADC_HTR_HT,\n             AWDThresholdValue);\n}\n\n/**\n  * @brief  Get ADC analog watchdog threshold value of threshold high or\n  *         threshold low.\n  * @note   In case of ADC resolution different of 12 bits,\n  *         analog watchdog thresholds data require a specific shift.\n  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().\n  * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\\n\n  *         LTR      LT             LL_ADC_GetAnalogWDThresholds\n  * @param  ADCx ADC instance\n  * @param  AWDThresholdsHighLow This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH\n  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n*/\n__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);\n  \n  return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode\n  * @{\n  */\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Set ADC multimode configuration to operate in independent mode\n  *         or multimode (for devices with several ADC instances).\n  * @note   If multimode configuration: the selected ADC instance is\n  *         either master or slave depending on hardware.\n  *         Refer to reference manual.\n  * @rmtoll CCR      MULTI          LL_ADC_SetMultimode\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  Multimode This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_INDEPENDENT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);\n}\n\n/**\n  * @brief  Get ADC multimode configuration to operate in independent mode\n  *         or multimode (for devices with several ADC instances).\n  * @note   If multimode configuration: the selected ADC instance is\n  *         either master or slave depending on hardware.\n  *         Refer to reference manual.\n  * @rmtoll CCR      MULTI          LL_ADC_GetMultimode\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_INDEPENDENT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL\n  *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));\n}\n\n/**\n  * @brief  Set ADC multimode conversion data transfer: no transfer\n  *         or transfer by DMA.\n  * @note   If ADC multimode transfer by DMA is not selected:\n  *         each ADC uses its own DMA channel, with its individual\n  *         DMA transfer settings.\n  *         If ADC multimode transfer by DMA is selected:\n  *         One DMA channel is used for both ADC (DMA of ADC master)\n  *         Specifies the DMA requests mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   How to retrieve multimode conversion data:\n  *         Whatever multimode transfer by DMA setting: using function\n  *         @ref LL_ADC_REG_ReadMultiConversionData32().\n  *         If ADC multimode transfer by DMA is selected: conversion data\n  *         is a raw data with ADC master and slave concatenated.\n  *         A macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\\n\n  *         CCR      DDS            LL_ADC_SetMultiDMATransfer\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  MultiDMATransfer This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);\n}\n\n/**\n  * @brief  Get ADC multimode conversion data transfer: no transfer\n  *         or transfer by DMA.\n  * @note   If ADC multimode transfer by DMA is not selected:\n  *         each ADC uses its own DMA channel, with its individual\n  *         DMA transfer settings.\n  *         If ADC multimode transfer by DMA is selected:\n  *         One DMA channel is used for both ADC (DMA of ADC master)\n  *         Specifies the DMA requests mode:\n  *         - Limited mode (One shot mode): DMA transfer requests are stopped\n  *           when number of DMA data transfers (number of\n  *           ADC conversions) is reached.\n  *           This ADC mode is intended to be used with DMA mode non-circular.\n  *         - Unlimited mode: DMA transfer requests are unlimited,\n  *           whatever number of DMA data transfers (number of\n  *           ADC conversions).\n  *           This ADC mode is intended to be used with DMA mode circular.\n  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to\n  *         mode non-circular:\n  *         when DMA transfers size will be reached, DMA will stop transfers of\n  *         ADC conversions data ADC will raise an overrun error\n  *         (overrun flag and interruption if enabled).\n  * @note   How to retrieve multimode conversion data:\n  *         Whatever multimode transfer by DMA setting: using function\n  *         @ref LL_ADC_REG_ReadMultiConversionData32().\n  *         If ADC multimode transfer by DMA is selected: conversion data\n  *         is a raw data with ADC master and slave concatenated.\n  *         A macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\\n\n  *         CCR      DDS            LL_ADC_GetMultiDMATransfer\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2\n  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));\n}\n\n/**\n  * @brief  Set ADC multimode delay between 2 sampling phases.\n  * @note   The sampling delay range depends on ADC resolution:\n  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.\n  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.\n  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.\n  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.\n  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)\n{\n  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);\n}\n\n/**\n  * @brief  Get ADC multimode delay between 2 sampling phases.\n  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval Returned value can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES\n  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES\n  */\n__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));\n}\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance\n  * @{\n  */\n\n/**\n  * @brief  Enable the selected ADC instance.\n  * @note   On this STM32 series, after ADC enable, a delay for \n  *         ADC internal analog stabilization is required before performing a\n  *         ADC conversion start.\n  *         Refer to device datasheet, parameter tSTAB.\n  * @rmtoll CR2      ADON           LL_ADC_Enable\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR2, ADC_CR2_ADON);\n}\n\n/**\n  * @brief  Disable the selected ADC instance.\n  * @rmtoll CR2      ADON           LL_ADC_Disable\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);\n}\n\n/**\n  * @brief  Get the selected ADC instance enable state.\n  * @rmtoll CR2      ADON           LL_ADC_IsEnabled\n  * @param  ADCx ADC instance\n  * @retval 0: ADC is disabled, 1: ADC is enabled.\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular\n  * @{\n  */\n\n/**\n  * @brief  Start ADC group regular conversion.\n  * @note   On this STM32 series, this function is relevant only for\n  *         internal trigger (SW start), not for external trigger:\n  *         - If ADC trigger has been set to software start, ADC conversion\n  *           starts immediately.\n  *         - If ADC trigger has been set to external trigger, ADC conversion\n  *           start must be performed using function \n  *           @ref LL_ADC_REG_StartConversionExtTrig().\n  *           (if external trigger edge would have been set during ADC other \n  *           settings, ADC conversion would start at trigger event\n  *           as soon as ADC is enabled).\n  * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);\n}\n\n/**\n  * @brief  Start ADC group regular conversion from external trigger.\n  * @note   ADC conversion will start at next trigger event (on the selected\n  *         trigger edge) following the ADC start conversion command.\n  * @note   On this STM32 series, this function is relevant for \n  *         ADC conversion start from external trigger.\n  *         If internal trigger (SW start) is needed, perform ADC conversion\n  *         start using function @ref LL_ADC_REG_StartConversionSWStart().\n  * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig\n  * @param  ExternalTriggerEdge This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\n{\n  SET_BIT(ADCx->CR2, ExternalTriggerEdge);\n}\n\n/**\n  * @brief  Stop ADC group regular conversion from external trigger.\n  * @note   No more ADC conversion will start at next trigger event\n  *         following the ADC stop conversion command.\n  *         If a conversion is on-going, it will be completed.\n  * @note   On this STM32 series, there is no specific command\n  *         to stop a conversion on-going or to stop ADC converting\n  *         in continuous mode. These actions can be performed\n  *         using function @ref LL_ADC_Disable().\n  * @rmtoll CR2      EXTEN          LL_ADC_REG_StopConversionExtTrig\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         all ADC configurations: all ADC resolutions and\n  *         all oversampling increased data width (for devices\n  *         with feature oversampling).\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 12 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 10 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\n  */\n__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 8 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         ADC resolution 6 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.\n  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6\n  * @param  ADCx ADC instance\n  * @retval Value between Min_Data=0x00 and Max_Data=0x3F\n  */\n__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)\n{\n  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));\n}\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Get ADC multimode conversion data of ADC master, ADC slave\n  *         or raw data with ADC master and slave concatenated.\n  * @note   If raw data with ADC master and slave concatenated is retrieved,\n  *         a macro is available to get the conversion data of\n  *         ADC master or ADC slave: see helper macro\n  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().\n  *         (however this macro is mainly intended for multimode\n  *         transfer by DMA, because this function can do the same\n  *         by getting multimode conversion data of ADC master or ADC slave\n  *         separately).\n  * @rmtoll CDR      DATA1          LL_ADC_REG_ReadMultiConversionData32\\n\n  *         CDR      DATA2          LL_ADC_REG_ReadMultiConversionData32\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  ConversionData This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_MULTI_MASTER\n  *         @arg @ref LL_ADC_MULTI_SLAVE\n  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)\n{\n  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,\n                             ADC_DR_ADC2DATA)\n                    >> POSITION_VAL(ConversionData)\n                   );\n}\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected\n  * @{\n  */\n\n/**\n  * @brief  Start ADC group injected conversion.\n  * @note   On this STM32 series, this function is relevant only for\n  *         internal trigger (SW start), not for external trigger:\n  *         - If ADC trigger has been set to software start, ADC conversion\n  *           starts immediately.\n  *         - If ADC trigger has been set to external trigger, ADC conversion\n  *           start must be performed using function \n  *           @ref LL_ADC_INJ_StartConversionExtTrig().\n  *           (if external trigger edge would have been set during ADC other \n  *           settings, ADC conversion would start at trigger event\n  *           as soon as ADC is enabled).\n  * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);\n}\n\n/**\n  * @brief  Start ADC group injected conversion from external trigger.\n  * @note   ADC conversion will start at next trigger event (on the selected\n  *         trigger edge) following the ADC start conversion command.\n  * @note   On this STM32 series, this function is relevant for \n  *         ADC conversion start from external trigger.\n  *         If internal trigger (SW start) is needed, perform ADC conversion\n  *         start using function @ref LL_ADC_INJ_StartConversionSWStart().\n  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig\n  * @param  ExternalTriggerEdge This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING\n  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)\n{\n  SET_BIT(ADCx->CR2, ExternalTriggerEdge);\n}\n\n/**\n  * @brief  Stop ADC group injected conversion from external trigger.\n  * @note   No more ADC conversion will start at next trigger event\n  *         following the ADC stop conversion command.\n  *         If a conversion is on-going, it will be completed.\n  * @note   On this STM32 series, there is no specific command\n  *         to stop a conversion on-going or to stop ADC converting\n  *         in continuous mode. These actions can be performed\n  *         using function @ref LL_ADC_Disable().\n  * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StopConversionExtTrig\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);\n}\n\n/**\n  * @brief  Get ADC group regular conversion data, range fit for\n  *         all ADC configurations: all ADC resolutions and\n  *         all oversampling increased data width (for devices\n  *         with feature oversampling).\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF\n  */\n__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n  \n  return (uint32_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 12 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF\n  */\n__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n  \n  return (uint16_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 10 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF\n  */\n__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n  \n  return (uint16_t)(READ_BIT(*preg,\n                             ADC_JDR1_JDATA)\n                   );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 8 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00 and Max_Data=0xFF\n  */\n__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n  \n  return (uint8_t)(READ_BIT(*preg,\n                            ADC_JDR1_JDATA)\n                  );\n}\n\n/**\n  * @brief  Get ADC group injected conversion data, range fit for\n  *         ADC resolution 6 bits.\n  * @note   For devices with feature oversampling: Oversampling\n  *         can increase data width, function for extended range\n  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.\n  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\\n\n  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6\n  * @param  ADCx ADC instance\n  * @param  Rank This parameter can be one of the following values:\n  *         @arg @ref LL_ADC_INJ_RANK_1\n  *         @arg @ref LL_ADC_INJ_RANK_2\n  *         @arg @ref LL_ADC_INJ_RANK_3\n  *         @arg @ref LL_ADC_INJ_RANK_4\n  * @retval Value between Min_Data=0x00 and Max_Data=0x3F\n  */\n__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)\n{\n  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));\n  \n  return (uint8_t)(READ_BIT(*preg,\n                            ADC_JDR1_JDATA)\n                  );\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management\n  * @{\n  */\n\n/**\n  * @brief  Get flag ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOCS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));\n}\n\n/**\n  * @brief  Get flag ADC group regular overrun.\n  * @rmtoll SR       OVR            LL_ADC_IsActiveFlag_OVR\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));\n}\n\n\n/**\n  * @brief  Get flag ADC group injected end of sequence conversions.\n  * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));\n}\n\n/**\n  * @brief  Get flag ADC analog watchdog 1 flag\n  * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));\n}\n\n/**\n  * @brief  Clear flag ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOCS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);\n}\n\n/**\n  * @brief  Clear flag ADC group regular overrun.\n  * @rmtoll SR       OVR            LL_ADC_ClearFlag_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);\n}\n\n\n/**\n  * @brief  Clear flag ADC group injected end of sequence conversions.\n  * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);\n}\n\n/**\n  * @brief  Clear flag ADC analog watchdog 1.\n  * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)\n{\n  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);\n}\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/**\n  * @brief  Get flag multimode ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration, of the ADC master.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll CSR      EOC1           LL_ADC_IsActiveFlag_MST_EOCS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration, of the ADC slave 1.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll CSR      EOC2           LL_ADC_IsActiveFlag_SLV1_EOCS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration, of the ADC slave 2.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll CSR      EOC3           LL_ADC_IsActiveFlag_SLV2_EOCS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));\n}\n/**\n  * @brief  Get flag multimode ADC group regular overrun of the ADC master.\n  * @rmtoll CSR      OVR1           LL_ADC_IsActiveFlag_MST_OVR\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular overrun of the ADC slave 1.\n  * @rmtoll CSR      OVR2           LL_ADC_IsActiveFlag_SLV1_OVR\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));\n}\n\n/**\n  * @brief  Get flag multimode ADC group regular overrun of the ADC slave 2.\n  * @rmtoll CSR      OVR3           LL_ADC_IsActiveFlag_SLV2_OVR\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));\n}\n\n\n/**\n  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.\n  * @rmtoll CSR      JEOC           LL_ADC_IsActiveFlag_MST_EOCS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.\n  * @rmtoll CSR      JEOC2          LL_ADC_IsActiveFlag_SLV1_JEOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));\n}\n\n/**\n  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.\n  * @rmtoll CSR      JEOC3          LL_ADC_IsActiveFlag_SLV2_JEOS\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));\n}\n\n/**\n  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.\n  * @rmtoll CSR      AWD1           LL_ADC_IsActiveFlag_MST_AWD1\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));\n}\n\n/**\n  * @brief  Get flag multimode analog watchdog 1 of the ADC slave 1.\n  * @rmtoll CSR      AWD2           LL_ADC_IsActiveFlag_SLV1_AWD1\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));\n}\n\n/**\n  * @brief  Get flag multimode analog watchdog 1 of the ADC slave 2.\n  * @rmtoll CSR      AWD3           LL_ADC_IsActiveFlag_SLV2_AWD1\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n    return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));\n}\n\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_LL_EF_IT_Management ADC IT management\n  * @{\n  */\n\n/**\n  * @brief  Enable interruption ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOCS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);\n}\n\n/**\n  * @brief  Enable ADC group regular interruption overrun.\n  * @rmtoll CR1      OVRIE          LL_ADC_EnableIT_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);\n}\n\n\n/**\n  * @brief  Enable interruption ADC group injected end of sequence conversions.\n  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);\n}\n\n/**\n  * @brief  Enable interruption ADC analog watchdog 1.\n  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)\n{\n  SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOCS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);\n}\n\n/**\n  * @brief  Disable interruption ADC group regular overrun.\n  * @rmtoll CR1      OVRIE          LL_ADC_DisableIT_OVR\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);\n}\n\n\n/**\n  * @brief  Disable interruption ADC group injected end of sequence conversions.\n  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);\n}\n\n/**\n  * @brief  Disable interruption ADC analog watchdog 1.\n  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval None\n  */\n__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)\n{\n  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular end of unitary conversion\n  *         or end of sequence conversions, depending on\n  *         ADC configuration.\n  * @note   To configure flag of end of conversion,\n  *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().\n  *         (0: interrupt disabled, 1: interrupt enabled)\n  * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOCS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));\n}\n\n/**\n  * @brief  Get state of interruption ADC group regular overrun\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll CR1      OVRIE          LL_ADC_IsEnabledIT_OVR\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));\n}\n\n\n/**\n  * @brief  Get state of interruption ADC group injected end of sequence conversions\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)\n{\n  /* Note: on this STM32 series, there is no flag ADC group injected          */\n  /*       end of unitary conversion.                                         */\n  /*       Flag noted as \"JEOC\" is corresponding to flag \"JEOS\"               */\n  /*       in other STM32 families).                                          */\n  return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));\n}\n\n/**\n  * @brief  Get state of interruption ADC analog watchdog 1\n  *         (0: interrupt disabled, 1: interrupt enabled).\n  * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1\n  * @param  ADCx ADC instance\n  * @retval State of bit (1 or 0).\n  */\n__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)\n{\n  return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));\n}\n\n/**\n  * @}\n  */\n\n#if defined(USE_FULL_LL_DRIVER)\n/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions\n  * @{\n  */\n\n/* Initialization of some features of ADC common parameters and multimode */\nErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);\nErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\nvoid        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);\n\n/* De-initialization of ADC instance, ADC group regular and ADC group injected */\n/* (availability of ADC group injected depends on STM32 families) */\nErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);\n\n/* Initialization of some features of ADC instance */\nErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);\nvoid        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);\n\n/* Initialization of some features of ADC instance and ADC group regular */\nErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\nvoid        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);\n\n/* Initialization of some features of ADC instance and ADC group injected */\nErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\nvoid        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);\n\n/**\n  * @}\n  */\n#endif /* USE_FULL_LL_DRIVER */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* ADC1 || ADC2 || ADC3 */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F4xx_LL_ADC_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usb.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usb.h\n  * @author  MCD Application Team\n  * @brief   Header file of USB Low Layer HAL module.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef STM32F4xx_LL_USB_H\n#define STM32F4xx_LL_USB_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal_def.h\"\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup USB_LL\n  * @{\n  */\n\n/* Exported types ------------------------------------------------------------*/\n\n/**\n  * @brief  USB Mode definition\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n\ntypedef enum\n{\n  USB_DEVICE_MODE  = 0,\n  USB_HOST_MODE    = 1,\n  USB_DRD_MODE     = 2\n} USB_OTG_ModeTypeDef;\n\n/**\n  * @brief  URB States definition\n  */\ntypedef enum\n{\n  URB_IDLE = 0,\n  URB_DONE,\n  URB_NOTREADY,\n  URB_NYET,\n  URB_ERROR,\n  URB_STALL\n} USB_OTG_URBStateTypeDef;\n\n/**\n  * @brief  Host channel States  definition\n  */\ntypedef enum\n{\n  HC_IDLE = 0,\n  HC_XFRC,\n  HC_HALTED,\n  HC_NAK,\n  HC_NYET,\n  HC_STALL,\n  HC_XACTERR,\n  HC_BBLERR,\n  HC_DATATGLERR\n} USB_OTG_HCStateTypeDef;\n\n/**\n  * @brief  USB Instance Initialization Structure definition\n  */\ntypedef struct\n{\n  uint32_t dev_endpoints;           /*!< Device Endpoints number.\n                                         This parameter depends on the used USB core.\n                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\n\n  uint32_t Host_channels;           /*!< Host Channels number.\n                                         This parameter Depends on the used USB core.\n                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */\n\n  uint32_t speed;                   /*!< USB Core speed.\n                                         This parameter can be any value of @ref USB_Core_Speed                 */\n\n  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */\n\n  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */\n\n  uint32_t phy_itface;              /*!< Select the used PHY interface.\n                                         This parameter can be any value of @ref USB_Core_PHY                   */\n\n  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */\n\n  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */\n\n  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */\n\n  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */\n\n  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */\n\n  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */\n\n  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */\n\n} USB_OTG_CfgTypeDef;\n\ntypedef struct\n{\n  uint8_t   num;                  /*!< Endpoint number\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\n\n  uint8_t   is_in;                /*!< Endpoint direction\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\n\n  uint8_t   is_stall;             /*!< Endpoint stall condition\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\n\n  uint8_t   type;                 /*!< Endpoint type\n                                       This parameter can be any value of @ref USB_EP_Type_                     */\n\n  uint8_t   data_pid_start;       /*!< Initial data PID\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\n\n  uint8_t   even_odd_frame;       /*!< IFrame parity\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */\n\n  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number\n                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */\n\n  uint32_t  maxpacket;            /*!< Endpoint Max packet size\n                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */\n\n  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */\n\n  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */\n\n  uint32_t  xfer_len;             /*!< Current transfer length                                                  */\n\n  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */\n} USB_OTG_EPTypeDef;\n\ntypedef struct\n{\n  uint8_t   dev_addr;           /*!< USB device address.\n                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */\n\n  uint8_t   ch_num;             /*!< Host channel number.\n                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\n\n  uint8_t   ep_num;             /*!< Endpoint number.\n                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */\n\n  uint8_t   ep_is_in;           /*!< Endpoint direction\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\n\n  uint8_t   speed;              /*!< USB Host speed.\n                                     This parameter can be any value of @ref USB_Core_Speed_                    */\n\n  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */\n\n  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */\n\n  uint8_t   ep_type;            /*!< Endpoint Type.\n                                     This parameter can be any value of @ref USB_EP_Type_                       */\n\n  uint16_t  max_packet;         /*!< Endpoint Max packet size.\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */\n\n  uint8_t   data_pid;           /*!< Initial data PID.\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\n\n  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */\n\n  uint32_t  XferSize;             /*!< OTG Channel transfer size.                                                   */\n\n  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */\n\n  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */\n\n  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\n\n  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag\n                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */\n\n  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */\n\n  uint32_t  ErrCnt;             /*!< Host channel error count.                                                  */\n\n  USB_OTG_URBStateTypeDef urb_state;  /*!< URB state.\n                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */\n\n  USB_OTG_HCStateTypeDef state;       /*!< Host Channel state.\n                                            This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */\n} USB_OTG_HCTypeDef;\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/* Exported constants --------------------------------------------------------*/\n\n/** @defgroup PCD_Exported_Constants PCD Exported Constants\n  * @{\n  */\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/** @defgroup USB_OTG_CORE VERSION ID\n  * @{\n  */\n#define USB_OTG_CORE_ID_300A          0x4F54300AU\n#define USB_OTG_CORE_ID_310A          0x4F54310AU\n/**\n  * @}\n  */\n\n/** @defgroup USB_Core_Mode_ USB Core Mode\n  * @{\n  */\n#define USB_OTG_MODE_DEVICE                    0U\n#define USB_OTG_MODE_HOST                      1U\n#define USB_OTG_MODE_DRD                       2U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL Device Speed\n  * @{\n  */\n#define USBD_HS_SPEED                          0U\n#define USBD_HSINFS_SPEED                      1U\n#define USBH_HS_SPEED                          0U\n#define USBD_FS_SPEED                          2U\n#define USBH_FSLS_SPEED                        1U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed\n  * @{\n  */\n#define USB_OTG_SPEED_HIGH                     0U\n#define USB_OTG_SPEED_HIGH_IN_FULL             1U\n#define USB_OTG_SPEED_FULL                     3U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY\n  * @{\n  */\n#define USB_OTG_ULPI_PHY                       1U\n#define USB_OTG_EMBEDDED_PHY                   2U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value\n  * @{\n  */\n#ifndef USBD_HS_TRDT_VALUE\n#define USBD_HS_TRDT_VALUE                     9U\n#endif /* USBD_HS_TRDT_VALUE */\n#ifndef USBD_FS_TRDT_VALUE\n#define USBD_FS_TRDT_VALUE                     5U\n#define USBD_DEFAULT_TRDT_VALUE                9U\n#endif /* USBD_HS_TRDT_VALUE */\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS\n  * @{\n  */\n#define USB_OTG_HS_MAX_PACKET_SIZE           512U\n#define USB_OTG_FS_MAX_PACKET_SIZE            64U\n#define USB_OTG_MAX_EP0_SIZE                  64U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency\n  * @{\n  */\n#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)\n#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)\n#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval\n  * @{\n  */\n#define DCFG_FRAME_INTERVAL_80                 0U\n#define DCFG_FRAME_INTERVAL_85                 1U\n#define DCFG_FRAME_INTERVAL_90                 2U\n#define DCFG_FRAME_INTERVAL_95                 3U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS\n  * @{\n  */\n#define EP_MPS_64                        0U\n#define EP_MPS_32                        1U\n#define EP_MPS_16                        2U\n#define EP_MPS_8                         3U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed\n  * @{\n  */\n#define EP_SPEED_LOW                           0U\n#define EP_SPEED_FULL                          1U\n#define EP_SPEED_HIGH                          2U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_EP_Type USB Low Layer EP Type\n  * @{\n  */\n#define EP_TYPE_CTRL                           0U\n#define EP_TYPE_ISOC                           1U\n#define EP_TYPE_BULK                           2U\n#define EP_TYPE_INTR                           3U\n#define EP_TYPE_MSK                            3U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines\n  * @{\n  */\n#define STS_GOUT_NAK                           1U\n#define STS_DATA_UPDT                          2U\n#define STS_XFER_COMP                          3U\n#define STS_SETUP_COMP                         4U\n#define STS_SETUP_UPDT                         6U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines\n  * @{\n  */\n#define HCFG_30_60_MHZ                         0U\n#define HCFG_48_MHZ                            1U\n#define HCFG_6_MHZ                             2U\n/**\n  * @}\n  */\n\n/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines\n  * @{\n  */\n#define HPRT0_PRTSPD_HIGH_SPEED                0U\n#define HPRT0_PRTSPD_FULL_SPEED                1U\n#define HPRT0_PRTSPD_LOW_SPEED                 2U\n/**\n  * @}\n  */\n\n#define HCCHAR_CTRL                            0U\n#define HCCHAR_ISOC                            1U\n#define HCCHAR_BULK                            2U\n#define HCCHAR_INTR                            3U\n\n#define HC_PID_DATA0                           0U\n#define HC_PID_DATA2                           1U\n#define HC_PID_DATA1                           2U\n#define HC_PID_SETUP                           3U\n\n#define GRXSTS_PKTSTS_IN                       2U\n#define GRXSTS_PKTSTS_IN_XFER_COMP             3U\n#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U\n#define GRXSTS_PKTSTS_CH_HALTED                7U\n\n#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)\n#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)\n\n#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))\n#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))\n#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))\n\n#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))\n#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n#define EP_ADDR_MSK                            0xFU\n/**\n  * @}\n  */\n\n/* Exported macro ------------------------------------------------------------*/\n/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))\n#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))\n\n#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))\n#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\nHAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);\nHAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,\n                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma);\n\nvoid             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);\nHAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);\nHAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);\nuint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\nuint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);\nvoid              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);\n\nHAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);\nuint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);\nuint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,\n                              uint8_t epnum, uint8_t dev_address, uint8_t speed,\n                              uint8_t ep_type, uint16_t mps);\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx,\n                                   USB_OTG_HCTypeDef *hc, uint8_t dma);\n\nuint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\nHAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n#ifdef __cplusplus\n}\n#endif\n\n\n#endif /* STM32F4xx_LL_USB_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal.c\n  * @author  MCD Application Team\n  * @brief   HAL module driver.\n  *          This is the common part of the HAL initialization\n  *\n  @verbatim\n  ==============================================================================\n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    The common HAL driver contains a set of generic and common APIs that can be\n    used by the PPP peripheral drivers and the user to start using the HAL. \n    [..]\n    The HAL contains two APIs' categories: \n         (+) Common HAL APIs\n         (+) Services HAL APIs\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup HAL HAL\n  * @brief HAL module driver.\n  * @{\n  */\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup HAL_Private_Constants\n  * @{\n  */\n/**\n  * @brief STM32F4xx HAL Driver version number V1.7.12\n  */\n#define __STM32F4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */\n#define __STM32F4xx_HAL_VERSION_SUB1   (0x07U) /*!< [23:16] sub1 version */\n#define __STM32F4xx_HAL_VERSION_SUB2   (0x0CU) /*!< [15:8]  sub2 version */\n#define __STM32F4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */ \n#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\\\n                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\\\n                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\\\n                                        |(__STM32F4xx_HAL_VERSION_RC))\n                                        \n#define IDCODE_DEVID_MASK    0x00000FFFU\n\n/* ------------ RCC registers bit address in the alias region ----------- */\n#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)\n/* ---  MEMRMP Register ---*/ \n/* Alias word address of UFB_MODE bit */ \n#define MEMRMP_OFFSET             SYSCFG_OFFSET \n#define UFB_MODE_BIT_NUMBER       SYSCFG_MEMRMP_UFB_MODE_Pos\n#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) \n\n/* ---  CMPCR Register ---*/ \n/* Alias word address of CMP_PD bit */ \n#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) \n#define CMP_PD_BIT_NUMBER         SYSCFG_CMPCR_CMP_PD_Pos\n#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))\n\n/* ---  MCHDLYCR Register ---*/ \n/* Alias word address of BSCKSEL bit */ \n#define MCHDLYCR_OFFSET            (SYSCFG_OFFSET + 0x30U) \n#define BSCKSEL_BIT_NUMBER         SYSCFG_MCHDLYCR_BSCKSEL_Pos\n#define MCHDLYCR_BSCKSEL_BB        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))\n/**\n  * @}\n  */\n\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup HAL_Private_Variables\n  * @{\n  */\n__IO uint32_t uwTick;\nuint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */\nHAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n\n/** @defgroup HAL_Exported_Functions HAL Exported Functions\n  * @{\n  */\n\n/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions \n *  @brief    Initialization and de-initialization functions\n *\n@verbatim    \n ===============================================================================\n              ##### Initialization and Configuration functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Initializes the Flash interface the NVIC allocation and initial clock \n          configuration. It initializes the systick also when timeout is needed \n          and the backup domain when enabled.\n      (+) De-Initializes common part of the HAL.\n      (+) Configure the time base source to have 1ms time base with a dedicated \n          Tick interrupt priority. \n        (++) SysTick timer is used by default as source of time base, but user\n             can eventually implement his proper time base source (a general purpose \n             timer for example or other time source), keeping in mind that Time base \n             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and \n             handled in milliseconds basis.\n        (++) Time base configuration function (HAL_InitTick ()) is called automatically \n             at the beginning of the program after reset by HAL_Init() or at any time \n             when clock is configured, by HAL_RCC_ClockConfig(). \n        (++) Source of time base is configured  to generate interrupts at regular \n             time intervals. Care must be taken if HAL_Delay() is called from a \n             peripheral ISR process, the Tick interrupt line must have higher priority \n            (numerically lower) than the peripheral interrupt. Otherwise the caller \n            ISR process will be blocked. \n       (++) functions affecting time base configurations are declared as __weak  \n             to make  override possible  in case of other  implementations in user file.\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  This function is used to initialize the HAL Library; it must be the first \n  *         instruction to be executed in the main program (before to call any other\n  *         HAL function), it performs the following:\n  *           Configure the Flash prefetch, instruction and Data caches.\n  *           Configures the SysTick to generate an interrupt each 1 millisecond,\n  *           which is clocked by the HSI (at this stage, the clock is not yet\n  *           configured and thus the system is running from the internal HSI at 16 MHz).\n  *           Set NVIC Group Priority to 4.\n  *           Calls the HAL_MspInit() callback function defined in user file \n  *           \"stm32f4xx_hal_msp.c\" to do the global low level hardware initialization \n  *            \n  * @note   SysTick is used as time base for the HAL_Delay() function, the application\n  *         need to ensure that the SysTick time base is always set to 1 millisecond\n  *         to have correct HAL operation.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_Init(void)\n{\n  /* Configure Flash prefetch, Instruction cache, Data cache */ \n#if (INSTRUCTION_CACHE_ENABLE != 0U)\n  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();\n#endif /* INSTRUCTION_CACHE_ENABLE */\n\n#if (DATA_CACHE_ENABLE != 0U)\n  __HAL_FLASH_DATA_CACHE_ENABLE();\n#endif /* DATA_CACHE_ENABLE */\n\n#if (PREFETCH_ENABLE != 0U)\n  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();\n#endif /* PREFETCH_ENABLE */\n\n  /* Set Interrupt Group Priority */\n  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);\n\n  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */\n  HAL_InitTick(TICK_INT_PRIORITY);\n\n  /* Init the low level hardware */\n  HAL_MspInit();\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function de-Initializes common part of the HAL and stops the systick.\n  *         This function is optional.   \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DeInit(void)\n{\n  /* Reset of all peripherals */\n  __HAL_RCC_APB1_FORCE_RESET();\n  __HAL_RCC_APB1_RELEASE_RESET();\n\n  __HAL_RCC_APB2_FORCE_RESET();\n  __HAL_RCC_APB2_RELEASE_RESET();\n\n  __HAL_RCC_AHB1_FORCE_RESET();\n  __HAL_RCC_AHB1_RELEASE_RESET();\n\n  __HAL_RCC_AHB2_FORCE_RESET();\n  __HAL_RCC_AHB2_RELEASE_RESET();\n\n  __HAL_RCC_AHB3_FORCE_RESET();\n  __HAL_RCC_AHB3_RELEASE_RESET();\n\n  /* De-Init the low level hardware */\n  HAL_MspDeInit();\n    \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initialize the MSP.\n  * @retval None\n  */\n__weak void HAL_MspInit(void)\n{\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes the MSP.\n  * @retval None\n  */\n__weak void HAL_MspDeInit(void)\n{\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_MspDeInit could be implemented in the user file\n   */ \n}\n\n/**\n  * @brief This function configures the source of the time base.\n  *        The time source is configured  to have 1ms time base with a dedicated \n  *        Tick interrupt priority.\n  * @note This function is called  automatically at the beginning of program after\n  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().\n  * @note In the default implementation, SysTick timer is the source of time base. \n  *       It is used to generate interrupts at regular time intervals. \n  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, \n  *       The SysTick interrupt must have higher priority (numerically lower)\n  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.\n  *       The function is declared as __weak  to be overwritten  in case of other\n  *       implementation  in user file.\n  * @param TickPriority Tick interrupt priority.\n  * @retval HAL status\n  */\n__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)\n{\n  /* Configure the SysTick to have interrupt in 1ms time basis*/\n  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Configure the SysTick IRQ priority */\n  if (TickPriority < (1UL << __NVIC_PRIO_BITS))\n  {\n    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);\n    uwTickPrio = TickPriority;\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions \n *  @brief    HAL Control functions\n *\n@verbatim\n ===============================================================================\n                      ##### HAL Control functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Provide a tick value in millisecond\n      (+) Provide a blocking delay in millisecond\n      (+) Suspend the time base source interrupt\n      (+) Resume the time base source interrupt\n      (+) Get the HAL API driver version\n      (+) Get the device identifier\n      (+) Get the device revision identifier\n      (+) Enable/Disable Debug module during SLEEP mode\n      (+) Enable/Disable Debug module during STOP mode\n      (+) Enable/Disable Debug module during STANDBY mode\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief This function is called to increment  a global variable \"uwTick\"\n  *        used as application time base.\n  * @note In the default implementation, this variable is incremented each 1ms\n  *       in SysTick ISR.\n * @note This function is declared as __weak to be overwritten in case of other \n  *      implementations in user file.\n  * @retval None\n  */\n__weak void HAL_IncTick(void)\n{\n  uwTick += uwTickFreq;\n}\n\n/**\n  * @brief Provides a tick value in millisecond.\n  * @note This function is declared as __weak to be overwritten in case of other \n  *       implementations in user file.\n  * @retval tick value\n  */\n__weak uint32_t HAL_GetTick(void)\n{\n  return uwTick;\n}\n\n/**\n  * @brief This function returns a tick priority.\n  * @retval tick priority\n  */\nuint32_t HAL_GetTickPrio(void)\n{\n  return uwTickPrio;\n}\n\n/**\n  * @brief Set new tick Freq.\n  * @retval Status\n  */\nHAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)\n{\n  HAL_StatusTypeDef status  = HAL_OK;\n  HAL_TickFreqTypeDef prevTickFreq;\n\n  assert_param(IS_TICKFREQ(Freq));\n\n  if (uwTickFreq != Freq)\n  {\n    /* Back up uwTickFreq frequency */\n    prevTickFreq = uwTickFreq;\n\n    /* Update uwTickFreq global variable used by HAL_InitTick() */\n    uwTickFreq = Freq;\n\n    /* Apply the new tick Freq  */\n    status = HAL_InitTick(uwTickPrio);\n\n    if (status != HAL_OK)\n    {\n      /* Restore previous tick frequency */\n      uwTickFreq = prevTickFreq;\n    }\n  }\n\n  return status;\n}\n\n/**\n  * @brief Return tick frequency.\n  * @retval tick period in Hz\n  */\nHAL_TickFreqTypeDef HAL_GetTickFreq(void)\n{\n  return uwTickFreq;\n}\n\n/**\n  * @brief This function provides minimum delay (in milliseconds) based \n  *        on variable incremented.\n  * @note In the default implementation , SysTick timer is the source of time base.\n  *       It is used to generate interrupts at regular time intervals where uwTick\n  *       is incremented.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @param Delay specifies the delay time length, in milliseconds.\n  * @retval None\n  */\n__weak void HAL_Delay(uint32_t Delay)\n{\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t wait = Delay;\n\n  /* Add a freq to guarantee minimum wait */\n  if (wait < HAL_MAX_DELAY)\n  {\n    wait += (uint32_t)(uwTickFreq);\n  }\n\n  while((HAL_GetTick() - tickstart) < wait)\n  {\n  }\n}\n\n/**\n  * @brief Suspend Tick increment.\n  * @note In the default implementation , SysTick timer is the source of time base. It is\n  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()\n  *       is called, the SysTick interrupt will be disabled and so Tick increment \n  *       is suspended.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @retval None\n  */\n__weak void HAL_SuspendTick(void)\n{\n  /* Disable SysTick Interrupt */\n  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;\n}\n\n/**\n  * @brief Resume Tick increment.\n  * @note In the default implementation , SysTick timer is the source of time base. It is\n  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()\n  *       is called, the SysTick interrupt will be enabled and so Tick increment \n  *       is resumed.\n  * @note This function is declared as __weak to be overwritten in case of other\n  *       implementations in user file.\n  * @retval None\n  */\n__weak void HAL_ResumeTick(void)\n{\n  /* Enable SysTick Interrupt */\n  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;\n}\n\n/**\n  * @brief  Returns the HAL revision\n  * @retval version : 0xXYZR (8bits for each decimal, R for RC)\n  */\nuint32_t HAL_GetHalVersion(void)\n{\n  return __STM32F4xx_HAL_VERSION;\n}\n\n/**\n  * @brief  Returns the device revision identifier.\n  * @retval Device revision identifier\n  */\nuint32_t HAL_GetREVID(void)\n{\n  return((DBGMCU->IDCODE) >> 16U);\n}\n\n/**\n  * @brief  Returns the device identifier.\n  * @retval Device identifier\n  */\nuint32_t HAL_GetDEVID(void)\n{\n  return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);\n}\n\n/**\n  * @brief  Enable the Debug Module during SLEEP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGSleepMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Disable the Debug Module during SLEEP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGSleepMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STOP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGStopMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Disable the Debug Module during STOP mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGStopMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);\n}\n\n/**\n  * @brief  Enable the Debug Module during STANDBY mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_EnableDBGStandbyMode(void)\n{\n  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Disable the Debug Module during STANDBY mode\n  * @retval None\n  */\nvoid HAL_DBGMCU_DisableDBGStandbyMode(void)\n{\n  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);\n}\n\n/**\n  * @brief  Enables the I/O Compensation Cell.\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V.  \n  * @retval None\n  */\nvoid HAL_EnableCompensationCell(void)\n{\n  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief  Power-down the I/O Compensation Cell.\n  * @note   The I/O compensation cell can be used only when the device supply\n  *         voltage ranges from 2.4 to 3.6 V.  \n  * @retval None\n  */\nvoid HAL_DisableCompensationCell(void)\n{\n  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)\n  * @retval Device identifier\n  */\nuint32_t HAL_GetUIDw0(void)\n{\n  return (READ_REG(*((uint32_t *)UID_BASE)));\n}\n\n/**\n  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)\n  * @retval Device identifier\n  */\nuint32_t HAL_GetUIDw1(void)\n{\n  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));\n}\n\n/**\n  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)\n  * @retval Device identifier\n  */\nuint32_t HAL_GetUIDw2(void)\n{\n  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));\n}\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\\\n    defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Enables the Internal FLASH Bank Swapping.\n  *   \n  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. \n  *\n  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) \n  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   \n  *\n  * @retval None\n  */\nvoid HAL_EnableMemorySwappingBank(void)\n{\n  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief  Disables the Internal FLASH Bank Swapping.\n  *   \n  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. \n  *\n  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) \n  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) \n  *           \n  * @retval None\n  */\nvoid HAL_DisableMemorySwappingBank(void)\n{\n  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;\n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_adc.c\n  * @author  MCD Application Team\n  * @brief   This file provides firmware functions to manage the following \n  *          functionalities of the Analog to Digital Converter (ADC) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + State and errors functions\n  *         \n  @verbatim\n  ==============================================================================\n                    ##### ADC Peripheral features #####\n  ==============================================================================\n  [..] \n  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.\n  (#) Interrupt generation at the end of conversion, end of injected conversion,  \n      and in case of analog watchdog or overrun events\n  (#) Single and continuous conversion modes.\n  (#) Scan mode for automatic conversion of channel 0 to channel x.\n  (#) Data alignment with in-built data coherency.\n  (#) Channel-wise programmable sampling time.\n  (#) External trigger option with configurable polarity for both regular and \n      injected conversion.\n  (#) Dual/Triple mode (on devices with 2 ADCs or more).\n  (#) Configurable DMA data storage in Dual/Triple ADC mode. \n  (#) Configurable delay between conversions in Dual/Triple interleaved mode.\n  (#) ADC conversion type (refer to the datasheets).\n  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at \n      slower speed.\n  (#) ADC input range: VREF(minus) = VIN = VREF(plus).\n  (#) DMA request generation during regular channel conversion.\n\n\n                     ##### How to use this driver #####\n  ==============================================================================\n  [..]\n  (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\n       (##) ADC pins configuration\n             (+++) Enable the clock for the ADC GPIOs using the following function:\n                   __HAL_RCC_GPIOx_CLK_ENABLE()  \n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() \n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\n       (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\n             (+++) Configure and enable two DMA streams stream for managing data\n                 transfer from peripheral to memory (output stream)\n             (+++) Associate the initialized DMA handle to the CRYP DMA handle\n                 using  __HAL_LINKDMA()\n             (+++) Configure the priority and enable the NVIC for the transfer complete\n                 interrupt on the two DMA Streams. The output stream should have higher\n                 priority than the input stream.\n                       \n    *** Configuration of ADC, groups regular/injected, channels parameters ***\n  ==============================================================================\n  [..]\n  (#) Configure the ADC parameters (resolution, data alignment, ...)\n      and regular group parameters (conversion trigger, sequencer, ...)\n      using function HAL_ADC_Init().\n\n  (#) Configure the channels for regular group parameters (channel number, \n      channel rank into sequencer, ..., into regular group)\n      using function HAL_ADC_ConfigChannel().\n\n  (#) Optionally, configure the injected group parameters (conversion trigger, \n      sequencer, ..., of injected group)\n      and the channels for injected group parameters (channel number, \n      channel rank into sequencer, ..., into injected group)\n      using function HAL_ADCEx_InjectedConfigChannel().\n\n  (#) Optionally, configure the analog watchdog parameters (channels\n      monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig().\n\n  (#) Optionally, for devices with several ADC instances: configure the \n      multimode parameters using function HAL_ADCEx_MultiModeConfigChannel().\n\n                       *** Execution of ADC conversions ***\n  ==============================================================================\n  [..]  \n  (#) ADC driver can be used among three modes: polling, interruption,\n      transfer by DMA.    \n\n     *** Polling mode IO operation ***\n     =================================\n     [..]    \n       (+) Start the ADC peripheral using HAL_ADC_Start() \n       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\n           user can specify the value of timeout according to his end application      \n       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.\n       (+) Stop the ADC peripheral using HAL_ADC_Stop()\n       \n     *** Interrupt mode IO operation ***    \n     ===================================\n     [..]    \n       (+) Start the ADC peripheral using HAL_ADC_Start_IT() \n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\n       (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can \n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \n       (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can \n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_IT()     \n\n     *** DMA mode IO operation ***    \n     ==============================\n     [..]    \n       (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length \n           of data to be transferred at each end of conversion \n       (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can \n           add his own code by customization of function pointer HAL_ADC_ConvCpltCallback \n       (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can \n           add his own code by customization of function pointer HAL_ADC_ErrorCallback\n       (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA()\n                    \n     *** ADC HAL driver macros list ***\n     ============================================= \n     [..]\n       Below the list of most used macros in ADC HAL driver.\n       \n      (+) __HAL_ADC_ENABLE : Enable the ADC peripheral\n      (+) __HAL_ADC_DISABLE : Disable the ADC peripheral\n      (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt\n      (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt\n      (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled\n      (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags\n      (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status\n      (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register \n      \n     [..] \n       (@) You can refer to the ADC HAL driver header file for more useful macros \n\n                      *** Deinitialization of ADC ***\n  ==============================================================================\n  [..]\n  (#) Disable the ADC interface\n     (++) ADC clock can be hard reset and disabled at RCC top level.\n     (++) Hard reset of ADC peripherals\n          using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET().\n     (++) ADC clock disable using the equivalent macro/functions as configuration step.\n               (+++) Example:\n                   Into HAL_ADC_MspDeInit() (recommended code location) or with\n                   other device clock parameters configuration:\n               (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure);\n               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI;\n               (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock)\n               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);\n\n  (#) ADC pins configuration\n     (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE()\n\n  (#) Optionally, in case of usage of ADC with interruptions:\n     (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn)\n\n  (#) Optionally, in case of usage of DMA:\n        (++) Deinitialize the DMA using function HAL_DMA_DeInit().\n        (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn)   \n                      *** Callback registration ***\n  ==============================================================================\n    [..]\n\n     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,\n     allows the user to configure dynamically the driver callbacks.\n     Use Functions @ref HAL_ADC_RegisterCallback()\n     to register an interrupt callback.\n    [..]\n\n     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:\n       (+) ConvCpltCallback               : ADC conversion complete callback\n       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback\n       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback\n       (+) ErrorCallback                  : ADC error callback\n       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback\n       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback\n       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback\n       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback\n       (+) EndOfSamplingCallback          : ADC end of sampling callback\n       (+) MspInitCallback                : ADC Msp Init callback\n       (+) MspDeInitCallback              : ADC Msp DeInit callback\n     This function takes as parameters the HAL peripheral handle, the Callback ID\n     and a pointer to the user callback function.\n    [..]\n\n     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default\n     weak function.\n    [..]\n\n     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,\n     and the Callback ID.\n     This function allows to reset following callbacks:\n       (+) ConvCpltCallback               : ADC conversion complete callback\n       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback\n       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback\n       (+) ErrorCallback                  : ADC error callback\n       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback\n       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback\n       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback\n       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback\n       (+) EndOfSamplingCallback          : ADC end of sampling callback\n       (+) MspInitCallback                : ADC Msp Init callback\n       (+) MspDeInitCallback              : ADC Msp DeInit callback\n     [..]\n\n     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET\n     all callbacks are set to the corresponding weak functions:\n     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().\n     Exception done for MspInit and MspDeInit functions that are\n     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when\n     these callbacks are null (not registered beforehand).\n    [..]\n\n     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()\n     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\n     [..]\n\n     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.\n     Exception done MspInit/MspDeInit functions that can be registered/unregistered\n     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,\n     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\n    [..]\n\n     Then, the user first registers the MspInit/MspDeInit user callbacks\n     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()\n     or @ref HAL_ADC_Init() function.\n     [..]\n\n     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or\n     not defined, the callback registration feature is not available and all callbacks\n     are set to the corresponding weak functions.\n\n    @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup ADC ADC\n  * @brief ADC driver modules\n  * @{\n  */ \n\n#ifdef HAL_ADC_MODULE_ENABLED\n    \n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup ADC_Private_Functions\n  * @{\n  */\n/* Private function prototypes -----------------------------------------------*/\nstatic void ADC_Init(ADC_HandleTypeDef* hadc);\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma);\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);\n/**\n  * @}\n  */\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup ADC_Exported_Functions ADC Exported Functions\n  * @{\n  */\n\n/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions \n *  @brief    Initialization and Configuration functions \n *\n@verbatim    \n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Initialize and configure the ADC. \n      (+) De-initialize the ADC. \n         \n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \n  *         in the ADC_InitStruct and initializes the ADC MSP.\n  *           \n  * @note   This function is used to configure the global features of the ADC ( \n  *         ClockPrescaler, Resolution, Data Alignment and number of conversion), however,\n  *         the rest of the configuration parameters are specific to the regular\n  *         channels group (scan mode activation, continuous mode activation,\n  *         External trigger source and edge, DMA continuous request after the  \n  *         last transfer and End of conversion selection).\n  *             \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  \n  /* Check ADC handle */\n  if(hadc == NULL)\n  {\n    return HAL_ERROR;\n  }\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));\n  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode));\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv));\n  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));\n  \n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\n  {\n    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\n  }\n  \n  if(hadc->State == HAL_ADC_STATE_RESET)\n  {\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n    /* Init the ADC Callback settings */\n    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */\n    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */\n    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */\n    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */\n    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */\n    if (hadc->MspInitCallback == NULL)\n    {\n      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */\n    }\n\n    /* Init the low level hardware */\n    hadc->MspInitCallback(hadc);\n#else\n    /* Init the low level hardware */\n    HAL_ADC_MspInit(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n\n    /* Initialize ADC error code */\n    ADC_CLEAR_ERRORCODE(hadc);\n    \n    /* Allocate lock resource and initialize it */\n    hadc->Lock = HAL_UNLOCKED;\n  }\n  \n  /* Configuration of ADC parameters if previous preliminary actions are      */ \n  /* correctly completed.                                                     */\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\n  {\n    /* Set ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                      HAL_ADC_STATE_BUSY_INTERNAL);\n    \n    /* Set ADC parameters */\n    ADC_Init(hadc);\n    \n    /* Set ADC error code to none */\n    ADC_CLEAR_ERRORCODE(hadc);\n    \n    /* Set the ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_BUSY_INTERNAL,\n                      HAL_ADC_STATE_READY);\n  }\n  else\n  {\n    tmp_hal_status = HAL_ERROR;\n  }\n  \n  /* Release Lock */\n  __HAL_UNLOCK(hadc);\n\n  /* Return function status */\n  return tmp_hal_status;\n}\n\n/**\n  * @brief  Deinitializes the ADCx peripheral registers to their default reset values. \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  \n  /* Check ADC handle */\n  if(hadc == NULL)\n  {\n    return HAL_ERROR;\n  }\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  \n  /* Set ADC state */\n  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);\n  \n  /* Stop potential conversion on going, on regular and injected groups */\n  /* Disable ADC peripheral */\n  __HAL_ADC_DISABLE(hadc);\n  \n  /* Configuration of ADC parameters if previous preliminary actions are      */ \n  /* correctly completed.                                                     */\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n  if (hadc->MspDeInitCallback == NULL)\n  {\n    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */\n  }\n\n  /* DeInit the low level hardware: RCC clock, NVIC */\n  hadc->MspDeInitCallback(hadc);\n#else\n  /* DeInit the low level hardware: RCC clock, NVIC */\n  HAL_ADC_MspDeInit(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n    \n    /* Set ADC error code to none */\n    ADC_CLEAR_ERRORCODE(hadc);\n    \n    /* Set ADC state */\n    hadc->State = HAL_ADC_STATE_RESET;\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return tmp_hal_status;\n}\n\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  Register a User ADC Callback\n  *         To be used instead of the weak predefined callback\n  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains\n  *                the configuration information for the specified ADC.\n  * @param  CallbackID ID of the callback to be registered\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID\n  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID\n  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID\n  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID\n  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID\n  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID\n  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)\n  {\n    switch (CallbackID)\n    {\n      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :\n        hadc->ConvCpltCallback = pCallback;\n        break;\n\n      case HAL_ADC_CONVERSION_HALF_CB_ID :\n        hadc->ConvHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :\n        hadc->LevelOutOfWindowCallback = pCallback;\n        break;\n\n      case HAL_ADC_ERROR_CB_ID :\n        hadc->ErrorCallback = pCallback;\n        break;\n\n      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :\n        hadc->InjectedConvCpltCallback = pCallback;\n        break;\n\n      case HAL_ADC_MSPINIT_CB_ID :\n        hadc->MspInitCallback = pCallback;\n        break;\n\n      case HAL_ADC_MSPDEINIT_CB_ID :\n        hadc->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status = HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_ADC_STATE_RESET == hadc->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_ADC_MSPINIT_CB_ID :\n        hadc->MspInitCallback = pCallback;\n        break;\n\n      case HAL_ADC_MSPDEINIT_CB_ID :\n        hadc->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status = HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Unregister a ADC Callback\n  *         ADC callback is redirected to the weak predefined callback\n  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains\n  *                the configuration information for the specified ADC.\n  * @param  CallbackID ID of the callback to be unregistered\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID\n  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID\n  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID\n  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID\n  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID\n  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID\n  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)\n  {\n    switch (CallbackID)\n    {\n      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :\n        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;\n        break;\n\n      case HAL_ADC_CONVERSION_HALF_CB_ID :\n        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;\n        break;\n\n      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :\n        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;\n        break;\n\n      case HAL_ADC_ERROR_CB_ID :\n        hadc->ErrorCallback = HAL_ADC_ErrorCallback;\n        break;\n\n      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :\n        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;\n        break;\n\n      case HAL_ADC_MSPINIT_CB_ID :\n        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */\n        break;\n\n      case HAL_ADC_MSPDEINIT_CB_ID :\n        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_ADC_STATE_RESET == hadc->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_ADC_MSPINIT_CB_ID :\n        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */\n        break;\n\n      case HAL_ADC_MSPDEINIT_CB_ID :\n        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  return status;\n}\n\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n\n/**\n  * @brief  Initializes the ADC MSP.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.  \n  * @retval None\n  */\n__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_MspInit could be implemented in the user file\n   */ \n}\n\n/**\n  * @brief  DeInitializes the ADC MSP.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.  \n  * @retval None\n  */\n__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_MspDeInit could be implemented in the user file\n   */ \n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_Exported_Functions_Group2 IO operation functions\n *  @brief    IO operation functions \n *\n@verbatim   \n ===============================================================================\n             ##### IO operation functions #####\n ===============================================================================  \n    [..]  This section provides functions allowing to:\n      (+) Start conversion of regular channel.\n      (+) Stop conversion of regular channel.\n      (+) Start conversion of regular channel and enable interrupt.\n      (+) Stop conversion of regular channel and disable interrupt.\n      (+) Start conversion of regular channel and enable DMA transfer.\n      (+) Stop conversion of regular channel and disable DMA transfer.\n      (+) Handle ADC interrupt request. \n               \n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Enables ADC and starts conversion of the regular channels.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)\n{\n  __IO uint32_t counter = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Enable the ADC peripheral */\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n  Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for ADC stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to regular group conversion results     */\n    /* - Set state bitfield related to regular group operation                */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\n                      HAL_ADC_STATE_REG_BUSY);\n    \n    /* If conversions on group regular are also triggering group injected,    */\n    /* update ADC state.                                                      */\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\n    {\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \n    }\n    \n    /* State machine update: Check if an injected conversion is ongoing */\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n    {\n      /* Reset ADC error code fields related to conversions on group regular */\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \n    }\n    else\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    } \n\n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n    /* Clear regular group conversion flag and overrun flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\n    \n    /* Check if Multimode enabled */\n    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))\n    {\n#if defined(ADC2) && defined(ADC3)\n      if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \\\n                                  || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))\n      {\n#endif /* ADC2 || ADC3 */\n        /* if no external trigger present enable software conversion of regular channels */\n        if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \n        {\n          /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n        }\n#if defined(ADC2) && defined(ADC3)\n      }\n#endif /* ADC2 || ADC3 */\n    }\n    else\n    {\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\n      {\n        /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n      }\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Disables ADC and stop conversion of regular channels.\n  * \n  * @note   Caution: This function will stop also injected channels.  \n  *\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  *\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)\n{\n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Stop potential conversion on going, on regular and injected groups */\n  /* Disable ADC peripheral */\n  __HAL_ADC_DISABLE(hadc);\n  \n  /* Check if ADC is effectively disabled */\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                      HAL_ADC_STATE_READY);\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Poll for regular conversion complete\n  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of\n  *         conversion) are cleared by this function.\n  * @note   This function cannot be used in a particular setup: ADC configured \n  *         in DMA mode and polling for end of each conversion (ADC init\n  *         parameter \"EOCSelection\" set to ADC_EOC_SINGLE_CONV).\n  *         In this case, DMA resets the flag EOC and polling cannot be\n  *         performed on each conversion. Nevertheless, polling can still \n  *         be performed on the complete sequence.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  Timeout Timeout value in millisecond.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\n{\n  uint32_t tickstart = 0U;\n \n  /* Verification that ADC configuration is compliant with polling for      */\n  /* each conversion:                                                       */\n  /* Particular case is ADC configured in DMA mode and ADC sequencer with   */\n  /* several ranks and polling for end of each conversion.                  */\n  /* For code simplicity sake, this particular case is generalized to       */\n  /* ADC configured in DMA mode and polling for end of each conversion.     */\n  if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&\n      HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)    )\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\n    \n    /* Process unlocked */\n    __HAL_UNLOCK(hadc);\n    \n    return HAL_ERROR;\n  }\n\n  /* Get tick */ \n  tickstart = HAL_GetTick();\n\n  /* Check End of conversion flag */\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\n  {\n    /* Check if timeout is disabled (set to infinite wait) */\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        /* New check to avoid false timeout detection in case of preemption */\n        if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC)))\n        {\n          /* Update ADC state machine to timeout */\n          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\n          \n          /* Process unlocked */\n          __HAL_UNLOCK(hadc);\n          \n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n  \n  /* Clear regular group conversion flag */\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\n  \n  /* Update ADC state machine */\n  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\n  \n  /* Determine whether any further conversion upcoming on group regular       */\n  /* by external trigger, continuous mode or scan sequence on going.          */\n  /* Note: On STM32F4, there is no independent flag of end of sequence.       */\n  /*       The test of scan sequence on going is done either with scan        */\n  /*       sequence disabled or with end of conversion flag set to            */\n  /*       of end of sequence.                                                */\n  if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\n     (hadc->Init.ContinuousConvMode == DISABLE)            &&\n     (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\n  {\n    /* Set ADC state */\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \n    \n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n    { \n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n    }\n  }\n  \n  /* Return ADC state */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Poll for conversion event\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  EventType the ADC event type.\n  *          This parameter can be one of the following values:\n  *            @arg ADC_AWD_EVENT: ADC Analog watch Dog event.\n  *            @arg ADC_OVR_EVENT: ADC Overrun event.\n  * @param  Timeout Timeout value in millisecond.   \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)\n{\n  uint32_t tickstart = 0U;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  assert_param(IS_ADC_EVENT_TYPE(EventType));\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  /* Check selected event flag */\n  while(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\n  {\n    /* Check for the Timeout */\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        /* New check to avoid false timeout detection in case of preemption */\n        if(!(__HAL_ADC_GET_FLAG(hadc,EventType)))\n        {\n          /* Update ADC state machine to timeout */\n          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);\n          \n          /* Process unlocked */\n          __HAL_UNLOCK(hadc);\n          \n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n  \n  /* Analog watchdog (level out of window) event */\n  if(EventType == ADC_AWD_EVENT)\n  {\n    /* Set ADC state */\n    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\n      \n    /* Clear ADC analog watchdog flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\n  }\n  /* Overrun event */\n  else\n  {\n    /* Set ADC state */\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);\n    /* Set ADC error code to overrun */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\n    \n    /* Clear ADC overrun flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\n  }\n  \n  /* Return ADC state */\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  Enables the interrupt and starts ADC conversion of regular channels.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)\n{\n  __IO uint32_t counter = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Enable the ADC peripheral */\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n  Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for ADC stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to regular group conversion results     */\n    /* - Set state bitfield related to regular group operation                */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\n                      HAL_ADC_STATE_REG_BUSY);\n    \n    /* If conversions on group regular are also triggering group injected,    */\n    /* update ADC state.                                                      */\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\n    {\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \n    }\n    \n    /* State machine update: Check if an injected conversion is ongoing */\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n    {\n      /* Reset ADC error code fields related to conversions on group regular */\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \n    }\n    else\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    }\n\n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n    /* Clear regular group conversion flag and overrun flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\n    \n    /* Enable end of conversion interrupt for regular group */\n    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\n    \n    /* Check if Multimode enabled */\n    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))\n    {\n#if defined(ADC2) && defined(ADC3)\n      if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \\\n                                  || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))\n      {\n#endif /* ADC2 || ADC3 */\n        /* if no external trigger present enable software conversion of regular channels */\n        if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \n        {\n          /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n        }\n#if defined(ADC2) && defined(ADC3)\n      }\n#endif /* ADC2 || ADC3 */\n    }\n    else\n    {\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\n      {\n        /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n      }\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Disables the interrupt and stop ADC conversion of regular channels.\n  * \n  * @note   Caution: This function will stop also injected channels.  \n  *\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)\n{\n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Stop potential conversion on going, on regular and injected groups */\n  /* Disable ADC peripheral */\n  __HAL_ADC_DISABLE(hadc);\n  \n  /* Check if ADC is effectively disabled */\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n  \t/* Disable ADC end of conversion interrupt for regular group */\n    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));\n\n    /* Set ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                      HAL_ADC_STATE_READY);\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Handles ADC interrupt request  \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\nvoid HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)\n{\n  uint32_t tmp1 = 0U, tmp2 = 0U;\n  \n  /* Check the parameters */\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));\n  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));\n  \n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC);\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC);\n  /* Check End of conversion flag for regular channels */\n  if(tmp1 && tmp2)\n  {\n    /* Update state machine on conversion status if not in error state */\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\n    {\n      /* Set ADC state */\n      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); \n    }\n    \n    /* Determine whether any further conversion upcoming on group regular   */\n    /* by external trigger, continuous mode or scan sequence on going.      */\n    /* Note: On STM32F4, there is no independent flag of end of sequence.   */\n    /*       The test of scan sequence on going is done either with scan    */\n    /*       sequence disabled or with end of conversion flag set to        */\n    /*       of end of sequence.                                            */\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\n    {\n      /* Disable ADC end of single conversion interrupt on group regular */\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\n      /* by overrun IRQ process below.                                      */\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\n      \n      /* Set ADC state */\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);\n      \n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n      {\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n      }\n    }\n    \n    /* Conversion complete callback */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n    hadc->ConvCpltCallback(hadc);\n#else\n    HAL_ADC_ConvCpltCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n    \n    /* Clear regular group conversion flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);\n  }\n  \n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC);\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC);                               \n  /* Check End of conversion flag for injected channels */\n  if(tmp1 && tmp2)\n  {\n    /* Update state machine on conversion status if not in error state */\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))\n    {\n      /* Set ADC state */\n      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\n    }\n\n    /* Determine whether any further conversion upcoming on group injected  */\n    /* by external trigger, scan sequence on going or by automatic injected */\n    /* conversion from group regular (same conditions as group regular      */\n    /* interruption disabling above).                                       */\n    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\n       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||\n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&\n       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\n        (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&\n        (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )\n    {\n      /* Disable ADC end of single conversion interrupt on group injected */\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\n      \n      /* Set ADC state */\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   \n\n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\n      { \n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n      }\n    }\n\n    /* Conversion complete callback */ \n    /* Conversion complete callback */ \n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n      hadc->InjectedConvCpltCallback(hadc);\n#else\n      HAL_ADCEx_InjectedConvCpltCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n    \n    /* Clear injected group conversion flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));\n  }\n  \n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD);\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD);                          \n  /* Check Analog watchdog flag */\n  if(tmp1 && tmp2)\n  {\n    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))\n    {\n      /* Set ADC state */\n      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);\n      \n      /* Level out of window callback */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n      hadc->LevelOutOfWindowCallback(hadc);\n#else\n      HAL_ADC_LevelOutOfWindowCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n      \n      /* Clear the ADC analog watchdog flag */\n      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);\n    }\n  }\n  \n  tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR);\n  tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR);\n  /* Check Overrun flag */\n  if(tmp1 && tmp2)\n  {\n    /* Note: On STM32F4, ADC overrun can be set through other parameters    */\n    /*       refer to description of parameter \"EOCSelection\" for more      */\n    /*       details.                                                       */\n    \n    /* Set ADC error code to overrun */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);\n    \n    /* Clear ADC overrun flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\n    \n    /* Error callback */ \n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n      hadc->ErrorCallback(hadc);\n#else\n      HAL_ADC_ErrorCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n    \n    /* Clear the Overrun flag */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);\n  }\n}\n\n/**\n  * @brief  Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral  \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  pData The destination Buffer address.\n  * @param  Length The length of data to be transferred from ADC peripheral to memory.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\n{\n  __IO uint32_t counter = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); \n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Enable the ADC peripheral */\n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n  Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for ADC stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Check ADC DMA Mode                                                     */\n  /* - disable the DMA Mode if it is already enabled                        */\n  if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA)\n  {\n    CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to regular group conversion results     */\n    /* - Set state bitfield related to regular group operation                */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\n                      HAL_ADC_STATE_REG_BUSY);\n    \n    /* If conversions on group regular are also triggering group injected,    */\n    /* update ADC state.                                                      */\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\n    {\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \n    }\n    \n    /* State machine update: Check if an injected conversion is ongoing */\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n    {\n      /* Reset ADC error code fields related to conversions on group regular */\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \n    }\n    else\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    }\n\n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);   \n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n    /* Set the DMA transfer complete callback */\n    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;\n\n    /* Set the DMA half transfer complete callback */\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;\n    \n    /* Set the DMA error callback */\n    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;\n\n    \n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\n    /* start (in case of SW start):                                           */\n    \n    /* Clear regular group conversion flag and overrun flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);\n\n    /* Enable ADC overrun interrupt */\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\n    \n    /* Enable ADC DMA mode */\n    hadc->Instance->CR2 |= ADC_CR2_DMA;\n    \n    /* Start the DMA channel */\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);\n    \n    /* Check if Multimode enabled */\n    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))\n    {\n#if defined(ADC2) && defined(ADC3)\n      if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \\\n                                  || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))\n      {\n#endif /* ADC2 || ADC3 */\n        /* if no external trigger present enable software conversion of regular channels */\n        if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \n        {\n          /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n        }\n#if defined(ADC2) && defined(ADC3)\n      }\n#endif /* ADC2 || ADC3 */\n    }\n    else\n    {\n      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */\n      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))\n      {\n        /* Enable the selected ADC software conversion for regular group */\n          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n      }\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Disables ADC DMA (Single-ADC mode) and disables ADC peripheral    \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Stop potential conversion on going, on regular and injected groups */\n  /* Disable ADC peripheral */\n  __HAL_ADC_DISABLE(hadc);\n  \n  /* Check if ADC is effectively disabled */\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Disable the selected ADC DMA mode */\n    hadc->Instance->CR2 &= ~ADC_CR2_DMA;\n    \n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\n    /* DMA transfer is on going)                                              */\n    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)\n    {\n      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\n      \n      /* Check if DMA channel effectively disabled */\n      if (tmp_hal_status != HAL_OK)\n      {\n        /* Update ADC state machine to error */\n        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);\n      }\n    }\n    \n    /* Disable ADC overrun interrupt */\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\n    \n    /* Set ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                      HAL_ADC_STATE_READY);\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return tmp_hal_status;\n}\n\n/**\n  * @brief  Gets the converted value from data register of regular channel.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval Converted value\n  */\nuint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)\n{       \n  /* Return the selected ADC converted value */ \n  return hadc->Instance->DR;\n}\n\n/**\n  * @brief  Regular conversion complete callback in non blocking mode \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\n__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_ConvCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Regular conversion half DMA transfer callback in non blocking mode \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\n__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Analog watchdog callback in non blocking mode \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\n__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Error ADC callback.\n  * @note   In case of error due to overrun when using ADC with DMA transfer \n  *         (HAL ADC handle paramater \"ErrorCode\" to state \"HAL_ADC_ERROR_OVR\"):\n  *         - Reinitialize the DMA using function \"HAL_ADC_Stop_DMA()\".\n  *         - If needed, restart a new ADC conversion using function\n  *           \"HAL_ADC_Start_DMA()\"\n  *           (this function is also clearing overrun flag)\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\n__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_ErrorCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n  \n/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions\n *  @brief   \tPeripheral Control functions \n *\n@verbatim   \n ===============================================================================\n             ##### Peripheral Control functions #####\n ===============================================================================  \n    [..]  This section provides functions allowing to:\n      (+) Configure regular channels. \n      (+) Configure injected channels.\n      (+) Configure multimode.\n      (+) Configure the analog watch dog.\n      \n@endverbatim\n  * @{\n  */\n\n  /**\n  * @brief  Configures for the selected ADC regular channel its corresponding\n  *         rank in the sequencer and its sample time.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  sConfig ADC configuration structure. \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)\n{\n  __IO uint32_t counter = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_CHANNEL(sConfig->Channel));\n  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));\n  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n    \n  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\n  if (sConfig->Channel > ADC_CHANNEL_9)\n  {\n    /* Clear the old sample time */\n    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);\n    \n    /* Set the new sample time */\n    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);\n  }\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\n  {\n    /* Clear the old sample time */\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);\n    \n    /* Set the new sample time */\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);\n  }\n  \n  /* For Rank 1 to 6 */\n  if (sConfig->Rank < 7U)\n  {\n    /* Clear the old SQx bits for the selected rank */\n    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);\n    \n    /* Set the SQx bits for the selected rank */\n    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);\n  }\n  /* For Rank 7 to 12 */\n  else if (sConfig->Rank < 13U)\n  {\n    /* Clear the old SQx bits for the selected rank */\n    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);\n    \n    /* Set the SQx bits for the selected rank */\n    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);\n  }\n  /* For Rank 13 to 16 */\n  else\n  {\n    /* Clear the old SQx bits for the selected rank */\n    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);\n    \n    /* Set the SQx bits for the selected rank */\n    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);\n  }\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n  /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */\n  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))\n  {\n    /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/    \n    if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)\n    {\n      tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;\n    }\n    /* Enable the VBAT channel*/\n    tmpADC_Common->CCR |= ADC_CCR_VBATE;\n  }\n  \n  /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or \n     Channel_17 is selected for VREFINT enable TSVREFE */\n  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))\n  {\n    /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/\n    if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)\n    {\n      tmpADC_Common->CCR &= ~ADC_CCR_VBATE;\n    }\n    /* Enable the Temperature sensor and VREFINT channel*/\n    tmpADC_Common->CCR |= ADC_CCR_TSVREFE;\n    \n    if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))\n    {\n      /* Delay for temperature sensor stabilization time */\n      /* Compute number of CPU cycles to wait for */\n      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));\n      while(counter != 0U)\n      {\n        counter--;\n      }\n    }\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the analog watchdog.\n  * @note Analog watchdog thresholds can be modified while ADC conversion\n  * is on going.\n  * In this case, some constraints must be taken into account:\n  * The programmed threshold values are effective from the next\n  * ADC EOC (end of unitary conversion).\n  * Considering that registers write delay may happen due to\n  * bus activity, this might cause an uncertainty on the\n  * effective timing of the new programmed threshold values.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  AnalogWDGConfig  pointer to an ADC_AnalogWDGConfTypeDef structure \n  *         that contains the configuration information of ADC analog watchdog.\n  * @retval HAL status\t  \n  */\nHAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)\n{\n#ifdef USE_FULL_ASSERT  \n  uint32_t tmp = 0U;\n#endif /* USE_FULL_ASSERT  */  \n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode));\n  assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));\n  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));\n\n#ifdef USE_FULL_ASSERT  \n  tmp = ADC_GET_RESOLUTION(hadc);\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold));\n  assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold));\n#endif /* USE_FULL_ASSERT  */\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  if(AnalogWDGConfig->ITMode == ENABLE)\n  {\n    /* Enable the ADC Analog watchdog interrupt */\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);\n  }\n  else\n  {\n    /* Disable the ADC Analog watchdog interrupt */\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);\n  }\n  \n  /* Clear AWDEN, JAWDEN and AWDSGL bits */\n  hadc->Instance->CR1 &=  ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN);\n  \n  /* Set the analog watchdog enable mode */\n  hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode;\n  \n  /* Set the high threshold */\n  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;\n  \n  /* Set the low threshold */\n  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;\n  \n  /* Clear the Analog watchdog channel select bits */\n  hadc->Instance->CR1 &= ~ADC_CR1_AWDCH;\n  \n  /* Set the Analog watchdog channel */\n  hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel));\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions\n *  @brief   ADC Peripheral State functions \n *\n@verbatim   \n ===============================================================================\n            ##### Peripheral State and errors functions #####\n ===============================================================================  \n    [..]\n    This subsection provides functions allowing to\n      (+) Check the ADC state\n      (+) Check the ADC Error\n         \n@endverbatim\n  * @{\n  */\n  \n/**\n  * @brief  return the ADC state\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL state\n  */\nuint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)\n{\n  /* Return ADC state */\n  return hadc->State;\n}\n\n/**\n  * @brief  Return the ADC error code\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval ADC Error Code\n  */\nuint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)\n{\n  return hadc->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup ADC_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Initializes the ADCx peripheral according to the specified parameters \n  *         in the ADC_InitStruct without initializing the ADC MSP.       \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.  \n  * @retval None\n  */\nstatic void ADC_Init(ADC_HandleTypeDef* hadc)\n{\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Set ADC parameters */\n  /* Pointer to the common control register to which is belonging hadc    */\n  /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */\n  /* control register)                                                    */\n  tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n  \n  /* Set the ADC clock prescaler */\n  tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);\n  tmpADC_Common->CCR |=  hadc->Init.ClockPrescaler;\n  \n  /* Set ADC scan mode */\n  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);\n  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);\n  \n  /* Set ADC resolution */\n  hadc->Instance->CR1 &= ~(ADC_CR1_RES);\n  hadc->Instance->CR1 |=  hadc->Init.Resolution;\n  \n  /* Set ADC data alignment */\n  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);\n  hadc->Instance->CR2 |= hadc->Init.DataAlign;\n  \n  /* Enable external trigger if trigger selection is different of software  */\n  /* start.                                                                 */\n  /* Note: This configuration keeps the hardware feature of parameter       */\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\n  /*       software start.                                                  */\n  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)\n  {\n    /* Select external trigger to start conversion */\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;\n    \n    /* Select external trigger polarity */\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\n    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;\n  }\n  else\n  {\n    /* Reset the external trigger */\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);\n    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);\n  }\n  \n  /* Enable or disable ADC continuous conversion mode */\n  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);\n  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);\n  \n  if(hadc->Init.DiscontinuousConvMode != DISABLE)\n  {\n    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));\n  \n    /* Enable the selected ADC regular discontinuous mode */\n    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;\n    \n    /* Set the number of channels to be converted in discontinuous mode */\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);\n    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);\n  }\n  else\n  {\n    /* Disable the selected ADC regular discontinuous mode */\n    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);\n  }\n  \n  /* Set ADC number of conversion */\n  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);\n  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);\n  \n  /* Enable or disable ADC DMA continuous request */\n  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);\n  hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);\n  \n  /* Enable or disable ADC end of conversion selection */\n  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);\n  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);\n}\n\n/**\n  * @brief  DMA transfer complete callback. \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)   \n{\n  /* Retrieve ADC handle corresponding to current DMA handle */\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  \n  /* Update state machine on conversion status if not in error state */\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\n  {\n    /* Update ADC state machine */\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\n    \n    /* Determine whether any further conversion upcoming on group regular   */\n    /* by external trigger, continuous mode or scan sequence on going.      */\n    /* Note: On STM32F4, there is no independent flag of end of sequence.   */\n    /*       The test of scan sequence on going is done either with scan    */\n    /*       sequence disabled or with end of conversion flag set to        */\n    /*       of end of sequence.                                            */\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\n    {\n      /* Disable ADC end of single conversion interrupt on group regular */\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\n      /* by overrun IRQ process below.                                      */\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\n      \n      /* Set ADC state */\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \n      \n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n      {\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n      }\n    }\n    \n    /* Conversion complete callback */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n    hadc->ConvCpltCallback(hadc);\n#else\n    HAL_ADC_ConvCpltCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n  }\n  else /* DMA and-or internal error occurred */\n  {\n    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)\n    {\n      /* Call HAL ADC Error Callback function */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n      hadc->ErrorCallback(hadc);\n#else\n      HAL_ADC_ErrorCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n    }\n\telse\n\t{\n      /* Call DMA error callback */\n      hadc->DMA_Handle->XferErrorCallback(hdma);\n    }\n  }\n}\n\n/**\n  * @brief  DMA half transfer complete callback. \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \n{\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n   /* Half conversion callback */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n  hadc->ConvHalfCpltCallback(hadc);\n#else\n  HAL_ADC_ConvHalfCpltCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA error callback \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_DMAError(DMA_HandleTypeDef *hdma)   \n{\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  hadc->State= HAL_ADC_STATE_ERROR_DMA;\n  /* Set ADC error code to DMA error */\n  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\n   /* Error callback */\n#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)\n  hadc->ErrorCallback(hadc);\n#else\n  HAL_ADC_ErrorCallback(hadc);\n#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_ADC_MODULE_ENABLED */\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_adc_ex.c\n  * @author  MCD Application Team\n  * @brief   This file provides firmware functions to manage the following\n  *          functionalities of the ADC extension peripheral:\n  *           + Extended features functions\n  *\n  @verbatim\n  ==============================================================================\n                    ##### How to use this driver #####\n  ==============================================================================\n    [..]\n    (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit():\n       (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE()\n       (##) ADC pins configuration\n             (+++) Enable the clock for the ADC GPIOs using the following function:\n                   __HAL_RCC_GPIOx_CLK_ENABLE()\n             (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init()\n       (##) In case of using interrupts (e.g. HAL_ADC_Start_IT())\n             (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority()\n             (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ()\n             (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler()\n      (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA())\n             (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE()\n             (+++) Configure and enable two DMA streams stream for managing data\n                 transfer from peripheral to memory (output stream)\n             (+++) Associate the initialized DMA handle to the ADC DMA handle\n                 using  __HAL_LINKDMA()\n             (+++) Configure the priority and enable the NVIC for the transfer complete\n                 interrupt on the two DMA Streams. The output stream should have higher\n                 priority than the input stream.\n     (#) Configure the ADC Prescaler, conversion resolution and data alignment\n         using the HAL_ADC_Init() function.\n\n     (#) Configure the ADC Injected channels group features, use HAL_ADC_Init()\n         and HAL_ADC_ConfigChannel() functions.\n\n     (#) Three operation modes are available within this driver:\n\n     *** Polling mode IO operation ***\n     =================================\n     [..]\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart()\n       (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage\n           user can specify the value of timeout according to his end application\n       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function.\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop()\n\n     *** Interrupt mode IO operation ***\n     ===================================\n     [..]\n       (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT()\n       (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine\n       (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can\n            add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback \n       (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can \n            add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback\n       (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT()\n\n     *** Multi mode ADCs Regular channels configuration ***\n     ======================================================\n     [..]\n       (+) Select the Multi mode ADC regular channels features (dual or triple mode)\n          and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions.\n       (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length\n           of data to be transferred at each end of conversion\n       (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function.\n\n\n    @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup ADCEx ADCEx\n  * @brief ADC Extended driver modules\n  * @{\n  */ \n\n#ifdef HAL_ADC_MODULE_ENABLED\n    \n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/ \n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup ADCEx_Private_Functions\n  * @{\n  */\n/* Private function prototypes -----------------------------------------------*/\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma);\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma);\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); \n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup ADCEx_Exported_Functions ADC Exported Functions\n  * @{\n  */\n\n/** @defgroup ADCEx_Exported_Functions_Group1  Extended features functions \n  *  @brief    Extended features functions  \n  *\n@verbatim   \n ===============================================================================\n                 ##### Extended features functions #####\n ===============================================================================  \n    [..]  This section provides functions allowing to:\n      (+) Start conversion of injected channel.\n      (+) Stop conversion of injected channel.\n      (+) Start multimode and enable DMA transfer.\n      (+) Stop multimode and disable DMA transfer.\n      (+) Get result of injected channel conversion.\n      (+) Get result of multimode conversion.\n      (+) Configure injected channels.\n      (+) Configure multimode.\n               \n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Enables the selected ADC software start conversion of the injected channels.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)\n{\n  __IO uint32_t counter = 0U;\n  uint32_t tmp1 = 0U, tmp2 = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Enable the ADC peripheral */\n  \n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n     Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for ADC stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to injected group conversion results    */\n    /* - Set state bitfield related to injected operation                     */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\n                      HAL_ADC_STATE_INJ_BUSY);\n    \n    /* Check if a regular conversion is ongoing */\n    /* Note: On this device, there is no ADC error code fields related to     */\n    /*       conversions on group injected only. In case of conversion on     */\n    /*       going on group regular, no error code is reset.                  */\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    }\n    \n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);\n    \n    /* Clear injected group conversion flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n    /* Check if Multimode enabled */\n    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))\n    {\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\n      if(tmp1 && tmp2)\n      {\n        /* Enable the selected ADC software conversion for injected group */\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\n      }\n    }\n    else\n    {\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \n      {\n        /* Enable the selected ADC software conversion for injected group */\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\n      }\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Enables the interrupt and starts ADC conversion of injected channels.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  *\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)\n{\n  __IO uint32_t counter = 0U;\n  uint32_t tmp1 = 0U, tmp2 = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Enable the ADC peripheral */\n  \n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n     Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for ADC stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to injected group conversion results    */\n    /* - Set state bitfield related to injected operation                     */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,\n                      HAL_ADC_STATE_INJ_BUSY);\n    \n    /* Check if a regular conversion is ongoing */\n    /* Note: On this device, there is no ADC error code fields related to     */\n    /*       conversions on group injected only. In case of conversion on     */\n    /*       going on group regular, no error code is reset.                  */\n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    }\n    \n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);\n    \n    /* Clear injected group conversion flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\n    \n    /* Enable end of conversion interrupt for injected channels */\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n    \n    /* Check if Multimode enabled */\n    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))\n    {\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\n      if(tmp1 && tmp2)\n      {\n        /* Enable the selected ADC software conversion for injected group */\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\n      }\n    }\n    else\n    {\n      tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN);\n      tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO);\n      if((hadc->Instance == ADC1) && tmp1 && tmp2)  \n      {\n        /* Enable the selected ADC software conversion for injected group */\n        hadc->Instance->CR2 |= ADC_CR2_JSWSTART;\n      }\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stop conversion of injected channels. Disable ADC peripheral if\n  *         no regular conversion is on going.\n  * @note   If ADC must be disabled and if conversion is on going on \n  *         regular group, function HAL_ADC_Stop must be used to stop both\n  *         injected and regular groups, and disable the ADC.\n  * @note   If injected group mode auto-injection is enabled,\n  *         function HAL_ADC_Stop must be used.\n  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.\n  * @param  hadc ADC handle\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n\n  /* Process locked */\n  __HAL_LOCK(hadc);\n    \n  /* Stop potential conversion and disable ADC peripheral                     */\n  /* Conditioned to:                                                          */\n  /* - No conversion on the other group (regular group) is intended to        */\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\n  /*   are common)                                                            */\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */\n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\n  {\n    /* Stop potential conversion on going, on regular and injected groups */\n    /* Disable ADC peripheral */\n    __HAL_ADC_DISABLE(hadc);\n    \n    /* Check if ADC is effectively disabled */\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n    {\n      /* Set ADC state */\n      ADC_STATE_CLR_SET(hadc->State,\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                        HAL_ADC_STATE_READY);\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\n      \n    tmp_hal_status = HAL_ERROR;\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return tmp_hal_status;\n}\n\n/**\n  * @brief  Poll for injected conversion complete\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  Timeout Timeout value in millisecond.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)\n{\n  uint32_t tickstart = 0U;\n\n  /* Get tick */ \n  tickstart = HAL_GetTick();\n\n  /* Check End of conversion flag */\n  while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\n  {\n    /* Check for the Timeout */\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        /* New check to avoid false timeout detection in case of preemption */\n        if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC)))\n        {\n          hadc->State= HAL_ADC_STATE_TIMEOUT;\n          /* Process unlocked */\n          __HAL_UNLOCK(hadc);\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n  \n  /* Clear injected group conversion flag */\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);\n    \n  /* Update ADC state machine */\n  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);\n  \n  /* Determine whether any further conversion upcoming on group injected      */\n  /* by external trigger, continuous mode or scan sequence on going.          */\n  /* Note: On STM32F4, there is no independent flag of end of sequence.       */\n  /*       The test of scan sequence on going is done either with scan        */\n  /*       sequence disabled or with end of conversion flag set to            */\n  /*       of end of sequence.                                                */\n  if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&\n     (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||\n      HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&\n     (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&\n      (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&\n      (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )\n  {\n    /* Set ADC state */\n    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);\n    \n    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))\n    { \n      SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n    }\n  }\n  \n  /* Return ADC state */\n  return HAL_OK;\n}      \n  \n/**\n  * @brief  Stop conversion of injected channels, disable interruption of \n  *         end-of-conversion. Disable ADC peripheral if no regular conversion\n  *         is on going.\n  * @note   If ADC must be disabled and if conversion is on going on \n  *         regular group, function HAL_ADC_Stop must be used to stop both\n  *         injected and regular groups, and disable the ADC.\n  * @note   If injected group mode auto-injection is enabled,\n  *         function HAL_ADC_Stop must be used.\n  * @param  hadc ADC handle\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n\n  /* Process locked */\n  __HAL_LOCK(hadc);\n    \n  /* Stop potential conversion and disable ADC peripheral                     */\n  /* Conditioned to:                                                          */\n  /* - No conversion on the other group (regular group) is intended to        */\n  /*   continue (injected and regular groups stop conversion and ADC disable  */\n  /*   are common)                                                            */\n  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ \n  if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET)  &&\n     HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )\n  {\n    /* Stop potential conversion on going, on regular and injected groups */\n    /* Disable ADC peripheral */\n    __HAL_ADC_DISABLE(hadc);\n    \n    /* Check if ADC is effectively disabled */\n    if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n    {\n      /* Disable ADC end of conversion interrupt for injected channels */\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);\n      \n      /* Set ADC state */\n      ADC_STATE_CLR_SET(hadc->State,\n                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                        HAL_ADC_STATE_READY);\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);\n      \n    tmp_hal_status = HAL_ERROR;\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return tmp_hal_status;\n}\n\n/**\n  * @brief  Gets the converted value from data register of injected channel.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  InjectedRank the ADC injected rank.\n  *          This parameter can be one of the following values:\n  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected\n  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected\n  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected\n  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected\n  * @retval None\n  */\nuint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)\n{\n  __IO uint32_t tmp = 0U;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));\n  \n  /* Clear injected group conversion flag to have similar behaviour as        */\n  /* regular group: reading data register also clears end of conversion flag. */\n  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);\n  \n  /* Return the selected ADC converted value */ \n  switch(InjectedRank)\n  {  \n    case ADC_INJECTED_RANK_4:\n    {\n      tmp =  hadc->Instance->JDR4;\n    }  \n    break;\n    case ADC_INJECTED_RANK_3: \n    {  \n      tmp =  hadc->Instance->JDR3;\n    }  \n    break;\n    case ADC_INJECTED_RANK_2: \n    {  \n      tmp =  hadc->Instance->JDR2;\n    }\n    break;\n    case ADC_INJECTED_RANK_1:\n    {\n      tmp =  hadc->Instance->JDR1;\n    }\n    break;\n    default:\n    break;  \n  }\n  return tmp;\n}\n\n/**\n  * @brief  Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral\n  * \n  * @note   Caution: This function must be used only with the ADC master.  \n  *\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  pData   Pointer to buffer in which transferred from ADC peripheral to memory will be stored. \n  * @param  Length  The length of data to be transferred from ADC peripheral to memory.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)\n{\n  __IO uint32_t counter = 0U;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));\n  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));\n  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Check if ADC peripheral is disabled in order to enable it and wait during \n     Tstab time the ADC's stabilization */\n  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)\n  {  \n    /* Enable the Peripheral */\n    __HAL_ADC_ENABLE(hadc);\n    \n    /* Delay for temperature sensor stabilization time */\n    /* Compute number of CPU cycles to wait for */\n    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));\n    while(counter != 0U)\n    {\n      counter--;\n    }\n  }\n  \n  /* Start conversion if ADC is effectively enabled */\n  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Set ADC state                                                          */\n    /* - Clear state bitfield related to regular group conversion results     */\n    /* - Set state bitfield related to regular group operation                */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,\n                      HAL_ADC_STATE_REG_BUSY);\n    \n    /* If conversions on group regular are also triggering group injected,    */\n    /* update ADC state.                                                      */\n    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)\n    {\n      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  \n    }\n    \n    /* State machine update: Check if an injected conversion is ongoing */\n    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n    {\n      /* Reset ADC error code fields related to conversions on group regular */\n      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         \n    }\n    else\n    {\n      /* Reset ADC all error code fields */\n      ADC_CLEAR_ERRORCODE(hadc);\n    }\n    \n    /* Process unlocked */\n    /* Unlock before starting ADC conversions: in case of potential           */\n    /* interruption, to let the process to ADC IRQ Handler.                   */\n    __HAL_UNLOCK(hadc);\n    \n    /* Set the DMA transfer complete callback */\n    hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt;\n    \n    /* Set the DMA half transfer complete callback */\n    hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt;\n    \n    /* Set the DMA error callback */\n    hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ;\n    \n    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */\n    /* start (in case of SW start):                                           */\n    \n    /* Clear regular group conversion flag and overrun flag */\n    /* (To ensure of no unknown state from potential previous ADC operations) */\n    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);\n\n    /* Enable ADC overrun interrupt */\n    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);\n\n    /* Pointer to the common control register to which is belonging hadc    */\n    /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n    /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n    if (hadc->Init.DMAContinuousRequests != DISABLE)\n    {\n      /* Enable the selected ADC DMA request after last transfer */\n      tmpADC_Common->CCR |= ADC_CCR_DDS;\n    }\n    else\n    {\n      /* Disable the selected ADC EOC rising on each regular channel conversion */\n      tmpADC_Common->CCR &= ~ADC_CCR_DDS;\n    }\n    \n    /* Enable the DMA Stream */\n    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);\n    \n    /* if no external trigger present enable software conversion of regular channels */\n    if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) \n    {\n      /* Enable the selected ADC software conversion for regular group */\n      hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;\n    }\n  }\n  else\n  {\n    /* Update ADC state machine to error */\n    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);\n\n    /* Set ADC error code to ADC IP internal error */\n    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);\n  }\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Disables ADC DMA (multi-ADC mode) and disables ADC peripheral    \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)\n{\n  HAL_StatusTypeDef tmp_hal_status = HAL_OK;\n  ADC_Common_TypeDef *tmpADC_Common;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* Stop potential conversion on going, on regular and injected groups */\n  /* Disable ADC peripheral */\n  __HAL_ADC_DISABLE(hadc);\n\n  /* Pointer to the common control register to which is belonging hadc    */\n  /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n  /* control register)                                                    */\n  tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n  /* Check if ADC is effectively disabled */\n  if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))\n  {\n    /* Disable the selected ADC DMA mode for multimode */\n    tmpADC_Common->CCR &= ~ADC_CCR_DDS;\n    \n    /* Disable the DMA channel (in case of DMA in circular mode or stop while */\n    /* DMA transfer is on going)                                              */\n    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);\n    \n    /* Disable ADC overrun interrupt */\n    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);\n    \n    /* Set ADC state */\n    ADC_STATE_CLR_SET(hadc->State,\n                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,\n                      HAL_ADC_STATE_READY);\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return tmp_hal_status;\n}\n\n/**\n  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results \n  *         data in the selected multi mode.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval The converted data value.\n  */\nuint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)\n{\n  ADC_Common_TypeDef *tmpADC_Common;\n\n  /* Pointer to the common control register to which is belonging hadc    */\n  /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n  /* control register)                                                    */\n  tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n  /* Return the multi mode conversion value */\n  return tmpADC_Common->CDR;\n}\n\n/**\n  * @brief  Injected conversion complete callback in non blocking mode \n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @retval None\n  */\n__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hadc);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Configures for the selected ADC injected channel its corresponding\n  *         rank in the sequencer and its sample time.\n  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains\n  *         the configuration information for the specified ADC.\n  * @param  sConfigInjected ADC configuration structure for injected channel. \n  * @retval None\n  */\nHAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)\n{\n  \n#ifdef USE_FULL_ASSERT  \n  uint32_t tmp = 0U;\n  \n#endif /* USE_FULL_ASSERT  */\n\n  ADC_Common_TypeDef *tmpADC_Common;\n\n  /* Check the parameters */\n  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));\n  assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));\n  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));\n  assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv));\n  assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion));\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));\n  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));\n\n#ifdef USE_FULL_ASSERT\n  tmp = ADC_GET_RESOLUTION(hadc);\n  assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset));\n#endif /* USE_FULL_ASSERT  */\n\n  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\n  {\n    assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hadc);\n  \n  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */\n  if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9)\n  {\n    /* Clear the old sample time */\n    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel);\n    \n    /* Set the new sample time */\n    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\n  }\n  else /* ADC_Channel include in ADC_Channel_[0..9] */\n  {\n    /* Clear the old sample time */\n    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel);\n    \n    /* Set the new sample time */\n    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);\n  }\n  \n  /*---------------------------- ADCx JSQR Configuration -----------------*/\n  hadc->Instance->JSQR &= ~(ADC_JSQR_JL);\n  hadc->Instance->JSQR |=  ADC_SQR1(sConfigInjected->InjectedNbrOfConversion);\n  \n  /* Rank configuration */\n  \n  /* Clear the old SQx bits for the selected rank */\n  hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\n   \n  /* Set the SQx bits for the selected rank */\n  hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion);\n\n  /* Enable external trigger if trigger selection is different of software  */\n  /* start.                                                                 */\n  /* Note: This configuration keeps the hardware feature of parameter       */\n  /*       ExternalTrigConvEdge \"trigger edge none\" equivalent to           */\n  /*       software start.                                                  */ \n  if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)\n  {  \n    /* Select external trigger to start conversion */\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\n    hadc->Instance->CR2 |=  sConfigInjected->ExternalTrigInjecConv;\n    \n    /* Select external trigger polarity */\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);\n    hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge;\n  }\n  else\n  {\n    /* Reset the external trigger */\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL);\n    hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN);  \n  }\n  \n  if (sConfigInjected->AutoInjectedConv != DISABLE)\n  {\n    /* Enable the selected ADC automatic injected group conversion */\n    hadc->Instance->CR1 |= ADC_CR1_JAUTO;\n  }\n  else\n  {\n    /* Disable the selected ADC automatic injected group conversion */\n    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO);\n  }\n  \n  if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE)\n  {\n    /* Enable the selected ADC injected discontinuous mode */\n    hadc->Instance->CR1 |= ADC_CR1_JDISCEN;\n  }\n  else\n  {\n    /* Disable the selected ADC injected discontinuous mode */\n    hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN);\n  }\n  \n  switch(sConfigInjected->InjectedRank)\n  {\n    case 1U:\n      /* Set injected channel 1 offset */\n      hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1);\n      hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset;\n      break;\n    case 2U:\n      /* Set injected channel 2 offset */\n      hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2);\n      hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset;\n      break;\n    case 3U:\n      /* Set injected channel 3 offset */\n      hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3);\n      hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset;\n      break;\n    default:\n      /* Set injected channel 4 offset */\n      hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4);\n      hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset;\n      break;\n  }\n\n  /* Pointer to the common control register to which is belonging hadc    */\n  /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n  /* control register)                                                    */\n    tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n  /* if ADC1 Channel_18 is selected enable VBAT Channel */\n  if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT))\n  {\n    /* Enable the VBAT channel*/\n    tmpADC_Common->CCR |= ADC_CCR_VBATE;\n  }\n  \n  /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */\n  if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)))\n  {\n    /* Enable the TSVREFE channel*/\n    tmpADC_Common->CCR |= ADC_CCR_TSVREFE;\n  }\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the ADC multi-mode \n  * @param  hadc       pointer to a ADC_HandleTypeDef structure that contains\n  *                     the configuration information for the specified ADC.  \n  * @param  multimode  pointer to an ADC_MultiModeTypeDef structure that contains \n  *                     the configuration information for  multimode.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)\n{\n\n  ADC_Common_TypeDef *tmpADC_Common;\n\n  /* Check the parameters */\n  assert_param(IS_ADC_MODE(multimode->Mode));\n  assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode));\n  assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));\n  \n  /* Process locked */\n  __HAL_LOCK(hadc);\n\n  /* Pointer to the common control register to which is belonging hadc    */\n  /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */\n  /* control register)                                                    */\n  tmpADC_Common = ADC_COMMON_REGISTER(hadc);\n\n  /* Set ADC mode */\n  tmpADC_Common->CCR &= ~(ADC_CCR_MULTI);\n  tmpADC_Common->CCR |= multimode->Mode;\n  \n  /* Set the ADC DMA access mode */\n  tmpADC_Common->CCR &= ~(ADC_CCR_DMA);\n  tmpADC_Common->CCR |= multimode->DMAAccessMode;\n  \n  /* Set delay between two sampling phases */\n  tmpADC_Common->CCR &= ~(ADC_CCR_DELAY);\n  tmpADC_Common->CCR |= multimode->TwoSamplingDelay;\n  \n  /* Process unlocked */\n  __HAL_UNLOCK(hadc);\n  \n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @brief  DMA transfer complete callback. \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma)   \n{\n  /* Retrieve ADC handle corresponding to current DMA handle */\n  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n  \n  /* Update state machine on conversion status if not in error state */\n  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))\n  {\n    /* Update ADC state machine */\n    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);\n    \n    /* Determine whether any further conversion upcoming on group regular   */\n    /* by external trigger, continuous mode or scan sequence on going.      */\n    /* Note: On STM32F4, there is no independent flag of end of sequence.   */\n    /*       The test of scan sequence on going is done either with scan    */\n    /*       sequence disabled or with end of conversion flag set to        */\n    /*       of end of sequence.                                            */\n    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&\n       (hadc->Init.ContinuousConvMode == DISABLE)            &&\n       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || \n        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )\n    {\n      /* Disable ADC end of single conversion interrupt on group regular */\n      /* Note: Overrun interrupt was enabled with EOC interrupt in          */\n      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */\n      /* by overrun IRQ process below.                                      */\n      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);\n      \n      /* Set ADC state */\n      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);   \n      \n      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))\n      {\n        SET_BIT(hadc->State, HAL_ADC_STATE_READY);\n      }\n    }\n    \n    /* Conversion complete callback */\n    HAL_ADC_ConvCpltCallback(hadc);\n  }\n  else\n  {\n    /* Call DMA error callback */\n    hadc->DMA_Handle->XferErrorCallback(hdma);\n  }\n}\n\n/**\n  * @brief  DMA half transfer complete callback. \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma)   \n{\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n    /* Conversion complete callback */\n    HAL_ADC_ConvHalfCpltCallback(hadc); \n}\n\n/**\n  * @brief  DMA error callback \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *                the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma)   \n{\n    ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;\n    hadc->State= HAL_ADC_STATE_ERROR_DMA;\n    /* Set ADC error code to DMA error */\n    hadc->ErrorCode |= HAL_ADC_ERROR_DMA;\n    HAL_ADC_ErrorCallback(hadc); \n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_ADC_MODULE_ENABLED */\n/**\n  * @}\n  */ \n\n/**\n  * @}\n  */ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_can.c\n  * @author  MCD Application Team\n  * @brief   CAN HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Controller Area Network (CAN) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + Configuration functions\n  *           + Control functions\n  *           + Interrupts management\n  *           + Callbacks functions\n  *           + Peripheral State and Error functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      (#) Initialize the CAN low level resources by implementing the\n          HAL_CAN_MspInit():\n         (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()\n         (++) Configure CAN pins\n             (+++) Enable the clock for the CAN GPIOs\n             (+++) Configure CAN pins as alternate function open-drain\n         (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())\n             (+++) Configure the CAN interrupt priority using\n                   HAL_NVIC_SetPriority()\n             (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()\n             (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()\n\n      (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This\n          function resorts to HAL_CAN_MspInit() for low-level initialization.\n\n      (#) Configure the reception filters using the following configuration\n          functions:\n            (++) HAL_CAN_ConfigFilter()\n\n      (#) Start the CAN module using HAL_CAN_Start() function. At this level\n          the node is active on the bus: it receive messages, and can send\n          messages.\n\n      (#) To manage messages transmission, the following Tx control functions\n          can be used:\n            (++) HAL_CAN_AddTxMessage() to request transmission of a new\n                 message.\n            (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending\n                 message.\n            (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx\n                 mailboxes.\n            (++) HAL_CAN_IsTxMessagePending() to check if a message is pending\n                 in a Tx mailbox.\n            (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message\n                 sent, if time triggered communication mode is enabled.\n\n      (#) When a message is received into the CAN Rx FIFOs, it can be retrieved\n          using the HAL_CAN_GetRxMessage() function. The function\n          HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are\n          stored in the Rx Fifo.\n\n      (#) Calling the HAL_CAN_Stop() function stops the CAN module.\n\n      (#) The deinitialization is achieved with HAL_CAN_DeInit() function.\n\n\n      *** Polling mode operation ***\n      ==============================\n    [..]\n      (#) Reception:\n            (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()\n                 until at least one message is received.\n            (++) Then get the message using HAL_CAN_GetRxMessage().\n\n      (#) Transmission:\n            (++) Monitor the Tx mailboxes availability until at least one Tx\n                 mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().\n            (++) Then request transmission of a message using\n                 HAL_CAN_AddTxMessage().\n\n\n      *** Interrupt mode operation ***\n      ================================\n    [..]\n      (#) Notifications are activated using HAL_CAN_ActivateNotification()\n          function. Then, the process can be controlled through the\n          available user callbacks: HAL_CAN_xxxCallback(), using same APIs\n          HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().\n\n      (#) Notifications can be deactivated using\n          HAL_CAN_DeactivateNotification() function.\n\n      (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and\n          CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig\n          the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and\n          HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options\n          here.\n            (++) Directly get the Rx message in the callback, using\n                 HAL_CAN_GetRxMessage().\n            (++) Or deactivate the notification in the callback without\n                 getting the Rx message. The Rx message can then be got later\n                 using HAL_CAN_GetRxMessage(). Once the Rx message have been\n                 read, the notification can be activated again.\n\n\n      *** Sleep mode ***\n      ==================\n    [..]\n      (#) The CAN peripheral can be put in sleep mode (low power), using\n          HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the\n          current CAN activity (transmission or reception of a CAN frame) will\n          be completed.\n\n      (#) A notification can be activated to be informed when the sleep mode\n          will be entered.\n\n      (#) It can be checked if the sleep mode is entered using\n          HAL_CAN_IsSleepActive().\n          Note that the CAN state (accessible from the API HAL_CAN_GetState())\n          is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is\n          submitted (the sleep mode is not yet entered), and become\n          HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.\n\n      (#) The wake-up from sleep mode can be triggered by two ways:\n            (++) Using HAL_CAN_WakeUp(). When returning from this function,\n                 the sleep mode is exited (if return status is HAL_OK).\n            (++) When a start of Rx CAN frame is detected by the CAN peripheral,\n                 if automatic wake up mode is enabled.\n\n  *** Callback registration ***\n  =============================================\n\n  The compilation define  USE_HAL_CAN_REGISTER_CALLBACKS when set to 1\n  allows the user to configure dynamically the driver callbacks.\n  Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback.\n\n  Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks:\n    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.\n    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.\n    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.\n    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.\n    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.\n    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.\n    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.\n    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.\n    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.\n    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.\n    (+) SleepCallback                : Sleep Callback.\n    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.\n    (+) ErrorCallback                : Error Callback.\n    (+) MspInitCallback              : CAN MspInit.\n    (+) MspDeInitCallback            : CAN MspDeInit.\n  This function takes as parameters the HAL peripheral handle, the Callback ID\n  and a pointer to the user callback function.\n\n  Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default\n  weak function.\n  @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,\n  and the Callback ID.\n  This function allows to reset following callbacks:\n    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.\n    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.\n    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.\n    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.\n    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.\n    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.\n    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.\n    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.\n    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.\n    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.\n    (+) SleepCallback                : Sleep Callback.\n    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.\n    (+) ErrorCallback                : Error Callback.\n    (+) MspInitCallback              : CAN MspInit.\n    (+) MspDeInitCallback            : CAN MspDeInit.\n\n  By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,\n  all callbacks are set to the corresponding weak functions:\n  example @ref HAL_CAN_ErrorCallback().\n  Exception done for MspInit and MspDeInit functions that are\n  reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when\n  these callbacks are null (not registered beforehand).\n  if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit()\n  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)\n\n  Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.\n  Exception done MspInit/MspDeInit that can be registered/unregistered\n  in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,\n  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\n  In that case first register the MspInit/MspDeInit user callbacks\n  using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit()\n  or @ref HAL_CAN_Init() function.\n\n  When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or\n  not defined, the callback registration feature is not available and all callbacks\n  are set to the corresponding weak functions.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n#if defined(CAN1)\n\n/** @defgroup CAN CAN\n  * @brief CAN driver modules\n  * @{\n  */\n\n#ifdef HAL_CAN_MODULE_ENABLED\n\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\n  #error \"The CAN driver cannot be used with its legacy, Please enable only one CAN module at once\"\n#endif\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @defgroup CAN_Private_Constants CAN Private Constants\n  * @{\n  */\n#define CAN_TIMEOUT_VALUE 10U\n/**\n  * @}\n  */\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup CAN_Exported_Functions CAN Exported Functions\n  * @{\n  */\n\n/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions\n *\n@verbatim\n  ==============================================================================\n              ##### Initialization and de-initialization functions #####\n  ==============================================================================\n    [..]  This section provides functions allowing to:\n      (+) HAL_CAN_Init                       : Initialize and configure the CAN.\n      (+) HAL_CAN_DeInit                     : De-initialize the CAN.\n      (+) HAL_CAN_MspInit                    : Initialize the CAN MSP.\n      (+) HAL_CAN_MspDeInit                  : DeInitialize the CAN MSP.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the CAN peripheral according to the specified\n  *         parameters in the CAN_InitStruct.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)\n{\n  uint32_t tickstart;\n\n  /* Check CAN handle */\n  if (hcan == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));\n  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));\n  assert_param(IS_CAN_MODE(hcan->Init.Mode));\n  assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));\n  assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));\n  assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));\n  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n  if (hcan->State == HAL_CAN_STATE_RESET)\n  {\n    /* Reset callbacks to legacy functions */\n    hcan->RxFifo0MsgPendingCallback  =  HAL_CAN_RxFifo0MsgPendingCallback;  /* Legacy weak RxFifo0MsgPendingCallback  */\n    hcan->RxFifo0FullCallback        =  HAL_CAN_RxFifo0FullCallback;        /* Legacy weak RxFifo0FullCallback        */\n    hcan->RxFifo1MsgPendingCallback  =  HAL_CAN_RxFifo1MsgPendingCallback;  /* Legacy weak RxFifo1MsgPendingCallback  */\n    hcan->RxFifo1FullCallback        =  HAL_CAN_RxFifo1FullCallback;        /* Legacy weak RxFifo1FullCallback        */\n    hcan->TxMailbox0CompleteCallback =  HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */\n    hcan->TxMailbox1CompleteCallback =  HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */\n    hcan->TxMailbox2CompleteCallback =  HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */\n    hcan->TxMailbox0AbortCallback    =  HAL_CAN_TxMailbox0AbortCallback;    /* Legacy weak TxMailbox0AbortCallback    */\n    hcan->TxMailbox1AbortCallback    =  HAL_CAN_TxMailbox1AbortCallback;    /* Legacy weak TxMailbox1AbortCallback    */\n    hcan->TxMailbox2AbortCallback    =  HAL_CAN_TxMailbox2AbortCallback;    /* Legacy weak TxMailbox2AbortCallback    */\n    hcan->SleepCallback              =  HAL_CAN_SleepCallback;              /* Legacy weak SleepCallback              */\n    hcan->WakeUpFromRxMsgCallback    =  HAL_CAN_WakeUpFromRxMsgCallback;    /* Legacy weak WakeUpFromRxMsgCallback    */\n    hcan->ErrorCallback              =  HAL_CAN_ErrorCallback;              /* Legacy weak ErrorCallback              */\n\n    if (hcan->MspInitCallback == NULL)\n    {\n      hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */\n    }\n\n    /* Init the low level hardware: CLOCK, NVIC */\n    hcan->MspInitCallback(hcan);\n  }\n\n#else\n  if (hcan->State == HAL_CAN_STATE_RESET)\n  {\n    /* Init the low level hardware: CLOCK, NVIC */\n    HAL_CAN_MspInit(hcan);\n  }\n#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */\n\n  /* Exit from sleep mode */\n  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  /* Check Sleep mode leave acknowledge */\n  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)\n  {\n    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\n    {\n      /* Update error code */\n      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\n\n      /* Change CAN state */\n      hcan->State = HAL_CAN_STATE_ERROR;\n\n      return HAL_ERROR;\n    }\n  }\n\n  /* Request initialisation */\n  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  /* Wait initialisation acknowledge */\n  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)\n  {\n    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\n    {\n      /* Update error code */\n      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\n\n      /* Change CAN state */\n      hcan->State = HAL_CAN_STATE_ERROR;\n\n      return HAL_ERROR;\n    }\n  }\n\n  /* Set the time triggered communication mode */\n  if (hcan->Init.TimeTriggeredMode == ENABLE)\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);\n  }\n  else\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);\n  }\n\n  /* Set the automatic bus-off management */\n  if (hcan->Init.AutoBusOff == ENABLE)\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);\n  }\n  else\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);\n  }\n\n  /* Set the automatic wake-up mode */\n  if (hcan->Init.AutoWakeUp == ENABLE)\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);\n  }\n  else\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);\n  }\n\n  /* Set the automatic retransmission */\n  if (hcan->Init.AutoRetransmission == ENABLE)\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);\n  }\n  else\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);\n  }\n\n  /* Set the receive FIFO locked mode */\n  if (hcan->Init.ReceiveFifoLocked == ENABLE)\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);\n  }\n  else\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);\n  }\n\n  /* Set the transmit FIFO priority */\n  if (hcan->Init.TransmitFifoPriority == ENABLE)\n  {\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);\n  }\n  else\n  {\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);\n  }\n\n  /* Set the bit timing register */\n  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |\n                                            hcan->Init.SyncJumpWidth  |\n                                            hcan->Init.TimeSeg1       |\n                                            hcan->Init.TimeSeg2       |\n                                            (hcan->Init.Prescaler - 1U)));\n\n  /* Initialize the error code */\n  hcan->ErrorCode = HAL_CAN_ERROR_NONE;\n\n  /* Initialize the CAN state */\n  hcan->State = HAL_CAN_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Deinitializes the CAN peripheral registers to their default\n  *         reset values.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)\n{\n  /* Check CAN handle */\n  if (hcan == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));\n\n  /* Stop the CAN module */\n  (void)HAL_CAN_Stop(hcan);\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n  if (hcan->MspDeInitCallback == NULL)\n  {\n    hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */\n  }\n\n  /* DeInit the low level hardware: CLOCK, NVIC */\n  hcan->MspDeInitCallback(hcan);\n\n#else\n  /* DeInit the low level hardware: CLOCK, NVIC */\n  HAL_CAN_MspDeInit(hcan);\n#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */\n\n  /* Reset the CAN peripheral */\n  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);\n\n  /* Reset the CAN ErrorCode */\n  hcan->ErrorCode = HAL_CAN_ERROR_NONE;\n\n  /* Change CAN state */\n  hcan->State = HAL_CAN_STATE_RESET;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the CAN MSP.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes the CAN MSP.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_MspDeInit could be implemented in the user file\n   */\n}\n\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n/**\n  * @brief  Register a CAN CallBack.\n  *         To be used instead of the weak predefined callback\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for CAN module\n  * @param  CallbackID ID of the callback to be registered\n  *         This parameter can be one of the following values:\n  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID\n  *           @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID\n  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID\n  *           @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID\n  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID\n  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  if (hcan->State == HAL_CAN_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :\n        hcan->TxMailbox0CompleteCallback = pCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :\n        hcan->TxMailbox1CompleteCallback = pCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :\n        hcan->TxMailbox2CompleteCallback = pCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :\n        hcan->TxMailbox0AbortCallback = pCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :\n        hcan->TxMailbox1AbortCallback = pCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :\n        hcan->TxMailbox2AbortCallback = pCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :\n        hcan->RxFifo0MsgPendingCallback = pCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO0_FULL_CB_ID :\n        hcan->RxFifo0FullCallback = pCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :\n        hcan->RxFifo1MsgPendingCallback = pCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO1_FULL_CB_ID :\n        hcan->RxFifo1FullCallback = pCallback;\n        break;\n\n      case HAL_CAN_SLEEP_CB_ID :\n        hcan->SleepCallback = pCallback;\n        break;\n\n      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :\n        hcan->WakeUpFromRxMsgCallback = pCallback;\n        break;\n\n      case HAL_CAN_ERROR_CB_ID :\n        hcan->ErrorCallback = pCallback;\n        break;\n\n      case HAL_CAN_MSPINIT_CB_ID :\n        hcan->MspInitCallback = pCallback;\n        break;\n\n      case HAL_CAN_MSPDEINIT_CB_ID :\n        hcan->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (hcan->State == HAL_CAN_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_CAN_MSPINIT_CB_ID :\n        hcan->MspInitCallback = pCallback;\n        break;\n\n      case HAL_CAN_MSPDEINIT_CB_ID :\n        hcan->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Unregister a CAN CallBack.\n  *         CAN callabck is redirected to the weak predefined callback\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for CAN module\n  * @param  CallbackID ID of the callback to be unregistered\n  *         This parameter can be one of the following values:\n  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID\n  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID\n  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID\n  *           @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID\n  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID\n  *           @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID\n  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID\n  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (hcan->State == HAL_CAN_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :\n        hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :\n        hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :\n        hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :\n        hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :\n        hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;\n        break;\n\n      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :\n        hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :\n        hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO0_FULL_CB_ID :\n        hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :\n        hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;\n        break;\n\n      case HAL_CAN_RX_FIFO1_FULL_CB_ID :\n        hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;\n        break;\n\n      case HAL_CAN_SLEEP_CB_ID :\n        hcan->SleepCallback = HAL_CAN_SleepCallback;\n        break;\n\n      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :\n        hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;\n        break;\n\n      case HAL_CAN_ERROR_CB_ID :\n        hcan->ErrorCallback = HAL_CAN_ErrorCallback;\n        break;\n\n      case HAL_CAN_MSPINIT_CB_ID :\n        hcan->MspInitCallback = HAL_CAN_MspInit;\n        break;\n\n      case HAL_CAN_MSPDEINIT_CB_ID :\n        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;\n        break;\n\n      default :\n        /* Update the error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (hcan->State == HAL_CAN_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_CAN_MSPINIT_CB_ID :\n        hcan->MspInitCallback = HAL_CAN_MspInit;\n        break;\n\n      case HAL_CAN_MSPDEINIT_CB_ID :\n        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;\n        break;\n\n      default :\n        /* Update the error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  return status;\n}\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Exported_Functions_Group2 Configuration functions\n *  @brief    Configuration functions.\n *\n@verbatim\n  ==============================================================================\n              ##### Configuration functions #####\n  ==============================================================================\n    [..]  This section provides functions allowing to:\n      (+) HAL_CAN_ConfigFilter            : Configure the CAN reception filters\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Configures the CAN reception filter according to the specified\n  *         parameters in the CAN_FilterInitStruct.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that\n  *         contains the filter configuration information.\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)\n{\n  uint32_t filternbrbitpos;\n  CAN_TypeDef *can_ip = hcan->Instance;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check the parameters */\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));\n    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));\n    assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));\n    assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));\n    assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));\n    assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));\n\n#if defined(CAN3)\n    /* Check the CAN instance */\n    if (hcan->Instance == CAN3)\n    {\n      /* CAN3 is single instance with 14 dedicated filters banks */\n\n      /* Check the parameters */\n      assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));\n    }\n    else\n    {\n      /* CAN1 and CAN2 are dual instances with 28 common filters banks */\n      /* Select master instance to access the filter banks */\n      can_ip = CAN1;\n\n      /* Check the parameters */\n      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));\n      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));\n    }\n#elif defined(CAN2)\n    /* CAN1 and CAN2 are dual instances with 28 common filters banks */\n    /* Select master instance to access the filter banks */\n    can_ip = CAN1;\n\n    /* Check the parameters */\n    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));\n    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));\n#else\n    /* CAN1 is single instance with 14 dedicated filters banks */\n\n    /* Check the parameters */\n    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));\n#endif\n\n    /* Initialisation mode for the filter */\n    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);\n\n#if defined(CAN3)\n    /* Check the CAN instance */\n    if (can_ip == CAN1)\n    {\n      /* Select the start filter number of CAN2 slave instance */\n      CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);\n      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);\n    }\n\n#elif defined(CAN2)\n    /* Select the start filter number of CAN2 slave instance */\n    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);\n    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);\n\n#endif\n    /* Convert filter number into bit position */\n    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);\n\n    /* Filter Deactivation */\n    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);\n\n    /* Filter Scale */\n    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)\n    {\n      /* 16-bit scale for the filter */\n      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);\n\n      /* First 16-bit identifier and First 16-bit mask */\n      /* Or First 16-bit identifier and Second 16-bit identifier */\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);\n\n      /* Second 16-bit identifier and Second 16-bit mask */\n      /* Or Third 16-bit identifier and Fourth 16-bit identifier */\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);\n    }\n\n    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)\n    {\n      /* 32-bit scale for the filter */\n      SET_BIT(can_ip->FS1R, filternbrbitpos);\n\n      /* 32-bit identifier or First 32-bit identifier */\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);\n\n      /* 32-bit mask or Second 32-bit identifier */\n      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =\n        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |\n        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);\n    }\n\n    /* Filter Mode */\n    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)\n    {\n      /* Id/Mask mode for the filter*/\n      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);\n    }\n    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */\n    {\n      /* Identifier list mode for the filter*/\n      SET_BIT(can_ip->FM1R, filternbrbitpos);\n    }\n\n    /* Filter FIFO assignment */\n    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)\n    {\n      /* FIFO 0 assignation for the filter */\n      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);\n    }\n    else\n    {\n      /* FIFO 1 assignation for the filter */\n      SET_BIT(can_ip->FFA1R, filternbrbitpos);\n    }\n\n    /* Filter activation */\n    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)\n    {\n      SET_BIT(can_ip->FA1R, filternbrbitpos);\n    }\n\n    /* Leave the initialisation mode for the filter */\n    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Exported_Functions_Group3 Control functions\n *  @brief    Control functions\n *\n@verbatim\n  ==============================================================================\n                      ##### Control functions #####\n  ==============================================================================\n    [..]  This section provides functions allowing to:\n      (+) HAL_CAN_Start                    : Start the CAN module\n      (+) HAL_CAN_Stop                     : Stop the CAN module\n      (+) HAL_CAN_RequestSleep             : Request sleep mode entry.\n      (+) HAL_CAN_WakeUp                   : Wake up from sleep mode.\n      (+) HAL_CAN_IsSleepActive            : Check is sleep mode is active.\n      (+) HAL_CAN_AddTxMessage             : Add a message to the Tx mailboxes\n                                             and activate the corresponding\n                                             transmission request\n      (+) HAL_CAN_AbortTxRequest           : Abort transmission request\n      (+) HAL_CAN_GetTxMailboxesFreeLevel  : Return Tx mailboxes free level\n      (+) HAL_CAN_IsTxMessagePending       : Check if a transmission request is\n                                             pending on the selected Tx mailbox\n      (+) HAL_CAN_GetRxMessage             : Get a CAN frame from the Rx FIFO\n      (+) HAL_CAN_GetRxFifoFillLevel       : Return Rx FIFO fill level\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Start the CAN module.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)\n{\n  uint32_t tickstart;\n\n  if (hcan->State == HAL_CAN_STATE_READY)\n  {\n    /* Change CAN peripheral state */\n    hcan->State = HAL_CAN_STATE_LISTENING;\n\n    /* Request leave initialisation */\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    /* Wait the acknowledge */\n    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)\n    {\n      /* Check for the Timeout */\n      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\n\n        /* Change CAN state */\n        hcan->State = HAL_CAN_STATE_ERROR;\n\n        return HAL_ERROR;\n      }\n    }\n\n    /* Reset the CAN ErrorCode */\n    hcan->ErrorCode = HAL_CAN_ERROR_NONE;\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Stop the CAN module and enable access to configuration registers.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)\n{\n  uint32_t tickstart;\n\n  if (hcan->State == HAL_CAN_STATE_LISTENING)\n  {\n    /* Request initialisation */\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    /* Wait the acknowledge */\n    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)\n    {\n      /* Check for the Timeout */\n      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\n\n        /* Change CAN state */\n        hcan->State = HAL_CAN_STATE_ERROR;\n\n        return HAL_ERROR;\n      }\n    }\n\n    /* Exit from sleep mode */\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\n\n    /* Change CAN peripheral state */\n    hcan->State = HAL_CAN_STATE_READY;\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Request the sleep mode (low power) entry.\n  *         When returning from this function, Sleep mode will be entered\n  *         as soon as the current CAN activity (transmission or reception\n  *         of a CAN frame) has been completed.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Request Sleep mode */\n    SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    /* Return function status */\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Wake up from sleep mode.\n  *         When returning with HAL_OK status from this function, Sleep mode\n  *         is exited.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status.\n  */\nHAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)\n{\n  __IO uint32_t count = 0;\n  uint32_t timeout = 1000000U;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Wake up request */\n    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);\n\n    /* Wait sleep mode is exited */\n    do\n    {\n      /* Increment counter */\n      count++;\n\n      /* Check if timeout is reached */\n      if (count > timeout)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;\n\n        return HAL_ERROR;\n      }\n    }\n    while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Check is sleep mode is active.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval Status\n  *          - 0 : Sleep mode is not active.\n  *          - 1 : Sleep mode is active.\n  */\nuint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)\n{\n  uint32_t status = 0U;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check Sleep mode */\n    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)\n    {\n      status = 1U;\n    }\n  }\n\n  /* Return function status */\n  return status;\n}\n\n/**\n  * @brief  Add a message to the first free Tx mailbox and activate the\n  *         corresponding transmission request.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  pHeader pointer to a CAN_TxHeaderTypeDef structure.\n  * @param  aData array containing the payload of the Tx frame.\n  * @param  pTxMailbox pointer to a variable where the function will return\n  *         the TxMailbox used to store the Tx message.\n  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)\n{\n  uint32_t transmitmailbox;\n  HAL_CAN_StateTypeDef state = hcan->State;\n  uint32_t tsr = READ_REG(hcan->Instance->TSR);\n\n  /* Check the parameters */\n  assert_param(IS_CAN_IDTYPE(pHeader->IDE));\n  assert_param(IS_CAN_RTR(pHeader->RTR));\n  assert_param(IS_CAN_DLC(pHeader->DLC));\n  if (pHeader->IDE == CAN_ID_STD)\n  {\n    assert_param(IS_CAN_STDID(pHeader->StdId));\n  }\n  else\n  {\n    assert_param(IS_CAN_EXTID(pHeader->ExtId));\n  }\n  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check that all the Tx mailboxes are not full */\n    if (((tsr & CAN_TSR_TME0) != 0U) ||\n        ((tsr & CAN_TSR_TME1) != 0U) ||\n        ((tsr & CAN_TSR_TME2) != 0U))\n    {\n      /* Select an empty transmit mailbox */\n      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;\n\n      /* Check transmit mailbox value */\n      if (transmitmailbox > 2U)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;\n\n        return HAL_ERROR;\n      }\n\n      /* Store the Tx mailbox */\n      *pTxMailbox = (uint32_t)1 << transmitmailbox;\n\n      /* Set up the Id */\n      if (pHeader->IDE == CAN_ID_STD)\n      {\n        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |\n                                                           pHeader->RTR);\n      }\n      else\n      {\n        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |\n                                                           pHeader->IDE |\n                                                           pHeader->RTR);\n      }\n\n      /* Set up the DLC */\n      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);\n\n      /* Set up the Transmit Global Time mode */\n      if (pHeader->TransmitGlobalTime == ENABLE)\n      {\n        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);\n      }\n\n      /* Set up the data field */\n      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,\n                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |\n                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |\n                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |\n                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));\n      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,\n                ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |\n                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |\n                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |\n                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));\n\n      /* Request transmission */\n      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);\n\n      /* Return function status */\n      return HAL_OK;\n    }\n    else\n    {\n      /* Update error code */\n      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Abort transmission requests\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  TxMailboxes List of the Tx Mailboxes to abort.\n  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check Tx Mailbox 0 */\n    if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)\n    {\n      /* Add cancellation request for Tx Mailbox 0 */\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);\n    }\n\n    /* Check Tx Mailbox 1 */\n    if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)\n    {\n      /* Add cancellation request for Tx Mailbox 1 */\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);\n    }\n\n    /* Check Tx Mailbox 2 */\n    if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)\n    {\n      /* Add cancellation request for Tx Mailbox 2 */\n      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);\n    }\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Return Tx Mailboxes free level: number of free Tx Mailboxes.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval Number of free Tx Mailboxes.\n  */\nuint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)\n{\n  uint32_t freelevel = 0U;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check Tx Mailbox 0 status */\n    if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)\n    {\n      freelevel++;\n    }\n\n    /* Check Tx Mailbox 1 status */\n    if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)\n    {\n      freelevel++;\n    }\n\n    /* Check Tx Mailbox 2 status */\n    if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)\n    {\n      freelevel++;\n    }\n  }\n\n  /* Return Tx Mailboxes free level */\n  return freelevel;\n}\n\n/**\n  * @brief  Check if a transmission request is pending on the selected Tx\n  *         Mailboxes.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  TxMailboxes List of Tx Mailboxes to check.\n  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.\n  * @retval Status\n  *          - 0 : No pending transmission request on any selected Tx Mailboxes.\n  *          - 1 : Pending transmission request on at least one of the selected\n  *                Tx Mailbox.\n  */\nuint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)\n{\n  uint32_t status = 0U;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check pending transmission request on the selected Tx Mailboxes */\n    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))\n    {\n      status = 1U;\n    }\n  }\n\n  /* Return status */\n  return status;\n}\n\n/**\n  * @brief  Return timestamp of Tx message sent, if time triggered communication\n            mode is enabled.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  TxMailbox Tx Mailbox where the timestamp of message sent will be\n  *         read.\n  *         This parameter can be one value of @arg CAN_Tx_Mailboxes.\n  * @retval Timestamp of message sent from Tx Mailbox.\n  */\nuint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)\n{\n  uint32_t timestamp = 0U;\n  uint32_t transmitmailbox;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_TX_MAILBOX(TxMailbox));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Select the Tx mailbox */\n    transmitmailbox = POSITION_VAL(TxMailbox);\n\n    /* Get timestamp */\n    timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;\n  }\n\n  /* Return the timestamp */\n  return timestamp;\n}\n\n/**\n  * @brief  Get an CAN frame from the Rx FIFO zone into the message RAM.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  RxFifo Fifo number of the received message to be read.\n  *         This parameter can be a value of @arg CAN_receive_FIFO_number.\n  * @param  pHeader pointer to a CAN_RxHeaderTypeDef structure where the header\n  *         of the Rx frame will be stored.\n  * @param  aData array where the payload of the Rx frame will be stored.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  assert_param(IS_CAN_RX_FIFO(RxFifo));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check the Rx FIFO */\n    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */\n    {\n      /* Check that the Rx FIFO 0 is not empty */\n      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\n\n        return HAL_ERROR;\n      }\n    }\n    else /* Rx element is assigned to Rx FIFO 1 */\n    {\n      /* Check that the Rx FIFO 1 is not empty */\n      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)\n      {\n        /* Update error code */\n        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;\n\n        return HAL_ERROR;\n      }\n    }\n\n    /* Get the header */\n    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;\n    if (pHeader->IDE == CAN_ID_STD)\n    {\n      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;\n    }\n    else\n    {\n      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;\n    }\n    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);\n    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;\n    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;\n    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;\n\n    /* Get the data */\n    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);\n    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);\n    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);\n    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);\n    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);\n    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);\n    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);\n    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);\n\n    /* Release the FIFO */\n    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */\n    {\n      /* Release RX FIFO 0 */\n      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);\n    }\n    else /* Rx element is assigned to Rx FIFO 1 */\n    {\n      /* Release RX FIFO 1 */\n      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);\n    }\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Return Rx FIFO fill level.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  RxFifo Rx FIFO.\n  *         This parameter can be a value of @arg CAN_receive_FIFO_number.\n  * @retval Number of messages available in Rx FIFO.\n  */\nuint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)\n{\n  uint32_t filllevel = 0U;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_RX_FIFO(RxFifo));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    if (RxFifo == CAN_RX_FIFO0)\n    {\n      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;\n    }\n    else /* RxFifo == CAN_RX_FIFO1 */\n    {\n      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;\n    }\n  }\n\n  /* Return Rx FIFO fill level */\n  return filllevel;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Exported_Functions_Group4 Interrupts management\n *  @brief    Interrupts management\n *\n@verbatim\n  ==============================================================================\n                       ##### Interrupts management #####\n  ==============================================================================\n    [..]  This section provides functions allowing to:\n      (+) HAL_CAN_ActivateNotification      : Enable interrupts\n      (+) HAL_CAN_DeactivateNotification    : Disable interrupts\n      (+) HAL_CAN_IRQHandler                : Handles CAN interrupt request\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Enable interrupts.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  ActiveITs indicates which interrupts will be enabled.\n  *         This parameter can be any combination of @arg CAN_Interrupts.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_IT(ActiveITs));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Enable the selected interrupts */\n    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Disable interrupts.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @param  InactiveITs indicates which interrupts will be disabled.\n  *         This parameter can be any combination of @arg CAN_Interrupts.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  /* Check function parameters */\n  assert_param(IS_CAN_IT(InactiveITs));\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Disable the selected interrupts */\n    __HAL_CAN_DISABLE_IT(hcan, InactiveITs);\n\n    /* Return function status */\n    return HAL_OK;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Handles CAN interrupt request\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\nvoid HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)\n{\n  uint32_t errorcode = HAL_CAN_ERROR_NONE;\n  uint32_t interrupts = READ_REG(hcan->Instance->IER);\n  uint32_t msrflags = READ_REG(hcan->Instance->MSR);\n  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);\n  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);\n  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);\n  uint32_t esrflags = READ_REG(hcan->Instance->ESR);\n\n  /* Transmit Mailbox empty interrupt management *****************************/\n  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)\n  {\n    /* Transmit Mailbox 0 management *****************************************/\n    if ((tsrflags & CAN_TSR_RQCP0) != 0U)\n    {\n      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);\n\n      if ((tsrflags & CAN_TSR_TXOK0) != 0U)\n      {\n        /* Transmission Mailbox 0 complete callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n        /* Call registered callback*/\n        hcan->TxMailbox0CompleteCallback(hcan);\n#else\n        /* Call weak (surcharged) callback */\n        HAL_CAN_TxMailbox0CompleteCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        if ((tsrflags & CAN_TSR_ALST0) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_ALST0;\n        }\n        else if ((tsrflags & CAN_TSR_TERR0) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_TERR0;\n        }\n        else\n        {\n          /* Transmission Mailbox 0 abort callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n          /* Call registered callback*/\n          hcan->TxMailbox0AbortCallback(hcan);\n#else\n          /* Call weak (surcharged) callback */\n          HAL_CAN_TxMailbox0AbortCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n        }\n      }\n    }\n\n    /* Transmit Mailbox 1 management *****************************************/\n    if ((tsrflags & CAN_TSR_RQCP1) != 0U)\n    {\n      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);\n\n      if ((tsrflags & CAN_TSR_TXOK1) != 0U)\n      {\n        /* Transmission Mailbox 1 complete callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n        /* Call registered callback*/\n        hcan->TxMailbox1CompleteCallback(hcan);\n#else\n        /* Call weak (surcharged) callback */\n        HAL_CAN_TxMailbox1CompleteCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        if ((tsrflags & CAN_TSR_ALST1) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_ALST1;\n        }\n        else if ((tsrflags & CAN_TSR_TERR1) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_TERR1;\n        }\n        else\n        {\n          /* Transmission Mailbox 1 abort callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n          /* Call registered callback*/\n          hcan->TxMailbox1AbortCallback(hcan);\n#else\n          /* Call weak (surcharged) callback */\n          HAL_CAN_TxMailbox1AbortCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n        }\n      }\n    }\n\n    /* Transmit Mailbox 2 management *****************************************/\n    if ((tsrflags & CAN_TSR_RQCP2) != 0U)\n    {\n      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);\n\n      if ((tsrflags & CAN_TSR_TXOK2) != 0U)\n      {\n        /* Transmission Mailbox 2 complete callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n        /* Call registered callback*/\n        hcan->TxMailbox2CompleteCallback(hcan);\n#else\n        /* Call weak (surcharged) callback */\n        HAL_CAN_TxMailbox2CompleteCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        if ((tsrflags & CAN_TSR_ALST2) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_ALST2;\n        }\n        else if ((tsrflags & CAN_TSR_TERR2) != 0U)\n        {\n          /* Update error code */\n          errorcode |= HAL_CAN_ERROR_TX_TERR2;\n        }\n        else\n        {\n          /* Transmission Mailbox 2 abort callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n          /* Call registered callback*/\n          hcan->TxMailbox2AbortCallback(hcan);\n#else\n          /* Call weak (surcharged) callback */\n          HAL_CAN_TxMailbox2AbortCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n        }\n      }\n    }\n  }\n\n  /* Receive FIFO 0 overrun interrupt management *****************************/\n  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)\n  {\n    if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)\n    {\n      /* Set CAN error code to Rx Fifo 0 overrun error */\n      errorcode |= HAL_CAN_ERROR_RX_FOV0;\n\n      /* Clear FIFO0 Overrun Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);\n    }\n  }\n\n  /* Receive FIFO 0 full interrupt management ********************************/\n  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)\n  {\n    if ((rf0rflags & CAN_RF0R_FULL0) != 0U)\n    {\n      /* Clear FIFO 0 full Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);\n\n      /* Receive FIFO 0 full Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->RxFifo0FullCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_RxFifo0FullCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Receive FIFO 0 message pending interrupt management *********************/\n  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)\n  {\n    /* Check if message is still pending */\n    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)\n    {\n      /* Receive FIFO 0 message pending Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->RxFifo0MsgPendingCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_RxFifo0MsgPendingCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Receive FIFO 1 overrun interrupt management *****************************/\n  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)\n  {\n    if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)\n    {\n      /* Set CAN error code to Rx Fifo 1 overrun error */\n      errorcode |= HAL_CAN_ERROR_RX_FOV1;\n\n      /* Clear FIFO1 Overrun Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);\n    }\n  }\n\n  /* Receive FIFO 1 full interrupt management ********************************/\n  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)\n  {\n    if ((rf1rflags & CAN_RF1R_FULL1) != 0U)\n    {\n      /* Clear FIFO 1 full Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);\n\n      /* Receive FIFO 1 full Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->RxFifo1FullCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_RxFifo1FullCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Receive FIFO 1 message pending interrupt management *********************/\n  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)\n  {\n    /* Check if message is still pending */\n    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)\n    {\n      /* Receive FIFO 1 message pending Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->RxFifo1MsgPendingCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_RxFifo1MsgPendingCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Sleep interrupt management *********************************************/\n  if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)\n  {\n    if ((msrflags & CAN_MSR_SLAKI) != 0U)\n    {\n      /* Clear Sleep interrupt Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);\n\n      /* Sleep Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->SleepCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_SleepCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* WakeUp interrupt management *********************************************/\n  if ((interrupts & CAN_IT_WAKEUP) != 0U)\n  {\n    if ((msrflags & CAN_MSR_WKUI) != 0U)\n    {\n      /* Clear WakeUp Flag */\n      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);\n\n      /* WakeUp Callback */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n      /* Call registered callback*/\n      hcan->WakeUpFromRxMsgCallback(hcan);\n#else\n      /* Call weak (surcharged) callback */\n      HAL_CAN_WakeUpFromRxMsgCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Error interrupts management *********************************************/\n  if ((interrupts & CAN_IT_ERROR) != 0U)\n  {\n    if ((msrflags & CAN_MSR_ERRI) != 0U)\n    {\n      /* Check Error Warning Flag */\n      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&\n          ((esrflags & CAN_ESR_EWGF) != 0U))\n      {\n        /* Set CAN error code to Error Warning */\n        errorcode |= HAL_CAN_ERROR_EWG;\n\n        /* No need for clear of Error Warning Flag as read-only */\n      }\n\n      /* Check Error Passive Flag */\n      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&\n          ((esrflags & CAN_ESR_EPVF) != 0U))\n      {\n        /* Set CAN error code to Error Passive */\n        errorcode |= HAL_CAN_ERROR_EPV;\n\n        /* No need for clear of Error Passive Flag as read-only */\n      }\n\n      /* Check Bus-off Flag */\n      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&\n          ((esrflags & CAN_ESR_BOFF) != 0U))\n      {\n        /* Set CAN error code to Bus-Off */\n        errorcode |= HAL_CAN_ERROR_BOF;\n\n        /* No need for clear of Error Bus-Off as read-only */\n      }\n\n      /* Check Last Error Code Flag */\n      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&\n          ((esrflags & CAN_ESR_LEC) != 0U))\n      {\n        switch (esrflags & CAN_ESR_LEC)\n        {\n          case (CAN_ESR_LEC_0):\n            /* Set CAN error code to Stuff error */\n            errorcode |= HAL_CAN_ERROR_STF;\n            break;\n          case (CAN_ESR_LEC_1):\n            /* Set CAN error code to Form error */\n            errorcode |= HAL_CAN_ERROR_FOR;\n            break;\n          case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):\n            /* Set CAN error code to Acknowledgement error */\n            errorcode |= HAL_CAN_ERROR_ACK;\n            break;\n          case (CAN_ESR_LEC_2):\n            /* Set CAN error code to Bit recessive error */\n            errorcode |= HAL_CAN_ERROR_BR;\n            break;\n          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):\n            /* Set CAN error code to Bit Dominant error */\n            errorcode |= HAL_CAN_ERROR_BD;\n            break;\n          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):\n            /* Set CAN error code to CRC error */\n            errorcode |= HAL_CAN_ERROR_CRC;\n            break;\n          default:\n            break;\n        }\n\n        /* Clear Last error code Flag */\n        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);\n      }\n    }\n\n    /* Clear ERRI Flag */\n    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);\n  }\n\n  /* Call the Error call Back in case of Errors */\n  if (errorcode != HAL_CAN_ERROR_NONE)\n  {\n    /* Update error code in handle */\n    hcan->ErrorCode |= errorcode;\n\n    /* Call Error callback function */\n#if USE_HAL_CAN_REGISTER_CALLBACKS == 1\n    /* Call registered callback*/\n    hcan->ErrorCallback(hcan);\n#else\n    /* Call weak (surcharged) callback */\n    HAL_CAN_ErrorCallback(hcan);\n#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Exported_Functions_Group5 Callback functions\n *  @brief   CAN Callback functions\n *\n@verbatim\n  ==============================================================================\n                          ##### Callback functions #####\n  ==============================================================================\n    [..]\n    This subsection provides the following callback functions:\n      (+) HAL_CAN_TxMailbox0CompleteCallback\n      (+) HAL_CAN_TxMailbox1CompleteCallback\n      (+) HAL_CAN_TxMailbox2CompleteCallback\n      (+) HAL_CAN_TxMailbox0AbortCallback\n      (+) HAL_CAN_TxMailbox1AbortCallback\n      (+) HAL_CAN_TxMailbox2AbortCallback\n      (+) HAL_CAN_RxFifo0MsgPendingCallback\n      (+) HAL_CAN_RxFifo0FullCallback\n      (+) HAL_CAN_RxFifo1MsgPendingCallback\n      (+) HAL_CAN_RxFifo1FullCallback\n      (+) HAL_CAN_SleepCallback\n      (+) HAL_CAN_WakeUpFromRxMsgCallback\n      (+) HAL_CAN_ErrorCallback\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Transmission Mailbox 0 complete callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Transmission Mailbox 1 complete callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Transmission Mailbox 2 complete callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Transmission Mailbox 0 Cancellation callback.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Transmission Mailbox 1 Cancellation callback.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Transmission Mailbox 2 Cancellation callback.\n  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Rx FIFO 0 message pending callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Rx FIFO 0 full callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_RxFifo0FullCallback could be implemented in the user\n            file\n   */\n}\n\n/**\n  * @brief  Rx FIFO 1 message pending callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Rx FIFO 1 full callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_RxFifo1FullCallback could be implemented in the user\n            file\n   */\n}\n\n/**\n  * @brief  Sleep callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_SleepCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  WakeUp from Rx message callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the\n            user file\n   */\n}\n\n/**\n  * @brief  Error CAN callback.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval None\n  */\n__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hcan);\n\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_CAN_ErrorCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions\n *  @brief   CAN Peripheral State functions\n *\n@verbatim\n  ==============================================================================\n            ##### Peripheral State and Error functions #####\n  ==============================================================================\n    [..]\n    This subsection provides functions allowing to :\n      (+) HAL_CAN_GetState()  : Return the CAN state.\n      (+) HAL_CAN_GetError()  : Return the CAN error codes if any.\n      (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the CAN state.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL state\n  */\nHAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)\n{\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Check sleep mode acknowledge flag */\n    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)\n    {\n      /* Sleep mode is active */\n      state = HAL_CAN_STATE_SLEEP_ACTIVE;\n    }\n    /* Check sleep mode request flag */\n    else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)\n    {\n      /* Sleep mode request is pending */\n      state = HAL_CAN_STATE_SLEEP_PENDING;\n    }\n    else\n    {\n      /* Neither sleep mode request nor sleep mode acknowledge */\n    }\n  }\n\n  /* Return CAN state */\n  return state;\n}\n\n/**\n  * @brief  Return the CAN error code.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval CAN Error Code\n  */\nuint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)\n{\n  /* Return CAN error code */\n  return hcan->ErrorCode;\n}\n\n/**\n  * @brief  Reset the CAN error code.\n  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains\n  *         the configuration information for the specified CAN.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  HAL_CAN_StateTypeDef state = hcan->State;\n\n  if ((state == HAL_CAN_STATE_READY) ||\n      (state == HAL_CAN_STATE_LISTENING))\n  {\n    /* Reset CAN error code */\n    hcan->ErrorCode = 0U;\n  }\n  else\n  {\n    /* Update error code */\n    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;\n\n    status = HAL_ERROR;\n  }\n\n  /* Return the status */\n  return status;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_CAN_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n#endif /* CAN1 */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_cortex.c\n  * @author  MCD Application Team\n  * @brief   CORTEX HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of the CORTEX:\n  *           + Initialization and de-initialization functions\n  *           + Peripheral Control functions \n  *\n  @verbatim  \n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n\n    [..]  \n    *** How to configure Interrupts using CORTEX HAL driver ***\n    ===========================================================\n    [..]     \n    This section provides functions allowing to configure the NVIC interrupts (IRQ).\n    The Cortex-M4 exceptions are managed by CMSIS functions.\n   \n    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()\n        function according to the following table.\n    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). \n    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().\n    (#) please refer to programming manual for details in how to configure priority. \n      \n     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. \n         The pending IRQ priority will be managed only by the sub priority.\n   \n     -@- IRQ priority order (sorted by highest to lowest priority):\n        (+@) Lowest preemption priority\n        (+@) Lowest sub priority\n        (+@) Lowest hardware priority (IRQ number)\n \n    [..]  \n    *** How to configure Systick using CORTEX HAL driver ***\n    ========================================================\n    [..]\n    Setup SysTick Timer for time base.\n           \n   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which\n       is a CMSIS function that:\n        (++) Configures the SysTick Reload register with value passed as function parameter.\n        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.\n        (++) Resets the SysTick Counter register.\n        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).\n        (++) Enables the SysTick Interrupt.\n        (++) Starts the SysTick Counter.\n    \n   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro\n       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the\n       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined\n       inside the stm32f4xx_hal_cortex.h file.\n\n   (+) You can change the SysTick IRQ priority by calling the\n       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function \n       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.\n\n   (+) To adjust the SysTick time base, use the following formula:\n                            \n       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)\n       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function\n       (++) Reload Value should not exceed 0xFFFFFF\n   \n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup CORTEX CORTEX\n  * @brief CORTEX HAL module driver\n  * @{\n  */\n\n#ifdef HAL_CORTEX_MODULE_ENABLED\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions\n  * @{\n  */\n\n\n/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions \n *\n@verbatim    \n  ==============================================================================\n              ##### Initialization and de-initialization functions #####\n  ==============================================================================\n    [..]\n      This section provides the CORTEX HAL driver functions allowing to configure Interrupts\n      Systick functionalities \n\n@endverbatim\n  * @{\n  */\n\n\n/**\n  * @brief  Sets the priority grouping field (preemption priority and subpriority)\n  *         using the required unlock sequence.\n  * @param  PriorityGroup The priority grouping bits length. \n  *         This parameter can be one of the following values:\n  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\n  *                                    4 bits for subpriority\n  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\n  *                                    3 bits for subpriority\n  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\n  *                                    2 bits for subpriority\n  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\n  *                                    1 bits for subpriority\n  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\n  *                                    0 bits for subpriority\n  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. \n  *         The pending IRQ priority will be managed only by the subpriority. \n  * @retval None\n  */\nvoid HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\n  \n  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */\n  NVIC_SetPriorityGrouping(PriorityGroup);\n}\n\n/**\n  * @brief  Sets the priority of an interrupt.\n  * @param  IRQn External interrupt number.\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @param  PreemptPriority The preemption priority for the IRQn channel.\n  *         This parameter can be a value between 0 and 15\n  *         A lower priority value indicates a higher priority \n  * @param  SubPriority the subpriority level for the IRQ channel.\n  *         This parameter can be a value between 0 and 15\n  *         A lower priority value indicates a higher priority.          \n  * @retval None\n  */\nvoid HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)\n{ \n  uint32_t prioritygroup = 0x00U;\n  \n  /* Check the parameters */\n  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));\n  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));\n  \n  prioritygroup = NVIC_GetPriorityGrouping();\n  \n  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));\n}\n\n/**\n  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.\n  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()\n  *         function should be called before. \n  * @param  IRQn External interrupt number.\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval None\n  */\nvoid HAL_NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Enable interrupt */\n  NVIC_EnableIRQ(IRQn);\n}\n\n/**\n  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.\n  * @param  IRQn External interrupt number.\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval None\n  */\nvoid HAL_NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Disable interrupt */\n  NVIC_DisableIRQ(IRQn);\n}\n\n/**\n  * @brief  Initiates a system reset request to reset the MCU.\n  * @retval None\n  */\nvoid HAL_NVIC_SystemReset(void)\n{\n  /* System Reset */\n  NVIC_SystemReset();\n}\n\n/**\n  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n  *         Counter is in free running mode to generate periodic interrupts.\n  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.\n  * @retval status:  - 0  Function succeeded.\n  *                  - 1  Function failed.\n  */\nuint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)\n{\n   return SysTick_Config(TicksNumb);\n}\n/**\n  * @}\n  */\n\n/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions\n *  @brief   Cortex control functions \n *\n@verbatim   \n  ==============================================================================\n                      ##### Peripheral Control functions #####\n  ==============================================================================  \n    [..]\n      This subsection provides a set of functions allowing to control the CORTEX\n      (NVIC, SYSTICK, MPU) functionalities. \n \n      \n@endverbatim\n  * @{\n  */\n\n#if (__MPU_PRESENT == 1U)\n/**\n  * @brief  Disables the MPU\n  * @retval None\n  */\nvoid HAL_MPU_Disable(void)\n{\n  /* Make sure outstanding transfers are done */\n  __DMB();\n\n  /* Disable fault exceptions */\n  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;\n  \n  /* Disable the MPU and clear the control register*/\n  MPU->CTRL = 0U;\n}\n\n/**\n  * @brief  Enable the MPU.\n  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, \n  *          NMI, FAULTMASK and privileged access to the default memory \n  *          This parameter can be one of the following values:\n  *            @arg MPU_HFNMI_PRIVDEF_NONE\n  *            @arg MPU_HARDFAULT_NMI\n  *            @arg MPU_PRIVILEGED_DEFAULT\n  *            @arg MPU_HFNMI_PRIVDEF\n  * @retval None\n  */\nvoid HAL_MPU_Enable(uint32_t MPU_Control)\n{\n  /* Enable the MPU */\n  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;\n  \n  /* Enable fault exceptions */\n  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;\n  \n  /* Ensure MPU setting take effects */\n  __DSB();\n  __ISB();\n}\n\n/**\n  * @brief  Initializes and configures the Region and the memory to be protected.\n  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains\n  *                the initialization and configuration information.\n  * @retval None\n  */\nvoid HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)\n{\n  /* Check the parameters */\n  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));\n  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));\n\n  /* Set the Region number */\n  MPU->RNR = MPU_Init->Number;\n\n  if ((MPU_Init->Enable) != RESET)\n  {\n    /* Check the parameters */\n    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));\n    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));\n    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));\n    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));\n    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));\n    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));\n    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));\n    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));\n    \n    MPU->RBAR = MPU_Init->BaseAddress;\n    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |\n                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |\n                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |\n                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |\n                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |\n                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |\n                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |\n                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |\n                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);\n  }\n  else\n  {\n    MPU->RBAR = 0x00U;\n    MPU->RASR = 0x00U;\n  }\n}\n#endif /* __MPU_PRESENT */\n\n/**\n  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.\n  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)\n  */\nuint32_t HAL_NVIC_GetPriorityGrouping(void)\n{\n  /* Get the PRIGROUP[10:8] field value */\n  return NVIC_GetPriorityGrouping();\n}\n\n/**\n  * @brief  Gets the priority of an interrupt.\n  * @param  IRQn External interrupt number.\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @param   PriorityGroup the priority grouping bits length.\n  *         This parameter can be one of the following values:\n  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority\n  *                                      4 bits for subpriority\n  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority\n  *                                      3 bits for subpriority\n  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority\n  *                                      2 bits for subpriority\n  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority\n  *                                      1 bits for subpriority\n  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority\n  *                                      0 bits for subpriority\n  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).\n  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).\n  * @retval None\n  */\nvoid HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));\n /* Get priority for Cortex-M system or device specific interrupts */\n  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);\n}\n\n/**\n  * @brief  Sets Pending bit of an external interrupt.\n  * @param  IRQn External interrupt number\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval None\n  */\nvoid HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Set interrupt pending */\n  NVIC_SetPendingIRQ(IRQn);\n}\n\n/**\n  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC \n  *         and returns the pending bit for the specified interrupt).\n  * @param  IRQn External interrupt number.\n  *          This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval status: - 0  Interrupt status is not pending.\n  *                 - 1  Interrupt status is pending.\n  */\nuint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Return 1 if pending else 0 */\n  return NVIC_GetPendingIRQ(IRQn);\n}\n\n/**\n  * @brief  Clears the pending bit of an external interrupt.\n  * @param  IRQn External interrupt number.\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval None\n  */\nvoid HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Clear pending interrupt */\n  NVIC_ClearPendingIRQ(IRQn);\n}\n\n/**\n  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).\n  * @param IRQn External interrupt number\n  *         This parameter can be an enumerator of IRQn_Type enumeration\n  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))\n  * @retval status: - 0  Interrupt status is not pending.\n  *                 - 1  Interrupt status is pending.\n  */\nuint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)\n{\n  /* Check the parameters */\n  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));\n  \n  /* Return 1 if active else 0 */\n  return NVIC_GetActive(IRQn);\n}\n\n/**\n  * @brief  Configures the SysTick clock source.\n  * @param  CLKSource specifies the SysTick clock source.\n  *          This parameter can be one of the following values:\n  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.\n  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.\n  * @retval None\n  */\nvoid HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)\n{\n  /* Check the parameters */\n  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));\n  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)\n  {\n    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;\n  }\n  else\n  {\n    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;\n  }\n}\n\n/**\n  * @brief  This function handles SYSTICK interrupt request.\n  * @retval None\n  */\nvoid HAL_SYSTICK_IRQHandler(void)\n{\n  HAL_SYSTICK_Callback();\n}\n\n/**\n  * @brief  SYSTICK callback.\n  * @retval None\n  */\n__weak void HAL_SYSTICK_Callback(void)\n{\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_SYSTICK_Callback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_CORTEX_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_dma.c\n  * @author  MCD Application Team\n  * @brief   DMA HAL module driver.\n  *    \n  *          This file provides firmware functions to manage the following \n  *          functionalities of the Direct Memory Access (DMA) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral State and errors functions\n  @verbatim     \n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n  [..]\n   (#) Enable and configure the peripheral to be connected to the DMA Stream\n       (except for internal SRAM/FLASH memories: no initialization is \n       necessary) please refer to Reference manual for connection between peripherals\n       and DMA requests.\n\n   (#) For a given Stream, program the required configuration through the following parameters:\n       Transfer Direction, Source and Destination data formats, \n       Circular, Normal or peripheral flow control mode, Stream Priority level, \n       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), \n       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.\n\n   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:\n         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().\n\n     *** Polling mode IO operation ***\n     =================================\n    [..]\n          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source \n              address and destination address and the Length of data to be transferred.\n          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  \n              case a fixed Timeout can be configured by User depending from his application.\n          (+) Use HAL_DMA_Abort() function to abort the current transfer.\n\n     *** Interrupt mode IO operation ***\n     ===================================\n    [..]\n          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()\n          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() \n          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  \n              Source address and destination address and the Length of data to be transferred. In this \n              case the DMA interrupt is configured \n          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine\n          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can \n              add his own function by customization of function pointer XferCpltCallback and \n              XferErrorCallback (i.e a member of DMA handle structure).\n    [..]\n     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error \n         detection.\n\n     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer\n\n     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.\n\n     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is\n           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set\n           Half-Word data size for the peripheral to access its data register and set Word data size\n           for the Memory to gain in access time. Each two half words will be packed and written in\n           a single access to a Word in the Memory).\n\n     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source\n           and Destination. In this case the Peripheral Data Size will be applied to both Source\n           and Destination.\n\n     *** DMA HAL driver macros list ***\n     =============================================\n     [..]\n       Below the list of most used macros in DMA HAL driver.\n       \n      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.\n      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.\n      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. \n\n     [..]\n      (@) You can refer to the DMA HAL driver header file for more useful macros\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup DMA DMA\n  * @brief DMA HAL module driver\n  * @{\n  */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n\n/* Private types -------------------------------------------------------------*/\ntypedef struct\n{\n  __IO uint32_t ISR;   /*!< DMA interrupt status register */\n  __IO uint32_t Reserved0;\n  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */\n} DMA_Base_Registers;\n\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/** @addtogroup DMA_Private_Constants\n * @{\n */\n #define HAL_TIMEOUT_DMA_ABORT    5U  /* 5 ms */\n/**\n  * @}\n  */\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/** @addtogroup DMA_Private_Functions\n  * @{\n  */\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);\n\n/**\n  * @}\n  */  \n\n/* Exported functions ---------------------------------------------------------*/\n/** @addtogroup DMA_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup DMA_Exported_Functions_Group1\n  *\n@verbatim\n ===============================================================================\n             ##### Initialization and de-initialization functions  #####\n ===============================================================================\n    [..]\n    This section provides functions allowing to initialize the DMA Stream source\n    and destination addresses, incrementation and data sizes, transfer direction, \n    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.\n    [..]\n    The HAL_DMA_Init() function follows the DMA configuration procedures as described in\n    reference manual.\n\n@endverbatim\n  * @{\n  */\n  \n/**\n  * @brief  Initialize the DMA according to the specified\n  *         parameters in the DMA_InitTypeDef and create the associated handle.\n  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA Stream.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)\n{\n  uint32_t tmp = 0U;\n  uint32_t tickstart = HAL_GetTick();\n  DMA_Base_Registers *regs;\n\n  /* Check the DMA peripheral state */\n  if(hdma == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\n  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));\n  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));\n  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));\n  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));\n  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));\n  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));\n  assert_param(IS_DMA_MODE(hdma->Init.Mode));\n  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));\n  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));\n  /* Check the memory burst, peripheral burst and FIFO threshold parameters only\n     when FIFO mode is enabled */\n  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)\n  {\n    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));\n    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));\n    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));\n  }\n  \n  /* Allocate lock resource */\n  __HAL_UNLOCK(hdma);\n\n  /* Change DMA peripheral state */\n  hdma->State = HAL_DMA_STATE_BUSY;\n  \n  /* Disable the peripheral */\n  __HAL_DMA_DISABLE(hdma);\n  \n  /* Check if the DMA Stream is effectively disabled */\n  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\n  {\n    /* Check for the Timeout */\n    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\n    {\n      /* Update error code */\n      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\n      \n      /* Change the DMA state */\n      hdma->State = HAL_DMA_STATE_TIMEOUT;\n      \n      return HAL_TIMEOUT;\n    }\n  }\n  \n  /* Get the CR register value */\n  tmp = hdma->Instance->CR;\n\n  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */\n  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \\\n                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \\\n                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \\\n                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));\n\n  /* Prepare the DMA Stream configuration */\n  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |\n          hdma->Init.PeriphInc           | hdma->Init.MemInc           |\n          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |\n          hdma->Init.Mode                | hdma->Init.Priority;\n\n  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\n  {\n    /* Get memory burst and peripheral burst */\n    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;\n  }\n  \n  /* Write to DMA Stream CR register */\n  hdma->Instance->CR = tmp;  \n\n  /* Get the FCR register value */\n  tmp = hdma->Instance->FCR;\n\n  /* Clear Direct mode and FIFO threshold bits */\n  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);\n\n  /* Prepare the DMA Stream FIFO configuration */\n  tmp |= hdma->Init.FIFOMode;\n\n  /* The FIFO threshold is not used when the FIFO mode is disabled */\n  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)\n  {\n    /* Get the FIFO threshold */\n    tmp |= hdma->Init.FIFOThreshold;\n    \n    /* Check compatibility between FIFO threshold level and size of the memory burst */\n    /* for INCR4, INCR8, INCR16 bursts */\n    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)\n    {\n      if (DMA_CheckFifoParam(hdma) != HAL_OK)\n      {\n        /* Update error code */\n        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\n        \n        /* Change the DMA state */\n        hdma->State = HAL_DMA_STATE_READY;\n        \n        return HAL_ERROR; \n      }\n    }\n  }\n  \n  /* Write to DMA Stream FCR */\n  hdma->Instance->FCR = tmp;\n\n  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate\n     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */\n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\n  \n  /* Clear all interrupt flags */\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\n\n  /* Initialize the error code */\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\n                                                                                     \n  /* Initialize the DMA state */\n  hdma->State = HAL_DMA_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the DMA peripheral \n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA Stream.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)\n{\n  DMA_Base_Registers *regs;\n\n  /* Check the DMA peripheral state */\n  if(hdma == NULL)\n  {\n    return HAL_ERROR;\n  }\n  \n  /* Check the DMA peripheral state */\n  if(hdma->State == HAL_DMA_STATE_BUSY)\n  {\n    /* Return error status */\n    return HAL_BUSY;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));\n\n  /* Disable the selected DMA Streamx */\n  __HAL_DMA_DISABLE(hdma);\n\n  /* Reset DMA Streamx control register */\n  hdma->Instance->CR   = 0U;\n\n  /* Reset DMA Streamx number of data to transfer register */\n  hdma->Instance->NDTR = 0U;\n\n  /* Reset DMA Streamx peripheral address register */\n  hdma->Instance->PAR  = 0U;\n\n  /* Reset DMA Streamx memory 0 address register */\n  hdma->Instance->M0AR = 0U;\n  \n  /* Reset DMA Streamx memory 1 address register */\n  hdma->Instance->M1AR = 0U;\n  \n  /* Reset DMA Streamx FIFO control register */\n  hdma->Instance->FCR  = 0x00000021U;\n  \n  /* Get DMA steam Base Address */  \n  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);\n  \n  /* Clean all callbacks */\n  hdma->XferCpltCallback = NULL;\n  hdma->XferHalfCpltCallback = NULL;\n  hdma->XferM1CpltCallback = NULL;\n  hdma->XferM1HalfCpltCallback = NULL;\n  hdma->XferErrorCallback = NULL;\n  hdma->XferAbortCallback = NULL;\n\n  /* Clear all interrupt flags at correct offset within the register */\n  regs->IFCR = 0x3FU << hdma->StreamIndex;\n\n  /* Reset the error code */\n  hdma->ErrorCode = HAL_DMA_ERROR_NONE;\n\n  /* Reset the DMA state */\n  hdma->State = HAL_DMA_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(hdma);\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup DMA_Exported_Functions_Group2\n  *\n@verbatim   \n ===============================================================================\n                      #####  IO operation functions  #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Configure the source, destination address and data length and Start DMA transfer\n      (+) Configure the source, destination address and data length and \n          Start DMA transfer with interrupt\n      (+) Abort DMA transfer\n      (+) Poll for transfer complete\n      (+) Handle DMA interrupt request  \n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Starts the DMA Transfer.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.\n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\n\n  /* Process locked */\n  __HAL_LOCK(hdma);\n\n  if(HAL_DMA_STATE_READY == hdma->State)\n  {\n    /* Change DMA peripheral state */\n    hdma->State = HAL_DMA_STATE_BUSY;\n    \n    /* Initialize the error code */\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\n    \n    /* Configure the source, destination address and the data length */\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\n\n    /* Enable the Peripheral */\n    __HAL_DMA_ENABLE(hdma);\n  }\n  else\n  {\n    /* Process unlocked */\n    __HAL_UNLOCK(hdma);\n    \n    /* Return error status */\n    status = HAL_BUSY;\n  } \n  return status; \n}\n\n/**\n  * @brief  Start the DMA Transfer with interrupt enabled.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.  \n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* calculate DMA base and stream number */\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\n  \n  /* Check the parameters */\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\n \n  /* Process locked */\n  __HAL_LOCK(hdma);\n  \n  if(HAL_DMA_STATE_READY == hdma->State)\n  {\n    /* Change DMA peripheral state */\n    hdma->State = HAL_DMA_STATE_BUSY;\n    \n    /* Initialize the error code */\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\n    \n    /* Configure the source, destination address and the data length */\n    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);\n    \n    /* Clear all interrupt flags at correct offset within the register */\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\n    \n    /* Enable Common interrupts*/\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\n    \n    if(hdma->XferHalfCpltCallback != NULL)\n    {\n      hdma->Instance->CR  |= DMA_IT_HT;\n    }\n    \n    /* Enable the Peripheral */\n    __HAL_DMA_ENABLE(hdma);\n  }\n  else\n  {\n    /* Process unlocked */\n    __HAL_UNLOCK(hdma);\t  \n    \n    /* Return error status */\n    status = HAL_BUSY;\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Aborts the DMA Transfer.\n  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains\n  *                 the configuration information for the specified DMA Stream.\n  *                   \n  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is \n  *        effectively disabled is added. If a Stream is disabled \n  *        while a data transfer is ongoing, the current data will be transferred\n  *        and the Stream will be effectively disabled only after the transfer of\n  *        this single data is finished.  \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)\n{\n  /* calculate DMA base and stream number */\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\n  \n  uint32_t tickstart = HAL_GetTick();\n  \n  if(hdma->State != HAL_DMA_STATE_BUSY)\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(hdma);\n    \n    return HAL_ERROR;\n  }\n  else\n  {\n    /* Disable all the transfer interrupts */\n    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\n    hdma->Instance->FCR &= ~(DMA_IT_FE);\n    \n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\n    {\n      hdma->Instance->CR  &= ~(DMA_IT_HT);\n    }\n    \n    /* Disable the stream */\n    __HAL_DMA_DISABLE(hdma);\n    \n    /* Check if the DMA Stream is effectively disabled */\n    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)\n    {\n      /* Check for the Timeout */\n      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)\n      {\n        /* Update error code */\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\n        \n        /* Process Unlocked */\n        __HAL_UNLOCK(hdma);\n        \n        /* Change the DMA state */\n        hdma->State = HAL_DMA_STATE_TIMEOUT;\n        \n        return HAL_TIMEOUT;\n      }\n    }\n    \n    /* Clear all interrupt flags at correct offset within the register */\n    regs->IFCR = 0x3FU << hdma->StreamIndex;\n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(hdma);\n    \n    /* Change the DMA state*/\n    hdma->State = HAL_DMA_STATE_READY;\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Aborts the DMA Transfer in Interrupt mode.\n  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains\n  *                 the configuration information for the specified DMA Stream.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)\n{\n  if(hdma->State != HAL_DMA_STATE_BUSY)\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\n    return HAL_ERROR;\n  }\n  else\n  {\n    /* Set Abort State  */\n    hdma->State = HAL_DMA_STATE_ABORT;\n    \n    /* Disable the stream */\n    __HAL_DMA_DISABLE(hdma);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Polling for transfer complete.\n  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains\n  *                        the configuration information for the specified DMA Stream.\n  * @param  CompleteLevel Specifies the DMA level complete.\n  * @note   The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.\n  *         This model could be used for debug purpose.\n  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). \n  * @param  Timeout       Timeout duration.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)\n{\n  HAL_StatusTypeDef status = HAL_OK; \n  uint32_t mask_cpltlevel;\n  uint32_t tickstart = HAL_GetTick(); \n  uint32_t tmpisr;\n  \n  /* calculate DMA base and stream number */\n  DMA_Base_Registers *regs;\n\n  if(HAL_DMA_STATE_BUSY != hdma->State)\n  {\n    /* No transfer ongoing */\n    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;\n    __HAL_UNLOCK(hdma);\n    return HAL_ERROR;\n  }\n\n  /* Polling mode not supported in circular mode and double buffering mode */\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\n    return HAL_ERROR;\n  }\n  \n  /* Get the level transfer complete flag */\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\n  {\n    /* Transfer Complete flag */\n    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\n  }\n  else\n  {\n    /* Half Transfer Complete flag */\n    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\n  }\n  \n  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\n  tmpisr = regs->ISR;\n  \n  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))\n  {\n    /* Check for the Timeout (Not applicable in circular mode)*/\n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        /* Update error code */\n        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hdma);\n        \n        /* Change the DMA state */\n        hdma->State = HAL_DMA_STATE_READY;\n        \n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* Get the ISR register value */\n    tmpisr = regs->ISR;\n\n    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\n    {\n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\n      \n      /* Clear the transfer error flag */\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\n    }\n    \n    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\n    {\n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\n      \n      /* Clear the FIFO error flag */\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\n    }\n    \n    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\n    {\n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\n      \n      /* Clear the Direct Mode error flag */\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\n    }\n  }\n  \n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\n  {\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\n    {\n      HAL_DMA_Abort(hdma);\n    \n      /* Clear the half transfer and transfer complete flags */\n      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\n    \n      /* Process Unlocked */\n      __HAL_UNLOCK(hdma);\n\n      /* Change the DMA state */\n      hdma->State= HAL_DMA_STATE_READY;\n\n      return HAL_ERROR;\n   }\n  }\n  \n  /* Get the level transfer complete flag */\n  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)\n  {\n    /* Clear the half transfer and transfer complete flags */\n    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;\n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(hdma);\n\n    hdma->State = HAL_DMA_STATE_READY;\n  }\n  else\n  {\n    /* Clear the half transfer and transfer complete flags */\n    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Handles DMA interrupt request.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA Stream.  \n  * @retval None\n  */\nvoid HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)\n{\n  uint32_t tmpisr;\n  __IO uint32_t count = 0U;\n  uint32_t timeout = SystemCoreClock / 9600U;\n\n  /* calculate DMA base and stream number */\n  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;\n\n  tmpisr = regs->ISR;\n\n  /* Transfer Error Interrupt management ***************************************/\n  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)\n  {\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)\n    {\n      /* Disable the transfer error interrupt */\n      hdma->Instance->CR  &= ~(DMA_IT_TE);\n      \n      /* Clear the transfer error flag */\n      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;\n      \n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_TE;\n    }\n  }\n  /* FIFO Error Interrupt management ******************************************/\n  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)\n  {\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)\n    {\n      /* Clear the FIFO error flag */\n      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;\n\n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_FE;\n    }\n  }\n  /* Direct Mode Error Interrupt management ***********************************/\n  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)\n  {\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)\n    {\n      /* Clear the direct mode error flag */\n      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;\n\n      /* Update error code */\n      hdma->ErrorCode |= HAL_DMA_ERROR_DME;\n    }\n  }\n  /* Half Transfer Complete Interrupt management ******************************/\n  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)\n  {\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)\n    {\n      /* Clear the half transfer complete flag */\n      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;\n      \n      /* Multi_Buffering mode enabled */\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\n      {\n        /* Current memory buffer used is Memory 0 */\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\n        {\n          if(hdma->XferHalfCpltCallback != NULL)\n          {\n            /* Half transfer callback */\n            hdma->XferHalfCpltCallback(hdma);\n          }\n        }\n        /* Current memory buffer used is Memory 1 */\n        else\n        {\n          if(hdma->XferM1HalfCpltCallback != NULL)\n          {\n            /* Half transfer callback */\n            hdma->XferM1HalfCpltCallback(hdma);\n          }\n        }\n      }\n      else\n      {\n        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\n        {\n          /* Disable the half transfer interrupt */\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\n        }\n        \n        if(hdma->XferHalfCpltCallback != NULL)\n        {\n          /* Half transfer callback */\n          hdma->XferHalfCpltCallback(hdma);\n        }\n      }\n    }\n  }\n  /* Transfer Complete Interrupt management ***********************************/\n  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)\n  {\n    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)\n    {\n      /* Clear the transfer complete flag */\n      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;\n      \n      if(HAL_DMA_STATE_ABORT == hdma->State)\n      {\n        /* Disable all the transfer interrupts */\n        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);\n        hdma->Instance->FCR &= ~(DMA_IT_FE);\n        \n        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\n        {\n          hdma->Instance->CR  &= ~(DMA_IT_HT);\n        }\n\n        /* Clear all interrupt flags at correct offset within the register */\n        regs->IFCR = 0x3FU << hdma->StreamIndex;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hdma);\n\n        /* Change the DMA state */\n        hdma->State = HAL_DMA_STATE_READY;\n\n        if(hdma->XferAbortCallback != NULL)\n        {\n          hdma->XferAbortCallback(hdma);\n        }\n        return;\n      }\n\n      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)\n      {\n        /* Current memory buffer used is Memory 0 */\n        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)\n        {\n          if(hdma->XferM1CpltCallback != NULL)\n          {\n            /* Transfer complete Callback for memory1 */\n            hdma->XferM1CpltCallback(hdma);\n          }\n        }\n        /* Current memory buffer used is Memory 1 */\n        else\n        {\n          if(hdma->XferCpltCallback != NULL)\n          {\n            /* Transfer complete Callback for memory0 */\n            hdma->XferCpltCallback(hdma);\n          }\n        }\n      }\n      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */\n      else\n      {\n        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)\n        {\n          /* Disable the transfer complete interrupt */\n          hdma->Instance->CR  &= ~(DMA_IT_TC);\n\n          /* Process Unlocked */\n          __HAL_UNLOCK(hdma);\n\n          /* Change the DMA state */\n          hdma->State = HAL_DMA_STATE_READY;\n        }\n\n        if(hdma->XferCpltCallback != NULL)\n        {\n          /* Transfer complete callback */\n          hdma->XferCpltCallback(hdma);\n        }\n      }\n    }\n  }\n  \n  /* manage error case */\n  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)\n  {\n    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)\n    {\n      hdma->State = HAL_DMA_STATE_ABORT;\n\n      /* Disable the stream */\n      __HAL_DMA_DISABLE(hdma);\n\n      do\n      {\n        if (++count > timeout)\n        {\n          break;\n        }\n      }\n      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hdma);\n\n      /* Change the DMA state */\n      hdma->State = HAL_DMA_STATE_READY;\n    }\n\n    if(hdma->XferErrorCallback != NULL)\n    {\n      /* Transfer error callback */\n      hdma->XferErrorCallback(hdma);\n    }\n  }\n}\n\n/**\n  * @brief  Register callbacks\n  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\n  *                               the configuration information for the specified DMA Stream.\n  * @param  CallbackID           User Callback identifer\n  *                               a DMA_HandleTypeDef structure as parameter.\n  * @param  pCallback            pointer to private callbacsk function which has pointer to \n  *                               a DMA_HandleTypeDef structure as parameter.\n  * @retval HAL status\n  */                      \nHAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))\n{\n\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hdma);\n\n  if(HAL_DMA_STATE_READY == hdma->State)\n  {\n    switch (CallbackID)\n    {\n    case  HAL_DMA_XFER_CPLT_CB_ID:\n      hdma->XferCpltCallback = pCallback;\n      break;\n\n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\n      hdma->XferHalfCpltCallback = pCallback;\n      break;\n\n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\n      hdma->XferM1CpltCallback = pCallback;\n      break;\n\n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\n      hdma->XferM1HalfCpltCallback = pCallback;\n      break;\n\n    case  HAL_DMA_XFER_ERROR_CB_ID:\n      hdma->XferErrorCallback = pCallback;\n      break;\n\n    case  HAL_DMA_XFER_ABORT_CB_ID:\n      hdma->XferAbortCallback = pCallback;\n      break;\n\n    default:\n      break;\n    }\n  }\n  else\n  {\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hdma);\n  \n  return status;\n}\n\n/**\n  * @brief  UnRegister callbacks\n  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains\n  *                               the configuration information for the specified DMA Stream.\n  * @param  CallbackID           User Callback identifer\n  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.\n  * @retval HAL status\n  */              \nHAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Process locked */\n  __HAL_LOCK(hdma);\n  \n  if(HAL_DMA_STATE_READY == hdma->State)\n  {\n    switch (CallbackID)\n    {\n    case  HAL_DMA_XFER_CPLT_CB_ID:\n      hdma->XferCpltCallback = NULL;\n      break;\n      \n    case  HAL_DMA_XFER_HALFCPLT_CB_ID:\n      hdma->XferHalfCpltCallback = NULL;\n      break;\n      \n    case  HAL_DMA_XFER_M1CPLT_CB_ID:\n      hdma->XferM1CpltCallback = NULL;\n      break;\n      \n    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:\n      hdma->XferM1HalfCpltCallback = NULL;\n      break;\n      \n    case  HAL_DMA_XFER_ERROR_CB_ID:\n      hdma->XferErrorCallback = NULL;\n      break;\n      \n    case  HAL_DMA_XFER_ABORT_CB_ID:\n      hdma->XferAbortCallback = NULL;\n      break; \n      \n    case   HAL_DMA_XFER_ALL_CB_ID:\n      hdma->XferCpltCallback = NULL;\n      hdma->XferHalfCpltCallback = NULL;\n      hdma->XferM1CpltCallback = NULL;\n      hdma->XferM1HalfCpltCallback = NULL;\n      hdma->XferErrorCallback = NULL;\n      hdma->XferAbortCallback = NULL;\n      break; \n      \n    default:\n      status = HAL_ERROR;\n      break;\n    }\n  }\n  else\n  {\n    status = HAL_ERROR;\n  }\n  \n  /* Release Lock */\n  __HAL_UNLOCK(hdma);\n  \n  return status;\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup DMA_Exported_Functions_Group3\n  *\n@verbatim\n ===============================================================================\n                    ##### State and Errors functions #####\n ===============================================================================\n    [..]\n    This subsection provides functions allowing to\n      (+) Check the DMA state\n      (+) Get error code\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Returns the DMA state.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA Stream.\n  * @retval HAL state\n  */\nHAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)\n{\n  return hdma->State;\n}\n\n/**\n  * @brief  Return the DMA error code\n  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains\n  *              the configuration information for the specified DMA Stream.\n  * @retval DMA Error Code\n  */\nuint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)\n{\n  return hdma->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup DMA_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Sets the DMA Transfer parameter.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.\n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nstatic void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\n{\n  /* Clear DBM bit */\n  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);\n\n  /* Configure DMA Stream data length */\n  hdma->Instance->NDTR = DataLength;\n\n  /* Memory to Peripheral */\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\n  {\n    /* Configure DMA Stream destination address */\n    hdma->Instance->PAR = DstAddress;\n\n    /* Configure DMA Stream source address */\n    hdma->Instance->M0AR = SrcAddress;\n  }\n  /* Peripheral to Memory */\n  else\n  {\n    /* Configure DMA Stream source address */\n    hdma->Instance->PAR = SrcAddress;\n\n    /* Configure DMA Stream destination address */\n    hdma->Instance->M0AR = DstAddress;\n  }\n}\n\n/**\n  * @brief  Returns the DMA Stream base address depending on stream number\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream. \n  * @retval Stream base address\n  */\nstatic uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)\n{\n  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;\n  \n  /* lookup table for necessary bitshift of flags within status registers */\n  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};\n  hdma->StreamIndex = flagBitshiftOffset[stream_number];\n  \n  if (stream_number > 3U)\n  {\n    /* return pointer to HISR and HIFCR */\n    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);\n  }\n  else\n  {\n    /* return pointer to LISR and LIFCR */\n    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));\n  }\n  \n  return hdma->StreamBaseAddress;\n}\n\n/**\n  * @brief  Check compatibility between FIFO threshold level and size of the memory burst\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream. \n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  uint32_t tmp = hdma->Init.FIFOThreshold;\n  \n  /* Memory Data size equal to Byte */\n  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)\n  {\n    switch (tmp)\n    {\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\n      {\n        status = HAL_ERROR;\n      }\n      break;\n    case DMA_FIFO_THRESHOLD_HALFFULL:\n      if (hdma->Init.MemBurst == DMA_MBURST_INC16)\n      {\n        status = HAL_ERROR;\n      }\n      break;\n    case DMA_FIFO_THRESHOLD_FULL:\n      break;\n    default:\n      break;\n    }\n  }\n  \n  /* Memory Data size equal to Half-Word */\n  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)\n  {\n    switch (tmp)\n    {\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\n      status = HAL_ERROR;\n      break;\n    case DMA_FIFO_THRESHOLD_HALFFULL:\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\n      {\n        status = HAL_ERROR;\n      }\n      break;\n    case DMA_FIFO_THRESHOLD_FULL:\n      if (hdma->Init.MemBurst == DMA_MBURST_INC16)\n      {\n        status = HAL_ERROR;\n      }\n      break;   \n    default:\n      break;\n    }\n  }\n  \n  /* Memory Data size equal to Word */\n  else\n  {\n    switch (tmp)\n    {\n    case DMA_FIFO_THRESHOLD_1QUARTERFULL:\n    case DMA_FIFO_THRESHOLD_HALFFULL:\n    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:\n      status = HAL_ERROR;\n      break;\n    case DMA_FIFO_THRESHOLD_FULL:\n      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)\n      {\n        status = HAL_ERROR;\n      }\n      break;\n    default:\n      break;\n    }\n  } \n  \n  return status; \n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_DMA_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_dma_ex.c\n  * @author  MCD Application Team\n  * @brief   DMA Extension HAL module driver\n  *         This file provides firmware functions to manage the following \n  *         functionalities of the DMA Extension peripheral:\n  *           + Extended features functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n  [..]\n  The DMA Extension HAL driver can be used as follows:\n   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function\n       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.\n                   \n     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.\n     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.\n     -@-  In Multi (Double) buffer mode, it is possible to update the base address for \n          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. \n  \n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup DMAEx DMAEx\n  * @brief DMA Extended HAL module driver\n  * @{\n  */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private Constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/** @addtogroup DMAEx_Private_Functions\n  * @{\n  */\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);\n/**\n  * @}\n  */\n\n/* Exported functions ---------------------------------------------------------*/\n\n/** @addtogroup DMAEx_Exported_Functions\n  * @{\n  */\n\n\n/** @addtogroup DMAEx_Exported_Functions_Group1\n  *\n@verbatim   \n ===============================================================================\n                #####  Extended features functions  #####\n ===============================================================================  \n    [..]  This section provides functions allowing to:\n      (+) Configure the source, destination address and data length and \n          Start MultiBuffer DMA transfer\n      (+) Configure the source, destination address and data length and \n          Start MultiBuffer DMA transfer with interrupt\n      (+) Change on the fly the memory0 or memory1 address.\n      \n@endverbatim\n  * @{\n  */\n\n\n/**\n  * @brief  Starts the multi_buffer DMA Transfer.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.  \n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  \n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\n  \n  /* Memory-to-memory transfer not supported in double buffering mode */\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\n    status = HAL_ERROR;\n  }\n  else\n  {\n    /* Process Locked */\n    __HAL_LOCK(hdma);\n    \n    if(HAL_DMA_STATE_READY == hdma->State)\n    {\n      /* Change DMA peripheral state */\n      hdma->State = HAL_DMA_STATE_BUSY; \n      \n      /* Enable the double buffer mode */\n      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\n      \n      /* Configure DMA Stream destination address */\n      hdma->Instance->M1AR = SecondMemAddress;\n      \n      /* Configure the source, destination address and the data length */\n      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);\n      \n      /* Enable the peripheral */\n      __HAL_DMA_ENABLE(hdma);\n    }\n    else\n    {\n      /* Return error status */\n      status = HAL_BUSY;\n    }\n  }\n  return status;\n}\n\n/**\n  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.  \n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  \n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_DMA_BUFFER_SIZE(DataLength));\n  \n  /* Memory-to-memory transfer not supported in double buffering mode */\n  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;\n    return HAL_ERROR;\n  }\n  \n  /* Check callback functions */\n  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))\n  {\n    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;\n    return HAL_ERROR;\n  }\n  \n  /* Process locked */\n  __HAL_LOCK(hdma);\n  \n  if(HAL_DMA_STATE_READY == hdma->State)\n  {\n    /* Change DMA peripheral state */\n    hdma->State = HAL_DMA_STATE_BUSY;\n    \n    /* Initialize the error code */\n    hdma->ErrorCode = HAL_DMA_ERROR_NONE;\n    \n    /* Enable the Double buffer mode */\n    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;\n    \n    /* Configure DMA Stream destination address */\n    hdma->Instance->M1AR = SecondMemAddress;\n    \n    /* Configure the source, destination address and the data length */\n    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); \n    \n    /* Clear all flags */\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));\n    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));\n\n    /* Enable Common interrupts*/\n    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;\n    hdma->Instance->FCR |= DMA_IT_FE;\n    \n    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))\n    {\n      hdma->Instance->CR  |= DMA_IT_HT;\n    }\n    \n    /* Enable the peripheral */\n    __HAL_DMA_ENABLE(hdma); \n  }\n  else\n  {     \n    /* Process unlocked */\n    __HAL_UNLOCK(hdma);\t  \n    \n    /* Return error status */\n    status = HAL_BUSY;\n  }  \n  return status; \n}\n\n/**\n  * @brief  Change the memory0 or memory1 address on the fly.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.  \n  * @param  Address    The new address\n  * @param  memory     the memory to be changed, This parameter can be one of \n  *                     the following values:\n  *                      MEMORY0 /\n  *                      MEMORY1\n  * @note   The MEMORY0 address can be changed only when the current transfer use\n  *         MEMORY1 and the MEMORY1 address can be changed only when the current \n  *         transfer use MEMORY0.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)\n{\n  if(memory == MEMORY0)\n  {\n    /* change the memory0 address */\n    hdma->Instance->M0AR = Address;\n  }\n  else\n  {\n    /* change the memory1 address */\n    hdma->Instance->M1AR = Address;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup DMAEx_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Set the DMA Transfer parameter.\n  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains\n  *                     the configuration information for the specified DMA Stream.  \n  * @param  SrcAddress The source memory Buffer address\n  * @param  DstAddress The destination memory Buffer address\n  * @param  DataLength The length of data to be transferred from source to destination\n  * @retval HAL status\n  */\nstatic void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)\n{  \n  /* Configure DMA Stream data length */\n  hdma->Instance->NDTR = DataLength;\n  \n  /* Peripheral to Memory */\n  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)\n  {   \n    /* Configure DMA Stream destination address */\n    hdma->Instance->PAR = DstAddress;\n    \n    /* Configure DMA Stream source address */\n    hdma->Instance->M0AR = SrcAddress;\n  }\n  /* Memory to Peripheral */\n  else\n  {\n    /* Configure DMA Stream source address */\n    hdma->Instance->PAR = SrcAddress;\n    \n    /* Configure DMA Stream destination address */\n    hdma->Instance->M0AR = DstAddress;\n  }\n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_DMA_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_exti.c\n  * @author  MCD Application Team\n  * @brief   EXTI HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *\n  @verbatim\n  ==============================================================================\n                    ##### EXTI Peripheral features #####\n  ==============================================================================\n  [..]\n    (+) Each Exti line can be configured within this driver.\n\n    (+) Exti line can be configured in 3 different modes\n        (++) Interrupt\n        (++) Event\n        (++) Both of them\n\n    (+) Configurable Exti lines can be configured with 3 different triggers\n        (++) Rising\n        (++) Falling\n        (++) Both of them\n\n    (+) When set in interrupt mode, configurable Exti lines have two different\n        interrupts pending registers which allow to distinguish which transition\n        occurs:\n        (++) Rising edge pending interrupt\n        (++) Falling\n\n    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can\n        be selected through multiplexer.\n\n                     ##### How to use this driver #####\n  ==============================================================================\n  [..]\n\n    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().\n        (++) Choose the interrupt line number by setting \"Line\" member from\n             EXTI_ConfigTypeDef structure.\n        (++) Configure the interrupt and/or event mode using \"Mode\" member from\n             EXTI_ConfigTypeDef structure.\n        (++) For configurable lines, configure rising and/or falling trigger\n             \"Trigger\" member from EXTI_ConfigTypeDef structure.\n        (++) For Exti lines linked to gpio, choose gpio port using \"GPIOSel\"\n             member from GPIO_InitTypeDef structure.\n\n    (#) Get current Exti configuration of a dedicated line using\n        HAL_EXTI_GetConfigLine().\n        (++) Provide exiting handle as parameter.\n        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.\n\n    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().\n        (++) Provide exiting handle as parameter.\n\n    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().\n        (++) Provide exiting handle as first parameter.\n        (++) Provide which callback will be registered using one value from\n             EXTI_CallbackIDTypeDef.\n        (++) Provide callback function pointer.\n\n    (#) Get interrupt pending bit using HAL_EXTI_GetPending().\n\n    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().\n\n    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @addtogroup EXTI\n  * @{\n  */\n/** MISRA C:2012 deviation rule has been granted for following rule:\n  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out\n  * of bounds [0,3] in following API :\n  * HAL_EXTI_SetConfigLine\n  * HAL_EXTI_GetConfigLine\n  * HAL_EXTI_ClearConfigLine\n  */\n\n#ifdef HAL_EXTI_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private defines -----------------------------------------------------------*/\n/** @defgroup EXTI_Private_Constants EXTI Private Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n\n/** @addtogroup EXTI_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup EXTI_Exported_Functions_Group1\n  *  @brief    Configuration functions\n  *\n@verbatim\n ===============================================================================\n              ##### Configuration functions #####\n ===============================================================================\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Set configuration of a dedicated Exti line.\n  * @param  hexti Exti handle.\n  * @param  pExtiConfig Pointer on EXTI configuration to be set.\n  * @retval HAL Status.\n  */\nHAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\n{\n  uint32_t regval;\n  uint32_t linepos;\n  uint32_t maskline;\n\n  /* Check null pointer */\n  if ((hexti == NULL) || (pExtiConfig == NULL))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check parameters */\n  assert_param(IS_EXTI_LINE(pExtiConfig->Line));\n  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));\n\n  /* Assign line number to handle */\n  hexti->Line = pExtiConfig->Line;\n\n  /* Compute line mask */\n  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\n  maskline = (1uL << linepos);\n\n  /* Configure triggers for configurable lines */\n  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\n  {\n    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));\n\n    /* Configure rising trigger */\n    /* Mask or set line */\n    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)\n    {\n      EXTI->RTSR |= maskline;\n    }\n    else\n    {\n      EXTI->RTSR &= ~maskline;\n    }\n\n    /* Configure falling trigger */\n    /* Mask or set line */\n    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)\n    {\n      EXTI->FTSR |= maskline;\n    }\n    else\n    {\n      EXTI->FTSR &= ~maskline;\n    }\n\n\n    /* Configure gpio port selection in case of gpio exti line */\n    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\n    {\n      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));\n      assert_param(IS_EXTI_GPIO_PIN(linepos));\n\n      regval = SYSCFG->EXTICR[linepos >> 2u];\n      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\n      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\n      SYSCFG->EXTICR[linepos >> 2u] = regval;\n    }\n  }\n\n  /* Configure interrupt mode : read current mode */\n  /* Mask or set line */\n  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)\n  {\n    EXTI->IMR |= maskline;\n  }\n  else\n  {\n    EXTI->IMR &= ~maskline;\n  }\n\n  /* Configure event mode : read current mode */\n  /* Mask or set line */\n  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)\n  {\n    EXTI->EMR |= maskline;\n  }\n  else\n  {\n    EXTI->EMR &= ~maskline;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Get configuration of a dedicated Exti line.\n  * @param  hexti Exti handle.\n  * @param  pExtiConfig Pointer on structure to store Exti configuration.\n  * @retval HAL Status.\n  */\nHAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)\n{\n  uint32_t regval;\n  uint32_t linepos;\n  uint32_t maskline;\n\n  /* Check null pointer */\n  if ((hexti == NULL) || (pExtiConfig == NULL))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameter */\n  assert_param(IS_EXTI_LINE(hexti->Line));\n\n  /* Store handle line number to configuration structure */\n  pExtiConfig->Line = hexti->Line;\n\n  /* Compute line mask */\n  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);\n  maskline = (1uL << linepos);\n\n  /* 1] Get core mode : interrupt */\n\n  /* Check if selected line is enable */\n  if ((EXTI->IMR & maskline) != 0x00u)\n  {\n    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;\n  }\n  else\n  {\n    pExtiConfig->Mode = EXTI_MODE_NONE;\n  }\n\n  /* Get event mode */\n  /* Check if selected line is enable */\n  if ((EXTI->EMR & maskline) != 0x00u)\n  {\n    pExtiConfig->Mode |= EXTI_MODE_EVENT;\n  }\n\n  /* 2] Get trigger for configurable lines : rising */\n  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)\n  {\n    /* Check if configuration of selected line is enable */\n    if ((EXTI->RTSR & maskline) != 0x00u)\n    {\n      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;\n    }\n    else\n    {\n      pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\n    }\n\n    /* Get falling configuration */\n    /* Check if configuration of selected line is enable */\n    if ((EXTI->FTSR & maskline) != 0x00u)\n    {\n      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;\n    }\n\n    /* Get Gpio port selection for gpio lines */\n    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)\n    {\n      assert_param(IS_EXTI_GPIO_PIN(linepos));\n\n      regval = SYSCFG->EXTICR[linepos >> 2u];\n      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);\n    }\n    else\n    {\n      pExtiConfig->GPIOSel = 0x00u;\n    }\n  }\n  else\n  {\n    /* No Trigger selected */\n    pExtiConfig->Trigger = EXTI_TRIGGER_NONE;\n    pExtiConfig->GPIOSel = 0x00u;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Clear whole configuration of a dedicated Exti line.\n  * @param  hexti Exti handle.\n  * @retval HAL Status.\n  */\nHAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)\n{\n  uint32_t regval;\n  uint32_t linepos;\n  uint32_t maskline;\n\n  /* Check null pointer */\n  if (hexti == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameter */\n  assert_param(IS_EXTI_LINE(hexti->Line));\n\n  /* compute line mask */\n  linepos = (hexti->Line & EXTI_PIN_MASK);\n  maskline = (1uL << linepos);\n\n  /* 1] Clear interrupt mode */\n  EXTI->IMR = (EXTI->IMR & ~maskline);\n\n  /* 2] Clear event mode */\n  EXTI->EMR = (EXTI->EMR & ~maskline);\n\n  /* 3] Clear triggers in case of configurable lines */\n  if ((hexti->Line & EXTI_CONFIG) != 0x00u)\n  {\n    EXTI->RTSR = (EXTI->RTSR & ~maskline);\n    EXTI->FTSR = (EXTI->FTSR & ~maskline);\n\n    /* Get Gpio port selection for gpio lines */\n    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)\n    {\n      assert_param(IS_EXTI_GPIO_PIN(linepos));\n\n      regval = SYSCFG->EXTICR[linepos >> 2u];\n      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));\n      SYSCFG->EXTICR[linepos >> 2u] = regval;\n    }\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Register callback for a dedicated Exti line.\n  * @param  hexti Exti handle.\n  * @param  CallbackID User callback identifier.\n  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.\n  * @param  pPendingCbfn function pointer to be stored as callback.\n  * @retval HAL Status.\n  */\nHAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  switch (CallbackID)\n  {\n    case  HAL_EXTI_COMMON_CB_ID:\n      hexti->PendingCallback = pPendingCbfn;\n      break;\n\n    default:\n      status = HAL_ERROR;\n      break;\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Store line number as handle private field.\n  * @param  hexti Exti handle.\n  * @param  ExtiLine Exti line number.\n  *         This parameter can be from 0 to @ref EXTI_LINE_NB.\n  * @retval HAL Status.\n  */\nHAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)\n{\n  /* Check the parameters */\n  assert_param(IS_EXTI_LINE(ExtiLine));\n\n  /* Check null pointer */\n  if (hexti == NULL)\n  {\n    return HAL_ERROR;\n  }\n  else\n  {\n    /* Store line number as handle private field */\n    hexti->Line = ExtiLine;\n\n    return HAL_OK;\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @addtogroup EXTI_Exported_Functions_Group2\n  *  @brief EXTI IO functions.\n  *\n@verbatim\n ===============================================================================\n                       ##### IO operation functions #####\n ===============================================================================\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Handle EXTI interrupt request.\n  * @param  hexti Exti handle.\n  * @retval none.\n  */\nvoid HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)\n{\n  uint32_t regval;\n  uint32_t maskline;\n\n  /* Compute line mask */\n  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\n\n  /* Get pending bit  */\n  regval = (EXTI->PR & maskline);\n  if (regval != 0x00u)\n  {\n    /* Clear pending bit */\n    EXTI->PR = maskline;\n\n    /* Call callback */\n    if (hexti->PendingCallback != NULL)\n    {\n      hexti->PendingCallback();\n    }\n  }\n}\n\n/**\n  * @brief  Get interrupt pending bit of a dedicated line.\n  * @param  hexti Exti handle.\n  * @param  Edge Specify which pending edge as to be checked.\n  *         This parameter can be one of the following values:\n  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\n  *         This parameter is kept for compatibility with other series.\n  * @retval 1 if interrupt is pending else 0.\n  */\nuint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\n{\n  uint32_t regval;\n  uint32_t linepos;\n  uint32_t maskline;\n\n  /* Check parameters */\n  assert_param(IS_EXTI_LINE(hexti->Line));\n  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\n  assert_param(IS_EXTI_PENDING_EDGE(Edge));\n\n  /* Compute line mask */\n  linepos = (hexti->Line & EXTI_PIN_MASK);\n  maskline = (1uL << linepos);\n\n  /* return 1 if bit is set else 0 */\n  regval = ((EXTI->PR & maskline) >> linepos);\n  return regval;\n}\n\n/**\n  * @brief  Clear interrupt pending bit of a dedicated line.\n  * @param  hexti Exti handle.\n  * @param  Edge Specify which pending edge as to be clear.\n  *         This parameter can be one of the following values:\n  *           @arg @ref EXTI_TRIGGER_RISING_FALLING\n  *         This parameter is kept for compatibility with other series.\n  * @retval None.\n  */\nvoid HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)\n{\n  uint32_t maskline;\n\n  /* Check parameters */\n  assert_param(IS_EXTI_LINE(hexti->Line));\n  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\n  assert_param(IS_EXTI_PENDING_EDGE(Edge));\n\n  /* Compute line mask */\n  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\n\n  /* Clear Pending bit */\n  EXTI->PR =  maskline;\n}\n\n/**\n  * @brief  Generate a software interrupt for a dedicated line.\n  * @param  hexti Exti handle.\n  * @retval None.\n  */\nvoid HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)\n{\n  uint32_t maskline;\n\n  /* Check parameters */\n  assert_param(IS_EXTI_LINE(hexti->Line));\n  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));\n\n  /* Compute line mask */\n  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));\n\n  /* Generate Software interrupt */\n  EXTI->SWIER = maskline;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_EXTI_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash.c\n  * @author  MCD Application Team\n  * @brief   FLASH HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of the internal FLASH memory:\n  *           + Program operations functions\n  *           + Memory Control functions \n  *           + Peripheral Errors functions\n  *         \n  @verbatim\n  ==============================================================================\n                        ##### FLASH peripheral features #####\n  ==============================================================================\n           \n  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses \n       to the Flash memory. It implements the erase and program Flash memory operations \n       and the read and write protection mechanisms.\n      \n  [..] The Flash memory interface accelerates code execution with a system of instruction\n       prefetch and cache lines. \n\n  [..] The FLASH main features are:\n      (+) Flash memory read operations\n      (+) Flash memory program/erase operations\n      (+) Read / write protections\n      (+) Prefetch on I-Code\n      (+) 64 cache lines of 128 bits on I-Code\n      (+) 8 cache lines of 128 bits on D-Code\n      \n      \n                     ##### How to use this driver #####\n  ==============================================================================\n    [..]                             \n      This driver provides functions and macros to configure and program the FLASH \n      memory of all STM32F4xx devices.\n    \n      (#) FLASH Memory IO Programming functions: \n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \n                HAL_FLASH_Lock() functions\n           (++) Program functions: byte, half word, word and double word\n           (++) There Two modes of programming :\n            (+++) Polling mode using HAL_FLASH_Program() function\n            (+++) Interrupt mode using HAL_FLASH_Program_IT() function\n    \n      (#) Interrupts and flags management functions : \n           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()\n           (++) Wait for last FLASH operation according to its status\n           (++) Get error flag status by calling HAL_SetErrorCode()          \n\n    [..] \n      In addition to these functions, this driver includes a set of macros allowing\n      to handle the following operations:\n       (+) Set the latency\n       (+) Enable/Disable the prefetch buffer\n       (+) Enable/Disable the Instruction cache and the Data cache\n       (+) Reset the Instruction cache and the Data cache\n       (+) Enable/Disable the FLASH interrupts\n       (+) Monitor the FLASH flags status\n          \n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup FLASH FLASH\n  * @brief FLASH HAL module driver\n  * @{\n  */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup FLASH_Private_Constants\n  * @{\n  */\n#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */\n/**\n  * @}\n  */         \n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup FLASH_Private_Variables\n  * @{\n  */\n/* Variable used for Erase sectors under interruption */\nFLASH_ProcessTypeDef pFlash;\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n/** @addtogroup FLASH_Private_Functions\n  * @{\n  */\n/* Program operations */\nstatic void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);\nstatic void   FLASH_Program_Word(uint32_t Address, uint32_t Data);\nstatic void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);\nstatic void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);\nstatic void   FLASH_SetErrorCode(void);\n\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup FLASH_Exported_Functions FLASH Exported Functions\n  * @{\n  */\n  \n/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions \n *  @brief   Programming operation functions \n *\n@verbatim   \n ===============================================================================\n                  ##### Programming operation functions #####\n ===============================================================================  \n    [..]\n    This subsection provides a set of functions allowing to manage the FLASH \n    program operations.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Program byte, halfword, word or double word at a specified address\n  * @param  TypeProgram  Indicate the way to program at a specified address.\n  *                           This parameter can be a value of @ref FLASH_Type_Program\n  * @param  Address  specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed\n  * \n  * @retval HAL_StatusTypeDef HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\n{\n  HAL_StatusTypeDef status = HAL_ERROR;\n  \n  /* Process Locked */\n  __HAL_LOCK(&pFlash);\n  \n  /* Check the parameters */\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\n  \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n  \n  if(status == HAL_OK)\n  {\n    if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)\n    {\n      /*Program byte (8-bit) at a specified address.*/\n      FLASH_Program_Byte(Address, (uint8_t) Data);\n    }\n    else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)\n    {\n      /*Program halfword (16-bit) at a specified address.*/\n      FLASH_Program_HalfWord(Address, (uint16_t) Data);\n    }\n    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)\n    {\n      /*Program word (32-bit) at a specified address.*/\n      FLASH_Program_Word(Address, (uint32_t) Data);\n    }\n    else\n    {\n      /*Program double word (64-bit) at a specified address.*/\n      FLASH_Program_DoubleWord(Address, Data);\n    }\n    \n    /* Wait for last operation to be completed */\n    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n    \n    /* If the program operation is completed, disable the PG Bit */\n    FLASH->CR &= (~FLASH_CR_PG);  \n  }\n  \n  /* Process Unlocked */\n  __HAL_UNLOCK(&pFlash);\n  \n  return status;\n}\n\n/**\n  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.\n  * @param  TypeProgram  Indicate the way to program at a specified address.\n  *                           This parameter can be a value of @ref FLASH_Type_Program\n  * @param  Address  specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Process Locked */\n  __HAL_LOCK(&pFlash);\n\n  /* Check the parameters */\n  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));\n\n  /* Enable End of FLASH Operation interrupt */\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\n  \n  /* Enable Error source interrupt */\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\n\n  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;\n  pFlash.Address = Address;\n\n  if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)\n  {\n    /*Program byte (8-bit) at a specified address.*/\n      FLASH_Program_Byte(Address, (uint8_t) Data);\n  }\n  else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)\n  {\n    /*Program halfword (16-bit) at a specified address.*/\n    FLASH_Program_HalfWord(Address, (uint16_t) Data);\n  }\n  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)\n  {\n    /*Program word (32-bit) at a specified address.*/\n    FLASH_Program_Word(Address, (uint32_t) Data);\n  }\n  else\n  {\n    /*Program double word (64-bit) at a specified address.*/\n    FLASH_Program_DoubleWord(Address, Data);\n  }\n\n  return status;\n}\n\n/**\n  * @brief This function handles FLASH interrupt request.\n  * @retval None\n  */\nvoid HAL_FLASH_IRQHandler(void)\n{\n  uint32_t addresstmp = 0U;\n  \n  /* Check FLASH operation error flags */\n#if defined(FLASH_SR_RDERR) \n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\n    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)\n#else\n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\n    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)\n#endif /* FLASH_SR_RDERR */\n  {\n    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)\n    {\n      /*return the faulty sector*/\n      addresstmp = pFlash.Sector;\n      pFlash.Sector = 0xFFFFFFFFU;\n    }\n    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)\n    {\n      /*return the faulty bank*/\n      addresstmp = pFlash.Bank;\n    }\n    else\n    {\n      /*return the faulty address*/\n      addresstmp = pFlash.Address;\n    }\n    \n    /*Save the Error code*/\n    FLASH_SetErrorCode();\n    \n    /* FLASH error interrupt user callback */\n    HAL_FLASH_OperationErrorCallback(addresstmp);\n    \n    /*Stop the procedure ongoing*/\n    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\n  }\n  \n  /* Check FLASH End of Operation flag  */\n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\n  {\n    /* Clear FLASH End of Operation pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\n    \n    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)\n    {\n      /*Nb of sector to erased can be decreased*/\n      pFlash.NbSectorsToErase--;\n      \n      /* Check if there are still sectors to erase*/\n      if(pFlash.NbSectorsToErase != 0U)\n      {\n        addresstmp = pFlash.Sector;\n        /*Indicate user which sector has been erased*/\n        HAL_FLASH_EndOfOperationCallback(addresstmp);\n        \n        /*Increment sector number*/\n        pFlash.Sector++;\n        addresstmp = pFlash.Sector;\n        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);\n      }\n      else\n      {\n        /*No more sectors to Erase, user callback can be called.*/\n        /*Reset Sector and stop Erase sectors procedure*/\n        pFlash.Sector = addresstmp = 0xFFFFFFFFU;\n        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\n        \n        /* Flush the caches to be sure of the data consistency */\n        FLASH_FlushCaches() ;\n                \n        /* FLASH EOP interrupt user callback */\n        HAL_FLASH_EndOfOperationCallback(addresstmp);\n      }\n    }\n    else \n    {\n      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) \n      {\n        /* MassErase ended. Return the selected bank */\n        /* Flush the caches to be sure of the data consistency */\n        FLASH_FlushCaches() ;\n\n        /* FLASH EOP interrupt user callback */\n        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);\n      }\n      else\n      {\n        /*Program ended. Return the selected address*/\n        /* FLASH EOP interrupt user callback */\n        HAL_FLASH_EndOfOperationCallback(pFlash.Address);\n      }\n      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;\n    }\n  }\n  \n  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)\n  {\n    /* Operation is completed, disable the PG, SER, SNB and MER Bits */\n    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));\n\n    /* Disable End of FLASH Operation interrupt */\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);\n    \n    /* Disable Error source interrupt */\n    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);\n    \n    /* Process Unlocked */\n    __HAL_UNLOCK(&pFlash);\n  }\n}\n\n/**\n  * @brief  FLASH end of operation interrupt callback\n  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure\n  *                  Mass Erase: Bank number which has been requested to erase\n  *                  Sectors Erase: Sector which has been erased \n  *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)\n  *                  Program: Address which was selected for data program\n  * @retval None\n  */\n__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(ReturnValue);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file\n   */ \n}\n\n/**\n  * @brief  FLASH operation error interrupt callback\n  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure\n  *                 Mass Erase: Bank number which has been requested to erase\n  *                 Sectors Erase: Sector number which returned an error\n  *                 Program: Address which was selected for data program\n  * @retval None\n  */\n__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(ReturnValue);\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_FLASH_OperationErrorCallback could be implemented in the user file\n   */ \n}\n\n/**\n  * @}\n  */\n\n/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions \n *  @brief   management functions \n *\n@verbatim   \n ===============================================================================\n                      ##### Peripheral Control functions #####\n ===============================================================================  \n    [..]\n    This subsection provides a set of functions allowing to control the FLASH \n    memory operations.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Unlock the FLASH control register access\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_Unlock(void)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\n  {\n    /* Authorize the FLASH Registers access */\n    WRITE_REG(FLASH->KEYR, FLASH_KEY1);\n    WRITE_REG(FLASH->KEYR, FLASH_KEY2);\n\n    /* Verify Flash is unlocked */\n    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)\n    {\n      status = HAL_ERROR;\n    }\n  }\n\n  return status;\n}\n\n/**\n  * @brief  Locks the FLASH control register access\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_Lock(void)\n{\n  /* Set the LOCK Bit to lock the FLASH Registers access */\n  FLASH->CR |= FLASH_CR_LOCK;\n  \n  return HAL_OK;  \n}\n\n/**\n  * @brief  Unlock the FLASH Option Control Registers access.\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)\n{\n  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)\n  {\n    /* Authorizes the Option Byte register programming */\n    FLASH->OPTKEYR = FLASH_OPT_KEY1;\n    FLASH->OPTKEYR = FLASH_OPT_KEY2;\n  }\n  else\n  {\n    return HAL_ERROR;\n  }  \n  \n  return HAL_OK;  \n}\n\n/**\n  * @brief  Lock the FLASH Option Control Registers access.\n  * @retval HAL Status \n  */\nHAL_StatusTypeDef HAL_FLASH_OB_Lock(void)\n{\n  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */\n  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;\n  \n  return HAL_OK;  \n}\n\n/**\n  * @brief  Launch the option byte loading.\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASH_OB_Launch(void)\n{\n  /* Set the OPTSTRT bit in OPTCR register */\n  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;\n\n  /* Wait for last operation to be completed */\n  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); \n}\n\n/**\n  * @}\n  */\n\n/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions \n *  @brief   Peripheral Errors functions \n *\n@verbatim   \n ===============================================================================\n                ##### Peripheral Errors functions #####\n ===============================================================================  \n    [..]\n    This subsection permits to get in run-time Errors of the FLASH peripheral.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Get the specific FLASH error flag.\n  * @retval FLASH_ErrorCode: The returned value can be a combination of:\n  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)\n  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag \n  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  \n  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag\n  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag\n  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag \n  */\nuint32_t HAL_FLASH_GetError(void)\n{ \n   return pFlash.ErrorCode;\n}  \n  \n/**\n  * @}\n  */    \n\n/**\n  * @brief  Wait for a FLASH operation to complete.\n  * @param  Timeout maximum flash operationtimeout\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)\n{ \n  uint32_t tickstart = 0U;\n  \n  /* Clear Error Code */\n  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;\n  \n  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.\n     Even if the FLASH operation fails, the BUSY flag will be reset and an error\n     flag will be set */\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) \n  { \n    if(Timeout != HAL_MAX_DELAY)\n    {\n      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))\n      {\n        return HAL_TIMEOUT;\n      }\n    } \n  }\n\n  /* Check FLASH End of Operation flag  */\n  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)\n  {\n    /* Clear FLASH End of Operation pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);\n  }\n#if defined(FLASH_SR_RDERR)  \n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\n                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)\n#else\n  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \\\n                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)\n#endif /* FLASH_SR_RDERR */\n  {\n    /*Save the error code*/\n    FLASH_SetErrorCode();\n    return HAL_ERROR;\n  }\n\n  /* If there is no error flag set */\n  return HAL_OK;\n  \n}  \n\n/**\n  * @brief  Program a double word (64-bit) at a specified address.\n  * @note   This function must be used when the device voltage range is from\n  *         2.7V to 3.6V and Vpp in the range 7V to 9V.\n  *\n  * @note   If an erase and a program operations are requested simultaneously,    \n  *         the erase operation is performed before the program one.\n  *  \n  * @param  Address specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed.\n  * @retval None\n  */\nstatic void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)\n{\n  /* Check the parameters */\n  assert_param(IS_FLASH_ADDRESS(Address));\n  \n  /* If the previous operation is completed, proceed to program the new data */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;\n  FLASH->CR |= FLASH_CR_PG;\n\n  /* Program first word */\n  *(__IO uint32_t*)Address = (uint32_t)Data;\n\n  /* Barrier to ensure programming is performed in 2 steps, in right order\n    (independently of compiler optimization behavior) */\n  __ISB();\n\n  /* Program second word */\n  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);\n}\n\n\n/**\n  * @brief  Program word (32-bit) at a specified address.\n  * @note   This function must be used when the device voltage range is from\n  *         2.7V to 3.6V.\n  *\n  * @note   If an erase and a program operations are requested simultaneously,    \n  *         the erase operation is performed before the program one.\n  *  \n  * @param  Address specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed.\n  * @retval None\n  */\nstatic void FLASH_Program_Word(uint32_t Address, uint32_t Data)\n{\n  /* Check the parameters */\n  assert_param(IS_FLASH_ADDRESS(Address));\n  \n  /* If the previous operation is completed, proceed to program the new data */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= FLASH_PSIZE_WORD;\n  FLASH->CR |= FLASH_CR_PG;\n\n  *(__IO uint32_t*)Address = Data;\n}\n\n/**\n  * @brief  Program a half-word (16-bit) at a specified address.\n  * @note   This function must be used when the device voltage range is from\n  *         2.1V to 3.6V.\n  *\n  * @note   If an erase and a program operations are requested simultaneously,    \n  *         the erase operation is performed before the program one.\n  *  \n  * @param  Address specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed.\n  * @retval None\n  */\nstatic void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)\n{\n  /* Check the parameters */\n  assert_param(IS_FLASH_ADDRESS(Address));\n  \n  /* If the previous operation is completed, proceed to program the new data */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= FLASH_PSIZE_HALF_WORD;\n  FLASH->CR |= FLASH_CR_PG;\n\n  *(__IO uint16_t*)Address = Data;\n}\n\n/**\n  * @brief  Program byte (8-bit) at a specified address.\n  * @note   This function must be used when the device voltage range is from\n  *         1.8V to 3.6V.\n  *\n  * @note   If an erase and a program operations are requested simultaneously,    \n  *         the erase operation is performed before the program one.\n  *  \n  * @param  Address specifies the address to be programmed.\n  * @param  Data specifies the data to be programmed.\n  * @retval None\n  */\nstatic void FLASH_Program_Byte(uint32_t Address, uint8_t Data)\n{\n  /* Check the parameters */\n  assert_param(IS_FLASH_ADDRESS(Address));\n  \n  /* If the previous operation is completed, proceed to program the new data */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= FLASH_PSIZE_BYTE;\n  FLASH->CR |= FLASH_CR_PG;\n\n  *(__IO uint8_t*)Address = Data;\n}\n\n/**\n  * @brief  Set the specific FLASH error flag.\n  * @retval None\n  */\nstatic void FLASH_SetErrorCode(void)\n{ \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)\n  {\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;\n   \n   /* Clear FLASH write protection error pending bit */\n   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);\n  }\n  \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)\n  {\n   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;\n   \n   /* Clear FLASH Programming alignment error pending bit */\n   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);\n  }\n  \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)\n  {\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;\n    \n    /* Clear FLASH Programming parallelism error pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);\n  }\n  \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)\n  {\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;\n    \n    /* Clear FLASH Programming sequence error pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);\n  }\n#if defined(FLASH_SR_RDERR) \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)\n  {\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;\n    \n    /* Clear FLASH Proprietary readout protection error pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);\n  }\n#endif /* FLASH_SR_RDERR */  \n  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)\n  {\n    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;\n    \n    /* Clear FLASH Operation error pending bit */\n    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);\n  }\n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_FLASH_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash_ex.c\n  * @author  MCD Application Team\n  * @brief   Extended FLASH HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of the FLASH extension peripheral:\n  *           + Extended programming operations functions\n  *  \n  @verbatim\n  ==============================================================================\n                   ##### Flash Extension features #####\n  ==============================================================================\n           \n  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and \n       STM32F429xx/439xx devices contains the following additional features \n       \n       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write\n           capability (RWW)\n       (+) Dual bank memory organization       \n       (+) PCROP protection for all banks\n   \n                      ##### How to use this driver #####\n  ==============================================================================\n  [..] This driver provides functions to configure and program the FLASH memory \n       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx \n       devices. It includes\n      (#) FLASH Memory Erase functions: \n           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and \n                HAL_FLASH_Lock() functions\n           (++) Erase function: Erase sector, erase all sectors\n           (++) There are two modes of erase :\n             (+++) Polling Mode using HAL_FLASHEx_Erase()\n             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()\n             \n      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :\n           (++) Set/Reset the write protection\n           (++) Set the Read protection Level\n           (++) Set the BOR level\n           (++) Program the user Option Bytes\n      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :  \n       (++) Extended space (bank 2) erase function\n       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)\n       (++) Dual Boot activation\n       (++) Write protection configuration for bank 2\n       (++) PCROP protection configuration and control for both banks\n  \n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup FLASHEx FLASHEx\n  * @brief FLASH HAL Extension module driver\n  * @{\n  */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup FLASHEx_Private_Constants\n  * @{\n  */    \n#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */\n/**\n  * @}\n  */\n    \n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/** @addtogroup FLASHEx_Private_Variables\n  * @{\n  */    \nextern FLASH_ProcessTypeDef pFlash;\n/**\n  * @}\n  */\n\n/* Private function prototypes -----------------------------------------------*/\n/** @addtogroup FLASHEx_Private_Functions\n  * @{\n  */\n/* Option bytes control */\nstatic void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);\nstatic HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);\nstatic HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);\nstatic HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);\nstatic HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);\nstatic HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);\nstatic uint8_t            FLASH_OB_GetUser(void);\nstatic uint16_t           FLASH_OB_GetWRP(void);\nstatic uint8_t            FLASH_OB_GetRDP(void);\nstatic uint8_t            FLASH_OB_GetBOR(void);\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\\\n    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\nstatic HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);\nstatic HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx\n          STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \nstatic HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);\nstatic HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);\nstatic HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\nextern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions\n  * @{\n  */\n\n/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions\n *  @brief   Extended IO operation functions \n *\n@verbatim   \n ===============================================================================\n                ##### Extended programming operation functions #####\n ===============================================================================  \n    [..]\n    This subsection provides a set of functions allowing to manage the Extension FLASH \n    programming operations.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors \n  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\n  *         contains the configuration information for the erasing.\n  * \n  * @param[out]  SectorError pointer to variable  that\n  *         contains the configuration information on faulty sector in case of error \n  *         (0xFFFFFFFFU means that all the sectors have been correctly erased)\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)\n{\n  HAL_StatusTypeDef status = HAL_ERROR;\n  uint32_t index = 0U;\n  \n  /* Process Locked */\n  __HAL_LOCK(&pFlash);\n\n  /* Check the parameters */\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\n\n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  {\n    /*Initialization of SectorError variable*/\n    *SectorError = 0xFFFFFFFFU;\n    \n    if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\n    {\n      /*Mass erase to be done*/\n      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\n\n      /* Wait for last operation to be completed */\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n      \n      /* if the erase operation is completed, disable the MER Bit */\n      FLASH->CR &= (~FLASH_MER_BIT);\n    }\n    else\n    {\n      /* Check the parameters */\n      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\n\n      /* Erase by sector by sector to be done*/\n      for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)\n      {\n        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);\n\n        /* Wait for last operation to be completed */\n        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n        \n        /* If the erase operation is completed, disable the SER and SNB Bits */\n        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));\n\n        if(status != HAL_OK) \n        {\n          /* In case of error, stop erase procedure and return the faulty sector*/\n          *SectorError = index;\n          break;\n        }\n      }\n    }\n    /* Flush the caches to be sure of the data consistency */\n    FLASH_FlushCaches();    \n  }\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(&pFlash);\n\n  return status;\n}\n\n/**\n  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled\n  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that\n  *         contains the configuration information for the erasing.\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process Locked */\n  __HAL_LOCK(&pFlash);\n\n  /* Check the parameters */\n  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));\n\n  /* Enable End of FLASH Operation interrupt */\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);\n  \n  /* Enable Error source interrupt */\n  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);\n  \n  /* Clear pending flags (if any) */  \n  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\\\n                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR);  \n  \n  if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)\n  {\n    /*Mass erase to be done*/\n    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;\n    pFlash.Bank = pEraseInit->Banks;\n    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);\n  }\n  else\n  {\n    /* Erase by sector to be done*/\n\n    /* Check the parameters */\n    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));\n\n    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;\n    pFlash.NbSectorsToErase = pEraseInit->NbSectors;\n    pFlash.Sector = pEraseInit->Sector;\n    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;\n\n    /*Erase 1st sector and wait for IT*/\n    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);\n  }\n\n  return status;\n}\n\n/**\n  * @brief   Program option bytes\n  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that\n  *         contains the configuration information for the programming.\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)\n{\n  HAL_StatusTypeDef status = HAL_ERROR;\n  \n  /* Process Locked */\n  __HAL_LOCK(&pFlash);\n\n  /* Check the parameters */\n  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));\n\n  /*Write protection configuration*/\n  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)\n  {\n    assert_param(IS_WRPSTATE(pOBInit->WRPState));\n    if(pOBInit->WRPState == OB_WRPSTATE_ENABLE)\n    {\n      /*Enable of Write protection on the selected Sector*/\n      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);\n    }\n    else\n    {\n      /*Disable of Write protection on the selected Sector*/\n      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);\n    }\n  }\n\n  /*Read protection configuration*/\n  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)\n  {\n    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);\n  }\n\n  /*USER  configuration*/\n  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)\n  {\n    status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, \n                                     pOBInit->USERConfig&OB_STOP_NO_RST,\n                                     pOBInit->USERConfig&OB_STDBY_NO_RST);\n  }\n\n  /*BOR Level  configuration*/\n  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)\n  {\n    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);\n  }\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(&pFlash);\n\n  return status;\n}\n\n/**\n  * @brief   Get the Option byte configuration\n  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that\n  *         contains the configuration information for the programming.\n  * \n  * @retval None\n  */\nvoid HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)\n{\n  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;\n\n  /*Get WRP*/\n  pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();\n\n  /*Get RDP Level*/\n  pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();\n\n  /*Get USER*/\n  pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();\n\n  /*Get BOR Level*/\n  pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();\n}\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\\\n    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief   Program option bytes\n  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that\n  *         contains the configuration information for the programming.\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)\n{\n  HAL_StatusTypeDef status = HAL_ERROR;\n  \n  /* Check the parameters */\n  assert_param(IS_OBEX(pAdvOBInit->OptionType));\n\n  /*Program PCROP option byte*/\n  if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)\n  {\n    /* Check the parameters */\n    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));\n    if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)\n    {\n      /*Enable of Write protection on the selected Sector*/\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\\\n    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);\n#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n    }\n    else\n    {\n      /*Disable of Write protection on the selected Sector*/\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\\\n    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);\n#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n    }\n  }\n   \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n  /*Program BOOT config option byte*/\n  if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)\n  {\n    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);\n  }\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n  return status;\n}\n\n/**\n  * @brief   Get the OBEX byte configuration\n  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that\n  *         contains the configuration information for the programming.\n  * \n  * @retval None\n  */\nvoid HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)\n{\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\\\n    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  /*Get Sector*/\n  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));\n#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */\n  /*Get Sector for Bank1*/\n  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));\n\n  /*Get Sector for Bank2*/\n  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));\n\n  /*Get Boot config OB*/\n  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n}\n\n/**\n  * @brief  Select the Protection Mode \n  * \n  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted \n  *         Global Read Out Protection modification (from level1 to level0) \n  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible \n  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag\n  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/\n  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)\n{\n  uint8_t optiontmp = 0xFF;\n\n  /* Mask SPRMOD bit */\n  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); \n  \n  /* Update Option Byte */\n  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); \n  \n  return HAL_OK;\n}\n\n/**\n  * @brief  Deselect the Protection Mode \n  * \n  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted \n  *         Global Read Out Protection modification (from level1 to level0) \n  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible \n  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag\n  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/\n  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.\n  * \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)\n{\n  uint8_t optiontmp = 0xFF;\n  \n  /* Mask SPRMOD bit */\n  optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); \n  \n  /* Update Option Byte */\n  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);  \n  \n  return HAL_OK;\n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\\\n          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2\n  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.  \n  * @retval The FLASH Write Protection  Option Bytes value\n  */\nuint16_t HAL_FLASHEx_OB_GetBank2WRP(void)\n{                            \n  /* Return the FLASH write protection Register value */\n  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));\n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n/**\n  * @}\n  */\n  \n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Full erase of FLASH memory sectors \n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \n  *          This parameter can be one of the following values:\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \n  *                                  the operation will be done by byte (8-bit) \n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\n  *                                  the operation will be done by half word (16-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\n  *                                  the operation will be done by word (32-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \n  *                                  the operation will be done by double word (64-bit)\n  * \n  * @param  Banks Banks to be erased\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: Bank1 to be erased\n  *            @arg FLASH_BANK_2: Bank2 to be erased\n  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\n  *\n  * @retval HAL Status\n  */\nstatic void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\n{\n  /* Check the parameters */\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\n  assert_param(IS_FLASH_BANK(Banks));\n\n  /* if the previous operation is completed, proceed to erase all sectors */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n\n  if(Banks == FLASH_BANK_BOTH)\n  {\n    /* bank1 & bank2 will be erased*/\n    FLASH->CR |= FLASH_MER_BIT;\n  }\n  else if(Banks == FLASH_BANK_1)\n  {\n    /*Only bank1 will be erased*/\n    FLASH->CR |= FLASH_CR_MER1;\n  }\n  else\n  {\n    /*Only bank2 will be erased*/\n    FLASH->CR |= FLASH_CR_MER2;\n  }\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);\n}\n\n/**\n  * @brief  Erase the specified FLASH memory sector\n  * @param  Sector FLASH sector to erase\n  *         The value of this parameter depend on device used within the same series      \n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \n  *          This parameter can be one of the following values:\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \n  *                                  the operation will be done by byte (8-bit) \n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\n  *                                  the operation will be done by half word (16-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\n  *                                  the operation will be done by word (32-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \n  *                                  the operation will be done by double word (64-bit)\n  * \n  * @retval None\n  */\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\n{\n  uint32_t tmp_psize = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_FLASH_SECTOR(Sector));\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\n  \n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\n  {\n     tmp_psize = FLASH_PSIZE_BYTE;\n  }\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\n  {\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\n  }\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\n  {\n    tmp_psize = FLASH_PSIZE_WORD;\n  }\n  else\n  {\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\n  }\n\n  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */\n  if(Sector > FLASH_SECTOR_11) \n  {\n    Sector += 4U;\n  }\n  /* If the previous operation is completed, proceed to erase the sector */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= tmp_psize;\n  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\n  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\n  FLASH->CR |= FLASH_CR_STRT;\n}\n\n/**\n  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors\n  *\n  * @note   When the memory read protection level is selected (RDP level = 1), \n  *         it is not possible to program or erase the flash sector i if CortexM4  \n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \n  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   \n  * \n  * @param  WRPSector specifies the sector(s) to be write protected.\n  *          This parameter can be one of the following values:\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23\n  *            @arg OB_WRP_SECTOR_All\n  * @note   BANK2 starts from OB_WRP_SECTOR_12\n  *\n  * @param  Banks Enable write protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: WRP on all sectors of bank1\n  *            @arg FLASH_BANK_2: WRP on all sectors of bank2\n  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2\n  *\n  * @retval HAL FLASH State   \n  */\nstatic HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  {\n    if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||\n         (WRPSector < OB_WRP_SECTOR_12))\n    {\n       if(WRPSector == OB_WRP_SECTOR_All)\n       {\n          /*Write protection on all sector of BANK1*/\n          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12));  \n       }\n       else\n       {\n          /*Write protection done on sectors of BANK1*/\n          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  \n       }\n    }\n    else \n    {\n      /*Write protection done on sectors of BANK2*/\n      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));  \n    }\n\n    /*Write protection on all sector of BANK2*/\n    if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))\n    {\n      /* Wait for last operation to be completed */\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n      \n      if(status == HAL_OK)\n      { \n        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12));  \n      }\n    }\n    \n  }\n  return status;\n}\n\n/**\n  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors\n  *\n  * @note   When the memory read protection level is selected (RDP level = 1), \n  *         it is not possible to program or erase the flash sector i if CortexM4  \n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \n  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   \n  * \n  * @param  WRPSector specifies the sector(s) to be write protected.\n  *          This parameter can be one of the following values:\n  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23\n  *            @arg OB_WRP_Sector_All\n  * @note   BANK2 starts from OB_WRP_SECTOR_12\n  *\n  * @param  Banks Disable write protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: Bank1 to be erased\n  *            @arg FLASH_BANK_2: Bank2 to be erased\n  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased\n  *\n  * @retval HAL Status   \n  */\nstatic HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  {\n    if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||\n         (WRPSector < OB_WRP_SECTOR_12))\n    {\n       if(WRPSector == OB_WRP_SECTOR_All)\n       {\n          /*Write protection on all sector of BANK1*/\n          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); \n       }\n       else\n       {\n          /*Write protection done on sectors of BANK1*/\n          *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; \n       }\n    }\n    else \n    {\n      /*Write protection done on sectors of BANK2*/\n      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); \n    }\n\n    /*Write protection on all sector  of BANK2*/\n    if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))\n    {\n      /* Wait for last operation to be completed */\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n      \n      if(status == HAL_OK)\n      { \n        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); \n      }\n    }\n    \n  }\n\n  return status;\n}\n\n/**\n  * @brief  Configure the Dual Bank Boot.\n  *   \n  * @note   This function can be used only for STM32F42xxx/43xxx devices.\n  *      \n  * @param  BootConfig specifies the Dual Bank Boot Option byte.\n  *          This parameter can be one of the following values:\n  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable\n  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled\n  * @retval None\n  */\nstatic HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Check the parameters */\n  assert_param(IS_OB_BOOT(BootConfig));\n\n  /* Wait for last operation to be completed */  \n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    /* Set Dual Bank Boot */\n    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);\n    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Enable the read/write protection (PCROP) of the desired \n  *         sectors of Bank 1 and/or Bank 2.\n  * @note   This function can be used only for STM32F42xxx/43xxx devices.\n  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11\n  *            @arg OB_PCROP_SECTOR__All                         \n  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23\n  *            @arg OB_PCROP_SECTOR__All                         \n  * @param  Banks Enable PCROP protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: WRP on all sectors of bank1\n  *            @arg FLASH_BANK_2: WRP on all sectors of bank2\n  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2\n  *\n  * @retval HAL Status  \n  */\nstatic HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  {\n    if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))\n    {\n      assert_param(IS_OB_PCROP(SectorBank1));\n      /*Write protection done on sectors of BANK1*/\n      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; \n    }\n    else \n    {\n      assert_param(IS_OB_PCROP(SectorBank2));\n      /*Write protection done on sectors of BANK2*/\n      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; \n    }\n\n    /*Write protection on all sector  of BANK2*/\n    if(Banks == FLASH_BANK_BOTH)\n    {\n      assert_param(IS_OB_PCROP(SectorBank2));\n      /* Wait for last operation to be completed */\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n      \n      if(status == HAL_OK)\n      { \n        /*Write protection done on sectors of BANK2*/\n        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; \n      }\n    }\n    \n  }\n\n  return status;\n}\n\n\n/**\n  * @brief  Disable the read/write protection (PCROP) of the desired \n  *         sectors  of Bank 1 and/or Bank 2.\n  * @note   This function can be used only for STM32F42xxx/43xxx devices.\n  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11\n  *            @arg OB_PCROP_SECTOR__All                         \n  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23\n  *            @arg OB_PCROP_SECTOR__All                         \n  * @param  Banks Disable PCROP protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: WRP on all sectors of bank1\n  *            @arg FLASH_BANK_2: WRP on all sectors of bank2\n  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2\n  *\n  * @retval HAL Status  \n  */\nstatic HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)\n{  \n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  {\n    if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))\n    {\n      assert_param(IS_OB_PCROP(SectorBank1));\n      /*Write protection done on sectors of BANK1*/\n      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); \n    }\n    else \n    {\n      /*Write protection done on sectors of BANK2*/\n      assert_param(IS_OB_PCROP(SectorBank2));\n      *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); \n    }\n\n    /*Write protection on all sector  of BANK2*/\n    if(Banks == FLASH_BANK_BOTH)\n    {\n      assert_param(IS_OB_PCROP(SectorBank2));\n     /* Wait for last operation to be completed */\n      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n      \n      if(status == HAL_OK)\n      { \n        /*Write protection done on sectors of BANK2*/\n        *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); \n      }\n    }\n    \n  }\n  \n  return status;\n\n}\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\\\n    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\\\n    defined(STM32F423xx)\n/**\n  * @brief  Mass erase of FLASH memory\n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \n  *          This parameter can be one of the following values:\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \n  *                                  the operation will be done by byte (8-bit) \n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\n  *                                  the operation will be done by half word (16-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\n  *                                  the operation will be done by word (32-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \n  *                                  the operation will be done by double word (64-bit)\n  * \n  * @param  Banks Banks to be erased\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: Bank1 to be erased\n  *\n  * @retval None\n  */\nstatic void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)\n{\n  /* Check the parameters */\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\n  assert_param(IS_FLASH_BANK(Banks));\n  \n  /* If the previous operation is completed, proceed to erase all sectors */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= FLASH_CR_MER;\n  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U);\n}\n\n/**\n  * @brief  Erase the specified FLASH memory sector\n  * @param  Sector FLASH sector to erase\n  *         The value of this parameter depend on device used within the same series      \n  * @param  VoltageRange The device voltage range which defines the erase parallelism.  \n  *          This parameter can be one of the following values:\n  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, \n  *                                  the operation will be done by byte (8-bit) \n  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,\n  *                                  the operation will be done by half word (16-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,\n  *                                  the operation will be done by word (32-bit)\n  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, \n  *                                  the operation will be done by double word (64-bit)\n  * \n  * @retval None\n  */\nvoid FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)\n{\n  uint32_t tmp_psize = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_FLASH_SECTOR(Sector));\n  assert_param(IS_VOLTAGERANGE(VoltageRange));\n  \n  if(VoltageRange == FLASH_VOLTAGE_RANGE_1)\n  {\n     tmp_psize = FLASH_PSIZE_BYTE;\n  }\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)\n  {\n    tmp_psize = FLASH_PSIZE_HALF_WORD;\n  }\n  else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)\n  {\n    tmp_psize = FLASH_PSIZE_WORD;\n  }\n  else\n  {\n    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;\n  }\n\n  /* If the previous operation is completed, proceed to erase the sector */\n  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);\n  FLASH->CR |= tmp_psize;\n  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);\n  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);\n  FLASH->CR |= FLASH_CR_STRT;\n}\n\n/**\n  * @brief  Enable the write protection of the desired bank 1 sectors\n  *\n  * @note   When the memory read protection level is selected (RDP level = 1), \n  *         it is not possible to program or erase the flash sector i if CortexM4  \n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \n  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   \n  * \n  * @param  WRPSector specifies the sector(s) to be write protected.\n  *         The value of this parameter depend on device used within the same series \n  * \n  * @param  Banks Enable write protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: WRP on all sectors of bank1\n  *\n  * @retval HAL Status \n  */\nstatic HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector);  \n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Disable the write protection of the desired bank 1 sectors\n  *\n  * @note   When the memory read protection level is selected (RDP level = 1), \n  *         it is not possible to program or erase the flash sector i if CortexM4  \n  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1 \n  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).   \n  * \n  * @param  WRPSector specifies the sector(s) to be write protected.\n  *         The value of this parameter depend on device used within the same series \n  * \n  * @param  Banks Enable write protection on all the sectors for the specific bank\n  *          This parameter can be one of the following values:\n  *            @arg FLASH_BANK_1: WRP on all sectors of bank1\n  *\n  * @retval HAL Status \n  */\nstatic HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_WRP_SECTOR(WRPSector));\n  assert_param(IS_FLASH_BANK(Banks));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; \n  }\n  \n  return status;\n}\n#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx\n          STM32F413xx || STM32F423xx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\\\n    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\\\n    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Enable the read/write protection (PCROP) of the desired sectors.\n  * @note   This function can be used only for STM32F401xx devices.\n  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5\n  *            @arg OB_PCROP_Sector_All                         \n  * @retval HAL Status  \n  */\nstatic HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_PCROP(Sector));\n    \n  /* Wait for last operation to be completed */  \n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;\n  }\n  \n  return status;\n}\n\n\n/**\n  * @brief  Disable the read/write protection (PCROP) of the desired sectors.\n  * @note   This function can be used only for STM32F401xx devices.\n  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.\n  *          This parameter can be one of the following values:\n  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5\n  *            @arg OB_PCROP_Sector_All                         \n  * @retval HAL Status  \n  */\nstatic HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)\n{  \n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_PCROP(Sector));\n    \n  /* Wait for last operation to be completed */  \n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector);\n  }\n  \n  return status;\n\n}\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx\n          STM32F413xx || STM32F423xx */\n\n/**\n  * @brief  Set the read protection level.\n  * @param  Level specifies the read protection level.\n  *          This parameter can be one of the following values:\n  *            @arg OB_RDP_LEVEL_0: No protection\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\n  *   \n  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0\n  *    \n  * @retval HAL Status\n  */\nstatic HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n  \n  /* Check the parameters */\n  assert_param(IS_OB_RDP_LEVEL(Level));\n    \n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n\n  if(status == HAL_OK)\n  { \n    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    \n  * @param  Iwdg Selects the IWDG mode\n  *          This parameter can be one of the following values:\n  *            @arg OB_IWDG_SW: Software IWDG selected\n  *            @arg OB_IWDG_HW: Hardware IWDG selected\n  * @param  Stop Reset event when entering STOP mode.\n  *          This parameter  can be one of the following values:\n  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP\n  *            @arg OB_STOP_RST: Reset generated when entering in STOP\n  * @param  Stdby Reset event when entering Standby mode.\n  *          This parameter  can be one of the following values:\n  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY\n  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY\n  * @retval HAL Status\n  */\nstatic HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)\n{\n  uint8_t optiontmp = 0xFF;\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Check the parameters */\n  assert_param(IS_OB_IWDG_SOURCE(Iwdg));\n  assert_param(IS_OB_STOP_SOURCE(Stop));\n  assert_param(IS_OB_STDBY_SOURCE(Stdby));\n\n  /* Wait for last operation to be completed */\n  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);\n  \n  if(status == HAL_OK)\n  {     \n    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */\n    optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);\n\n    /* Update User Option Byte */\n    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); \n  }\n  \n  return status; \n}\n\n/**\n  * @brief  Set the BOR Level. \n  * @param  Level specifies the Option Bytes BOR Reset Level.\n  *          This parameter can be one of the following values:\n  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\n  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\n  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\n  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V\n  * @retval HAL Status\n  */\nstatic HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)\n{\n  /* Check the parameters */\n  assert_param(IS_OB_BOR_LEVEL(Level));\n\n  /* Set the BOR Level */\n  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);\n  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;\n  \n  return HAL_OK;\n  \n}\n\n/**\n  * @brief  Return the FLASH User Option Byte value.\n  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)\n  *         and RST_STDBY(Bit2).\n  */\nstatic uint8_t FLASH_OB_GetUser(void)\n{\n  /* Return the User Option Byte */\n  return ((uint8_t)(FLASH->OPTCR & 0xE0));\n}\n\n/**\n  * @brief  Return the FLASH Write Protection Option Bytes value.\n  * @retval uint16_t FLASH Write Protection Option Bytes value\n  */\nstatic uint16_t FLASH_OB_GetWRP(void)\n{\n  /* Return the FLASH write protection Register value */\n  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));\n}\n\n/**\n  * @brief  Returns the FLASH Read Protection level.\n  * @retval FLASH ReadOut Protection Status:\n  *         This parameter can be one of the following values:\n  *            @arg OB_RDP_LEVEL_0: No protection\n  *            @arg OB_RDP_LEVEL_1: Read protection of the memory\n  *            @arg OB_RDP_LEVEL_2: Full chip protection\n  */\nstatic uint8_t FLASH_OB_GetRDP(void)\n{\n  uint8_t readstatus = OB_RDP_LEVEL_0;\n\n  if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2))\n  {\n    readstatus = OB_RDP_LEVEL_2;\n  }\n  else if((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0))\n  {\n    readstatus = OB_RDP_LEVEL_0;\n  }\n  else \n  {\n    readstatus = OB_RDP_LEVEL_1;\n  }\n\n  return readstatus;\n}\n\n/**\n  * @brief  Returns the FLASH BOR level.\n  * @retval uint8_t The FLASH BOR level:\n  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V\n  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V\n  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V\n  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  \n  */\nstatic uint8_t FLASH_OB_GetBOR(void)\n{\n  /* Return the FLASH BOR level */\n  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);\n}\n\n/**\n  * @brief  Flush the instruction and data caches\n  * @retval None\n  */\nvoid FLASH_FlushCaches(void)\n{\n  /* Flush instruction cache  */\n  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET)\n  {\n    /* Disable instruction cache  */\n    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();\n    /* Reset instruction cache */\n    __HAL_FLASH_INSTRUCTION_CACHE_RESET();\n    /* Enable instruction cache */\n    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();\n  }\n  \n  /* Flush data cache */\n  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)\n  {\n    /* Disable data cache  */\n    __HAL_FLASH_DATA_CACHE_DISABLE();\n    /* Reset data cache */\n    __HAL_FLASH_DATA_CACHE_RESET();\n    /* Enable data cache */\n    __HAL_FLASH_DATA_CACHE_ENABLE();\n  }\n}\n\n/**\n  * @}\n  */\n  \n#endif /* HAL_FLASH_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_flash_ramfunc.c\n  * @author  MCD Application Team\n  * @brief   FLASH RAMFUNC module driver.\n  *          This file provides a FLASH firmware functions which should be \n  *          executed from internal SRAM\n  *            + Stop/Start the flash interface while System Run\n  *            + Enable/Disable the flash sleep while System Run\n  @verbatim\n  ==============================================================================\n                    ##### APIs executed from Internal RAM #####\n  ==============================================================================\n  [..]\n    *** ARM Compiler ***\n    --------------------\n    [..] RAM functions are defined using the toolchain options. \n         Functions that are be executed in RAM should reside in a separate\n         source module. Using the 'Options for File' dialog you can simply change\n         the 'Code / Const' area of a module to a memory space in physical RAM.\n         Available memory areas are declared in the 'Target' tab of the \n         Options for Target' dialog.\n\n    *** ICCARM Compiler ***\n    -----------------------\n    [..] RAM functions are defined using a specific toolchain keyword \"__ramfunc\".\n\n    *** GNU Compiler ***\n    --------------------\n    [..] RAM functions are defined using a specific toolchain attribute\n         \"__attribute__((section(\".RamFunc\")))\".\n  \n  @endverbatim         \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC\n  * @brief FLASH functions executed from RAM\n  * @{\n  */\n#ifdef HAL_FLASH_MODULE_ENABLED\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \\\n    defined(STM32F412Rx) || defined(STM32F412Cx)\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions\n  * @{\n  */\n\n/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM \n  *  @brief Peripheral Extended features functions \n  *\n@verbatim   \n\n ===============================================================================\n                      ##### ramfunc functions #####\n ===============================================================================  \n    [..]\n    This subsection provides a set of functions that should be executed from RAM \n    transfers.\n    \n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief Stop the flash interface while System Run\n  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. \n  * @note  This mode couldn't be set while executing with the flash itself. \n  *        It should be done with specific routine executed from RAM.     \n  * @retval HAL status\n  */\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)\n{\n  /* Enable Power ctrl clock */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  /* Stop the flash interface while System Run */  \n  SET_BIT(PWR->CR, PWR_CR_FISSR);\n   \n  return HAL_OK;\n}\n\n/**\n  * @brief Start the flash interface while System Run\n  * @note  This mode is only available for STM32F411xx/STM32F446xx devices. \n  * @note  This mode couldn't be set while executing with the flash itself. \n  *        It should be done with specific routine executed from RAM.     \n  * @retval HAL status\n  */\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)\n{\n  /* Enable Power ctrl clock */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  /* Start the flash interface while System Run */\n  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Enable the flash sleep while System Run\n  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. \n  * @note  This mode could n't be set while executing with the flash itself. \n  *        It should be done with specific routine executed from RAM.     \n  * @retval HAL status\n  */\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)\n{\n  /* Enable Power ctrl clock */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  /* Enable the flash sleep while System Run */\n  SET_BIT(PWR->CR, PWR_CR_FMSSR);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Disable the flash sleep while System Run\n  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. \n  * @note  This mode couldn't be set while executing with the flash itself. \n  *        It should be done with specific routine executed from RAM.     \n  * @retval HAL status\n  */\n__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)\n{\n  /* Enable Power ctrl clock */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  /* Disable the flash sleep while System Run */\n  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);\n  \n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n#endif /* HAL_FLASH_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_gpio.c\n  * @author  MCD Application Team\n  * @brief   GPIO HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *\n  @verbatim\n  ==============================================================================\n                    ##### GPIO Peripheral features #####\n  ==============================================================================\n  [..] \n  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each\n  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software\n  in several modes:\n  (+) Input mode \n  (+) Analog mode\n  (+) Output mode\n  (+) Alternate function mode\n  (+) External interrupt/event lines\n\n  [..]  \n  During and just after reset, the alternate functions and external interrupt  \n  lines are not active and the I/O ports are configured in input floating mode.\n  \n  [..]   \n  All GPIO pins have weak internal pull-up and pull-down resistors, which can be \n  activated or not.\n\n  [..]\n  In Output or Alternate mode, each IO can be configured on open-drain or push-pull\n  type and the IO speed can be selected depending on the VDD value.\n\n  [..]  \n  All ports have external interrupt/event capability. To use external interrupt \n  lines, the port must be configured in input mode. All available GPIO pins are \n  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.\n  \n  [..]\n  The external interrupt/event controller consists of up to 23 edge detectors \n  (16 lines are connected to GPIO) for generating event/interrupt requests (each \n  input line can be independently configured to select the type (interrupt or event) \n  and the corresponding trigger event (rising or falling or both). Each line can \n  also be masked independently. \n\n                     ##### How to use this driver #####\n  ==============================================================================  \n  [..]\n    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). \n\n    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().\n        (++) Configure the IO mode using \"Mode\" member from GPIO_InitTypeDef structure\n        (++) Activate Pull-up, Pull-down resistor using \"Pull\" member from GPIO_InitTypeDef \n             structure.\n        (++) In case of Output or alternate function mode selection: the speed is \n             configured through \"Speed\" member from GPIO_InitTypeDef structure.\n        (++) In alternate mode is selection, the alternate function connected to the IO\n             is configured through \"Alternate\" member from GPIO_InitTypeDef structure.\n        (++) Analog mode is required when a pin is to be used as ADC channel \n             or DAC output.\n        (++) In case of external interrupt/event selection the \"Mode\" member from \n             GPIO_InitTypeDef structure select the type (interrupt or event) and \n             the corresponding trigger event (rising or falling or both).\n\n    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority \n        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using\n        HAL_NVIC_EnableIRQ().\n         \n    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().\n            \n    (#) To set/reset the level of a pin configured in output mode use \n        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().\n    \n    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().\n\n                 \n    (#) During and just after reset, the alternate functions are not \n        active and the GPIO pins are configured in input floating mode (except JTAG\n        pins).\n  \n    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose \n        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has \n        priority over the GPIO function.\n  \n    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as \n        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. \n        The HSE has priority over the GPIO function.\n  \n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup GPIO GPIO\n  * @brief GPIO HAL module driver\n  * @{\n  */\n\n#ifdef HAL_GPIO_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup GPIO_Private_Constants GPIO Private Constants\n  * @{\n  */\n\n#define GPIO_NUMBER           16U\n/**\n  * @}\n  */\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup GPIO_Exported_Functions GPIO Exported Functions\n  * @{\n  */\n\n/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions\n  *  @brief    Initialization and Configuration functions\n  *\n@verbatim    \n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n  [..]\n    This section provides functions allowing to initialize and de-initialize the GPIOs\n    to be ready for use.\n \n@endverbatim\n  * @{\n  */\n\n\n/**\n  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or\n  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains\n  *         the configuration information for the specified GPIO peripheral.\n  * @retval None\n  */\nvoid HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)\n{\n  uint32_t position;\n  uint32_t ioposition = 0x00U;\n  uint32_t iocurrent = 0x00U;\n  uint32_t temp = 0x00U;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));\n  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));\n  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));\n\n  /* Configure the port pins */\n  for(position = 0U; position < GPIO_NUMBER; position++)\n  {\n    /* Get the IO position */\n    ioposition = 0x01U << position;\n    /* Get the current IO position */\n    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;\n\n    if(iocurrent == ioposition)\n    {\n      /*--------------------- GPIO Mode Configuration ------------------------*/\n      /* In case of Output or Alternate function mode selection */\n      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \\\n          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)\n      {\n        /* Check the Speed parameter */\n        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));\n        /* Configure the IO Speed */\n        temp = GPIOx->OSPEEDR; \n        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));\n        temp |= (GPIO_Init->Speed << (position * 2U));\n        GPIOx->OSPEEDR = temp;\n\n        /* Configure the IO Output Type */\n        temp = GPIOx->OTYPER;\n        temp &= ~(GPIO_OTYPER_OT_0 << position) ;\n        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);\n        GPIOx->OTYPER = temp;\n       }\n\n      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)\n      {\n        /* Activate the Pull-up or Pull down resistor for the current IO */\n        temp = GPIOx->PUPDR;\n        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));\n        temp |= ((GPIO_Init->Pull) << (position * 2U));\n        GPIOx->PUPDR = temp;\n      }\n\n      /* In case of Alternate function mode selection */\n      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)\n      {\n        /* Check the Alternate function parameter */\n        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));\n        /* Configure Alternate function mapped with the current IO */\n        temp = GPIOx->AFR[position >> 3U];\n        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;\n        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));\n        GPIOx->AFR[position >> 3U] = temp;\n      }\n\n      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */\n      temp = GPIOx->MODER;\n      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));\n      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));\n      GPIOx->MODER = temp;\n\n      /*--------------------- EXTI Mode Configuration ------------------------*/\n      /* Configure the External Interrupt or event for the current IO */\n      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)\n      {\n        /* Enable SYSCFG Clock */\n        __HAL_RCC_SYSCFG_CLK_ENABLE();\n\n        temp = SYSCFG->EXTICR[position >> 2U];\n        temp &= ~(0x0FU << (4U * (position & 0x03U)));\n        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));\n        SYSCFG->EXTICR[position >> 2U] = temp;\n\n        /* Clear EXTI line configuration */\n        temp = EXTI->IMR;\n        temp &= ~((uint32_t)iocurrent);\n        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)\n        {\n          temp |= iocurrent;\n        }\n        EXTI->IMR = temp;\n\n        temp = EXTI->EMR;\n        temp &= ~((uint32_t)iocurrent);\n        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)\n        {\n          temp |= iocurrent;\n        }\n        EXTI->EMR = temp;\n\n        /* Clear Rising Falling edge configuration */\n        temp = EXTI->RTSR;\n        temp &= ~((uint32_t)iocurrent);\n        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)\n        {\n          temp |= iocurrent;\n        }\n        EXTI->RTSR = temp;\n\n        temp = EXTI->FTSR;\n        temp &= ~((uint32_t)iocurrent);\n        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)\n        {\n          temp |= iocurrent;\n        }\n        EXTI->FTSR = temp;\n      }\n    }\n  }\n}\n\n/**\n  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or\n  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n  * @param  GPIO_Pin specifies the port bit to be written.\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\n  * @retval None\n  */\nvoid HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)\n{\n  uint32_t position;\n  uint32_t ioposition = 0x00U;\n  uint32_t iocurrent = 0x00U;\n  uint32_t tmp = 0x00U;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));\n  \n  /* Configure the port pins */\n  for(position = 0U; position < GPIO_NUMBER; position++)\n  {\n    /* Get the IO position */\n    ioposition = 0x01U << position;\n    /* Get the current IO position */\n    iocurrent = (GPIO_Pin) & ioposition;\n\n    if(iocurrent == ioposition)\n    {\n      /*------------------------- EXTI Mode Configuration --------------------*/\n      tmp = SYSCFG->EXTICR[position >> 2U];\n      tmp &= (0x0FU << (4U * (position & 0x03U)));\n      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))\n      {\n        /* Clear EXTI line configuration */\n        EXTI->IMR &= ~((uint32_t)iocurrent);\n        EXTI->EMR &= ~((uint32_t)iocurrent);\n        \n        /* Clear Rising Falling edge configuration */\n        EXTI->RTSR &= ~((uint32_t)iocurrent);\n        EXTI->FTSR &= ~((uint32_t)iocurrent);\n\n        /* Configure the External Interrupt or event for the current IO */\n        tmp = 0x0FU << (4U * (position & 0x03U));\n        SYSCFG->EXTICR[position >> 2U] &= ~tmp;\n      }\n\n      /*------------------------- GPIO Mode Configuration --------------------*/\n      /* Configure IO Direction in Input Floating Mode */\n      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));\n\n      /* Configure the default Alternate Function in current IO */\n      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;\n\n      /* Deactivate the Pull-up and Pull-down resistor for the current IO */\n      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));\n\n      /* Configure the default value IO Output Type */\n      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;\n\n      /* Configure the default value for IO Speed */\n      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));\n    }\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions \n  *  @brief   GPIO Read and Write\n  *\n@verbatim\n ===============================================================================\n                       ##### IO operation functions #####\n ===============================================================================\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Reads the specified input port pin.\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or\n  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n  * @param  GPIO_Pin specifies the port bit to read.\n  *         This parameter can be GPIO_PIN_x where x can be (0..15).\n  * @retval The input port pin value.\n  */\nGPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\n{\n  GPIO_PinState bitstatus;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\n\n  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)\n  {\n    bitstatus = GPIO_PIN_SET;\n  }\n  else\n  {\n    bitstatus = GPIO_PIN_RESET;\n  }\n  return bitstatus;\n}\n\n/**\n  * @brief  Sets or clears the selected data port bit.\n  *\n  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify\n  *         accesses. In this way, there is no risk of an IRQ occurring between\n  *         the read and the modify access.\n  *\n  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or\n  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n  * @param  GPIO_Pin specifies the port bit to be written.\n  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).\n  * @param  PinState specifies the value to be written to the selected bit.\n  *          This parameter can be one of the GPIO_PinState enum values:\n  *            @arg GPIO_PIN_RESET: to clear the port pin\n  *            @arg GPIO_PIN_SET: to set the port pin\n  * @retval None\n  */\nvoid HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)\n{\n  /* Check the parameters */\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\n  assert_param(IS_GPIO_PIN_ACTION(PinState));\n\n  if(PinState != GPIO_PIN_RESET)\n  {\n    GPIOx->BSRR = GPIO_Pin;\n  }\n  else\n  {\n    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;\n  }\n}\n\n/**\n  * @brief  Toggles the specified GPIO pins.\n  * @param  GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or\n  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.\n  * @param  GPIO_Pin Specifies the pins to be toggled.\n  * @retval None\n  */\nvoid HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\n{\n  uint32_t odr;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\n\n  /* get current Ouput Data Register value */\n  odr = GPIOx->ODR;\n\n  /* Set selected pins that were at low level, and reset ones that were high */\n  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);\n}\n\n/**\n  * @brief  Locks GPIO Pins configuration registers.\n  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,\n  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.\n  * @note   The configuration of the locked GPIO pins can no longer be modified\n  *         until the next reset.\n  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family\n  * @param  GPIO_Pin specifies the port bit to be locked.\n  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)\n{\n  __IO uint32_t tmp = GPIO_LCKR_LCKK;\n\n  /* Check the parameters */\n  assert_param(IS_GPIO_PIN(GPIO_Pin));\n\n  /* Apply lock key write sequence */\n  tmp |= GPIO_Pin;\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\n  GPIOx->LCKR = tmp;\n  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */\n  GPIOx->LCKR = GPIO_Pin;\n  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */\n  GPIOx->LCKR = tmp;\n  /* Read LCKR register. This read is mandatory to complete key lock sequence */\n  tmp = GPIOx->LCKR;\n\n  /* Read again in order to confirm lock is active */\n if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)\n  {\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  This function handles EXTI interrupt request.\n  * @param  GPIO_Pin Specifies the pins connected EXTI line\n  * @retval None\n  */\nvoid HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)\n{\n  /* EXTI line interrupt detected */\n  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)\n  {\n    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);\n    HAL_GPIO_EXTI_Callback(GPIO_Pin);\n  }\n}\n\n/**\n  * @brief  EXTI line detection callbacks.\n  * @param  GPIO_Pin Specifies the pins connected EXTI line\n  * @retval None\n  */\n__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(GPIO_Pin);\n  /* NOTE: This function Should not be modified, when the callback is needed,\n           the HAL_GPIO_EXTI_Callback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n\n/**\n  * @}\n  */\n\n#endif /* HAL_GPIO_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_i2c.c\n  * @author  MCD Application Team\n  * @brief   I2C HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral State, Mode and Error functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n  [..]\n    The I2C HAL driver can be used as follows:\n\n    (#) Declare a I2C_HandleTypeDef handle structure, for example:\n        I2C_HandleTypeDef  hi2c;\n\n    (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:\n        (##) Enable the I2Cx interface clock\n        (##) I2C pins configuration\n            (+++) Enable the clock for the I2C GPIOs\n            (+++) Configure I2C pins as alternate function open-drain\n        (##) NVIC configuration if you need to use interrupt process\n            (+++) Configure the I2Cx interrupt priority\n            (+++) Enable the NVIC I2C IRQ Channel\n        (##) DMA Configuration if you need to use DMA process\n            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream\n            (+++) Enable the DMAx interface clock using\n            (+++) Configure the DMA handle parameters\n            (+++) Configure the DMA Tx or Rx stream\n            (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle\n            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on\n                  the DMA Tx or Rx stream\n\n    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,\n        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.\n\n    (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware\n        (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API.\n\n    (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()\n\n    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :\n\n    *** Polling mode IO operation ***\n    =================================\n    [..]\n      (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()\n      (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()\n      (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()\n      (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()\n\n    *** Polling mode IO MEM operation ***\n    =====================================\n    [..]\n      (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()\n      (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()\n\n\n    *** Interrupt mode IO operation ***\n    ===================================\n    [..]\n      (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()\n      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\n      (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()\n      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\n      (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()\n      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\n      (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()\n      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\n      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\n      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\n      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\n\n    *** Interrupt mode or DMA mode IO sequential operation ***\n    ==========================================================\n    [..]\n      (@) These interfaces allow to manage a sequential transfer with a repeated start condition\n          when a direction change during transfer\n    [..]\n      (+) A specific option field manage the different steps of a sequential transfer\n      (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below:\n      (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode\n      (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address\n                            and data to transfer without a final stop condition\n      (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address\n                            and data to transfer without a final stop condition, an then permit a call the same master sequential interface\n                            several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()\n                            or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())\n      (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address\n                            and with new data to transfer if the direction change or manage only the new data to transfer\n                            if no direction change and without a final stop condition in both cases\n      (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address\n                            and with new data to transfer if the direction change or manage only the new data to transfer\n                            if no direction change and with a final stop condition in both cases\n      (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential\n                            interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).\n                            Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\n                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\n                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)\n                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).\n                            Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit\n                              without stopping the communication and so generate a restart condition.\n      (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential\n                            interface.\n                            Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\n                              or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\n                              or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)\n                              or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).\n                            Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.\n\n      (+) Different sequential I2C interfaces are listed below:\n      (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()\n            or using @ref HAL_I2C_Master_Seq_Transmit_DMA()\n      (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\n      (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()\n            or using @ref HAL_I2C_Master_Seq_Receive_DMA()\n      (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\n      (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\n      (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\n      (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()\n      (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can\n           add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).\n      (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()\n      (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()\n            or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()\n      (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\n      (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()\n            or using @ref HAL_I2C_Slave_Seq_Receive_DMA()\n      (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\n      (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\n\n    *** Interrupt mode IO MEM operation ***\n    =======================================\n    [..]\n      (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using\n          @ref HAL_I2C_Mem_Write_IT()\n      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\n      (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using\n          @ref HAL_I2C_Mem_Read_IT()\n      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\n      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\n\n    *** DMA mode IO operation ***\n    ==============================\n    [..]\n      (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using\n          @ref HAL_I2C_Master_Transmit_DMA()\n      (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()\n      (+) Receive in master mode an amount of data in non-blocking mode (DMA) using\n          @ref HAL_I2C_Master_Receive_DMA()\n      (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()\n      (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using\n          @ref HAL_I2C_Slave_Transmit_DMA()\n      (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()\n      (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using\n          @ref HAL_I2C_Slave_Receive_DMA()\n      (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()\n      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\n      (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()\n      (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()\n\n    *** DMA mode IO MEM operation ***\n    =================================\n    [..]\n      (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using\n          @ref HAL_I2C_Mem_Write_DMA()\n      (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()\n      (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using\n          @ref HAL_I2C_Mem_Read_DMA()\n      (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()\n      (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can\n           add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()\n\n\n     *** I2C HAL driver macros list ***\n     ==================================\n     [..]\n       Below the list of most used macros in I2C HAL driver.\n\n      (+) @ref __HAL_I2C_ENABLE:     Enable the I2C peripheral\n      (+) @ref __HAL_I2C_DISABLE:    Disable the I2C peripheral\n      (+) @ref __HAL_I2C_GET_FLAG:   Checks whether the specified I2C flag is set or not\n      (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag\n      (+) @ref __HAL_I2C_ENABLE_IT:  Enable the specified I2C interrupt\n      (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt\n\n     *** Callback registration ***\n     =============================================\n    [..]\n     The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1\n     allows the user to configure dynamically the driver callbacks.\n     Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()\n     to register an interrupt callback.\n    [..]\n     Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:\n       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\n       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\n       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\n       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\n       (+) ListenCpltCallback   : callback for end of listen mode.\n       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\n       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\n       (+) ErrorCallback        : callback for error detection.\n       (+) AbortCpltCallback    : callback for abort completion process.\n       (+) MspInitCallback      : callback for Msp Init.\n       (+) MspDeInitCallback    : callback for Msp DeInit.\n     This function takes as parameters the HAL peripheral handle, the Callback ID\n     and a pointer to the user callback function.\n    [..]\n     For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().\n    [..]\n     Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default\n     weak function.\n     @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,\n     and the Callback ID.\n     This function allows to reset following callbacks:\n       (+) MasterTxCpltCallback : callback for Master transmission end of transfer.\n       (+) MasterRxCpltCallback : callback for Master reception end of transfer.\n       (+) SlaveTxCpltCallback  : callback for Slave transmission end of transfer.\n       (+) SlaveRxCpltCallback  : callback for Slave reception end of transfer.\n       (+) ListenCpltCallback   : callback for end of listen mode.\n       (+) MemTxCpltCallback    : callback for Memory transmission end of transfer.\n       (+) MemRxCpltCallback    : callback for Memory reception end of transfer.\n       (+) ErrorCallback        : callback for error detection.\n       (+) AbortCpltCallback    : callback for abort completion process.\n       (+) MspInitCallback      : callback for Msp Init.\n       (+) MspDeInitCallback    : callback for Msp DeInit.\n    [..]\n     For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().\n    [..]\n     By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET\n     all callbacks are set to the corresponding weak functions:\n     examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().\n     Exception done for MspInit and MspDeInit functions that are\n     reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when\n     these callbacks are null (not registered beforehand).\n     If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()\n     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\n    [..]\n     Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.\n     Exception done MspInit/MspDeInit functions that can be registered/unregistered\n     in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,\n     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\n     Then, the user first registers the MspInit/MspDeInit user callbacks\n     using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()\n     or @ref HAL_I2C_Init() function.\n    [..]\n     When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or\n     not defined, the callback registration feature is not available and all callbacks\n     are set to the corresponding weak functions.\n\n\n\n     [..]\n       (@) You can refer to the I2C HAL driver header file for more useful macros\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup I2C I2C\n  * @brief I2C HAL module driver\n  * @{\n  */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup I2C_Private_Define\n  * @{\n  */\n#define I2C_TIMEOUT_FLAG          35U         /*!< Timeout 35 ms             */\n#define I2C_TIMEOUT_BUSY_FLAG     25U         /*!< Timeout 25 ms             */\n#define I2C_TIMEOUT_STOP_FLAG     5U          /*!< Timeout 5 ms              */\n#define I2C_NO_OPTION_FRAME       0xFFFF0000U /*!< XferOptions default value */\n\n/* Private define for @ref PreviousState usage */\n#define I2C_STATE_MSK             ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits            */\n#define I2C_STATE_NONE            ((uint32_t)(HAL_I2C_MODE_NONE))                                                        /*!< Default Value                                          */\n#define I2C_STATE_MASTER_BUSY_TX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy TX, combinaison of State LSB and Mode enum */\n#define I2C_STATE_MASTER_BUSY_RX  ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER))            /*!< Master Busy RX, combinaison of State LSB and Mode enum */\n#define I2C_STATE_SLAVE_BUSY_TX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy TX, combinaison of State LSB and Mode enum  */\n#define I2C_STATE_SLAVE_BUSY_RX   ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE))             /*!< Slave Busy RX, combinaison of State LSB and Mode enum  */\n\n/**\n  * @}\n  */\n\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n\n/** @defgroup I2C_Private_Functions I2C Private Functions\n  * @{\n  */\n/* Private functions to handle DMA transfer */\nstatic void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma);\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma);\n\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c);\n\nstatic HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);\n\n/* Private functions to handle flags during polling transfer */\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c);\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);\n\n/* Private functions for I2C transfer IRQ handler */\nstatic void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);\nstatic void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);\nstatic void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);\nstatic void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);\nstatic void I2C_Master_SB(I2C_HandleTypeDef *hi2c);\nstatic void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);\nstatic void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);\n\nstatic void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);\nstatic void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);\nstatic void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);\nstatic void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);\nstatic void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags);\nstatic void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);\nstatic void I2C_Slave_AF(I2C_HandleTypeDef *hi2c);\n\nstatic void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c);\n\n/* Private function to Convert Specific options */\nstatic void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup I2C_Exported_Functions I2C Exported Functions\n  * @{\n  */\n\n/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions\n *\n@verbatim\n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This subsection provides a set of functions allowing to initialize and\n          deinitialize the I2Cx peripheral:\n\n      (+) User must Implement HAL_I2C_MspInit() function in which he configures\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).\n\n      (+) Call the function HAL_I2C_Init() to configure the selected device with\n          the selected configuration:\n        (++) Communication Speed\n        (++) Duty cycle\n        (++) Addressing mode\n        (++) Own Address 1\n        (++) Dual Addressing mode\n        (++) Own Address 2\n        (++) General call mode\n        (++) Nostretch mode\n\n      (+) Call the function HAL_I2C_DeInit() to restore the default configuration\n          of the selected I2Cx peripheral.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the I2C according to the specified parameters\n  *         in the I2C_InitTypeDef and initialize the associated handle.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)\n{\n  uint32_t freqrange;\n  uint32_t pclk1;\n\n  /* Check the I2C handle allocation */\n  if (hi2c == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\n  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));\n  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));\n  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));\n  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));\n  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));\n  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));\n  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));\n  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));\n\n  if (hi2c->State == HAL_I2C_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    hi2c->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    /* Init the I2C Callback settings */\n    hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\n    hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\n    hi2c->SlaveTxCpltCallback  = HAL_I2C_SlaveTxCpltCallback;  /* Legacy weak SlaveTxCpltCallback  */\n    hi2c->SlaveRxCpltCallback  = HAL_I2C_SlaveRxCpltCallback;  /* Legacy weak SlaveRxCpltCallback  */\n    hi2c->ListenCpltCallback   = HAL_I2C_ListenCpltCallback;   /* Legacy weak ListenCpltCallback   */\n    hi2c->MemTxCpltCallback    = HAL_I2C_MemTxCpltCallback;    /* Legacy weak MemTxCpltCallback    */\n    hi2c->MemRxCpltCallback    = HAL_I2C_MemRxCpltCallback;    /* Legacy weak MemRxCpltCallback    */\n    hi2c->ErrorCallback        = HAL_I2C_ErrorCallback;        /* Legacy weak ErrorCallback        */\n    hi2c->AbortCpltCallback    = HAL_I2C_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\n    hi2c->AddrCallback         = HAL_I2C_AddrCallback;         /* Legacy weak AddrCallback         */\n\n    if (hi2c->MspInitCallback == NULL)\n    {\n      hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit  */\n    }\n\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    hi2c->MspInitCallback(hi2c);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    HAL_I2C_MspInit(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n\n  hi2c->State = HAL_I2C_STATE_BUSY;\n\n  /* Disable the selected I2C peripheral */\n  __HAL_I2C_DISABLE(hi2c);\n\n  /*Reset I2C*/\n  hi2c->Instance->CR1 |= I2C_CR1_SWRST;\n  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;\n\n  /* Get PCLK1 frequency */\n  pclk1 = HAL_RCC_GetPCLK1Freq();\n\n  /* Check the minimum allowed PCLK1 frequency */\n  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Calculate frequency range */\n  freqrange = I2C_FREQRANGE(pclk1);\n\n  /*---------------------------- I2Cx CR2 Configuration ----------------------*/\n  /* Configure I2Cx: Frequency range */\n  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);\n\n  /*---------------------------- I2Cx TRISE Configuration --------------------*/\n  /* Configure I2Cx: Rise Time */\n  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));\n\n  /*---------------------------- I2Cx CCR Configuration ----------------------*/\n  /* Configure I2Cx: Speed */\n  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));\n\n  /*---------------------------- I2Cx CR1 Configuration ----------------------*/\n  /* Configure I2Cx: Generalcall and NoStretch mode */\n  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));\n\n  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/\n  /* Configure I2Cx: Own Address1 and addressing mode */\n  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));\n\n  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/\n  /* Configure I2Cx: Dual mode and Own Address2 */\n  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));\n\n  /* Enable the selected I2C peripheral */\n  __HAL_I2C_ENABLE(hi2c);\n\n  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n  hi2c->State = HAL_I2C_STATE_READY;\n  hi2c->PreviousState = I2C_STATE_NONE;\n  hi2c->Mode = HAL_I2C_MODE_NONE;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitialize the I2C peripheral.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)\n{\n  /* Check the I2C handle allocation */\n  if (hi2c == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\n\n  hi2c->State = HAL_I2C_STATE_BUSY;\n\n  /* Disable the I2C Peripheral Clock */\n  __HAL_I2C_DISABLE(hi2c);\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n  if (hi2c->MspDeInitCallback == NULL)\n  {\n    hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit  */\n  }\n\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  hi2c->MspDeInitCallback(hi2c);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  HAL_I2C_MspDeInit(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n\n  hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;\n  hi2c->State         = HAL_I2C_STATE_RESET;\n  hi2c->PreviousState = I2C_STATE_NONE;\n  hi2c->Mode          = HAL_I2C_MODE_NONE;\n\n  /* Release Lock */\n  __HAL_UNLOCK(hi2c);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initialize the I2C MSP.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitialize the I2C MSP.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MspDeInit could be implemented in the user file\n   */\n}\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  Register a User I2C Callback\n  *         To be used instead of the weak predefined callback\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  CallbackID ID of the callback to be registered\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\n  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\n  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\n  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\n  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\n  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(hi2c);\n\n  if (HAL_I2C_STATE_READY == hi2c->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\n        hi2c->MasterTxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\n        hi2c->MasterRxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\n        hi2c->SlaveTxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\n        hi2c->SlaveRxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\n        hi2c->ListenCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\n        hi2c->MemTxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\n        hi2c->MemRxCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_ERROR_CB_ID :\n        hi2c->ErrorCallback = pCallback;\n        break;\n\n      case HAL_I2C_ABORT_CB_ID :\n        hi2c->AbortCpltCallback = pCallback;\n        break;\n\n      case HAL_I2C_MSPINIT_CB_ID :\n        hi2c->MspInitCallback = pCallback;\n        break;\n\n      case HAL_I2C_MSPDEINIT_CB_ID :\n        hi2c->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_I2C_STATE_RESET == hi2c->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_I2C_MSPINIT_CB_ID :\n        hi2c->MspInitCallback = pCallback;\n        break;\n\n      case HAL_I2C_MSPDEINIT_CB_ID :\n        hi2c->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hi2c);\n  return status;\n}\n\n/**\n  * @brief  Unregister an I2C Callback\n  *         I2C callback is redirected to the weak predefined callback\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  CallbackID ID of the callback to be unregistered\n  *         This parameter can be one of the following values:\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID\n  *          @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID\n  *          @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID\n  *          @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID\n  *          @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID\n  *          @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID\n  *          @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hi2c);\n\n  if (HAL_I2C_STATE_READY == hi2c->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_I2C_MASTER_TX_COMPLETE_CB_ID :\n        hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */\n        break;\n\n      case HAL_I2C_MASTER_RX_COMPLETE_CB_ID :\n        hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */\n        break;\n\n      case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID :\n        hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback;   /* Legacy weak SlaveTxCpltCallback  */\n        break;\n\n      case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID :\n        hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback;   /* Legacy weak SlaveRxCpltCallback  */\n        break;\n\n      case HAL_I2C_LISTEN_COMPLETE_CB_ID :\n        hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback;     /* Legacy weak ListenCpltCallback   */\n        break;\n\n      case HAL_I2C_MEM_TX_COMPLETE_CB_ID :\n        hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback;       /* Legacy weak MemTxCpltCallback    */\n        break;\n\n      case HAL_I2C_MEM_RX_COMPLETE_CB_ID :\n        hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback;       /* Legacy weak MemRxCpltCallback    */\n        break;\n\n      case HAL_I2C_ERROR_CB_ID :\n        hi2c->ErrorCallback = HAL_I2C_ErrorCallback;               /* Legacy weak ErrorCallback        */\n        break;\n\n      case HAL_I2C_ABORT_CB_ID :\n        hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\n        break;\n\n      case HAL_I2C_MSPINIT_CB_ID :\n        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\n        break;\n\n      case HAL_I2C_MSPDEINIT_CB_ID :\n        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_I2C_STATE_RESET == hi2c->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_I2C_MSPINIT_CB_ID :\n        hi2c->MspInitCallback = HAL_I2C_MspInit;                   /* Legacy weak MspInit              */\n        break;\n\n      case HAL_I2C_MSPDEINIT_CB_ID :\n        hi2c->MspDeInitCallback = HAL_I2C_MspDeInit;               /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hi2c);\n  return status;\n}\n\n/**\n  * @brief  Register the Slave Address Match I2C Callback\n  *         To be used instead of the weak HAL_I2C_AddrCallback() predefined callback\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  pCallback pointer to the Address Match Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(hi2c);\n\n  if (HAL_I2C_STATE_READY == hi2c->State)\n  {\n    hi2c->AddrCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hi2c);\n  return status;\n}\n\n/**\n  * @brief  UnRegister the Slave Address Match I2C Callback\n  *         Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hi2c);\n\n  if (HAL_I2C_STATE_READY == hi2c->State)\n  {\n    hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hi2c);\n  return status;\n}\n\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions\n *  @brief   Data transfers functions\n *\n@verbatim\n ===============================================================================\n                      ##### IO operation functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to manage the I2C data\n    transfers.\n\n    (#) There are two modes of transfer:\n       (++) Blocking mode : The communication is performed in the polling mode.\n            The status of all data processing is returned by the same function\n            after finishing transfer.\n       (++) No-Blocking mode : The communication is performed using Interrupts\n            or DMA. These functions return the status of the transfer startup.\n            The end of the data processing will be indicated through the\n            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when\n            using DMA mode.\n\n    (#) Blocking mode functions are :\n        (++) HAL_I2C_Master_Transmit()\n        (++) HAL_I2C_Master_Receive()\n        (++) HAL_I2C_Slave_Transmit()\n        (++) HAL_I2C_Slave_Receive()\n        (++) HAL_I2C_Mem_Write()\n        (++) HAL_I2C_Mem_Read()\n        (++) HAL_I2C_IsDeviceReady()\n\n    (#) No-Blocking mode functions with Interrupt are :\n        (++) HAL_I2C_Master_Transmit_IT()\n        (++) HAL_I2C_Master_Receive_IT()\n        (++) HAL_I2C_Slave_Transmit_IT()\n        (++) HAL_I2C_Slave_Receive_IT()\n        (++) HAL_I2C_Mem_Write_IT()\n        (++) HAL_I2C_Mem_Read_IT()\n        (++) HAL_I2C_Master_Seq_Transmit_IT()\n        (++) HAL_I2C_Master_Seq_Receive_IT()\n        (++) HAL_I2C_Slave_Seq_Transmit_IT()\n        (++) HAL_I2C_Slave_Seq_Receive_IT()\n        (++) HAL_I2C_EnableListen_IT()\n        (++) HAL_I2C_DisableListen_IT()\n        (++) HAL_I2C_Master_Abort_IT()\n\n    (#) No-Blocking mode functions with DMA are :\n        (++) HAL_I2C_Master_Transmit_DMA()\n        (++) HAL_I2C_Master_Receive_DMA()\n        (++) HAL_I2C_Slave_Transmit_DMA()\n        (++) HAL_I2C_Slave_Receive_DMA()\n        (++) HAL_I2C_Mem_Write_DMA()\n        (++) HAL_I2C_Mem_Read_DMA()\n        (++) HAL_I2C_Master_Seq_Transmit_DMA()\n        (++) HAL_I2C_Master_Seq_Receive_DMA()\n        (++) HAL_I2C_Slave_Seq_Transmit_DMA()\n        (++) HAL_I2C_Slave_Seq_Receive_DMA()\n\n    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:\n        (++) HAL_I2C_MasterTxCpltCallback()\n        (++) HAL_I2C_MasterRxCpltCallback()\n        (++) HAL_I2C_SlaveTxCpltCallback()\n        (++) HAL_I2C_SlaveRxCpltCallback()\n        (++) HAL_I2C_MemTxCpltCallback()\n        (++) HAL_I2C_MemRxCpltCallback()\n        (++) HAL_I2C_AddrCallback()\n        (++) HAL_I2C_ListenCpltCallback()\n        (++) HAL_I2C_ErrorCallback()\n        (++) HAL_I2C_AbortCpltCallback()\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Transmits in master mode an amount of data in blocking mode.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n    {\n      return HAL_BUSY;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Send Slave Address */\n    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    while (hi2c->XferSize > 0U)\n    {\n      /* Wait until TXE flag is set */\n      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n      {\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n        {\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n        }\n        return HAL_ERROR;\n      }\n\n      /* Write data to DR */\n      hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n      hi2c->XferSize--;\n\n      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))\n      {\n        /* Write data to DR */\n        hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferCount--;\n        hi2c->XferSize--;\n      }\n\n      /* Wait until BTF flag is set */\n      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n      {\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n        {\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n        }\n        return HAL_ERROR;\n      }\n    }\n\n    /* Generate Stop */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receives in master mode an amount of data in blocking mode.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n    {\n      return HAL_BUSY;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode        = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Send Slave Address */\n    if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    if (hi2c->XferSize == 0U)\n    {\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    else if (hi2c->XferSize == 1U)\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    else if (hi2c->XferSize == 2U)\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Enable Pos */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n\n    while (hi2c->XferSize > 0U)\n    {\n      if (hi2c->XferSize <= 3U)\n      {\n        /* One byte */\n        if (hi2c->XferSize == 1U)\n        {\n          /* Wait until RXNE flag is set */\n          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n        /* Two bytes */\n        else if (hi2c->XferSize == 2U)\n        {\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n        /* 3 Last bytes */\n        else\n        {\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n      }\n      else\n      {\n        /* Wait until RXNE flag is set */\n        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n        {\n          return HAL_ERROR;\n        }\n\n        /* Read data from DR */\n        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferSize--;\n        hi2c->XferCount--;\n\n        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)\n        {\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n      }\n    }\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Transmits in slave mode an amount of data in blocking mode.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State       = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Enable Address Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Wait until ADDR flag is set */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    /* If 10bit addressing mode is selected */\n    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)\n    {\n      /* Wait until ADDR flag is set */\n      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\n      {\n        return HAL_ERROR;\n      }\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n\n    while (hi2c->XferSize > 0U)\n    {\n      /* Wait until TXE flag is set */\n      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n      {\n        /* Disable Address Acknowledge */\n        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        return HAL_ERROR;\n      }\n\n      /* Write data to DR */\n      hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n      hi2c->XferSize--;\n\n      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))\n      {\n        /* Write data to DR */\n        hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferCount--;\n        hi2c->XferSize--;\n      }\n    }\n\n    /* Wait until AF flag is set */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Clear AF flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n    /* Disable Address Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receive in slave mode an amount of data in blocking mode\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == (uint16_t)0))\n    {\n      return HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State       = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode        = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Enable Address Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Wait until ADDR flag is set */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    while (hi2c->XferSize > 0U)\n    {\n      /* Wait until RXNE flag is set */\n      if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n      {\n        /* Disable Address Acknowledge */\n        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        return HAL_ERROR;\n      }\n\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferSize--;\n      hi2c->XferCount--;\n\n      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))\n      {\n        /* Read data from DR */\n        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferSize--;\n        hi2c->XferCount--;\n      }\n    }\n\n    /* Wait until STOP flag is set */\n    if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n    {\n      /* Disable Address Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      return HAL_ERROR;\n    }\n\n    /* Clear STOP flag */\n    __HAL_I2C_CLEAR_STOPFLAG(hi2c);\n\n    /* Disable Address Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with Interrupt\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n              to avoid the risk of I2C interrupt handle execution before current\n              process unlock */\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receive in master mode an amount of data in non-blocking mode with Interrupt\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n\n    /* Enable Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n    to avoid the risk of I2C interrupt handle execution before current\n    process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with Interrupt\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\n{\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Enable Address Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n              to avoid the risk of I2C interrupt handle execution before current\n              process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with Interrupt\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\n{\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Enable Address Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n              to avoid the risk of I2C interrupt handle execution before current\n              process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Transmit in master mode an amount of data in non-blocking mode with DMA\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n  HAL_StatusTypeDef dmaxferstatus;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if (hi2c->hdmatx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmatx->XferHalfCpltCallback = NULL;\n        hi2c->hdmatx->XferM1CpltCallback = NULL;\n        hi2c->hdmatx->XferM1HalfCpltCallback = NULL;\n        hi2c->hdmatx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        /* Generate Start */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n\n        /* Enable EVT and ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n        /* Enable DMA Request */\n        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Generate Start */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n\n      /* Enable EVT, BUF and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n    }\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receive in master mode an amount of data in non-blocking mode with DMA\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n  HAL_StatusTypeDef dmaxferstatus;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if (hi2c->hdmarx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmarx->XferHalfCpltCallback = NULL;\n        hi2c->hdmarx->XferM1CpltCallback = NULL;\n        hi2c->hdmarx->XferM1HalfCpltCallback = NULL;\n        hi2c->hdmarx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        /* Generate Start */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n\n        /* Enable EVT and ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n        /* Enable DMA Request */\n        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Generate Start */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n\n      /* Enable EVT, BUF and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n    }\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Transmit in slave mode an amount of data in non-blocking mode with DMA\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef dmaxferstatus;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    if (hi2c->hdmatx != NULL)\n    {\n      /* Set the I2C DMA transfer complete callback */\n      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;\n\n      /* Set the DMA error callback */\n      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\n\n      /* Set the unused DMA callbacks to NULL */\n      hi2c->hdmatx->XferHalfCpltCallback = NULL;\n      hi2c->hdmatx->XferM1CpltCallback = NULL;\n      hi2c->hdmatx->XferM1HalfCpltCallback = NULL;\n      hi2c->hdmatx->XferAbortCallback = NULL;\n\n      /* Enable the DMA stream */\n      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_LISTEN;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    if (dmaxferstatus == HAL_OK)\n    {\n      /* Enable Address Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n      /* Enable EVT and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n      /* Enable DMA Request */\n      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;\n\n      return HAL_OK;\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_READY;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receive in slave mode an amount of data in non-blocking mode with DMA\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef dmaxferstatus;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    if (hi2c->hdmarx != NULL)\n    {\n      /* Set the I2C DMA transfer complete callback */\n      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;\n\n      /* Set the DMA error callback */\n      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\n\n      /* Set the unused DMA callbacks to NULL */\n      hi2c->hdmarx->XferHalfCpltCallback = NULL;\n      hi2c->hdmarx->XferM1CpltCallback = NULL;\n      hi2c->hdmarx->XferM1HalfCpltCallback = NULL;\n      hi2c->hdmarx->XferAbortCallback = NULL;\n\n      /* Enable the DMA stream */\n      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_LISTEN;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    if (dmaxferstatus == HAL_OK)\n    {\n      /* Enable Address Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n      /* Enable EVT and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n      /* Enable DMA Request */\n      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n      return HAL_OK;\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_READY;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Write an amount of data in blocking mode to a specific memory address\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n    {\n      return HAL_BUSY;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Send Slave Address and Memory Address */\n    if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    while (hi2c->XferSize > 0U)\n    {\n      /* Wait until TXE flag is set */\n      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n      {\n        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n        {\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n        }\n        return HAL_ERROR;\n      }\n\n      /* Write data to DR */\n      hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferSize--;\n      hi2c->XferCount--;\n\n      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))\n      {\n        /* Write data to DR */\n        hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferSize--;\n        hi2c->XferCount--;\n      }\n    }\n\n    /* Wait until BTF flag is set */\n    if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n    {\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n      }\n      return HAL_ERROR;\n    }\n\n    /* Generate Stop */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Read an amount of data in blocking mode from a specific memory address\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n    {\n      return HAL_BUSY;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Send Slave Address and Memory Address */\n    if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    if (hi2c->XferSize == 0U)\n    {\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    else if (hi2c->XferSize == 1U)\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    else if (hi2c->XferSize == 2U)\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Enable Pos */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n    else\n    {\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n\n    while (hi2c->XferSize > 0U)\n    {\n      if (hi2c->XferSize <= 3U)\n      {\n        /* One byte */\n        if (hi2c->XferSize == 1U)\n        {\n          /* Wait until RXNE flag is set */\n          if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n        /* Two bytes */\n        else if (hi2c->XferSize == 2U)\n        {\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n        /* 3 Last bytes */\n        else\n        {\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Wait until BTF flag is set */\n          if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)\n          {\n            return HAL_ERROR;\n          }\n\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n      }\n      else\n      {\n        /* Wait until RXNE flag is set */\n        if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)\n        {\n          return HAL_ERROR;\n        }\n\n        /* Read data from DR */\n        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferSize--;\n        hi2c->XferCount--;\n\n        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)\n        {\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n\n          /* Update counter */\n          hi2c->XferSize--;\n          hi2c->XferCount--;\n        }\n      }\n    }\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Write an amount of data in non-blocking mode with Interrupt to a specific memory address\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n    hi2c->Memaddress  = MemAddress;\n    hi2c->MemaddSize  = MemAddSize;\n    hi2c->EventCount  = 0U;\n\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n    to avoid the risk of I2C interrupt handle execution before current\n    process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Read an amount of data in non-blocking mode with Interrupt from a specific memory address\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n    hi2c->Devaddress  = DevAddress;\n    hi2c->Memaddress  = MemAddress;\n    hi2c->MemaddSize  = MemAddSize;\n    hi2c->EventCount  = 0U;\n\n    /* Enable Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    if (hi2c->XferSize > 0U)\n    {\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n\n      /* Enable EVT, BUF and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n    }\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Write an amount of data in non-blocking mode with DMA to a specific memory address\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\n{\n  __IO uint32_t count = 0U;\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if (hi2c->hdmatx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmatx->XferHalfCpltCallback = NULL;\n        hi2c->hdmatx->XferM1CpltCallback = NULL;\n        hi2c->hdmatx->XferM1HalfCpltCallback = NULL;\n        hi2c->hdmatx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* Send Slave Address and Memory Address */\n        if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\n        {\n          /* Abort the ongoing DMA */\n          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx);\n\n          /* Prevent unused argument(s) compilation and MISRA warning */\n          UNUSED(dmaxferstatus);\n\n          /* Set the unused I2C DMA transfer complete callback to NULL */\n          hi2c->hdmatx->XferCpltCallback = NULL;\n\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          hi2c->XferSize = 0U;\n          hi2c->XferCount = 0U;\n\n          /* Disable I2C peripheral to prevent dummy data in buffer */\n          __HAL_I2C_DISABLE(hi2c);\n\n          return HAL_ERROR;\n        }\n\n        /* Clear ADDR flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n        /* Enable ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);\n\n        /* Enable DMA Request */\n        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n        return HAL_OK;\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_READY;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Reads an amount of data in non-blocking mode with DMA from a specific memory address.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be read\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)\n{\n  /* Init tickstart for timeout management*/\n  uint32_t tickstart = HAL_GetTick();\n  __IO uint32_t count = 0U;\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n    do\n    {\n      count--;\n      if (count == 0U)\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MEM;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if (hi2c->hdmarx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmarx->XferHalfCpltCallback = NULL;\n        hi2c->hdmarx->XferM1CpltCallback = NULL;\n        hi2c->hdmarx->XferM1HalfCpltCallback = NULL;\n        hi2c->hdmarx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* Send Slave Address and Memory Address */\n        if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\n        {\n          /* Abort the ongoing DMA */\n          dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx);\n\n          /* Prevent unused argument(s) compilation and MISRA warning */\n          UNUSED(dmaxferstatus);\n\n          /* Set the unused I2C DMA transfer complete callback to NULL */\n          hi2c->hdmarx->XferCpltCallback = NULL;\n\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          hi2c->XferSize = 0U;\n          hi2c->XferCount = 0U;\n\n          /* Disable I2C peripheral to prevent dummy data in buffer */\n          __HAL_I2C_DISABLE(hi2c);\n\n          return HAL_ERROR;\n        }\n\n        if (hi2c->XferSize == 1U)\n        {\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n        }\n        else\n        {\n          /* Enable Last DMA bit */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n        }\n\n        /* Clear ADDR flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n        /* Enable ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);\n\n        /* Enable DMA Request */\n        hi2c->Instance->CR2 |= I2C_CR2_DMAEN;\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Send Slave Address and Memory Address */\n      if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)\n      {\n        return HAL_ERROR;\n      }\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n      hi2c->State = HAL_I2C_STATE_READY;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n    }\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Checks if target device is ready for communication.\n  * @note   This function is used with Memory devices\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  Trials Number of trials\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)\n{\n  /* Get tick */\n  uint32_t tickstart = HAL_GetTick();\n  uint32_t I2C_Trials = 1U;\n  FlagStatus tmp1;\n  FlagStatus tmp2;\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Wait until BUSY flag is reset */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n    {\n      return HAL_BUSY;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State = HAL_I2C_STATE_BUSY;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    do\n    {\n      /* Generate Start */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n      /* Wait until SB flag is set */\n      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)\n      {\n        if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n        {\n          hi2c->ErrorCode = HAL_I2C_WRONG_START;\n        }\n        return HAL_TIMEOUT;\n      }\n\n      /* Send slave address */\n      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);\n\n      /* Wait until ADDR or AF flag are set */\n      /* Get tick */\n      tickstart = HAL_GetTick();\n\n      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);\n      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\n      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))\n      {\n        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\n        {\n          hi2c->State = HAL_I2C_STATE_TIMEOUT;\n        }\n        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);\n        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);\n      }\n\n      hi2c->State = HAL_I2C_STATE_READY;\n\n      /* Check if the ADDR flag has been set */\n      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n        /* Clear ADDR Flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n        /* Wait until BUSY flag is reset */\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n        {\n          return HAL_ERROR;\n        }\n\n        hi2c->State = HAL_I2C_STATE_READY;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_OK;\n      }\n      else\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n        /* Clear AF Flag */\n        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n        /* Wait until BUSY flag is reset */\n        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)\n        {\n          return HAL_ERROR;\n        }\n      }\n\n      /* Increment Trials */\n      I2C_Trials++;\n    }\n    while (I2C_Trials < Trials);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_ERROR;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  __IO uint32_t Prev_State = 0x00U;\n  __IO uint32_t count      = 0x00U;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Check Busy Flag only if FIRST call of Master interface */\n    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))\n    {\n      /* Wait until BUSY flag is reset */\n      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n      do\n      {\n        count--;\n        if (count == 0U)\n        {\n          hi2c->PreviousState       = I2C_STATE_NONE;\n          hi2c->State               = HAL_I2C_STATE_READY;\n          hi2c->Mode                = HAL_I2C_MODE_NONE;\n          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n          /* Process Unlocked */\n          __HAL_UNLOCK(hi2c);\n\n          return HAL_ERROR;\n        }\n      }\n      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n    hi2c->Devaddress  = DevAddress;\n\n    Prev_State = hi2c->PreviousState;\n\n    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n    /* Mean Previous state is same as current state */\n    if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n    {\n      /* Generate Start */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n    }\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n    to avoid the risk of I2C interrupt handle execution before current\n    process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA.\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  __IO uint32_t Prev_State = 0x00U;\n  __IO uint32_t count      = 0x00U;\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Check Busy Flag only if FIRST call of Master interface */\n    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))\n    {\n      /* Wait until BUSY flag is reset */\n      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n      do\n      {\n        count--;\n        if (count == 0U)\n        {\n          hi2c->PreviousState       = I2C_STATE_NONE;\n          hi2c->State               = HAL_I2C_STATE_READY;\n          hi2c->Mode                = HAL_I2C_MODE_NONE;\n          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n          /* Process Unlocked */\n          __HAL_UNLOCK(hi2c);\n\n          return HAL_ERROR;\n        }\n      }\n      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n    hi2c->Devaddress  = DevAddress;\n\n    Prev_State = hi2c->PreviousState;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if (hi2c->hdmatx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmatx->XferHalfCpltCallback = NULL;\n        hi2c->hdmatx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n        /* Mean Previous state is same as current state */\n        if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n        {\n          /* Generate Start */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n        }\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n\n        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */\n        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */\n        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))\n        {\n          /* Enable DMA Request */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n        }\n\n        /* Enable EVT and ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n      /* Mean Previous state is same as current state */\n      if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n      {\n        /* Generate Start */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n      }\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n\n      /* Enable EVT, BUF and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n    }\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  __IO uint32_t Prev_State = 0x00U;\n  __IO uint32_t count = 0U;\n  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Check Busy Flag only if FIRST call of Master interface */\n    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))\n    {\n      /* Wait until BUSY flag is reset */\n      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n      do\n      {\n        count--;\n        if (count == 0U)\n        {\n          hi2c->PreviousState       = I2C_STATE_NONE;\n          hi2c->State               = HAL_I2C_STATE_READY;\n          hi2c->Mode                = HAL_I2C_MODE_NONE;\n          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n          /* Process Unlocked */\n          __HAL_UNLOCK(hi2c);\n\n          return HAL_ERROR;\n        }\n      }\n      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n    hi2c->Devaddress  = DevAddress;\n\n    Prev_State = hi2c->PreviousState;\n\n    if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))\n    {\n      if (Prev_State == I2C_STATE_MASTER_BUSY_RX)\n      {\n        /* Disable Acknowledge */\n        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        /* Enable Pos */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n        /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */\n        enableIT &= ~I2C_IT_BUF;\n      }\n      else\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n      }\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n    }\n\n    /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n    /* Mean Previous state is same as current state */\n    if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n    {\n      /* Generate Start */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n    }\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n    to avoid the risk of I2C interrupt handle execution before current\n    process unlock */\n\n    /* Enable interrupts */\n    __HAL_I2C_ENABLE_IT(hi2c, enableIT);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential receive in master mode an amount of data in non-blocking mode with DMA\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  __IO uint32_t Prev_State = 0x00U;\n  __IO uint32_t count = 0U;\n  uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    /* Check Busy Flag only if FIRST call of Master interface */\n    if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME))\n    {\n      /* Wait until BUSY flag is reset */\n      count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U);\n      do\n      {\n        count--;\n        if (count == 0U)\n        {\n          hi2c->PreviousState       = I2C_STATE_NONE;\n          hi2c->State               = HAL_I2C_STATE_READY;\n          hi2c->Mode                = HAL_I2C_MODE_NONE;\n          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n          /* Process Unlocked */\n          __HAL_UNLOCK(hi2c);\n\n          return HAL_ERROR;\n        }\n      }\n      while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    /* Clear Last DMA bit */\n    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX;\n    hi2c->Mode      = HAL_I2C_MODE_MASTER;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n    hi2c->Devaddress  = DevAddress;\n\n    Prev_State = hi2c->PreviousState;\n\n    if (hi2c->XferSize > 0U)\n    {\n      if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)))\n      {\n        if (Prev_State == I2C_STATE_MASTER_BUSY_RX)\n        {\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          /* Enable Pos */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n          /* Enable Last DMA bit */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n        }\n        else\n        {\n          /* Enable Acknowledge */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n        }\n      }\n      else\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))\n        {\n          /* Enable Last DMA bit */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n        }\n      }\n      if (hi2c->hdmarx != NULL)\n      {\n        /* Set the I2C DMA transfer complete callback */\n        hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;\n\n        /* Set the DMA error callback */\n        hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\n\n        /* Set the unused DMA callbacks to NULL */\n        hi2c->hdmarx->XferHalfCpltCallback = NULL;\n        hi2c->hdmarx->XferAbortCallback = NULL;\n\n        /* Enable the DMA stream */\n        dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n      if (dmaxferstatus == HAL_OK)\n      {\n        /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n        /* Mean Previous state is same as current state */\n        if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n        {\n          /* Generate Start */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n          /* Update interrupt for only EVT and ERR */\n          enableIT = (I2C_IT_EVT | I2C_IT_ERR);\n        }\n        else\n        {\n          /* Update interrupt for only ERR */\n          enableIT = I2C_IT_ERR;\n        }\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        /* Note : The I2C interrupts must be enabled after unlocking current process\n        to avoid the risk of I2C interrupt handle execution before current\n        process unlock */\n\n        /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */\n        /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */\n        if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))\n        {\n          /* Enable DMA Request */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n        }\n\n        /* Enable EVT and ERR interrupt */\n        __HAL_I2C_ENABLE_IT(hi2c, enableIT);\n      }\n      else\n      {\n        /* Update I2C state */\n        hi2c->State     = HAL_I2C_STATE_READY;\n        hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n        /* Update I2C error code */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */\n      /* Mean Previous state is same as current state */\n      if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1))\n      {\n        /* Generate Start */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n      }\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n\n      /* Enable interrupts */\n      __HAL_I2C_ENABLE_IT(hi2c, enableIT);\n    }\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n              to avoid the risk of I2C interrupt handle execution before current\n              process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential transmit in slave mode an amount of data in non-blocking mode with DMA\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\n    /* and then toggle the HAL slave RX state to TX state */\n    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\n    {\n      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n      {\n        /* Abort DMA Xfer if any */\n        if (hi2c->hdmarx != NULL)\n        {\n          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n          /* Set the I2C DMA Abort callback :\n           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\n\n          /* Abort DMA RX */\n          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\n          {\n            /* Call Directly XferAbortCallback function in case of error */\n            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\n          }\n        }\n      }\n    }\n    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\n    {\n      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n      {\n        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n        /* Abort DMA Xfer if any */\n        if (hi2c->hdmatx != NULL)\n        {\n          /* Set the I2C DMA Abort callback :\n           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\n\n          /* Abort DMA TX */\n          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\n          {\n            /* Call Directly XferAbortCallback function in case of error */\n            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\n          }\n        }\n      }\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_TX_LISTEN;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n\n    if (hi2c->hdmatx != NULL)\n    {\n      /* Set the I2C DMA transfer complete callback */\n      hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;\n\n      /* Set the DMA error callback */\n      hi2c->hdmatx->XferErrorCallback = I2C_DMAError;\n\n      /* Set the unused DMA callbacks to NULL */\n      hi2c->hdmatx->XferHalfCpltCallback = NULL;\n      hi2c->hdmatx->XferAbortCallback = NULL;\n\n      /* Enable the DMA stream */\n      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_LISTEN;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    if (dmaxferstatus == HAL_OK)\n    {\n      /* Enable Address Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n      /* Enable EVT and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n      /* Enable DMA Request */\n      hi2c->Instance->CR2 |= I2C_CR2_DMAEN;\n\n      return HAL_OK;\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_READY;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Note : The I2C interrupts must be enabled after unlocking current process\n              to avoid the risk of I2C interrupt handle execution before current\n              process unlock */\n\n    /* Enable EVT, BUF and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sequential receive in slave mode an amount of data in non-blocking mode with DMA\n  * @note   This interface allow to manage repeated start condition when a direction change during transfer\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  pData Pointer to data buffer\n  * @param  Size Amount of data to be sent\n  * @param  XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)\n{\n  HAL_StatusTypeDef dmaxferstatus;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));\n\n  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    /* Disable Interrupts, to prevent preemption during treatment in case of multicall */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */\n    /* and then toggle the HAL slave RX state to TX state */\n    if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)\n    {\n      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n      {\n        /* Abort DMA Xfer if any */\n        if (hi2c->hdmarx != NULL)\n        {\n          CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n          /* Set the I2C DMA Abort callback :\n           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n          hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\n\n          /* Abort DMA RX */\n          if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\n          {\n            /* Call Directly XferAbortCallback function in case of error */\n            hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\n          }\n        }\n      }\n    }\n    else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)\n    {\n      if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n      {\n        CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n        /* Abort DMA Xfer if any */\n        if (hi2c->hdmatx != NULL)\n        {\n          /* Set the I2C DMA Abort callback :\n           will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n          hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\n\n          /* Abort DMA TX */\n          if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\n          {\n            /* Call Directly XferAbortCallback function in case of error */\n            hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\n          }\n        }\n      }\n    }\n    else\n    {\n      /* Nothing to do */\n    }\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Disable Pos */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n\n    hi2c->State     = HAL_I2C_STATE_BUSY_RX_LISTEN;\n    hi2c->Mode      = HAL_I2C_MODE_SLAVE;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Prepare transfer parameters */\n    hi2c->pBuffPtr    = pData;\n    hi2c->XferCount   = Size;\n    hi2c->XferSize    = hi2c->XferCount;\n    hi2c->XferOptions = XferOptions;\n\n    if (hi2c->hdmarx != NULL)\n    {\n      /* Set the I2C DMA transfer complete callback */\n      hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;\n\n      /* Set the DMA error callback */\n      hi2c->hdmarx->XferErrorCallback = I2C_DMAError;\n\n      /* Set the unused DMA callbacks to NULL */\n      hi2c->hdmarx->XferHalfCpltCallback = NULL;\n      hi2c->hdmarx->XferAbortCallback = NULL;\n\n      /* Enable the DMA stream */\n      dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_LISTEN;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    if (dmaxferstatus == HAL_OK)\n    {\n      /* Enable Address Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      /* Enable DMA Request */\n      SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n      /* Note : The I2C interrupts must be enabled after unlocking current process\n      to avoid the risk of I2C interrupt handle execution before current\n      process unlock */\n      /* Enable EVT and ERR interrupt */\n      __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n      return HAL_OK;\n    }\n    else\n    {\n      /* Update I2C state */\n      hi2c->State     = HAL_I2C_STATE_READY;\n      hi2c->Mode      = HAL_I2C_MODE_NONE;\n\n      /* Update I2C error code */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Enable the Address listen mode with Interrupt.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)\n{\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    hi2c->State = HAL_I2C_STATE_LISTEN;\n\n    /* Check if the I2C is already enabled */\n    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)\n    {\n      /* Enable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n    }\n\n    /* Enable Address Acknowledge */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Enable EVT and ERR interrupt */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Disable the Address listen mode with Interrupt.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of tmp to prevent undefined behavior of volatile usage */\n  uint32_t tmp;\n\n  /* Disable Address listen mode only if a transfer is not ongoing */\n  if (hi2c->State == HAL_I2C_STATE_LISTEN)\n  {\n    tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;\n    hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    /* Disable Address Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Disable EVT and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Abort a master I2C IT or DMA process communication with Interrupt.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for the specified I2C.\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;\n\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(DevAddress);\n\n  /* Abort Master transfer during Receive or Transmit process    */\n  if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER))\n  {\n    /* Process Locked */\n    __HAL_LOCK(hi2c);\n\n    hi2c->PreviousState = I2C_STATE_NONE;\n    hi2c->State = HAL_I2C_STATE_ABORT;\n\n    /* Disable Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    /* Generate Stop */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n    hi2c->XferCount = 0U;\n\n    /* Disable EVT, BUF and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\n    I2C_ITError(hi2c);\n\n    return HAL_OK;\n  }\n  else\n  {\n    /* Wrong usage of abort function */\n    /* This function should be used only in case of abort monitored by master device */\n    /* Or periphal is not in busy state, mean there is no active sequence to be abort */\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks\n * @{\n */\n\n/**\n  * @brief  This function handles I2C event interrupt request.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\nvoid HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)\n{\n  uint32_t sr1itflags;\n  uint32_t sr2itflags               = 0U;\n  uint32_t itsources                = READ_REG(hi2c->Instance->CR2);\n  uint32_t CurrentXferOptions       = hi2c->XferOptions;\n  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  /* Master or Memory mode selected */\n  if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))\n  {\n    sr2itflags   = READ_REG(hi2c->Instance->SR2);\n    sr1itflags   = READ_REG(hi2c->Instance->SR1);\n\n    /* Exit IRQ event until Start Bit detected in case of Other frame requested */\n    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U))\n    {\n      return;\n    }\n\n    /* SB Set ----------------------------------------------------------------*/\n    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n    {\n      /* Convert OTHER_xxx XferOptions if any */\n      I2C_ConvertOtherXferOptions(hi2c);\n\n      I2C_Master_SB(hi2c);\n    }\n    /* ADD10 Set -------------------------------------------------------------*/\n    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n    {\n      I2C_Master_ADD10(hi2c);\n    }\n    /* ADDR Set --------------------------------------------------------------*/\n    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n    {\n      I2C_Master_ADDR(hi2c);\n    }\n    /* I2C in mode Transmitter -----------------------------------------------*/\n    else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET)\n    {\n      /* Do not check buffer and BTF flag if a Xfer DMA is on going */\n      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)\n      {\n        /* TXE set and BTF reset -----------------------------------------------*/\n        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))\n        {\n          I2C_MasterTransmit_TXE(hi2c);\n        }\n        /* BTF set -------------------------------------------------------------*/\n        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n        {\n          if (CurrentMode == HAL_I2C_MODE_MASTER)\n          {\n            I2C_MasterTransmit_BTF(hi2c);\n          }\n          else /* HAL_I2C_MODE_MEM */\n          {\n            I2C_MemoryTransmit_TXE_BTF(hi2c);\n          }\n        }\n        else\n        {\n          /* Do nothing */\n        }\n      }\n    }\n    /* I2C in mode Receiver --------------------------------------------------*/\n    else\n    {\n      /* Do not check buffer and BTF flag if a Xfer DMA is on going */\n      if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN)\n      {\n        /* RXNE set and BTF reset -----------------------------------------------*/\n        if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))\n        {\n          I2C_MasterReceive_RXNE(hi2c);\n        }\n        /* BTF set -------------------------------------------------------------*/\n        else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n        {\n          I2C_MasterReceive_BTF(hi2c);\n        }\n        else\n        {\n          /* Do nothing */\n        }\n      }\n    }\n  }\n  /* Slave mode selected */\n  else\n  {\n    /* If an error is detected, read only SR1 register to prevent */\n    /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */\n    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\n    {\n      sr1itflags   = READ_REG(hi2c->Instance->SR1);\n    }\n    else\n    {\n      sr2itflags   = READ_REG(hi2c->Instance->SR2);\n      sr1itflags   = READ_REG(hi2c->Instance->SR1);\n    }\n\n    /* ADDR set --------------------------------------------------------------*/\n    if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n    {\n      /* Now time to read SR2, this will clear ADDR flag automatically */\n      if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\n      {\n        sr2itflags   = READ_REG(hi2c->Instance->SR2);\n      }\n      I2C_Slave_ADDR(hi2c, sr2itflags);\n    }\n    /* STOPF set --------------------------------------------------------------*/\n    else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n    {\n      I2C_Slave_STOPF(hi2c);\n    }\n    /* I2C in mode Transmitter -----------------------------------------------*/\n    else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))\n    {\n      /* TXE set and BTF reset -----------------------------------------------*/\n      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))\n      {\n        I2C_SlaveTransmit_TXE(hi2c);\n      }\n      /* BTF set -------------------------------------------------------------*/\n      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n      {\n        I2C_SlaveTransmit_BTF(hi2c);\n      }\n      else\n      {\n        /* Do nothing */\n      }\n    }\n    /* I2C in mode Receiver --------------------------------------------------*/\n    else\n    {\n      /* RXNE set and BTF reset ----------------------------------------------*/\n      if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET))\n      {\n        I2C_SlaveReceive_RXNE(hi2c);\n      }\n      /* BTF set -------------------------------------------------------------*/\n      else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET))\n      {\n        I2C_SlaveReceive_BTF(hi2c);\n      }\n      else\n      {\n        /* Do nothing */\n      }\n    }\n  }\n}\n\n/**\n  * @brief  This function handles I2C error interrupt request.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\nvoid HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)\n{\n  HAL_I2C_ModeTypeDef tmp1;\n  uint32_t tmp2;\n  HAL_I2C_StateTypeDef tmp3;\n  uint32_t tmp4;\n  uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);\n  uint32_t itsources  = READ_REG(hi2c->Instance->CR2);\n  uint32_t error      = HAL_I2C_ERROR_NONE;\n  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;\n\n  /* I2C Bus error interrupt occurred ----------------------------------------*/\n  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))\n  {\n    error |= HAL_I2C_ERROR_BERR;\n\n    /* Clear BERR flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);\n  }\n\n  /* I2C Arbitration Lost error interrupt occurred ---------------------------*/\n  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))\n  {\n    error |= HAL_I2C_ERROR_ARLO;\n\n    /* Clear ARLO flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);\n  }\n\n  /* I2C Acknowledge failure error interrupt occurred ------------------------*/\n  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))\n  {\n    tmp1 = CurrentMode;\n    tmp2 = hi2c->XferCount;\n    tmp3 = hi2c->State;\n    tmp4 = hi2c->PreviousState;\n    if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \\\n        ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \\\n         ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))\n    {\n      I2C_Slave_AF(hi2c);\n    }\n    else\n    {\n      /* Clear AF flag */\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n      error |= HAL_I2C_ERROR_AF;\n\n      /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */\n      if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM))\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n      }\n    }\n  }\n\n  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/\n  if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET))\n  {\n    error |= HAL_I2C_ERROR_OVR;\n    /* Clear OVR flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);\n  }\n\n  /* Call the Error Callback in case of Error detected -----------------------*/\n  if (error != HAL_I2C_ERROR_NONE)\n  {\n    hi2c->ErrorCode |= error;\n    I2C_ITError(hi2c);\n  }\n}\n\n/**\n  * @brief  Master Tx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MasterTxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Master Rx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MasterRxCpltCallback could be implemented in the user file\n   */\n}\n\n/** @brief  Slave Tx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Slave Rx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Slave Address Match callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition\n  * @param  AddrMatchCode Address Match Code\n  * @retval None\n  */\n__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n  UNUSED(TransferDirection);\n  UNUSED(AddrMatchCode);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_AddrCallback() could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Listen Complete callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_ListenCpltCallback() could be implemented in the user file\n  */\n}\n\n/**\n  * @brief  Memory Tx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MemTxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Memory Rx Transfer completed callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_MemRxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  I2C error callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_ErrorCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  I2C abort callback.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval None\n  */\n__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hi2c);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_I2C_AbortCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions\n *  @brief   Peripheral State, Mode and Error functions\n  *\n@verbatim\n ===============================================================================\n            ##### Peripheral State, Mode and Error functions #####\n ===============================================================================\n    [..]\n    This subsection permit to get in run-time the status of the peripheral\n    and the data flow.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the I2C handle state.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL state\n  */\nHAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)\n{\n  /* Return I2C handle state */\n  return hi2c->State;\n}\n\n/**\n  * @brief  Returns the I2C Master, Slave, Memory or no mode.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval HAL mode\n  */\nHAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)\n{\n  return hi2c->Mode;\n}\n\n/**\n  * @brief  Return the I2C error code.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *              the configuration information for the specified I2C.\n  * @retval I2C Error Code\n  */\nuint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)\n{\n  return hi2c->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup I2C_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Handle TXE flag for Master\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;\n  uint32_t CurrentXferOptions       = hi2c->XferOptions;\n\n  if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))\n  {\n    /* Call TxCpltCallback() directly if no stop mode is set */\n    if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))\n    {\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n      hi2c->State = HAL_I2C_STATE_READY;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->MasterTxCpltCallback(hi2c);\n#else\n      HAL_I2C_MasterTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else /* Generate Stop condition then Call TxCpltCallback() */\n    {\n      /* Disable EVT, BUF and ERR interrupt */\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n      hi2c->PreviousState = I2C_STATE_NONE;\n      hi2c->State = HAL_I2C_STATE_READY;\n\n      if (hi2c->Mode == HAL_I2C_MODE_MEM)\n      {\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MemTxCpltCallback(hi2c);\n#else\n        HAL_I2C_MemTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MasterTxCpltCallback(hi2c);\n#else\n        HAL_I2C_MasterTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n    }\n  }\n  else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \\\n           ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))\n  {\n    if (hi2c->XferCount == 0U)\n    {\n      /* Disable BUF interrupt */\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n    }\n    else\n    {\n      if (hi2c->Mode == HAL_I2C_MODE_MEM)\n      {\n        I2C_MemoryTransmit_TXE_BTF(hi2c);\n      }\n      else\n      {\n        /* Write data to DR */\n        hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferCount--;\n      }\n    }\n  }\n  else\n  {\n    /* Do nothing */\n  }\n}\n\n/**\n  * @brief  Handle BTF flag for Master transmitter\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  uint32_t CurrentXferOptions = hi2c->XferOptions;\n\n  if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\n  {\n    if (hi2c->XferCount != 0U)\n    {\n      /* Write data to DR */\n      hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n    }\n    else\n    {\n      /* Call TxCpltCallback() directly if no stop mode is set */\n      if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))\n      {\n        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n        hi2c->State = HAL_I2C_STATE_READY;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MasterTxCpltCallback(hi2c);\n#else\n        HAL_I2C_MasterTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n      else /* Generate Stop condition then Call TxCpltCallback() */\n      {\n        /* Disable EVT, BUF and ERR interrupt */\n        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n        hi2c->PreviousState = I2C_STATE_NONE;\n        hi2c->State = HAL_I2C_STATE_READY;\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MasterTxCpltCallback(hi2c);\n#else\n        HAL_I2C_MasterTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n    }\n  }\n  else\n  {\n    /* Do nothing */\n  }\n}\n\n/**\n  * @brief  Handle TXE and BTF flag for Memory transmitter\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  if (hi2c->EventCount == 0U)\n  {\n    /* If Memory address size is 8Bit */\n    if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)\n    {\n      /* Send Memory Address */\n      hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);\n\n      hi2c->EventCount += 2U;\n    }\n    /* If Memory address size is 16Bit */\n    else\n    {\n      /* Send MSB of Memory Address */\n      hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);\n\n      hi2c->EventCount++;\n    }\n  }\n  else if (hi2c->EventCount == 1U)\n  {\n    /* Send LSB of Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);\n\n    hi2c->EventCount++;\n  }\n  else if (hi2c->EventCount == 2U)\n  {\n    if (CurrentState == HAL_I2C_STATE_BUSY_RX)\n    {\n      /* Generate Restart */\n      hi2c->Instance->CR1 |= I2C_CR1_START;\n    }\n    else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))\n    {\n      /* Write data to DR */\n      hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n    }\n    else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))\n    {\n      /* Generate Stop condition then Call TxCpltCallback() */\n      /* Disable EVT, BUF and ERR interrupt */\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n      hi2c->PreviousState = I2C_STATE_NONE;\n      hi2c->State = HAL_I2C_STATE_READY;\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->MemTxCpltCallback(hi2c);\n#else\n      HAL_I2C_MemTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      /* Do nothing */\n    }\n  }\n  else\n  {\n    /* Do nothing */\n  }\n}\n\n/**\n  * @brief  Handle RXNE flag for Master\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)\n{\n  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\n  {\n    uint32_t tmp;\n\n    tmp = hi2c->XferCount;\n    if (tmp > 3U)\n    {\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n\n      if (hi2c->XferCount == (uint16_t)3)\n      {\n        /* Disable BUF interrupt, this help to treat correctly the last 4 bytes\n        on BTF subroutine */\n        /* Disable BUF interrupt */\n        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n      }\n    }\n    else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U)))\n    {\n      if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK)\n      {\n        /* Disable Acknowledge */\n        CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        /* Disable EVT, BUF and ERR interrupt */\n        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n        /* Read data from DR */\n        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferCount--;\n\n        hi2c->State = HAL_I2C_STATE_READY;\n\n        if (hi2c->Mode == HAL_I2C_MODE_MEM)\n        {\n          hi2c->Mode = HAL_I2C_MODE_NONE;\n          hi2c->PreviousState = I2C_STATE_NONE;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n          hi2c->MemRxCpltCallback(hi2c);\n#else\n          HAL_I2C_MemRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n        }\n        else\n        {\n          hi2c->Mode = HAL_I2C_MODE_NONE;\n          hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n          hi2c->MasterRxCpltCallback(hi2c);\n#else\n          HAL_I2C_MasterRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n        }\n      }\n      else\n      {\n        /* Disable EVT, BUF and ERR interrupt */\n        __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n        /* Read data from DR */\n        *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n        /* Increment Buffer pointer */\n        hi2c->pBuffPtr++;\n\n        /* Update counter */\n        hi2c->XferCount--;\n\n        hi2c->State = HAL_I2C_STATE_READY;\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n\n        /* Call user error callback */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->ErrorCallback(hi2c);\n#else\n        HAL_I2C_ErrorCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n    }\n    else\n    {\n      /* Do nothing */\n    }\n  }\n}\n\n/**\n  * @brief  Handle BTF flag for Master receiver\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  uint32_t CurrentXferOptions = hi2c->XferOptions;\n\n  if (hi2c->XferCount == 4U)\n  {\n    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes\n       on BTF subroutine if there is a reception delay between N-1 and N byte */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n  }\n  else if (hi2c->XferCount == 3U)\n  {\n    /* Disable BUF interrupt, this help to treat correctly the last 2 bytes\n       on BTF subroutine if there is a reception delay between N-1 and N byte */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n\n    if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME))\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n    }\n\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n  }\n  else if (hi2c->XferCount == 2U)\n  {\n    /* Prepare next transfer or stop current transfer */\n    if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP))\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n    }\n    else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME))\n    {\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n    }\n    else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    else\n    {\n      /* Do nothing */\n    }\n\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n\n    /* Disable EVT and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    if (hi2c->Mode == HAL_I2C_MODE_MEM)\n    {\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n      hi2c->PreviousState = I2C_STATE_NONE;\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->MemRxCpltCallback(hi2c);\n#else\n      HAL_I2C_MemRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n      hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->MasterRxCpltCallback(hi2c);\n#else\n      HAL_I2C_MasterRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n  }\n  else\n  {\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n  }\n}\n\n/**\n  * @brief  Handle SB flag for Master\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_Master_SB(I2C_HandleTypeDef *hi2c)\n{\n  if (hi2c->Mode == HAL_I2C_MODE_MEM)\n  {\n    if (hi2c->EventCount == 0U)\n    {\n      /* Send slave address */\n      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);\n    }\n    else\n    {\n      hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);\n    }\n  }\n  else\n  {\n    if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\n    {\n      /* Send slave 7 Bits address */\n      if (hi2c->State == HAL_I2C_STATE_BUSY_TX)\n      {\n        hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);\n      }\n      else\n      {\n        hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);\n      }\n\n      if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))\n          || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))\n      {\n        /* Enable DMA Request */\n        SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n      }\n    }\n    else\n    {\n      if (hi2c->EventCount == 0U)\n      {\n        /* Send header of slave address */\n        hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);\n      }\n      else if (hi2c->EventCount == 1U)\n      {\n        /* Send header of slave address */\n        hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);\n      }\n      else\n      {\n        /* Do nothing */\n      }\n    }\n  }\n}\n\n/**\n  * @brief  Handle ADD10 flag for Master\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)\n{\n  /* Send slave address */\n  hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);\n\n  if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL))\n      || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL)))\n  {\n    /* Enable DMA Request */\n    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n  }\n}\n\n/**\n  * @brief  Handle ADDR flag for Master\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  HAL_I2C_ModeTypeDef CurrentMode       = hi2c->Mode;\n  uint32_t CurrentXferOptions           = hi2c->XferOptions;\n  uint32_t Prev_State                   = hi2c->PreviousState;\n\n  if (hi2c->State == HAL_I2C_STATE_BUSY_RX)\n  {\n    if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))\n    {\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n    }\n    else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))\n    {\n      /* Clear ADDR flag */\n      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n      /* Generate Restart */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n      hi2c->EventCount++;\n    }\n    else\n    {\n      if (hi2c->XferCount == 0U)\n      {\n        /* Clear ADDR flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n      }\n      else if (hi2c->XferCount == 1U)\n      {\n        if (CurrentXferOptions == I2C_NO_OPTION_FRAME)\n        {\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n          {\n            /* Disable Acknowledge */\n            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n            /* Clear ADDR flag */\n            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n          }\n          else\n          {\n            /* Clear ADDR flag */\n            __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n            /* Generate Stop */\n            SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n          }\n        }\n        /* Prepare next transfer or stop current transfer */\n        else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \\\n                 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME)))\n        {\n          if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))\n          {\n            /* Disable Acknowledge */\n            CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n          }\n          else\n          {\n            /* Enable Acknowledge */\n            SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n          }\n\n          /* Clear ADDR flag */\n          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n        }\n        else\n        {\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          /* Clear ADDR flag */\n          __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n          /* Generate Stop */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n        }\n      }\n      else if (hi2c->XferCount == 2U)\n      {\n        if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP))\n        {\n          /* Disable Acknowledge */\n          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n          /* Enable Pos */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);\n        }\n        else\n        {\n          /* Enable Acknowledge */\n          SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n        }\n\n        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))\n        {\n          /* Enable Last DMA bit */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n        }\n\n        /* Clear ADDR flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n      }\n      else\n      {\n        /* Enable Acknowledge */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n        if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME)))\n        {\n          /* Enable Last DMA bit */\n          SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n        }\n\n        /* Clear ADDR flag */\n        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n      }\n\n      /* Reset Event counter  */\n      hi2c->EventCount = 0U;\n    }\n  }\n  else\n  {\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n  }\n}\n\n/**\n  * @brief  Handle TXE flag for Slave\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  if (hi2c->XferCount != 0U)\n  {\n    /* Write data to DR */\n    hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n\n    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))\n    {\n      /* Last Byte is received, disable Interrupt */\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n\n      /* Set state at HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->SlaveTxCpltCallback(hi2c);\n#else\n      HAL_I2C_SlaveTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n  }\n}\n\n/**\n  * @brief  Handle BTF flag for Slave transmitter\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)\n{\n  if (hi2c->XferCount != 0U)\n  {\n    /* Write data to DR */\n    hi2c->Instance->DR = *hi2c->pBuffPtr;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n  }\n}\n\n/**\n  * @brief  Handle RXNE flag for Slave\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  if (hi2c->XferCount != 0U)\n  {\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n\n    if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))\n    {\n      /* Last Byte is received, disable Interrupt */\n      __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);\n\n      /* Set state at HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->SlaveRxCpltCallback(hi2c);\n#else\n      HAL_I2C_SlaveRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n  }\n}\n\n/**\n  * @brief  Handle BTF flag for Slave receiver\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)\n{\n  if (hi2c->XferCount != 0U)\n  {\n    /* Read data from DR */\n    *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n    /* Increment Buffer pointer */\n    hi2c->pBuffPtr++;\n\n    /* Update counter */\n    hi2c->XferCount--;\n  }\n}\n\n/**\n  * @brief  Handle ADD flag for Slave\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  IT2Flags Interrupt2 flags to handle.\n  * @retval None\n  */\nstatic void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags)\n{\n  uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;\n  uint16_t SlaveAddrCode;\n\n  if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */\n    __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF));\n\n    /* Transfer Direction requested by Master */\n    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET)\n    {\n      TransferDirection = I2C_DIRECTION_TRANSMIT;\n    }\n\n    if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET)\n    {\n      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1;\n    }\n    else\n    {\n      SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2;\n    }\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    /* Call Slave Addr callback */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode);\n#else\n    HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n  }\n}\n\n/**\n  * @brief  Handle STOPF flag for Slave\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  /* Disable EVT, BUF and ERR interrupt */\n  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n  /* Clear STOPF flag */\n  __HAL_I2C_CLEAR_STOPFLAG(hi2c);\n\n  /* Disable Acknowledge */\n  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n  /* If a DMA is ongoing, Update handle size context */\n  if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n  {\n    if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))\n    {\n      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx));\n\n      if (hi2c->XferCount != 0U)\n      {\n        /* Set ErrorCode corresponding to a Non-Acknowledge */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\n      }\n\n      /* Disable, stop the current DMA */\n      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n      /* Abort DMA Xfer if any */\n      if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY)\n      {\n        /* Set the I2C DMA Abort callback :\n        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n        hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\n\n        /* Abort DMA RX */\n        if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\n        {\n          /* Call Directly XferAbortCallback function in case of error */\n          hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\n        }\n      }\n    }\n    else\n    {\n      hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx));\n\n      if (hi2c->XferCount != 0U)\n      {\n        /* Set ErrorCode corresponding to a Non-Acknowledge */\n        hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\n      }\n\n      /* Disable, stop the current DMA */\n      CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n      /* Abort DMA Xfer if any */\n      if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY)\n      {\n        /* Set the I2C DMA Abort callback :\n        will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n        hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\n\n        /* Abort DMA TX */\n        if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\n        {\n          /* Call Directly XferAbortCallback function in case of error */\n          hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\n        }\n      }\n    }\n  }\n\n  /* All data are not transferred, so set error code accordingly */\n  if (hi2c->XferCount != 0U)\n  {\n    /* Store Last receive data if any */\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)\n    {\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n    }\n\n    /* Store Last receive data if any */\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\n    {\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n\n      /* Update counter */\n      hi2c->XferCount--;\n    }\n\n    if (hi2c->XferCount != 0U)\n    {\n      /* Set ErrorCode corresponding to a Non-Acknowledge */\n      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;\n    }\n  }\n\n  if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\n  {\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\n    I2C_ITError(hi2c);\n  }\n  else\n  {\n    if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)\n    {\n      /* Set state at HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_NONE;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->SlaveRxCpltCallback(hi2c);\n#else\n      HAL_I2C_SlaveRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n\n    if (hi2c->State == HAL_I2C_STATE_LISTEN)\n    {\n      hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n      hi2c->PreviousState = I2C_STATE_NONE;\n      hi2c->State = HAL_I2C_STATE_READY;\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n\n      /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->ListenCpltCallback(hi2c);\n#else\n      HAL_I2C_ListenCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      if ((hi2c->PreviousState  == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX))\n      {\n        hi2c->PreviousState = I2C_STATE_NONE;\n        hi2c->State = HAL_I2C_STATE_READY;\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->SlaveRxCpltCallback(hi2c);\n#else\n        HAL_I2C_SlaveRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n    }\n  }\n}\n\n/**\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @retval None\n  */\nstatic void I2C_Slave_AF(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variables to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n  uint32_t CurrentXferOptions       = hi2c->XferOptions;\n\n  if (((CurrentXferOptions ==  I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \\\n      (CurrentState == HAL_I2C_STATE_LISTEN))\n  {\n    hi2c->XferOptions = I2C_NO_OPTION_FRAME;\n\n    /* Disable EVT, BUF and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    /* Clear AF flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n    /* Disable Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n    hi2c->PreviousState = I2C_STATE_NONE;\n    hi2c->State         = HAL_I2C_STATE_READY;\n    hi2c->Mode          = HAL_I2C_MODE_NONE;\n\n    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->ListenCpltCallback(hi2c);\n#else\n    HAL_I2C_ListenCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n  else if (CurrentState == HAL_I2C_STATE_BUSY_TX)\n  {\n    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\n    hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\n    hi2c->State         = HAL_I2C_STATE_READY;\n    hi2c->Mode          = HAL_I2C_MODE_NONE;\n\n    /* Disable EVT, BUF and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n\n    /* Clear AF flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n    /* Disable Acknowledge */\n    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->SlaveTxCpltCallback(hi2c);\n#else\n    HAL_I2C_SlaveTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* Clear AF flag only */\n    /* State Listen, but XferOptions == FIRST or NEXT */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n  }\n}\n\n/**\n  * @brief  I2C interrupts error process\n  * @param  hi2c I2C handle.\n  * @retval None\n  */\nstatic void I2C_ITError(I2C_HandleTypeDef *hi2c)\n{\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n  HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode;\n  uint32_t CurrentError;\n\n  if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX))\n  {\n    /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */\n    hi2c->Instance->CR1 &= ~I2C_CR1_POS;\n  }\n\n  if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n  {\n    /* keep HAL_I2C_STATE_LISTEN */\n    hi2c->PreviousState = I2C_STATE_NONE;\n    hi2c->State = HAL_I2C_STATE_LISTEN;\n  }\n  else\n  {\n    /* If state is an abort treatment on going, don't change state */\n    /* This change will be do later */\n    if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT))\n    {\n      hi2c->State = HAL_I2C_STATE_READY;\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n    }\n    hi2c->PreviousState = I2C_STATE_NONE;\n  }\n\n  /* Abort DMA transfer */\n  if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN)\n  {\n    hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;\n\n    if (hi2c->hdmatx->State != HAL_DMA_STATE_READY)\n    {\n      /* Set the DMA Abort callback :\n      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n      hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;\n\n      if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)\n      {\n        /* Disable I2C peripheral to prevent dummy data in buffer */\n        __HAL_I2C_DISABLE(hi2c);\n\n        hi2c->State = HAL_I2C_STATE_READY;\n\n        /* Call Directly XferAbortCallback function in case of error */\n        hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);\n      }\n    }\n    else\n    {\n      /* Set the DMA Abort callback :\n      will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */\n      hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;\n\n      if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)\n      {\n        /* Store Last receive data if any */\n        if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\n        {\n          /* Read data from DR */\n          *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n          /* Increment Buffer pointer */\n          hi2c->pBuffPtr++;\n        }\n\n        /* Disable I2C peripheral to prevent dummy data in buffer */\n        __HAL_I2C_DISABLE(hi2c);\n\n        hi2c->State = HAL_I2C_STATE_READY;\n\n        /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */\n        hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);\n      }\n    }\n  }\n  else if (hi2c->State == HAL_I2C_STATE_ABORT)\n  {\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;\n\n    /* Store Last receive data if any */\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\n    {\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n    }\n\n    /* Disable I2C peripheral to prevent dummy data in buffer */\n    __HAL_I2C_DISABLE(hi2c);\n\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->AbortCpltCallback(hi2c);\n#else\n    HAL_I2C_AbortCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* Store Last receive data if any */\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)\n    {\n      /* Read data from DR */\n      *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR;\n\n      /* Increment Buffer pointer */\n      hi2c->pBuffPtr++;\n    }\n\n    /* Call user error callback */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->ErrorCallback(hi2c);\n#else\n    HAL_I2C_ErrorCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n\n  /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */\n  CurrentError = hi2c->ErrorCode;\n\n  if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \\\n      ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \\\n      ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF)     || \\\n      ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR))\n  {\n    /* Disable EVT, BUF and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);\n  }\n\n  /* So may inform upper layer that listen phase is stopped */\n  /* during NACK error treatment */\n  CurrentState = hi2c->State;\n  if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN))\n  {\n    hi2c->XferOptions   = I2C_NO_OPTION_FRAME;\n    hi2c->PreviousState = I2C_STATE_NONE;\n    hi2c->State         = HAL_I2C_STATE_READY;\n    hi2c->Mode          = HAL_I2C_MODE_NONE;\n\n    /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->ListenCpltCallback(hi2c);\n#else\n    HAL_I2C_ListenCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  uint32_t CurrentXferOptions = hi2c->XferOptions;\n\n  /* Generate Start condition if first transfer */\n  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))\n  {\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n  }\n  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)\n  {\n    /* Generate ReStart */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n  }\n  else\n  {\n    /* Do nothing */\n  }\n\n  /* Wait until SB flag is set */\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n    {\n      hi2c->ErrorCode = HAL_I2C_WRONG_START;\n    }\n    return HAL_TIMEOUT;\n  }\n\n  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\n  {\n    /* Send slave address */\n    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);\n  }\n  else\n  {\n    /* Send header of slave address */\n    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);\n\n    /* Wait until ADD10 flag is set */\n    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Send slave address */\n    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);\n  }\n\n  /* Wait until ADDR flag is set */\n  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Master sends target device address for read request.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  uint32_t CurrentXferOptions = hi2c->XferOptions;\n\n  /* Enable Acknowledge */\n  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n  /* Generate Start condition if first transfer */\n  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME)  || (CurrentXferOptions == I2C_NO_OPTION_FRAME))\n  {\n    /* Generate Start */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n  }\n  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)\n  {\n    /* Generate ReStart */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n  }\n  else\n  {\n    /* Do nothing */\n  }\n\n  /* Wait until SB flag is set */\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n    {\n      hi2c->ErrorCode = HAL_I2C_WRONG_START;\n    }\n    return HAL_TIMEOUT;\n  }\n\n  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)\n  {\n    /* Send slave address */\n    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);\n  }\n  else\n  {\n    /* Send header of slave address */\n    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);\n\n    /* Wait until ADD10 flag is set */\n    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Send slave address */\n    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);\n\n    /* Wait until ADDR flag is set */\n    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Clear ADDR flag */\n    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n    /* Generate Restart */\n    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n    /* Wait until SB flag is set */\n    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n    {\n      if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n      {\n        hi2c->ErrorCode = HAL_I2C_WRONG_START;\n      }\n      return HAL_TIMEOUT;\n    }\n\n    /* Send header of slave address */\n    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);\n  }\n\n  /* Wait until ADDR flag is set */\n  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Master sends target device address followed by internal memory address for write request.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Generate Start */\n  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n  /* Wait until SB flag is set */\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n    {\n      hi2c->ErrorCode = HAL_I2C_WRONG_START;\n    }\n    return HAL_TIMEOUT;\n  }\n\n  /* Send slave address */\n  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);\n\n  /* Wait until ADDR flag is set */\n  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Clear ADDR flag */\n  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n  /* Wait until TXE flag is set */\n  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\n  {\n    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    return HAL_ERROR;\n  }\n\n  /* If Memory address size is 8Bit */\n  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\n  {\n    /* Send Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);\n  }\n  /* If Memory address size is 16Bit */\n  else\n  {\n    /* Send MSB of Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);\n\n    /* Wait until TXE flag is set */\n    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\n    {\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n      }\n      return HAL_ERROR;\n    }\n\n    /* Send LSB of Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Master sends target device address followed by internal memory address for read request.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  DevAddress Target device address: The device 7 bits address value\n  *         in datasheet must be shifted to the left before calling the interface\n  * @param  MemAddress Internal memory address\n  * @param  MemAddSize Size of internal memory address\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Enable Acknowledge */\n  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n  /* Generate Start */\n  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n  /* Wait until SB flag is set */\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n    {\n      hi2c->ErrorCode = HAL_I2C_WRONG_START;\n    }\n    return HAL_TIMEOUT;\n  }\n\n  /* Send slave address */\n  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);\n\n  /* Wait until ADDR flag is set */\n  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Clear ADDR flag */\n  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);\n\n  /* Wait until TXE flag is set */\n  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\n  {\n    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    return HAL_ERROR;\n  }\n\n  /* If Memory address size is 8Bit */\n  if (MemAddSize == I2C_MEMADD_SIZE_8BIT)\n  {\n    /* Send Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);\n  }\n  /* If Memory address size is 16Bit */\n  else\n  {\n    /* Send MSB of Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);\n\n    /* Wait until TXE flag is set */\n    if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\n    {\n      if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n      {\n        /* Generate Stop */\n        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n      }\n      return HAL_ERROR;\n    }\n\n    /* Send LSB of Memory Address */\n    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);\n  }\n\n  /* Wait until TXE flag is set */\n  if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)\n  {\n    if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n    return HAL_ERROR;\n  }\n\n  /* Generate Restart */\n  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);\n\n  /* Wait until SB flag is set */\n  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)\n  {\n    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)\n    {\n      hi2c->ErrorCode = HAL_I2C_WRONG_START;\n    }\n    return HAL_TIMEOUT;\n  }\n\n  /* Send slave address */\n  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);\n\n  /* Wait until ADDR flag is set */\n  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DMA I2C process complete callback.\n  * @param  hdma DMA handle\n  * @retval None\n  */\nstatic void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)\n{\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n  HAL_I2C_ModeTypeDef CurrentMode   = hi2c->Mode;\n  uint32_t CurrentXferOptions       = hi2c->XferOptions;\n\n  /* Disable EVT and ERR interrupt */\n  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n  /* Clear Complete callback */\n  if (hi2c->hdmatx != NULL)\n  {\n    hi2c->hdmatx->XferCpltCallback = NULL;\n  }\n  if (hi2c->hdmarx != NULL)\n  {\n    hi2c->hdmarx->XferCpltCallback = NULL;\n  }\n\n  if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))\n  {\n    /* Disable DMA Request */\n    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n    hi2c->XferCount = 0U;\n\n    if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)\n    {\n      /* Set state at HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->SlaveTxCpltCallback(hi2c);\n#else\n      HAL_I2C_SlaveTxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)\n    {\n      /* Set state at HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n\n      /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->SlaveRxCpltCallback(hi2c);\n#else\n      HAL_I2C_SlaveRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      /* Do nothing */\n    }\n\n    /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */\n    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n  }\n  /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */\n  else if (hi2c->Mode != HAL_I2C_MODE_NONE)\n  {\n    if (hi2c->XferCount == (uint16_t)1)\n    {\n      /* Disable Acknowledge */\n      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n    }\n\n    /* Disable EVT and ERR interrupt */\n    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);\n\n    /* Prepare next transfer or stop current transfer */\n    if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME))\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n    }\n\n    /* Disable Last DMA */\n    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);\n\n    /* Disable DMA Request */\n    CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);\n\n    hi2c->XferCount = 0U;\n\n    /* Check if Errors has been detected during transfer */\n    if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)\n    {\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n      hi2c->ErrorCallback(hi2c);\n#else\n      HAL_I2C_ErrorCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      hi2c->State = HAL_I2C_STATE_READY;\n\n      if (hi2c->Mode == HAL_I2C_MODE_MEM)\n      {\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n        hi2c->PreviousState = I2C_STATE_NONE;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MemRxCpltCallback(hi2c);\n#else\n        HAL_I2C_MemRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        hi2c->Mode = HAL_I2C_MODE_NONE;\n        hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n        hi2c->MasterRxCpltCallback(hi2c);\n#else\n        HAL_I2C_MasterRxCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n      }\n    }\n  }\n  else\n  {\n    /* Do nothing */\n  }\n}\n\n/**\n  * @brief  DMA I2C communication error callback.\n  * @param  hdma DMA handle\n  * @retval None\n  */\nstatic void I2C_DMAError(DMA_HandleTypeDef *hdma)\n{\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Clear Complete callback */\n  if (hi2c->hdmatx != NULL)\n  {\n    hi2c->hdmatx->XferCpltCallback = NULL;\n  }\n  if (hi2c->hdmarx != NULL)\n  {\n    hi2c->hdmarx->XferCpltCallback = NULL;\n  }\n\n  /* Ignore DMA FIFO error */\n  if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)\n  {\n    /* Disable Acknowledge */\n    hi2c->Instance->CR1 &= ~I2C_CR1_ACK;\n\n    hi2c->XferCount = 0U;\n\n    hi2c->State = HAL_I2C_STATE_READY;\n    hi2c->Mode = HAL_I2C_MODE_NONE;\n\n    hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;\n\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->ErrorCallback(hi2c);\n#else\n    HAL_I2C_ErrorCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief DMA I2C communication abort callback\n  *        (To be called at end of DMA Abort procedure).\n  * @param hdma DMA handle.\n  * @retval None\n  */\nstatic void I2C_DMAAbort(DMA_HandleTypeDef *hdma)\n{\n  __IO uint32_t count = 0U;\n  I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */\n  HAL_I2C_StateTypeDef CurrentState = hi2c->State;\n\n  /* During abort treatment, check that there is no pending STOP request */\n  /* Wait until STOP flag is reset */\n  count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U);\n  do\n  {\n    if (count == 0U)\n    {\n      hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;\n      break;\n    }\n    count--;\n  }\n  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);\n\n  /* Clear Complete callback */\n  if (hi2c->hdmatx != NULL)\n  {\n    hi2c->hdmatx->XferCpltCallback = NULL;\n  }\n  if (hi2c->hdmarx != NULL)\n  {\n    hi2c->hdmarx->XferCpltCallback = NULL;\n  }\n\n  /* Disable Acknowledge */\n  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n  hi2c->XferCount = 0U;\n\n  /* Reset XferAbortCallback */\n  if (hi2c->hdmatx != NULL)\n  {\n    hi2c->hdmatx->XferAbortCallback = NULL;\n  }\n  if (hi2c->hdmarx != NULL)\n  {\n    hi2c->hdmarx->XferAbortCallback = NULL;\n  }\n\n  /* Disable I2C peripheral to prevent dummy data in buffer */\n  __HAL_I2C_DISABLE(hi2c);\n\n  /* Check if come from abort from user */\n  if (hi2c->State == HAL_I2C_STATE_ABORT)\n  {\n    hi2c->State         = HAL_I2C_STATE_READY;\n    hi2c->Mode          = HAL_I2C_MODE_NONE;\n    hi2c->ErrorCode     = HAL_I2C_ERROR_NONE;\n\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->AbortCpltCallback(hi2c);\n#else\n    HAL_I2C_AbortCpltCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN)\n    {\n      /* Renable I2C peripheral */\n      __HAL_I2C_ENABLE(hi2c);\n\n      /* Enable Acknowledge */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);\n\n      /* keep HAL_I2C_STATE_LISTEN */\n      hi2c->PreviousState = I2C_STATE_NONE;\n      hi2c->State = HAL_I2C_STATE_LISTEN;\n    }\n    else\n    {\n      hi2c->State = HAL_I2C_STATE_READY;\n      hi2c->Mode = HAL_I2C_MODE_NONE;\n    }\n\n    /* Call the corresponding callback to inform upper layer of End of Transfer */\n#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)\n    hi2c->ErrorCallback(hi2c);\n#else\n    HAL_I2C_ErrorCallback(hi2c);\n#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  Flag specifies the I2C flag to check.\n  * @param  Status The new Flag status (SET or RESET).\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Wait until flag is set */\n  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)\n  {\n    /* Check for the Timeout */\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n      {\n        hi2c->PreviousState     = I2C_STATE_NONE;\n        hi2c->State             = HAL_I2C_STATE_READY;\n        hi2c->Mode              = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for Master addressing phase.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *         the configuration information for I2C module\n  * @param  Flag specifies the I2C flag to check.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)\n{\n  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)\n  {\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\n    {\n      /* Generate Stop */\n      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);\n\n      /* Clear AF Flag */\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n      hi2c->PreviousState       = I2C_STATE_NONE;\n      hi2c->State               = HAL_I2C_STATE_READY;\n      hi2c->Mode                = HAL_I2C_MODE_NONE;\n      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    /* Check for the Timeout */\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for specific usage of TXE flag.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\n{\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Check for the Timeout */\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for specific usage of BTF flag.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\n{\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Check for the Timeout */\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n      {\n        hi2c->PreviousState       = I2C_STATE_NONE;\n        hi2c->State               = HAL_I2C_STATE_READY;\n        hi2c->Mode                = HAL_I2C_MODE_NONE;\n        hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hi2c);\n\n        return HAL_ERROR;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for specific usage of STOP flag.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\n{\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)\n  {\n    /* Check if a NACK is detected */\n    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)\n    {\n      return HAL_ERROR;\n    }\n\n    /* Check for the Timeout */\n    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n    {\n      hi2c->PreviousState       = I2C_STATE_NONE;\n      hi2c->State               = HAL_I2C_STATE_READY;\n      hi2c->Mode                = HAL_I2C_MODE_NONE;\n      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c)\n{\n  __IO uint32_t count = 0U;\n\n  /* Wait until STOP flag is reset */\n  count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U);\n  do\n  {\n    count--;\n    if (count == 0U)\n    {\n      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n      return HAL_ERROR;\n    }\n  }\n  while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles I2C Communication Timeout for specific usage of RXNE flag.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart Tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)\n{\n\n  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)\n  {\n    /* Check if a STOPF is detected */\n    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)\n    {\n      /* Clear STOP Flag */\n      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);\n\n      hi2c->PreviousState       = I2C_STATE_NONE;\n      hi2c->State               = HAL_I2C_STATE_READY;\n      hi2c->Mode                = HAL_I2C_MODE_NONE;\n      hi2c->ErrorCode           |= HAL_I2C_ERROR_NONE;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n\n    /* Check for the Timeout */\n    if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))\n    {\n      hi2c->PreviousState       = I2C_STATE_NONE;\n      hi2c->State               = HAL_I2C_STATE_READY;\n      hi2c->Mode                = HAL_I2C_MODE_NONE;\n      hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;\n\n      /* Process Unlocked */\n      __HAL_UNLOCK(hi2c);\n\n      return HAL_ERROR;\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles Acknowledge failed detection during an I2C Communication.\n  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2C.\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)\n{\n  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)\n  {\n    /* Clear NACKF Flag */\n    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);\n\n    hi2c->PreviousState       = I2C_STATE_NONE;\n    hi2c->State               = HAL_I2C_STATE_READY;\n    hi2c->Mode                = HAL_I2C_MODE_NONE;\n    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(hi2c);\n\n    return HAL_ERROR;\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Convert I2Cx OTHER_xxx XferOptions to functional XferOptions.\n  * @param  hi2c I2C handle.\n  * @retval None\n  */\nstatic void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c)\n{\n  /* if user set XferOptions to I2C_OTHER_FRAME            */\n  /* it request implicitly to generate a restart condition */\n  /* set XferOptions to I2C_FIRST_FRAME                    */\n  if (hi2c->XferOptions == I2C_OTHER_FRAME)\n  {\n    hi2c->XferOptions = I2C_FIRST_FRAME;\n  }\n  /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */\n  /* it request implicitly to generate a restart condition    */\n  /* then generate a stop condition at the end of transfer    */\n  /* set XferOptions to I2C_FIRST_AND_LAST_FRAME              */\n  else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME)\n  {\n    hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME;\n  }\n  else\n  {\n    /* Nothing to do */\n  }\n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_I2C_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_i2c_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_i2c_ex.c\n  * @author  MCD Application Team\n  * @brief   I2C Extension HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of I2C extension peripheral:\n  *           + Extension features functions\n  *\n  @verbatim\n  ==============================================================================\n               ##### I2C peripheral extension features  #####\n  ==============================================================================\n\n  [..] Comparing to other previous devices, the I2C interface for STM32F427xx/437xx/\n       429xx/439xx devices contains the following additional features :\n\n       (+) Possibility to disable or enable Analog Noise Filter\n       (+) Use of a configured Digital Noise Filter\n\n                     ##### How to use this driver #####\n  ==============================================================================\n  [..] This driver provides functions to configure Noise Filter\n    (#) Configure I2C Analog noise filter using the function HAL_I2C_AnalogFilter_Config()\n    (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config()\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup I2CEx I2CEx\n  * @brief I2C HAL module driver\n  * @{\n  */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n\n#if  defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup I2CEx_Exported_Functions I2C Exported Functions\n  * @{\n  */\n\n\n/** @defgroup I2CEx_Exported_Functions_Group1 Extension features functions\n *  @brief   Extension features functions\n *\n@verbatim\n ===============================================================================\n                      ##### Extension features functions #####\n ===============================================================================\n    [..] This section provides functions allowing to:\n      (+) Configure Noise Filters\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Configures I2C Analog noise filter.\n  * @param  hi2c pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2Cx peripheral.\n  * @param  AnalogFilter new state of the Analog filter.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)\n{\n  /* Check the parameters */\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\n  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    hi2c->State = HAL_I2C_STATE_BUSY;\n\n    /* Disable the selected I2C peripheral */\n    __HAL_I2C_DISABLE(hi2c);\n\n    /* Reset I2Cx ANOFF bit */\n    hi2c->Instance->FLTR &= ~(I2C_FLTR_ANOFF);\n\n    /* Disable the analog filter */\n    hi2c->Instance->FLTR |= AnalogFilter;\n\n    __HAL_I2C_ENABLE(hi2c);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Configures I2C Digital noise filter.\n  * @param  hi2c pointer to a I2C_HandleTypeDef structure that contains\n  *                the configuration information for the specified I2Cx peripheral.\n  * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)\n{\n  uint16_t tmpreg = 0;\n\n  /* Check the parameters */\n  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));\n  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));\n\n  if (hi2c->State == HAL_I2C_STATE_READY)\n  {\n    hi2c->State = HAL_I2C_STATE_BUSY;\n\n    /* Disable the selected I2C peripheral */\n    __HAL_I2C_DISABLE(hi2c);\n\n    /* Get the old register value */\n    tmpreg = hi2c->Instance->FLTR;\n\n    /* Reset I2Cx DNF bit [3:0] */\n    tmpreg &= ~(I2C_FLTR_DNF);\n\n    /* Set I2Cx DNF coefficient */\n    tmpreg |= DigitalFilter;\n\n    /* Store the new register value */\n    hi2c->Instance->FLTR = tmpreg;\n\n    __HAL_I2C_ENABLE(hi2c);\n\n    hi2c->State = HAL_I2C_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif\n\n#endif /* HAL_I2C_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pcd.c\n  * @author  MCD Application Team\n  * @brief   PCD HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the USB Peripheral Controller:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                    ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      The PCD HAL driver can be used as follows:\n\n     (#) Declare a PCD_HandleTypeDef handle structure, for example:\n         PCD_HandleTypeDef  hpcd;\n\n     (#) Fill parameters of Init structure in HCD handle\n\n     (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)\n\n     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:\n         (##) Enable the PCD/USB Low Level interface clock using\n              (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\n              (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)\n\n         (##) Initialize the related GPIO clocks\n         (##) Configure PCD pin-out\n         (##) Configure PCD NVIC interrupt\n\n     (#)Associate the Upper USB device stack to the HAL PCD Driver:\n         (##) hpcd.pData = pdev;\n\n     (#)Enable PCD transmission and reception:\n         (##) HAL_PCD_Start();\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup PCD PCD\n  * @brief PCD HAL module driver\n  * @{\n  */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/** @defgroup PCD_Private_Macros PCD Private Macros\n  * @{\n  */\n#define PCD_MIN(a, b)  (((a) < (b)) ? (a) : (b))\n#define PCD_MAX(a, b)  (((a) > (b)) ? (a) : (b))\n/**\n  * @}\n  */\n\n/* Private functions prototypes ----------------------------------------------*/\n/** @defgroup PCD_Private_Functions PCD Private Functions\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum);\nstatic HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\nstatic HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum);\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup PCD_Exported_Functions PCD Exported Functions\n  * @{\n  */\n\n/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions\n  *  @brief    Initialization and Configuration functions\n  *\n@verbatim\n ===============================================================================\n            ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the PCD according to the specified\n  *         parameters in the PCD_InitTypeDef and initialize the associated handle.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx;\n  uint8_t i;\n\n  /* Check the PCD handle allocation */\n  if (hpcd == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));\n\n  USBx = hpcd->Instance;\n\n  if (hpcd->State == HAL_PCD_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    hpcd->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n    hpcd->SOFCallback = HAL_PCD_SOFCallback;\n    hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\n    hpcd->ResetCallback = HAL_PCD_ResetCallback;\n    hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\n    hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\n    hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\n    hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\n    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback;\n    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback;\n    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback;\n    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback;\n    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback;\n    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback;\n\n    if (hpcd->MspInitCallback == NULL)\n    {\n      hpcd->MspInitCallback = HAL_PCD_MspInit;\n    }\n\n    /* Init the low level hardware */\n    hpcd->MspInitCallback(hpcd);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\n    HAL_PCD_MspInit(hpcd);\n#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */\n  }\n\n  hpcd->State = HAL_PCD_STATE_BUSY;\n\n  /* Disable DMA mode for FS instance */\n  if ((USBx->CID & (0x1U << 8)) == 0U)\n  {\n    hpcd->Init.dma_enable = 0U;\n  }\n\n  /* Disable the Interrupts */\n  __HAL_PCD_DISABLE(hpcd);\n\n  /*Init the Core (common init.) */\n  if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK)\n  {\n    hpcd->State = HAL_PCD_STATE_ERROR;\n    return HAL_ERROR;\n  }\n\n  /* Force Device Mode*/\n  (void)USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE);\n\n  /* Init endpoints structures */\n  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\n  {\n    /* Init ep structure */\n    hpcd->IN_ep[i].is_in = 1U;\n    hpcd->IN_ep[i].num = i;\n    hpcd->IN_ep[i].tx_fifo_num = i;\n    /* Control until ep is activated */\n    hpcd->IN_ep[i].type = EP_TYPE_CTRL;\n    hpcd->IN_ep[i].maxpacket = 0U;\n    hpcd->IN_ep[i].xfer_buff = 0U;\n    hpcd->IN_ep[i].xfer_len = 0U;\n  }\n\n  for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\n  {\n    hpcd->OUT_ep[i].is_in = 0U;\n    hpcd->OUT_ep[i].num = i;\n    /* Control until ep is activated */\n    hpcd->OUT_ep[i].type = EP_TYPE_CTRL;\n    hpcd->OUT_ep[i].maxpacket = 0U;\n    hpcd->OUT_ep[i].xfer_buff = 0U;\n    hpcd->OUT_ep[i].xfer_len = 0U;\n  }\n\n  /* Init Device */\n  if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK)\n  {\n    hpcd->State = HAL_PCD_STATE_ERROR;\n    return HAL_ERROR;\n  }\n\n  hpcd->USB_Address = 0U;\n  hpcd->State = HAL_PCD_STATE_READY;\n  #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  /* Activate LPM */\n  if (hpcd->Init.lpm_enable == 1U)\n  {\n    (void)HAL_PCDEx_ActivateLPM(hpcd);\n  }\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n  (void)USB_DevDisconnect(hpcd->Instance);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the PCD peripheral.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)\n{\n  /* Check the PCD handle allocation */\n  if (hpcd == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  hpcd->State = HAL_PCD_STATE_BUSY;\n\n  /* Stop Device */\n  if (USB_StopDevice(hpcd->Instance) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n  if (hpcd->MspDeInitCallback == NULL)\n  {\n    hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit  */\n  }\n\n  /* DeInit the low level hardware */\n  hpcd->MspDeInitCallback(hpcd);\n#else\n  /* DeInit the low level hardware: CLOCK, NVIC.*/\n  HAL_PCD_MspDeInit(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n  hpcd->State = HAL_PCD_STATE_RESET;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the PCD MSP.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes PCD MSP.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_MspDeInit could be implemented in the user file\n   */\n}\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n/**\n  * @brief  Register a User USB PCD Callback\n  *         To be used instead of the weak predefined callback\n  * @param  hpcd USB PCD handle\n  * @param  CallbackID ID of the callback to be registered\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\n  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\n  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\n  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\n  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\n  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\n  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\n  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\n  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,\n                                           HAL_PCD_CallbackIDTypeDef CallbackID,\n                                           pPCD_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_PCD_SOF_CB_ID :\n        hpcd->SOFCallback = pCallback;\n        break;\n\n      case HAL_PCD_SETUPSTAGE_CB_ID :\n        hpcd->SetupStageCallback = pCallback;\n        break;\n\n      case HAL_PCD_RESET_CB_ID :\n        hpcd->ResetCallback = pCallback;\n        break;\n\n      case HAL_PCD_SUSPEND_CB_ID :\n        hpcd->SuspendCallback = pCallback;\n        break;\n\n      case HAL_PCD_RESUME_CB_ID :\n        hpcd->ResumeCallback = pCallback;\n        break;\n\n      case HAL_PCD_CONNECT_CB_ID :\n        hpcd->ConnectCallback = pCallback;\n        break;\n\n      case HAL_PCD_DISCONNECT_CB_ID :\n        hpcd->DisconnectCallback = pCallback;\n        break;\n\n      case HAL_PCD_MSPINIT_CB_ID :\n        hpcd->MspInitCallback = pCallback;\n        break;\n\n      case HAL_PCD_MSPDEINIT_CB_ID :\n        hpcd->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (hpcd->State == HAL_PCD_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_PCD_MSPINIT_CB_ID :\n        hpcd->MspInitCallback = pCallback;\n        break;\n\n      case HAL_PCD_MSPDEINIT_CB_ID :\n        hpcd->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n  return status;\n}\n\n/**\n  * @brief  Unregister an USB PCD Callback\n  *         USB PCD callabck is redirected to the weak predefined callback\n  * @param  hpcd USB PCD handle\n  * @param  CallbackID ID of the callback to be unregistered\n  *         This parameter can be one of the following values:\n  *          @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID\n  *          @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID\n  *          @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID\n  *          @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID\n  *          @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID\n  *          @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID\n  *          @arg @ref HAL_PCD_DISCONNECT_CB_ID OTG PCD Disconnect callback ID\n  *          @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID\n  *          @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  /* Setup Legacy weak Callbacks  */\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_PCD_SOF_CB_ID :\n        hpcd->SOFCallback = HAL_PCD_SOFCallback;\n        break;\n\n      case HAL_PCD_SETUPSTAGE_CB_ID :\n        hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback;\n        break;\n\n      case HAL_PCD_RESET_CB_ID :\n        hpcd->ResetCallback = HAL_PCD_ResetCallback;\n        break;\n\n      case HAL_PCD_SUSPEND_CB_ID :\n        hpcd->SuspendCallback = HAL_PCD_SuspendCallback;\n        break;\n\n      case HAL_PCD_RESUME_CB_ID :\n        hpcd->ResumeCallback = HAL_PCD_ResumeCallback;\n        break;\n\n      case HAL_PCD_CONNECT_CB_ID :\n        hpcd->ConnectCallback = HAL_PCD_ConnectCallback;\n        break;\n\n      case HAL_PCD_DISCONNECT_CB_ID :\n        hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback;\n        break;\n\n      case HAL_PCD_MSPINIT_CB_ID :\n        hpcd->MspInitCallback = HAL_PCD_MspInit;\n        break;\n\n      case HAL_PCD_MSPDEINIT_CB_ID :\n        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\n        break;\n\n      default :\n        /* Update the error code */\n        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (hpcd->State == HAL_PCD_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_PCD_MSPINIT_CB_ID :\n        hpcd->MspInitCallback = HAL_PCD_MspInit;\n        break;\n\n      case HAL_PCD_MSPDEINIT_CB_ID :\n        hpcd->MspDeInitCallback = HAL_PCD_MspDeInit;\n        break;\n\n      default :\n        /* Update the error code */\n        hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD Data OUT Stage Callback\n  *         To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD Data OUT Stage Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,\n                                                       pPCD_DataOutStageCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->DataOutStageCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD Data OUT Stage Callback\n  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD Data IN Stage Callback\n  *         To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD Data IN Stage Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,\n                                                      pPCD_DataInStageCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->DataInStageCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD Data IN Stage Callback\n  *         USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD Iso OUT incomplete Callback\n  *         To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD Iso OUT incomplete Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,\n                                                       pPCD_IsoOutIncpltCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->ISOOUTIncompleteCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD Iso OUT incomplete Callback\n  *         USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD Iso IN incomplete Callback\n  *         To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD Iso IN incomplete Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,\n                                                      pPCD_IsoInIncpltCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->ISOINIncompleteCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD Iso IN incomplete Callback\n  *         USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD BCD Callback\n  *         To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD BCD Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->BCDCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD BCD Callback\n  *         USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Register USB PCD LPM Callback\n  *         To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback\n  * @param  hpcd PCD handle\n  * @param  pCallback pointer to the USB PCD LPM Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->LPMCallback = pCallback;\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister the USB PCD LPM Callback\n  *         USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hpcd);\n\n  if (hpcd->State == HAL_PCD_STATE_READY)\n  {\n    hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback  */\n  }\n  else\n  {\n    /* Update the error code */\n    hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hpcd);\n\n  return status;\n}\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions\n  *  @brief   Data transfers functions\n  *\n@verbatim\n ===============================================================================\n                      ##### IO operation functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to manage the PCD data\n    transfers.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Start the USB device\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  __HAL_LOCK(hpcd);\n\n  if ((hpcd->Init.battery_charging_enable == 1U) &&\n      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))\n  {\n    /* Enable USB Transceiver */\n    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\n  }\n\n  __HAL_PCD_ENABLE(hpcd);\n  (void)USB_DevConnect(hpcd->Instance);\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stop the USB device.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  __HAL_LOCK(hpcd);\n  __HAL_PCD_DISABLE(hpcd);\n  (void)USB_DevDisconnect(hpcd->Instance);\n\n  (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);\n\n  if ((hpcd->Init.battery_charging_enable == 1U) &&\n      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))\n  {\n    /* Disable USB Transceiver */\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\n  }\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/**\n  * @brief  Handles PCD interrupt request.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nvoid HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t i, ep_intr, epint, epnum;\n  uint32_t fifoemptymsk, temp;\n  USB_OTG_EPTypeDef *ep;\n\n  /* ensure that we are in device mode */\n  if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)\n  {\n    /* avoid spurious interrupt */\n    if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))\n    {\n      return;\n    }\n\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))\n    {\n      /* incorrect mode, acknowledge the interrupt */\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);\n    }\n\n    /* Handle RxQLevel Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))\n    {\n      USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\n\n      temp = USBx->GRXSTSP;\n\n      ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];\n\n      if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_DATA_UPDT)\n      {\n        if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U)\n        {\n          (void)USB_ReadPacket(USBx, ep->xfer_buff,\n                               (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4));\n\n          ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\n          ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\n        }\n      }\n      else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) ==  STS_SETUP_UPDT)\n      {\n        (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U);\n        ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4;\n      }\n      else\n      {\n        /* ... */\n      }\n      USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);\n    }\n\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))\n    {\n      epnum = 0U;\n\n      /* Read in the device interrupt bits */\n      ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);\n\n      while (ep_intr != 0U)\n      {\n        if ((ep_intr & 0x1U) != 0U)\n        {\n          epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum);\n\n          if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)\n          {\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);\n            (void)PCD_EP_OutXfrComplete_int(hpcd, epnum);\n          }\n\n          if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)\n          {\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);\n            /* Class B setup phase done for previous decoded setup */\n            (void)PCD_EP_OutSetupPacket_int(hpcd, epnum);\n          }\n\n          if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)\n          {\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);\n          }\n\n          /* Clear Status Phase Received interrupt */\n          if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\n          {\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\n          }\n\n          /* Clear OUT NAK interrupt */\n          if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK)\n          {\n            CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK);\n          }\n        }\n        epnum++;\n        ep_intr >>= 1U;\n      }\n    }\n\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))\n    {\n      /* Read in the device interrupt bits */\n      ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);\n\n      epnum = 0U;\n\n      while (ep_intr != 0U)\n      {\n        if ((ep_intr & 0x1U) != 0U) /* In ITR */\n        {\n          epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum);\n\n          if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)\n          {\n            fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\n            USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\n\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);\n\n            if (hpcd->Init.dma_enable == 1U)\n            {\n              hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;\n\n              /* this is ZLP, so prepare EP0 for next setup */\n              if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U))\n              {\n                /* prepare to rx more setup packets */\n                (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);\n              }\n            }\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n            hpcd->DataInStageCallback(hpcd, (uint8_t)epnum);\n#else\n            HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n          }\n          if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)\n          {\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC);\n          }\n          if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE)\n          {\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE);\n          }\n          if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE)\n          {\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE);\n          }\n          if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)\n          {\n            CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);\n          }\n          if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)\n          {\n            (void)PCD_WriteEmptyTxFifo(hpcd, epnum);\n          }\n        }\n        epnum++;\n        ep_intr >>= 1U;\n      }\n    }\n\n    /* Handle Resume Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))\n    {\n      /* Clear the Remote Wake-up Signaling */\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\n\n      if (hpcd->LPM_State == LPM_L1)\n      {\n        hpcd->LPM_State = LPM_L0;\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE);\n#else\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n      else\n      {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->ResumeCallback(hpcd);\n#else\n        HAL_PCD_ResumeCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);\n    }\n\n    /* Handle Suspend Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))\n    {\n      if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\n      {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->SuspendCallback(hpcd);\n#else\n        HAL_PCD_SuspendCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);\n    }\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n    /* Handle LPM Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))\n    {\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);\n\n      if (hpcd->LPM_State == LPM_L0)\n      {\n        hpcd->LPM_State = LPM_L1;\n        hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U;\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE);\n#else\n        HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n      else\n      {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->SuspendCallback(hpcd);\n#else\n        HAL_PCD_SuspendCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n    }\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n    /* Handle Reset Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))\n    {\n      USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;\n      (void)USB_FlushTxFifo(hpcd->Instance, 0x10U);\n\n      for (i = 0U; i < hpcd->Init.dev_endpoints; i++)\n      {\n        USBx_INEP(i)->DIEPINT = 0xFB7FU;\n        USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\n        USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;\n        USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\n        USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\n        USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;\n      }\n      USBx_DEVICE->DAINTMSK |= 0x10001U;\n\n      if (hpcd->Init.use_dedicated_ep1 != 0U)\n      {\n        USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM |\n                                   USB_OTG_DOEPMSK_XFRCM |\n                                   USB_OTG_DOEPMSK_EPDM;\n\n        USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM |\n                                  USB_OTG_DIEPMSK_XFRCM |\n                                  USB_OTG_DIEPMSK_EPDM;\n      }\n      else\n      {\n        USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |\n                                USB_OTG_DOEPMSK_XFRCM |\n                                USB_OTG_DOEPMSK_EPDM |\n                                USB_OTG_DOEPMSK_OTEPSPRM |\n                                USB_OTG_DOEPMSK_NAKM;\n\n        USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |\n                                USB_OTG_DIEPMSK_XFRCM |\n                                USB_OTG_DIEPMSK_EPDM;\n      }\n\n      /* Set Default Address to 0 */\n      USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;\n\n      /* setup EP0 to receive SETUP packets */\n      (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable,\n                             (uint8_t *)hpcd->Setup);\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);\n    }\n\n    /* Handle Enumeration done Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))\n    {\n      (void)USB_ActivateSetup(hpcd->Instance);\n      hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance);\n\n      /* Set USB Turnaround time */\n      (void)USB_SetTurnaroundTime(hpcd->Instance,\n                                  HAL_RCC_GetHCLKFreq(),\n                                  (uint8_t)hpcd->Init.speed);\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->ResetCallback(hpcd);\n#else\n      HAL_PCD_ResetCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);\n    }\n\n    /* Handle SOF Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))\n    {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->SOFCallback(hpcd);\n#else\n      HAL_PCD_SOFCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);\n    }\n\n    /* Handle Incomplete ISO IN Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))\n    {\n      /* Keep application checking the corresponding Iso IN endpoint\n      causing the incomplete Interrupt */\n      epnum = 0U;\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\n#else\n      HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);\n    }\n\n    /* Handle Incomplete ISO OUT Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))\n    {\n      /* Keep application checking the corresponding Iso OUT endpoint\n      causing the incomplete Interrupt */\n      epnum = 0U;\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\n#else\n      HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);\n    }\n\n    /* Handle Connection event Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))\n    {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->ConnectCallback(hpcd);\n#else\n      HAL_PCD_ConnectCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);\n    }\n\n    /* Handle Disconnection event Interrupt */\n    if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))\n    {\n      temp = hpcd->Instance->GOTGINT;\n\n      if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)\n      {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->DisconnectCallback(hpcd);\n#else\n        HAL_PCD_DisconnectCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n      hpcd->Instance->GOTGINT |= temp;\n    }\n  }\n}\n\n\n/**\n  * @brief  Handles PCD Wakeup interrupt request.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nvoid HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx;\n\n  USBx = hpcd->Instance;\n\n  if ((USBx->CID & (0x1U << 8)) == 0U)\n  {\n    /* Clear EXTI pending Bit */\n    __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG();\n  }\n  else\n  {\n    /* Clear EXTI pending Bit */\n    __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG();\n  }\n}\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/**\n  * @brief  Data OUT stage callback.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval None\n  */\n__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(epnum);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_DataOutStageCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Data IN stage callback\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval None\n  */\n__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(epnum);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_DataInStageCallback could be implemented in the user file\n   */\n}\n/**\n  * @brief  Setup stage callback\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_SetupStageCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  USB Start Of Frame callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_SOFCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  USB Reset callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_ResetCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Suspend event callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_SuspendCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Resume event callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_ResumeCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Incomplete ISO OUT callback.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval None\n  */\n__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(epnum);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Incomplete ISO IN callback.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval None\n  */\n__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(epnum);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Connection event callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_ConnectCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Disconnection event callback.\n  * @param  hpcd PCD handle\n  * @retval None\n  */\n__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCD_DisconnectCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions\n  *  @brief   management functions\n  *\n@verbatim\n ===============================================================================\n                      ##### Peripheral Control functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the PCD data\n    transfers.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Connect the USB device\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)\n{\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n  __HAL_LOCK(hpcd);\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n  if ((hpcd->Init.battery_charging_enable == 1U) &&\n      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))\n  {\n    /* Enable USB Transceiver */\n    USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\n  }\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n  (void)USB_DevConnect(hpcd->Instance);\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Disconnect the USB device.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)\n{\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n  __HAL_LOCK(hpcd);\n  (void)USB_DevDisconnect(hpcd->Instance);\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n  if ((hpcd->Init.battery_charging_enable == 1U) &&\n      (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY))\n  {\n    /* Disable USB Transceiver */\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\n  }\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Set the USB Device address.\n  * @param  hpcd PCD handle\n  * @param  address new device address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)\n{\n  __HAL_LOCK(hpcd);\n  hpcd->USB_Address = address;\n  (void)USB_SetDevAddress(hpcd->Instance, address);\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n/**\n  * @brief  Open and configure an endpoint.\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @param  ep_mps endpoint max packet size\n  * @param  ep_type endpoint type\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,\n                                  uint16_t ep_mps, uint8_t ep_type)\n{\n  HAL_StatusTypeDef  ret = HAL_OK;\n  PCD_EPTypeDef *ep;\n\n  if ((ep_addr & 0x80U) == 0x80U)\n  {\n    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 1U;\n  }\n  else\n  {\n    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 0U;\n  }\n\n  ep->num = ep_addr & EP_ADDR_MSK;\n  ep->maxpacket = ep_mps;\n  ep->type = ep_type;\n\n  if (ep->is_in != 0U)\n  {\n    /* Assign a Tx FIFO */\n    ep->tx_fifo_num = ep->num;\n  }\n  /* Set initial data PID. */\n  if (ep_type == EP_TYPE_BULK)\n  {\n    ep->data_pid_start = 0U;\n  }\n\n  __HAL_LOCK(hpcd);\n  (void)USB_ActivateEndpoint(hpcd->Instance, ep);\n  __HAL_UNLOCK(hpcd);\n\n  return ret;\n}\n\n/**\n  * @brief  Deactivate an endpoint.\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\n{\n  PCD_EPTypeDef *ep;\n\n  if ((ep_addr & 0x80U) == 0x80U)\n  {\n    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 1U;\n  }\n  else\n  {\n    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 0U;\n  }\n  ep->num   = ep_addr & EP_ADDR_MSK;\n\n  __HAL_LOCK(hpcd);\n  (void)USB_DeactivateEndpoint(hpcd->Instance, ep);\n  __HAL_UNLOCK(hpcd);\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  Receive an amount of data.\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @param  pBuf pointer to the reception buffer\n  * @param  len amount of data to be received\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\n{\n  PCD_EPTypeDef *ep;\n\n  ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\n\n  /*setup and start the Xfer */\n  ep->xfer_buff = pBuf;\n  ep->xfer_len = len;\n  ep->xfer_count = 0U;\n  ep->is_in = 0U;\n  ep->num = ep_addr & EP_ADDR_MSK;\n\n  if (hpcd->Init.dma_enable == 1U)\n  {\n    ep->dma_addr = (uint32_t)pBuf;\n  }\n\n  if ((ep_addr & EP_ADDR_MSK) == 0U)\n  {\n    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\n  }\n  else\n  {\n    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Get Received Data Size\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @retval Data Size\n  */\nuint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\n{\n  return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count;\n}\n/**\n  * @brief  Send an amount of data\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @param  pBuf pointer to the transmission buffer\n  * @param  len amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)\n{\n  PCD_EPTypeDef *ep;\n\n  ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\n\n  /*setup and start the Xfer */\n  ep->xfer_buff = pBuf;\n  ep->xfer_len = len;\n  ep->xfer_count = 0U;\n  ep->is_in = 1U;\n  ep->num = ep_addr & EP_ADDR_MSK;\n\n  if (hpcd->Init.dma_enable == 1U)\n  {\n    ep->dma_addr = (uint32_t)pBuf;\n  }\n\n  if ((ep_addr & EP_ADDR_MSK) == 0U)\n  {\n    (void)USB_EP0StartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\n  }\n  else\n  {\n    (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Set a STALL condition over an endpoint\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\n{\n  PCD_EPTypeDef *ep;\n\n  if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints)\n  {\n    return HAL_ERROR;\n  }\n\n  if ((0x80U & ep_addr) == 0x80U)\n  {\n    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 1U;\n  }\n  else\n  {\n    ep = &hpcd->OUT_ep[ep_addr];\n    ep->is_in = 0U;\n  }\n\n  ep->is_stall = 1U;\n  ep->num = ep_addr & EP_ADDR_MSK;\n\n  __HAL_LOCK(hpcd);\n\n  (void)USB_EPSetStall(hpcd->Instance, ep);\n\n  if ((ep_addr & EP_ADDR_MSK) == 0U)\n  {\n    (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);\n  }\n\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Clear a STALL condition over in an endpoint\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\n{\n  PCD_EPTypeDef *ep;\n\n  if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints)\n  {\n    return HAL_ERROR;\n  }\n\n  if ((0x80U & ep_addr) == 0x80U)\n  {\n    ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 1U;\n  }\n  else\n  {\n    ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK];\n    ep->is_in = 0U;\n  }\n\n  ep->is_stall = 0U;\n  ep->num = ep_addr & EP_ADDR_MSK;\n\n  __HAL_LOCK(hpcd);\n  (void)USB_EPClearStall(hpcd->Instance, ep);\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Flush an endpoint\n  * @param  hpcd PCD handle\n  * @param  ep_addr endpoint address\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)\n{\n  __HAL_LOCK(hpcd);\n\n  if ((ep_addr & 0x80U) == 0x80U)\n  {\n    (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK);\n  }\n  else\n  {\n    (void)USB_FlushRxFifo(hpcd->Instance);\n  }\n\n  __HAL_UNLOCK(hpcd);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Activate remote wakeup signalling\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\n{\n  return (USB_ActivateRemoteWakeup(hpcd->Instance));\n}\n\n/**\n  * @brief  De-activate remote wakeup signalling.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)\n{\n  return (USB_DeActivateRemoteWakeup(hpcd->Instance));\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions\n  *  @brief   Peripheral State functions\n  *\n@verbatim\n ===============================================================================\n                      ##### Peripheral State functions #####\n ===============================================================================\n    [..]\n    This subsection permits to get in run-time the status of the peripheral\n    and the data flow.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the PCD handle state.\n  * @param  hpcd PCD handle\n  * @retval HAL state\n  */\nPCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)\n{\n  return hpcd->State;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @addtogroup PCD_Private_Functions\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/**\n  * @brief  Check FIFO for the next packet to be loaded.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  USB_OTG_EPTypeDef *ep;\n  uint32_t len;\n  uint32_t len32b;\n  uint32_t fifoemptymsk;\n\n  ep = &hpcd->IN_ep[epnum];\n\n  if (ep->xfer_count > ep->xfer_len)\n  {\n    return HAL_ERROR;\n  }\n\n  len = ep->xfer_len - ep->xfer_count;\n\n  if (len > ep->maxpacket)\n  {\n    len = ep->maxpacket;\n  }\n\n  len32b = (len + 3U) / 4U;\n\n  while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) &&\n         (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U))\n  {\n    /* Write the FIFO */\n    len = ep->xfer_len - ep->xfer_count;\n\n    if (len > ep->maxpacket)\n    {\n      len = ep->maxpacket;\n    }\n    len32b = (len + 3U) / 4U;\n\n    (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len,\n                          (uint8_t)hpcd->Init.dma_enable);\n\n    ep->xfer_buff  += len;\n    ep->xfer_count += len;\n  }\n\n  if (ep->xfer_len <= ep->xfer_count)\n  {\n    fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK));\n    USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;\n  }\n\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  process EP OUT transfer complete interrupt.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\n  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\n\n  if (hpcd->Init.dma_enable == 1U)\n  {\n    if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */\n    {\n      /* StupPktRcvd = 1 this is a setup packet */\n      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&\n          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))\n      {\n        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\n      }\n    }\n    else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */\n    {\n      CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\n    }\n    else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U)\n    {\n      /* StupPktRcvd = 1 this is a setup packet */\n      if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&\n          ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))\n      {\n        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\n      }\n      else\n      {\n        /* out data packet received over EP0 */\n        hpcd->OUT_ep[epnum].xfer_count =\n          hpcd->OUT_ep[epnum].maxpacket -\n          (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);\n\n        hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;\n\n        if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))\n        {\n          /* this is ZLP, so prepare EP0 for next setup */\n          (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);\n        }\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\n#else\n        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n    }\n    else\n    {\n      /* ... */\n    }\n  }\n  else\n  {\n    if (gSNPSiD == USB_OTG_CORE_ID_310A)\n    {\n      /* StupPktRcvd = 1 this is a setup packet */\n      if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)\n      {\n        CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\n      }\n      else\n      {\n        if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR)\n        {\n          CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR);\n        }\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n        hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\n#else\n        HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n      }\n    }\n    else\n    {\n      if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U))\n      {\n        /* this is ZLP, so prepare EP0 for next setup */\n        (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup);\n      }\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum);\n#else\n      HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n    }\n  }\n\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  process EP OUT setup packet received interrupt.\n  * @param  hpcd PCD handle\n  * @param  epnum endpoint number\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\n  uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT;\n\n  if ((gSNPSiD > USB_OTG_CORE_ID_300A) &&\n      ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX))\n  {\n    CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX);\n  }\n\n  /* Inform the upper layer that a setup packet is available */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n  hpcd->SetupStageCallback(hpcd);\n#else\n  HAL_PCD_SetupStageCallback(hpcd);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n  if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U))\n  {\n    (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);\n  }\n\n  return HAL_OK;\n}\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pcd_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pcd_ex.c\n  * @author  MCD Application Team\n  * @brief   PCD Extended HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the USB Peripheral Controller:\n  *           + Extended features functions\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup PCDEx PCDEx\n  * @brief PCD Extended HAL module driver\n  * @{\n  */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions\n  * @{\n  */\n\n/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions\n  * @brief    PCDEx control functions\n  *\n@verbatim\n ===============================================================================\n                 ##### Extended features functions #####\n ===============================================================================\n    [..]  This section provides functions allowing to:\n      (+) Update FIFO configuration\n\n@endverbatim\n  * @{\n  */\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/**\n  * @brief  Set Tx FIFO\n  * @param  hpcd PCD handle\n  * @param  fifo The number of Tx fifo\n  * @param  size Fifo size\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)\n{\n  uint8_t i;\n  uint32_t Tx_Offset;\n\n  /*  TXn min size = 16 words. (n  : Transmit FIFO index)\n      When a TxFIFO is not used, the Configuration should be as follows:\n          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)\n         --> Txm can use the space allocated for Txn.\n         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)\n         --> Txn should be configured with the minimum space of 16 words\n     The FIFO is used optimally when used TxFIFOs are allocated in the top\n         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.\n     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */\n\n  Tx_Offset = hpcd->Instance->GRXFSIZ;\n\n  if (fifo == 0U)\n  {\n    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset;\n  }\n  else\n  {\n    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;\n    for (i = 0U; i < (fifo - 1U); i++)\n    {\n      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);\n    }\n\n    /* Multiply Tx_Size by 2 to get higher performance */\n    hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Set Rx FIFO\n  * @param  hpcd PCD handle\n  * @param  size Size of Rx fifo\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)\n{\n  hpcd->Instance->GRXFSIZ = size;\n\n  return HAL_OK;\n}\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Activate LPM feature.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  hpcd->lpm_active = 1U;\n  hpcd->LPM_State = LPM_L0;\n  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;\n  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Deactivate LPM feature.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  hpcd->lpm_active = 0U;\n  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;\n  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);\n\n  return HAL_OK;\n}\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Handle BatteryCharging Process.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nvoid HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n  uint32_t tickstart = HAL_GetTick();\n\n  /* Enable DCD : Data Contact Detect */\n  USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;\n\n  /* Wait Detect flag or a timeout is happen*/\n  while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U)\n  {\n    /* Check for the Timeout */\n    if ((HAL_GetTick() - tickstart) > 1000U)\n    {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->BCDCallback(hpcd, PCD_BCD_ERROR);\n#else\n      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n\n      return;\n    }\n  }\n\n  /* Right response got */\n  HAL_Delay(200U);\n\n  /* Check Detect flag*/\n  if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET)\n  {\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n    hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION);\n#else\n    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n  }\n\n  /*Primary detection: checks if connected to Standard Downstream Port\n  (without charging capability) */\n  USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN;\n  HAL_Delay(50U);\n  USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;\n  HAL_Delay(50U);\n\n  if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U)\n  {\n    /* Case of Standard Downstream Port */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n    hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\n#else\n    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* start secondary detection to check connection to Charging Downstream\n    Port or Dedicated Charging Port */\n    USBx->GCCFG &= ~ USB_OTG_GCCFG_PDEN;\n    HAL_Delay(50U);\n    USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;\n    HAL_Delay(50U);\n\n    if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET)\n    {\n      /* case Dedicated Charging Port  */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\n#else\n      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      /* case Charging Downstream Port  */\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n      hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\n#else\n      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n    }\n  }\n\n  /* Battery Charging capability discovery finished */\n  (void)HAL_PCDEx_DeActivateBCD(hpcd);\n\n#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)\n  hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\n#else\n  HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);\n#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  Activate BatteryCharging feature.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\n\n  /* Power Down USB transceiver  */\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\n\n  /* Enable Battery charging */\n  USBx->GCCFG |= USB_OTG_GCCFG_BCDEN;\n\n  hpcd->battery_charging_active = 1U;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Deactivate BatteryCharging feature.\n  * @param  hpcd PCD handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)\n{\n  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;\n\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN);\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN);\n\n  /* Disable Battery charging */\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\n\n  hpcd->battery_charging_active = 0U;\n\n  return HAL_OK;\n}\n#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n/**\n  * @brief  Send LPM message to user layer callback.\n  * @param  hpcd PCD handle\n  * @param  msg LPM message\n  * @retval HAL status\n  */\n__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(msg);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCDEx_LPM_Callback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Send BatteryCharging message to user layer callback.\n  * @param  hpcd PCD handle\n  * @param  msg LPM message\n  * @retval HAL status\n  */\n__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hpcd);\n  UNUSED(msg);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_PCDEx_BCD_Callback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pwr.c\n  * @author  MCD Application Team\n  * @brief   PWR HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of the Power Controller (PWR) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + Peripheral Control functions \n  *         \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup PWR PWR\n  * @brief PWR HAL module driver\n  * @{\n  */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup PWR_Private_Constants\n  * @{\n  */\n  \n/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask\n  * @{\n  */     \n#define PVD_MODE_IT               0x00010000U\n#define PVD_MODE_EVT              0x00020000U\n#define PVD_RISING_EDGE           0x00000001U\n#define PVD_FALLING_EDGE          0x00000002U\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */    \n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n\n/** @defgroup PWR_Exported_Functions PWR Exported Functions\n  * @{\n  */\n\n/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions \n  *  @brief    Initialization and de-initialization functions\n  *\n@verbatim\n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]\n      After reset, the backup domain (RTC registers, RTC backup data \n      registers and backup SRAM) is protected against possible unwanted \n      write accesses. \n      To enable access to the RTC Domain and RTC registers, proceed as follows:\n        (+) Enable the Power Controller (PWR) APB1 interface clock using the\n            __HAL_RCC_PWR_CLK_ENABLE() macro.\n        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.\n \n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.\n  * @retval None\n  */\nvoid HAL_PWR_DeInit(void)\n{\n  __HAL_RCC_PWR_FORCE_RESET();\n  __HAL_RCC_PWR_RELEASE_RESET();\n}\n\n/**\n  * @brief Enables access to the backup domain (RTC registers, RTC \n  *         backup data registers and backup SRAM).\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \n  *         Backup Domain Access should be kept enabled.\n  * @note The following sequence is required to bypass the delay between\n  *         DBP bit programming and the effective enabling  of the backup domain.\n  *         Please check the Errata Sheet for more details under \"Possible delay\n  *         in backup domain protection disabling/enabling after programming the\n  *         DBP bit\" section.\n  * @retval None\n  */\nvoid HAL_PWR_EnableBkUpAccess(void)\n{\n  __IO uint32_t dummyread;\n  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;\n  dummyread = PWR->CR;\n  UNUSED(dummyread);\n}\n\n/**\n  * @brief Disables access to the backup domain (RTC registers, RTC \n  *         backup data registers and backup SRAM).\n  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the \n  *         Backup Domain Access should be kept enabled.\n  * @note The following sequence is required to bypass the delay between\n  *         DBP bit programming and the effective disabling  of the backup domain.\n  *         Please check the Errata Sheet for more details under \"Possible delay\n  *         in backup domain protection disabling/enabling after programming the\n  *         DBP bit\" section.\n  * @retval None\n  */\nvoid HAL_PWR_DisableBkUpAccess(void)\n{\n  __IO uint32_t dummyread;\n  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;\n  dummyread = PWR->CR;\n  UNUSED(dummyread);\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions \n  *  @brief Low Power modes configuration functions \n  *\n@verbatim\n\n ===============================================================================\n                 ##### Peripheral Control functions #####\n ===============================================================================\n     \n    *** PVD configuration ***\n    =========================\n    [..]\n      (+) The PVD is used to monitor the VDD power supply by comparing it to a \n          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).\n      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower \n          than the PVD threshold. This event is internally connected to the EXTI \n          line16 and can generate an interrupt if enabled. This is done through\n          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.\n      (+) The PVD is stopped in Standby mode.\n\n    *** Wake-up pin configuration ***\n    ================================\n    [..]\n      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is \n          forced in input pull-down configuration and is active on rising edges.\n      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.\n\t   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13\n           (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 \n\n    *** Low Power modes configuration ***\n    =====================================\n    [..]\n      The devices feature 3 low-power modes:\n      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.\n      (+) Stop mode: all clocks are stopped, regulator running, regulator \n          in low power mode\n      (+) Standby mode: 1.2V domain powered off.\n   \n   *** Sleep mode ***\n   ==================\n    [..]\n      (+) Entry:\n        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)\n              functions with\n          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\n          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\n      \n      -@@- The Regulator parameter is not used for the STM32F4 family \n              and is kept as parameter just to maintain compatibility with the \n              lower power families (STM32L).\n      (+) Exit:\n        Any peripheral interrupt acknowledged by the nested vectored interrupt \n              controller (NVIC) can wake up the device from Sleep mode.\n\n   *** Stop mode ***\n   =================\n    [..]\n      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,\n      and the HSE RC oscillators are disabled. Internal SRAM and register contents \n      are preserved.\n      The voltage regulator can be configured either in normal or low-power mode.\n      To minimize the consumption In Stop mode, FLASH can be powered off before \n      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.\n      It can be switched on again by software after exiting the Stop mode using\n      the HAL_PWREx_DisableFlashPowerDown() function. \n\n      (+) Entry:\n         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) \n             function with:\n          (++) Main regulator ON.\n          (++) Low Power regulator ON.\n      (+) Exit:\n        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.\n\n   *** Standby mode ***\n   ====================\n    [..]\n    (+)\n      The Standby mode allows to achieve the lowest power consumption. It is based \n      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. \n      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and \n      the HSE oscillator are also switched off. SRAM and register contents are lost \n      except for the RTC registers, RTC backup registers, backup SRAM and Standby \n      circuitry.\n   \n      The voltage regulator is OFF.\n      \n      (++) Entry:\n        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.\n      (++) Exit:\n        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,\n             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.\n\n   *** Auto-wake-up (AWU) from low-power mode ***\n   =============================================\n    [..]\n    \n     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC \n      Wake-up event, a tamper event or a time-stamp event, without depending on \n      an external interrupt (Auto-wake-up mode).\n\n      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes\n       \n        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to \n              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.\n\n        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it \n             is necessary to configure the RTC to detect the tamper or time stamp event using the\n                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.\n                  \n        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to\n              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).\n  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration\n  *        information for the PVD.\n  * @note Refer to the electrical characteristics of your device datasheet for\n  *         more details about the voltage threshold corresponding to each \n  *         detection level.\n  * @retval None\n  */\nvoid HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)\n{\n  /* Check the parameters */\n  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));\n  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));\n  \n  /* Set PLS[7:5] bits according to PVDLevel value */\n  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);\n  \n  /* Clear any previous config. Keep it clear if no event or IT mode is selected */\n  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();\n  __HAL_PWR_PVD_EXTI_DISABLE_IT();\n  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\n  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \n\n  /* Configure interrupt mode */\n  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)\n  {\n    __HAL_PWR_PVD_EXTI_ENABLE_IT();\n  }\n  \n  /* Configure event mode */\n  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)\n  {\n    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();\n  }\n  \n  /* Configure the edge */\n  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)\n  {\n    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\n  }\n  \n  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)\n  {\n    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\n  }\n}\n\n/**\n  * @brief Enables the Power Voltage Detector(PVD).\n  * @retval None\n  */\nvoid HAL_PWR_EnablePVD(void)\n{\n  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief Disables the Power Voltage Detector(PVD).\n  * @retval None\n  */\nvoid HAL_PWR_DisablePVD(void)\n{\n  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief Enables the Wake-up PINx functionality.\n  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.\n  *         This parameter can be one of the following values:\n  *           @arg PWR_WAKEUP_PIN1\n  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices\n  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices\n  * @retval None\n  */\nvoid HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)\n{\n  /* Check the parameter */\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));\n\n  /* Enable the wake up pin */\n  SET_BIT(PWR->CSR, WakeUpPinx);\n}\n\n/**\n  * @brief Disables the Wake-up PINx functionality.\n  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.\n  *         This parameter can be one of the following values:\n  *           @arg PWR_WAKEUP_PIN1\n  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices\n  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices\n  * @retval None\n  */\nvoid HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)\n{\n  /* Check the parameter */\n  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  \n\n  /* Disable the wake up pin */\n  CLEAR_BIT(PWR->CSR, WakeUpPinx);\n}\n  \n/**\n  * @brief Enters Sleep mode.\n  *   \n  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.\n  * \n  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with\n  *       systick interrupt when used as time base for Timeout \n  *                \n  * @param Regulator Specifies the regulator state in SLEEP mode.\n  *            This parameter can be one of the following values:\n  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON\n  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON\n  * @note This parameter is not used for the STM32F4 family and is kept as parameter\n  *       just to maintain compatibility with the lower power families.\n  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction\n  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction\n  * @retval None\n  */\nvoid HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)\n{\n  /* Check the parameters */\n  assert_param(IS_PWR_REGULATOR(Regulator));\n  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));\n\n  /* Clear SLEEPDEEP bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n\n  /* Select SLEEP mode entry -------------------------------------------------*/\n  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)\n  {   \n    /* Request Wait For Interrupt */\n    __WFI();\n  }\n  else\n  {\n    /* Request Wait For Event */\n    __SEV();\n    __WFE();\n    __WFE();\n  }\n}\n\n/**\n  * @brief Enters Stop mode. \n  * @note In Stop mode, all I/O pins keep the same state as in Run mode.\n  * @note When exiting Stop mode by issuing an interrupt or a wake-up event, \n  *         the HSI RC oscillator is selected as system clock.\n  * @note When the voltage regulator operates in low power mode, an additional \n  *         startup delay is incurred when waking up from Stop mode. \n  *         By keeping the internal regulator ON during Stop mode, the consumption \n  *         is higher although the startup time is reduced.    \n  * @param Regulator Specifies the regulator state in Stop mode.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON\n  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON\n  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction\n  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction\n  * @retval None\n  */\nvoid HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\n{\n  /* Check the parameters */\n  assert_param(IS_PWR_REGULATOR(Regulator));\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\n  \n  /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */\n  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);\n  \n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n  \n  /* Select Stop mode entry --------------------------------------------------*/\n  if(STOPEntry == PWR_STOPENTRY_WFI)\n  {   \n    /* Request Wait For Interrupt */\n    __WFI();\n  }\n  else\n  {\n    /* Request Wait For Event */\n    __SEV();\n    __WFE();\n    __WFE();\n  }\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  \n}\n\n/**\n  * @brief Enters Standby mode.\n  * @note In Standby mode, all I/O pins are high impedance except for:\n  *          - Reset pad (still available) \n  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC \n  *            Alarm out, or RTC clock calibration out.\n  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  \n  *          - WKUP pin 1 (PA0) if enabled.       \n  * @retval None\n  */\nvoid HAL_PWR_EnterSTANDBYMode(void)\n{\n  /* Select Standby mode */\n  SET_BIT(PWR->CR, PWR_CR_PDDS);\n\n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));\n  \n  /* This option is used to ensure that store operations are completed */\n#if defined ( __CC_ARM)\n  __force_stores();\n#endif\n  /* Request Wait For Interrupt */\n  __WFI();\n}\n\n/**\n  * @brief This function handles the PWR PVD interrupt request.\n  * @note This API should be called under the PVD_IRQHandler().\n  * @retval None\n  */\nvoid HAL_PWR_PVD_IRQHandler(void)\n{\n  /* Check PWR Exti flag */\n  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)\n  {\n    /* PWR PVD interrupt user callback */\n    HAL_PWR_PVDCallback();\n    \n    /* Clear PWR Exti pending bit */\n    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();\n  }\n}\n\n/**\n  * @brief  PWR PVD interrupt callback\n  * @retval None\n  */\n__weak void HAL_PWR_PVDCallback(void)\n{\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_PWR_PVDCallback could be implemented in the user file\n   */ \n}\n\n/**\n  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. \n  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor \n  *       re-enters SLEEP mode when an interruption handling is over.\n  *       Setting this bit is useful when the processor is expected to run only on\n  *       interruptions handling.         \n  * @retval None\n  */\nvoid HAL_PWR_EnableSleepOnExit(void)\n{\n  /* Set SLEEPONEXIT bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. \n  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor \n  *       re-enters SLEEP mode when an interruption handling is over.          \n  * @retval None\n  */\nvoid HAL_PWR_DisableSleepOnExit(void)\n{\n  /* Clear SLEEPONEXIT bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));\n}\n\n/**\n  * @brief Enables CORTEX M4 SEVONPEND bit. \n  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes \n  *       WFE to wake up when an interrupt moves from inactive to pended.\n  * @retval None\n  */\nvoid HAL_PWR_EnableSEVOnPend(void)\n{\n  /* Set SEVONPEND bit of Cortex System Control Register */\n  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @brief Disables CORTEX M4 SEVONPEND bit. \n  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes \n  *       WFE to wake up when an interrupt moves from inactive to pended.         \n  * @retval None\n  */\nvoid HAL_PWR_DisableSEVOnPend(void)\n{\n  /* Clear SEVONPEND bit of Cortex System Control Register */\n  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));\n}\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */\n\n#endif /* HAL_PWR_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_pwr_ex.c\n  * @author  MCD Application Team\n  * @brief   Extended PWR HAL module driver.\n  *          This file provides firmware functions to manage the following \n  *          functionalities of PWR extension peripheral:           \n  *           + Peripheral Extended features functions\n  *         \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup PWREx PWREx\n  * @brief PWR HAL module driver\n  * @{\n  */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup PWREx_Private_Constants\n  * @{\n  */    \n#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U\n#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U\n#define PWR_BKPREG_TIMEOUT_VALUE     1000U\n#define PWR_VOSRDY_TIMEOUT_VALUE     1000U\n/**\n  * @}\n  */\n\n   \n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup PWREx_Exported_Functions PWREx Exported Functions\n  *  @{\n  */\n\n/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions \n  *  @brief Peripheral Extended features functions \n  *\n@verbatim   \n\n ===============================================================================\n                 ##### Peripheral extended features functions #####\n ===============================================================================\n\n    *** Main and Backup Regulators configuration ***\n    ================================================\n    [..] \n      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from \n          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is \n          retained even in Standby or VBAT mode when the low power backup regulator\n          is enabled. It can be considered as an internal EEPROM when VBAT is \n          always present. You can use the HAL_PWREx_EnableBkUpReg() function to \n          enable the low power backup regulator. \n\n      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) \n          the backup SRAM is powered from VDD which replaces the VBAT power supply to \n          save battery life.\n\n      (+) The backup SRAM is not mass erased by a tamper event. It is read \n          protected to prevent confidential data, such as cryptographic private \n          key, from being accessed. The backup SRAM can be erased only through \n          the Flash interface when a protection level change from level 1 to \n          level 0 is requested. \n      -@- Refer to the description of Read protection (RDP) in the Flash \n          programming manual.\n\n      (+) The main internal regulator can be configured to have a tradeoff between \n          performance and power consumption when the device does not operate at \n          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() \n          macro which configure VOS bit in PWR_CR register\n          \n        Refer to the product datasheets for more details.\n\n    *** FLASH Power Down configuration ****\n    =======================================\n    [..] \n      (+) By setting the FPDS bit in the PWR_CR register by using the \n          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power \n          down mode when the device enters Stop mode. When the Flash memory \n          is in power down mode, an additional startup delay is incurred when \n          waking up from Stop mode.\n          \n           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL \n           is OFF and the HSI or HSE clock source is selected as system clock. \n           The new value programmed is active only when the PLL is ON.\n           When the PLL is OFF, the voltage scale 3 is automatically selected. \n        Refer to the datasheets for more details.\n\n    *** Over-Drive and Under-Drive configuration ****\n    =================================================\n    [..]         \n       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has\n           2 operating modes available:\n        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given \n             voltage scaling (scale 1, scale 2 or scale 3)\n        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a \n            higher frequency than the normal mode for a given voltage scaling (scale 1,  \n            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and\n            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow \n            the sequence described in Reference manual.\n             \n       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator \n           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers \n           and internal SRAM. 2 operating modes are available:\n         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only \n              available when the main regulator or the low power regulator is used in Scale 3 or \n              low voltage mode.\n         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only\n              available when the main regulator or the low power regulator is in low voltage mode.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief Enables the Backup Regulator.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)\n{\n  uint32_t tickstart = 0U;\n\n  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  /* Wait till Backup regulator ready flag is set */  \n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    } \n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief Disables the Backup Regulator.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)\n{\n  uint32_t tickstart = 0U;\n\n  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  /* Wait till Backup regulator ready flag is set */  \n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    } \n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief Enables the Flash Power Down in Stop mode.\n  * @retval None\n  */\nvoid HAL_PWREx_EnableFlashPowerDown(void)\n{\n  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief Disables the Flash Power Down in Stop mode.\n  * @retval None\n  */\nvoid HAL_PWREx_DisableFlashPowerDown(void)\n{\n  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief Return Voltage Scaling Range.\n  * @retval The configured scale for the regulator voltage(VOS bit field).\n  *         The returned value can be one of the following:\n  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode\n  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode\n  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode\n  */  \nuint32_t HAL_PWREx_GetVoltageRange(void)\n{\n  return (PWR->CR & PWR_CR_VOS);\n}\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\n/**\n  * @brief Configures the main internal regulator output voltage.\n  * @param  VoltageScaling specifies the regulator output voltage to achieve\n  *         a tradeoff between performance and power consumption.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\n  *                                               the maximum value of fHCLK = 168 MHz.\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\n  *                                               the maximum value of fHCLK = 144 MHz.\n  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to\n  *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.\n  *        When moving from Range 2 to Range 1, the system frequency can be increased to\n  *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.\n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\n{\n  uint32_t tickstart = 0U;\n  \n  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));\n  \n  /* Enable PWR RCC Clock Peripheral */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  \n  /* Set Range */\n  __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\n  \n  /* Get Start Tick*/\n  tickstart = HAL_GetTick();\n  while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\n  {\n    if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    } \n  }\n\n  return HAL_OK;\n}\n\n#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \\\n      defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \\\n      defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \\\n      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \\\n      defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief Configures the main internal regulator output voltage.\n  * @param  VoltageScaling specifies the regulator output voltage to achieve\n  *         a tradeoff between performance and power consumption.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,\n  *                                               the maximum value of fHCLK is 168 MHz. It can be extended to\n  *                                               180 MHz by activating the over-drive mode.\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,\n  *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,                \n  *                                               168 MHz by activating the over-drive mode.\n  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,\n  *                                               the maximum value of fHCLK is 120 MHz.\n  * @note To update the system clock frequency(SYSCLK):\n  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().\n  *        - Call the HAL_RCC_OscConfig() to configure the PLL.\n  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.\n  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().\n  * @note The scale can be modified only when the HSI or HSE clock source is selected \n  *        as system clock source, otherwise the API returns HAL_ERROR.  \n  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits\n  *       value in the PWR_CR1 register are not taken in account.\n  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.\n  * @note The new voltage scale is active only when the PLL is ON.  \n  * @retval HAL Status\n  */\nHAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)\n{\n  uint32_t tickstart = 0U;\n  \n  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));\n  \n  /* Enable PWR RCC Clock Peripheral */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  \n  /* Check if the PLL is used as system clock or not */\n  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\n  {\n    /* Disable the main PLL */\n    __HAL_RCC_PLL_DISABLE();\n    \n    /* Get Start Tick */\n    tickstart = HAL_GetTick();    \n    /* Wait till PLL is disabled */  \n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    \n    /* Set Range */\n    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);\n    \n    /* Enable the main PLL */\n    __HAL_RCC_PLL_ENABLE();\n    \n    /* Get Start Tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLL is ready */  \n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      } \n    }\n    \n    /* Get Start Tick */\n    tickstart = HAL_GetTick();\n    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))\n    {\n      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      } \n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  return HAL_OK;\n}\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\\\n    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n    defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief Enables Main Regulator low voltage mode.\n  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/\n  *        STM32F413xx/STM32F423xx devices.   \n  * @retval None\n  */\nvoid HAL_PWREx_EnableMainRegulatorLowVoltage(void)\n{\n  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief Disables Main Regulator low voltage mode.\n  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/\n  *        STM32F413xx/STM32F423xxdevices. \n  * @retval None\n  */\nvoid HAL_PWREx_DisableMainRegulatorLowVoltage(void)\n{\n  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief Enables Low Power Regulator low voltage mode.\n  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/\n  *        STM32F413xx/STM32F423xx devices.   \n  * @retval None\n  */\nvoid HAL_PWREx_EnableLowRegulatorLowVoltage(void)\n{\n  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief Disables Low Power Regulator low voltage mode.\n  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/\n  *        STM32F413xx/STM32F423xx  devices.   \n  * @retval None\n  */\nvoid HAL_PWREx_DisableLowRegulatorLowVoltage(void)\n{\n  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;\n}\n\n#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||\n          STM32F413xx || STM32F423xx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Activates the Over-Drive mode.\n  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.\n  *         This mode allows the CPU and the core logic to operate at a higher frequency\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   \n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \n  *         critical tasks and when the system clock source is either HSI or HSE. \n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   \n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)\n{\n  uint32_t tickstart = 0U;\n\n  __HAL_RCC_PWR_CLK_ENABLE();\n  \n  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */\n  __HAL_PWR_OVERDRIVE_ENABLE();\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\n  {\n    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n  \n  /* Enable the Over-drive switch */\n  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\n  {\n    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  } \n  return HAL_OK;\n}\n\n/**\n  * @brief  Deactivates the Over-Drive mode.\n  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.\n  *         This mode allows the CPU and the core logic to operate at a higher frequency\n  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    \n  * @note   It is recommended to enter or exit Over-drive mode when the application is not running \n  *         critical tasks and when the system clock source is either HSI or HSE. \n  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   \n  *         The peripheral clocks must be enabled once the Over-drive mode is activated.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)\n{\n  uint32_t tickstart = 0U;\n  \n  __HAL_RCC_PWR_CLK_ENABLE();\n    \n  /* Disable the Over-drive switch */\n  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();\n  \n  /* Get tick */\n  tickstart = HAL_GetTick();\n \n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))\n  {\n    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  } \n  \n  /* Disable the Over-drive */\n  __HAL_PWR_OVERDRIVE_DISABLE();\n\n  /* Get tick */\n  tickstart = HAL_GetTick();\n\n  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))\n  {\n    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n  \n  return HAL_OK;\n}\n\n/**\n  * @brief  Enters in Under-Drive STOP mode.\n  *  \n  * @note   This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.\n  * \n  * @note    This mode can be selected only when the Under-Drive is already active \n  *   \n  * @note    This mode is enabled only with STOP low power mode.\n  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This \n  *          mode is only available when the main regulator or the low power regulator \n  *          is in low voltage mode\n  *        \n  * @note   If the Under-drive mode was enabled, it is automatically disabled after \n  *         exiting Stop mode. \n  *         When the voltage regulator operates in Under-drive mode, an additional  \n  *         startup delay is induced when waking up from Stop mode.\n  *                    \n  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.\n  *   \n  * @note   When exiting Stop mode by issuing an interrupt or a wake-up event, \n  *         the HSI RC oscillator is selected as system clock.\n  *           \n  * @note   When the voltage regulator operates in low power mode, an additional \n  *         startup delay is incurred when waking up from Stop mode. \n  *         By keeping the internal regulator ON during Stop mode, the consumption \n  *         is higher although the startup time is reduced.\n  *     \n  * @param  Regulator specifies the regulator state in STOP mode.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode \n  *                 and Flash memory in power-down when the device is in Stop under-drive mode\n  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode \n  *                and Flash memory in power-down when the device is in Stop under-drive mode\n  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.\n  *          This parameter can be one of the following values:\n  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction\n  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)\n{\n  uint32_t tmpreg1 = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));\n  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));\n  \n  /* Enable Power ctrl clock */\n  __HAL_RCC_PWR_CLK_ENABLE();\n  /* Enable the Under-drive Mode ---------------------------------------------*/\n  /* Clear Under-drive flag */\n  __HAL_PWR_CLEAR_ODRUDR_FLAG();\n  \n  /* Enable the Under-drive */ \n  __HAL_PWR_UNDERDRIVE_ENABLE();\n\n  /* Select the regulator state in STOP mode ---------------------------------*/\n  tmpreg1 = PWR->CR;\n  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */\n  tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);\n  \n  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */\n  tmpreg1 |= Regulator;\n  \n  /* Store the new value */\n  PWR->CR = tmpreg1;\n  \n  /* Set SLEEPDEEP bit of Cortex System Control Register */\n  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;\n  \n  /* Select STOP mode entry --------------------------------------------------*/\n  if(STOPEntry == PWR_SLEEPENTRY_WFI)\n  {   \n    /* Request Wait For Interrupt */\n    __WFI();\n  }\n  else\n  {\n    /* Request Wait For Event */\n    __WFE();\n  }\n  /* Reset SLEEPDEEP bit of Cortex System Control Register */\n  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);\n\n  return HAL_OK;  \n}\n\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_PWR_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_rcc.c\n  * @author  MCD Application Team\n  * @brief   RCC HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Reset and Clock Control (RCC) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + Peripheral Control functions\n  *\n  @verbatim\n  ==============================================================================\n                      ##### RCC specific features #####\n  ==============================================================================\n    [..]\n      After reset the device is running from Internal High Speed oscillator\n      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache\n      and I-Cache are disabled, and all peripherals are off except internal\n      SRAM, Flash and JTAG.\n      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;\n          all peripherals mapped on these busses are running at HSI speed.\n      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.\n      (+) All GPIOs are in input floating state, except the JTAG pins which\n          are assigned to be used for debug purpose.\n\n    [..]\n      Once the device started from reset, the user application has to:\n      (+) Configure the clock source to be used to drive the System clock\n          (if the application needs higher frequency/performance)\n      (+) Configure the System clock frequency and Flash settings\n      (+) Configure the AHB and APB busses prescalers\n      (+) Enable the clock for the peripheral(s) to be used\n      (+) Configure the clock source(s) for peripherals which clocks are not\n          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)\n\n                      ##### RCC Limitations #####\n  ==============================================================================\n    [..]\n      A delay between an RCC peripheral clock enable and the effective peripheral\n      enabling should be taken into account in order to manage the peripheral read/write\n      from/to registers.\n      (+) This delay depends on the peripheral mapping.\n      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle\n          after the clock enable bit is set on the hardware register\n      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle\n          after the clock enable bit is set on the hardware register\n\n    [..]\n      Implemented Workaround:\n      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been\n          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup RCC RCC\n  * @brief RCC HAL module driver\n  * @{\n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup RCC_Private_Constants\n  * @{\n  */\n\n/* Private macro -------------------------------------------------------------*/\n#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()\n#define MCO1_GPIO_PORT        GPIOA\n#define MCO1_PIN              GPIO_PIN_8\n\n#define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()\n#define MCO2_GPIO_PORT         GPIOC\n#define MCO2_PIN               GPIO_PIN_9\n/**\n  * @}\n  */\n\n/* Private variables ---------------------------------------------------------*/\n/** @defgroup RCC_Private_Variables RCC Private Variables\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n\n/** @defgroup RCC_Exported_Functions RCC Exported Functions\n  *  @{\n  */\n\n/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions\n *  @brief    Initialization and Configuration functions\n *\n@verbatim\n ===============================================================================\n           ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]\n      This section provides functions allowing to configure the internal/external oscillators\n      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1\n       and APB2).\n\n    [..] Internal/external clock and PLL configuration\n         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through\n             the PLL as System clock source.\n\n         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC\n             clock source.\n\n         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or\n             through the PLL as System clock source. Can be used also as RTC clock source.\n\n         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.\n\n         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:\n           (++) The first output is used to generate the high speed system clock (up to 168 MHz)\n           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),\n                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).\n\n         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()\n             and if a HSE clock failure occurs(HSE used directly or through PLL as System\n             clock source), the System clocks automatically switched to HSI and an interrupt\n             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI\n             (Non-Maskable Interrupt) exception vector.\n\n         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL\n             clock (through a configurable prescaler) on PA8 pin.\n\n         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S\n             clock (through a configurable prescaler) on PC9 pin.\n\n    [..] System, AHB and APB busses clocks configuration\n         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,\n             HSE and PLL.\n             The AHB clock (HCLK) is derived from System clock through configurable\n             prescaler and used to clock the CPU, memory and peripherals mapped\n             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived\n             from AHB clock through configurable prescalers and used to clock\n             the peripherals mapped on these busses. You can use\n             \"HAL_RCC_GetSysClockFreq()\" function to retrieve the frequencies of these clocks.\n\n         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum\n             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.\n             Depending on the device voltage range, the maximum frequency should\n             be adapted accordingly (refer to the product datasheets for more details).\n\n         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,\n             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.\n             Depending on the device voltage range, the maximum frequency should\n             be adapted accordingly (refer to the product datasheets for more details).\n\n         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,\n             PCLK2 84 MHz and PCLK1 42 MHz.\n             Depending on the device voltage range, the maximum frequency should\n             be adapted accordingly (refer to the product datasheets for more details).\n\n         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,\n             PCLK2 100 MHz and PCLK1 50 MHz.\n             Depending on the device voltage range, the maximum frequency should\n             be adapted accordingly (refer to the product datasheets for more details).\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Resets the RCC clock configuration to the default reset state.\n  * @note   The default reset state of the clock configuration is given below:\n  *            - HSI ON and used as system clock source\n  *            - HSE and PLL OFF\n  *            - AHB, APB1 and APB2 prescaler set to 1.\n  *            - CSS, MCO1 and MCO2 OFF\n  *            - All interrupts disabled\n  * @note   This function doesn't modify the configuration of the\n  *            - Peripheral clocks\n  *            - LSI, LSE and RTC clocks\n  * @retval HAL status\n  */\n__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)\n{\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the RCC Oscillators according to the specified parameters in the\n  *         RCC_OscInitTypeDef.\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\n  *         contains the configuration information for the RCC Oscillators.\n  * @note   The PLL is not disabled when used as system clock.\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\n  *         supported by this API. User should request a transition to LSE Off\n  *         first and then LSE On or LSE Bypass.\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\n  *         supported by this API. User should request a transition to HSE Off\n  *         first and then HSE On or HSE Bypass.\n  * @retval HAL status\n  */\n__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\n{\n  uint32_t tickstart, pll_config;\n\n  /* Check Null pointer */\n  if(RCC_OscInitStruct == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\n  /*------------------------------- HSE Configuration ------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\n    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\n    {\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\n      {\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Set the new HSE configuration ---------------------------------------*/\n      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\n\n      /* Check the HSE State */\n      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)\n      {\n        /* Get Start Tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n      else\n      {\n        /* Get Start Tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSE is bypassed or disabled */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n  }\n  /*----------------------------- HSI Configuration --------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\n    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\n\n    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\n    {\n      /* When HSI is used as system clock it will not disabled */\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\n      {\n        return HAL_ERROR;\n      }\n      /* Otherwise, just the calibration is allowed */\n      else\n      {\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\n      }\n    }\n    else\n    {\n      /* Check the HSI State */\n      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\n      {\n        /* Enable the Internal High Speed oscillator (HSI). */\n        __HAL_RCC_HSI_ENABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSI is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\n      }\n      else\n      {\n        /* Disable the Internal High Speed oscillator (HSI). */\n        __HAL_RCC_HSI_DISABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSI is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n  }\n  /*------------------------------ LSI Configuration -------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\n\n    /* Check the LSI State */\n    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\n    {\n      /* Enable the Internal Low Speed oscillator (LSI). */\n      __HAL_RCC_LSI_ENABLE();\n\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSI is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n    else\n    {\n      /* Disable the Internal Low Speed oscillator (LSI). */\n      __HAL_RCC_LSI_DISABLE();\n\n      /* Get Start Tick */\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSI is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n  /*------------------------------ LSE Configuration -------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\n  {\n    FlagStatus       pwrclkchanged = RESET;\n\n    /* Check the parameters */\n    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\n\n    /* Update LSE configuration in Backup Domain control register    */\n    /* Requires to enable write access to Backup Domain of necessary */\n    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\n    {\n      __HAL_RCC_PWR_CLK_ENABLE();\n      pwrclkchanged = SET;\n    }\n\n    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\n    {\n      /* Enable write access to Backup domain */\n      SET_BIT(PWR->CR, PWR_CR_DBP);\n\n      /* Wait for Backup domain Write protection disable */\n      tickstart = HAL_GetTick();\n\n      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\n      {\n        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n\n    /* Set the new LSE configuration -----------------------------------------*/\n    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\n    /* Check the LSE State */\n    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\n    {\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSE is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n    else\n    {\n      /* Get Start Tick */\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSE is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n\n    /* Restore clock configuration if changed */\n    if(pwrclkchanged == SET)\n    {\n      __HAL_RCC_PWR_CLK_DISABLE();\n    }\n  }\n  /*-------------------------------- PLL Configuration -----------------------*/\n  /* Check the parameters */\n  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\n  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\n  {\n    /* Check if the PLL is used as system clock or not */\n    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\n    {\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\n      {\n        /* Check the parameters */\n        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\n        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\n        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\n        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\n        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\n\n        /* Disable the main PLL. */\n        __HAL_RCC_PLL_DISABLE();\n\n        /* Get Start Tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n\n        /* Configure the main PLL clock source, multiplication and division factors. */\n        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \\\n                                 RCC_OscInitStruct->PLL.PLLM                                                 | \\\n                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \\\n                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \\\n                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));\n        /* Enable the main PLL. */\n        __HAL_RCC_PLL_ENABLE();\n\n        /* Get Start Tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n      else\n      {\n        /* Disable the main PLL. */\n        __HAL_RCC_PLL_DISABLE();\n\n        /* Get Start Tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    else\n    {\n      /* Check if there is a request to disable the PLL used as System clock source */\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\n      {\n        return HAL_ERROR;\n      }\n      else\n      {\n        /* Do not return HAL_ERROR if request repeats the current configuration */\n        pll_config = RCC->PLLCFGR;\n#if defined (RCC_PLLCFGR_PLLR)\n        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))\n#else\n        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))\n#endif\n        {\n          return HAL_ERROR;\n        }\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified\n  *         parameters in the RCC_ClkInitStruct.\n  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that\n  *         contains the configuration information for the RCC peripheral.\n  * @param  FLatency FLASH Latency, this parameter depend on device selected\n  *\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency\n  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function\n  *\n  * @note   The HSI is used (enabled by hardware) as system clock source after\n  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case\n  *         of failure of the HSE used directly or indirectly as system clock\n  *         (if the Clock Security System CSS is enabled).\n  *\n  * @note   A switch from one clock source to another occurs only if the target\n  *         clock source is ready (clock stable after startup delay or PLL locked).\n  *         If a clock source which is not yet ready is selected, the switch will\n  *         occur when the clock source will be ready.\n  *\n  * @note   Depending on the device voltage range, the software has to set correctly\n  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency\n  *         (for more details refer to section above \"Initialization/de-initialization functions\")\n  * @retval None\n  */\nHAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)\n{\n  uint32_t tickstart;\n\n  /* Check Null pointer */\n  if(RCC_ClkInitStruct == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));\n  assert_param(IS_FLASH_LATENCY(FLatency));\n\n  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)\n    must be correctly programmed according to the frequency of the CPU clock\n    (HCLK) and the supply voltage of the device. */\n\n  /* Increasing the number of wait states because of higher CPU frequency */\n  if(FLatency > __HAL_FLASH_GET_LATENCY())\n  {\n    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\n    __HAL_FLASH_SET_LATENCY(FLatency);\n\n    /* Check that the new number of wait states is taken into account to access the Flash\n    memory by reading the FLASH_ACR register */\n    if(__HAL_FLASH_GET_LATENCY() != FLatency)\n    {\n      return HAL_ERROR;\n    }\n  }\n\n  /*-------------------------- HCLK Configuration --------------------------*/\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)\n  {\n    /* Set the highest APBx dividers in order to ensure that we do not go through\n       a non-spec phase whatever we decrease or increase HCLK. */\n    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\n    {\n      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);\n    }\n\n    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\n    {\n      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));\n    }\n\n    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);\n  }\n\n  /*------------------------- SYSCLK Configuration ---------------------------*/\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)\n  {\n    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));\n\n    /* HSE is selected as System Clock Source */\n    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)\n    {\n      /* Check the HSE ready flag */\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\n      {\n        return HAL_ERROR;\n      }\n    }\n    /* PLL is selected as System Clock Source */\n    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||\n            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))\n    {\n      /* Check the PLL ready flag */\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\n      {\n        return HAL_ERROR;\n      }\n    }\n    /* HSI is selected as System Clock Source */\n    else\n    {\n      /* Check the HSI ready flag */\n      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\n      {\n        return HAL_ERROR;\n      }\n    }\n\n    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);\n\n    /* Get Start Tick */\n    tickstart = HAL_GetTick();\n\n    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))\n    {\n      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n\n  /* Decreasing the number of wait states because of lower CPU frequency */\n  if(FLatency < __HAL_FLASH_GET_LATENCY())\n  {\n     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */\n    __HAL_FLASH_SET_LATENCY(FLatency);\n\n    /* Check that the new number of wait states is taken into account to access the Flash\n    memory by reading the FLASH_ACR register */\n    if(__HAL_FLASH_GET_LATENCY() != FLatency)\n    {\n      return HAL_ERROR;\n    }\n  }\n\n  /*-------------------------- PCLK1 Configuration ---------------------------*/\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)\n  {\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);\n  }\n\n  /*-------------------------- PCLK2 Configuration ---------------------------*/\n  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)\n  {\n    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));\n    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));\n  }\n\n  /* Update the SystemCoreClock global variable */\n  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];\n\n  /* Configure the source of time base considering new system clocks settings */\n  HAL_InitTick (uwTickPrio);\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions\n *  @brief   RCC clocks control functions\n *\n@verbatim\n ===============================================================================\n                      ##### Peripheral Control functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the RCC Clocks\n    frequencies.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).\n  * @note   PA8/PC9 should be configured in alternate function mode.\n  * @param  RCC_MCOx specifies the output direction for the clock source.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).\n  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).\n  * @param  RCC_MCOSource specifies the clock source to output.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source\n  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source\n  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source\n  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx\n  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices\n  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source\n  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source\n  * @param  RCC_MCODiv specifies the MCOx prescaler.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_MCODIV_1: no division applied to MCOx clock\n  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock\n  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock\n  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock\n  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock\n  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have\n  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).\n  * @retval None\n  */\nvoid HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)\n{\n  GPIO_InitTypeDef GPIO_InitStruct;\n  /* Check the parameters */\n  assert_param(IS_RCC_MCO(RCC_MCOx));\n  assert_param(IS_RCC_MCODIV(RCC_MCODiv));\n  /* RCC_MCO1 */\n  if(RCC_MCOx == RCC_MCO1)\n  {\n    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));\n\n    /* MCO1 Clock Enable */\n    __MCO1_CLK_ENABLE();\n\n    /* Configure the MCO1 pin in alternate function mode */\n    GPIO_InitStruct.Pin = MCO1_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\n    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);\n\n    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));\n\n   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */\n#if defined(RCC_CFGR_MCO1EN)\n    __HAL_RCC_MCO1_ENABLE();\n#endif /* RCC_CFGR_MCO1EN */\n  }\n#if defined(RCC_CFGR_MCO2)\n  else\n  {\n    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));\n\n    /* MCO2 Clock Enable */\n    __MCO2_CLK_ENABLE();\n\n    /* Configure the MCO2 pin in alternate function mode */\n    GPIO_InitStruct.Pin = MCO2_PIN;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;\n    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);\n\n    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */\n    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));\n\n   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */\n#if defined(RCC_CFGR_MCO2EN)\n    __HAL_RCC_MCO2_ENABLE();\n#endif /* RCC_CFGR_MCO2EN */\n  }\n#endif /* RCC_CFGR_MCO2 */\n}\n\n/**\n  * @brief  Enables the Clock Security System.\n  * @note   If a failure is detected on the HSE oscillator clock, this oscillator\n  *         is automatically disabled and an interrupt is generated to inform the\n  *         software about the failure (Clock Security System Interrupt, CSSI),\n  *         allowing the MCU to perform rescue operations. The CSSI is linked to\n  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.\n  * @retval None\n  */\nvoid HAL_RCC_EnableCSS(void)\n{\n  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;\n}\n\n/**\n  * @brief  Disables the Clock Security System.\n  * @retval None\n  */\nvoid HAL_RCC_DisableCSS(void)\n{\n  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;\n}\n\n/**\n  * @brief  Returns the SYSCLK frequency\n  *\n  * @note   The system frequency computed by this function is not the real\n  *         frequency in the chip. It is calculated based on the predefined\n  *         constant and the selected clock source:\n  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\n  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\n  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)\n  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *               16 MHz) but the real value may vary depending on the variations\n  *               in voltage and temperature.\n  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *                25 MHz), user has to ensure that HSE_VALUE is same as the real\n  *                frequency of the crystal used. Otherwise, this function may\n  *                have wrong result.\n  *\n  * @note   The result of this function could be not correct when using fractional\n  *         value for HSE crystal.\n  *\n  * @note   This function can be used by the user application to compute the\n  *         baudrate for the communication peripherals or configure other parameters.\n  *\n  * @note   Each time SYSCLK changes, this function must be called to update the\n  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\n  *\n  *\n  * @retval SYSCLK frequency\n  */\n__weak uint32_t HAL_RCC_GetSysClockFreq(void)\n{\n  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;\n  uint32_t sysclockfreq = 0U;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (RCC->CFGR & RCC_CFGR_SWS)\n  {\n    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */\n    {\n      sysclockfreq = HSI_VALUE;\n       break;\n    }\n    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */\n    {\n      sysclockfreq = HSE_VALUE;\n      break;\n    }\n    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */\n    {\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n      SYSCLK = PLL_VCO / PLLP */\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)\n      {\n        /* HSE used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      else\n      {\n        /* HSI used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);\n\n      sysclockfreq = pllvco/pllp;\n      break;\n    }\n    default:\n    {\n      sysclockfreq = HSI_VALUE;\n      break;\n    }\n  }\n  return sysclockfreq;\n}\n\n/**\n  * @brief  Returns the HCLK frequency\n  * @note   Each time HCLK changes, this function must be called to update the\n  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.\n  *\n  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency\n  *         and updated within this function\n  * @retval HCLK frequency\n  */\nuint32_t HAL_RCC_GetHCLKFreq(void)\n{\n  return SystemCoreClock;\n}\n\n/**\n  * @brief  Returns the PCLK1 frequency\n  * @note   Each time PCLK1 changes, this function must be called to update the\n  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.\n  * @retval PCLK1 frequency\n  */\nuint32_t HAL_RCC_GetPCLK1Freq(void)\n{\n  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/\n  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);\n}\n\n/**\n  * @brief  Returns the PCLK2 frequency\n  * @note   Each time PCLK2 changes, this function must be called to update the\n  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.\n  * @retval PCLK2 frequency\n  */\nuint32_t HAL_RCC_GetPCLK2Freq(void)\n{\n  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/\n  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);\n}\n\n/**\n  * @brief  Configures the RCC_OscInitStruct according to the internal\n  * RCC configuration registers.\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\n  * will be configured.\n  * @retval None\n  */\n__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\n{\n  /* Set all possible values for the Oscillator type parameter ---------------*/\n  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\n\n  /* Get the HSE configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\n  }\n  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\n  }\n\n  /* Get the HSI configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\n  {\n    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\n  }\n\n  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\n\n  /* Get the LSE configuration -----------------------------------------------*/\n  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\n  }\n  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\n  }\n\n  /* Get the LSI configuration -----------------------------------------------*/\n  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\n  {\n    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\n  }\n\n  /* Get the PLL configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\n  {\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\n  }\n  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\n  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\n  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);\n  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);\n  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);\n}\n\n/**\n  * @brief  Configures the RCC_ClkInitStruct according to the internal\n  * RCC configuration registers.\n  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that\n  * will be configured.\n  * @param  pFLatency Pointer on the Flash Latency.\n  * @retval None\n  */\nvoid HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)\n{\n  /* Set all possible values for the Clock type parameter --------------------*/\n  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;\n\n  /* Get the SYSCLK configuration --------------------------------------------*/\n  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);\n\n  /* Get the HCLK configuration ----------------------------------------------*/\n  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);\n\n  /* Get the APB1 configuration ----------------------------------------------*/\n  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);\n\n  /* Get the APB2 configuration ----------------------------------------------*/\n  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);\n\n  /* Get the Flash Wait State (Latency) configuration ------------------------*/\n  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);\n}\n\n/**\n  * @brief This function handles the RCC CSS interrupt request.\n  * @note This API should be called under the NMI_Handler().\n  * @retval None\n  */\nvoid HAL_RCC_NMI_IRQHandler(void)\n{\n  /* Check RCC CSSF flag  */\n  if(__HAL_RCC_GET_IT(RCC_IT_CSS))\n  {\n    /* RCC Clock Security System interrupt user callback */\n    HAL_RCC_CSSCallback();\n\n    /* Clear RCC CSS pending bit */\n    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);\n  }\n}\n\n/**\n  * @brief  RCC Clock Security System interrupt callback\n  * @retval None\n  */\n__weak void HAL_RCC_CSSCallback(void)\n{\n  /* NOTE : This function Should not be modified, when the callback is needed,\n            the HAL_RCC_CSSCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_RCC_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_rcc_ex.c\n  * @author  MCD Application Team\n  * @brief   Extension RCC HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities RCC extension peripheral:\n  *           + Extended Peripheral Control functions\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup RCCEx RCCEx\n  * @brief RCCEx HAL module driver\n  * @{\n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup RCCEx_Private_Constants\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions\n  *  @{\n  */\n\n/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions\n *  @brief  Extended Peripheral Control functions\n *\n@verbatim\n ===============================================================================\n                ##### Extended Peripheral Control functions  #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the RCC Clocks\n    frequencies.\n    [..]\n    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to\n        select the RTC clock source; in this case the Backup domain will be reset in\n        order to modify the RTC Clock source, as consequence RTC registers (including\n        the backup registers) and RCC_BDCR register are set to their reset values.\n\n@endverbatim\n  * @{\n  */\n\n#if defined(STM32F446xx)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals\n  *         clocks(I2S, SAI, LTDC RTC and TIM).\n  *\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\n  *         the RTC clock source; in this case the Backup domain will be reset in\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\n  *         the backup registers) and RCC_BDCR register are set to their reset values.\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n  uint32_t plli2sp = 0U;\n  uint32_t plli2sq = 0U;\n  uint32_t plli2sr = 0U;\n  uint32_t pllsaip = 0U;\n  uint32_t pllsaiq = 0U;\n  uint32_t plli2sused = 0U;\n  uint32_t pllsaiused = 0U;\n\n  /* Check the peripheral clock selection parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*------------------------ I2S APB1 configuration --------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));\n\n    /* Configure I2S Clock source */\n    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for I2S */\n    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- I2S APB2 configuration ----------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));\n\n    /* Configure I2S Clock source */\n    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for I2S */\n    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*--------------------------- SAI1 configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));\n\n    /* Configure SAI1 Clock source */\n    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for SAI */\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n    /* Enable the PLLSAI when it's used as clock source for SAI */\n    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)\n    {\n      pllsaiused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*-------------------------- SAI2 configuration ----------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));\n\n    /* Configure SAI2 Clock source */\n    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);\n\n    /* Enable the PLLI2S when it's used as clock source for SAI */\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n    /* Enable the PLLSAI when it's used as clock source for SAI */\n    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)\n    {\n      pllsaiused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------------- RTC configuration --------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- TIM configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    /* Configure Timer Prescaler */\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- FMPI2C1 Configuration -----------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));\n\n    /* Configure the FMPI2C1 clock source */\n    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------ CEC Configuration -------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));\n\n    /* Configure the CEC clock source */\n    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------------- CLK48 Configuration ------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));\n\n    /* Configure the CLK48 clock source */\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\n\n    /* Enable the PLLSAI when it's used as clock source for CLK48 */\n    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)\n    {\n      pllsaiused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------------- SDIO Configuration -------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));\n\n    /* Configure the SDIO clock source */\n    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------ SPDIFRX Configuration ---------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));\n\n    /* Configure the SPDIFRX clock source */\n    __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for SPDIFRX */\n    if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- PLLI2S Configuration ------------------------*/\n  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,\n     I2S on APB2 or SPDIFRX */\n  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\n  {\n    /* Disable the PLLI2S */\n    __HAL_RCC_PLLI2S_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is disabled */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* check for common PLLI2S Parameters */\n    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\n\n    /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n\n      /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */\n      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);\n      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))\n    {\n      /* Check for PLLI2S Parameters */\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n      /* Check for PLLI2S/DIVQ parameters */\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\n\n      /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */\n      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);\n      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);\n\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\n    }\n\n    /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\n      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */\n      plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);\n      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);\n    }\n\n     /*----------------- In Case of PLLI2S is just selected  -----------------*/\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\n    {\n      /* Check for Parameters */\n      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /* Enable the PLLI2S */\n    __HAL_RCC_PLLI2S_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is ready */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------------- PLLSAI Configuration -----------------------*/\n  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */\n  if(pllsaiused == 1U)\n  {\n    /* Disable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is disabled */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* Check the PLLSAI division factors */\n    assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\n\n    /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))\n    {\n      /* check for PLLSAIQ Parameter */\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\n      /* check for PLLSAI/DIVQ Parameter */\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\n\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\n      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);\n\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\n    }\n\n    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/\n    /* In Case of PLLI2S is selected as source clock for CLK48 */\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\n      /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */\n      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n      /* Configure the PLLSAI division factors */\n      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */\n      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);\n    }\n\n    /* Enable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is ready */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal\n  *         RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\\\n                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\\\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\n                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\\\n                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\\\n                                        RCC_PERIPHCLK_SPDIFRX;\n\n  /* Get the PLLI2S Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n  /* Get the PLLSAI Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);\n\n  /* Get the SAI1 clock configuration ----------------------------------------*/\n  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();\n\n  /* Get the SAI2 clock configuration ----------------------------------------*/\n  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();\n\n  /* Get the I2S APB1 clock configuration ------------------------------------*/\n  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();\n\n  /* Get the I2S APB2 clock configuration ------------------------------------*/\n  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();\n\n  /* Get the RTC Clock configuration -----------------------------------------*/\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n  /* Get the CEC clock configuration -----------------------------------------*/\n  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();\n\n  /* Get the FMPI2C1 clock configuration -------------------------------------*/\n  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();\n\n  /* Get the CLK48 clock configuration ----------------------------------------*/\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\n\n  /* Get the SDIO clock configuration ----------------------------------------*/\n  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();\n\n  /* Get the SPDIFRX clock configuration -------------------------------------*/\n  PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();\n\n  /* Get the TIM Prescaler configuration -------------------------------------*/\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n}\n\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock\n  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock\n  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock\n  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  uint32_t tmpreg1 = 0U;\n  /* This variable used to store the SAI clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  /* This variable used to store the SAI clock source */\n  uint32_t saiclocksource = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_SAI1:\n  case RCC_PERIPHCLK_SAI2:\n    {\n      saiclocksource = RCC->DCKCFGR;\n      saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);\n      switch (saiclocksource)\n      {\n      case 0U: /* PLLSAI is the clock source for SAI*/\n        {\n          /* Configure the PLLSAI division factor */\n          /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\n          {\n            /* In Case the PLL Source is HSI (Internal Clock) */\n            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));\n          }\n          else\n          {\n            /* In Case the PLL Source is HSE (External Clock) */\n            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));\n          }\n          /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n          /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\n          tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;\n          frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);\n\n          /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\n          tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);\n          frequency = frequency/(tmpreg1);\n          break;\n        }\n      case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/\n      case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\n          {\n            /* In Case the PLL Source is HSI (Internal Clock) */\n            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* In Case the PLL Source is HSE (External Clock) */\n            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));\n          }\n\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\n          tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;\n          frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);\n\n          /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\n          tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);\n          frequency = frequency/(tmpreg1);\n          break;\n        }\n      case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/\n      case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\n          {\n            /* In Case the PLL Source is HSI (Internal Clock) */\n            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* In Case the PLL Source is HSE (External Clock) */\n            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          /* SAI_CLK_x = PLL_VCO Output/PLLR */\n          tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;\n          frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);\n          break;\n        }\n      case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/\n        {\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)\n          {\n            /* In Case the PLL Source is HSI (Internal Clock) */\n            frequency = (uint32_t)(HSI_VALUE);\n          }\n          else\n          {\n            /* In Case the PLL Source is HSE (External Clock) */\n            frequency = (uint32_t)(HSE_VALUE);\n          }\n          break;\n        }\n      default :\n        {\n          break;\n        }\n      }\n      break;\n    }\n  case RCC_PERIPHCLK_I2S_APB1:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLI2S:\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLR:\n        {\n          /* Configure the PLL division factor R */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));\n          /* I2S_CLK = PLL_VCO Output/PLLR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));\n          break;\n        }\n      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLSRC:\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            frequency = HSE_VALUE;\n          }\n          else\n          {\n            frequency = HSI_VALUE;\n          }\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  case RCC_PERIPHCLK_I2S_APB2:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();\n      switch (srcclk)\n      {\n        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLI2S:\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLR:\n        {\n          /* Configure the PLL division factor R */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));\n          /* I2S_CLK = PLL_VCO Output/PLLR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));\n          break;\n        }\n        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLSRC:\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            frequency = HSE_VALUE;\n          }\n          else\n          {\n            frequency = HSI_VALUE;\n          }\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F446xx */\n\n#if defined(STM32F469xx) || defined(STM32F479xx)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals\n  *         clocks(I2S, SAI, LTDC, RTC and TIM).\n  *\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\n  *         the RTC clock source; in this case the Backup domain will be reset in\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\n  *         the backup registers) and RCC_BDCR register are set to their reset values.\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n  uint32_t pllsaip = 0U;\n  uint32_t pllsaiq = 0U;\n  uint32_t pllsair = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*--------------------------- CLK48 Configuration --------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));\n\n    /* Configure the CLK48 clock source */\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------ SDIO Configuration ------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));\n\n    /* Configure the SDIO clock source */\n    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/\n  /*------------------- Common configuration SAI/I2S -------------------------*/\n  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division\n     factor is common parameters for both peripherals */\n  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))\n  {\n    /* check for Parameters */\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\n\n    /* Disable the PLLI2S */\n    __HAL_RCC_PLLI2S_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is disabled */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /*---------------------- I2S configuration -------------------------------*/\n    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added\n      only for I2S configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /*---------------------------- SAI configuration -------------------------*/\n    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must\n       be added only for SAI configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))\n    {\n      /* Check the PLLI2S division factors */\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\n\n      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\n      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\n    }\n\n    /*----------------- In Case of PLLI2S is just selected  -----------------*/\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\n    {\n      /* Check for Parameters */\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n\n      /* Configure the PLLI2S multiplication and division factors */\n      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /* Enable the PLLI2S */\n    __HAL_RCC_PLLI2S_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is ready */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/\n  /*----------------------- Common configuration SAI/LTDC --------------------*/\n  /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division\n     factor is common parameters for these peripherals */\n  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             ||\n     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&\n      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))\n  {\n    /* Check the PLLSAI division factors */\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\n\n    /* Disable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is disabled */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /*---------------------------- SAI configuration -------------------------*/\n    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must\n       be added only for SAI configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))\n    {\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\n\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\n      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);\n      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\n    }\n\n    /*---------------------------- LTDC configuration ------------------------*/\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\n    {\n      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\n      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\n\n      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */\n      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);\n      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);\n      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\n    }\n\n    /*---------------------------- CLK48 configuration ------------------------*/\n    /* Configure the PLLSAI when it is used as clock source for CLK48 */\n    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&\n       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))\n    {\n      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));\n\n      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);\n    }\n\n    /* Enable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is ready */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- RTC configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- TIM configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal\n  * RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\\\n                                        RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\\\n                                        RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\\\n                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;\n\n  /* Get the PLLI2S Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n  /* Get the PLLSAI Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);\n  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);\n  /* Get the RTC Clock configuration -----------------------------------------*/\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n    /* Get the CLK48 clock configuration -------------------------------------*/\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\n\n  /* Get the SDIO clock configuration ----------------------------------------*/\n  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();\n\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n}\n\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  /* This variable used to store the I2S clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_I2S:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SCLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SCLKSOURCE_PLLI2S:\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F469xx || STM32F479xx */\n\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals\n  *         clocks(I2S, LTDC RTC and TIM).\n  *\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\n  *         the RTC clock source; in this case the Backup domain will be reset in\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\n  *         the backup registers) and RCC_BDCR register are set to their reset values.\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  uint32_t plli2sq = 0U;\n#endif /* STM32F413xx || STM32F423xx */\n  uint32_t plli2sused = 0U;\n\n  /* Check the peripheral clock selection parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*----------------------------------- I2S APB1 configuration ---------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));\n\n    /* Configure I2S Clock source */\n    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for I2S */\n    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------------------- I2S APB2 configuration ---------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));\n\n    /* Configure I2S Clock source */\n    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for I2S */\n    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  /*----------------------- SAI1 Block A configuration -----------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));\n\n    /* Configure SAI1 Clock source */\n    __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for SAI */\n    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)\n    {\n      plli2sused = 1U;\n    }\n    /* Enable the PLLSAI when it's used as clock source for SAI */\n    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)\n    {\n      /* Check for PLL/DIVR parameters */\n      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));\n\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */\n      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------- SAI1 Block B configuration ------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));\n\n    /* Configure SAI1 Clock source */\n    __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);\n    /* Enable the PLLI2S when it's used as clock source for SAI */\n    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)\n    {\n      plli2sused = 1U;\n    }\n    /* Enable the PLLSAI when it's used as clock source for SAI */\n    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)\n    {\n      /* Check for PLL/DIVR parameters */\n      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));\n\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */\n      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n#endif /* STM32F413xx || STM32F423xx */\n\n  /*------------------------------------ RTC configuration -------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------------ TIM configuration -------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    /* Configure Timer Prescaler */\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------------- FMPI2C1 Configuration --------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));\n\n    /* Configure the FMPI2C1 clock source */\n    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------------- CLK48 Configuration ----------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));\n\n    /* Configure the SDIO clock source */\n    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);\n\n    /* Enable the PLLI2S when it's used as clock source for CLK48 */\n    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)\n    {\n      plli2sused = 1U;\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*------------------------------------- SDIO Configuration -----------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));\n\n    /* Configure the SDIO clock source */\n    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*-------------------------------------- PLLI2S Configuration --------------*/\n  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or\n     I2S on APB2*/\n  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))\n  {\n    /* Disable the PLLI2S */\n    __HAL_RCC_PLLI2S_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is disabled */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /* check for common PLLI2S Parameters */\n    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));\n    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\n    /*-------------------- Set the PLL I2S clock -----------------------------*/\n    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);\n\n    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/\n    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||\n       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))\n    {\n      /* Check for PLLI2S Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      /* Check for PLLI2S/DIVR parameters */\n      assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));\n\n      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */\n      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);\n\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);\n    }\n#endif /* STM32F413xx || STM32F423xx */\n\n    /*----------------- In Case of PLLI2S is just selected  ------------------*/\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\n    {\n      /* Check for Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/\n      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /* Enable the PLLI2S */\n    __HAL_RCC_PLLI2S_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is ready */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*-------------------- DFSDM1 clock source configuration -------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));\n\n    /* Configure the DFSDM1 interface clock source */\n    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*-------------------- DFSDM1 Audio clock source configuration -------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));\n\n    /* Configure the DFSDM1 Audio interface clock source */\n    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  /*-------------------- DFSDM2 clock source configuration -------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));\n\n    /* Configure the DFSDM1 interface clock source */\n    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*-------------------- DFSDM2 Audio clock source configuration -------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));\n\n    /* Configure the DFSDM1 Audio interface clock source */\n    __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- LPTIM1 Configuration ------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));\n\n    /* Configure the LPTIM1 clock source */\n    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n#endif /* STM32F413xx || STM32F423xx */\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal\n  *         RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1     | RCC_PERIPHCLK_I2S_APB2 |\\\n                                        RCC_PERIPHCLK_TIM          | RCC_PERIPHCLK_RTC      |\\\n                                        RCC_PERIPHCLK_FMPI2C1      | RCC_PERIPHCLK_CLK48    |\\\n                                        RCC_PERIPHCLK_SDIO         | RCC_PERIPHCLK_DFSDM1   |\\\n                                        RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2   |\\\n                                        RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1   |\\\n                                        RCC_PERIPHCLK_SAIA         | RCC_PERIPHCLK_SAIB;\n#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\\\n                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\\\n                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48    |\\\n                                        RCC_PERIPHCLK_SDIO     | RCC_PERIPHCLK_DFSDM1   |\\\n                                        RCC_PERIPHCLK_DFSDM1_AUDIO;\n#endif /* STM32F413xx || STM32F423xx */\n\n\n\n  /* Get the PLLI2S Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  /* Get the PLL/PLLI2S division factors -------------------------------------*/\n  PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);\n  PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);\n#endif /* STM32F413xx || STM32F423xx */\n\n  /* Get the I2S APB1 clock configuration ------------------------------------*/\n  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();\n\n  /* Get the I2S APB2 clock configuration ------------------------------------*/\n  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();\n\n  /* Get the RTC Clock configuration -----------------------------------------*/\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n  /* Get the FMPI2C1 clock configuration -------------------------------------*/\n  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();\n\n  /* Get the CLK48 clock configuration ---------------------------------------*/\n  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();\n\n  /* Get the SDIO clock configuration ----------------------------------------*/\n  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();\n\n  /* Get the DFSDM1 clock configuration --------------------------------------*/\n  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();\n\n  /* Get the DFSDM1 Audio clock configuration --------------------------------*/\n  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();\n\n#if defined(STM32F413xx) || defined(STM32F423xx)\n  /* Get the DFSDM2 clock configuration --------------------------------------*/\n  PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();\n\n  /* Get the DFSDM2 Audio clock configuration --------------------------------*/\n  PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();\n\n  /* Get the LPTIM1 clock configuration --------------------------------------*/\n  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();\n\n  /* Get the SAI1 Block Aclock configuration ---------------------------------*/\n  PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();\n\n  /* Get the SAI1 Block B clock configuration --------------------------------*/\n  PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();\n#endif /* STM32F413xx || STM32F423xx */\n\n  /* Get the TIM Prescaler configuration -------------------------------------*/\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n}\n\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(I2S..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock\n  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  /* This variable used to store the I2S clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_I2S_APB1:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLI2S:\n        {\n          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* Configure the PLLI2S division factor */\n            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n            {\n              /* Get the I2S source clock value */\n              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n            }\n            else\n            {\n              /* Get the I2S source clock value */\n              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n            }\n          }\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLR:\n        {\n          /* Configure the PLL division factor R */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));\n          /* I2S_CLK = PLL_VCO Output/PLLR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));\n          break;\n        }\n      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */\n      case RCC_I2SAPB1CLKSOURCE_PLLSRC:\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            frequency = HSE_VALUE;\n          }\n          else\n          {\n            frequency = HSI_VALUE;\n          }\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  case RCC_PERIPHCLK_I2S_APB2:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();\n      switch (srcclk)\n      {\n        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLI2S:\n        {\n          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* Configure the PLLI2S division factor */\n            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n            {\n              /* Get the I2S source clock value */\n              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n            }\n            else\n            {\n              /* Get the I2S source clock value */\n              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n            }\n          }\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLR:\n        {\n          /* Configure the PLL division factor R */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));\n          /* I2S_CLK = PLL_VCO Output/PLLR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));\n          break;\n        }\n        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */\n      case RCC_I2SAPB2CLKSOURCE_PLLSRC:\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            frequency = HSE_VALUE;\n          }\n          else\n          {\n            frequency = HSI_VALUE;\n          }\n          break;\n        }\n      /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the\n  *         RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).\n  *\n  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case\n  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup\n  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*---------------------------- RTC configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- TIM configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- FMPI2C1 Configuration -----------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));\n\n    /* Configure the FMPI2C1 clock source */\n    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- LPTIM1 Configuration ------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));\n\n    /* Configure the LPTIM1 clock source */\n    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);\n  }\n\n  /*---------------------------- I2S Configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));\n\n    /* Configure the I2S clock source */\n    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the RCC_OscInitStruct according to the internal\n  * RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  * will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;\n\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n  /* Get the FMPI2C1 clock configuration -------------------------------------*/\n  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();\n\n  /* Get the I2S clock configuration -----------------------------------------*/\n  PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();\n\n\n}\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  /* This variable used to store the I2S clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_I2S:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SAPBCLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */\n      case RCC_I2SAPBCLKSOURCE_PLLR:\n        {\n          /* Configure the PLL division factor R */\n          /* PLL_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLL_VCO Output = PLL_VCO Input * PLLN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));\n          /* I2S_CLK = PLL_VCO Output/PLLR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));\n          break;\n        }\n      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */\n      case RCC_I2SAPBCLKSOURCE_PLLSRC:\n        {\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            frequency = HSE_VALUE;\n          }\n          else\n          {\n            frequency = HSI_VALUE;\n          }\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */\n\n#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified\n  *         parameters in the RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals\n  *         clocks(I2S, SAI, LTDC RTC and TIM).\n  *\n  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select\n  *         the RTC clock source; in this case the Backup domain will be reset in\n  *         order to modify the RTC Clock source, as consequence RTC registers (including\n  *         the backup registers) and RCC_BDCR register are set to their reset values.\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/\n  /*----------------------- Common configuration SAI/I2S ---------------------*/\n  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division\n     factor is common parameters for both peripherals */\n  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))\n  {\n    /* check for Parameters */\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\n\n    /* Disable the PLLI2S */\n    __HAL_RCC_PLLI2S_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is disabled */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /*---------------------------- I2S configuration -------------------------*/\n    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added\n      only for I2S configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))\n    {\n      /* check for Parameters */\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */\n      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /*---------------------------- SAI configuration -------------------------*/\n    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must\n       be added only for SAI configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))\n    {\n      /* Check the PLLI2S division factors */\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));\n\n      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */\n      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n      /* Configure the PLLI2S division factors */\n      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */\n      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */\n      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);\n    }\n\n    /*----------------- In Case of PLLI2S is just selected  -----------------*/\n    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)\n    {\n      /* Check for Parameters */\n      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));\n      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n\n      /* Configure the PLLI2S multiplication and division factors */\n      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);\n    }\n\n    /* Enable the PLLI2S */\n    __HAL_RCC_PLLI2S_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is ready */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/\n  /*----------------------- Common configuration SAI/LTDC --------------------*/\n  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division\n     factor is common parameters for both peripherals */\n  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))\n  {\n    /* Check the PLLSAI division factors */\n    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));\n\n    /* Disable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is disabled */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n    /*---------------------------- SAI configuration -------------------------*/\n    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must\n       be added only for SAI configuration */\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))\n    {\n      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));\n      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));\n\n      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);\n      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);\n    }\n\n    /*---------------------------- LTDC configuration ------------------------*/\n    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))\n    {\n      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));\n      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));\n\n      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */\n      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */\n      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */\n      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */\n      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);\n      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */\n      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);\n    }\n    /* Enable PLLSAI Clock */\n    __HAL_RCC_PLLSAI_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLSAI is ready */\n    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- RTC configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n  /*--------------------------------------------------------------------------*/\n\n  /*---------------------------- TIM configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the PeriphClkInit according to the internal\n  * RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;\n\n  /* Get the PLLI2S Clock configuration -----------------------------------------------*/\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);\n  /* Get the PLLSAI Clock configuration -----------------------------------------------*/\n  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);\n  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);\n  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/\n  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);\n  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);\n  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);\n  /* Get the RTC Clock configuration -----------------------------------------------*/\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n}\n\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  /* This variable used to store the I2S clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_I2S:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SCLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SCLKSOURCE_PLLI2S:\n        {\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */\n\n#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\\\n    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n/**\n  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the\n  *         RCC_PeriphCLKInitTypeDef.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).\n  *\n  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case\n  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup\n  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tickstart = 0U;\n  uint32_t tmpreg1 = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));\n\n  /*---------------------------- I2S configuration ---------------------------*/\n  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||\n     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))\n  {\n    /* check for Parameters */\n    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));\n    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));\n#if defined(STM32F411xE)\n    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));\n#endif /* STM32F411xE */\n    /* Disable the PLLI2S */\n    __HAL_RCC_PLLI2S_DISABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is disabled */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n\n#if defined(STM32F411xE)\n    /* Configure the PLLI2S division factors */\n    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);\n#else\n    /* Configure the PLLI2S division factors */\n    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */\n    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */\n    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);\n#endif /* STM32F411xE */\n\n    /* Enable the PLLI2S */\n    __HAL_RCC_PLLI2S_ENABLE();\n    /* Get tick */\n    tickstart = HAL_GetTick();\n    /* Wait till PLLI2S is ready */\n    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n      {\n        /* return in case of Timeout detected */\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n\n  /*---------------------------- RTC configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))\n  {\n    /* Check for RTC Parameters used to output RTCCLK */\n    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));\n\n    /* Enable Power Clock*/\n    __HAL_RCC_PWR_CLK_ENABLE();\n\n    /* Enable write access to Backup domain */\n    PWR->CR |= PWR_CR_DBP;\n\n    /* Get tick */\n    tickstart = HAL_GetTick();\n\n    while((PWR->CR & PWR_CR_DBP) == RESET)\n    {\n      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)\n      {\n        return HAL_TIMEOUT;\n      }\n    }\n    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */\n    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);\n    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))\n    {\n      /* Store the content of BDCR register before the reset of Backup Domain */\n      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));\n      /* RTC Clock selection can be changed only if the Backup Domain is reset */\n      __HAL_RCC_BACKUPRESET_FORCE();\n      __HAL_RCC_BACKUPRESET_RELEASE();\n      /* Restore the Content of BDCR register */\n      RCC->BDCR = tmpreg1;\n\n      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */\n      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))\n      {\n        /* Get tick */\n        tickstart = HAL_GetTick();\n\n        /* Wait till LSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);\n  }\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n  /*---------------------------- TIM configuration ---------------------------*/\n  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))\n  {\n    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);\n  }\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the RCC_OscInitStruct according to the internal\n  * RCC configuration registers.\n  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that\n  * will be configured.\n  * @retval None\n  */\nvoid HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)\n{\n  uint32_t tempreg;\n\n  /* Set all possible values for the extended clock type parameter------------*/\n  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;\n\n  /* Get the PLLI2S Clock configuration --------------------------------------*/\n  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);\n  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);\n#if defined(STM32F411xE)\n  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);\n#endif /* STM32F411xE */\n  /* Get the RTC Clock configuration -----------------------------------------*/\n  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);\n  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));\n\n#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)\n  /* Get the TIM Prescaler configuration -------------------------------------*/\n  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;\n  }\n  else\n  {\n    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;\n  }\n#endif /* STM32F401xC || STM32F401xE || STM32F411xE */\n}\n\n/**\n  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)\n  * @note   Return 0 if peripheral clock identifier not managed by this API\n  * @param  PeriphClk Peripheral clock identifier\n  *         This parameter can be one of the following values:\n  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock\n  * @retval Frequency in KHz\n  */\nuint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)\n{\n  /* This variable used to store the I2S clock frequency (value in Hz) */\n  uint32_t frequency = 0U;\n  /* This variable used to store the VCO Input (value in Hz) */\n  uint32_t vcoinput = 0U;\n  uint32_t srcclk = 0U;\n  /* This variable used to store the VCO Output (value in Hz) */\n  uint32_t vcooutput = 0U;\n  switch (PeriphClk)\n  {\n  case RCC_PERIPHCLK_I2S:\n    {\n      /* Get the current I2S source */\n      srcclk = __HAL_RCC_GET_I2S_SOURCE();\n      switch (srcclk)\n      {\n      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */\n      case RCC_I2SCLKSOURCE_EXT:\n        {\n          /* Set the I2S clock to the external clock  value */\n          frequency = EXTERNAL_CLOCK_VALUE;\n          break;\n        }\n      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */\n      case RCC_I2SCLKSOURCE_PLLI2S:\n        {\n#if defined(STM32F411xE)\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));\n          }\n#else\n          /* Configure the PLLI2S division factor */\n          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */\n          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n          else\n          {\n            /* Get the I2S source clock value */\n            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));\n          }\n#endif /* STM32F411xE */\n          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */\n          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));\n          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */\n          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));\n          break;\n        }\n        /* Clock not enabled for I2S*/\n      default:\n        {\n          frequency = 0U;\n          break;\n        }\n      }\n      break;\n    }\n  }\n  return frequency;\n}\n#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Select LSE mode\n  *\n  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.\n  *\n  * @param  Mode specifies the LSE mode.\n  *          This parameter can be one of the following values:\n  *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection\n  *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection\n  * @retval None\n  */\nvoid HAL_RCCEx_SelectLSEMode(uint8_t Mode)\n{\n  /* Check the parameters */\n  assert_param(IS_RCC_LSE_MODE(Mode));\n  if(Mode == RCC_LSE_HIGHDRIVE_MODE)\n  {\n    SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n  }\n  else\n  {\n    CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);\n  }\n}\n\n#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions\n *  @brief  Extended Clock management functions\n *\n@verbatim   \n ===============================================================================\n                ##### Extended clock management functions  #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the \n    activation or deactivation of PLLI2S, PLLSAI.\n@endverbatim\n  * @{\n  */\n\n#if defined(RCC_PLLI2S_SUPPORT)\n/**\n  * @brief  Enable PLLI2S.\n  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that\n  *         contains the configuration information for the PLLI2S\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)\n{\n  uint32_t tickstart;\n\n  /* Check for parameters */\n  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));\n  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));\n#if defined(RCC_PLLI2SCFGR_PLLI2SM)\n  assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));\n#endif /* RCC_PLLI2SCFGR_PLLI2SM */\n#if defined(RCC_PLLI2SCFGR_PLLI2SP)\n  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));\n#endif /* RCC_PLLI2SCFGR_PLLI2SP */\n#if defined(RCC_PLLI2SCFGR_PLLI2SQ)\n  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));\n#endif /* RCC_PLLI2SCFGR_PLLI2SQ */\n\n  /* Disable the PLLI2S */\n  __HAL_RCC_PLLI2S_DISABLE();\n\n  /* Wait till PLLI2S is disabled */\n  tickstart = HAL_GetTick();\n  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n  /* Configure the PLLI2S division factors */\n#if defined(STM32F446xx)\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */\n  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\n  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \\\n                          PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\n#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\\\n      defined(STM32F413xx) || defined(STM32F423xx)\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/\n  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\n  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \\\n                          PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\n#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\\\n      defined(STM32F469xx) || defined(STM32F479xx)\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */\n  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\n  __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);\n#elif defined(STM32F411xE)\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\n  __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);\n#else\n  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */\n  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */\n  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);\n#endif /* STM32F446xx */\n\n  /* Enable the PLLI2S */\n  __HAL_RCC_PLLI2S_ENABLE();\n\n  /* Wait till PLLI2S is ready */\n  tickstart = HAL_GetTick();\n  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n return HAL_OK;\n}\n\n/**\n  * @brief  Disable PLLI2S.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)\n{\n  uint32_t tickstart;\n\n  /* Disable the PLLI2S */\n  __HAL_RCC_PLLI2S_DISABLE();\n\n  /* Wait till PLLI2S is disabled */\n  tickstart = HAL_GetTick();\n  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\n  {\n    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n  return HAL_OK;\n}\n\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n/**\n  * @brief  Enable PLLSAI.\n  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that\n  *         contains the configuration information for the PLLSAI\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)\n{\n  uint32_t tickstart;\n\n  /* Check for parameters */\n  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));\n  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));\n#if defined(RCC_PLLSAICFGR_PLLSAIM)\n  assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));\n#endif /* RCC_PLLSAICFGR_PLLSAIM */\n#if defined(RCC_PLLSAICFGR_PLLSAIP)\n  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));\n#endif /* RCC_PLLSAICFGR_PLLSAIP */\n#if defined(RCC_PLLSAICFGR_PLLSAIR)\n  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));\n#endif /* RCC_PLLSAICFGR_PLLSAIR */\n\n  /* Disable the PLLSAI */\n  __HAL_RCC_PLLSAI_DISABLE();\n\n  /* Wait till PLLSAI is disabled */\n  tickstart = HAL_GetTick();\n  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n  /* Configure the PLLSAI division factors */\n#if defined(STM32F446xx)\n  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */\n  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\n  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\n  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */\n  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \\\n                          PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);\n#elif defined(STM32F469xx) || defined(STM32F479xx)\n  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */\n  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */\n  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\n  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */\n  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \\\n                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);\n#else\n  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */\n  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */\n  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */\n  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);\n#endif /* STM32F446xx */\n\n  /* Enable the PLLSAI */\n  __HAL_RCC_PLLSAI_ENABLE();\n\n  /* Wait till PLLSAI is ready */\n  tickstart = HAL_GetTick();\n  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)\n  {\n    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n return HAL_OK;\n}\n\n/**\n  * @brief  Disable PLLSAI.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)\n{\n  uint32_t tickstart;\n\n  /* Disable the PLLSAI */\n  __HAL_RCC_PLLSAI_DISABLE();\n\n  /* Wait till PLLSAI is disabled */\n  tickstart = HAL_GetTick();\n  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)\n  {\n    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\n    {\n      /* return in case of Timeout detected */\n      return HAL_TIMEOUT;\n    }\n  }\n\n  return HAL_OK;\n}\n\n#endif /* RCC_PLLSAI_SUPPORT */\n\n/**\n  * @}\n  */\n\n#if defined(STM32F446xx)\n/**\n  * @brief  Returns the SYSCLK frequency\n  *\n  * @note   This function implementation is valid only for STM32F446xx devices.\n  * @note   This function add the PLL/PLLR System clock source\n  *\n  * @note   The system frequency computed by this function is not the real\n  *         frequency in the chip. It is calculated based on the predefined\n  *         constant and the selected clock source:\n  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)\n  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)\n  * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)\n  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.\n  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *               16 MHz) but the real value may vary depending on the variations\n  *               in voltage and temperature.\n  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value\n  *                25 MHz), user has to ensure that HSE_VALUE is same as the real\n  *                frequency of the crystal used. Otherwise, this function may\n  *                have wrong result.\n  *\n  * @note   The result of this function could be not correct when using fractional\n  *         value for HSE crystal.\n  *\n  * @note   This function can be used by the user application to compute the\n  *         baudrate for the communication peripherals or configure other parameters.\n  *\n  * @note   Each time SYSCLK changes, this function must be called to update the\n  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.\n  *\n  *\n  * @retval SYSCLK frequency\n  */\nuint32_t HAL_RCC_GetSysClockFreq(void)\n{\n  uint32_t pllm = 0U;\n  uint32_t pllvco = 0U;\n  uint32_t pllp = 0U;\n  uint32_t pllr = 0U;\n  uint32_t sysclockfreq = 0U;\n\n  /* Get SYSCLK source -------------------------------------------------------*/\n  switch (RCC->CFGR & RCC_CFGR_SWS)\n  {\n    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */\n    {\n      sysclockfreq = HSI_VALUE;\n       break;\n    }\n    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */\n    {\n      sysclockfreq = HSE_VALUE;\n      break;\n    }\n    case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */\n    {\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n      SYSCLK = PLL_VCO / PLLP */\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)\n      {\n        /* HSE used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      else\n      {\n        /* HSI used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);\n\n      sysclockfreq = pllvco/pllp;\n      break;\n    }\n    case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */\n    {\n      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN\n      SYSCLK = PLL_VCO / PLLR */\n      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;\n      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)\n      {\n        /* HSE used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      else\n      {\n        /* HSI used as PLL clock source */\n        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);\n      }\n      pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);\n\n      sysclockfreq = pllvco/pllr;\n      break;\n    }\n    default:\n    {\n      sysclockfreq = HSI_VALUE;\n      break;\n    }\n  }\n  return sysclockfreq;\n}\n#endif /* STM32F446xx */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @brief  Resets the RCC clock configuration to the default reset state.\n  * @note   The default reset state of the clock configuration is given below:\n  *            - HSI ON and used as system clock source\n  *            - HSE, PLL, PLLI2S and PLLSAI OFF\n  *            - AHB, APB1 and APB2 prescaler set to 1.\n  *            - CSS, MCO1 and MCO2 OFF\n  *            - All interrupts disabled\n  * @note   This function doesn't modify the configuration of the\n  *            - Peripheral clocks\n  *            - LSI, LSE and RTC clocks\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCC_DeInit(void)\n{\n  uint32_t tickstart;\n\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Set HSION bit to the reset value */\n  SET_BIT(RCC->CR, RCC_CR_HSION);\n\n  /* Wait till HSI is ready */\n  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n\n  /* Set HSITRIM[4:0] bits to the reset value */\n  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);\n\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Reset CFGR register */\n  CLEAR_REG(RCC->CFGR);\n\n  /* Wait till clock switch is ready */\n  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Clear HSEON, HSEBYP and CSSON bits */\n  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);\n\n  /* Wait till HSE is disabled */\n  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Clear PLLON bit */\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);\n\n  /* Wait till PLL is disabled */\n  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n\n#if defined(RCC_PLLI2S_SUPPORT)\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Reset PLLI2SON bit */\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);\n\n  /* Wait till PLLI2S is disabled */\n  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n#endif /* RCC_PLLI2S_SUPPORT */\n\n#if defined(RCC_PLLSAI_SUPPORT)\n  /* Get Start Tick */\n  tickstart = HAL_GetTick();\n\n  /* Reset PLLSAI bit */\n  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);\n\n  /* Wait till PLLSAI is disabled */\n  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)\n  {\n    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)\n    {\n      return HAL_TIMEOUT;\n    }\n  }\n#endif /* RCC_PLLSAI_SUPPORT */\n\n  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */\n#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \\\n    defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)\n  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;\n#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)\n  RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;\n#else\n  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;\n#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */\n\n  /* Reset PLLI2SCFGR register to default value */\n#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \\\n    defined(STM32F423xx) || defined(STM32F446xx)\n  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;\n#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\n  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;\n#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;\n#elif defined(STM32F411xE)\n  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;\n#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */\n\n  /* Reset PLLSAICFGR register */\n#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)\n  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;\n#elif defined(STM32F446xx)\n  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;\n#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */\n\n  /* Disable all interrupts */\n  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);\n\n#if defined(RCC_CIR_PLLI2SRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);\n#endif /* RCC_CIR_PLLI2SRDYIE */\n\n#if defined(RCC_CIR_PLLSAIRDYIE)\n  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);\n#endif /* RCC_CIR_PLLSAIRDYIE */\n\n  /* Clear all interrupt flags */\n  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);\n\n#if defined(RCC_CIR_PLLI2SRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);\n#endif /* RCC_CIR_PLLI2SRDYC */\n\n#if defined(RCC_CIR_PLLSAIRDYC)\n  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);\n#endif /* RCC_CIR_PLLSAIRDYC */\n\n  /* Clear LSION bit */\n  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);\n\n  /* Reset all CSR flags */\n  SET_BIT(RCC->CSR, RCC_CSR_RMVF);\n\n  /* Update the SystemCoreClock global variable */\n  SystemCoreClock = HSI_VALUE;\n\n  /* Adapt Systick interrupt period */\n  if(HAL_InitTick(uwTickPrio) != HAL_OK)\n  {\n    return HAL_ERROR;\n  }\n  else\n  {\n    return HAL_OK;\n  }\n}\n\n#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\\\n    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n/**\n  * @brief  Initializes the RCC Oscillators according to the specified parameters in the\n  *         RCC_OscInitTypeDef.\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that\n  *         contains the configuration information for the RCC Oscillators.\n  * @note   The PLL is not disabled when used as system clock.\n  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not\n  *         supported by this API. User should request a transition to LSE Off\n  *         first and then LSE On or LSE Bypass.\n  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not\n  *         supported by this API. User should request a transition to HSE Off\n  *         first and then HSE On or HSE Bypass.\n  * @note   This function add the PLL/PLLR factor management during PLL configuration this feature\n  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\n{\n  uint32_t tickstart, pll_config;\n\n  /* Check Null pointer */\n  if(RCC_OscInitStruct == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));\n  /*------------------------------- HSE Configuration ------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));\n    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */\n#if defined(STM32F446xx)\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\n#else\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))\n#endif /* STM32F446xx */\n    {\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))\n      {\n        return HAL_ERROR;\n      }\n    }\n    else\n    {\n      /* Set the new HSE configuration ---------------------------------------*/\n      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);\n\n      /* Check the HSE State */\n      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)\n      {\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSE is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n      else\n      {\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSE is bypassed or disabled */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n  }\n  /*----------------------------- HSI Configuration --------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));\n    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));\n\n    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */\n#if defined(STM32F446xx)\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\n#else\n    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\\\n      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))\n#endif /* STM32F446xx */\n    {\n      /* When HSI is used as system clock it will not disabled */\n      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))\n      {\n        return HAL_ERROR;\n      }\n      /* Otherwise, just the calibration is allowed */\n      else\n      {\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\n      }\n    }\n    else\n    {\n      /* Check the HSI State */\n      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)\n      {\n        /* Enable the Internal High Speed oscillator (HSI). */\n        __HAL_RCC_HSI_ENABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSI is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n\n        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/\n        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);\n      }\n      else\n      {\n        /* Disable the Internal High Speed oscillator (HSI). */\n        __HAL_RCC_HSI_DISABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till HSI is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n  }\n  /*------------------------------ LSI Configuration -------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)\n  {\n    /* Check the parameters */\n    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));\n\n    /* Check the LSI State */\n    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)\n    {\n      /* Enable the Internal Low Speed oscillator (LSI). */\n      __HAL_RCC_LSI_ENABLE();\n\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSI is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n    else\n    {\n      /* Disable the Internal Low Speed oscillator (LSI). */\n      __HAL_RCC_LSI_DISABLE();\n\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSI is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n  /*------------------------------ LSE Configuration -------------------------*/\n  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)\n  {\n    FlagStatus       pwrclkchanged = RESET;\n\n    /* Check the parameters */\n    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));\n\n    /* Update LSE configuration in Backup Domain control register    */\n    /* Requires to enable write access to Backup Domain of necessary */\n    if(__HAL_RCC_PWR_IS_CLK_DISABLED())\n    {\n      __HAL_RCC_PWR_CLK_ENABLE();\n      pwrclkchanged = SET;\n    }\n\n    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\n    {\n      /* Enable write access to Backup domain */\n      SET_BIT(PWR->CR, PWR_CR_DBP);\n\n      /* Wait for Backup domain Write protection disable */\n      tickstart = HAL_GetTick();\n\n      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))\n      {\n        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n\n    /* Set the new LSE configuration -----------------------------------------*/\n    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);\n    /* Check the LSE State */\n    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)\n    {\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSE is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n    else\n    {\n      /* Get Start Tick*/\n      tickstart = HAL_GetTick();\n\n      /* Wait till LSE is ready */\n      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)\n      {\n        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)\n        {\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n\n    /* Restore clock configuration if changed */\n    if(pwrclkchanged == SET)\n    {\n      __HAL_RCC_PWR_CLK_DISABLE();\n    }\n  }\n  /*-------------------------------- PLL Configuration -----------------------*/\n  /* Check the parameters */\n  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));\n  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)\n  {\n    /* Check if the PLL is used as system clock or not */\n    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)\n    {\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)\n      {\n        /* Check the parameters */\n        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));\n        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));\n        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));\n        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));\n        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));\n        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));\n\n        /* Disable the main PLL. */\n        __HAL_RCC_PLL_DISABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n\n        /* Configure the main PLL clock source, multiplication and division factors. */\n        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \\\n                                 RCC_OscInitStruct->PLL.PLLM                                                 | \\\n                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)                       | \\\n                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)        | \\\n                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)                       | \\\n                                 (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));\n        /* Enable the main PLL. */\n        __HAL_RCC_PLL_ENABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n      else\n      {\n        /* Disable the main PLL. */\n        __HAL_RCC_PLL_DISABLE();\n\n        /* Get Start Tick*/\n        tickstart = HAL_GetTick();\n\n        /* Wait till PLL is ready */\n        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)\n        {\n          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)\n          {\n            return HAL_TIMEOUT;\n          }\n        }\n      }\n    }\n    else\n    {\n      /* Check if there is a request to disable the PLL used as System clock source */\n      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)\n      {\n        return HAL_ERROR;\n      }\n      else\n      {\n        /* Do not return HAL_ERROR if request repeats the current configuration */\n        pll_config = RCC->PLLCFGR;\n#if defined (RCC_PLLCFGR_PLLR)\n        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))\n#else\n        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||\n            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))\n#endif\n        {\n          return HAL_ERROR;\n        }\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the RCC_OscInitStruct according to the internal\n  * RCC configuration registers.\n  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.\n  *\n  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.\n  * @note   This function add the PLL/PLLR factor management\n  * @retval None\n  */\nvoid HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)\n{\n  /* Set all possible values for the Oscillator type parameter ---------------*/\n  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;\n\n  /* Get the HSE configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;\n  }\n  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;\n  }\n\n  /* Get the HSI configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)\n  {\n    RCC_OscInitStruct->HSIState = RCC_HSI_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;\n  }\n\n  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);\n\n  /* Get the LSE configuration -----------------------------------------------*/\n  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;\n  }\n  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;\n  }\n\n  /* Get the LSI configuration -----------------------------------------------*/\n  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)\n  {\n    RCC_OscInitStruct->LSIState = RCC_LSI_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;\n  }\n\n  /* Get the PLL configuration -----------------------------------------------*/\n  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)\n  {\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;\n  }\n  else\n  {\n    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;\n  }\n  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);\n  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);\n  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);\n  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);\n  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);\n  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);\n}\n#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */\n\n#endif /* HAL_RCC_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_spi.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_spi.c\n  * @author  MCD Application Team\n  * @brief   SPI HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      The SPI HAL driver can be used as follows:\n\n      (#) Declare a SPI_HandleTypeDef handle structure, for example:\n          SPI_HandleTypeDef  hspi;\n\n      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:\n          (##) Enable the SPIx interface clock\n          (##) SPI pins configuration\n              (+++) Enable the clock for the SPI GPIOs\n              (+++) Configure these SPI pins as alternate function push-pull\n          (##) NVIC configuration if you need to use interrupt process\n              (+++) Configure the SPIx interrupt priority\n              (+++) Enable the NVIC SPI IRQ handle\n          (##) DMA Configuration if you need to use DMA process\n              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel\n              (+++) Enable the DMAx clock\n              (+++) Configure the DMA handle parameters\n              (+++) Configure the DMA Tx or Rx Stream/Channel\n              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle\n              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel\n\n      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS\n          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.\n\n      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:\n          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)\n              by calling the customized HAL_SPI_MspInit() API.\n     [..]\n       Circular mode restriction:\n      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:\n          (##) Master 2Lines RxOnly\n          (##) Master 1Line Rx\n      (#) The CRC feature is not managed when the DMA circular mode is enabled\n      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs\n          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks\n     [..]\n       Master Receive mode restriction:\n      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or\n          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI\n          does not initiate a new transfer the following procedure has to be respected:\n          (##) HAL_SPI_DeInit()\n          (##) HAL_SPI_Init()\n     [..]\n       Callback registration:\n\n      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U\n          allows the user to configure dynamically the driver callbacks.\n          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.\n\n          Function HAL_SPI_RegisterCallback() allows to register following callbacks:\n            (++) TxCpltCallback        : SPI Tx Completed callback\n            (++) RxCpltCallback        : SPI Rx Completed callback\n            (++) TxRxCpltCallback      : SPI TxRx Completed callback\n            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback\n            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback\n            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\n            (++) ErrorCallback         : SPI Error callback\n            (++) AbortCpltCallback     : SPI Abort callback\n            (++) MspInitCallback       : SPI Msp Init callback\n            (++) MspDeInitCallback     : SPI Msp DeInit callback\n          This function takes as parameters the HAL peripheral handle, the Callback ID\n          and a pointer to the user callback function.\n\n\n      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default\n          weak function.\n          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,\n          and the Callback ID.\n          This function allows to reset following callbacks:\n            (++) TxCpltCallback        : SPI Tx Completed callback\n            (++) RxCpltCallback        : SPI Rx Completed callback\n            (++) TxRxCpltCallback      : SPI TxRx Completed callback\n            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback\n            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback\n            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback\n            (++) ErrorCallback         : SPI Error callback\n            (++) AbortCpltCallback     : SPI Abort callback\n            (++) MspInitCallback       : SPI Msp Init callback\n            (++) MspDeInitCallback     : SPI Msp DeInit callback\n\n       [..]\n       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET\n       all callbacks are set to the corresponding weak functions:\n       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().\n       Exception done for MspInit and MspDeInit functions that are\n       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when\n       these callbacks are null (not registered beforehand).\n       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()\n       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.\n\n       [..]\n       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.\n       Exception done MspInit/MspDeInit functions that can be registered/unregistered\n       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,\n       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.\n       Then, the user first registers the MspInit/MspDeInit user callbacks\n       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()\n       or HAL_SPI_Init() function.\n\n       [..]\n       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or\n       not defined, the callback registering feature is not available\n       and weak (surcharged) callbacks are used.\n\n     [..]\n       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,\n       the following table resume the max SPI frequency reached with data size 8bits/16bits,\n         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.\n\n  @endverbatim\n\n  Additional table :\n\n       DataSize = SPI_DATASIZE_8BIT:\n       +----------------------------------------------------------------------------------------------+\n       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\n       | Process | Transfer mode  |---------------------|----------------------|----------------------|\n       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\n       |==============================================================================================|\n       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |\n       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n       |=========|================|==========|==========|===========|==========|===========|==========|\n       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |\n       |=========|================|==========|==========|===========|==========|===========|==========|\n       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|\n       +----------------------------------------------------------------------------------------------+\n\n       DataSize = SPI_DATASIZE_16BIT:\n       +----------------------------------------------------------------------------------------------+\n       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |\n       | Process | Transfer mode  |---------------------|----------------------|----------------------|\n       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |\n       |==============================================================================================|\n       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |\n       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |\n       |=========|================|==========|==========|===========|==========|===========|==========|\n       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |\n       |=========|================|==========|==========|===========|==========|===========|==========|\n       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |\n       |         |----------------|----------|----------|-----------|----------|-----------|----------|\n       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |\n       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|\n       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|\n       +----------------------------------------------------------------------------------------------+\n       @note The max SPI frequency depend on SPI data size (8bits, 16bits),\n             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).\n       @note\n            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()\n            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()\n            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()\n\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup SPI SPI\n  * @brief SPI HAL module driver\n  * @{\n  */\n#ifdef HAL_SPI_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private defines -----------------------------------------------------------*/\n/** @defgroup SPI_Private_Constants SPI Private Constants\n  * @{\n  */\n#define SPI_DEFAULT_TIMEOUT 100U\n#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs             */\n/**\n  * @}\n  */\n\n/* Private macros ------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/** @defgroup SPI_Private_Functions SPI Private Functions\n  * @{\n  */\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\n                                                       uint32_t Timeout, uint32_t Tickstart);\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);\n#if (USE_SPI_CRC != 0U)\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);\n#endif /* USE_SPI_CRC */\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);\n/**\n  * @}\n  */\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup SPI_Exported_Functions SPI Exported Functions\n  * @{\n  */\n\n/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions\n  *  @brief    Initialization and Configuration functions\n  *\n@verbatim\n ===============================================================================\n              ##### Initialization and de-initialization functions #####\n ===============================================================================\n    [..]  This subsection provides a set of functions allowing to initialize and\n          de-initialize the SPIx peripheral:\n\n      (+) User must implement HAL_SPI_MspInit() function in which he configures\n          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).\n\n      (+) Call the function HAL_SPI_Init() to configure the selected device with\n          the selected configuration:\n        (++) Mode\n        (++) Direction\n        (++) Data Size\n        (++) Clock Polarity and Phase\n        (++) NSS Management\n        (++) BaudRate Prescaler\n        (++) FirstBit\n        (++) TIMode\n        (++) CRC Calculation\n        (++) CRC Polynomial if CRC enabled\n\n      (+) Call the function HAL_SPI_DeInit() to restore the default configuration\n          of the selected SPIx peripheral.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initialize the SPI according to the specified parameters\n  *         in the SPI_InitTypeDef and initialize the associated handle.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)\n{\n  /* Check the SPI handle allocation */\n  if (hspi == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\n  assert_param(IS_SPI_MODE(hspi->Init.Mode));\n  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));\n  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));\n  assert_param(IS_SPI_NSS(hspi->Init.NSS));\n  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\n  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));\n  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));\n  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)\n  {\n    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));\n    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));\n\n    if (hspi->Init.Mode == SPI_MODE_MASTER)\n    {\n      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\n    }\n    else\n    {\n      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */\n      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;\n    }\n  }\n  else\n  {\n    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));\n\n    /* Force polarity and phase to TI protocaol requirements */\n    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;\n    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;\n  }\n#if (USE_SPI_CRC != 0U)\n  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));\n  }\n#else\n  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n#endif /* USE_SPI_CRC */\n\n  if (hspi->State == HAL_SPI_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    hspi->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    /* Init the SPI Callback settings */\n    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */\n    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */\n    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */\n    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */\n    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */\n    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\n    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */\n    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */\n\n    if (hspi->MspInitCallback == NULL)\n    {\n      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */\n    }\n\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\n    hspi->MspInitCallback(hspi);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC... */\n    HAL_SPI_MspInit(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n\n  hspi->State = HAL_SPI_STATE_BUSY;\n\n  /* Disable the selected SPI peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/\n  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,\n  Communication speed, First bit and CRC calculation state */\n  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |\n                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |\n                                  (hspi->Init.DataSize & SPI_CR1_DFF) |\n                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |\n                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |\n                                  (hspi->Init.NSS & SPI_CR1_SSM) |\n                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |\n                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |\n                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));\n\n  /* Configure : NSS management, TI Mode */\n  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));\n\n#if (USE_SPI_CRC != 0U)\n  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/\n  /* Configure : CRC Polynomial */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));\n  }\n#endif /* USE_SPI_CRC */\n\n#if defined(SPI_I2SCFGR_I2SMOD)\n  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */\n  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);\n#endif /* SPI_I2SCFGR_I2SMOD */\n\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  hspi->State     = HAL_SPI_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  De-Initialize the SPI peripheral.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)\n{\n  /* Check the SPI handle allocation */\n  if (hspi == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check SPI Instance parameter */\n  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));\n\n  hspi->State = HAL_SPI_STATE_BUSY;\n\n  /* Disable the SPI Peripheral Clock */\n  __HAL_SPI_DISABLE(hspi);\n\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  if (hspi->MspDeInitCallback == NULL)\n  {\n    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */\n  }\n\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\n  hspi->MspDeInitCallback(hspi);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */\n  HAL_SPI_MspDeInit(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n\n  hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  hspi->State = HAL_SPI_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initialize the SPI MSP.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_MspInit should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  De-Initialize the SPI MSP.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_MspDeInit should be implemented in the user file\n   */\n}\n\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n/**\n  * @brief  Register a User SPI Callback\n  *         To be used instead of the weak predefined callback\n  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\n  *                the configuration information for the specified SPI.\n  * @param  CallbackID ID of the callback to be registered\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,\n                                           pSPI_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  if (HAL_SPI_STATE_READY == hspi->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_SPI_TX_COMPLETE_CB_ID :\n        hspi->TxCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_RX_COMPLETE_CB_ID :\n        hspi->RxCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\n        hspi->TxRxCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\n        hspi->TxHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\n        hspi->RxHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\n        hspi->TxRxHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_ERROR_CB_ID :\n        hspi->ErrorCallback = pCallback;\n        break;\n\n      case HAL_SPI_ABORT_CB_ID :\n        hspi->AbortCpltCallback = pCallback;\n        break;\n\n      case HAL_SPI_MSPINIT_CB_ID :\n        hspi->MspInitCallback = pCallback;\n        break;\n\n      case HAL_SPI_MSPDEINIT_CB_ID :\n        hspi->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_SPI_STATE_RESET == hspi->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_SPI_MSPINIT_CB_ID :\n        hspi->MspInitCallback = pCallback;\n        break;\n\n      case HAL_SPI_MSPDEINIT_CB_ID :\n        hspi->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hspi);\n  return status;\n}\n\n/**\n  * @brief  Unregister an SPI Callback\n  *         SPI callback is redirected to the weak predefined callback\n  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains\n  *                the configuration information for the specified SPI.\n  * @param  CallbackID ID of the callback to be unregistered\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  if (HAL_SPI_STATE_READY == hspi->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_SPI_TX_COMPLETE_CB_ID :\n        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */\n        break;\n\n      case HAL_SPI_RX_COMPLETE_CB_ID :\n        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */\n        break;\n\n      case HAL_SPI_TX_RX_COMPLETE_CB_ID :\n        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */\n        break;\n\n      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :\n        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */\n        break;\n\n      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :\n        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */\n        break;\n\n      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :\n        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */\n        break;\n\n      case HAL_SPI_ERROR_CB_ID :\n        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */\n        break;\n\n      case HAL_SPI_ABORT_CB_ID :\n        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */\n        break;\n\n      case HAL_SPI_MSPINIT_CB_ID :\n        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\n        break;\n\n      case HAL_SPI_MSPDEINIT_CB_ID :\n        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_SPI_STATE_RESET == hspi->State)\n  {\n    switch (CallbackID)\n    {\n      case HAL_SPI_MSPINIT_CB_ID :\n        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */\n        break;\n\n      case HAL_SPI_MSPDEINIT_CB_ID :\n        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */\n        break;\n\n      default :\n        /* Update the error code */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(hspi);\n  return status;\n}\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Exported_Functions_Group2 IO operation functions\n  *  @brief   Data transfers functions\n  *\n@verbatim\n  ==============================================================================\n                      ##### IO operation functions #####\n ===============================================================================\n [..]\n    This subsection provides a set of functions allowing to manage the SPI\n    data transfers.\n\n    [..] The SPI supports master and slave mode :\n\n    (#) There are two modes of transfer:\n       (++) Blocking mode: The communication is performed in polling mode.\n            The HAL status of all data processing is returned by the same function\n            after finishing transfer.\n       (++) No-Blocking mode: The communication is performed using Interrupts\n            or DMA, These APIs return the HAL status.\n            The end of the data processing will be indicated through the\n            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when\n            using DMA mode.\n            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks\n            will be executed respectively at the end of the transmit or Receive process\n            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected\n\n    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)\n        exist for 1Line (simplex) and 2Lines (full duplex) modes.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Transmit an amount of data in blocking mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @param  Size amount of data to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  uint32_t tickstart;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n  uint16_t initial_TxXferCount;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n  initial_TxXferCount = Size;\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n  hspi->TxISR       = NULL;\n  hspi->RxISR       = NULL;\n\n  /* Configure communication direction : 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Transmit data in 16 Bit mode */\n  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n  {\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\n    {\n      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n      hspi->pTxBuffPtr += sizeof(uint16_t);\n      hspi->TxXferCount--;\n    }\n    /* Transmit data in 16 Bit mode */\n    while (hspi->TxXferCount > 0U)\n    {\n      /* Wait until TXE flag is set to send data */\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\n      {\n        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n        hspi->pTxBuffPtr += sizeof(uint16_t);\n        hspi->TxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n  /* Transmit data in 8 Bit mode */\n  else\n  {\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\n    {\n      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\n      hspi->pTxBuffPtr += sizeof(uint8_t);\n      hspi->TxXferCount--;\n    }\n    while (hspi->TxXferCount > 0U)\n    {\n      /* Wait until TXE flag is set to send data */\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))\n      {\n        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\n        hspi->pTxBuffPtr += sizeof(uint8_t);\n        hspi->TxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\n  {\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    errorcode = HAL_ERROR;\n  }\n\nerror:\n  hspi->State = HAL_SPI_STATE_READY;\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in blocking mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @param  Size amount of data to be received\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n#if (USE_SPI_CRC != 0U)\n  __IO uint32_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n  uint32_t tickstart;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n    /* this is done to handle the CRCNEXT before the latest data */\n    hspi->RxXferCount--;\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Configure communication direction: 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_RX(hspi);\n  }\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Receive data in 8 Bit mode */\n  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)\n  {\n    /* Transfer loop */\n    while (hspi->RxXferCount > 0U)\n    {\n      /* Check the RXNE flag */\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\n      {\n        /* read the received data */\n        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\n        hspi->pRxBuffPtr += sizeof(uint8_t);\n        hspi->RxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n  else\n  {\n    /* Transfer loop */\n    while (hspi->RxXferCount > 0U)\n    {\n      /* Check the RXNE flag */\n      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))\n      {\n        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\n        hspi->pRxBuffPtr += sizeof(uint16_t);\n        hspi->RxXferCount--;\n      }\n      else\n      {\n        /* Timeout management */\n        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))\n        {\n          errorcode = HAL_TIMEOUT;\n          goto error;\n        }\n      }\n    }\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Handle the CRC Transmission */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    /* freeze the CRC before the latest data */\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n\n    /* Read the latest data */\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      /* the latest data has not been received */\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n\n    /* Receive last data in 16 Bit mode */\n    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n    {\n      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\n    }\n    /* Receive last data in 8 Bit mode */\n    else\n    {\n      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;\n    }\n\n    /* Wait the CRC data */\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n\n    /* Read CRC to Flush DR and RXNE flag */\n    tmpreg = READ_REG(hspi->Instance->DR);\n    /* To avoid GCC warning */\n    UNUSED(tmpreg);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)\n  {\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Check if CRC error occurred */\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    errorcode = HAL_ERROR;\n  }\n\nerror :\n  hspi->State = HAL_SPI_STATE_READY;\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in blocking mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData pointer to transmission data buffer\n  * @param  pRxData pointer to reception data buffer\n  * @param  Size amount of data to be sent and received\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,\n                                          uint32_t Timeout)\n{\n#if (USE_SPI_CRC != 0U)\n  __IO uint32_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n  uint16_t             initial_TxXferCount;\n  uint32_t             tmp_mode;\n  HAL_SPI_StateTypeDef tmp_state;\n  uint32_t             tickstart;\n\n  /* Variable used to alternate Rx and Tx during transfer */\n  uint32_t             txallowed = 1U;\n  HAL_StatusTypeDef    errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* Init temporary variables */\n  tmp_state           = hspi->State;\n  tmp_mode            = hspi->Init.Mode;\n  initial_TxXferCount = Size;\n\n  if (!((tmp_state == HAL_SPI_STATE_READY) || \\\n        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\n  hspi->RxXferCount = Size;\n  hspi->RxXferSize  = Size;\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\n  hspi->TxXferCount = Size;\n  hspi->TxXferSize  = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Transmit and Receive data in 16 Bit mode */\n  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)\n  {\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\n    {\n      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n      hspi->pTxBuffPtr += sizeof(uint16_t);\n      hspi->TxXferCount--;\n    }\n    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\n    {\n      /* Check TXE flag */\n      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\n      {\n        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n        hspi->pTxBuffPtr += sizeof(uint16_t);\n        hspi->TxXferCount--;\n        /* Next Data is a reception (Rx). Tx not allowed */\n        txallowed = 0U;\n\n#if (USE_SPI_CRC != 0U)\n        /* Enable CRC Transmission */\n        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n        {\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n        }\n#endif /* USE_SPI_CRC */\n      }\n\n      /* Check RXNE flag */\n      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\n      {\n        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;\n        hspi->pRxBuffPtr += sizeof(uint16_t);\n        hspi->RxXferCount--;\n        /* Next Data is a Transmission (Tx). Tx is allowed */\n        txallowed = 1U;\n      }\n      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))\n      {\n        errorcode = HAL_TIMEOUT;\n        goto error;\n      }\n    }\n  }\n  /* Transmit and Receive data in 8 Bit mode */\n  else\n  {\n    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))\n    {\n      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);\n      hspi->pTxBuffPtr += sizeof(uint8_t);\n      hspi->TxXferCount--;\n    }\n    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))\n    {\n      /* Check TXE flag */\n      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))\n      {\n        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\n        hspi->pTxBuffPtr++;\n        hspi->TxXferCount--;\n        /* Next Data is a reception (Rx). Tx not allowed */\n        txallowed = 0U;\n\n#if (USE_SPI_CRC != 0U)\n        /* Enable CRC Transmission */\n        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n        {\n          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n        }\n#endif /* USE_SPI_CRC */\n      }\n\n      /* Wait until RXNE flag is reset */\n      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))\n      {\n        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;\n        hspi->pRxBuffPtr++;\n        hspi->RxXferCount--;\n        /* Next Data is a Transmission (Tx). Tx is allowed */\n        txallowed = 1U;\n      }\n      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))\n      {\n        errorcode = HAL_TIMEOUT;\n        goto error;\n      }\n    }\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Read CRC from DR to close CRC calculation process */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    /* Wait until TXE flag */\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)\n    {\n      /* Error on the CRC reception */\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      errorcode = HAL_TIMEOUT;\n      goto error;\n    }\n    /* Read CRC */\n    tmpreg = READ_REG(hspi->Instance->DR);\n    /* To avoid GCC warning */\n    UNUSED(tmpreg);\n  }\n\n  /* Check if CRC error occurred */\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    /* Clear CRC Flag */\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n\n    errorcode = HAL_ERROR;\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)\n  {\n    errorcode = HAL_ERROR;\n    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n    goto error;\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\nerror :\n  hspi->State = HAL_SPI_STATE_READY;\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @param  Size amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n  hspi->RxISR       = NULL;\n\n  /* Set the function for IT treatment */\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\n  {\n    hspi->TxISR = SPI_TxISR_16BIT;\n  }\n  else\n  {\n    hspi->TxISR = SPI_TxISR_8BIT;\n  }\n\n  /* Configure communication direction : 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Enable TXE and ERR interrupt */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\n\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @param  Size amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pTxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n  hspi->TxISR       = NULL;\n\n  /* Set the function for IT treatment */\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\n  {\n    hspi->RxISR = SPI_RxISR_16BIT;\n  }\n  else\n  {\n    hspi->RxISR = SPI_RxISR_8BIT;\n  }\n\n  /* Configure communication direction : 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_RX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Enable TXE and ERR interrupt */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  /* Note : The SPI must be enabled after unlocking current process\n            to avoid the risk of SPI interrupt handle execution before current\n            process unlock */\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData pointer to transmission data buffer\n  * @param  pRxData pointer to reception data buffer\n  * @param  Size amount of data to be sent and received\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)\n{\n  uint32_t             tmp_mode;\n  HAL_SPI_StateTypeDef tmp_state;\n  HAL_StatusTypeDef    errorcode = HAL_OK;\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  /* Init temporary variables */\n  tmp_state           = hspi->State;\n  tmp_mode            = hspi->Init.Mode;\n\n  if (!((tmp_state == HAL_SPI_STATE_READY) || \\\n        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Set the function for IT treatment */\n  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)\n  {\n    hspi->RxISR     = SPI_2linesRxISR_16BIT;\n    hspi->TxISR     = SPI_2linesTxISR_16BIT;\n  }\n  else\n  {\n    hspi->RxISR     = SPI_2linesRxISR_8BIT;\n    hspi->TxISR     = SPI_2linesTxISR_8BIT;\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Enable TXE, RXNE and ERR interrupt */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit an amount of data in non-blocking mode with DMA.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @param  Size amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check tx dma handle */\n  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_TX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->pRxBuffPtr  = (uint8_t *)NULL;\n  hspi->TxISR       = NULL;\n  hspi->RxISR       = NULL;\n  hspi->RxXferSize  = 0U;\n  hspi->RxXferCount = 0U;\n\n  /* Configure communication direction : 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_TX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Set the SPI TxDMA Half transfer complete callback */\n  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;\n\n  /* Set the SPI TxDMA transfer complete callback */\n  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;\n\n  /* Set the DMA error callback */\n  hspi->hdmatx->XferErrorCallback = SPI_DMAError;\n\n  /* Set the DMA AbortCpltCallback */\n  hspi->hdmatx->XferAbortCallback = NULL;\n\n  /* Enable the Tx DMA Stream/Channel */\n  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,\n                                 hspi->TxXferCount))\n  {\n    /* Update SPI error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n    errorcode = HAL_ERROR;\n\n    hspi->State = HAL_SPI_STATE_READY;\n    goto error;\n  }\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Enable the SPI Error Interrupt Bit */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\n\n  /* Enable Tx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Receive an amount of data in non-blocking mode with DMA.\n  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pData pointer to data buffer\n  * @note   When the CRC feature is enabled the pData Length must be Size + 1.\n  * @param  Size amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check rx dma handle */\n  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\n\n  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_RX;\n\n    /* Check tx dma handle */\n    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\n\n    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */\n    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);\n  }\n\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  if (hspi->State != HAL_SPI_STATE_READY)\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Set the transaction information */\n  hspi->State       = HAL_SPI_STATE_BUSY_RX;\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pRxBuffPtr  = (uint8_t *)pData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /*Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n  hspi->TxXferSize  = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Configure communication direction : 1Line */\n  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)\n  {\n    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */\n    __HAL_SPI_DISABLE(hspi);\n    SPI_1LINE_RX(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Set the SPI RxDMA Half transfer complete callback */\n  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\n\n  /* Set the SPI Rx DMA transfer complete callback */\n  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;\n\n  /* Set the DMA error callback */\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\n\n  /* Set the DMA AbortCpltCallback */\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Enable the Rx DMA Stream/Channel  */\n  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,\n                                 hspi->RxXferCount))\n  {\n    /* Update SPI error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n    errorcode = HAL_ERROR;\n\n    hspi->State = HAL_SPI_STATE_READY;\n    goto error;\n  }\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n\n  /* Enable the SPI Error Interrupt Bit */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\n\n  /* Enable Rx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\nerror:\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  pTxData pointer to transmission data buffer\n  * @param  pRxData pointer to reception data buffer\n  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1\n  * @param  Size amount of data to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,\n                                              uint16_t Size)\n{\n  uint32_t             tmp_mode;\n  HAL_SPI_StateTypeDef tmp_state;\n  HAL_StatusTypeDef errorcode = HAL_OK;\n\n  /* Check rx & tx dma handles */\n  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));\n  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));\n\n  /* Check Direction parameter */\n  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));\n\n  /* Process locked */\n  __HAL_LOCK(hspi);\n\n  /* Init temporary variables */\n  tmp_state           = hspi->State;\n  tmp_mode            = hspi->Init.Mode;\n\n  if (!((tmp_state == HAL_SPI_STATE_READY) ||\n        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))\n  {\n    errorcode = HAL_BUSY;\n    goto error;\n  }\n\n  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))\n  {\n    errorcode = HAL_ERROR;\n    goto error;\n  }\n\n  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */\n  if (hspi->State != HAL_SPI_STATE_BUSY_RX)\n  {\n    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;\n  }\n\n  /* Set the transaction information */\n  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;\n  hspi->pTxBuffPtr  = (uint8_t *)pTxData;\n  hspi->TxXferSize  = Size;\n  hspi->TxXferCount = Size;\n  hspi->pRxBuffPtr  = (uint8_t *)pRxData;\n  hspi->RxXferSize  = Size;\n  hspi->RxXferCount = Size;\n\n  /* Init field not used in handle to zero */\n  hspi->RxISR       = NULL;\n  hspi->TxISR       = NULL;\n\n#if (USE_SPI_CRC != 0U)\n  /* Reset CRC Calculation */\n  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n  {\n    SPI_RESET_CRC(hspi);\n  }\n#endif /* USE_SPI_CRC */\n\n  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */\n  if (hspi->State == HAL_SPI_STATE_BUSY_RX)\n  {\n    /* Set the SPI Rx DMA Half transfer complete callback */\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;\n    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;\n  }\n  else\n  {\n    /* Set the SPI Tx/Rx DMA Half transfer complete callback */\n    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;\n    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;\n  }\n\n  /* Set the DMA error callback */\n  hspi->hdmarx->XferErrorCallback = SPI_DMAError;\n\n  /* Set the DMA AbortCpltCallback */\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Enable the Rx DMA Stream/Channel  */\n  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,\n                                 hspi->RxXferCount))\n  {\n    /* Update SPI error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n    errorcode = HAL_ERROR;\n\n    hspi->State = HAL_SPI_STATE_READY;\n    goto error;\n  }\n\n  /* Enable Rx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\n  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing\n  is performed in DMA reception complete callback  */\n  hspi->hdmatx->XferHalfCpltCallback = NULL;\n  hspi->hdmatx->XferCpltCallback     = NULL;\n  hspi->hdmatx->XferErrorCallback    = NULL;\n  hspi->hdmatx->XferAbortCallback    = NULL;\n\n  /* Enable the Tx DMA Stream/Channel  */\n  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,\n                                 hspi->TxXferCount))\n  {\n    /* Update SPI error code */\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n    errorcode = HAL_ERROR;\n\n    hspi->State = HAL_SPI_STATE_READY;\n    goto error;\n  }\n\n  /* Check if the SPI is already enabled */\n  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)\n  {\n    /* Enable SPI peripheral */\n    __HAL_SPI_ENABLE(hspi);\n  }\n  /* Enable the SPI Error Interrupt Bit */\n  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));\n\n  /* Enable Tx DMA Request */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\nerror :\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n  return errorcode;\n}\n\n/**\n  * @brief  Abort ongoing transfer (blocking mode).\n  * @param  hspi SPI handle.\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\n  *         started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable SPI Interrupts (depending of transfer direction)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)\n{\n  HAL_StatusTypeDef errorcode;\n  __IO uint32_t count;\n  __IO uint32_t resetcount;\n\n  /* Initialized local variable  */\n  errorcode = HAL_OK;\n  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n  count = resetcount;\n\n  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\n  {\n    hspi->TxISR = SPI_AbortTx_ISR;\n    /* Wait HAL_SPI_STATE_ABORT state */\n    do\n    {\n      if (count == 0U)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n        break;\n      }\n      count--;\n    } while (hspi->State != HAL_SPI_STATE_ABORT);\n    /* Reset Timeout Counter */\n    count = resetcount;\n  }\n\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\n  {\n    hspi->RxISR = SPI_AbortRx_ISR;\n    /* Wait HAL_SPI_STATE_ABORT state */\n    do\n    {\n      if (count == 0U)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n        break;\n      }\n      count--;\n    } while (hspi->State != HAL_SPI_STATE_ABORT);\n    /* Reset Timeout Counter */\n    count = resetcount;\n  }\n\n  /* Disable the SPI DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\n  {\n    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */\n    if (hspi->hdmatx != NULL)\n    {\n      /* Set the SPI DMA Abort callback :\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\n      hspi->hdmatx->XferAbortCallback = NULL;\n\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\n      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)\n      {\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\n      }\n\n      /* Disable Tx DMA Request */\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));\n\n      /* Wait until TXE flag is set */\n      do\n      {\n        if (count == 0U)\n        {\n          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n          break;\n        }\n        count--;\n      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n    }\n  }\n\n  /* Disable the SPI DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\n  {\n    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */\n    if (hspi->hdmarx != NULL)\n    {\n      /* Set the SPI DMA Abort callback :\n      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */\n      hspi->hdmarx->XferAbortCallback = NULL;\n\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\n      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)\n      {\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\n      }\n\n      /* Disable peripheral */\n      __HAL_SPI_DISABLE(hspi);\n\n      /* Disable Rx DMA Request */\n      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));\n    }\n  }\n  /* Reset Tx and Rx transfer counters */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Check error during Abort procedure */\n  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\n  {\n    /* return HAL_Error in case of error during Abort procedure */\n    errorcode = HAL_ERROR;\n  }\n  else\n  {\n    /* Reset errorCode */\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  }\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->state to ready */\n  hspi->State = HAL_SPI_STATE_READY;\n\n  return errorcode;\n}\n\n/**\n  * @brief  Abort ongoing transfer (Interrupt mode).\n  * @param  hspi SPI handle.\n  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),\n  *         started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable SPI Interrupts (depending of transfer direction)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  *           - At abort completion, call user abort complete callback\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)\n{\n  HAL_StatusTypeDef errorcode;\n  uint32_t abortcplt ;\n  __IO uint32_t count;\n  __IO uint32_t resetcount;\n\n  /* Initialized local variable  */\n  errorcode = HAL_OK;\n  abortcplt = 1U;\n  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n  count = resetcount;\n\n  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);\n\n  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))\n  {\n    hspi->TxISR = SPI_AbortTx_ISR;\n    /* Wait HAL_SPI_STATE_ABORT state */\n    do\n    {\n      if (count == 0U)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n        break;\n      }\n      count--;\n    } while (hspi->State != HAL_SPI_STATE_ABORT);\n    /* Reset Timeout Counter */\n    count = resetcount;\n  }\n\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))\n  {\n    hspi->RxISR = SPI_AbortRx_ISR;\n    /* Wait HAL_SPI_STATE_ABORT state */\n    do\n    {\n      if (count == 0U)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n        break;\n      }\n      count--;\n    } while (hspi->State != HAL_SPI_STATE_ABORT);\n    /* Reset Timeout Counter */\n    count = resetcount;\n  }\n\n  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised\n     before any call to DMA Abort functions */\n  /* DMA Tx Handle is valid */\n  if (hspi->hdmatx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\n       Otherwise, set it to NULL */\n    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\n    {\n      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;\n    }\n    else\n    {\n      hspi->hdmatx->XferAbortCallback = NULL;\n    }\n  }\n  /* DMA Rx Handle is valid */\n  if (hspi->hdmarx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\n       Otherwise, set it to NULL */\n    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\n    {\n      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;\n    }\n    else\n    {\n      hspi->hdmarx->XferAbortCallback = NULL;\n    }\n  }\n\n  /* Disable the SPI DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))\n  {\n    /* Abort the SPI DMA Tx Stream/Channel */\n    if (hspi->hdmatx != NULL)\n    {\n      /* Abort DMA Tx Handle linked to SPI Peripheral */\n      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)\n      {\n        hspi->hdmatx->XferAbortCallback = NULL;\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n  }\n  /* Disable the SPI DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))\n  {\n    /* Abort the SPI DMA Rx Stream/Channel */\n    if (hspi->hdmarx != NULL)\n    {\n      /* Abort DMA Rx Handle linked to SPI Peripheral */\n      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)\n      {\n        hspi->hdmarx->XferAbortCallback = NULL;\n        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;\n      }\n      else\n      {\n        abortcplt = 0U;\n      }\n    }\n  }\n\n  if (abortcplt == 1U)\n  {\n    /* Reset Tx and Rx transfer counters */\n    hspi->RxXferCount = 0U;\n    hspi->TxXferCount = 0U;\n\n    /* Check error during Abort procedure */\n    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)\n    {\n      /* return HAL_Error in case of error during Abort procedure */\n      errorcode = HAL_ERROR;\n    }\n    else\n    {\n      /* Reset errorCode */\n      hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n    }\n\n    /* Clear the Error flags in the SR register */\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n    __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n    /* Restore hspi->State to Ready */\n    hspi->State = HAL_SPI_STATE_READY;\n\n    /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    hspi->AbortCpltCallback(hspi);\n#else\n    HAL_SPI_AbortCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n\n  return errorcode;\n}\n\n/**\n  * @brief  Pause the DMA Transfer.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)\n{\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Disable the SPI DMA Tx & Rx requests */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Resume the DMA Transfer.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)\n{\n  /* Process Locked */\n  __HAL_LOCK(hspi);\n\n  /* Enable the SPI DMA Tx & Rx requests */\n  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(hspi);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stop the DMA Transfer.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)\n{\n  HAL_StatusTypeDef errorcode = HAL_OK;\n  /* The Lock is not implemented on this API to allow the user application\n     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():\n     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\n     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()\n     */\n\n  /* Abort the SPI DMA tx Stream/Channel  */\n  if (hspi->hdmatx != NULL)\n  {\n    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n      errorcode = HAL_ERROR;\n    }\n  }\n  /* Abort the SPI DMA rx Stream/Channel  */\n  if (hspi->hdmarx != NULL)\n  {\n    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n      errorcode = HAL_ERROR;\n    }\n  }\n\n  /* Disable the SPI DMA Tx & Rx requests */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n  hspi->State = HAL_SPI_STATE_READY;\n  return errorcode;\n}\n\n/**\n  * @brief  Handle SPI interrupt request.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for the specified SPI module.\n  * @retval None\n  */\nvoid HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)\n{\n  uint32_t itsource = hspi->Instance->CR2;\n  uint32_t itflag   = hspi->Instance->SR;\n\n  /* SPI in mode Receiver ----------------------------------------------------*/\n  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&\n      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))\n  {\n    hspi->RxISR(hspi);\n    return;\n  }\n\n  /* SPI in mode Transmitter -------------------------------------------------*/\n  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))\n  {\n    hspi->TxISR(hspi);\n    return;\n  }\n\n  /* SPI in Error Treatment --------------------------------------------------*/\n  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)\n       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))\n  {\n    /* SPI Overrun error interrupt occurred ----------------------------------*/\n    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)\n    {\n      if (hspi->State != HAL_SPI_STATE_BUSY_TX)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\n      }\n      else\n      {\n        __HAL_SPI_CLEAR_OVRFLAG(hspi);\n        return;\n      }\n    }\n\n    /* SPI Mode Fault error interrupt occurred -------------------------------*/\n    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);\n      __HAL_SPI_CLEAR_MODFFLAG(hspi);\n    }\n\n    /* SPI Frame error interrupt occurred ------------------------------------*/\n    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);\n      __HAL_SPI_CLEAR_FREFLAG(hspi);\n    }\n\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      /* Disable all interrupts */\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);\n\n      hspi->State = HAL_SPI_STATE_READY;\n      /* Disable the SPI DMA requests if enabled */\n      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))\n      {\n        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));\n\n        /* Abort the SPI DMA Rx channel */\n        if (hspi->hdmarx != NULL)\n        {\n          /* Set the SPI DMA Abort callback :\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\n          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;\n          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))\n          {\n            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n          }\n        }\n        /* Abort the SPI DMA Tx channel */\n        if (hspi->hdmatx != NULL)\n        {\n          /* Set the SPI DMA Abort callback :\n          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */\n          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;\n          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))\n          {\n            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n          }\n        }\n      }\n      else\n      {\n        /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n        hspi->ErrorCallback(hspi);\n#else\n        HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      }\n    }\n    return;\n  }\n}\n\n/**\n  * @brief  Tx Transfer completed callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxCpltCallback should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Rx Transfer completed callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_RxCpltCallback should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Tx and Rx Transfer completed callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxRxCpltCallback should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Tx Half Transfer completed callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Rx Half Transfer completed callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Tx and Rx Half Transfer callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file\n   */\n}\n\n/**\n  * @brief  SPI error callback.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\n__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_ErrorCallback should be implemented in the user file\n   */\n  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes\n            and user can use HAL_SPI_GetError() API to check the latest error occurred\n   */\n}\n\n/**\n  * @brief  SPI Abort Complete callback.\n  * @param  hspi SPI handle.\n  * @retval None\n  */\n__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(hspi);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_SPI_AbortCpltCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions\n  * @brief   SPI control functions\n  *\n@verbatim\n ===============================================================================\n                      ##### Peripheral State and Errors functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to control the SPI.\n     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral\n     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the SPI handle state.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval SPI state\n  */\nHAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)\n{\n  /* Return SPI handle state */\n  return hspi->State;\n}\n\n/**\n  * @brief  Return the SPI error code.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval SPI error code in bitmap format\n  */\nuint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)\n{\n  /* Return SPI ErrorCode */\n  return hspi->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup SPI_Private_Functions\n  * @brief   Private functions\n  * @{\n  */\n\n/**\n  * @brief  DMA SPI transmit process complete callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n  uint32_t tickstart;\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* DMA Normal Mode */\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\n  {\n    /* Disable ERR interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\n\n    /* Disable Tx DMA Request */\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\n    /* Check the end of the transaction */\n    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n    }\n\n    /* Clear overrun flag in 2 Lines communication mode because received data is not read */\n    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n    {\n      __HAL_SPI_CLEAR_OVRFLAG(hspi);\n    }\n\n    hspi->TxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->ErrorCallback(hspi);\n#else\n      HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      return;\n    }\n  }\n  /* Call user Tx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->TxCpltCallback(hspi);\n#else\n  HAL_SPI_TxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI receive process complete callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n  uint32_t tickstart;\n#if (USE_SPI_CRC != 0U)\n  __IO uint32_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* DMA Normal Mode */\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\n  {\n    /* Disable ERR interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\n\n#if (USE_SPI_CRC != 0U)\n    /* CRC handling */\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Wait until RXNE flag */\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n      {\n        /* Error on the CRC reception */\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      }\n      /* Read CRC */\n      tmpreg = READ_REG(hspi->Instance->DR);\n      /* To avoid GCC warning */\n      UNUSED(tmpreg);\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Check if we are in Master RX 2 line mode */\n    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))\n    {\n      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */\n      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n    }\n    else\n    {\n      /* Normal case */\n      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n    }\n\n    /* Check the end of the transaction */\n    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n    {\n      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;\n    }\n\n    hspi->RxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n    /* Check if CRC error occurred */\n    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    }\n#endif /* USE_SPI_CRC */\n\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->ErrorCallback(hspi);\n#else\n      HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      return;\n    }\n  }\n  /* Call user Rx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->RxCpltCallback(hspi);\n#else\n  HAL_SPI_RxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI transmit receive process complete callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n  uint32_t tickstart;\n#if (USE_SPI_CRC != 0U)\n  __IO uint32_t tmpreg = 0U;\n#endif /* USE_SPI_CRC */\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* DMA Normal Mode */\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC)\n  {\n    /* Disable ERR interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\n\n#if (USE_SPI_CRC != 0U)\n    /* CRC handling */\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Wait the CRC data */\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      }\n      /* Read CRC to Flush DR and RXNE flag */\n      tmpreg = READ_REG(hspi->Instance->DR);\n      /* To avoid GCC warning */\n      UNUSED(tmpreg);\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Check the end of the transaction */\n    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n    }\n\n    /* Disable Rx/Tx DMA Request */\n    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n    hspi->TxXferCount = 0U;\n    hspi->RxXferCount = 0U;\n    hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n    /* Check if CRC error occurred */\n    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    }\n#endif /* USE_SPI_CRC */\n\n    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n    {\n      /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->ErrorCallback(hspi);\n#else\n      HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      return;\n    }\n  }\n  /* Call user TxRx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->TxRxCpltCallback(hspi);\n#else\n  HAL_SPI_TxRxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI half transmit process complete callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Call user Tx half complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->TxHalfCpltCallback(hspi);\n#else\n  HAL_SPI_TxHalfCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI half receive process complete callback\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Call user Rx half complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->RxHalfCpltCallback(hspi);\n#else\n  HAL_SPI_RxHalfCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI half transmit receive process complete callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Call user TxRx half complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->TxRxHalfCpltCallback(hspi);\n#else\n  HAL_SPI_TxRxHalfCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI communication error callback.\n  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void SPI_DMAError(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Stop the disable DMA transfer on SPI side */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);\n\n  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);\n  hspi->State = HAL_SPI_STATE_READY;\n  /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->ErrorCallback(hspi);\n#else\n  HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error\n  *         (To be called at end of DMA Abort procedure following error occurrence).\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->ErrorCallback(hspi);\n#else\n  HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI Tx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Tx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Rx DMA Handle.\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n  __IO uint32_t count;\n\n  hspi->hdmatx->XferAbortCallback = NULL;\n  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Disable Tx DMA Request */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if (count == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n      break;\n    }\n    count--;\n  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Check if an Abort process is still ongoing */\n  if (hspi->hdmarx != NULL)\n  {\n    if (hspi->hdmarx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Check no error during Abort procedure */\n  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\n  {\n    /* Reset errorCode */\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  }\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->State to Ready */\n  hspi->State  = HAL_SPI_STATE_READY;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->AbortCpltCallback(hspi);\n#else\n  HAL_SPI_AbortCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA SPI Rx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Rx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Tx DMA Handle.\n  * @param  hdma DMA handle.\n  * @retval None\n  */\nstatic void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  hspi->hdmarx->XferAbortCallback = NULL;\n\n  /* Disable Rx DMA Request */\n  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);\n\n  /* Check Busy flag */\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n  }\n\n  /* Check if an Abort process is still ongoing */\n  if (hspi->hdmatx != NULL)\n  {\n    if (hspi->hdmatx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */\n  hspi->RxXferCount = 0U;\n  hspi->TxXferCount = 0U;\n\n  /* Check no error during Abort procedure */\n  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)\n  {\n    /* Reset errorCode */\n    hspi->ErrorCode = HAL_SPI_ERROR_NONE;\n  }\n\n  /* Clear the Error flags in the SR register */\n  __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  __HAL_SPI_CLEAR_FREFLAG(hspi);\n\n  /* Restore hspi->State to Ready */\n  hspi->State  = HAL_SPI_STATE_READY;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n  hspi->AbortCpltCallback(hspi);\n#else\n  HAL_SPI_AbortCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Receive data in 8bit mode */\n  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);\n  hspi->pRxBuffPtr++;\n  hspi->RxXferCount--;\n\n  /* Check end of the reception */\n  if (hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable RXNE  and ERR interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n    if (hspi->TxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n\n  /* Read 8bit CRC to flush Data Register */\n  tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  /* Disable RXNE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  if (hspi->TxXferCount == 0U)\n  {\n    SPI_CloseRxTx_ISR(hspi);\n  }\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr++;\n  hspi->TxXferCount--;\n\n  /* Check the end of the transmission */\n  if (hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Set CRC Next Bit to send CRC */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n      /* Disable TXE interrupt */\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable TXE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n\n    if (hspi->RxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n/**\n  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Receive data in 16 Bit mode */\n  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\n  hspi->pRxBuffPtr += sizeof(uint16_t);\n  hspi->RxXferCount--;\n\n  if (hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable RXNE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\n\n    if (hspi->TxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n\n  /* Read 16bit CRC to flush Data Register */\n  tmpreg = READ_REG(hspi->Instance->DR);\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);  \n\n  /* Disable RXNE interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);\n\n  SPI_CloseRxTx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Transmit data in 16 Bit mode */\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr += sizeof(uint16_t);\n  hspi->TxXferCount--;\n\n  /* Enable CRC Transmission */\n  if (hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Set CRC Next Bit to send CRC */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n      /* Disable TXE interrupt */\n      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n      return;\n    }\n#endif /* USE_SPI_CRC */\n\n    /* Disable TXE interrupt */\n    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);\n\n    if (hspi->RxXferCount == 0U)\n    {\n      SPI_CloseRxTx_ISR(hspi);\n    }\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 8-bit receive in Interrupt context.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n\n  /* Read 8bit CRC to flush Data Register */\n  tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  SPI_CloseRx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Manage the receive 8-bit in Interrupt context.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);\n  hspi->pRxBuffPtr++;\n  hspi->RxXferCount--;\n\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n  {\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  if (hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR =  SPI_RxISR_8BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseRx_ISR(hspi);\n  }\n}\n\n#if (USE_SPI_CRC != 0U)\n/**\n  * @brief  Manage the CRC 16-bit receive in Interrupt context.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n\n  /* Read 16bit CRC to flush Data Register */\n  tmpreg = READ_REG(hspi->Instance->DR);\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  /* Disable RXNE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  SPI_CloseRx_ISR(hspi);\n}\n#endif /* USE_SPI_CRC */\n\n/**\n  * @brief  Manage the 16-bit receive in Interrupt context.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);\n  hspi->pRxBuffPtr += sizeof(uint16_t);\n  hspi->RxXferCount--;\n\n#if (USE_SPI_CRC != 0U)\n  /* Enable CRC Transmission */\n  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))\n  {\n    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n  }\n#endif /* USE_SPI_CRC */\n\n  if (hspi->RxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      hspi->RxISR = SPI_RxISR_16BITCRC;\n      return;\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseRx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief  Handle the data 8-bit transmit in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr++;\n  hspi->TxXferCount--;\n\n  if (hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Enable CRC Transmission */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseTx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief  Handle the data 16-bit transmit in Interrupt mode.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)\n{\n  /* Transmit data in 16 Bit mode */\n  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);\n  hspi->pTxBuffPtr += sizeof(uint16_t);\n  hspi->TxXferCount--;\n\n  if (hspi->TxXferCount == 0U)\n  {\n#if (USE_SPI_CRC != 0U)\n    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n    {\n      /* Enable CRC Transmission */\n      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);\n    }\n#endif /* USE_SPI_CRC */\n    SPI_CloseTx_ISR(hspi);\n  }\n}\n\n/**\n  * @brief  Handle SPI Communication Timeout.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *              the configuration information for SPI module.\n  * @param  Flag SPI flag to check\n  * @param  State flag state to check\n  * @param  Timeout Timeout duration\n  * @param  Tickstart tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,\n                                                       uint32_t Timeout, uint32_t Tickstart)\n{\n  __IO uint32_t count;\n  uint32_t tmp_timeout;\n  uint32_t tmp_tickstart;\n\n  /* Adjust Timeout value  in case of end of transfer */\n  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);\n  tmp_tickstart = HAL_GetTick();\n\n  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */\n  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);\n\n  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)\n  {\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))\n      {\n        /* Disable the SPI and reset the CRC: the CRC value should be cleared\n           on both master and slave sides in order to resynchronize the master\n           and slave for their respective CRC calculation */\n\n        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */\n        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));\n\n        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\n                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n        {\n          /* Disable SPI peripheral */\n          __HAL_SPI_DISABLE(hspi);\n        }\n\n        /* Reset CRC Calculation */\n        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)\n        {\n          SPI_RESET_CRC(hspi);\n        }\n\n        hspi->State = HAL_SPI_STATE_READY;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(hspi);\n\n        return HAL_TIMEOUT;\n      }\n      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */\n      if(count == 0U)\n      {\n        tmp_timeout = 0U;\n      }\n      count--;\n    }\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Handle the check of the RX transaction complete.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @param  Timeout Timeout duration\n  * @param  Tickstart tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)\n{\n  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)\n                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))\n  {\n    /* Disable SPI peripheral */\n    __HAL_SPI_DISABLE(hspi);\n  }\n\n  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */\n  if (hspi->Init.Mode == SPI_MODE_MASTER)\n  {\n    if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)\n    {\n      /* Control the BSY flag */\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n        return HAL_TIMEOUT;\n      }\n    }\n    else\n    {\n      /* Wait the RXNE reset */\n      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)\n      {\n        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  else\n  {\n    /* Wait the RXNE reset */\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      return HAL_TIMEOUT;\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Handle the check of the RXTX or TX transaction complete.\n  * @param  hspi SPI handle\n  * @param  Timeout Timeout duration\n  * @param  Tickstart tick start value\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)\n{\n  /* Timeout in µs */\n  __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);\n  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */\n  if (hspi->Init.Mode == SPI_MODE_MASTER)\n  {\n    /* Control the BSY flag */\n    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      return HAL_TIMEOUT;\n    }\n  }\n  else\n  {\n    /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer\n    * If Timeout is reached, the transfer is considered as finish.\n    * User have to calculate the timeout value to fit with the time of 1 byte transfer.\n    * This time is directly link with the SPI clock from Master device.\n    */\n    do\n    {\n      if (count == 0U)\n      {\n        break;\n      }\n      count--;\n    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Handle the end of the RXTX transaction.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  uint32_t tickstart;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Init tickstart for timeout management */\n  tickstart = HAL_GetTick();\n\n  /* Disable ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if (count == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n    count--;\n  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\n#if (USE_SPI_CRC != 0U)\n  /* Check if CRC error occurred */\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\n  {\n    hspi->State = HAL_SPI_STATE_READY;\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    hspi->ErrorCallback(hspi);\n#else\n    HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n  else\n  {\n#endif /* USE_SPI_CRC */\n    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\n    {\n      if (hspi->State == HAL_SPI_STATE_BUSY_RX)\n      {\n        hspi->State = HAL_SPI_STATE_READY;\n        /* Call user Rx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n        hspi->RxCpltCallback(hspi);\n#else\n        HAL_SPI_RxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      }\n      else\n      {\n        hspi->State = HAL_SPI_STATE_READY;\n        /* Call user TxRx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n        hspi->TxRxCpltCallback(hspi);\n#else\n        HAL_SPI_TxRxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n      }\n    }\n    else\n    {\n      hspi->State = HAL_SPI_STATE_READY;\n      /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->ErrorCallback(hspi);\n#else\n      HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n    }\n#if (USE_SPI_CRC != 0U)\n  }\n#endif /* USE_SPI_CRC */\n}\n\n/**\n  * @brief  Handle the end of the RX transaction.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)\n{\n  /* Disable RXNE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n  hspi->State = HAL_SPI_STATE_READY;\n\n#if (USE_SPI_CRC != 0U)\n  /* Check if CRC error occurred */\n  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);\n    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);\n    /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    hspi->ErrorCallback(hspi);\n#else\n    HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n  else\n  {\n#endif /* USE_SPI_CRC */\n    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)\n    {\n      /* Call user Rx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->RxCpltCallback(hspi);\n#else\n      HAL_SPI_RxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n    }\n    else\n    {\n      /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n      hspi->ErrorCallback(hspi);\n#else\n      HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n    }\n#if (USE_SPI_CRC != 0U)\n  }\n#endif /* USE_SPI_CRC */\n}\n\n/**\n  * @brief  Handle the end of the TX transaction.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  uint32_t tickstart;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Init tickstart for timeout management*/\n  tickstart = HAL_GetTick();\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if (count == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n      break;\n    }\n    count--;\n  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Disable TXE and ERR interrupt */\n  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));\n\n  /* Check the end of the transaction */\n  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)\n  {\n    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);\n  }\n\n  /* Clear overrun flag in 2 Lines communication mode because received is not read */\n  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)\n  {\n    __HAL_SPI_CLEAR_OVRFLAG(hspi);\n  }\n\n  hspi->State = HAL_SPI_STATE_READY;\n  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)\n  {\n    /* Call user error callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    hspi->ErrorCallback(hspi);\n#else\n    HAL_SPI_ErrorCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* Call user Rx complete callback */\n#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)\n    hspi->TxCpltCallback(hspi);\n#else\n    HAL_SPI_TxCpltCallback(hspi);\n#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief  Handle abort a Rx transaction.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)\n{\n  __IO uint32_t tmpreg = 0U;\n  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);\n\n  /* Wait until TXE flag is set */\n  do\n  {\n    if (count == 0U)\n    {\n      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);\n      break;\n    }\n    count--;\n  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));\n\n  /* Flush Data Register by a blank read */\n  tmpreg = READ_REG(hspi->Instance->DR);\n  /* To avoid GCC warning */\n  UNUSED(tmpreg);\n\n  hspi->State = HAL_SPI_STATE_ABORT;\n}\n\n/**\n  * @brief  Handle abort a Tx or Rx/Tx transaction.\n  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains\n  *               the configuration information for SPI module.\n  * @retval None\n  */\nstatic void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)\n{\n  /* Disable TXEIE interrupt */\n  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));\n\n  /* Disable SPI Peripheral */\n  __HAL_SPI_DISABLE(hspi);\n\n  hspi->State = HAL_SPI_STATE_ABORT;\n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_tim.c\n  * @author  MCD Application Team\n  * @brief   TIM HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Timer (TIM) peripheral:\n  *           + TIM Time Base Initialization\n  *           + TIM Time Base Start\n  *           + TIM Time Base Start Interruption\n  *           + TIM Time Base Start DMA\n  *           + TIM Output Compare/PWM Initialization\n  *           + TIM Output Compare/PWM Channel Configuration\n  *           + TIM Output Compare/PWM  Start\n  *           + TIM Output Compare/PWM  Start Interruption\n  *           + TIM Output Compare/PWM Start DMA\n  *           + TIM Input Capture Initialization\n  *           + TIM Input Capture Channel Configuration\n  *           + TIM Input Capture Start\n  *           + TIM Input Capture Start Interruption\n  *           + TIM Input Capture Start DMA\n  *           + TIM One Pulse Initialization\n  *           + TIM One Pulse Channel Configuration\n  *           + TIM One Pulse Start\n  *           + TIM Encoder Interface Initialization\n  *           + TIM Encoder Interface Start\n  *           + TIM Encoder Interface Start Interruption\n  *           + TIM Encoder Interface Start DMA\n  *           + Commutation Event configuration with Interruption and DMA\n  *           + TIM OCRef clear configuration\n  *           + TIM External Clock configuration\n  @verbatim\n  ==============================================================================\n                      ##### TIMER Generic features #####\n  ==============================================================================\n  [..] The Timer features include:\n       (#) 16-bit up, down, up/down auto-reload counter.\n       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the\n           counter clock frequency either by any factor between 1 and 65536.\n       (#) Up to 4 independent channels for:\n           (++) Input Capture\n           (++) Output Compare\n           (++) PWM generation (Edge and Center-aligned Mode)\n           (++) One-pulse mode output\n       (#) Synchronization circuit to control the timer with external signals and to interconnect\n            several timers together.\n       (#) Supports incremental encoder for positioning purposes\n\n            ##### How to use this driver #####\n  ==============================================================================\n    [..]\n     (#) Initialize the TIM low level resources by implementing the following functions\n         depending on the selected feature:\n           (++) Time Base : HAL_TIM_Base_MspInit()\n           (++) Input Capture : HAL_TIM_IC_MspInit()\n           (++) Output Compare : HAL_TIM_OC_MspInit()\n           (++) PWM generation : HAL_TIM_PWM_MspInit()\n           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()\n           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()\n\n     (#) Initialize the TIM low level resources :\n        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\n        (##) TIM pins configuration\n            (+++) Enable the clock for the TIM GPIOs using the following function:\n             __HAL_RCC_GPIOx_CLK_ENABLE();\n            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\n\n     (#) The external Clock can be configured, if needed (the default clock is the\n         internal clock from the APBx), using the following function:\n         HAL_TIM_ConfigClockSource, the clock configuration should be done before\n         any start function.\n\n     (#) Configure the TIM in the desired functioning mode using one of the\n       Initialization function of this driver:\n       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base\n       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an\n            Output Compare signal.\n       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a\n            PWM signal.\n       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an\n            external signal.\n       (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer\n            in One Pulse Mode.\n       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.\n\n     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:\n           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()\n           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()\n           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()\n           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()\n           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()\n           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().\n\n     (#) The DMA Burst is managed with the two following functions:\n         HAL_TIM_DMABurst_WriteStart()\n         HAL_TIM_DMABurst_ReadStart()\n\n    *** Callback registration ***\n  =============================================\n\n  [..]\n  The compilation define  USE_HAL_TIM_REGISTER_CALLBACKS when set to 1\n  allows the user to configure dynamically the driver callbacks.\n\n  [..]\n  Use Function @ref HAL_TIM_RegisterCallback() to register a callback.\n  @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,\n  the Callback ID and a pointer to the user callback function.\n\n  [..]\n  Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default\n  weak function.\n  @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,\n  and the Callback ID.\n\n  [..]\n  These functions allow to register/unregister following callbacks:\n    (+) Base_MspInitCallback              : TIM Base Msp Init Callback.\n    (+) Base_MspDeInitCallback            : TIM Base Msp DeInit Callback.\n    (+) IC_MspInitCallback                : TIM IC Msp Init Callback.\n    (+) IC_MspDeInitCallback              : TIM IC Msp DeInit Callback.\n    (+) OC_MspInitCallback                : TIM OC Msp Init Callback.\n    (+) OC_MspDeInitCallback              : TIM OC Msp DeInit Callback.\n    (+) PWM_MspInitCallback               : TIM PWM Msp Init Callback.\n    (+) PWM_MspDeInitCallback             : TIM PWM Msp DeInit Callback.\n    (+) OnePulse_MspInitCallback          : TIM One Pulse Msp Init Callback.\n    (+) OnePulse_MspDeInitCallback        : TIM One Pulse Msp DeInit Callback.\n    (+) Encoder_MspInitCallback           : TIM Encoder Msp Init Callback.\n    (+) Encoder_MspDeInitCallback         : TIM Encoder Msp DeInit Callback.\n    (+) HallSensor_MspInitCallback        : TIM Hall Sensor Msp Init Callback.\n    (+) HallSensor_MspDeInitCallback      : TIM Hall Sensor Msp DeInit Callback.\n    (+) PeriodElapsedCallback             : TIM Period Elapsed Callback.\n    (+) PeriodElapsedHalfCpltCallback     : TIM Period Elapsed half complete Callback.\n    (+) TriggerCallback                   : TIM Trigger Callback.\n    (+) TriggerHalfCpltCallback           : TIM Trigger half complete Callback.\n    (+) IC_CaptureCallback                : TIM Input Capture Callback.\n    (+) IC_CaptureHalfCpltCallback        : TIM Input Capture half complete Callback.\n    (+) OC_DelayElapsedCallback           : TIM Output Compare Delay Elapsed Callback.\n    (+) PWM_PulseFinishedCallback         : TIM PWM Pulse Finished Callback.\n    (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.\n    (+) ErrorCallback                     : TIM Error Callback.\n    (+) CommutationCallback               : TIM Commutation Callback.\n    (+) CommutationHalfCpltCallback       : TIM Commutation half complete Callback.\n    (+) BreakCallback                     : TIM Break Callback.\n\n  [..]\nBy default, after the Init and when the state is HAL_TIM_STATE_RESET\nall interrupt callbacks are set to the corresponding weak functions:\n  examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().\n\n  [..]\n  Exception done for MspInit and MspDeInit functions that are reset to the legacy weak\n  functionalities in the Init / DeInit only when these callbacks are null\n  (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit\n    keep and use the user MspInit / MspDeInit callbacks(registered beforehand)\n\n  [..]\n    Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.\n    Exception done MspInit / MspDeInit that can be registered / unregistered\n    in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,\n    thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.\n  In that case first register the MspInit/MspDeInit user callbacks\n      using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.\n\n  [..]\n      When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or\n      not defined, the callback registration feature is not available and all callbacks\n      are set to the corresponding weak functions.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup TIM TIM\n  * @brief TIM HAL module driver\n  * @{\n  */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/** @addtogroup TIM_Private_Functions\n  * @{\n  */\nstatic void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\nstatic void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\nstatic void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter);\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter);\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter);\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);\nstatic void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);\nstatic void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);\nstatic void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);\nstatic HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\n                                                  TIM_SlaveConfigTypeDef *sSlaveConfig);\n/**\n  * @}\n  */\n/* Exported functions --------------------------------------------------------*/\n\n/** @defgroup TIM_Exported_Functions TIM Exported Functions\n  * @{\n  */\n\n/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions\n  *  @brief    Time Base functions\n  *\n@verbatim\n  ==============================================================================\n              ##### Time Base functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure the TIM base.\n    (+) De-initialize the TIM base.\n    (+) Start the Time Base.\n    (+) Stop the Time Base.\n    (+) Start the Time Base and enable interrupt.\n    (+) Stop the Time Base and disable interrupt.\n    (+) Start the Time Base and enable DMA transfer.\n    (+) Stop the Time Base and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM Time base Unit according to the specified\n  *         parameters in the TIM_HandleTypeDef and initialize the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)\n{\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->Base_MspInitCallback == NULL)\n    {\n      htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->Base_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    HAL_TIM_Base_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Set the Time Base configuration */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM Base peripheral\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->Base_MspDeInitCallback == NULL)\n  {\n    htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->Base_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  HAL_TIM_Base_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Change the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Base MSP.\n  * @param  htim TIM Base handle\n  * @retval None\n  */\n__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_Base_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM Base MSP.\n  * @param  htim TIM Base handle\n  * @retval None\n  */\n__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_Base_MspDeInit could be implemented in the user file\n   */\n}\n\n\n/**\n  * @brief  Starts the TIM Base generation.\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  /* Check the TIM state */\n  if (htim->State != HAL_TIM_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Base generation.\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Base generation in interrupt mode.\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  /* Check the TIM state */\n  if (htim->State != HAL_TIM_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Enable the TIM Update interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Base generation in interrupt mode.\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  /* Disable the TIM Update interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Base generation in DMA mode.\n  * @param  htim TIM Base handle\n  * @param  pData The source Buffer address.\n  * @param  Length The length of data to be transferred from memory to peripheral.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\n\n  /* Set the TIM state */\n  if (htim->State == HAL_TIM_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (htim->State == HAL_TIM_STATE_READY)\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      htim->State = HAL_TIM_STATE_BUSY;\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the DMA Period elapsed callbacks */\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\n\n  /* Set the DMA error callback */\n  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\n\n  /* Enable the DMA stream */\n  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)\n  {\n    /* Return error status */\n    return HAL_ERROR;\n  }\n\n  /* Enable the TIM Update DMA request */\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Base generation in DMA mode.\n  * @param  htim TIM Base handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));\n\n  /* Disable the TIM Update DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);\n\n  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions\n  *  @brief    TIM Output Compare functions\n  *\n@verbatim\n  ==============================================================================\n                  ##### TIM Output Compare functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure the TIM Output Compare.\n    (+) De-initialize the TIM Output Compare.\n    (+) Start the TIM Output Compare.\n    (+) Stop the TIM Output Compare.\n    (+) Start the TIM Output Compare and enable interrupt.\n    (+) Stop the TIM Output Compare and disable interrupt.\n    (+) Start the TIM Output Compare and enable DMA transfer.\n    (+) Stop the TIM Output Compare and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM Output Compare according to the specified\n  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()\n  * @param  htim TIM Output Compare handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)\n{\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->OC_MspInitCallback == NULL)\n    {\n      htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->OC_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIM_OC_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Init the base time for the Output Compare */\n  TIM_Base_SetConfig(htim->Instance,  &htim->Init);\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM peripheral\n  * @param  htim TIM Output Compare handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->OC_MspDeInitCallback == NULL)\n  {\n    htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->OC_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\n  HAL_TIM_OC_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Change the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Output Compare MSP.\n  * @param  htim TIM Output Compare handle\n  * @retval None\n  */\n__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_OC_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM Output Compare MSP.\n  * @param  htim TIM Output Compare handle\n  * @retval None\n  */\n__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_OC_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Disable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Enable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Enable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Enable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Enable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation in DMA mode.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  pData The source Buffer address.\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Set the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n\n      /* Enable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n\n      /* Enable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 3 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 4 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation in DMA mode.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Output compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions\n  *  @brief    TIM PWM functions\n  *\n@verbatim\n  ==============================================================================\n                          ##### TIM PWM functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure the TIM PWM.\n    (+) De-initialize the TIM PWM.\n    (+) Start the TIM PWM.\n    (+) Stop the TIM PWM.\n    (+) Start the TIM PWM and enable interrupt.\n    (+) Stop the TIM PWM and disable interrupt.\n    (+) Start the TIM PWM and enable DMA transfer.\n    (+) Stop the TIM PWM and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM PWM Time Base according to the specified\n  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()\n  * @param  htim TIM PWM handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)\n{\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->PWM_MspInitCallback == NULL)\n    {\n      htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->PWM_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIM_PWM_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Init the base time for the PWM */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM peripheral\n  * @param  htim TIM PWM handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->PWM_MspDeInitCallback == NULL)\n  {\n    htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->PWM_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\n  HAL_TIM_PWM_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Change the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM PWM MSP.\n  * @param  htim TIM PWM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PWM_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM PWM MSP.\n  * @param  htim TIM PWM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PWM_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the PWM signal generation.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the PWM signal generation.\n  * @param  htim TIM PWM handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Disable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the PWM signal generation in interrupt mode.\n  * @param  htim TIM PWM handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Enable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Enable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Enable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Enable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the PWM signal generation in interrupt mode.\n  * @param  htim TIM PWM handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM PWM signal generation in DMA mode.\n  * @param  htim TIM PWM handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  pData The source Buffer address.\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Set the TIM channel state */\n  if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n\n      /* Enable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Output Capture/Compare 3 request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 4 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM PWM signal generation in DMA mode.\n  * @param  htim TIM PWM handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Capture compare channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions\n  *  @brief    TIM Input Capture functions\n  *\n@verbatim\n  ==============================================================================\n              ##### TIM Input Capture functions #####\n  ==============================================================================\n [..]\n   This section provides functions allowing to:\n   (+) Initialize and configure the TIM Input Capture.\n   (+) De-initialize the TIM Input Capture.\n   (+) Start the TIM Input Capture.\n   (+) Stop the TIM Input Capture.\n   (+) Start the TIM Input Capture and enable interrupt.\n   (+) Stop the TIM Input Capture and disable interrupt.\n   (+) Start the TIM Input Capture and enable DMA transfer.\n   (+) Stop the TIM Input Capture and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM Input Capture Time base according to the specified\n  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()\n  * @param  htim TIM Input Capture handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)\n{\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->IC_MspInitCallback == NULL)\n    {\n      htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->IC_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIM_IC_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Init the base time for the input capture */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM peripheral\n  * @param  htim TIM Input Capture handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->IC_MspDeInitCallback == NULL)\n  {\n    htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->IC_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */\n  HAL_TIM_IC_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Change the TIM channels state */\n  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Input Capture MSP.\n  * @param  htim TIM Input Capture handle\n  * @retval None\n  */\n__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_IC_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM Input Capture MSP.\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_IC_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the TIM Input Capture measurement.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Input Capture measurement.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Disable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Input Capture measurement in interrupt mode.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM channel state */\n  if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Enable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Enable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Enable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Enable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n  /* Enable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Input Capture measurement in interrupt mode.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Input Capture measurement in DMA mode.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @param  pData The destination Buffer address.\n  * @param  Length The length of data to be transferred from TIM peripheral to memory.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\n\n  /* Set the TIM channel state */\n  if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)\n      || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))\n  {\n    return HAL_BUSY;\n  }\n  else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)\n           && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 2  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 3  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 4  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Input Capture measurement in DMA mode.\n  * @param  htim TIM Input Capture handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channel */\n  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3  DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Disable the TIM Capture/Compare 4  DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions\n  *  @brief    TIM One Pulse functions\n  *\n@verbatim\n  ==============================================================================\n                        ##### TIM One Pulse functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure the TIM One Pulse.\n    (+) De-initialize the TIM One Pulse.\n    (+) Start the TIM One Pulse.\n    (+) Stop the TIM One Pulse.\n    (+) Start the TIM One Pulse and enable interrupt.\n    (+) Stop the TIM One Pulse and disable interrupt.\n    (+) Start the TIM One Pulse and enable DMA transfer.\n    (+) Stop the TIM One Pulse and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM One Pulse Time Base according to the specified\n  *         parameters in the TIM_HandleTypeDef and initializes the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()\n  * @note   When the timer instance is initialized in One Pulse mode, timer\n  *         channels 1 and channel 2 are reserved and cannot be used for other\n  *         purpose.\n  * @param  htim TIM One Pulse handle\n  * @param  OnePulseMode Select the One pulse mode.\n  *         This parameter can be one of the following values:\n  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.\n  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)\n{\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_OPM_MODE(OnePulseMode));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->OnePulse_MspInitCallback == NULL)\n    {\n      htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->OnePulse_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIM_OnePulse_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Configure the Time base in the One Pulse Mode */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Reset the OPM Bit */\n  htim->Instance->CR1 &= ~TIM_CR1_OPM;\n\n  /* Configure the OPM Mode */\n  htim->Instance->CR1 |= OnePulseMode;\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM One Pulse\n  * @param  htim TIM One Pulse handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->OnePulse_MspDeInitCallback == NULL)\n  {\n    htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->OnePulse_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  HAL_TIM_OnePulse_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM One Pulse MSP.\n  * @param  htim TIM One Pulse handle\n  * @retval None\n  */\n__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_OnePulse_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM One Pulse MSP.\n  * @param  htim TIM One Pulse handle\n  * @retval None\n  */\n__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the TIM One Pulse signal generation.\n  * @note Though OutputChannel parameter is deprecated and ignored by the function\n  *        it has been kept to avoid HAL_TIM API compatibility break.\n  * @note The pulse output channel is determined when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel See note above\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(OutputChannel);\n\n  /* Check the TIM channels state */\n  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Capture compare and the Input Capture channels\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\n    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\n\n    No need to enable the counter, it's enabled automatically by hardware\n    (the counter starts in response to a stimulus and generate a pulse */\n\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM One Pulse signal generation.\n  * @note Though OutputChannel parameter is deprecated and ignored by the function\n  *        it has been kept to avoid HAL_TIM API compatibility break.\n  * @note The pulse output channel is determined when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel See note above\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(OutputChannel);\n\n  /* Disable the Capture compare and the Input Capture channels\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\n  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\n\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.\n  * @note Though OutputChannel parameter is deprecated and ignored by the function\n  *        it has been kept to avoid HAL_TIM API compatibility break.\n  * @note The pulse output channel is determined when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel See note above\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(OutputChannel);\n\n  /* Check the TIM channels state */\n  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Capture compare and the Input Capture channels\n    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\n    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\n    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\n    whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together\n\n    No need to enable the counter, it's enabled automatically by hardware\n    (the counter starts in response to a stimulus and generate a pulse */\n\n  /* Enable the TIM Capture/Compare 1 interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n\n  /* Enable the TIM Capture/Compare 2 interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Enable the main output */\n    __HAL_TIM_MOE_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.\n  * @note Though OutputChannel parameter is deprecated and ignored by the function\n  *        it has been kept to avoid HAL_TIM API compatibility break.\n  * @note The pulse output channel is determined when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel See note above\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(OutputChannel);\n\n  /* Disable the TIM Capture/Compare 1 interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n\n  /* Disable the TIM Capture/Compare 2 interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n\n  /* Disable the Capture compare and the Input Capture channels\n  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)\n  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and\n  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output\n  whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)\n  {\n    /* Disable the Main Output */\n    __HAL_TIM_MOE_DISABLE(htim);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions\n  *  @brief    TIM Encoder functions\n  *\n@verbatim\n  ==============================================================================\n                          ##### TIM Encoder functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure the TIM Encoder.\n    (+) De-initialize the TIM Encoder.\n    (+) Start the TIM Encoder.\n    (+) Stop the TIM Encoder.\n    (+) Start the TIM Encoder and enable interrupt.\n    (+) Stop the TIM Encoder and disable interrupt.\n    (+) Start the TIM Encoder and enable DMA transfer.\n    (+) Stop the TIM Encoder and disable DMA transfer.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM Encoder Interface and initialize the associated handle.\n  * @note   Switching from Center Aligned counter mode to Edge counter mode (or reverse)\n  *         requires a timer reset to avoid unexpected direction\n  *         due to DIR bit readonly in center aligned mode.\n  *         Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()\n  * @note   Encoder mode and External clock mode 2 are not compatible and must not be selected together\n  *         Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource\n  *         using TIM_CLOCKSOURCE_ETRMODE2 and vice versa\n  * @note   When the timer instance is initialized in Encoder mode, timer\n  *         channels 1 and channel 2 are reserved and cannot be used for other\n  *         purpose.\n  * @param  htim TIM Encoder Interface handle\n  * @param  sConfig TIM Encoder Interface configuration structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig)\n{\n  uint32_t tmpsmcr;\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));\n  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));\n  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));\n  assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy weak callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->Encoder_MspInitCallback == NULL)\n    {\n      htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->Encoder_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIM_Encoder_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Reset the SMS and ECE bits */\n  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);\n\n  /* Configure the Time base in the Encoder Mode */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Get the TIMx SMCR register value */\n  tmpsmcr = htim->Instance->SMCR;\n\n  /* Get the TIMx CCMR1 register value */\n  tmpccmr1 = htim->Instance->CCMR1;\n\n  /* Get the TIMx CCER register value */\n  tmpccer = htim->Instance->CCER;\n\n  /* Set the encoder Mode */\n  tmpsmcr |= sConfig->EncoderMode;\n\n  /* Select the Capture Compare 1 and the Capture Compare 2 as input */\n  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);\n  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));\n\n  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */\n  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);\n  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);\n  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);\n  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);\n\n  /* Set the TI1 and the TI2 Polarities */\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);\n  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);\n  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);\n\n  /* Write to TIMx SMCR */\n  htim->Instance->SMCR = tmpsmcr;\n\n  /* Write to TIMx CCMR1 */\n  htim->Instance->CCMR1 = tmpccmr1;\n\n  /* Write to TIMx CCER */\n  htim->Instance->CCER = tmpccer;\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n\n/**\n  * @brief  DeInitializes the TIM Encoder interface\n  * @param  htim TIM Encoder Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->Encoder_MspDeInitCallback == NULL)\n  {\n    htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->Encoder_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  HAL_TIM_Encoder_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Encoder Interface MSP.\n  * @param  htim TIM Encoder Interface handle\n  * @retval None\n  */\n__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_Encoder_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM Encoder Interface MSP.\n  * @param  htim TIM Encoder Interface handle\n  * @retval None\n  */\n__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the TIM Encoder Interface.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Set the TIM channel(s) state */\n  if (Channel == TIM_CHANNEL_1)\n  {\n    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n\n  /* Enable the encoder interface channels */\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n      break;\n    }\n\n    default :\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n      break;\n    }\n  }\n  /* Enable the Peripheral */\n  __HAL_TIM_ENABLE(htim);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Encoder Interface.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channels 1 and 2\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n      break;\n    }\n\n    default :\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n      break;\n    }\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel(s) state */\n  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))\n  {\n    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else\n  {\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Encoder Interface in interrupt mode.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Set the TIM channel(s) state */\n  if (Channel == TIM_CHANNEL_1)\n  {\n    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n\n  /* Enable the encoder interface channels */\n  /* Enable the capture compare Interrupts 1 and/or 2 */\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    default :\n    {\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n  }\n\n  /* Enable the Peripheral */\n  __HAL_TIM_ENABLE(htim);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Encoder Interface in interrupt mode.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channels 1 and 2\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\n  if (Channel == TIM_CHANNEL_1)\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare Interrupts 1 */\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare Interrupts 2 */\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n  }\n  else\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare Interrupts 1 and 2 */\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel(s) state */\n  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))\n  {\n    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else\n  {\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Encoder Interface in DMA mode.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @param  pData1 The destination Buffer address for IC1.\n  * @param  pData2 The destination Buffer address for IC2.\n  * @param  Length The length of data to be transferred from TIM peripheral to memory.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,\n                                            uint32_t *pData2, uint16_t Length)\n{\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Set the TIM channel(s) state */\n  if (Channel == TIM_CHANNEL_1)\n  {\n    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)\n        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))\n    {\n      return HAL_BUSY;\n    }\n    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)\n             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))\n    {\n      if ((pData1 == NULL) && (Length > 0U))\n      {\n        return HAL_ERROR;\n      }\n      else\n      {\n        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      }\n    }\n    else\n    {\n      return HAL_ERROR;\n    }\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)\n        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))\n    {\n      return HAL_BUSY;\n    }\n    else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)\n             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))\n    {\n      if ((pData2 == NULL) && (Length > 0U))\n      {\n        return HAL_ERROR;\n      }\n      else\n      {\n        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      }\n    }\n    else\n    {\n      return HAL_ERROR;\n    }\n  }\n  else\n  {\n    if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)\n        || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)\n        || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)\n        || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))\n    {\n      return HAL_BUSY;\n    }\n    else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)\n             && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)\n             && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)\n             && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))\n    {\n      if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))\n      {\n        return HAL_ERROR;\n      }\n      else\n      {\n        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n        TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n        TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n      }\n    }\n    else\n    {\n      return HAL_ERROR;\n    }\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Input Capture DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n\n      /* Enable the Peripheral */\n      __HAL_TIM_ENABLE(htim);\n\n      /* Enable the Capture compare channel */\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Input Capture  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n\n      /* Enable the Peripheral */\n      __HAL_TIM_ENABLE(htim);\n\n      /* Enable the Capture compare channel */\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n      break;\n    }\n\n    case TIM_CHANNEL_ALL:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the Peripheral */\n      __HAL_TIM_ENABLE(htim);\n\n      /* Enable the Capture compare channel */\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);\n\n      /* Enable the TIM Input Capture  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      /* Enable the TIM Input Capture  DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Encoder Interface in DMA mode.\n  * @param  htim TIM Encoder Interface handle\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channels 1 and 2\n    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */\n  if (Channel == TIM_CHANNEL_1)\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare DMA Request 1 */\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare DMA Request 2 */\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n  }\n  else\n  {\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);\n\n    /* Disable the capture compare DMA Request 1 and 2 */\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n    (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n  }\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel(s) state */\n  if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))\n  {\n    TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else\n  {\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management\n  *  @brief    TIM IRQ handler management\n  *\n@verbatim\n  ==============================================================================\n                        ##### IRQ handler management #####\n  ==============================================================================\n  [..]\n    This section provides Timer IRQ handler function.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  This function handles TIM interrupts requests.\n  * @param  htim TIM  handle\n  * @retval None\n  */\nvoid HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)\n{\n  /* Capture compare 1 event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)\n    {\n      {\n        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n\n        /* Input capture event */\n        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)\n        {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n          htim->IC_CaptureCallback(htim);\n#else\n          HAL_TIM_IC_CaptureCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n        }\n        /* Output compare event */\n        else\n        {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n          htim->OC_DelayElapsedCallback(htim);\n          htim->PWM_PulseFinishedCallback(htim);\n#else\n          HAL_TIM_OC_DelayElapsedCallback(htim);\n          HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n        }\n        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n      }\n    }\n  }\n  /* Capture compare 2 event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n      /* Input capture event */\n      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->IC_CaptureCallback(htim);\n#else\n        HAL_TIM_IC_CaptureCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      /* Output compare event */\n      else\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->OC_DelayElapsedCallback(htim);\n        htim->PWM_PulseFinishedCallback(htim);\n#else\n        HAL_TIM_OC_DelayElapsedCallback(htim);\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n    }\n  }\n  /* Capture compare 3 event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n      /* Input capture event */\n      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->IC_CaptureCallback(htim);\n#else\n        HAL_TIM_IC_CaptureCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      /* Output compare event */\n      else\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->OC_DelayElapsedCallback(htim);\n        htim->PWM_PulseFinishedCallback(htim);\n#else\n        HAL_TIM_OC_DelayElapsedCallback(htim);\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n    }\n  }\n  /* Capture compare 4 event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n      /* Input capture event */\n      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->IC_CaptureCallback(htim);\n#else\n        HAL_TIM_IC_CaptureCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      /* Output compare event */\n      else\n      {\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n        htim->OC_DelayElapsedCallback(htim);\n        htim->PWM_PulseFinishedCallback(htim);\n#else\n        HAL_TIM_OC_DelayElapsedCallback(htim);\n        HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n      }\n      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n    }\n  }\n  /* TIM Update event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n      htim->PeriodElapsedCallback(htim);\n#else\n      HAL_TIM_PeriodElapsedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n    }\n  }\n  /* TIM Break input event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n      htim->BreakCallback(htim);\n#else\n      HAL_TIMEx_BreakCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n    }\n  }\n  /* TIM Trigger detection event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n      htim->TriggerCallback(htim);\n#else\n      HAL_TIM_TriggerCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n    }\n  }\n  /* TIM commutation event */\n  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)\n  {\n    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)\n    {\n      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n      htim->CommutationCallback(htim);\n#else\n      HAL_TIMEx_CommutCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n    }\n  }\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions\n  *  @brief    TIM Peripheral Control functions\n  *\n@verbatim\n  ==============================================================================\n                   ##### Peripheral Control functions #####\n  ==============================================================================\n [..]\n   This section provides functions allowing to:\n      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.\n      (+) Configure External Clock source.\n      (+) Configure Complementary channels, break features and dead time.\n      (+) Configure Master and the Slave synchronization.\n      (+) Configure the DMA Burst Mode.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the TIM Output Compare Channels according to the specified\n  *         parameters in the TIM_OC_InitTypeDef.\n  * @param  htim TIM Output Compare handle\n  * @param  sConfig TIM Output Compare configuration structure\n  * @param  Channel TIM Channels to configure\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,\n                                           TIM_OC_InitTypeDef *sConfig,\n                                           uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CHANNELS(Channel));\n  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n\n      /* Configure the TIM Channel 1 in Output Compare */\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n      /* Configure the TIM Channel 2 in Output Compare */\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\n\n      /* Configure the TIM Channel 3 in Output Compare */\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\n\n      /* Configure the TIM Channel 4 in Output Compare */\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Input Capture Channels according to the specified\n  *         parameters in the TIM_IC_InitTypeDef.\n  * @param  htim TIM IC handle\n  * @param  sConfig TIM Input Capture configuration structure\n  * @param  Channel TIM Channel to configure\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));\n  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));\n  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  if (Channel == TIM_CHANNEL_1)\n  {\n    /* TI1 Configuration */\n    TIM_TI1_SetConfig(htim->Instance,\n                      sConfig->ICPolarity,\n                      sConfig->ICSelection,\n                      sConfig->ICFilter);\n\n    /* Reset the IC1PSC Bits */\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\n\n    /* Set the IC1PSC value */\n    htim->Instance->CCMR1 |= sConfig->ICPrescaler;\n  }\n  else if (Channel == TIM_CHANNEL_2)\n  {\n    /* TI2 Configuration */\n    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n    TIM_TI2_SetConfig(htim->Instance,\n                      sConfig->ICPolarity,\n                      sConfig->ICSelection,\n                      sConfig->ICFilter);\n\n    /* Reset the IC2PSC Bits */\n    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\n\n    /* Set the IC2PSC value */\n    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);\n  }\n  else if (Channel == TIM_CHANNEL_3)\n  {\n    /* TI3 Configuration */\n    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\n\n    TIM_TI3_SetConfig(htim->Instance,\n                      sConfig->ICPolarity,\n                      sConfig->ICSelection,\n                      sConfig->ICFilter);\n\n    /* Reset the IC3PSC Bits */\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;\n\n    /* Set the IC3PSC value */\n    htim->Instance->CCMR2 |= sConfig->ICPrescaler;\n  }\n  else\n  {\n    /* TI4 Configuration */\n    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\n\n    TIM_TI4_SetConfig(htim->Instance,\n                      sConfig->ICPolarity,\n                      sConfig->ICSelection,\n                      sConfig->ICFilter);\n\n    /* Reset the IC4PSC Bits */\n    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;\n\n    /* Set the IC4PSC value */\n    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);\n  }\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM PWM  channels according to the specified\n  *         parameters in the TIM_OC_InitTypeDef.\n  * @param  htim TIM PWM handle\n  * @param  sConfig TIM PWM configuration structure\n  * @param  Channel TIM Channels to be configured\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,\n                                            TIM_OC_InitTypeDef *sConfig,\n                                            uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CHANNELS(Channel));\n  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));\n  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));\n  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n\n      /* Configure the Channel 1 in PWM mode */\n      TIM_OC1_SetConfig(htim->Instance, sConfig);\n\n      /* Set the Preload enable bit for channel1 */\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;\n\n      /* Configure the Output Fast mode */\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;\n      htim->Instance->CCMR1 |= sConfig->OCFastMode;\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n      /* Configure the Channel 2 in PWM mode */\n      TIM_OC2_SetConfig(htim->Instance, sConfig);\n\n      /* Set the Preload enable bit for channel2 */\n      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;\n\n      /* Configure the Output Fast mode */\n      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;\n      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\n\n      /* Configure the Channel 3 in PWM mode */\n      TIM_OC3_SetConfig(htim->Instance, sConfig);\n\n      /* Set the Preload enable bit for channel3 */\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;\n\n      /* Configure the Output Fast mode */\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;\n      htim->Instance->CCMR2 |= sConfig->OCFastMode;\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\n\n      /* Configure the Channel 4 in PWM mode */\n      TIM_OC4_SetConfig(htim->Instance, sConfig);\n\n      /* Set the Preload enable bit for channel4 */\n      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;\n\n      /* Configure the Output Fast mode */\n      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;\n      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM One Pulse Channels according to the specified\n  *         parameters in the TIM_OnePulse_InitTypeDef.\n  * @param  htim TIM One Pulse handle\n  * @param  sConfig TIM One Pulse configuration structure\n  * @param  OutputChannel TIM output channel to configure\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @param  InputChannel TIM input Channel to configure\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @note  To output a waveform with a minimum delay user can enable the fast\n  *        mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx\n  *        output is forced in response to the edge detection on TIx input,\n  *        without taking in account the comparison.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef *sConfig,\n                                                 uint32_t OutputChannel,  uint32_t InputChannel)\n{\n  TIM_OC_InitTypeDef temp1;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));\n  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));\n\n  if (OutputChannel != InputChannel)\n  {\n    /* Process Locked */\n    __HAL_LOCK(htim);\n\n    htim->State = HAL_TIM_STATE_BUSY;\n\n    /* Extract the Output compare configuration from sConfig structure */\n    temp1.OCMode = sConfig->OCMode;\n    temp1.Pulse = sConfig->Pulse;\n    temp1.OCPolarity = sConfig->OCPolarity;\n    temp1.OCNPolarity = sConfig->OCNPolarity;\n    temp1.OCIdleState = sConfig->OCIdleState;\n    temp1.OCNIdleState = sConfig->OCNIdleState;\n\n    switch (OutputChannel)\n    {\n      case TIM_CHANNEL_1:\n      {\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n\n        TIM_OC1_SetConfig(htim->Instance, &temp1);\n        break;\n      }\n      case TIM_CHANNEL_2:\n      {\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n        TIM_OC2_SetConfig(htim->Instance, &temp1);\n        break;\n      }\n      default:\n        break;\n    }\n\n    switch (InputChannel)\n    {\n      case TIM_CHANNEL_1:\n      {\n        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n\n        TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,\n                          sConfig->ICSelection, sConfig->ICFilter);\n\n        /* Reset the IC1PSC Bits */\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\n\n        /* Select the Trigger source */\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\n        htim->Instance->SMCR |= TIM_TS_TI1FP1;\n\n        /* Select the Slave Mode */\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\n        break;\n      }\n      case TIM_CHANNEL_2:\n      {\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n        TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,\n                          sConfig->ICSelection, sConfig->ICFilter);\n\n        /* Reset the IC2PSC Bits */\n        htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;\n\n        /* Select the Trigger source */\n        htim->Instance->SMCR &= ~TIM_SMCR_TS;\n        htim->Instance->SMCR |= TIM_TS_TI2FP2;\n\n        /* Select the Slave Mode */\n        htim->Instance->SMCR &= ~TIM_SMCR_SMS;\n        htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;\n        break;\n      }\n\n      default:\n        break;\n    }\n\n    htim->State = HAL_TIM_STATE_READY;\n\n    __HAL_UNLOCK(htim);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n}\n\n/**\n  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral\n  * @param  htim TIM handle\n  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data write\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMABASE_CR1\n  *            @arg TIM_DMABASE_CR2\n  *            @arg TIM_DMABASE_SMCR\n  *            @arg TIM_DMABASE_DIER\n  *            @arg TIM_DMABASE_SR\n  *            @arg TIM_DMABASE_EGR\n  *            @arg TIM_DMABASE_CCMR1\n  *            @arg TIM_DMABASE_CCMR2\n  *            @arg TIM_DMABASE_CCER\n  *            @arg TIM_DMABASE_CNT\n  *            @arg TIM_DMABASE_PSC\n  *            @arg TIM_DMABASE_ARR\n  *            @arg TIM_DMABASE_RCR\n  *            @arg TIM_DMABASE_CCR1\n  *            @arg TIM_DMABASE_CCR2\n  *            @arg TIM_DMABASE_CCR3\n  *            @arg TIM_DMABASE_CCR4\n  *            @arg TIM_DMABASE_BDTR\n  * @param  BurstRequestSrc TIM DMA Request sources\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\n  * @param  BurstBuffer The Buffer address.\n  * @param  BurstLength DMA Burst length. This parameter can be one value\n  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\n  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                              uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t  BurstLength)\n{\n  return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,\n                                          ((BurstLength) >> 8U) + 1U);\n}\n\n/**\n  * @brief  Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral\n  * @param  htim TIM handle\n  * @param  BurstBaseAddress TIM Base address from where the DMA will start the Data write\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMABASE_CR1\n  *            @arg TIM_DMABASE_CR2\n  *            @arg TIM_DMABASE_SMCR\n  *            @arg TIM_DMABASE_DIER\n  *            @arg TIM_DMABASE_SR\n  *            @arg TIM_DMABASE_EGR\n  *            @arg TIM_DMABASE_CCMR1\n  *            @arg TIM_DMABASE_CCMR2\n  *            @arg TIM_DMABASE_CCER\n  *            @arg TIM_DMABASE_CNT\n  *            @arg TIM_DMABASE_PSC\n  *            @arg TIM_DMABASE_ARR\n  *            @arg TIM_DMABASE_RCR\n  *            @arg TIM_DMABASE_CCR1\n  *            @arg TIM_DMABASE_CCR2\n  *            @arg TIM_DMABASE_CCR3\n  *            @arg TIM_DMABASE_CCR4\n  *            @arg TIM_DMABASE_BDTR\n  * @param  BurstRequestSrc TIM DMA Request sources\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\n  * @param  BurstBuffer The Buffer address.\n  * @param  BurstLength DMA Burst length. This parameter can be one value\n  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\n  * @param  DataLength Data length. This parameter can be one value\n  *         between 1 and 0xFFFF.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer,\n                                                   uint32_t  BurstLength,  uint32_t  DataLength)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\n  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));\n\n  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)\n  {\n    if ((BurstBuffer == NULL) && (BurstLength > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;\n    }\n  }\n  else\n  {\n    /* nothing to do */\n  }\n  switch (BurstRequestSrc)\n  {\n    case TIM_DMA_UPDATE:\n    {\n      /* Set the DMA Period elapsed callbacks */\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC1:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC2:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC3:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC4:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;\n      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_COM:\n    {\n      /* Set the DMA commutation callbacks */\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_TRIGGER:\n    {\n      /* Set the DMA trigger callbacks */\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,\n                         (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    default:\n      break;\n  }\n\n  /* Configure the DMA Burst Mode */\n  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\n  /* Enable the TIM DMA Request */\n  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM DMA Burst mode\n  * @param  htim TIM handle\n  * @param  BurstRequestSrc TIM DMA Request sources to disable\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\n\n  /* Abort the DMA transfer (at least disable the DMA stream) */\n  switch (BurstRequestSrc)\n  {\n    case TIM_DMA_UPDATE:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\n      break;\n    }\n    case TIM_DMA_CC1:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n    case TIM_DMA_CC2:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n    case TIM_DMA_CC3:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n    case TIM_DMA_CC4:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\n      break;\n    }\n    case TIM_DMA_COM:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\n      break;\n    }\n    case TIM_DMA_TRIGGER:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\n      break;\n    }\n    default:\n      break;\n  }\n\n  /* Disable the TIM Update DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\n  * @param  htim TIM handle\n  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMABASE_CR1\n  *            @arg TIM_DMABASE_CR2\n  *            @arg TIM_DMABASE_SMCR\n  *            @arg TIM_DMABASE_DIER\n  *            @arg TIM_DMABASE_SR\n  *            @arg TIM_DMABASE_EGR\n  *            @arg TIM_DMABASE_CCMR1\n  *            @arg TIM_DMABASE_CCMR2\n  *            @arg TIM_DMABASE_CCER\n  *            @arg TIM_DMABASE_CNT\n  *            @arg TIM_DMABASE_PSC\n  *            @arg TIM_DMABASE_ARR\n  *            @arg TIM_DMABASE_RCR\n  *            @arg TIM_DMABASE_CCR1\n  *            @arg TIM_DMABASE_CCR2\n  *            @arg TIM_DMABASE_CCR3\n  *            @arg TIM_DMABASE_CCR4\n  *            @arg TIM_DMABASE_BDTR\n  * @param  BurstRequestSrc TIM DMA Request sources\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\n  * @param  BurstBuffer The Buffer address.\n  * @param  BurstLength DMA Burst length. This parameter can be one value\n  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\n  * @note   This function should be used only when BurstLength is equal to DMA data transfer length.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength)\n{\n  return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,\n                                         ((BurstLength) >> 8U) + 1U);\n}\n\n/**\n  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory\n  * @param  htim TIM handle\n  * @param  BurstBaseAddress TIM Base address from where the DMA  will start the Data read\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMABASE_CR1\n  *            @arg TIM_DMABASE_CR2\n  *            @arg TIM_DMABASE_SMCR\n  *            @arg TIM_DMABASE_DIER\n  *            @arg TIM_DMABASE_SR\n  *            @arg TIM_DMABASE_EGR\n  *            @arg TIM_DMABASE_CCMR1\n  *            @arg TIM_DMABASE_CCMR2\n  *            @arg TIM_DMABASE_CCER\n  *            @arg TIM_DMABASE_CNT\n  *            @arg TIM_DMABASE_PSC\n  *            @arg TIM_DMABASE_ARR\n  *            @arg TIM_DMABASE_RCR\n  *            @arg TIM_DMABASE_CCR1\n  *            @arg TIM_DMABASE_CCR2\n  *            @arg TIM_DMABASE_CCR3\n  *            @arg TIM_DMABASE_CCR4\n  *            @arg TIM_DMABASE_BDTR\n  * @param  BurstRequestSrc TIM DMA Request sources\n  *         This parameter can be one of the following values:\n  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source\n  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source\n  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source\n  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source\n  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source\n  *            @arg TIM_DMA_COM: TIM Commutation DMA source\n  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source\n  * @param  BurstBuffer The Buffer address.\n  * @param  BurstLength DMA Burst length. This parameter can be one value\n  *         between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.\n  * @param  DataLength Data length. This parameter can be one value\n  *         between 1 and 0xFFFF.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,\n                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer,\n                                                  uint32_t  BurstLength, uint32_t  DataLength)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\n  assert_param(IS_TIM_DMA_LENGTH(BurstLength));\n  assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));\n\n  if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)\n  {\n    if ((BurstBuffer == NULL) && (BurstLength > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;\n    }\n  }\n  else\n  {\n    /* nothing to do */\n  }\n  switch (BurstRequestSrc)\n  {\n    case TIM_DMA_UPDATE:\n    {\n      /* Set the DMA Period elapsed callbacks */\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC1:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC2:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC3:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_CC4:\n    {\n      /* Set the DMA capture callbacks */\n      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;\n      htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_COM:\n    {\n      /* Set the DMA commutation callbacks */\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback =  TIMEx_DMACommutationCplt;\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback =  TIMEx_DMACommutationHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    case TIM_DMA_TRIGGER:\n    {\n      /* Set the DMA trigger callbacks */\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,\n                         DataLength) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      break;\n    }\n    default:\n      break;\n  }\n\n  /* Configure the DMA Burst Mode */\n  htim->Instance->DCR = (BurstBaseAddress | BurstLength);\n\n  /* Enable the TIM DMA Request */\n  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stop the DMA burst reading\n  * @param  htim TIM handle\n  * @param  BurstRequestSrc TIM DMA Request sources to disable.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));\n\n  /* Abort the DMA transfer (at least disable the DMA stream) */\n  switch (BurstRequestSrc)\n  {\n    case TIM_DMA_UPDATE:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);\n      break;\n    }\n    case TIM_DMA_CC1:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n    case TIM_DMA_CC2:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n    case TIM_DMA_CC3:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n    case TIM_DMA_CC4:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);\n      break;\n    }\n    case TIM_DMA_COM:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);\n      break;\n    }\n    case TIM_DMA_TRIGGER:\n    {\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);\n      break;\n    }\n    default:\n      break;\n  }\n\n  /* Disable the TIM Update DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Generate a software event\n  * @param  htim TIM handle\n  * @param  EventSource specifies the event source.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source\n  *            @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source\n  *            @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source\n  *            @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source\n  *            @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source\n  *            @arg TIM_EVENTSOURCE_COM: Timer COM event source\n  *            @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source\n  *            @arg TIM_EVENTSOURCE_BREAK: Timer Break event source\n  * @note   Basic timers can only generate an update event.\n  * @note   TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.\n  * @note   TIM_EVENTSOURCE_BREAK are relevant only for timer instances\n  *         supporting a break input.\n  * @retval HAL status\n  */\n\nHAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_EVENT_SOURCE(EventSource));\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  /* Change the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Set the event sources */\n  htim->Instance->EGR = EventSource;\n\n  /* Change the TIM state */\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the OCRef clear feature\n  * @param  htim TIM handle\n  * @param  sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that\n  *         contains the OCREF clear feature and parameters for the TIM peripheral.\n  * @param  Channel specifies the TIM Channel\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1\n  *            @arg TIM_CHANNEL_2: TIM Channel 2\n  *            @arg TIM_CHANNEL_3: TIM Channel 3\n  *            @arg TIM_CHANNEL_4: TIM Channel 4\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,\n                                           TIM_ClearInputConfigTypeDef *sClearInputConfig,\n                                           uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  switch (sClearInputConfig->ClearInputSource)\n  {\n    case TIM_CLEARINPUTSOURCE_NONE:\n    {\n      /* Clear the OCREF clear selection bit and the the ETR Bits */\n      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));\n      break;\n    }\n\n    case TIM_CLEARINPUTSOURCE_ETR:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));\n      assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));\n      assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));\n\n      /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */\n      if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)\n      {\n        htim->State = HAL_TIM_STATE_READY;\n        __HAL_UNLOCK(htim);\n        return HAL_ERROR;\n      }\n\n      TIM_ETR_SetConfig(htim->Instance,\n                        sClearInputConfig->ClearInputPrescaler,\n                        sClearInputConfig->ClearInputPolarity,\n                        sClearInputConfig->ClearInputFilter);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\n      {\n        /* Enable the OCREF clear feature for Channel 1 */\n        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\n      }\n      else\n      {\n        /* Disable the OCREF clear feature for Channel 1 */\n        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);\n      }\n      break;\n    }\n    case TIM_CHANNEL_2:\n    {\n      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\n      {\n        /* Enable the OCREF clear feature for Channel 2 */\n        SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\n      }\n      else\n      {\n        /* Disable the OCREF clear feature for Channel 2 */\n        CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);\n      }\n      break;\n    }\n    case TIM_CHANNEL_3:\n    {\n      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\n      {\n        /* Enable the OCREF clear feature for Channel 3 */\n        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\n      }\n      else\n      {\n        /* Disable the OCREF clear feature for Channel 3 */\n        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);\n      }\n      break;\n    }\n    case TIM_CHANNEL_4:\n    {\n      if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)\n      {\n        /* Enable the OCREF clear feature for Channel 4 */\n        SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\n      }\n      else\n      {\n        /* Disable the OCREF clear feature for Channel 4 */\n        CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);\n      }\n      break;\n    }\n    default:\n      break;\n  }\n\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief   Configures the clock source to be used\n  * @param  htim TIM handle\n  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that\n  *         contains the clock source information for the TIM peripheral.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)\n{\n  uint32_t tmpsmcr;\n\n  /* Process Locked */\n  __HAL_LOCK(htim);\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));\n\n  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */\n  tmpsmcr = htim->Instance->SMCR;\n  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\n  htim->Instance->SMCR = tmpsmcr;\n\n  switch (sClockSourceConfig->ClockSource)\n  {\n    case TIM_CLOCKSOURCE_INTERNAL:\n    {\n      assert_param(IS_TIM_INSTANCE(htim->Instance));\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_ETRMODE1:\n    {\n      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/\n      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\n\n      /* Check ETR input conditioning related parameters */\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\n\n      /* Configure the ETR Clock source */\n      TIM_ETR_SetConfig(htim->Instance,\n                        sClockSourceConfig->ClockPrescaler,\n                        sClockSourceConfig->ClockPolarity,\n                        sClockSourceConfig->ClockFilter);\n\n      /* Select the External clock mode1 and the ETRF trigger */\n      tmpsmcr = htim->Instance->SMCR;\n      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);\n      /* Write to TIMx SMCR */\n      htim->Instance->SMCR = tmpsmcr;\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_ETRMODE2:\n    {\n      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/\n      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));\n\n      /* Check ETR input conditioning related parameters */\n      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\n\n      /* Configure the ETR Clock source */\n      TIM_ETR_SetConfig(htim->Instance,\n                        sClockSourceConfig->ClockPrescaler,\n                        sClockSourceConfig->ClockPolarity,\n                        sClockSourceConfig->ClockFilter);\n      /* Enable the External clock mode2 */\n      htim->Instance->SMCR |= TIM_SMCR_ECE;\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_TI1:\n    {\n      /* Check whether or not the timer instance supports external clock mode 1 */\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\n\n      /* Check TI1 input conditioning related parameters */\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\n\n      TIM_TI1_ConfigInputStage(htim->Instance,\n                               sClockSourceConfig->ClockPolarity,\n                               sClockSourceConfig->ClockFilter);\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_TI2:\n    {\n      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\n\n      /* Check TI2 input conditioning related parameters */\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\n\n      TIM_TI2_ConfigInputStage(htim->Instance,\n                               sClockSourceConfig->ClockPolarity,\n                               sClockSourceConfig->ClockFilter);\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_TI1ED:\n    {\n      /* Check whether or not the timer instance supports external clock mode 1 */\n      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));\n\n      /* Check TI1 input conditioning related parameters */\n      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));\n      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));\n\n      TIM_TI1_ConfigInputStage(htim->Instance,\n                               sClockSourceConfig->ClockPolarity,\n                               sClockSourceConfig->ClockFilter);\n      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);\n      break;\n    }\n\n    case TIM_CLOCKSOURCE_ITR0:\n    case TIM_CLOCKSOURCE_ITR1:\n    case TIM_CLOCKSOURCE_ITR2:\n    case TIM_CLOCKSOURCE_ITR3:\n      {\n        /* Check whether or not the timer instance supports internal trigger input */\n        assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));\n\n        TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);\n        break;\n      }\n\n    default:\n      break;\n  }\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input\n  *         or a XOR combination between CH1_input, CH2_input & CH3_input\n  * @param  htim TIM handle.\n  * @param  TI1_Selection Indicate whether or not channel 1 is connected to the\n  *         output of a XOR gate.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input\n  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3\n  *            pins are connected to the TI1 input (XOR combination)\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)\n{\n  uint32_t tmpcr2;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));\n\n  /* Get the TIMx CR2 register value */\n  tmpcr2 = htim->Instance->CR2;\n\n  /* Reset the TI1 selection */\n  tmpcr2 &= ~TIM_CR2_TI1S;\n\n  /* Set the TI1 selection */\n  tmpcr2 |= TI1_Selection;\n\n  /* Write to TIMxCR2 */\n  htim->Instance->CR2 = tmpcr2;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the TIM in Slave mode\n  * @param  htim TIM handle.\n  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\n  *         contains the selected trigger (internal trigger input, filtered\n  *         timer input or external trigger input) and the Slave mode\n  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\n\n  __HAL_LOCK(htim);\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\n  {\n    htim->State = HAL_TIM_STATE_READY;\n    __HAL_UNLOCK(htim);\n    return HAL_ERROR;\n  }\n\n  /* Disable Trigger Interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);\n\n  /* Disable Trigger DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\n\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the TIM in Slave mode in interrupt mode\n  * @param  htim TIM handle.\n  * @param  sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that\n  *         contains the selected trigger (internal trigger input, filtered\n  *         timer input or external trigger input) and the Slave mode\n  *         (Disable, Reset, Gated, Trigger, External clock mode 1).\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,\n                                                TIM_SlaveConfigTypeDef *sSlaveConfig)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));\n  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));\n\n  __HAL_LOCK(htim);\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)\n  {\n    htim->State = HAL_TIM_STATE_READY;\n    __HAL_UNLOCK(htim);\n    return HAL_ERROR;\n  }\n\n  /* Enable Trigger Interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);\n\n  /* Disable Trigger DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);\n\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Read the captured value from Capture Compare unit\n  * @param  htim TIM handle.\n  * @param  Channel TIM Channels to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected\n  * @retval Captured value\n  */\nuint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpreg = 0U;\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n\n      /* Return the capture 1 value */\n      tmpreg =  htim->Instance->CCR1;\n\n      break;\n    }\n    case TIM_CHANNEL_2:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n\n      /* Return the capture 2 value */\n      tmpreg =   htim->Instance->CCR2;\n\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));\n\n      /* Return the capture 3 value */\n      tmpreg =   htim->Instance->CCR3;\n\n      break;\n    }\n\n    case TIM_CHANNEL_4:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));\n\n      /* Return the capture 4 value */\n      tmpreg =   htim->Instance->CCR4;\n\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  return tmpreg;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions\n  *  @brief    TIM Callbacks functions\n  *\n@verbatim\n  ==============================================================================\n                        ##### TIM Callbacks functions #####\n  ==============================================================================\n [..]\n   This section provides TIM callback functions:\n   (+) TIM Period elapsed callback\n   (+) TIM Output Compare callback\n   (+) TIM Input capture callback\n   (+) TIM Trigger callback\n   (+) TIM Error callback\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Period elapsed callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PeriodElapsedCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Period elapsed half complete callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Output Compare callback in non-blocking mode\n  * @param  htim TIM OC handle\n  * @retval None\n  */\n__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Input Capture callback in non-blocking mode\n  * @param  htim TIM IC handle\n  * @retval None\n  */\n__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_IC_CaptureCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Input Capture half complete callback in non-blocking mode\n  * @param  htim TIM IC handle\n  * @retval None\n  */\n__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  PWM Pulse finished callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  PWM Pulse finished half complete callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Hall Trigger detection callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_TriggerCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Hall Trigger detection half complete callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Timer error callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIM_ErrorCallback could be implemented in the user file\n   */\n}\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  Register a User TIM callback to be used instead of the weak predefined callback\n  * @param htim tim handle\n  * @param CallbackID ID of the callback to be registered\n  *        This parameter can be one of the following values:\n  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\n  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\n  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\n  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\n  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\n  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\n  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\n  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\n  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\n  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\n  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\n  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\n  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\n  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\n  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\n  *          @param pCallback pointer to the callback function\n  *          @retval status\n  */\nHAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,\n                                           pTIM_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(htim);\n\n  if (htim->State == HAL_TIM_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_TIM_BASE_MSPINIT_CB_ID :\n        htim->Base_MspInitCallback                 = pCallback;\n        break;\n\n      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\n        htim->Base_MspDeInitCallback               = pCallback;\n        break;\n\n      case HAL_TIM_IC_MSPINIT_CB_ID :\n        htim->IC_MspInitCallback                   = pCallback;\n        break;\n\n      case HAL_TIM_IC_MSPDEINIT_CB_ID :\n        htim->IC_MspDeInitCallback                 = pCallback;\n        break;\n\n      case HAL_TIM_OC_MSPINIT_CB_ID :\n        htim->OC_MspInitCallback                   = pCallback;\n        break;\n\n      case HAL_TIM_OC_MSPDEINIT_CB_ID :\n        htim->OC_MspDeInitCallback                 = pCallback;\n        break;\n\n      case HAL_TIM_PWM_MSPINIT_CB_ID :\n        htim->PWM_MspInitCallback                  = pCallback;\n        break;\n\n      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\n        htim->PWM_MspDeInitCallback                = pCallback;\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\n        htim->OnePulse_MspInitCallback             = pCallback;\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\n        htim->OnePulse_MspDeInitCallback           = pCallback;\n        break;\n\n      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\n        htim->Encoder_MspInitCallback              = pCallback;\n        break;\n\n      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\n        htim->Encoder_MspDeInitCallback            = pCallback;\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\n        htim->HallSensor_MspInitCallback           = pCallback;\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\n        htim->HallSensor_MspDeInitCallback         = pCallback;\n        break;\n\n      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\n        htim->PeriodElapsedCallback                = pCallback;\n        break;\n\n      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\n        htim->PeriodElapsedHalfCpltCallback        = pCallback;\n        break;\n\n      case HAL_TIM_TRIGGER_CB_ID :\n        htim->TriggerCallback                      = pCallback;\n        break;\n\n      case HAL_TIM_TRIGGER_HALF_CB_ID :\n        htim->TriggerHalfCpltCallback              = pCallback;\n        break;\n\n      case HAL_TIM_IC_CAPTURE_CB_ID :\n        htim->IC_CaptureCallback                   = pCallback;\n        break;\n\n      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\n        htim->IC_CaptureHalfCpltCallback           = pCallback;\n        break;\n\n      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\n        htim->OC_DelayElapsedCallback              = pCallback;\n        break;\n\n      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\n        htim->PWM_PulseFinishedCallback            = pCallback;\n        break;\n\n      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\n        htim->PWM_PulseFinishedHalfCpltCallback    = pCallback;\n        break;\n\n      case HAL_TIM_ERROR_CB_ID :\n        htim->ErrorCallback                        = pCallback;\n        break;\n\n      case HAL_TIM_COMMUTATION_CB_ID :\n        htim->CommutationCallback                  = pCallback;\n        break;\n\n      case HAL_TIM_COMMUTATION_HALF_CB_ID :\n        htim->CommutationHalfCpltCallback          = pCallback;\n        break;\n\n      case HAL_TIM_BREAK_CB_ID :\n        htim->BreakCallback                        = pCallback;\n        break;\n\n      default :\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_TIM_BASE_MSPINIT_CB_ID :\n        htim->Base_MspInitCallback         = pCallback;\n        break;\n\n      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\n        htim->Base_MspDeInitCallback       = pCallback;\n        break;\n\n      case HAL_TIM_IC_MSPINIT_CB_ID :\n        htim->IC_MspInitCallback           = pCallback;\n        break;\n\n      case HAL_TIM_IC_MSPDEINIT_CB_ID :\n        htim->IC_MspDeInitCallback         = pCallback;\n        break;\n\n      case HAL_TIM_OC_MSPINIT_CB_ID :\n        htim->OC_MspInitCallback           = pCallback;\n        break;\n\n      case HAL_TIM_OC_MSPDEINIT_CB_ID :\n        htim->OC_MspDeInitCallback         = pCallback;\n        break;\n\n      case HAL_TIM_PWM_MSPINIT_CB_ID :\n        htim->PWM_MspInitCallback          = pCallback;\n        break;\n\n      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\n        htim->PWM_MspDeInitCallback        = pCallback;\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\n        htim->OnePulse_MspInitCallback     = pCallback;\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\n        htim->OnePulse_MspDeInitCallback   = pCallback;\n        break;\n\n      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\n        htim->Encoder_MspInitCallback      = pCallback;\n        break;\n\n      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\n        htim->Encoder_MspDeInitCallback    = pCallback;\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\n        htim->HallSensor_MspInitCallback   = pCallback;\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\n        htim->HallSensor_MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister a TIM callback\n  *         TIM callback is redirected to the weak predefined callback\n  * @param htim tim handle\n  * @param CallbackID ID of the callback to be unregistered\n  *        This parameter can be one of the following values:\n  *          @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID\n  *          @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID\n  *          @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID\n  *          @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID\n  *          @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID\n  *          @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID\n  *          @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID\n  *          @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID\n  *          @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID\n  *          @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID\n  *          @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID\n  *          @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID\n  *          @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID\n  *          @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID\n  *          @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID\n  *          @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID\n  *          @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID\n  *          @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID\n  *          @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID\n  *          @retval status\n  */\nHAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(htim);\n\n  if (htim->State == HAL_TIM_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_TIM_BASE_MSPINIT_CB_ID :\n        htim->Base_MspInitCallback              = HAL_TIM_Base_MspInit;                      /* Legacy weak Base MspInit Callback */\n        break;\n\n      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\n        htim->Base_MspDeInitCallback            = HAL_TIM_Base_MspDeInit;                    /* Legacy weak Base Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_IC_MSPINIT_CB_ID :\n        htim->IC_MspInitCallback                = HAL_TIM_IC_MspInit;                        /* Legacy weak IC Msp Init Callback */\n        break;\n\n      case HAL_TIM_IC_MSPDEINIT_CB_ID :\n        htim->IC_MspDeInitCallback              = HAL_TIM_IC_MspDeInit;                      /* Legacy weak IC Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_OC_MSPINIT_CB_ID :\n        htim->OC_MspInitCallback                = HAL_TIM_OC_MspInit;                        /* Legacy weak OC Msp Init Callback */\n        break;\n\n      case HAL_TIM_OC_MSPDEINIT_CB_ID :\n        htim->OC_MspDeInitCallback              = HAL_TIM_OC_MspDeInit;                      /* Legacy weak OC Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_PWM_MSPINIT_CB_ID :\n        htim->PWM_MspInitCallback               = HAL_TIM_PWM_MspInit;                       /* Legacy weak PWM Msp Init Callback */\n        break;\n\n      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\n        htim->PWM_MspDeInitCallback             = HAL_TIM_PWM_MspDeInit;                     /* Legacy weak PWM Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\n        htim->OnePulse_MspInitCallback          = HAL_TIM_OnePulse_MspInit;                  /* Legacy weak One Pulse Msp Init Callback */\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\n        htim->OnePulse_MspDeInitCallback        = HAL_TIM_OnePulse_MspDeInit;                /* Legacy weak One Pulse Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\n        htim->Encoder_MspInitCallback           = HAL_TIM_Encoder_MspInit;                   /* Legacy weak Encoder Msp Init Callback */\n        break;\n\n      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\n        htim->Encoder_MspDeInitCallback         = HAL_TIM_Encoder_MspDeInit;                 /* Legacy weak Encoder Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\n        htim->HallSensor_MspInitCallback        = HAL_TIMEx_HallSensor_MspInit;              /* Legacy weak Hall Sensor Msp Init Callback */\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\n        htim->HallSensor_MspDeInitCallback      = HAL_TIMEx_HallSensor_MspDeInit;            /* Legacy weak Hall Sensor Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_PERIOD_ELAPSED_CB_ID :\n        htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak Period Elapsed Callback */\n        break;\n\n      case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :\n        htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak Period Elapsed half complete Callback */\n        break;\n\n      case HAL_TIM_TRIGGER_CB_ID :\n        htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak Trigger Callback */\n        break;\n\n      case HAL_TIM_TRIGGER_HALF_CB_ID :\n        htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak Trigger half complete Callback */\n        break;\n\n      case HAL_TIM_IC_CAPTURE_CB_ID :\n        htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC Capture Callback */\n        break;\n\n      case HAL_TIM_IC_CAPTURE_HALF_CB_ID :\n        htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC Capture half complete Callback */\n        break;\n\n      case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :\n        htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC Delay Elapsed Callback */\n        break;\n\n      case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :\n        htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM Pulse Finished Callback */\n        break;\n\n      case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :\n        htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */\n        break;\n\n      case HAL_TIM_ERROR_CB_ID :\n        htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak Error Callback */\n        break;\n\n      case HAL_TIM_COMMUTATION_CB_ID :\n        htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak Commutation Callback */\n        break;\n\n      case HAL_TIM_COMMUTATION_HALF_CB_ID :\n        htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak Commutation half complete Callback */\n        break;\n\n      case HAL_TIM_BREAK_CB_ID :\n        htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak Break Callback */\n        break;\n\n      default :\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_TIM_BASE_MSPINIT_CB_ID :\n        htim->Base_MspInitCallback         = HAL_TIM_Base_MspInit;              /* Legacy weak Base MspInit Callback */\n        break;\n\n      case HAL_TIM_BASE_MSPDEINIT_CB_ID :\n        htim->Base_MspDeInitCallback       = HAL_TIM_Base_MspDeInit;            /* Legacy weak Base Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_IC_MSPINIT_CB_ID :\n        htim->IC_MspInitCallback           = HAL_TIM_IC_MspInit;                /* Legacy weak IC Msp Init Callback */\n        break;\n\n      case HAL_TIM_IC_MSPDEINIT_CB_ID :\n        htim->IC_MspDeInitCallback         = HAL_TIM_IC_MspDeInit;              /* Legacy weak IC Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_OC_MSPINIT_CB_ID :\n        htim->OC_MspInitCallback           = HAL_TIM_OC_MspInit;                /* Legacy weak OC Msp Init Callback */\n        break;\n\n      case HAL_TIM_OC_MSPDEINIT_CB_ID :\n        htim->OC_MspDeInitCallback         = HAL_TIM_OC_MspDeInit;              /* Legacy weak OC Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_PWM_MSPINIT_CB_ID :\n        htim->PWM_MspInitCallback          = HAL_TIM_PWM_MspInit;               /* Legacy weak PWM Msp Init Callback */\n        break;\n\n      case HAL_TIM_PWM_MSPDEINIT_CB_ID :\n        htim->PWM_MspDeInitCallback        = HAL_TIM_PWM_MspDeInit;             /* Legacy weak PWM Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :\n        htim->OnePulse_MspInitCallback     = HAL_TIM_OnePulse_MspInit;          /* Legacy weak One Pulse Msp Init Callback */\n        break;\n\n      case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :\n        htim->OnePulse_MspDeInitCallback   = HAL_TIM_OnePulse_MspDeInit;        /* Legacy weak One Pulse Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_ENCODER_MSPINIT_CB_ID :\n        htim->Encoder_MspInitCallback      = HAL_TIM_Encoder_MspInit;           /* Legacy weak Encoder Msp Init Callback */\n        break;\n\n      case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :\n        htim->Encoder_MspDeInitCallback    = HAL_TIM_Encoder_MspDeInit;         /* Legacy weak Encoder Msp DeInit Callback */\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :\n        htim->HallSensor_MspInitCallback   = HAL_TIMEx_HallSensor_MspInit;      /* Legacy weak Hall Sensor Msp Init Callback */\n        break;\n\n      case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :\n        htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;    /* Legacy weak Hall Sensor Msp DeInit Callback */\n        break;\n\n      default :\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return status;\n}\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions\n  *  @brief   TIM Peripheral State functions\n  *\n@verbatim\n  ==============================================================================\n                        ##### Peripheral State functions #####\n  ==============================================================================\n    [..]\n    This subsection permits to get in run-time the status of the peripheral\n    and the data flow.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the TIM Base handle state.\n  * @param  htim TIM Base handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM OC handle state.\n  * @param  htim TIM Output Compare handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM PWM handle state.\n  * @param  htim TIM handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM Input Capture handle state.\n  * @param  htim TIM IC handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM One Pulse Mode handle state.\n  * @param  htim TIM OPM handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM Encoder Mode handle state.\n  * @param  htim TIM Encoder Interface handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return the TIM Encoder Mode handle state.\n  * @param  htim TIM handle\n  * @retval Active channel\n  */\nHAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)\n{\n  return htim->Channel;\n}\n\n/**\n  * @brief  Return actual state of the TIM channel.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1\n  *            @arg TIM_CHANNEL_2: TIM Channel 2\n  *            @arg TIM_CHANNEL_3: TIM Channel 3\n  *            @arg TIM_CHANNEL_4: TIM Channel 4\n  *            @arg TIM_CHANNEL_5: TIM Channel 5\n  *            @arg TIM_CHANNEL_6: TIM Channel 6\n  * @retval TIM Channel state\n  */\nHAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim,  uint32_t Channel)\n{\n  HAL_TIM_ChannelStateTypeDef channel_state;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));\n\n  channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);\n\n  return channel_state;\n}\n\n/**\n  * @brief  Return actual state of a DMA burst operation.\n  * @param  htim TIM handle\n  * @retval DMA burst state\n  */\nHAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));\n\n  return htim->DMABurstState;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @defgroup TIM_Private_Functions TIM Private Functions\n  * @{\n  */\n\n/**\n  * @brief  TIM DMA error callback\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIM_DMAError(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n    TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else\n  {\n    htim->State = HAL_TIM_STATE_READY;\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->ErrorCallback(htim);\n#else\n  HAL_TIM_ErrorCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA Delay Pulse complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->PWM_PulseFinishedCallback(htim);\n#else\n  HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA Delay Pulse half complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->PWM_PulseFinishedHalfCpltCallback(htim);\n#else\n  HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA Capture complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->IC_CaptureCallback(htim);\n#else\n  HAL_TIM_IC_CaptureCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA Capture half complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->IC_CaptureHalfCpltCallback(htim);\n#else\n  HAL_TIM_IC_CaptureHalfCpltCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA Period Elapse complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)\n  {\n    htim->State = HAL_TIM_STATE_READY;\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->PeriodElapsedCallback(htim);\n#else\n  HAL_TIM_PeriodElapsedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  TIM DMA Period Elapse half complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->PeriodElapsedHalfCpltCallback(htim);\n#else\n  HAL_TIM_PeriodElapsedHalfCpltCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  TIM DMA Trigger callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)\n  {\n    htim->State = HAL_TIM_STATE_READY;\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->TriggerCallback(htim);\n#else\n  HAL_TIM_TriggerCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  TIM DMA Trigger half complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->TriggerHalfCpltCallback(htim);\n#else\n  HAL_TIM_TriggerHalfCpltCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  Time Base configuration\n  * @param  TIMx TIM peripheral\n  * @param  Structure TIM Base configuration structure\n  * @retval None\n  */\nvoid TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)\n{\n  uint32_t tmpcr1;\n  tmpcr1 = TIMx->CR1;\n\n  /* Set TIM Time Base Unit parameters ---------------------------------------*/\n  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))\n  {\n    /* Select the Counter Mode */\n    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);\n    tmpcr1 |= Structure->CounterMode;\n  }\n\n  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))\n  {\n    /* Set the clock division */\n    tmpcr1 &= ~TIM_CR1_CKD;\n    tmpcr1 |= (uint32_t)Structure->ClockDivision;\n  }\n\n  /* Set the auto-reload preload */\n  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);\n\n  TIMx->CR1 = tmpcr1;\n\n  /* Set the Autoreload value */\n  TIMx->ARR = (uint32_t)Structure->Period ;\n\n  /* Set the Prescaler value */\n  TIMx->PSC = Structure->Prescaler;\n\n  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))\n  {\n    /* Set the Repetition Counter value */\n    TIMx->RCR = Structure->RepetitionCounter;\n  }\n\n  /* Generate an update event to reload the Prescaler\n     and the repetition counter (only for advanced timer) value immediately */\n  TIMx->EGR = TIM_EGR_UG;\n}\n\n/**\n  * @brief  Timer Output Compare 1 configuration\n  * @param  TIMx to select the TIM peripheral\n  * @param  OC_Config The output configuration structure\n  * @retval None\n  */\nstatic void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\n{\n  uint32_t tmpccmrx;\n  uint32_t tmpccer;\n  uint32_t tmpcr2;\n\n  /* Disable the Channel 1: Reset the CC1E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC1E;\n\n  /* Get the TIMx CCER register value */\n  tmpccer = TIMx->CCER;\n  /* Get the TIMx CR2 register value */\n  tmpcr2 =  TIMx->CR2;\n\n  /* Get the TIMx CCMR1 register value */\n  tmpccmrx = TIMx->CCMR1;\n\n  /* Reset the Output Compare Mode Bits */\n  tmpccmrx &= ~TIM_CCMR1_OC1M;\n  tmpccmrx &= ~TIM_CCMR1_CC1S;\n  /* Select the Output Compare Mode */\n  tmpccmrx |= OC_Config->OCMode;\n\n  /* Reset the Output Polarity level */\n  tmpccer &= ~TIM_CCER_CC1P;\n  /* Set the Output Compare Polarity */\n  tmpccer |= OC_Config->OCPolarity;\n\n  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))\n  {\n    /* Check parameters */\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\n\n    /* Reset the Output N Polarity level */\n    tmpccer &= ~TIM_CCER_CC1NP;\n    /* Set the Output N Polarity */\n    tmpccer |= OC_Config->OCNPolarity;\n    /* Reset the Output N State */\n    tmpccer &= ~TIM_CCER_CC1NE;\n  }\n\n  if (IS_TIM_BREAK_INSTANCE(TIMx))\n  {\n    /* Check parameters */\n    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\n\n    /* Reset the Output Compare and Output Compare N IDLE State */\n    tmpcr2 &= ~TIM_CR2_OIS1;\n    tmpcr2 &= ~TIM_CR2_OIS1N;\n    /* Set the Output Idle state */\n    tmpcr2 |= OC_Config->OCIdleState;\n    /* Set the Output N Idle state */\n    tmpcr2 |= OC_Config->OCNIdleState;\n  }\n\n  /* Write to TIMx CR2 */\n  TIMx->CR2 = tmpcr2;\n\n  /* Write to TIMx CCMR1 */\n  TIMx->CCMR1 = tmpccmrx;\n\n  /* Set the Capture Compare Register value */\n  TIMx->CCR1 = OC_Config->Pulse;\n\n  /* Write to TIMx CCER */\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Timer Output Compare 2 configuration\n  * @param  TIMx to select the TIM peripheral\n  * @param  OC_Config The output configuration structure\n  * @retval None\n  */\nvoid TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\n{\n  uint32_t tmpccmrx;\n  uint32_t tmpccer;\n  uint32_t tmpcr2;\n\n  /* Disable the Channel 2: Reset the CC2E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC2E;\n\n  /* Get the TIMx CCER register value */\n  tmpccer = TIMx->CCER;\n  /* Get the TIMx CR2 register value */\n  tmpcr2 =  TIMx->CR2;\n\n  /* Get the TIMx CCMR1 register value */\n  tmpccmrx = TIMx->CCMR1;\n\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\n  tmpccmrx &= ~TIM_CCMR1_OC2M;\n  tmpccmrx &= ~TIM_CCMR1_CC2S;\n\n  /* Select the Output Compare Mode */\n  tmpccmrx |= (OC_Config->OCMode << 8U);\n\n  /* Reset the Output Polarity level */\n  tmpccer &= ~TIM_CCER_CC2P;\n  /* Set the Output Compare Polarity */\n  tmpccer |= (OC_Config->OCPolarity << 4U);\n\n  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))\n  {\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\n\n    /* Reset the Output N Polarity level */\n    tmpccer &= ~TIM_CCER_CC2NP;\n    /* Set the Output N Polarity */\n    tmpccer |= (OC_Config->OCNPolarity << 4U);\n    /* Reset the Output N State */\n    tmpccer &= ~TIM_CCER_CC2NE;\n\n  }\n\n  if (IS_TIM_BREAK_INSTANCE(TIMx))\n  {\n    /* Check parameters */\n    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\n\n    /* Reset the Output Compare and Output Compare N IDLE State */\n    tmpcr2 &= ~TIM_CR2_OIS2;\n    tmpcr2 &= ~TIM_CR2_OIS2N;\n    /* Set the Output Idle state */\n    tmpcr2 |= (OC_Config->OCIdleState << 2U);\n    /* Set the Output N Idle state */\n    tmpcr2 |= (OC_Config->OCNIdleState << 2U);\n  }\n\n  /* Write to TIMx CR2 */\n  TIMx->CR2 = tmpcr2;\n\n  /* Write to TIMx CCMR1 */\n  TIMx->CCMR1 = tmpccmrx;\n\n  /* Set the Capture Compare Register value */\n  TIMx->CCR2 = OC_Config->Pulse;\n\n  /* Write to TIMx CCER */\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Timer Output Compare 3 configuration\n  * @param  TIMx to select the TIM peripheral\n  * @param  OC_Config The output configuration structure\n  * @retval None\n  */\nstatic void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\n{\n  uint32_t tmpccmrx;\n  uint32_t tmpccer;\n  uint32_t tmpcr2;\n\n  /* Disable the Channel 3: Reset the CC2E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC3E;\n\n  /* Get the TIMx CCER register value */\n  tmpccer = TIMx->CCER;\n  /* Get the TIMx CR2 register value */\n  tmpcr2 =  TIMx->CR2;\n\n  /* Get the TIMx CCMR2 register value */\n  tmpccmrx = TIMx->CCMR2;\n\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\n  tmpccmrx &= ~TIM_CCMR2_OC3M;\n  tmpccmrx &= ~TIM_CCMR2_CC3S;\n  /* Select the Output Compare Mode */\n  tmpccmrx |= OC_Config->OCMode;\n\n  /* Reset the Output Polarity level */\n  tmpccer &= ~TIM_CCER_CC3P;\n  /* Set the Output Compare Polarity */\n  tmpccer |= (OC_Config->OCPolarity << 8U);\n\n  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))\n  {\n    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));\n\n    /* Reset the Output N Polarity level */\n    tmpccer &= ~TIM_CCER_CC3NP;\n    /* Set the Output N Polarity */\n    tmpccer |= (OC_Config->OCNPolarity << 8U);\n    /* Reset the Output N State */\n    tmpccer &= ~TIM_CCER_CC3NE;\n  }\n\n  if (IS_TIM_BREAK_INSTANCE(TIMx))\n  {\n    /* Check parameters */\n    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\n\n    /* Reset the Output Compare and Output Compare N IDLE State */\n    tmpcr2 &= ~TIM_CR2_OIS3;\n    tmpcr2 &= ~TIM_CR2_OIS3N;\n    /* Set the Output Idle state */\n    tmpcr2 |= (OC_Config->OCIdleState << 4U);\n    /* Set the Output N Idle state */\n    tmpcr2 |= (OC_Config->OCNIdleState << 4U);\n  }\n\n  /* Write to TIMx CR2 */\n  TIMx->CR2 = tmpcr2;\n\n  /* Write to TIMx CCMR2 */\n  TIMx->CCMR2 = tmpccmrx;\n\n  /* Set the Capture Compare Register value */\n  TIMx->CCR3 = OC_Config->Pulse;\n\n  /* Write to TIMx CCER */\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Timer Output Compare 4 configuration\n  * @param  TIMx to select the TIM peripheral\n  * @param  OC_Config The output configuration structure\n  * @retval None\n  */\nstatic void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)\n{\n  uint32_t tmpccmrx;\n  uint32_t tmpccer;\n  uint32_t tmpcr2;\n\n  /* Disable the Channel 4: Reset the CC4E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC4E;\n\n  /* Get the TIMx CCER register value */\n  tmpccer = TIMx->CCER;\n  /* Get the TIMx CR2 register value */\n  tmpcr2 =  TIMx->CR2;\n\n  /* Get the TIMx CCMR2 register value */\n  tmpccmrx = TIMx->CCMR2;\n\n  /* Reset the Output Compare mode and Capture/Compare selection Bits */\n  tmpccmrx &= ~TIM_CCMR2_OC4M;\n  tmpccmrx &= ~TIM_CCMR2_CC4S;\n\n  /* Select the Output Compare Mode */\n  tmpccmrx |= (OC_Config->OCMode << 8U);\n\n  /* Reset the Output Polarity level */\n  tmpccer &= ~TIM_CCER_CC4P;\n  /* Set the Output Compare Polarity */\n  tmpccer |= (OC_Config->OCPolarity << 12U);\n\n  if (IS_TIM_BREAK_INSTANCE(TIMx))\n  {\n    /* Check parameters */\n    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));\n\n    /* Reset the Output Compare IDLE State */\n    tmpcr2 &= ~TIM_CR2_OIS4;\n\n    /* Set the Output Idle state */\n    tmpcr2 |= (OC_Config->OCIdleState << 6U);\n  }\n\n  /* Write to TIMx CR2 */\n  TIMx->CR2 = tmpcr2;\n\n  /* Write to TIMx CCMR2 */\n  TIMx->CCMR2 = tmpccmrx;\n\n  /* Set the Capture Compare Register value */\n  TIMx->CCR4 = OC_Config->Pulse;\n\n  /* Write to TIMx CCER */\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Slave Timer configuration function\n  * @param  htim TIM handle\n  * @param  sSlaveConfig Slave timer configuration\n  * @retval None\n  */\nstatic HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,\n                                                  TIM_SlaveConfigTypeDef *sSlaveConfig)\n{\n  uint32_t tmpsmcr;\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Get the TIMx SMCR register value */\n  tmpsmcr = htim->Instance->SMCR;\n\n  /* Reset the Trigger Selection Bits */\n  tmpsmcr &= ~TIM_SMCR_TS;\n  /* Set the Input Trigger source */\n  tmpsmcr |= sSlaveConfig->InputTrigger;\n\n  /* Reset the slave mode Bits */\n  tmpsmcr &= ~TIM_SMCR_SMS;\n  /* Set the slave mode */\n  tmpsmcr |= sSlaveConfig->SlaveMode;\n\n  /* Write to TIMx SMCR */\n  htim->Instance->SMCR = tmpsmcr;\n\n  /* Configure the trigger prescaler, filter, and polarity */\n  switch (sSlaveConfig->InputTrigger)\n  {\n    case TIM_TS_ETRF:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));\n      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\n      /* Configure the ETR Trigger source */\n      TIM_ETR_SetConfig(htim->Instance,\n                        sSlaveConfig->TriggerPrescaler,\n                        sSlaveConfig->TriggerPolarity,\n                        sSlaveConfig->TriggerFilter);\n      break;\n    }\n\n    case TIM_TS_TI1F_ED:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\n\n      if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED)\n      {\n        return HAL_ERROR;\n      }\n\n      /* Disable the Channel 1: Reset the CC1E Bit */\n      tmpccer = htim->Instance->CCER;\n      htim->Instance->CCER &= ~TIM_CCER_CC1E;\n      tmpccmr1 = htim->Instance->CCMR1;\n\n      /* Set the filter */\n      tmpccmr1 &= ~TIM_CCMR1_IC1F;\n      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);\n\n      /* Write to TIMx CCMR1 and CCER registers */\n      htim->Instance->CCMR1 = tmpccmr1;\n      htim->Instance->CCER = tmpccer;\n      break;\n    }\n\n    case TIM_TS_TI1FP1:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\n\n      /* Configure TI1 Filter and Polarity */\n      TIM_TI1_ConfigInputStage(htim->Instance,\n                               sSlaveConfig->TriggerPolarity,\n                               sSlaveConfig->TriggerFilter);\n      break;\n    }\n\n    case TIM_TS_TI2FP2:\n    {\n      /* Check the parameters */\n      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));\n      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));\n\n      /* Configure TI2 Filter and Polarity */\n      TIM_TI2_ConfigInputStage(htim->Instance,\n                               sSlaveConfig->TriggerPolarity,\n                               sSlaveConfig->TriggerFilter);\n      break;\n    }\n\n    case TIM_TS_ITR0:\n    case TIM_TS_ITR1:\n    case TIM_TS_ITR2:\n    case TIM_TS_ITR3:\n      {\n        /* Check the parameter */\n        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));\n        break;\n      }\n\n    default:\n      break;\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configure the TI1 as Input.\n  * @param  TIMx to select the TIM peripheral.\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICSelection specifies the input to be used.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.\n  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.\n  *            @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @retval None\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1\n  *       (on channel2 path) is used as the input signal. Therefore CCMR1 must be\n  *        protected against un-initialized filter and polarity values.\n  */\nvoid TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                       uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 1: Reset the CC1E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC1E;\n  tmpccmr1 = TIMx->CCMR1;\n  tmpccer = TIMx->CCER;\n\n  /* Select the Input */\n  if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)\n  {\n    tmpccmr1 &= ~TIM_CCMR1_CC1S;\n    tmpccmr1 |= TIM_ICSelection;\n  }\n  else\n  {\n    tmpccmr1 |= TIM_CCMR1_CC1S_0;\n  }\n\n  /* Set the filter */\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\n  tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);\n\n  /* Select the Polarity and set the CC1E Bit */\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\n  tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));\n\n  /* Write to TIMx CCMR1 and CCER registers */\n  TIMx->CCMR1 = tmpccmr1;\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Configure the Polarity and Filter for TI1.\n  * @param  TIMx to select the TIM peripheral.\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @retval None\n  */\nstatic void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 1: Reset the CC1E Bit */\n  tmpccer = TIMx->CCER;\n  TIMx->CCER &= ~TIM_CCER_CC1E;\n  tmpccmr1 = TIMx->CCMR1;\n\n  /* Set the filter */\n  tmpccmr1 &= ~TIM_CCMR1_IC1F;\n  tmpccmr1 |= (TIM_ICFilter << 4U);\n\n  /* Select the Polarity and set the CC1E Bit */\n  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);\n  tmpccer |= TIM_ICPolarity;\n\n  /* Write to TIMx CCMR1 and CCER registers */\n  TIMx->CCMR1 = tmpccmr1;\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Configure the TI2 as Input.\n  * @param  TIMx to select the TIM peripheral\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICSelection specifies the input to be used.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.\n  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.\n  *            @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @retval None\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2\n  *       (on channel1 path) is used as the input signal. Therefore CCMR1 must be\n  *        protected against un-initialized filter and polarity values.\n  */\nstatic void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 2: Reset the CC2E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC2E;\n  tmpccmr1 = TIMx->CCMR1;\n  tmpccer = TIMx->CCER;\n\n  /* Select the Input */\n  tmpccmr1 &= ~TIM_CCMR1_CC2S;\n  tmpccmr1 |= (TIM_ICSelection << 8U);\n\n  /* Set the filter */\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\n  tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);\n\n  /* Select the Polarity and set the CC2E Bit */\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\n  tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));\n\n  /* Write to TIMx CCMR1 and CCER registers */\n  TIMx->CCMR1 = tmpccmr1 ;\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Configure the Polarity and Filter for TI2.\n  * @param  TIMx to select the TIM peripheral.\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @retval None\n  */\nstatic void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr1;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 2: Reset the CC2E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC2E;\n  tmpccmr1 = TIMx->CCMR1;\n  tmpccer = TIMx->CCER;\n\n  /* Set the filter */\n  tmpccmr1 &= ~TIM_CCMR1_IC2F;\n  tmpccmr1 |= (TIM_ICFilter << 12U);\n\n  /* Select the Polarity and set the CC2E Bit */\n  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);\n  tmpccer |= (TIM_ICPolarity << 4U);\n\n  /* Write to TIMx CCMR1 and CCER registers */\n  TIMx->CCMR1 = tmpccmr1 ;\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Configure the TI3 as Input.\n  * @param  TIMx to select the TIM peripheral\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICSelection specifies the input to be used.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.\n  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.\n  *            @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @retval None\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\n  *        protected against un-initialized filter and polarity values.\n  */\nstatic void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr2;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 3: Reset the CC3E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC3E;\n  tmpccmr2 = TIMx->CCMR2;\n  tmpccer = TIMx->CCER;\n\n  /* Select the Input */\n  tmpccmr2 &= ~TIM_CCMR2_CC3S;\n  tmpccmr2 |= TIM_ICSelection;\n\n  /* Set the filter */\n  tmpccmr2 &= ~TIM_CCMR2_IC3F;\n  tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);\n\n  /* Select the Polarity and set the CC3E Bit */\n  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);\n  tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));\n\n  /* Write to TIMx CCMR2 and CCER registers */\n  TIMx->CCMR2 = tmpccmr2;\n  TIMx->CCER = tmpccer;\n}\n\n/**\n  * @brief  Configure the TI4 as Input.\n  * @param  TIMx to select the TIM peripheral\n  * @param  TIM_ICPolarity The Input Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICPOLARITY_RISING\n  *            @arg TIM_ICPOLARITY_FALLING\n  *            @arg TIM_ICPOLARITY_BOTHEDGE\n  * @param  TIM_ICSelection specifies the input to be used.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.\n  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.\n  *            @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.\n  * @param  TIM_ICFilter Specifies the Input Capture Filter.\n  *          This parameter must be a value between 0x00 and 0x0F.\n  * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3\n  *       (on channel1 path) is used as the input signal. Therefore CCMR2 must be\n  *        protected against un-initialized filter and polarity values.\n  * @retval None\n  */\nstatic void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,\n                              uint32_t TIM_ICFilter)\n{\n  uint32_t tmpccmr2;\n  uint32_t tmpccer;\n\n  /* Disable the Channel 4: Reset the CC4E Bit */\n  TIMx->CCER &= ~TIM_CCER_CC4E;\n  tmpccmr2 = TIMx->CCMR2;\n  tmpccer = TIMx->CCER;\n\n  /* Select the Input */\n  tmpccmr2 &= ~TIM_CCMR2_CC4S;\n  tmpccmr2 |= (TIM_ICSelection << 8U);\n\n  /* Set the filter */\n  tmpccmr2 &= ~TIM_CCMR2_IC4F;\n  tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);\n\n  /* Select the Polarity and set the CC4E Bit */\n  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);\n  tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));\n\n  /* Write to TIMx CCMR2 and CCER registers */\n  TIMx->CCMR2 = tmpccmr2;\n  TIMx->CCER = tmpccer ;\n}\n\n/**\n  * @brief  Selects the Input Trigger source\n  * @param  TIMx to select the TIM peripheral\n  * @param  InputTriggerSource The Input Trigger source.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_TS_ITR0: Internal Trigger 0\n  *            @arg TIM_TS_ITR1: Internal Trigger 1\n  *            @arg TIM_TS_ITR2: Internal Trigger 2\n  *            @arg TIM_TS_ITR3: Internal Trigger 3\n  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector\n  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1\n  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2\n  *            @arg TIM_TS_ETRF: External Trigger input\n  * @retval None\n  */\nstatic void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)\n{\n  uint32_t tmpsmcr;\n\n  /* Get the TIMx SMCR register value */\n  tmpsmcr = TIMx->SMCR;\n  /* Reset the TS Bits */\n  tmpsmcr &= ~TIM_SMCR_TS;\n  /* Set the Input Trigger source and the slave mode*/\n  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);\n  /* Write to TIMx SMCR */\n  TIMx->SMCR = tmpsmcr;\n}\n/**\n  * @brief  Configures the TIMx External Trigger (ETR).\n  * @param  TIMx to select the TIM peripheral\n  * @param  TIM_ExtTRGPrescaler The external Trigger Prescaler.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.\n  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.\n  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.\n  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.\n  * @param  TIM_ExtTRGPolarity The external Trigger Polarity.\n  *          This parameter can be one of the following values:\n  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.\n  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.\n  * @param  ExtTRGFilter External Trigger Filter.\n  *          This parameter must be a value between 0x00 and 0x0F\n  * @retval None\n  */\nvoid TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,\n                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)\n{\n  uint32_t tmpsmcr;\n\n  tmpsmcr = TIMx->SMCR;\n\n  /* Reset the ETR Bits */\n  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);\n\n  /* Set the Prescaler, the Filter value and the Polarity */\n  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));\n\n  /* Write to TIMx SMCR */\n  TIMx->SMCR = tmpsmcr;\n}\n\n/**\n  * @brief  Enables or disables the TIM Capture Compare Channel x.\n  * @param  TIMx to select the TIM peripheral\n  * @param  Channel specifies the TIM Channel\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1\n  *            @arg TIM_CHANNEL_2: TIM Channel 2\n  *            @arg TIM_CHANNEL_3: TIM Channel 3\n  *            @arg TIM_CHANNEL_4: TIM Channel 4\n  * @param  ChannelState specifies the TIM Channel CCxE bit new state.\n  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.\n  * @retval None\n  */\nvoid TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)\n{\n  uint32_t tmp;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CC1_INSTANCE(TIMx));\n  assert_param(IS_TIM_CHANNELS(Channel));\n\n  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\n\n  /* Reset the CCxE Bit */\n  TIMx->CCER &= ~tmp;\n\n  /* Set or reset the CCxE Bit */\n  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\n}\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  Reset interrupt callbacks to the legacy weak callbacks.\n  * @param  htim pointer to a TIM_HandleTypeDef structure that contains\n  *                the configuration information for TIM module.\n  * @retval None\n  */\nvoid TIM_ResetCallback(TIM_HandleTypeDef *htim)\n{\n  /* Reset the TIM callback to the legacy weak callbacks */\n  htim->PeriodElapsedCallback             = HAL_TIM_PeriodElapsedCallback;             /* Legacy weak PeriodElapsedCallback             */\n  htim->PeriodElapsedHalfCpltCallback     = HAL_TIM_PeriodElapsedHalfCpltCallback;     /* Legacy weak PeriodElapsedHalfCpltCallback     */\n  htim->TriggerCallback                   = HAL_TIM_TriggerCallback;                   /* Legacy weak TriggerCallback                   */\n  htim->TriggerHalfCpltCallback           = HAL_TIM_TriggerHalfCpltCallback;           /* Legacy weak TriggerHalfCpltCallback           */\n  htim->IC_CaptureCallback                = HAL_TIM_IC_CaptureCallback;                /* Legacy weak IC_CaptureCallback                */\n  htim->IC_CaptureHalfCpltCallback        = HAL_TIM_IC_CaptureHalfCpltCallback;        /* Legacy weak IC_CaptureHalfCpltCallback        */\n  htim->OC_DelayElapsedCallback           = HAL_TIM_OC_DelayElapsedCallback;           /* Legacy weak OC_DelayElapsedCallback           */\n  htim->PWM_PulseFinishedCallback         = HAL_TIM_PWM_PulseFinishedCallback;         /* Legacy weak PWM_PulseFinishedCallback         */\n  htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */\n  htim->ErrorCallback                     = HAL_TIM_ErrorCallback;                     /* Legacy weak ErrorCallback                     */\n  htim->CommutationCallback               = HAL_TIMEx_CommutCallback;                  /* Legacy weak CommutationCallback               */\n  htim->CommutationHalfCpltCallback       = HAL_TIMEx_CommutHalfCpltCallback;          /* Legacy weak CommutationHalfCpltCallback       */\n  htim->BreakCallback                     = HAL_TIMEx_BreakCallback;                   /* Legacy weak BreakCallback                     */\n}\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n#endif /* HAL_TIM_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_tim_ex.c\n  * @author  MCD Application Team\n  * @brief   TIM HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Timer Extended peripheral:\n  *           + Time Hall Sensor Interface Initialization\n  *           + Time Hall Sensor Interface Start\n  *           + Time Complementary signal break and dead time configuration\n  *           + Time Master and Slave synchronization configuration\n  *           + Timer remapping capabilities configuration\n  @verbatim\n  ==============================================================================\n                      ##### TIMER Extended features #####\n  ==============================================================================\n  [..]\n    The Timer Extended features include:\n    (#) Complementary outputs with programmable dead-time for :\n        (++) Output Compare\n        (++) PWM generation (Edge and Center-aligned Mode)\n        (++) One-pulse mode output\n    (#) Synchronization circuit to control the timer with external signals and to\n        interconnect several timers together.\n    (#) Break input to put the timer output signals in reset state or in a known state.\n    (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for\n        positioning purposes\n\n            ##### How to use this driver #####\n  ==============================================================================\n    [..]\n     (#) Initialize the TIM low level resources by implementing the following functions\n         depending on the selected feature:\n           (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit()\n\n     (#) Initialize the TIM low level resources :\n        (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();\n        (##) TIM pins configuration\n            (+++) Enable the clock for the TIM GPIOs using the following function:\n              __HAL_RCC_GPIOx_CLK_ENABLE();\n            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();\n\n     (#) The external Clock can be configured, if needed (the default clock is the\n         internal clock from the APBx), using the following function:\n         HAL_TIM_ConfigClockSource, the clock configuration should be done before\n         any start function.\n\n     (#) Configure the TIM in the desired functioning mode using one of the\n         initialization function of this driver:\n          (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the\n               Timer Hall Sensor Interface and the commutation event with the corresponding\n               Interrupt and DMA request if needed (Note that One Timer is used to interface\n               with the Hall sensor Interface and another Timer should be used to use\n               the commutation event).\n\n     (#) Activate the TIM peripheral using one of the start functions:\n           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()\n           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()\n           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()\n           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup TIMEx TIMEx\n  * @brief TIM Extended HAL module driver\n  * @{\n  */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\nstatic void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);\nstatic void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);\nstatic void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions\n  * @{\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions\n  * @brief    Timer Hall Sensor functions\n  *\n@verbatim\n  ==============================================================================\n                      ##### Timer Hall Sensor functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Initialize and configure TIM HAL Sensor.\n    (+) De-initialize TIM HAL Sensor.\n    (+) Start the Hall Sensor Interface.\n    (+) Stop the Hall Sensor Interface.\n    (+) Start the Hall Sensor Interface and enable interrupts.\n    (+) Stop the Hall Sensor Interface and disable interrupts.\n    (+) Start the Hall Sensor Interface and enable DMA transfers.\n    (+) Stop the Hall Sensor Interface and disable DMA transfers.\n\n@endverbatim\n  * @{\n  */\n/**\n  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.\n  * @note   When the timer instance is initialized in Hall Sensor Interface mode,\n  *         timer channels 1 and channel 2 are reserved and cannot be used for\n  *         other purpose.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @param  sConfig TIM Hall Sensor configuration structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)\n{\n  TIM_OC_InitTypeDef OC_Config;\n\n  /* Check the TIM handle allocation */\n  if (htim == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));\n  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));\n  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));\n  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));\n  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));\n  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));\n\n  if (htim->State == HAL_TIM_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    htim->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n    /* Reset interrupt callbacks to legacy week callbacks */\n    TIM_ResetCallback(htim);\n\n    if (htim->HallSensor_MspInitCallback == NULL)\n    {\n      htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;\n    }\n    /* Init the low level hardware : GPIO, CLOCK, NVIC */\n    htim->HallSensor_MspInitCallback(htim);\n#else\n    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */\n    HAL_TIMEx_HallSensor_MspInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n  }\n\n  /* Set the TIM state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Configure the Time base in the Encoder Mode */\n  TIM_Base_SetConfig(htim->Instance, &htim->Init);\n\n  /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the  Hall sensor */\n  TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);\n\n  /* Reset the IC1PSC Bits */\n  htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;\n  /* Set the IC1PSC value */\n  htim->Instance->CCMR1 |= sConfig->IC1Prescaler;\n\n  /* Enable the Hall sensor interface (XOR function of the three inputs) */\n  htim->Instance->CR2 |= TIM_CR2_TI1S;\n\n  /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */\n  htim->Instance->SMCR &= ~TIM_SMCR_TS;\n  htim->Instance->SMCR |= TIM_TS_TI1F_ED;\n\n  /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */\n  htim->Instance->SMCR &= ~TIM_SMCR_SMS;\n  htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;\n\n  /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/\n  OC_Config.OCFastMode = TIM_OCFAST_DISABLE;\n  OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;\n  OC_Config.OCMode = TIM_OCMODE_PWM2;\n  OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;\n  OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;\n  OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;\n  OC_Config.Pulse = sConfig->Commutation_Delay;\n\n  TIM_OC2_SetConfig(htim->Instance, &OC_Config);\n\n  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2\n    register to 101 */\n  htim->Instance->CR2 &= ~TIM_CR2_MMS;\n  htim->Instance->CR2 |= TIM_TRGO_OC2REF;\n\n  /* Initialize the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;\n\n  /* Initialize the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Initialize the TIM state*/\n  htim->State = HAL_TIM_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the TIM Hall Sensor interface\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_INSTANCE(htim->Instance));\n\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Disable the TIM Peripheral Clock */\n  __HAL_TIM_DISABLE(htim);\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  if (htim->HallSensor_MspDeInitCallback == NULL)\n  {\n    htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  htim->HallSensor_MspDeInitCallback(htim);\n#else\n  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */\n  HAL_TIMEx_HallSensor_MspDeInit(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  /* Change the DMA burst operation state */\n  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;\n\n  /* Change the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);\n\n  /* Change TIM state */\n  htim->State = HAL_TIM_STATE_RESET;\n\n  /* Release Lock */\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the TIM Hall Sensor MSP.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval None\n  */\n__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  DeInitializes TIM Hall Sensor MSP.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval None\n  */\n__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Starts the TIM Hall Sensor Interface.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Check the TIM channels state */\n  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Input Capture channel 1\n  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Hall sensor Interface.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channels 1, 2 and 3\n    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Hall Sensor Interface in interrupt mode.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Check the TIM channels state */\n  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the capture compare Interrupts 1 event */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n\n  /* Enable the Input Capture channel 1\n    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Hall Sensor Interface in interrupt mode.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channel 1\n    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n\n  /* Disable the capture compare Interrupts event */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Hall Sensor Interface in DMA mode.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @param  pData The destination Buffer address.\n  * @param  Length The length of data to be transferred from TIM peripheral to memory.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Set the TIM channel state */\n  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)\n      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))\n  {\n    return HAL_BUSY;\n  }\n  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)\n           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  /* Enable the Input Capture channel 1\n    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);\n\n  /* Set the DMA Input Capture 1 Callbacks */\n  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;\n  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;\n  /* Set the DMA error callback */\n  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;\n\n  /* Enable the DMA stream for Capture 1*/\n  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)\n  {\n    /* Return error status */\n    return HAL_ERROR;\n  }\n  /* Enable the capture compare 1 Interrupt */\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Hall Sensor Interface in DMA mode.\n  * @param  htim TIM Hall Sensor Interface handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));\n\n  /* Disable the Input Capture channel 1\n    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */\n  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);\n\n\n  /* Disable the capture compare Interrupts 1 event */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n\n  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM channel state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions\n  *  @brief   Timer Complementary Output Compare functions\n  *\n@verbatim\n  ==============================================================================\n              ##### Timer Complementary Output Compare functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Start the Complementary Output Compare/PWM.\n    (+) Stop the Complementary Output Compare/PWM.\n    (+) Start the Complementary Output Compare/PWM and enable interrupts.\n    (+) Stop the Complementary Output Compare/PWM and disable interrupts.\n    (+) Start the Complementary Output Compare/PWM and enable DMA transfers.\n    (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation on the complementary\n  *         output.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation on the complementary\n  *         output.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Disable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation in interrupt mode\n  *         on the complementary output.\n  * @param  htim TIM OC handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Enable the TIM Output Compare interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Enable the TIM Output Compare interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Enable the TIM Output Compare interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n\n    default:\n      break;\n  }\n\n  /* Enable the TIM Break interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\n\n  /* Enable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation in interrupt mode\n  *         on the complementary output.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpccer;\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Output Compare interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Output Compare interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Output Compare interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the TIM Break interrupt (only if no more channel is active) */\n  tmpccer = htim->Instance->CCER;\n  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\n  {\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\n  }\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM Output Compare signal generation in DMA mode\n  *         on the complementary output.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @param  pData The source Buffer address.\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Set the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Output Compare DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Output Compare DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Output Compare DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM Output Compare signal generation in DMA mode\n  *         on the complementary output.\n  * @param  htim TIM Output Compare handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Output Compare DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Output Compare DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Output Compare DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the Capture compare channel N */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions\n  * @brief    Timer Complementary PWM functions\n  *\n@verbatim\n  ==============================================================================\n                 ##### Timer Complementary PWM functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Start the Complementary PWM.\n    (+) Stop the Complementary PWM.\n    (+) Start the Complementary PWM and enable interrupts.\n    (+) Stop the Complementary PWM and disable interrupts.\n    (+) Start the Complementary PWM and enable DMA transfers.\n    (+) Stop the Complementary PWM and disable DMA transfers.\n    (+) Start the Complementary Input Capture measurement.\n    (+) Stop the Complementary Input Capture.\n    (+) Start the Complementary Input Capture and enable interrupts.\n    (+) Stop the Complementary Input Capture and disable interrupts.\n    (+) Start the Complementary Input Capture and enable DMA transfers.\n    (+) Stop the Complementary Input Capture and disable DMA transfers.\n    (+) Start the Complementary One Pulse generation.\n    (+) Stop the Complementary One Pulse.\n    (+) Start the Complementary One Pulse and enable interrupts.\n    (+) Stop the Complementary One Pulse and disable interrupts.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Starts the PWM signal generation on the complementary output.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the complementary PWM output  */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the PWM signal generation on the complementary output.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Disable the complementary PWM output  */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the PWM signal generation in interrupt mode on the\n  *         complementary output.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Check the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Enable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Enable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Enable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the TIM Break interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);\n\n  /* Enable the complementary PWM output  */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the PWM signal generation in interrupt mode on the\n  *         complementary output.\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  uint32_t tmpccer;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 interrupt */\n      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the complementary PWM output  */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the TIM Break interrupt (only if no more channel is active) */\n  tmpccer = htim->Instance->CCER;\n  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)\n  {\n    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);\n  }\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM PWM signal generation in DMA mode on the\n  *         complementary output\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be enabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @param  pData The source Buffer address.\n  * @param  Length The length of data to be transferred from memory to TIM peripheral\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)\n{\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  /* Set the TIM complementary channel state */\n  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)\n  {\n    return HAL_BUSY;\n  }\n  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)\n  {\n    if ((pData == NULL) && (Length > 0U))\n    {\n      return HAL_ERROR;\n    }\n    else\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);\n    }\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Set the DMA compare callbacks */\n      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;\n      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;\n\n      /* Set the DMA error callback */\n      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;\n\n      /* Enable the DMA stream */\n      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)\n      {\n        /* Return error status */\n        return HAL_ERROR;\n      }\n      /* Enable the TIM Capture/Compare 3 DMA request */\n      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Enable the complementary PWM output  */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;\n    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))\n    {\n      __HAL_TIM_ENABLE(htim);\n    }\n  }\n  else\n  {\n    __HAL_TIM_ENABLE(htim);\n  }\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary\n  *         output\n  * @param  htim TIM handle\n  * @param  Channel TIM Channel to be disabled\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));\n\n  switch (Channel)\n  {\n    case TIM_CHANNEL_1:\n    {\n      /* Disable the TIM Capture/Compare 1 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);\n      break;\n    }\n\n    case TIM_CHANNEL_2:\n    {\n      /* Disable the TIM Capture/Compare 2 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);\n      break;\n    }\n\n    case TIM_CHANNEL_3:\n    {\n      /* Disable the TIM Capture/Compare 3 DMA request */\n      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);\n      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);\n      break;\n    }\n\n    default:\n      break;\n  }\n\n  /* Disable the complementary PWM output */\n  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM complementary channel state */\n  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions\n  * @brief    Timer Complementary One Pulse functions\n  *\n@verbatim\n  ==============================================================================\n                ##### Timer Complementary One Pulse functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n    (+) Start the Complementary One Pulse generation.\n    (+) Stop the Complementary One Pulse.\n    (+) Start the Complementary One Pulse and enable interrupts.\n    (+) Stop the Complementary One Pulse and disable interrupts.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Starts the TIM One Pulse signal generation on the complementary\n  *         output.\n  * @note OutputChannel must match the pulse output channel chosen when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel pulse output channel to enable\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\n\n  /* Check the TIM channels state */\n   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the complementary One Pulse output channel and the Input Capture channel */\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\n  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM One Pulse signal generation on the complementary\n  *         output.\n  * @note OutputChannel must match the pulse output channel chosen when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel pulse output channel to disable\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\n\n  /* Disable the complementary One Pulse output channel and the Input Capture channel */\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\n  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM  channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the\n  *         complementary channel.\n  * @note OutputChannel must match the pulse output channel chosen when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel pulse output channel to enable\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;\n  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);\n  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\n\n  /* Check the TIM channels state */\n   if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)\n      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))\n  {\n    return HAL_ERROR;\n  }\n\n  /* Set the TIM channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);\n\n  /* Enable the TIM Capture/Compare 1 interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);\n\n  /* Enable the TIM Capture/Compare 2 interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);\n\n  /* Enable the complementary One Pulse output channel and the Input Capture channel */\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);\n  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);\n\n  /* Enable the Main Output */\n  __HAL_TIM_MOE_ENABLE(htim);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the\n  *         complementary channel.\n  * @note OutputChannel must match the pulse output channel chosen when calling \n  *       @ref HAL_TIM_OnePulse_ConfigChannel(). \n  * @param  htim TIM One Pulse handle\n  * @param  OutputChannel pulse output channel to disable\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected\n  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)\n{\n  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));\n\n  /* Disable the TIM Capture/Compare 1 interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);\n\n  /* Disable the TIM Capture/Compare 2 interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);\n\n  /* Disable the complementary One Pulse output channel and the Input Capture channel */\n  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);\n  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);\n\n  /* Disable the Main Output */\n  __HAL_TIM_MOE_DISABLE(htim);\n\n  /* Disable the Peripheral */\n  __HAL_TIM_DISABLE(htim);\n\n  /* Set the TIM  channels state */\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n\n  /* Return function status */\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions\n  * @brief    Peripheral Control functions\n  *\n@verbatim\n  ==============================================================================\n                    ##### Peripheral Control functions #####\n  ==============================================================================\n  [..]\n    This section provides functions allowing to:\n      (+) Configure the commutation event in case of use of the Hall sensor interface.\n      (+) Configure Output channels for OC and PWM mode.\n\n      (+) Configure Complementary channels, break features and dead time.\n      (+) Configure Master synchronization.\n      (+) Configure timer remapping capabilities.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Configure the TIM commutation event sequence.\n  * @note  This function is mandatory to use the commutation event in order to\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\n  *        the typical use of this feature is with the use of another Timer(interface Timer)\n  *        configured in Hall sensor interface, this interface Timer will generate the\n  *        commutation at its TRGO output (connected to Timer used in this function) each time\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\n  * @param  htim TIM handle\n  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\n  *          This parameter can be one of the following values:\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\n  *            @arg TIM_TS_NONE: No trigger is needed\n  * @param  CommutationSource the Commutation Event source\n  *          This parameter can be one of the following values:\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                              uint32_t  CommutationSource)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\n\n  __HAL_LOCK(htim);\n\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\n  {\n    /* Select the Input trigger */\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\n    htim->Instance->SMCR |= InputTrigger;\n  }\n\n  /* Select the Capture Compare preload feature */\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\n  /* Select the Commutation event source */\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\n  htim->Instance->CR2 |= CommutationSource;\n\n  /* Disable Commutation Interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\n\n  /* Disable Commutation DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configure the TIM commutation event sequence with interrupt.\n  * @note  This function is mandatory to use the commutation event in order to\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\n  *        the typical use of this feature is with the use of another Timer(interface Timer)\n  *        configured in Hall sensor interface, this interface Timer will generate the\n  *        commutation at its TRGO output (connected to Timer used in this function) each time\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\n  * @param  htim TIM handle\n  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\n  *          This parameter can be one of the following values:\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\n  *            @arg TIM_TS_NONE: No trigger is needed\n  * @param  CommutationSource the Commutation Event source\n  *          This parameter can be one of the following values:\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                                 uint32_t  CommutationSource)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\n\n  __HAL_LOCK(htim);\n\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\n  {\n    /* Select the Input trigger */\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\n    htim->Instance->SMCR |= InputTrigger;\n  }\n\n  /* Select the Capture Compare preload feature */\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\n  /* Select the Commutation event source */\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\n  htim->Instance->CR2 |= CommutationSource;\n\n  /* Disable Commutation DMA request */\n  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);\n\n  /* Enable the Commutation Interrupt */\n  __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configure the TIM commutation event sequence with DMA.\n  * @note  This function is mandatory to use the commutation event in order to\n  *        update the configuration at each commutation detection on the TRGI input of the Timer,\n  *        the typical use of this feature is with the use of another Timer(interface Timer)\n  *        configured in Hall sensor interface, this interface Timer will generate the\n  *        commutation at its TRGO output (connected to Timer used in this function) each time\n  *        the TI1 of the Interface Timer detect a commutation at its input TI1.\n  * @note  The user should configure the DMA in his own software, in This function only the COMDE bit is set\n  * @param  htim TIM handle\n  * @param  InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor\n  *          This parameter can be one of the following values:\n  *            @arg TIM_TS_ITR0: Internal trigger 0 selected\n  *            @arg TIM_TS_ITR1: Internal trigger 1 selected\n  *            @arg TIM_TS_ITR2: Internal trigger 2 selected\n  *            @arg TIM_TS_ITR3: Internal trigger 3 selected\n  *            @arg TIM_TS_NONE: No trigger is needed\n  * @param  CommutationSource the Commutation Event source\n  *          This parameter can be one of the following values:\n  *            @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer\n  *            @arg TIM_COMMUTATION_SOFTWARE:  Commutation source is set by software using the COMG bit\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,\n                                                  uint32_t  CommutationSource)\n{\n  /* Check the parameters */\n  assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));\n\n  __HAL_LOCK(htim);\n\n  if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||\n      (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))\n  {\n    /* Select the Input trigger */\n    htim->Instance->SMCR &= ~TIM_SMCR_TS;\n    htim->Instance->SMCR |= InputTrigger;\n  }\n\n  /* Select the Capture Compare preload feature */\n  htim->Instance->CR2 |= TIM_CR2_CCPC;\n  /* Select the Commutation event source */\n  htim->Instance->CR2 &= ~TIM_CR2_CCUS;\n  htim->Instance->CR2 |= CommutationSource;\n\n  /* Enable the Commutation DMA Request */\n  /* Set the DMA Commutation Callback */\n  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;\n  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;\n  /* Set the DMA error callback */\n  htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;\n\n  /* Disable Commutation Interrupt */\n  __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);\n\n  /* Enable the Commutation DMA Request */\n  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the TIM in master mode.\n  * @param  htim TIM handle.\n  * @param  sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that\n  *         contains the selected trigger output (TRGO) and the Master/Slave\n  *         mode.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,\n                                                        TIM_MasterConfigTypeDef *sMasterConfig)\n{\n  uint32_t tmpcr2;\n  uint32_t tmpsmcr;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));\n  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));\n\n  /* Check input state */\n  __HAL_LOCK(htim);\n\n  /* Change the handler state */\n  htim->State = HAL_TIM_STATE_BUSY;\n\n  /* Get the TIMx CR2 register value */\n  tmpcr2 = htim->Instance->CR2;\n\n  /* Get the TIMx SMCR register value */\n  tmpsmcr = htim->Instance->SMCR;\n\n  /* Reset the MMS Bits */\n  tmpcr2 &= ~TIM_CR2_MMS;\n  /* Select the TRGO source */\n  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;\n\n  /* Update TIMx CR2 */\n  htim->Instance->CR2 = tmpcr2;\n\n  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))\n  {\n    /* Reset the MSM Bit */\n    tmpsmcr &= ~TIM_SMCR_MSM;\n    /* Set master mode */\n    tmpsmcr |= sMasterConfig->MasterSlaveMode;\n\n    /* Update TIMx SMCR */\n    htim->Instance->SMCR = tmpsmcr;\n  }\n\n  /* Change the htim state */\n  htim->State = HAL_TIM_STATE_READY;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State\n  *         and the AOE(automatic output enable).\n  * @param  htim TIM handle\n  * @param  sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that\n  *         contains the BDTR Register configuration  information for the TIM peripheral.\n  * @note   Interrupts can be generated when an active level is detected on the\n  *         break input, the break 2 input or the system break input. Break\n  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,\n                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)\n{\n  /* Keep this variable initialized to 0 as it is used to configure BDTR register */\n  uint32_t tmpbdtr = 0U;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));\n  assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));\n  assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));\n  assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));\n  assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));\n  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));\n  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));\n  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));\n\n  /* Check input state */\n  __HAL_LOCK(htim);\n\n  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,\n     the OSSI State, the dead time value and the Automatic Output Enable Bit */\n\n  /* Set the BDTR bits */\n  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);\n  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);\n\n\n  /* Set TIMx_BDTR */\n  htim->Instance->BDTR = tmpbdtr;\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Configures the TIMx Remapping input capabilities.\n  * @param  htim TIM handle.\n  * @param  Remap specifies the TIM remapping source.\n  *         For TIM1, the parameter can have the following values:                   (**)\n  *           @arg TIM_TIM1_TIM3_TRGO:  TIM1 ITR2 is connected to TIM3 TRGO\n  *           @arg TIM_TIM1_LPTIM:      TIM1 ITR2 is connected to LPTIM1 output\n  *\n  *         For TIM2, the parameter can have the following values:                   (**)\n  *           @arg TIM_TIM2_TIM8_TRGO:  TIM2 ITR1 is connected to TIM8 TRGO          (*)\n  *           @arg TIM_TIM2_ETH_PTP:    TIM2 ITR1 is connected to PTP trigger output (*)\n  *           @arg TIM_TIM2_USBFS_SOF:  TIM2 ITR1 is connected to OTG FS SOF\n  *           @arg TIM_TIM2_USBHS_SOF:  TIM2 ITR1 is connected to OTG FS SOF\n  *\n  *         For TIM5, the parameter can have the following values:\n  *           @arg TIM_TIM5_GPIO:       TIM5 TI4 is connected to GPIO\n  *           @arg TIM_TIM5_LSI:        TIM5 TI4 is connected to LSI\n  *           @arg TIM_TIM5_LSE:        TIM5 TI4 is connected to LSE\n  *           @arg TIM_TIM5_RTC:        TIM5 TI4 is connected to the RTC wakeup interrupt\n  *           @arg TIM_TIM5_TIM3_TRGO:  TIM5 ITR1 is connected to TIM3 TRGO          (*)\n  *           @arg TIM_TIM5_LPTIM:      TIM5 ITR1 is connected to LPTIM1 output      (*)\n  *\n  *         For TIM9, the parameter can have the following values:                   (**)\n  *           @arg TIM_TIM9_TIM3_TRGO:  TIM9 ITR1 is connected to TIM3 TRGO\n  *           @arg TIM_TIM9_LPTIM:      TIM9 ITR1 is connected to LPTIM1 output\n  *\n  *         For TIM11, the parameter can have the following values:\n  *           @arg TIM_TIM11_GPIO:     TIM11 TI1 is connected to GPIO\n  *           @arg TIM_TIM11_HSE:      TIM11 TI1 is connected to HSE_RTC clock\n  *           @arg TIM_TIM11_SPDIFRX:  TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC  (*)\n  *\n  *         (*)  Value not defined in all devices. \\n\n  *         (**) Register not available in all devices.\n  *\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)\n{\n  __HAL_LOCK(htim);\n\n  /* Check parameters */\n  assert_param(IS_TIM_REMAP(htim->Instance, Remap));\n\n#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP)\n  if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK)\n  {\n    /* Connect TIMx internal trigger to LPTIM1 output */\n    __HAL_RCC_LPTIM1_CLK_ENABLE();\n    MODIFY_REG(LPTIM1->OR,\n               (LPTIM_OR_TIM1_ITR2_RMP | LPTIM_OR_TIM5_ITR1_RMP | LPTIM_OR_TIM9_ITR1_RMP),\n               Remap & ~(LPTIM_REMAP_MASK));\n  }\n  else\n  {\n    /* Set the Timer remapping configuration */\n    WRITE_REG(htim->Instance->OR, Remap);\n  }\n#else\n  /* Set the Timer remapping configuration */\n  WRITE_REG(htim->Instance->OR, Remap);\n#endif /* LPTIM_OR_TIM1_ITR2_RMP &&  LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM9_ITR1_RMP */\n\n  __HAL_UNLOCK(htim);\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions\n  * @brief    Extended Callbacks functions\n  *\n@verbatim\n  ==============================================================================\n                    ##### Extended Callbacks functions #####\n  ==============================================================================\n  [..]\n    This section provides Extended TIM callback functions:\n    (+) Timer Commutation callback\n    (+) Timer Break callback\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Hall commutation changed callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIMEx_CommutCallback could be implemented in the user file\n   */\n}\n/**\n  * @brief  Hall commutation changed half complete callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Hall Break detection callback in non-blocking mode\n  * @param  htim TIM handle\n  * @retval None\n  */\n__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(htim);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_TIMEx_BreakCallback could be implemented in the user file\n   */\n}\n/**\n  * @}\n  */\n\n/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions\n  * @brief    Extended Peripheral State functions\n  *\n@verbatim\n  ==============================================================================\n                ##### Extended Peripheral State functions #####\n  ==============================================================================\n  [..]\n    This subsection permits to get in run-time the status of the peripheral\n    and the data flow.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Return the TIM Hall Sensor interface handle state.\n  * @param  htim TIM Hall Sensor handle\n  * @retval HAL state\n  */\nHAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)\n{\n  return htim->State;\n}\n\n/**\n  * @brief  Return actual state of the TIM complementary channel.\n  * @param  htim TIM handle\n  * @param  ChannelN TIM Complementary channel\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1\n  *            @arg TIM_CHANNEL_2: TIM Channel 2\n  *            @arg TIM_CHANNEL_3: TIM Channel 3\n  * @retval TIM Complementary channel state\n  */\nHAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)\n{\n  HAL_TIM_ChannelStateTypeDef channel_state;\n\n  /* Check the parameters */\n  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));\n\n  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);\n\n  return channel_state;\n}\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/* Private functions ---------------------------------------------------------*/\n/** @defgroup TIMEx_Private_Functions TIMEx Private Functions\n  * @{\n  */\n\n/**\n  * @brief  TIM DMA Commutation callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  /* Change the htim state */\n  htim->State = HAL_TIM_STATE_READY;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->CommutationCallback(htim);\n#else\n  HAL_TIMEx_CommutCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  TIM DMA Commutation half complete callback.\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nvoid TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  /* Change the htim state */\n  htim->State = HAL_TIM_STATE_READY;\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->CommutationHalfCpltCallback(htim);\n#else\n  HAL_TIMEx_CommutHalfCpltCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n}\n\n\n/**\n  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;\n\n    if (hdma->Init.Mode == DMA_NORMAL)\n    {\n      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);\n    }\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->PWM_PulseFinishedCallback(htim);\n#else\n  HAL_TIM_PWM_PulseFinishedCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  TIM DMA error callback (complementary channel)\n  * @param  hdma pointer to DMA handle.\n  * @retval None\n  */\nstatic void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)\n{\n  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  if (hdma == htim->hdma[TIM_DMA_ID_CC1])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])\n  {\n    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;\n    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);\n  }\n  else\n  {\n    /* nothing to do */\n  }\n\n#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)\n  htim->ErrorCallback(htim);\n#else\n  HAL_TIM_ErrorCallback(htim);\n#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */\n\n  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;\n}\n\n/**\n  * @brief  Enables or disables the TIM Capture Compare Channel xN.\n  * @param  TIMx to select the TIM peripheral\n  * @param  Channel specifies the TIM Channel\n  *          This parameter can be one of the following values:\n  *            @arg TIM_CHANNEL_1: TIM Channel 1\n  *            @arg TIM_CHANNEL_2: TIM Channel 2\n  *            @arg TIM_CHANNEL_3: TIM Channel 3\n  * @param  ChannelNState specifies the TIM Channel CCxNE bit new state.\n  *          This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.\n  * @retval None\n  */\nstatic void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState)\n{\n  uint32_t tmp;\n\n  tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */\n\n  /* Reset the CCxNE Bit */\n  TIMx->CCER &=  ~tmp;\n\n  /* Set or reset the CCxNE Bit */\n  TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */\n}\n/**\n  * @}\n  */\n\n#endif /* HAL_TIM_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_hal_uart.c\n  * @author  MCD Application Team\n  * @brief   UART HAL module driver.\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).\n  *           + Initialization and de-initialization functions\n  *           + IO operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State and Errors functions\n  @verbatim\n  ==============================================================================\n                        ##### How to use this driver #####\n  ==============================================================================\n  [..]\n    The UART HAL driver can be used as follows:\n\n    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).\n    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:\n        (##) Enable the USARTx interface clock.\n        (##) UART pins configuration:\n            (+++) Enable the clock for the UART GPIOs.\n            (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input).\n        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()\n             and HAL_UART_Receive_IT() APIs):\n            (+++) Configure the USARTx interrupt priority.\n            (+++) Enable the NVIC USART IRQ handle.\n        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()\n             and HAL_UART_Receive_DMA() APIs):\n            (+++) Declare a DMA handle structure for the Tx/Rx stream.\n            (+++) Enable the DMAx interface clock.\n            (+++) Configure the declared DMA handle structure with the required\n                  Tx/Rx parameters.\n            (+++) Configure the DMA Tx/Rx stream.\n            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.\n            (+++) Configure the priority and enable the NVIC for the transfer complete\n                  interrupt on the DMA Tx/Rx stream.\n            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle\n                  (used for last byte sending completion detection in DMA non circular mode)\n\n    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware\n        flow control and Mode(Receiver/Transmitter) in the huart Init structure.\n\n    (#) For the UART asynchronous mode, initialize the UART registers by calling\n        the HAL_UART_Init() API.\n\n    (#) For the UART Half duplex mode, initialize the UART registers by calling\n        the HAL_HalfDuplex_Init() API.\n\n    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.\n\n    (#) For the Multi-Processor mode, initialize the UART registers by calling\n        the HAL_MultiProcessor_Init() API.\n\n     [..]\n       (@) The specific UART interrupts (Transmission complete interrupt,\n            RXNE interrupt and Error Interrupts) will be managed using the macros\n            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit\n            and receive process.\n\n     [..]\n       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the\n            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized\n            HAL_UART_MspInit() API.\n\n    ##### Callback registration #####\n    ==================================\n\n    [..]\n    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1\n    allows the user to configure dynamically the driver callbacks.\n\n    [..]\n    Use Function @ref HAL_UART_RegisterCallback() to register a user callback.\n    Function @ref HAL_UART_RegisterCallback() allows to register following callbacks:\n    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\n    (+) TxCpltCallback            : Tx Complete Callback.\n    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\n    (+) RxCpltCallback            : Rx Complete Callback.\n    (+) ErrorCallback             : Error Callback.\n    (+) AbortCpltCallback         : Abort Complete Callback.\n    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\n    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\n    (+) MspInitCallback           : UART MspInit.\n    (+) MspDeInitCallback         : UART MspDeInit.\n    This function takes as parameters the HAL peripheral handle, the Callback ID\n    and a pointer to the user callback function.\n\n    [..]\n    Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default\n    weak (surcharged) function.\n    @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,\n    and the Callback ID.\n    This function allows to reset following callbacks:\n    (+) TxHalfCpltCallback        : Tx Half Complete Callback.\n    (+) TxCpltCallback            : Tx Complete Callback.\n    (+) RxHalfCpltCallback        : Rx Half Complete Callback.\n    (+) RxCpltCallback            : Rx Complete Callback.\n    (+) ErrorCallback             : Error Callback.\n    (+) AbortCpltCallback         : Abort Complete Callback.\n    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.\n    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.\n    (+) MspInitCallback           : UART MspInit.\n    (+) MspDeInitCallback         : UART MspDeInit.\n\n    [..]\n    For specific callback RxEventCallback, use dedicated registration/reset functions:\n    respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback().\n\n    [..]\n    By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET\n    all callbacks are set to the corresponding weak (surcharged) functions:\n    examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback().\n    Exception done for MspInit and MspDeInit functions that are respectively\n    reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init()\n    and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).\n    If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit()\n    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).\n\n    [..]\n    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.\n    Exception done MspInit/MspDeInit that can be registered/unregistered\n    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)\n    MspInit/DeInit callbacks can be used during the Init/DeInit.\n    In that case first register the MspInit/MspDeInit user callbacks\n    using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit()\n    or @ref HAL_UART_Init() function.\n\n    [..]\n    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or\n    not defined, the callback registration feature is not available\n    and weak (surcharged) callbacks are used.\n\n     [..]\n        Three operation modes are available within this driver :\n\n     *** Polling mode IO operation ***\n     =================================\n     [..]\n       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()\n       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()\n\n     *** Interrupt mode IO operation ***\n     ===================================\n     [..]\n       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\n       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\n\n     *** DMA mode IO operation ***\n     ==============================\n     [..]\n       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()\n       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback\n       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_TxCpltCallback\n       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()\n       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback\n       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can\n            add his own code by customization of function pointer HAL_UART_RxCpltCallback\n       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can\n            add his own code by customization of function pointer HAL_UART_ErrorCallback\n       (+) Pause the DMA Transfer using HAL_UART_DMAPause()\n       (+) Resume the DMA Transfer using HAL_UART_DMAResume()\n       (+) Stop the DMA Transfer using HAL_UART_DMAStop()\n\n\n    [..] This subsection also provides a set of additional functions providing enhanced reception\n    services to user. (For example, these functions allow application to handle use cases\n    where number of data to be received is unknown).\n\n    (#) Compared to standard reception services which only consider number of received\n        data elements as reception completion criteria, these functions also consider additional events\n        as triggers for updating reception status to caller :\n       (+) Detection of inactivity period (RX line has not been active for a given period).\n          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)\n               for 1 frame time, after last received byte.\n\n    (#) There are two mode of transfer:\n       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,\n           or till IDLE event occurs. Reception is handled only during function execution.\n           When function exits, no data reception could occur. HAL status and number of actually received data elements,\n           are returned by function after finishing transfer.\n       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.\n           These API's return the HAL status.\n           The end of the data processing will be indicated through the\n           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.\n           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process\n           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.\n\n    (#) Blocking mode API:\n        (+) HAL_UARTEx_ReceiveToIdle()\n\n    (#) Non-Blocking mode API with Interrupt:\n        (+) HAL_UARTEx_ReceiveToIdle_IT()\n\n    (#) Non-Blocking mode API with DMA:\n        (+) HAL_UARTEx_ReceiveToIdle_DMA()\n\n\n     *** UART HAL driver macros list ***\n     =============================================\n     [..]\n       Below the list of most used macros in UART HAL driver.\n\n      (+) __HAL_UART_ENABLE: Enable the UART peripheral\n      (+) __HAL_UART_DISABLE: Disable the UART peripheral\n      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not\n      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag\n      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt\n      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt\n      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not\n\n     [..]\n       (@) You can refer to the UART HAL driver header file for more useful macros\n\n  @endverbatim\n     [..]\n       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written\n           in the data register is transmitted but is changed by the parity bit.\n           Depending on the frame length defined by the M bit (8-bits or 9-bits),\n           the possible UART frame formats are as listed in the following table:\n    +-------------------------------------------------------------+\n    |   M bit |  PCE bit  |            UART frame                 |\n    |---------------------|---------------------------------------|\n    |    0    |    0      |    | SB | 8 bit data | STB |          |\n    |---------|-----------|---------------------------------------|\n    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |\n    |---------|-----------|---------------------------------------|\n    |    1    |    0      |    | SB | 9 bit data | STB |          |\n    |---------|-----------|---------------------------------------|\n    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |\n    +-------------------------------------------------------------+\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_HAL_Driver\n  * @{\n  */\n\n/** @defgroup UART UART\n  * @brief HAL UART module driver\n  * @{\n  */\n#ifdef HAL_UART_MODULE_ENABLED\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/** @addtogroup UART_Private_Constants\n  * @{\n  */\n/**\n  * @}\n  */\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/** @addtogroup UART_Private_Functions  UART Private Functions\n  * @{\n  */\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\nvoid UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart);\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart);\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma);\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);\nstatic void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);\nstatic void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);\nstatic void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\nstatic void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);\nstatic HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);\nstatic void UART_SetConfig(UART_HandleTypeDef *huart);\n\n/**\n  * @}\n  */\n\n/* Exported functions ---------------------------------------------------------*/\n/** @defgroup UART_Exported_Functions UART Exported Functions\n  * @{\n  */\n\n/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions\n  *  @brief    Initialization and Configuration functions\n  *\n@verbatim\n ===============================================================================\n            ##### Initialization and Configuration functions #####\n ===============================================================================\n    [..]\n    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy\n    in asynchronous mode.\n      (+) For the asynchronous mode only these parameters can be configured:\n        (++) Baud Rate\n        (++) Word Length\n        (++) Stop Bit\n        (++) Parity: If the parity is enabled, then the MSB bit of the data written\n             in the data register is transmitted but is changed by the parity bit.\n             Depending on the frame length defined by the M bit (8-bits or 9-bits),\n             please refer to Reference manual for possible UART frame formats.\n        (++) Hardware flow control\n        (++) Receiver/transmitter modes\n        (++) Over Sampling Method\n    [..]\n    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs\n    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration\n    procedures (details for the procedures are available in reference manual\n    (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs\n     RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs\n     RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs\n     RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the UART mode according to the specified parameters in\n  *         the UART_InitTypeDef and create the associated handle.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)\n{\n  /* Check the UART handle allocation */\n  if (huart == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)\n  {\n    /* The hardware flow control is available only for USART1, USART2, USART3 and USART6.\n       Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5.\n    */\n    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));\n    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));\n  }\n  else\n  {\n    assert_param(IS_UART_INSTANCE(huart->Instance));\n  }\n  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\n  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\n\n  if (huart->gState == HAL_UART_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    huart->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    UART_InitCallbacksToDefault(huart);\n\n    if (huart->MspInitCallback == NULL)\n    {\n      huart->MspInitCallback = HAL_UART_MspInit;\n    }\n\n    /* Init the low level hardware */\n    huart->MspInitCallback(huart);\n#else\n    /* Init the low level hardware : GPIO, CLOCK */\n    HAL_UART_MspInit(huart);\n#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\n  }\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the peripheral */\n  __HAL_UART_DISABLE(huart);\n\n  /* Set the UART Communication parameters */\n  UART_SetConfig(huart);\n\n  /* In asynchronous mode, the following bits must be kept cleared:\n     - LINEN and CLKEN bits in the USART_CR2 register,\n     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\n\n  /* Enable the peripheral */\n  __HAL_UART_ENABLE(huart);\n\n  /* Initialize the UART state */\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->gState = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the half-duplex mode according to the specified\n  *         parameters in the UART_InitTypeDef and create the associated handle.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)\n{\n  /* Check the UART handle allocation */\n  if (huart == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));\n  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\n  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\n\n  if (huart->gState == HAL_UART_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    huart->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    UART_InitCallbacksToDefault(huart);\n\n    if (huart->MspInitCallback == NULL)\n    {\n      huart->MspInitCallback = HAL_UART_MspInit;\n    }\n\n    /* Init the low level hardware */\n    huart->MspInitCallback(huart);\n#else\n    /* Init the low level hardware : GPIO, CLOCK */\n    HAL_UART_MspInit(huart);\n#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\n  }\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the peripheral */\n  __HAL_UART_DISABLE(huart);\n\n  /* Set the UART Communication parameters */\n  UART_SetConfig(huart);\n\n  /* In half-duplex mode, the following bits must be kept cleared:\n     - LINEN and CLKEN bits in the USART_CR2 register,\n     - SCEN and IREN bits in the USART_CR3 register.*/\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));\n\n  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */\n  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);\n\n  /* Enable the peripheral */\n  __HAL_UART_ENABLE(huart);\n\n  /* Initialize the UART state*/\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->gState = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the LIN mode according to the specified\n  *         parameters in the UART_InitTypeDef and create the associated handle.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @param  BreakDetectLength Specifies the LIN break detection length.\n  *         This parameter can be one of the following values:\n  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection\n  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)\n{\n  /* Check the UART handle allocation */\n  if (huart == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the LIN UART instance */\n  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));\n\n  /* Check the Break detection length parameter */\n  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));\n  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));\n  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));\n\n  if (huart->gState == HAL_UART_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    huart->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    UART_InitCallbacksToDefault(huart);\n\n    if (huart->MspInitCallback == NULL)\n    {\n      huart->MspInitCallback = HAL_UART_MspInit;\n    }\n\n    /* Init the low level hardware */\n    huart->MspInitCallback(huart);\n#else\n    /* Init the low level hardware : GPIO, CLOCK */\n    HAL_UART_MspInit(huart);\n#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\n  }\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the peripheral */\n  __HAL_UART_DISABLE(huart);\n\n  /* Set the UART Communication parameters */\n  UART_SetConfig(huart);\n\n  /* In LIN mode, the following bits must be kept cleared:\n     - CLKEN bits in the USART_CR2 register,\n     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));\n\n  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */\n  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);\n\n  /* Set the USART LIN Break detection length. */\n  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);\n  SET_BIT(huart->Instance->CR2, BreakDetectLength);\n\n  /* Enable the peripheral */\n  __HAL_UART_ENABLE(huart);\n\n  /* Initialize the UART state*/\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->gState = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initializes the Multi-Processor mode according to the specified\n  *         parameters in the UART_InitTypeDef and create the associated handle.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @param  Address USART address\n  * @param  WakeUpMethod specifies the USART wake-up method.\n  *         This parameter can be one of the following values:\n  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection\n  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)\n{\n  /* Check the UART handle allocation */\n  if (huart == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(huart->Instance));\n\n  /* Check the Address & wake up method parameters */\n  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));\n  assert_param(IS_UART_ADDRESS(Address));\n  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));\n  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));\n\n  if (huart->gState == HAL_UART_STATE_RESET)\n  {\n    /* Allocate lock resource and initialize it */\n    huart->Lock = HAL_UNLOCKED;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    UART_InitCallbacksToDefault(huart);\n\n    if (huart->MspInitCallback == NULL)\n    {\n      huart->MspInitCallback = HAL_UART_MspInit;\n    }\n\n    /* Init the low level hardware */\n    huart->MspInitCallback(huart);\n#else\n    /* Init the low level hardware : GPIO, CLOCK */\n    HAL_UART_MspInit(huart);\n#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\n  }\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the peripheral */\n  __HAL_UART_DISABLE(huart);\n\n  /* Set the UART Communication parameters */\n  UART_SetConfig(huart);\n\n  /* In Multi-Processor mode, the following bits must be kept cleared:\n     - LINEN and CLKEN bits in the USART_CR2 register,\n     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */\n  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));\n  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));\n\n  /* Set the USART address node */\n  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);\n  SET_BIT(huart->Instance->CR2, Address);\n\n  /* Set the wake up method by setting the WAKE bit in the CR1 register */\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);\n  SET_BIT(huart->Instance->CR1, WakeUpMethod);\n\n  /* Enable the peripheral */\n  __HAL_UART_ENABLE(huart);\n\n  /* Initialize the UART state */\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->gState = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  DeInitializes the UART peripheral.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)\n{\n  /* Check the UART handle allocation */\n  if (huart == NULL)\n  {\n    return HAL_ERROR;\n  }\n\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(huart->Instance));\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the Peripheral */\n  __HAL_UART_DISABLE(huart);\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  if (huart->MspDeInitCallback == NULL)\n  {\n    huart->MspDeInitCallback = HAL_UART_MspDeInit;\n  }\n  /* DeInit the low level hardware */\n  huart->MspDeInitCallback(huart);\n#else\n  /* DeInit the low level hardware */\n  HAL_UART_MspDeInit(huart);\n#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */\n\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->gState = HAL_UART_STATE_RESET;\n  huart->RxState = HAL_UART_STATE_RESET;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  /* Process Unlock */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  UART MSP Init.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_MspInit could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  UART MSP DeInit.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_MspDeInit could be implemented in the user file\n   */\n}\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n/**\n  * @brief  Register a User UART Callback\n  *         To be used instead of the weak predefined callback\n  * @param  huart uart handle\n  * @param  CallbackID ID of the callback to be registered\n  *         This parameter can be one of the following values:\n  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\n  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\n  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\n  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\n  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\n  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\n  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\n  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\n  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\n  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\n  * @param  pCallback pointer to the Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    /* Update the error code */\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n  /* Process locked */\n  __HAL_LOCK(huart);\n\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    switch (CallbackID)\n    {\n      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\n        huart->TxHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_TX_COMPLETE_CB_ID :\n        huart->TxCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\n        huart->RxHalfCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_RX_COMPLETE_CB_ID :\n        huart->RxCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_ERROR_CB_ID :\n        huart->ErrorCallback = pCallback;\n        break;\n\n      case HAL_UART_ABORT_COMPLETE_CB_ID :\n        huart->AbortCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\n        huart->AbortTransmitCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\n        huart->AbortReceiveCpltCallback = pCallback;\n        break;\n\n      case HAL_UART_MSPINIT_CB_ID :\n        huart->MspInitCallback = pCallback;\n        break;\n\n      case HAL_UART_MSPDEINIT_CB_ID :\n        huart->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (huart->gState == HAL_UART_STATE_RESET)\n  {\n    switch (CallbackID)\n    {\n      case HAL_UART_MSPINIT_CB_ID :\n        huart->MspInitCallback = pCallback;\n        break;\n\n      case HAL_UART_MSPDEINIT_CB_ID :\n        huart->MspDeInitCallback = pCallback;\n        break;\n\n      default :\n        /* Update the error code */\n        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(huart);\n\n  return status;\n}\n\n/**\n  * @brief  Unregister an UART Callback\n  *         UART callaback is redirected to the weak predefined callback\n  * @param  huart uart handle\n  * @param  CallbackID ID of the callback to be unregistered\n  *         This parameter can be one of the following values:\n  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID\n  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID\n  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID\n  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID\n  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID\n  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID\n  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID\n  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID\n  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID\n  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(huart);\n\n  if (HAL_UART_STATE_READY == huart->gState)\n  {\n    switch (CallbackID)\n    {\n      case HAL_UART_TX_HALFCOMPLETE_CB_ID :\n        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */\n        break;\n\n      case HAL_UART_TX_COMPLETE_CB_ID :\n        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */\n        break;\n\n      case HAL_UART_RX_HALFCOMPLETE_CB_ID :\n        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */\n        break;\n\n      case HAL_UART_RX_COMPLETE_CB_ID :\n        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */\n        break;\n\n      case HAL_UART_ERROR_CB_ID :\n        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */\n        break;\n\n      case HAL_UART_ABORT_COMPLETE_CB_ID :\n        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */\n        break;\n\n      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :\n        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\n        break;\n\n      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :\n        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */\n        break;\n\n      case HAL_UART_MSPINIT_CB_ID :\n        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */\n        break;\n\n      case HAL_UART_MSPDEINIT_CB_ID :\n        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */\n        break;\n\n      default :\n        /* Update the error code */\n        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else if (HAL_UART_STATE_RESET == huart->gState)\n  {\n    switch (CallbackID)\n    {\n      case HAL_UART_MSPINIT_CB_ID :\n        huart->MspInitCallback = HAL_UART_MspInit;\n        break;\n\n      case HAL_UART_MSPDEINIT_CB_ID :\n        huart->MspDeInitCallback = HAL_UART_MspDeInit;\n        break;\n\n      default :\n        /* Update the error code */\n        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n        /* Return error status */\n        status =  HAL_ERROR;\n        break;\n    }\n  }\n  else\n  {\n    /* Update the error code */\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    /* Return error status */\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(huart);\n\n  return status;\n}\n\n/**\n  * @brief  Register a User UART Rx Event Callback\n  *         To be used instead of the weak predefined callback\n  * @param  huart     Uart handle\n  * @param  pCallback Pointer to the Rx Event Callback function\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  if (pCallback == NULL)\n  {\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    return HAL_ERROR;\n  }\n\n  /* Process locked */\n  __HAL_LOCK(huart);\n\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    huart->RxEventCallback = pCallback;\n  }\n  else\n  {\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(huart);\n\n  return status;\n}\n\n/**\n  * @brief  UnRegister the UART Rx Event Callback\n  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback\n  * @param  huart     Uart handle\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)\n{\n  HAL_StatusTypeDef status = HAL_OK;\n\n  /* Process locked */\n  __HAL_LOCK(huart);\n\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */\n  }\n  else\n  {\n    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;\n\n    status =  HAL_ERROR;\n  }\n\n  /* Release Lock */\n  __HAL_UNLOCK(huart);\n  return status;\n}\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n/**\n  * @}\n  */\n\n/** @defgroup UART_Exported_Functions_Group2 IO operation functions\n  *  @brief UART Transmit and Receive functions\n  *\n@verbatim\n ===============================================================================\n                      ##### IO operation functions #####\n ===============================================================================\n    This subsection provides a set of functions allowing to manage the UART asynchronous\n    and Half duplex data transfers.\n\n    (#) There are two modes of transfer:\n       (+) Blocking mode: The communication is performed in polling mode.\n           The HAL status of all data processing is returned by the same function\n           after finishing transfer.\n       (+) Non-Blocking mode: The communication is performed using Interrupts\n           or DMA, these API's return the HAL status.\n           The end of the data processing will be indicated through the\n           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when\n           using DMA mode.\n           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks\n           will be executed respectively at the end of the transmit or receive process\n           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.\n\n    (#) Blocking mode API's are :\n        (+) HAL_UART_Transmit()\n        (+) HAL_UART_Receive()\n\n    (#) Non-Blocking mode API's with Interrupt are :\n        (+) HAL_UART_Transmit_IT()\n        (+) HAL_UART_Receive_IT()\n        (+) HAL_UART_IRQHandler()\n\n    (#) Non-Blocking mode API's with DMA are :\n        (+) HAL_UART_Transmit_DMA()\n        (+) HAL_UART_Receive_DMA()\n        (+) HAL_UART_DMAPause()\n        (+) HAL_UART_DMAResume()\n        (+) HAL_UART_DMAStop()\n\n    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:\n        (+) HAL_UART_TxHalfCpltCallback()\n        (+) HAL_UART_TxCpltCallback()\n        (+) HAL_UART_RxHalfCpltCallback()\n        (+) HAL_UART_RxCpltCallback()\n        (+) HAL_UART_ErrorCallback()\n\n    (#) Non-Blocking mode transfers could be aborted using Abort API's :\n        (+) HAL_UART_Abort()\n        (+) HAL_UART_AbortTransmit()\n        (+) HAL_UART_AbortReceive()\n        (+) HAL_UART_Abort_IT()\n        (+) HAL_UART_AbortTransmit_IT()\n        (+) HAL_UART_AbortReceive_IT()\n\n    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:\n        (+) HAL_UART_AbortCpltCallback()\n        (+) HAL_UART_AbortTransmitCpltCallback()\n        (+) HAL_UART_AbortReceiveCpltCallback()\n\n    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:\n        (+) HAL_UARTEx_RxEventCallback()\n\n    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.\n        Errors are handled as follows :\n       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is\n           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .\n           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,\n           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.\n           If user wants to abort it, Abort services should be called by user.\n       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.\n           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.\n           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.\n\n    -@- In the Half duplex communication, it is forbidden to run the transmit\n        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Sends an amount of data in blocking mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the sent data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 provided through pData.\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be sent\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  uint8_t  *pdata8bits;\n  uint16_t *pdata16bits;\n  uint32_t tickstart = 0U;\n\n  /* Check that a Tx process is not already ongoing */\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n    huart->gState = HAL_UART_STATE_BUSY_TX;\n\n    /* Init tickstart for timeout management */\n    tickstart = HAL_GetTick();\n\n    huart->TxXferSize = Size;\n    huart->TxXferCount = Size;\n\n    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\n    {\n      pdata8bits  = NULL;\n      pdata16bits = (uint16_t *) pData;\n    }\n    else\n    {\n      pdata8bits  = pData;\n      pdata16bits = NULL;\n    }\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(huart);\n\n    while (huart->TxXferCount > 0U)\n    {\n      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)\n      {\n        return HAL_TIMEOUT;\n      }\n      if (pdata8bits == NULL)\n      {\n        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);\n        pdata16bits++;\n      }\n      else\n      {\n        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);\n        pdata8bits++;\n      }\n      huart->TxXferCount--;\n    }\n\n    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)\n    {\n      return HAL_TIMEOUT;\n    }\n\n    /* At end of Tx process, restore huart->gState to Ready */\n    huart->gState = HAL_UART_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receives an amount of data in blocking mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the received data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 available through pData.\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be received.\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)\n{\n  uint8_t  *pdata8bits;\n  uint16_t *pdata16bits;\n  uint32_t tickstart = 0U;\n\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\n    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n    /* Init tickstart for timeout management */\n    tickstart = HAL_GetTick();\n\n    huart->RxXferSize = Size;\n    huart->RxXferCount = Size;\n\n    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\n    {\n      pdata8bits  = NULL;\n      pdata16bits = (uint16_t *) pData;\n    }\n    else\n    {\n      pdata8bits  = pData;\n      pdata16bits = NULL;\n    }\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(huart);\n\n    /* Check the remain data to be received */\n    while (huart->RxXferCount > 0U)\n    {\n      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)\n      {\n        return HAL_TIMEOUT;\n      }\n      if (pdata8bits == NULL)\n      {\n        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);\n        pdata16bits++;\n      }\n      else\n      {\n        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))\n        {\n          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);\n        }\n        else\n        {\n          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);\n        }\n        pdata8bits++;\n      }\n      huart->RxXferCount--;\n    }\n\n    /* At end of Rx process, restore huart->RxState to Ready */\n    huart->RxState = HAL_UART_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sends an amount of data in non blocking mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the sent data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 provided through pData.\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  /* Check that a Tx process is not already ongoing */\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    huart->pTxBuffPtr = pData;\n    huart->TxXferSize = Size;\n    huart->TxXferCount = Size;\n\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n    huart->gState = HAL_UART_STATE_BUSY_TX;\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(huart);\n\n    /* Enable the UART Transmit data register empty Interrupt */\n    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receives an amount of data in non blocking mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the received data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 available through pData.\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be received.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    /* Set Reception type to Standard reception */\n    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n    return(UART_Start_Receive_IT(huart, pData, Size));\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Sends an amount of data in DMA mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the sent data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 provided through pData.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be sent\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  uint32_t *tmp;\n\n  /* Check that a Tx process is not already ongoing */\n  if (huart->gState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    huart->pTxBuffPtr = pData;\n    huart->TxXferSize = Size;\n    huart->TxXferCount = Size;\n\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n    huart->gState = HAL_UART_STATE_BUSY_TX;\n\n    /* Set the UART DMA transfer complete callback */\n    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;\n\n    /* Set the UART DMA Half transfer complete callback */\n    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;\n\n    /* Set the DMA error callback */\n    huart->hdmatx->XferErrorCallback = UART_DMAError;\n\n    /* Set the DMA abort callback */\n    huart->hdmatx->XferAbortCallback = NULL;\n\n    /* Enable the UART transmit DMA stream */\n    tmp = (uint32_t *)&pData;\n    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);\n\n    /* Clear the TC flag in the SR register by writing 0 to it */\n    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);\n\n    /* Process Unlocked */\n    __HAL_UNLOCK(huart);\n\n    /* Enable the DMA transfer for transmit request by setting the DMAT bit\n       in the UART CR3 register */\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Receives an amount of data in DMA mode.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),\n  *         the received data is handled as a set of u16. In this case, Size must indicate the number\n  *         of u16 available through pData.\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART module.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be received.\n  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    /* Process Locked */\n    __HAL_LOCK(huart);\n\n    /* Set Reception type to Standard reception */\n    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n    return(UART_Start_Receive_DMA(huart, pData, Size));\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief Pauses the DMA Transfer.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)\n{\n  uint32_t dmarequest = 0x00U;\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\n  {\n    /* Disable the UART DMA Tx request */\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n  }\n\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\n  {\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n    /* Disable the UART DMA Rx request */\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n  }\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Resumes the DMA Transfer.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)\n{\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  if (huart->gState == HAL_UART_STATE_BUSY_TX)\n  {\n    /* Enable the UART DMA Tx request */\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n  }\n\n  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\n  {\n    /* Clear the Overrun flag before resuming the Rx transfer*/\n    __HAL_UART_CLEAR_OREFLAG(huart);\n\n    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */\n    SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\n    SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n    /* Enable the UART DMA Rx request */\n    SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n  }\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Stops the DMA Transfer.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)\n{\n  uint32_t dmarequest = 0x00U;\n  /* The Lock is not implemented on this API to allow the user application\n     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():\n     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated\n     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()\n     */\n\n  /* Stop UART DMA Tx request if ongoing */\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Abort the UART DMA Tx stream */\n    if (huart->hdmatx != NULL)\n    {\n      HAL_DMA_Abort(huart->hdmatx);\n    }\n    UART_EndTxTransfer(huart);\n  }\n\n  /* Stop UART DMA Rx request if ongoing */\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* Abort the UART DMA Rx stream */\n    if (huart->hdmarx != NULL)\n    {\n      HAL_DMA_Abort(huart->hdmarx);\n    }\n    UART_EndRxTransfer(huart);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.\n  * @note   HAL_OK is returned if reception is completed (expected number of data has been received)\n  *         or if reception is stopped after IDLE event (less than the expected number of data has been received)\n  *         In this case, RxLen output parameter indicates number of data available in reception buffer.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),\n  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number\n  *         of uint16_t available through pData.\n  * @param huart   UART handle.\n  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).\n  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.\n  * @param RxLen   Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)\n  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout)\n{\n  uint8_t  *pdata8bits;\n  uint16_t *pdata16bits;\n  uint32_t tickstart;\n\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return  HAL_ERROR;\n    }\n\n    __HAL_LOCK(huart);\n\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n    huart->RxState = HAL_UART_STATE_BUSY_RX;\n    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;\n\n    /* Init tickstart for timeout management */\n    tickstart = HAL_GetTick();\n\n    huart->RxXferSize  = Size;\n    huart->RxXferCount = Size;\n\n    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\n    {\n      pdata8bits  = NULL;\n      pdata16bits = (uint16_t *) pData;\n    }\n    else\n    {\n      pdata8bits  = pData;\n      pdata16bits = NULL;\n    }\n\n    __HAL_UNLOCK(huart);\n\n    /* Initialize output number of received elements */\n    *RxLen = 0U;\n\n    /* as long as data have to be received */\n    while (huart->RxXferCount > 0U)\n    {\n      /* Check if IDLE flag is set */\n      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))\n      {\n        /* Clear IDLE flag in ISR */\n        __HAL_UART_CLEAR_IDLEFLAG(huart);\n\n        /* If Set, but no data ever received, clear flag without exiting loop */\n        /* If Set, and data has already been received, this means Idle Event is valid : End reception */\n        if (*RxLen > 0U)\n        {\n          huart->RxState = HAL_UART_STATE_READY;\n\n          return HAL_OK;\n        }\n      }\n\n      /* Check if RXNE flag is set */\n      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))\n      {\n        if (pdata8bits == NULL)\n        {\n          *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);\n          pdata16bits++;\n        }\n        else\n        {\n           if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))\n           {\n             *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);\n           }\n           else\n           {\n             *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);\n           }\n\n          pdata8bits++;\n        }\n        /* Increment number of received elements */\n        *RxLen += 1U;\n        huart->RxXferCount--;\n      }\n\n      /* Check for the Timeout */\n      if (Timeout != HAL_MAX_DELAY)\n      {\n        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))\n        {\n          huart->RxState = HAL_UART_STATE_READY;\n\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n\n    /* Set number of received elements in output parameter : RxLen */\n    *RxLen = huart->RxXferSize - huart->RxXferCount;\n    /* At end of Rx process, restore huart->RxState to Ready */\n    huart->RxState = HAL_UART_STATE_READY;\n\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.\n  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks\n  *         to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating\n  *         number of received data elements.\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),\n  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number\n  *         of uint16_t available through pData.\n  * @param huart UART handle.\n  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).\n  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef status;\n\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    __HAL_LOCK(huart);\n\n    /* Set Reception type to reception till IDLE Event*/\n    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;\n\n    status =  UART_Start_Receive_IT(huart, pData, Size);\n\n    /* Check Rx process has been successfully started */\n    if (status == HAL_OK)\n    {\n      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n      {\n        __HAL_UART_CLEAR_IDLEFLAG(huart);\n        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n      }\n      else\n      {\n        /* In case of errors already pending when reception is started,\n           Interrupts may have already been raised and lead to reception abortion.\n           (Overrun error for instance).\n           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */\n        status = HAL_ERROR;\n      }\n    }\n\n    return status;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.\n  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks\n  *         to DMA services, transferring automatically received data elements in user reception buffer and\n  *         calling registered callbacks at half/end of reception. UART IDLE events are also used to consider\n  *         reception phase as ended. In all cases, callback execution will indicate number of received data elements.\n  * @note   When the UART parity is enabled (PCE = 1), the received data contain\n  *         the parity bit (MSB position).\n  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),\n  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number\n  *         of uint16_t available through pData.\n  * @param huart UART handle.\n  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).\n  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  HAL_StatusTypeDef status;\n\n  /* Check that a Rx process is not already ongoing */\n  if (huart->RxState == HAL_UART_STATE_READY)\n  {\n    if ((pData == NULL) || (Size == 0U))\n    {\n      return HAL_ERROR;\n    }\n\n    __HAL_LOCK(huart);\n\n    /* Set Reception type to reception till IDLE Event*/\n    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;\n\n    status =  UART_Start_Receive_DMA(huart, pData, Size);\n\n    /* Check Rx process has been successfully started */\n    if (status == HAL_OK)\n    {\n      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n      {\n        __HAL_UART_CLEAR_IDLEFLAG(huart);\n        SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n      }\n      else\n      {\n        /* In case of errors already pending when reception is started,\n           Interrupts may have already been raised and lead to reception abortion.\n           (Overrun error for instance).\n           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */\n        status = HAL_ERROR;\n      }\n    }\n\n    return status;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Abort ongoing transfers (blocking mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Tx and Rx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)\n{\n  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));\n  }\n\n  /* Disable the UART DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */\n    if (huart->hdmatx != NULL)\n    {\n      /* Set the UART DMA Abort callback to Null.\n         No call back execution at end of DMA abort procedure */\n      huart->hdmatx->XferAbortCallback = NULL;\n\n      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\n      {\n        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\n        {\n          /* Set error code to DMA */\n          huart->ErrorCode = HAL_UART_ERROR_DMA;\n\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n\n  /* Disable the UART DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */\n    if (huart->hdmarx != NULL)\n    {\n      /* Set the UART DMA Abort callback to Null.\n         No call back execution at end of DMA abort procedure */\n      huart->hdmarx->XferAbortCallback = NULL;\n\n      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\n      {\n        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\n        {\n          /* Set error code to DMA */\n          huart->ErrorCode = HAL_UART_ERROR_DMA;\n\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n\n  /* Reset Tx and Rx transfer counters */\n  huart->TxXferCount = 0x00U;\n  huart->RxXferCount = 0x00U;\n\n  /* Reset ErrorCode */\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n\n  /* Restore huart->RxState and huart->gState to Ready */\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->gState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing Transmit transfer (blocking mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Tx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)\n{\n  /* Disable TXEIE and TCIE interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\n\n  /* Disable the UART DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */\n    if (huart->hdmatx != NULL)\n    {\n      /* Set the UART DMA Abort callback to Null.\n         No call back execution at end of DMA abort procedure */\n      huart->hdmatx->XferAbortCallback = NULL;\n\n      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)\n      {\n        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)\n        {\n          /* Set error code to DMA */\n          huart->ErrorCode = HAL_UART_ERROR_DMA;\n\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n\n  /* Reset Tx transfer counter */\n  huart->TxXferCount = 0x00U;\n\n  /* Restore huart->gState to Ready */\n  huart->gState = HAL_UART_STATE_READY;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing Receive transfer (blocking mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Rx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)\n{\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));\n  }\n\n  /* Disable the UART DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */\n    if (huart->hdmarx != NULL)\n    {\n      /* Set the UART DMA Abort callback to Null.\n         No call back execution at end of DMA abort procedure */\n      huart->hdmarx->XferAbortCallback = NULL;\n\n      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)\n      {\n        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)\n        {\n          /* Set error code to DMA */\n          huart->ErrorCode = HAL_UART_ERROR_DMA;\n\n          return HAL_TIMEOUT;\n        }\n      }\n    }\n  }\n\n  /* Reset Rx transfer counter */\n  huart->RxXferCount = 0x00U;\n\n  /* Restore huart->RxState to Ready */\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing transfers (Interrupt mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Tx and Rx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  *           - At abort completion, call user abort complete callback\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)\n{\n  uint32_t AbortCplt = 0x01U;\n\n  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));\n  }\n\n  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised\n     before any call to DMA Abort functions */\n  /* DMA Tx Handle is valid */\n  if (huart->hdmatx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.\n       Otherwise, set it to NULL */\n    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\n    {\n      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;\n    }\n    else\n    {\n      huart->hdmatx->XferAbortCallback = NULL;\n    }\n  }\n  /* DMA Rx Handle is valid */\n  if (huart->hdmarx != NULL)\n  {\n    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.\n       Otherwise, set it to NULL */\n    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n    {\n      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;\n    }\n    else\n    {\n      huart->hdmarx->XferAbortCallback = NULL;\n    }\n  }\n\n  /* Disable the UART DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\n  {\n    /* Disable DMA Tx at UART level */\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */\n    if (huart->hdmatx != NULL)\n    {\n      /* UART Tx DMA Abort callback has already been initialised :\n         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\n\n      /* Abort DMA TX */\n      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\n      {\n        huart->hdmatx->XferAbortCallback = NULL;\n      }\n      else\n      {\n        AbortCplt = 0x00U;\n      }\n    }\n  }\n\n  /* Disable the UART DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */\n    if (huart->hdmarx != NULL)\n    {\n      /* UART Rx DMA Abort callback has already been initialised :\n         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\n\n      /* Abort DMA RX */\n      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\n      {\n        huart->hdmarx->XferAbortCallback = NULL;\n        AbortCplt = 0x01U;\n      }\n      else\n      {\n        AbortCplt = 0x00U;\n      }\n    }\n  }\n\n  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */\n  if (AbortCplt == 0x01U)\n  {\n    /* Reset Tx and Rx transfer counters */\n    huart->TxXferCount = 0x00U;\n    huart->RxXferCount = 0x00U;\n\n    /* Reset ErrorCode */\n    huart->ErrorCode = HAL_UART_ERROR_NONE;\n\n    /* Restore huart->gState and huart->RxState to Ready */\n    huart->gState  = HAL_UART_STATE_READY;\n    huart->RxState = HAL_UART_STATE_READY;\n    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n    /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /* Call registered Abort complete callback */\n    huart->AbortCpltCallback(huart);\n#else\n    /* Call legacy weak Abort complete callback */\n    HAL_UART_AbortCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing Transmit transfer (Interrupt mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Tx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  *           - At abort completion, call user abort complete callback\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)\n{\n  /* Disable TXEIE and TCIE interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\n\n  /* Disable the UART DMA Tx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */\n    if (huart->hdmatx != NULL)\n    {\n      /* Set the UART DMA Abort callback :\n         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\n      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;\n\n      /* Abort DMA TX */\n      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)\n      {\n        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */\n        huart->hdmatx->XferAbortCallback(huart->hdmatx);\n      }\n    }\n    else\n    {\n      /* Reset Tx transfer counter */\n      huart->TxXferCount = 0x00U;\n\n      /* Restore huart->gState to Ready */\n      huart->gState = HAL_UART_STATE_READY;\n\n      /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n      /* Call registered Abort Transmit Complete Callback */\n      huart->AbortTransmitCpltCallback(huart);\n#else\n      /* Call legacy weak Abort Transmit Complete Callback */\n      HAL_UART_AbortTransmitCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n    }\n  }\n  else\n  {\n    /* Reset Tx transfer counter */\n    huart->TxXferCount = 0x00U;\n\n    /* Restore huart->gState to Ready */\n    huart->gState = HAL_UART_STATE_READY;\n\n    /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /* Call registered Abort Transmit Complete Callback */\n    huart->AbortTransmitCpltCallback(huart);\n#else\n    /* Call legacy weak Abort Transmit Complete Callback */\n    HAL_UART_AbortTransmitCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Abort ongoing Receive transfer (Interrupt mode).\n  * @param  huart UART handle.\n  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.\n  *         This procedure performs following operations :\n  *           - Disable UART Interrupts (Rx)\n  *           - Disable the DMA transfer in the peripheral register (if enabled)\n  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)\n  *           - Set handle State to READY\n  *           - At abort completion, call user abort complete callback\n  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be\n  *         considered as completed only when user abort complete callback is executed (not when exiting function).\n  * @retval HAL status\n*/\nHAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)\n{\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n    CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));\n  }\n\n  /* Disable the UART DMA Rx request if enabled */\n  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n  {\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */\n    if (huart->hdmarx != NULL)\n    {\n      /* Set the UART DMA Abort callback :\n         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */\n      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;\n\n      /* Abort DMA RX */\n      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\n      {\n        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */\n        huart->hdmarx->XferAbortCallback(huart->hdmarx);\n      }\n    }\n    else\n    {\n      /* Reset Rx transfer counter */\n      huart->RxXferCount = 0x00U;\n\n      /* Restore huart->RxState to Ready */\n      huart->RxState = HAL_UART_STATE_READY;\n      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n      /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n      /* Call registered Abort Receive Complete Callback */\n      huart->AbortReceiveCpltCallback(huart);\n#else\n      /* Call legacy weak Abort Receive Complete Callback */\n      HAL_UART_AbortReceiveCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n    }\n  }\n  else\n  {\n    /* Reset Rx transfer counter */\n    huart->RxXferCount = 0x00U;\n\n    /* Restore huart->RxState to Ready */\n    huart->RxState = HAL_UART_STATE_READY;\n    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n    /* As no DMA to be aborted, call directly user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /* Call registered Abort Receive Complete Callback */\n    huart->AbortReceiveCpltCallback(huart);\n#else\n    /* Call legacy weak Abort Receive Complete Callback */\n    HAL_UART_AbortReceiveCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  This function handles UART interrupt request.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\nvoid HAL_UART_IRQHandler(UART_HandleTypeDef *huart)\n{\n  uint32_t isrflags   = READ_REG(huart->Instance->SR);\n  uint32_t cr1its     = READ_REG(huart->Instance->CR1);\n  uint32_t cr3its     = READ_REG(huart->Instance->CR3);\n  uint32_t errorflags = 0x00U;\n  uint32_t dmarequest = 0x00U;\n\n  /* If no error occurs */\n  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));\n  if (errorflags == RESET)\n  {\n    /* UART in mode Receiver -------------------------------------------------*/\n    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\n    {\n      UART_Receive_IT(huart);\n      return;\n    }\n  }\n\n  /* If some errors occur */\n  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))\n  {\n    /* UART parity error interrupt occurred ----------------------------------*/\n    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))\n    {\n      huart->ErrorCode |= HAL_UART_ERROR_PE;\n    }\n\n    /* UART noise error interrupt occurred -----------------------------------*/\n    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\n    {\n      huart->ErrorCode |= HAL_UART_ERROR_NE;\n    }\n\n    /* UART frame error interrupt occurred -----------------------------------*/\n    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))\n    {\n      huart->ErrorCode |= HAL_UART_ERROR_FE;\n    }\n\n    /* UART Over-Run interrupt occurred --------------------------------------*/\n    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))\n    {\n      huart->ErrorCode |= HAL_UART_ERROR_ORE;\n    }\n\n    /* Call UART Error Call back function if need be --------------------------*/\n    if (huart->ErrorCode != HAL_UART_ERROR_NONE)\n    {\n      /* UART in mode Receiver -----------------------------------------------*/\n      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))\n      {\n        UART_Receive_IT(huart);\n      }\n\n      /* If Overrun error occurs, or if any error occurs in DMA mode reception,\n         consider error as blocking */\n      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\n      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)\n      {\n        /* Blocking error : transfer is aborted\n           Set the UART state ready to be able to start again the process,\n           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */\n        UART_EndRxTransfer(huart);\n\n        /* Disable the UART DMA Rx request if enabled */\n        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n        {\n          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n          /* Abort the UART DMA Rx stream */\n          if (huart->hdmarx != NULL)\n          {\n            /* Set the UART DMA Abort callback :\n               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */\n            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;\n            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)\n            {\n              /* Call Directly XferAbortCallback function in case of error */\n              huart->hdmarx->XferAbortCallback(huart->hdmarx);\n            }\n          }\n          else\n          {\n            /* Call user error callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n            /*Call registered error callback*/\n            huart->ErrorCallback(huart);\n#else\n            /*Call legacy weak error callback*/\n            HAL_UART_ErrorCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n          }\n        }\n        else\n        {\n          /* Call user error callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n          /*Call registered error callback*/\n          huart->ErrorCallback(huart);\n#else\n          /*Call legacy weak error callback*/\n          HAL_UART_ErrorCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n        }\n      }\n      else\n      {\n        /* Non Blocking error : transfer could go on.\n           Error is notified to user through user error callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n        /*Call registered error callback*/\n        huart->ErrorCallback(huart);\n#else\n        /*Call legacy weak error callback*/\n        HAL_UART_ErrorCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n        huart->ErrorCode = HAL_UART_ERROR_NONE;\n      }\n    }\n    return;\n  } /* End if some error occurs */\n\n  /* Check current reception Mode :\n     If Reception till IDLE event has been selected : */\n  if (  (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n      &&((isrflags & USART_SR_IDLE) != 0U)\n      &&((cr1its & USART_SR_IDLE) != 0U))\n  {\n    __HAL_UART_CLEAR_IDLEFLAG(huart);\n\n    /* Check if DMA mode is enabled in UART */\n    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))\n    {\n      /* DMA mode enabled */\n      /* Check received length : If all expected data are received, do nothing,\n         (DMA cplt callback will be called).\n         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */\n      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);\n      if (  (nb_remaining_rx_data > 0U)\n          &&(nb_remaining_rx_data < huart->RxXferSize))\n      {\n        /* Reception is not complete */\n        huart->RxXferCount = nb_remaining_rx_data;\n\n        /* In Normal mode, end DMA xfer and HAL UART Rx process*/\n        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)\n        {\n          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */\n          CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\n          CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit\n             in the UART CR3 register */\n          CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n          /* At end of Rx process, restore huart->RxState to Ready */\n          huart->RxState = HAL_UART_STATE_READY;\n          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n          CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n\n          /* Last bytes received, so no need as the abort is immediate */\n          (void)HAL_DMA_Abort(huart->hdmarx);\n        }\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n        /*Call registered Rx Event callback*/\n        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));\n#else\n        /*Call legacy weak Rx Event callback*/\n        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));\n#endif\n      }\n      return;\n    }\n    else\n    {\n      /* DMA mode not enabled */\n      /* Check received length : If all expected data are received, do nothing.\n         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */\n      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;\n      if (  (huart->RxXferCount > 0U)\n          &&(nb_rx_data > 0U) )\n      {\n        /* Disable the UART Parity Error Interrupt and RXNE interrupts */\n        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\n\n        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\n        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n        /* Rx process is completed, restore huart->RxState to Ready */\n        huart->RxState = HAL_UART_STATE_READY;\n        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n        /*Call registered Rx complete callback*/\n        huart->RxEventCallback(huart, nb_rx_data);\n#else\n        /*Call legacy weak Rx Event callback*/\n        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);\n#endif\n      }\n      return;\n    }\n  }\n\n  /* UART in mode Transmitter ------------------------------------------------*/\n  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))\n  {\n    UART_Transmit_IT(huart);\n    return;\n  }\n\n  /* UART in mode Transmitter end --------------------------------------------*/\n  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))\n  {\n    UART_EndTransmit_IT(huart);\n    return;\n  }\n}\n\n/**\n  * @brief  Tx Transfer completed callbacks.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_TxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Tx Half Transfer completed callbacks.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_TxHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Rx Transfer completed callbacks.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_RxCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  Rx Half Transfer completed callbacks.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_RxHalfCpltCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  UART error callbacks.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\n__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  /* NOTE: This function should not be modified, when the callback is needed,\n           the HAL_UART_ErrorCallback could be implemented in the user file\n   */\n}\n\n/**\n  * @brief  UART Abort Complete callback.\n  * @param  huart UART handle.\n  * @retval None\n  */\n__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_UART_AbortCpltCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @brief  UART Abort Complete callback.\n  * @param  huart UART handle.\n  * @retval None\n  */\n__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @brief  UART Abort Receive Complete callback.\n  * @param  huart UART handle.\n  * @retval None\n  */\n__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).\n  * @param  huart UART handle\n  * @param  Size  Number of data available in application reception buffer (indicates a position in\n  *               reception buffer until which, data are available)\n  * @retval None\n  */\n__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)\n{\n  /* Prevent unused argument(s) compilation warning */\n  UNUSED(huart);\n  UNUSED(Size);\n\n  /* NOTE : This function should not be modified, when the callback is needed,\n            the HAL_UARTEx_RxEventCallback can be implemented in the user file.\n   */\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions\n  *  @brief   UART control functions\n  *\n@verbatim\n  ==============================================================================\n                      ##### Peripheral Control functions #####\n  ==============================================================================\n  [..]\n    This subsection provides a set of functions allowing to control the UART:\n    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.\n    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.\n    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.\n    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode\n    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Transmits break characters.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)\n{\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(huart->Instance));\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Send break characters */\n  SET_BIT(huart->Instance->CR1, USART_CR1_SBK);\n\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Enters the UART in mute mode.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)\n{\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(huart->Instance));\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */\n  SET_BIT(huart->Instance->CR1, USART_CR1_RWU);\n\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Exits the UART mute mode: wake up software.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)\n{\n  /* Check the parameters */\n  assert_param(IS_UART_INSTANCE(huart->Instance));\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */\n  CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);\n\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Enables the UART transmitter and disables the UART receiver.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)\n{\n  uint32_t tmpreg = 0x00U;\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /*-------------------------- USART CR1 Configuration -----------------------*/\n  tmpreg = huart->Instance->CR1;\n\n  /* Clear TE and RE bits */\n  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));\n\n  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */\n  tmpreg |= (uint32_t)USART_CR1_TE;\n\n  /* Write to USART CR1 */\n  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);\n\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Enables the UART receiver and disables the UART transmitter.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)\n{\n  uint32_t tmpreg = 0x00U;\n\n  /* Process Locked */\n  __HAL_LOCK(huart);\n\n  huart->gState = HAL_UART_STATE_BUSY;\n\n  /*-------------------------- USART CR1 Configuration -----------------------*/\n  tmpreg = huart->Instance->CR1;\n\n  /* Clear TE and RE bits */\n  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));\n\n  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */\n  tmpreg |= (uint32_t)USART_CR1_RE;\n\n  /* Write to USART CR1 */\n  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);\n\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  return HAL_OK;\n}\n\n/**\n  * @}\n  */\n\n/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions\n  *  @brief   UART State and Errors functions\n  *\n@verbatim\n  ==============================================================================\n                 ##### Peripheral State and Errors functions #####\n  ==============================================================================\n [..]\n   This subsection provides a set of functions allowing to return the State of\n   UART communication process, return Peripheral Errors occurred during communication\n   process\n   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.\n   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Returns the UART state.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL state\n  */\nHAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)\n{\n  uint32_t temp1 = 0x00U, temp2 = 0x00U;\n  temp1 = huart->gState;\n  temp2 = huart->RxState;\n\n  return (HAL_UART_StateTypeDef)(temp1 | temp2);\n}\n\n/**\n  * @brief  Return the UART error code\n  * @param  huart Pointer to a UART_HandleTypeDef structure that contains\n  *               the configuration information for the specified UART.\n  * @retval UART Error Code\n  */\nuint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)\n{\n  return huart->ErrorCode;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/** @defgroup UART_Private_Functions UART Private Functions\n  * @{\n  */\n\n/**\n  * @brief  Initialize the callbacks to their default values.\n  * @param  huart UART handle.\n  * @retval none\n  */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\nvoid UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)\n{\n  /* Init the UART Callback settings */\n  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */\n  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */\n  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */\n  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */\n  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */\n  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */\n  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */\n  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */\n  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */\n\n}\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n/**\n  * @brief  DMA UART transmit process complete callback.\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n  /* DMA Normal mode*/\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\n  {\n    huart->TxXferCount = 0x00U;\n\n    /* Disable the DMA transfer for transmit request by setting the DMAT bit\n       in the UART CR3 register */\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);\n\n    /* Enable the UART Transmit Complete Interrupt */\n    SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);\n\n  }\n  /* DMA Circular mode */\n  else\n  {\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /*Call registered Tx complete callback*/\n    huart->TxCpltCallback(huart);\n#else\n    /*Call legacy weak Tx complete callback*/\n    HAL_UART_TxCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief DMA UART transmit process half complete callback\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /*Call registered Tx complete callback*/\n  huart->TxHalfCpltCallback(huart);\n#else\n  /*Call legacy weak Tx complete callback*/\n  HAL_UART_TxHalfCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA UART receive process complete callback.\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n  /* DMA Normal mode*/\n  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)\n  {\n    huart->RxXferCount = 0U;\n\n    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n    /* Disable the DMA transfer for the receiver request by setting the DMAR bit\n       in the UART CR3 register */\n    CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n    /* At end of Rx process, restore huart->RxState to Ready */\n    huart->RxState = HAL_UART_STATE_READY;\n\n    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */\n    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n    {\n      CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n    }\n  }\n\n  /* Check current reception Mode :\n     If Reception till IDLE event has been selected : use Rx Event callback */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {  \n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /*Call registered Rx Event callback*/\n    huart->RxEventCallback(huart, huart->RxXferSize);\n#else\n    /*Call legacy weak Rx Event callback*/\n    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* In other cases : use Rx Complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /*Call registered Rx complete callback*/\n    huart->RxCpltCallback(huart);\n#else\n    /*Call legacy weak Rx complete callback*/\n    HAL_UART_RxCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief DMA UART receive process half complete callback\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  /* Check current reception Mode :\n     If Reception till IDLE event has been selected : use Rx Event callback */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /*Call registered Rx Event callback*/\n    huart->RxEventCallback(huart, huart->RxXferSize/2U);\n#else\n    /*Call legacy weak Rx Event callback*/\n    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n  else\n  {\n    /* In other cases : use Rx Half Complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n    /*Call registered Rx Half complete callback*/\n    huart->RxHalfCpltCallback(huart);\n#else\n    /*Call legacy weak Rx Half complete callback*/\n    HAL_UART_RxHalfCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n  }\n}\n\n/**\n  * @brief  DMA UART communication error callback.\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMAError(DMA_HandleTypeDef *hdma)\n{\n  uint32_t dmarequest = 0x00U;\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  /* Stop UART DMA Tx request if ongoing */\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);\n  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)\n  {\n    huart->TxXferCount = 0x00U;\n    UART_EndTxTransfer(huart);\n  }\n\n  /* Stop UART DMA Rx request if ongoing */\n  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);\n  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)\n  {\n    huart->RxXferCount = 0x00U;\n    UART_EndRxTransfer(huart);\n  }\n\n  huart->ErrorCode |= HAL_UART_ERROR_DMA;\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /*Call registered error callback*/\n  huart->ErrorCallback(huart);\n#else\n  /*Call legacy weak error callback*/\n  HAL_UART_ErrorCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  This function handles UART Communication Timeout.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @param  Flag specifies the UART flag to check.\n  * @param  Status The new Flag status (SET or RESET).\n  * @param  Tickstart Tick start value\n  * @param  Timeout Timeout duration\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)\n{\n  /* Wait until flag is set */\n  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)\n  {\n    /* Check for the Timeout */\n    if (Timeout != HAL_MAX_DELAY)\n    {\n      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))\n      {\n        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */\n        CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));\n        CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n        huart->gState  = HAL_UART_STATE_READY;\n        huart->RxState = HAL_UART_STATE_READY;\n\n        /* Process Unlocked */\n        __HAL_UNLOCK(huart);\n\n        return HAL_TIMEOUT;\n      }\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Start Receive operation in interrupt mode.\n  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.\n  * @note   When calling this function, parameters validity is considered as already checked,\n  *         i.e. Rx State, buffer address, ...\n  *         UART Handle is assumed as Locked.\n  * @param  huart UART handle.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be received.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  huart->pRxBuffPtr = pData;\n  huart->RxXferSize = Size;\n  huart->RxXferCount = Size;\n\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->RxState = HAL_UART_STATE_BUSY_RX;\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  /* Enable the UART Parity Error Interrupt */\n  __HAL_UART_ENABLE_IT(huart, UART_IT_PE);\n\n  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\n  __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);\n\n  /* Enable the UART Data Register not empty Interrupt */\n  __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Start Receive operation in DMA mode.\n  * @note   This function could be called by all HAL UART API providing reception in DMA mode.\n  * @note   When calling this function, parameters validity is considered as already checked,\n  *         i.e. Rx State, buffer address, ...\n  *         UART Handle is assumed as Locked.\n  * @param  huart UART handle.\n  * @param  pData Pointer to data buffer (u8 or u16 data elements).\n  * @param  Size  Amount of data elements (u8 or u16) to be received.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)\n{\n  uint32_t *tmp;\n\n  huart->pRxBuffPtr = pData;\n  huart->RxXferSize = Size;\n\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n  huart->RxState = HAL_UART_STATE_BUSY_RX;\n\n  /* Set the UART DMA transfer complete callback */\n  huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;\n\n  /* Set the UART DMA Half transfer complete callback */\n  huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;\n\n  /* Set the DMA error callback */\n  huart->hdmarx->XferErrorCallback = UART_DMAError;\n\n  /* Set the DMA abort callback */\n  huart->hdmarx->XferAbortCallback = NULL;\n\n  /* Enable the DMA stream */\n  tmp = (uint32_t *)&pData;\n  HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);\n\n  /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */\n  __HAL_UART_CLEAR_OREFLAG(huart);\n\n  /* Process Unlocked */\n  __HAL_UNLOCK(huart);\n\n  /* Enable the UART Parity Error Interrupt */\n  SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);\n\n  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */\n  SET_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* Enable the DMA transfer for the receiver request by setting the DMAR bit\n  in the UART CR3 register */\n  SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).\n  * @param  huart UART handle.\n  * @retval None\n  */\nstatic void UART_EndTxTransfer(UART_HandleTypeDef *huart)\n{\n  /* Disable TXEIE and TCIE interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));\n\n  /* At end of Tx process, restore huart->gState to Ready */\n  huart->gState = HAL_UART_STATE_READY;\n}\n\n/**\n  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).\n  * @param  huart UART handle.\n  * @retval None\n  */\nstatic void UART_EndRxTransfer(UART_HandleTypeDef *huart)\n{\n  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */\n  CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));\n  CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);\n\n  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */\n  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n  {\n    CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n  }\n\n  /* At end of Rx process, restore huart->RxState to Ready */\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n}\n\n/**\n  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error\n  *         (To be called at end of DMA Abort procedure following error occurrence).\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n  huart->RxXferCount = 0x00U;\n  huart->TxXferCount = 0x00U;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /*Call registered error callback*/\n  huart->ErrorCallback(huart);\n#else\n  /*Call legacy weak error callback*/\n  HAL_UART_ErrorCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA UART Tx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Tx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Rx DMA Handle.\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  huart->hdmatx->XferAbortCallback = NULL;\n\n  /* Check if an Abort process is still ongoing */\n  if (huart->hdmarx != NULL)\n  {\n    if (huart->hdmarx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\n  huart->TxXferCount = 0x00U;\n  huart->RxXferCount = 0x00U;\n\n  /* Reset ErrorCode */\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n\n  /* Restore huart->gState and huart->RxState to Ready */\n  huart->gState  = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /* Call registered Abort complete callback */\n  huart->AbortCpltCallback(huart);\n#else\n  /* Call legacy weak Abort complete callback */\n  HAL_UART_AbortCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA UART Rx communication abort callback, when initiated by user\n  *         (To be called at end of DMA Rx Abort procedure following user abort request).\n  * @note   When this callback is executed, User Abort complete call back is called only if no\n  *         Abort still ongoing for Tx DMA Handle.\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  huart->hdmarx->XferAbortCallback = NULL;\n\n  /* Check if an Abort process is still ongoing */\n  if (huart->hdmatx != NULL)\n  {\n    if (huart->hdmatx->XferAbortCallback != NULL)\n    {\n      return;\n    }\n  }\n\n  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */\n  huart->TxXferCount = 0x00U;\n  huart->RxXferCount = 0x00U;\n\n  /* Reset ErrorCode */\n  huart->ErrorCode = HAL_UART_ERROR_NONE;\n\n  /* Restore huart->gState and huart->RxState to Ready */\n  huart->gState  = HAL_UART_STATE_READY;\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /* Call registered Abort complete callback */\n  huart->AbortCpltCallback(huart);\n#else\n  /* Call legacy weak Abort complete callback */\n  HAL_UART_AbortCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to\n  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)\n  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,\n  *         and leads to user Tx Abort Complete callback execution).\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  huart->TxXferCount = 0x00U;\n\n  /* Restore huart->gState to Ready */\n  huart->gState = HAL_UART_STATE_READY;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /* Call registered Abort Transmit Complete Callback */\n  huart->AbortTransmitCpltCallback(huart);\n#else\n  /* Call legacy weak Abort Transmit Complete Callback */\n  HAL_UART_AbortTransmitCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to\n  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)\n  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,\n  *         and leads to user Rx Abort Complete callback execution).\n  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains\n  *               the configuration information for the specified DMA module.\n  * @retval None\n  */\nstatic void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)\n{\n  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;\n\n  huart->RxXferCount = 0x00U;\n\n  /* Restore huart->RxState to Ready */\n  huart->RxState = HAL_UART_STATE_READY;\n  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n\n  /* Call user Abort complete callback */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /* Call registered Abort Receive Complete Callback */\n  huart->AbortReceiveCpltCallback(huart);\n#else\n  /* Call legacy weak Abort Receive Complete Callback */\n  HAL_UART_AbortReceiveCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n}\n\n/**\n  * @brief  Sends an amount of data in non blocking mode.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)\n{\n  uint16_t *tmp;\n\n  /* Check that a Tx process is ongoing */\n  if (huart->gState == HAL_UART_STATE_BUSY_TX)\n  {\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\n    {\n      tmp = (uint16_t *) huart->pTxBuffPtr;\n      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);\n      huart->pTxBuffPtr += 2U;\n    }\n    else\n    {\n      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);\n    }\n\n    if (--huart->TxXferCount == 0U)\n    {\n      /* Disable the UART Transmit Complete Interrupt */\n      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);\n\n      /* Enable the UART Transmit Complete Interrupt */\n      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);\n    }\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Wraps up transmission in non blocking mode.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)\n{\n  /* Disable the UART Transmit Complete Interrupt */\n  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);\n\n  /* Tx process is ended, restore huart->gState to Ready */\n  huart->gState = HAL_UART_STATE_READY;\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n  /*Call registered Tx complete callback*/\n  huart->TxCpltCallback(huart);\n#else\n  /*Call legacy weak Tx complete callback*/\n  HAL_UART_TxCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Receives an amount of data in non blocking mode\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)\n{\n  uint8_t  *pdata8bits;\n  uint16_t *pdata16bits;\n\n  /* Check that a Rx process is ongoing */\n  if (huart->RxState == HAL_UART_STATE_BUSY_RX)\n  {\n    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))\n    {\n      pdata8bits  = NULL;\n      pdata16bits = (uint16_t *) huart->pRxBuffPtr;\n      *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);\n      huart->pRxBuffPtr += 2U;\n    }\n    else\n    {\n      pdata8bits = (uint8_t *) huart->pRxBuffPtr;\n      pdata16bits  = NULL;\n\n      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))\n      {\n        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);\n      }\n      else\n      {\n        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);\n      }\n      huart->pRxBuffPtr += 1U;\n    }\n\n    if (--huart->RxXferCount == 0U)\n    {\n      /* Disable the UART Data Register not empty Interrupt */\n      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);\n\n      /* Disable the UART Parity Error Interrupt */\n      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);\n\n      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */\n      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);\n\n      /* Rx process is completed, restore huart->RxState to Ready */\n      huart->RxState = HAL_UART_STATE_READY;\n\n      /* Check current reception Mode :\n         If Reception till IDLE event has been selected : */\n      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)\n      {\n        /* Disable IDLE interrupt */\n        CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);\n\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\n        /*Call registered Rx Event callback*/\n        huart->RxEventCallback(huart, huart->RxXferSize);\n#else\n        /*Call legacy weak Rx Event callback*/\n        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);\n#endif\n      }\n      else\n      {\n       /* Standard reception API called */\n#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)\t\t  \n       /*Call registered Rx complete callback*/\n       huart->RxCpltCallback(huart);\n#else\n       /*Call legacy weak Rx complete callback*/\n       HAL_UART_RxCpltCallback(huart);\n#endif /* USE_HAL_UART_REGISTER_CALLBACKS */\n      }\n      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;\n      return HAL_OK;\n    }\n    return HAL_OK;\n  }\n  else\n  {\n    return HAL_BUSY;\n  }\n}\n\n/**\n  * @brief  Configures the UART peripheral.\n  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains\n  *                the configuration information for the specified UART module.\n  * @retval None\n  */\nstatic void UART_SetConfig(UART_HandleTypeDef *huart)\n{\n  uint32_t tmpreg;\n  uint32_t pclk;\n\n  /* Check the parameters */\n  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));\n  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));\n  assert_param(IS_UART_PARITY(huart->Init.Parity));\n  assert_param(IS_UART_MODE(huart->Init.Mode));\n\n  /*-------------------------- USART CR2 Configuration -----------------------*/\n  /* Configure the UART Stop Bits: Set STOP[13:12] bits\n     according to huart->Init.StopBits value */\n  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);\n\n  /*-------------------------- USART CR1 Configuration -----------------------*/\n  /* Configure the UART Word Length, Parity and mode:\n     Set the M bits according to huart->Init.WordLength value\n     Set PCE and PS bits according to huart->Init.Parity value\n     Set TE and RE bits according to huart->Init.Mode value\n     Set OVER8 bit according to huart->Init.OverSampling value */\n\n  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;\n  MODIFY_REG(huart->Instance->CR1,\n             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),\n             tmpreg);\n\n  /*-------------------------- USART CR3 Configuration -----------------------*/\n  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */\n  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);\n\n\n#if defined(USART6) && defined(UART9) && defined(UART10)\n    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))\n    {\n      pclk = HAL_RCC_GetPCLK2Freq();\n    }\n#elif defined(USART6)\n    if ((huart->Instance == USART1) || (huart->Instance == USART6))\n    {\n      pclk = HAL_RCC_GetPCLK2Freq();\n    }\n#else\n    if (huart->Instance == USART1)\n    {\n      pclk = HAL_RCC_GetPCLK2Freq();\n    }\n#endif /* USART6 */\n    else\n    {\n      pclk = HAL_RCC_GetPCLK1Freq();\n    }\n  /*-------------------------- USART BRR Configuration ---------------------*/\n  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)\n  {\n    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);\n  }\n  else\n  {\n    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);\n  }\n}\n\n/**\n  * @}\n  */\n\n#endif /* HAL_UART_MODULE_ENABLED */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_adc.c\n  * @author  MCD Application Team\n  * @brief   ADC LL module driver\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n#if defined(USE_FULL_LL_DRIVER)\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_ll_adc.h\"\n#include \"stm32f4xx_ll_bus.h\"\n\n#ifdef  USE_FULL_ASSERT\n  #include \"stm32_assert.h\"\n#else\n  #define assert_param(expr) ((void)0U)\n#endif\n\n/** @addtogroup STM32F4xx_LL_Driver\n  * @{\n  */\n\n#if defined (ADC1) || defined (ADC2) || defined (ADC3)\n\n/** @addtogroup ADC_LL ADC\n  * @{\n  */\n\n/* Private types -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private constants ---------------------------------------------------------*/\n/* Private macros ------------------------------------------------------------*/\n\n/** @addtogroup ADC_LL_Private_Macros\n  * @{\n  */\n\n/* Check of parameters for configuration of ADC hierarchical scope:           */\n/* common to several ADC instances.                                           */\n#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \\\n  (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \\\n   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \\\n   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6)                             \\\n   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8)                             \\\n  )\n\n/* Check of parameters for configuration of ADC hierarchical scope:           */\n/* ADC instance.                                                              */\n#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \\\n  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \\\n   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \\\n   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \\\n   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \\\n  )\n\n#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \\\n  (   ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                            \\\n   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \\\n  )\n\n#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__)                           \\\n  (   ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE)                        \\\n   || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE)                         \\\n  )\n\n#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__)                             \\\n  (   ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE)                             \\\n   || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE)                              \\\n  )\n\n/* Check of parameters for configuration of ADC hierarchical scope:           */\n/* ADC group regular                                                          */\n#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \\\n  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)                  \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \\\n   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \\\n  )\n#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \\\n  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \\\n   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \\\n  )\n\n#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \\\n  (   ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                 \\\n   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \\\n   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \\\n  )\n\n#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__)           \\\n  (   ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV)      \\\n   || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV)       \\\n  )\n\n#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \\\n  (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \\\n   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \\\n  )\n\n#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \\\n  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \\\n   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \\\n  )\n\n/* Check of parameters for configuration of ADC hierarchical scope:           */\n/* ADC group injected                                                         */\n#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \\\n  (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO)                 \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \\\n   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \\\n  )\n\n#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \\\n  (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \\\n   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \\\n   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \\\n  )\n\n#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \\\n  (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \\\n   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \\\n  )\n\n#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \\\n  (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \\\n   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \\\n   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \\\n   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \\\n  )\n\n#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \\\n  (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \\\n   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \\\n  )\n\n#if defined(ADC_MULTIMODE_SUPPORT)\n/* Check of parameters for configuration of ADC hierarchical scope:           */\n/* multimode.                                                                 */\n#if defined(ADC3)\n#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \\\n  (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM)                \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT)                \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT)                     \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT)                     \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL)                     \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN)                     \\\n  )\n#else\n#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \\\n  (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \\\n   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \\\n  )\n#endif\n\n#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \\\n  (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1)               \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2)               \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3)               \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1)               \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2)               \\\n   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3)               \\\n  )\n\n#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \\\n  (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES)         \\\n   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES)         \\\n  )\n\n#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \\\n  (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \\\n   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \\\n   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \\\n  )\n\n#endif /* ADC_MULTIMODE_SUPPORT */\n/**\n  * @}\n  */\n\n\n/* Private function prototypes -----------------------------------------------*/\n\n/* Exported functions --------------------------------------------------------*/\n/** @addtogroup ADC_LL_Exported_Functions\n  * @{\n  */\n\n/** @addtogroup ADC_LL_EF_Init\n  * @{\n  */\n\n/**\n  * @brief  De-initialize registers of all ADC instances belonging to\n  *         the same ADC common instance to their default reset values.\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC common registers are de-initialized\n  *          - ERROR: not applicable\n  */\nErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)\n{\n  /* Check the parameters */\n  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));\n  \n\n  /* Force reset of ADC clock (core clock) */\n  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);\n  \n  /* Release reset of ADC clock (core clock) */\n  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);\n  \n  return SUCCESS;\n}\n\n/**\n  * @brief  Initialize some features of ADC common parameters\n  *         (all ADC instances belonging to the same ADC common instance)\n  *         and multimode (for devices with several ADC instances available).\n  * @note   The setting of ADC common parameters is conditioned to\n  *         ADC instances state:\n  *         All ADC instances belonging to the same ADC common instance\n  *         must be disabled.\n  * @param  ADCxy_COMMON ADC common instance\n  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )\n  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC common registers are initialized\n  *          - ERROR: ADC common registers are not initialized\n  */\nErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));\n  assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));\n  \n#if defined(ADC_MULTIMODE_SUPPORT)\n  assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));\n  if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)\n  {\n    assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));\n    assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));\n  }\n#endif /* ADC_MULTIMODE_SUPPORT */\n\n  /* Note: Hardware constraint (refer to description of functions             */\n  /*       \"LL_ADC_SetCommonXXX()\" and \"LL_ADC_SetMultiXXX()\"):               */\n  /*       On this STM32 series, setting of these features is conditioned to  */\n  /*       ADC state:                                                         */\n  /*       All ADC instances of the ADC common group must be disabled.        */\n  if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)\n  {\n    /* Configuration of ADC hierarchical scope:                               */\n    /*  - common to several ADC                                               */\n    /*    (all ADC instances belonging to the same ADC common instance)       */\n    /*    - Set ADC clock (conversion clock)                                  */\n    /*  - multimode (if several ADC instances available on the                */\n    /*    selected device)                                                    */\n    /*    - Set ADC multimode configuration                                   */\n    /*    - Set ADC multimode DMA transfer                                    */\n    /*    - Set ADC multimode: delay between 2 sampling phases                */\n#if defined(ADC_MULTIMODE_SUPPORT)\n    if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)\n    {\n      MODIFY_REG(ADCxy_COMMON->CCR,\n                   ADC_CCR_ADCPRE\n                 | ADC_CCR_MULTI\n                 | ADC_CCR_DMA\n                 | ADC_CCR_DDS\n                 | ADC_CCR_DELAY\n                ,\n                   ADC_CommonInitStruct->CommonClock\n                 | ADC_CommonInitStruct->Multimode\n                 | ADC_CommonInitStruct->MultiDMATransfer\n                 | ADC_CommonInitStruct->MultiTwoSamplingDelay\n                );\n    }\n    else\n    {\n      MODIFY_REG(ADCxy_COMMON->CCR,\n                   ADC_CCR_ADCPRE\n                 | ADC_CCR_MULTI\n                 | ADC_CCR_DMA\n                 | ADC_CCR_DDS\n                 | ADC_CCR_DELAY\n                ,\n                   ADC_CommonInitStruct->CommonClock\n                 | LL_ADC_MULTI_INDEPENDENT\n                );\n    }\n#else\n    LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);\n#endif\n  }\n  else\n  {\n    /* Initialization error: One or several ADC instances belonging to        */\n    /* the same ADC common instance are not disabled.                         */\n    status = ERROR;\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.\n  * @param  ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure\n  *                              whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)\n{\n  /* Set ADC_CommonInitStruct fields to default values */\n  /* Set fields of ADC common */\n  /* (all ADC instances belonging to the same ADC common instance) */\n  ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;\n  \n#if defined(ADC_MULTIMODE_SUPPORT)\n  /* Set fields of ADC multimode */\n  ADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;\n    ADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;\n  ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;\n#endif /* ADC_MULTIMODE_SUPPORT */\n}\n\n/**\n  * @brief  De-initialize registers of the selected ADC instance\n  *         to their default reset values.\n  * @note   To reset all ADC instances quickly (perform a hard reset),\n  *         use function @ref LL_ADC_CommonDeInit().\n  * @param  ADCx ADC instance\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC registers are de-initialized\n  *          - ERROR: ADC registers are not de-initialized\n  */\nErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)\n{\n  ErrorStatus status = SUCCESS;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(ADCx));\n  \n  /* Disable ADC instance if not already disabled.                            */\n  if(LL_ADC_IsEnabled(ADCx) == 1UL)\n  {\n    /* Set ADC group regular trigger source to SW start to ensure to not      */\n    /* have an external trigger event occurring during the conversion stop    */\n    /* ADC disable process.                                                   */\n    LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);\n    \n    /* Set ADC group injected trigger source to SW start to ensure to not     */\n    /* have an external trigger event occurring during the conversion stop    */\n    /* ADC disable process.                                                   */\n    LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);\n    \n    /* Disable the ADC instance */\n    LL_ADC_Disable(ADCx);\n  }\n  \n  /* Check whether ADC state is compliant with expected state */\n  /* (hardware requirements of bits state to reset registers below) */\n  if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL)\n  {\n    /* ========== Reset ADC registers ========== */\n    /* Reset register SR */\n    CLEAR_BIT(ADCx->SR,\n              (  LL_ADC_FLAG_STRT\n               | LL_ADC_FLAG_JSTRT\n               | LL_ADC_FLAG_EOCS\n               | LL_ADC_FLAG_OVR\n               | LL_ADC_FLAG_JEOS\n               | LL_ADC_FLAG_AWD1 )\n             );\n    \n    /* Reset register CR1 */\n    CLEAR_BIT(ADCx->CR1,\n              (  ADC_CR1_OVRIE   | ADC_CR1_RES     | ADC_CR1_AWDEN\n               | ADC_CR1_JAWDEN\n               | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN\n               | ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN\n               | ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE\n               | ADC_CR1_AWDCH                                     )\n             );\n    \n    /* Reset register CR2 */\n    CLEAR_BIT(ADCx->CR2,\n              (  ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL\n               | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL\n               | ADC_CR2_ALIGN    | ADC_CR2_EOCS\n               | ADC_CR2_DDS      | ADC_CR2_DMA\n               | ADC_CR2_CONT     | ADC_CR2_ADON                    )\n             );\n    \n    /* Reset register SMPR1 */\n    CLEAR_BIT(ADCx->SMPR1,\n              (  ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16\n               | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13\n               | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)\n             );\n    \n    /* Reset register SMPR2 */\n    CLEAR_BIT(ADCx->SMPR2,\n              (  ADC_SMPR2_SMP9\n               | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6\n               | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3\n               | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)\n             );\n    \n    /* Reset register JOFR1 */\n    CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);\n    /* Reset register JOFR2 */\n    CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);\n    /* Reset register JOFR3 */\n    CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);\n    /* Reset register JOFR4 */\n    CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);\n    \n    /* Reset register HTR */\n    SET_BIT(ADCx->HTR, ADC_HTR_HT);\n    /* Reset register LTR */\n    CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);\n    \n    /* Reset register SQR1 */\n    CLEAR_BIT(ADCx->SQR1,\n              (  ADC_SQR1_L\n               | ADC_SQR1_SQ16\n               | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)\n             );\n             \n    /* Reset register SQR2 */\n    CLEAR_BIT(ADCx->SQR2,\n              (  ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10\n               | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)\n             );\n    \n    \n    /* Reset register JSQR */\n    CLEAR_BIT(ADCx->JSQR,\n              (  ADC_JSQR_JL\n               | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3\n               | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  )\n             );\n    \n    /* Reset register DR */\n    /* bits in access mode read only, no direct reset applicable */\n    \n    /* Reset registers JDR1, JDR2, JDR3, JDR4 */\n    /* bits in access mode read only, no direct reset applicable */\n    \n    /* Reset register CCR */\n    CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);\n  }\n  \n  return status;\n}\n\n/**\n  * @brief  Initialize some features of ADC instance.\n  * @note   These parameters have an impact on ADC scope: ADC instance.\n  *         Affects both group regular and group injected (availability\n  *         of ADC group injected depends on STM32 families).\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Instance .\n  * @note   The setting of these parameters by function @ref LL_ADC_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  * @note   After using this function, some other features must be configured\n  *         using LL unitary functions.\n  *         The minimum configuration remaining to be done is:\n  *          - Set ADC group regular or group injected sequencer:\n  *            map channel on the selected sequencer rank.\n  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().\n  *          - Set ADC channel sampling time\n  *            Refer to function LL_ADC_SetChannelSamplingTime();\n  * @param  ADCx ADC instance\n  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC registers are initialized\n  *          - ERROR: ADC registers are not initialized\n  */\nErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(ADCx));\n  \n  assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));\n  assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));\n  assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));\n  \n  /* Note: Hardware constraint (refer to description of this function):       */\n  /*       ADC instance must be disabled.                                     */\n  if(LL_ADC_IsEnabled(ADCx) == 0UL)\n  {\n    /* Configuration of ADC hierarchical scope:                               */\n    /*  - ADC instance                                                        */\n    /*    - Set ADC data resolution                                           */\n    /*    - Set ADC conversion data alignment                                 */\n    MODIFY_REG(ADCx->CR1,\n                 ADC_CR1_RES\n               | ADC_CR1_SCAN\n              ,\n                 ADC_InitStruct->Resolution\n               | ADC_InitStruct->SequencersScanMode\n              );\n    \n    MODIFY_REG(ADCx->CR2,\n                 ADC_CR2_ALIGN\n              ,\n                 ADC_InitStruct->DataAlignment\n              );\n\n  }\n  else\n  {\n    /* Initialization error: ADC instance is not disabled. */\n    status = ERROR;\n  }\n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.\n  * @param  ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure\n  *                        whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)\n{\n  /* Set ADC_InitStruct fields to default values */\n  /* Set fields of ADC instance */\n  ADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;\n  ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;\n  \n  /* Enable scan mode to have a generic behavior with ADC of other            */\n  /* STM32 families, without this setting available:                          */\n  /* ADC group regular sequencer and ADC group injected sequencer depend      */\n  /* only of their own configuration.                                         */\n  ADC_InitStruct->SequencersScanMode      = LL_ADC_SEQ_SCAN_ENABLE;\n  \n}\n\n/**\n  * @brief  Initialize some features of ADC group regular.\n  * @note   These parameters have an impact on ADC scope: ADC group regular.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"REG\").\n  * @note   The setting of these parameters by function @ref LL_ADC_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  * @note   After using this function, other features must be configured\n  *         using LL unitary functions.\n  *         The minimum configuration remaining to be done is:\n  *          - Set ADC group regular or group injected sequencer:\n  *            map channel on the selected sequencer rank.\n  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().\n  *          - Set ADC channel sampling time\n  *            Refer to function LL_ADC_SetChannelSamplingTime();\n  * @param  ADCx ADC instance\n  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC registers are initialized\n  *          - ERROR: ADC registers are not initialized\n  */\nErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(ADCx));\n  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));\n  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));\n  if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)\n  {\n    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));\n  }\n  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));\n  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));\n  \n  /* ADC group regular continuous mode and discontinuous mode                 */\n  /* can not be enabled simultenaeously                                       */\n  assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)\n               || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));\n  \n  /* Note: Hardware constraint (refer to description of this function):       */\n  /*       ADC instance must be disabled.                                     */\n  if(LL_ADC_IsEnabled(ADCx) == 0UL)\n  {\n    /* Configuration of ADC hierarchical scope:                               */\n    /*  - ADC group regular                                                   */\n    /*    - Set ADC group regular trigger source                              */\n    /*    - Set ADC group regular sequencer length                            */\n    /*    - Set ADC group regular sequencer discontinuous mode                */\n    /*    - Set ADC group regular continuous mode                             */\n    /*    - Set ADC group regular conversion data transfer: no transfer or    */\n    /*      transfer by DMA, and DMA requests mode                            */\n    /* Note: On this STM32 series, ADC trigger edge is set when starting      */\n    /*       ADC conversion.                                                  */\n    /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().      */\n    if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)\n    {\n      MODIFY_REG(ADCx->CR1,\n                   ADC_CR1_DISCEN\n                 | ADC_CR1_DISCNUM\n                ,\n                   ADC_REG_InitStruct->SequencerDiscont\n                );\n    }\n    else\n    {\n      MODIFY_REG(ADCx->CR1,\n                   ADC_CR1_DISCEN\n                 | ADC_CR1_DISCNUM\n                ,\n                   LL_ADC_REG_SEQ_DISCONT_DISABLE\n                );\n    }\n    \n    MODIFY_REG(ADCx->CR2,\n                 ADC_CR2_EXTSEL\n               | ADC_CR2_EXTEN\n               | ADC_CR2_CONT\n               | ADC_CR2_DMA\n               | ADC_CR2_DDS\n              ,\n                (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)\n               | ADC_REG_InitStruct->ContinuousMode\n               | ADC_REG_InitStruct->DMATransfer\n              );\n\n    /* Set ADC group regular sequencer length and scan direction */\n    /* Note: Hardware constraint (refer to description of this function):     */\n    /* Note: If ADC instance feature scan mode is disabled                    */\n    /*       (refer to  ADC instance initialization structure                 */\n    /*       parameter @ref SequencersScanMode                                */\n    /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */\n    /*       this parameter is discarded.                                     */\n    LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);\n  }\n  else\n  {\n    /* Initialization error: ADC instance is not disabled. */\n    status = ERROR;\n  }\n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.\n  * @param  ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure\n  *                            whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)\n{\n  /* Set ADC_REG_InitStruct fields to default values */\n  /* Set fields of ADC group regular */\n  /* Note: On this STM32 series, ADC trigger edge is set when starting        */\n  /*       ADC conversion.                                                    */\n  /*       Refer to function @ref LL_ADC_REG_StartConversionExtTrig().        */\n  ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;\n  ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;\n  ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;\n  ADC_REG_InitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;\n  ADC_REG_InitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;\n}\n\n/**\n  * @brief  Initialize some features of ADC group injected.\n  * @note   These parameters have an impact on ADC scope: ADC group injected.\n  *         Refer to corresponding unitary functions into\n  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular\n  *         (functions with prefix \"INJ\").\n  * @note   The setting of these parameters by function @ref LL_ADC_Init()\n  *         is conditioned to ADC state:\n  *         ADC instance must be disabled.\n  *         This condition is applied to all ADC features, for efficiency\n  *         and compatibility over all STM32 families. However, the different\n  *         features can be set under different ADC state conditions\n  *         (setting possible with ADC enabled without conversion on going,\n  *         ADC enabled with conversion on going, ...)\n  *         Each feature can be updated afterwards with a unitary function\n  *         and potentially with ADC in a different state than disabled,\n  *         refer to description of each function for setting\n  *         conditioned to ADC state.\n  * @note   After using this function, other features must be configured\n  *         using LL unitary functions.\n  *         The minimum configuration remaining to be done is:\n  *          - Set ADC group injected sequencer:\n  *            map channel on the selected sequencer rank.\n  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().\n  *          - Set ADC channel sampling time\n  *            Refer to function LL_ADC_SetChannelSamplingTime();\n  * @param  ADCx ADC instance\n  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure\n  * @retval An ErrorStatus enumeration value:\n  *          - SUCCESS: ADC registers are initialized\n  *          - ERROR: ADC registers are not initialized\n  */\nErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)\n{\n  ErrorStatus status = SUCCESS;\n  \n  /* Check the parameters */\n  assert_param(IS_ADC_ALL_INSTANCE(ADCx));\n  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));\n  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));\n  if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)\n  {\n    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));\n  }\n  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));\n  \n  /* Note: Hardware constraint (refer to description of this function):       */\n  /*       ADC instance must be disabled.                                     */\n  if(LL_ADC_IsEnabled(ADCx) == 0UL)\n  {\n    /* Configuration of ADC hierarchical scope:                               */\n    /*  - ADC group injected                                                  */\n    /*    - Set ADC group injected trigger source                             */\n    /*    - Set ADC group injected sequencer length                           */\n    /*    - Set ADC group injected sequencer discontinuous mode               */\n    /*    - Set ADC group injected conversion trigger: independent or         */\n    /*      from ADC group regular                                            */\n    /* Note: On this STM32 series, ADC trigger edge is set when starting      */\n    /*       ADC conversion.                                                  */\n    /*       Refer to function @ref LL_ADC_INJ_StartConversionExtTrig().      */\n    if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)\n    {\n      MODIFY_REG(ADCx->CR1,\n                   ADC_CR1_JDISCEN\n                 | ADC_CR1_JAUTO\n                ,\n                   ADC_INJ_InitStruct->SequencerDiscont\n                 | ADC_INJ_InitStruct->TrigAuto\n                );\n    }\n    else\n    {\n      MODIFY_REG(ADCx->CR1,\n                   ADC_CR1_JDISCEN\n                 | ADC_CR1_JAUTO\n                ,\n                   LL_ADC_REG_SEQ_DISCONT_DISABLE\n                 | ADC_INJ_InitStruct->TrigAuto\n                );\n    }\n    \n    MODIFY_REG(ADCx->CR2,\n                 ADC_CR2_JEXTSEL\n               | ADC_CR2_JEXTEN\n              ,\n                (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)\n              );\n    \n    /* Note: Hardware constraint (refer to description of this function):     */\n    /* Note: If ADC instance feature scan mode is disabled                    */\n    /*       (refer to  ADC instance initialization structure                 */\n    /*       parameter @ref SequencersScanMode                                */\n    /*       or function @ref LL_ADC_SetSequencersScanMode() ),               */\n    /*       this parameter is discarded.                                     */\n    LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);\n  }\n  else\n  {\n    /* Initialization error: ADC instance is not disabled. */\n    status = ERROR;\n  }\n  return status;\n}\n\n/**\n  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.\n  * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure\n  *                            whose fields will be set to default values.\n  * @retval None\n  */\nvoid LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)\n{\n  /* Set ADC_INJ_InitStruct fields to default values */\n  /* Set fields of ADC group injected */\n  ADC_INJ_InitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;\n  ADC_INJ_InitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;\n  ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;\n  ADC_INJ_InitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#endif /* ADC1 || ADC2 || ADC3 */\n\n/**\n  * @}\n  */\n\n#endif /* USE_FULL_LL_DRIVER */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_usb.c",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f4xx_ll_usb.c\n  * @author  MCD Application Team\n  * @brief   USB Low Layer HAL module driver.\n  *\n  *          This file provides firmware functions to manage the following\n  *          functionalities of the USB Peripheral Controller:\n  *           + Initialization/de-initialization functions\n  *           + I/O operation functions\n  *           + Peripheral Control functions\n  *           + Peripheral State functions\n  *\n  @verbatim\n  ==============================================================================\n                    ##### How to use this driver #####\n  ==============================================================================\n    [..]\n      (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.\n\n      (#) Call USB_CoreInit() API to initialize the USB Core peripheral.\n\n      (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.\n\n  @endverbatim\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx_hal.h\"\n\n/** @addtogroup STM32F4xx_LL_USB_DRIVER\n  * @{\n  */\n\n#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n/* Private variables ---------------------------------------------------------*/\n/* Private function prototypes -----------------------------------------------*/\n/* Private functions ---------------------------------------------------------*/\n#if defined (USB_OTG_FS) || defined (USB_OTG_HS)\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);\n\n/* Exported functions --------------------------------------------------------*/\n/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions\n  * @{\n  */\n\n/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions\n  *  @brief    Initialization and Configuration functions\n  *\n@verbatim\n ===============================================================================\n                      ##### Initialization/de-initialization functions #####\n ===============================================================================\n\n@endverbatim\n  * @{\n  */\n\n/**\n  * @brief  Initializes the USB Core\n  * @param  USBx USB Instance\n  * @param  cfg pointer to a USB_OTG_CfgTypeDef structure that contains\n  *         the configuration information for the specified USBx peripheral.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\n{\n  HAL_StatusTypeDef ret;\n\n  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\n  {\n    USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\n\n    /* Init The ULPI Interface */\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);\n\n    /* Select vbus source */\n    USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);\n    if (cfg.use_external_vbus == 1U)\n    {\n      USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;\n    }\n    /* Reset after a PHY select  */\n    ret = USB_CoreReset(USBx);\n  }\n  else /* FS interface (embedded Phy) */\n  {\n    /* Select FS Embedded PHY */\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;\n\n    /* Reset after a PHY select */\n    ret = USB_CoreReset(USBx);\n\n    if (cfg.battery_charging_enable == 0U)\n    {\n      /* Activate the USB Transceiver */\n      USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;\n    }\n    else\n    {\n      /* Deactivate the USB Transceiver */\n      USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);\n    }\n  }\n\n  if (cfg.dma_enable == 1U)\n  {\n    USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;\n    USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;\n  }\n\n  return ret;\n}\n\n\n/**\n  * @brief  Set the USB turnaround time\n  * @param  USBx USB Instance\n  * @param  hclk: AHB clock frequency\n  * @retval USB turnaround time In PHY Clocks number\n  */\nHAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx,\n                                        uint32_t hclk, uint8_t speed)\n{\n  uint32_t UsbTrd;\n\n  /* The USBTRD is configured according to the tables below, depending on AHB frequency\n  used by application. In the low AHB frequency range it is used to stretch enough the USB response\n  time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access\n  latency to the Data FIFO */\n  if (speed == USBD_FS_SPEED)\n  {\n    if ((hclk >= 14200000U) && (hclk < 15000000U))\n    {\n      /* hclk Clock Range between 14.2-15 MHz */\n      UsbTrd = 0xFU;\n    }\n    else if ((hclk >= 15000000U) && (hclk < 16000000U))\n    {\n      /* hclk Clock Range between 15-16 MHz */\n      UsbTrd = 0xEU;\n    }\n    else if ((hclk >= 16000000U) && (hclk < 17200000U))\n    {\n      /* hclk Clock Range between 16-17.2 MHz */\n      UsbTrd = 0xDU;\n    }\n    else if ((hclk >= 17200000U) && (hclk < 18500000U))\n    {\n      /* hclk Clock Range between 17.2-18.5 MHz */\n      UsbTrd = 0xCU;\n    }\n    else if ((hclk >= 18500000U) && (hclk < 20000000U))\n    {\n      /* hclk Clock Range between 18.5-20 MHz */\n      UsbTrd = 0xBU;\n    }\n    else if ((hclk >= 20000000U) && (hclk < 21800000U))\n    {\n      /* hclk Clock Range between 20-21.8 MHz */\n      UsbTrd = 0xAU;\n    }\n    else if ((hclk >= 21800000U) && (hclk < 24000000U))\n    {\n      /* hclk Clock Range between 21.8-24 MHz */\n      UsbTrd = 0x9U;\n    }\n    else if ((hclk >= 24000000U) && (hclk < 27700000U))\n    {\n      /* hclk Clock Range between 24-27.7 MHz */\n      UsbTrd = 0x8U;\n    }\n    else if ((hclk >= 27700000U) && (hclk < 32000000U))\n    {\n      /* hclk Clock Range between 27.7-32 MHz */\n      UsbTrd = 0x7U;\n    }\n    else /* if(hclk >= 32000000) */\n    {\n      /* hclk Clock Range between 32-200 MHz */\n      UsbTrd = 0x6U;\n    }\n  }\n  else if (speed == USBD_HS_SPEED)\n  {\n    UsbTrd = USBD_HS_TRDT_VALUE;\n  }\n  else\n  {\n    UsbTrd = USBD_DEFAULT_TRDT_VALUE;\n  }\n\n  USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;\n  USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_EnableGlobalInt\n  *         Enables the controller's Global Int in the AHB Config reg\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\n{\n  USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DisableGlobalInt\n  *         Disable the controller's Global Int in the AHB Config reg\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)\n{\n  USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_SetCurrentMode Set functional mode\n  * @param  USBx  Selected device\n  * @param  mode  current core mode\n  *          This parameter can be one of these values:\n  *            @arg USB_DEVICE_MODE Peripheral mode\n  *            @arg USB_HOST_MODE Host mode\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode)\n{\n  USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);\n\n  if (mode == USB_HOST_MODE)\n  {\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;\n  }\n  else if (mode == USB_DEVICE_MODE)\n  {\n    USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;\n  }\n  else\n  {\n    return HAL_ERROR;\n  }\n  HAL_Delay(50U);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DevInit Initializes the USB_OTG controller registers\n  *         for device mode\n  * @param  USBx  Selected device\n  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\n  *         the configuration information for the specified USBx peripheral.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\n{\n  HAL_StatusTypeDef ret = HAL_OK;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t i;\n\n  for (i = 0U; i < 15U; i++)\n  {\n    USBx->DIEPTXF[i] = 0U;\n  }\n\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  /* VBUS Sensing setup */\n  if (cfg.vbus_sensing_enable == 0U)\n  {\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\n\n    /* Deactivate VBUS Sensing B */\n    USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;\n\n    /* B-peripheral session valid override enable */\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;\n    USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;\n  }\n  else\n  {\n    /* Enable HW VBUS sensing */\n    USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;\n  }\n#else\n  /* VBUS Sensing setup */\n  if (cfg.vbus_sensing_enable == 0U)\n  {\n    /*\n     * Disable HW VBUS sensing. VBUS is internally considered to be always\n     * at VBUS-Valid level (5V).\n     */\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\n    USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;\n    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;\n    USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;\n  }\n  else\n  {\n    /* Enable HW VBUS sensing */\n    USBx->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS;\n    USBx->GCCFG |= USB_OTG_GCCFG_VBUSBSEN;\n  }\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n\n  /* Restart the Phy Clock */\n  USBx_PCGCCTL = 0U;\n\n  /* Device mode configuration */\n  USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;\n\n  if (cfg.phy_itface == USB_OTG_ULPI_PHY)\n  {\n    if (cfg.speed == USBD_HS_SPEED)\n    {\n      /* Set Core speed to High speed mode */\n      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH);\n    }\n    else\n    {\n      /* Set Core speed to Full speed mode */\n      (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL);\n    }\n  }\n  else\n  {\n    /* Set Core speed to Full speed mode */\n    (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL);\n  }\n\n  /* Flush the FIFOs */\n  if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */\n  {\n    ret = HAL_ERROR;\n  }\n\n  if (USB_FlushRxFifo(USBx) != HAL_OK)\n  {\n    ret = HAL_ERROR;\n  }\n\n  /* Clear all pending Device Interrupts */\n  USBx_DEVICE->DIEPMSK = 0U;\n  USBx_DEVICE->DOEPMSK = 0U;\n  USBx_DEVICE->DAINTMSK = 0U;\n\n  for (i = 0U; i < cfg.dev_endpoints; i++)\n  {\n    if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\n    {\n      if (i == 0U)\n      {\n        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK;\n      }\n      else\n      {\n        USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK;\n      }\n    }\n    else\n    {\n      USBx_INEP(i)->DIEPCTL = 0U;\n    }\n\n    USBx_INEP(i)->DIEPTSIZ = 0U;\n    USBx_INEP(i)->DIEPINT  = 0xFB7FU;\n  }\n\n  for (i = 0U; i < cfg.dev_endpoints; i++)\n  {\n    if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\n    {\n      if (i == 0U)\n      {\n        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK;\n      }\n      else\n      {\n        USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK;\n      }\n    }\n    else\n    {\n      USBx_OUTEP(i)->DOEPCTL = 0U;\n    }\n\n    USBx_OUTEP(i)->DOEPTSIZ = 0U;\n    USBx_OUTEP(i)->DOEPINT  = 0xFB7FU;\n  }\n\n  USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);\n\n  /* Disable all interrupts. */\n  USBx->GINTMSK = 0U;\n\n  /* Clear any pending interrupts */\n  USBx->GINTSTS = 0xBFFFFFFFU;\n\n  /* Enable the common interrupts */\n  if (cfg.dma_enable == 0U)\n  {\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\n  }\n\n  /* Enable interrupts matching to the Device mode ONLY */\n  USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\n                   USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\n                   USB_OTG_GINTMSK_OEPINT   | USB_OTG_GINTMSK_IISOIXFRM |\n                   USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM;\n\n  if (cfg.Sof_enable != 0U)\n  {\n    USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;\n  }\n\n  if (cfg.vbus_sensing_enable == 1U)\n  {\n    USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);\n  }\n\n  return ret;\n}\n\n/**\n  * @brief  USB_OTG_FlushTxFifo : Flush a Tx FIFO\n  * @param  USBx  Selected device\n  * @param  num  FIFO number\n  *         This parameter can be a value from 1 to 15\n            15 means Flush all Tx FIFOs\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num)\n{\n  uint32_t count = 0U;\n\n  USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6));\n\n  do\n  {\n    if (++count > 200000U)\n    {\n      return HAL_TIMEOUT;\n    }\n  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_FlushRxFifo : Flush Rx FIFO\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t count = 0;\n\n  USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;\n\n  do\n  {\n    if (++count > 200000U)\n    {\n      return HAL_TIMEOUT;\n    }\n  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_SetDevSpeed  Initializes the DevSpd field of DCFG register\n  *         depending the PHY type and the enumeration speed of the device.\n  * @param  USBx  Selected device\n  * @param  speed  device speed\n  *          This parameter can be one of these values:\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\n  *            @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\n  * @retval  Hal status\n  */\nHAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  USBx_DEVICE->DCFG |= speed;\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_GetDevSpeed  Return the Dev Speed\n  * @param  USBx  Selected device\n  * @retval speed  device speed\n  *          This parameter can be one of these values:\n  *            @arg USBD_HS_SPEED: High speed mode\n  *            @arg USBD_FS_SPEED: Full speed mode\n  */\nuint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint8_t speed;\n  uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD;\n\n  if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)\n  {\n    speed = USBD_HS_SPEED;\n  }\n  else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) ||\n           (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ))\n  {\n    speed = USBD_FS_SPEED;\n  }\n  else\n  {\n    speed = 0xFU;\n  }\n\n  return speed;\n}\n\n/**\n  * @brief  Activate and configure an endpoint\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  if (ep->is_in == 1U)\n  {\n    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\n\n    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U)\n    {\n      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\n                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\n                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\n                                   USB_OTG_DIEPCTL_USBAEP;\n    }\n  }\n  else\n  {\n    USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\n\n    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\n    {\n      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\n                                    ((uint32_t)ep->type << 18) |\n                                    USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\n                                    USB_OTG_DOEPCTL_USBAEP;\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Activate and configure a dedicated endpoint\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  /* Read DEPCTLn register */\n  if (ep->is_in == 1U)\n  {\n    if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U)\n    {\n      USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) |\n                                   ((uint32_t)ep->type << 18) | (epnum << 22) |\n                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\n                                   USB_OTG_DIEPCTL_USBAEP;\n    }\n\n    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK));\n  }\n  else\n  {\n    if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U)\n    {\n      USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) |\n                                    ((uint32_t)ep->type << 18) | (epnum << 22) |\n                                    USB_OTG_DOEPCTL_USBAEP;\n    }\n\n    USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  De-activate and de-initialize an endpoint\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  /* Read DEPCTLn register */\n  if (ep->is_in == 1U)\n  {\n    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\n    {\n      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK;\n      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS;\n    }\n\n    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\n    USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP |\n                                   USB_OTG_DIEPCTL_MPSIZ |\n                                   USB_OTG_DIEPCTL_TXFNUM |\n                                   USB_OTG_DIEPCTL_SD0PID_SEVNFRM |\n                                   USB_OTG_DIEPCTL_EPTYP);\n  }\n  else\n  {\n    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\n    {\n      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK;\n      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS;\n    }\n\n    USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\n    USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP |\n                                    USB_OTG_DOEPCTL_MPSIZ |\n                                    USB_OTG_DOEPCTL_SD0PID_SEVNFRM |\n                                    USB_OTG_DOEPCTL_EPTYP);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  De-activate and de-initialize a dedicated endpoint\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  /* Read DEPCTLn register */\n  if (ep->is_in == 1U)\n  {\n    if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)\n    {\n      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_SNAK;\n      USBx_INEP(epnum)->DIEPCTL  |= USB_OTG_DIEPCTL_EPDIS;\n    }\n\n    USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)));\n  }\n  else\n  {\n    if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\n    {\n      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_SNAK;\n      USBx_OUTEP(epnum)->DOEPCTL  |= USB_OTG_DOEPCTL_EPDIS;\n    }\n\n    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;\n    USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16));\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_EPStartXfer : setup and starts a transfer over an EP\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @param  dma USB dma enabled or disabled\n  *          This parameter can be one of these values:\n  *           0 : DMA feature not used\n  *           1 : DMA feature used\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n  uint16_t pktcnt;\n\n  /* IN endpoint */\n  if (ep->is_in == 1U)\n  {\n    /* Zero Length Packet? */\n    if (ep->xfer_len == 0U)\n    {\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\n    }\n    else\n    {\n      /* Program the transfer size and packet count\n      * as follows: xfersize = N * maxpacket +\n      * short_packet pktcnt = N + (short_packet\n      * exist ? 1 : 0)\n      */\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19));\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\n\n      if (ep->type == EP_TYPE_ISOC)\n      {\n        USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);\n        USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));\n      }\n    }\n\n    if (dma == 1U)\n    {\n      if ((uint32_t)ep->dma_addr != 0U)\n      {\n        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);\n      }\n\n      if (ep->type == EP_TYPE_ISOC)\n      {\n        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\n        {\n          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\n        }\n        else\n        {\n          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\n        }\n      }\n\n      /* EP enable, IN data in FIFO */\n      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\n    }\n    else\n    {\n      /* EP enable, IN data in FIFO */\n      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\n\n      if (ep->type != EP_TYPE_ISOC)\n      {\n        /* Enable the Tx FIFO Empty Interrupt for this EP */\n        if (ep->xfer_len > 0U)\n        {\n          USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\n        }\n      }\n      else\n      {\n        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\n        {\n          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;\n        }\n        else\n        {\n          USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;\n        }\n\n        (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma);\n      }\n    }\n  }\n  else /* OUT endpoint */\n  {\n    /* Program the transfer size and packet count as follows:\n    * pktcnt = N\n    * xfersize = N * maxpacket\n    */\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\n\n    if (ep->xfer_len == 0U)\n    {\n      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);\n      USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\n    }\n    else\n    {\n      pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket);\n      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19);\n      USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt);\n    }\n\n    if (dma == 1U)\n    {\n      if ((uint32_t)ep->xfer_buff != 0U)\n      {\n        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);\n      }\n    }\n\n    if (ep->type == EP_TYPE_ISOC)\n    {\n      if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U)\n      {\n        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;\n      }\n      else\n      {\n        USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;\n      }\n    }\n    /* EP enable */\n    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_EP0StartXfer : setup and starts a transfer over the EP  0\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @param  dma USB dma enabled or disabled\n  *          This parameter can be one of these values:\n  *           0 : DMA feature not used\n  *           1 : DMA feature used\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  /* IN endpoint */\n  if (ep->is_in == 1U)\n  {\n    /* Zero Length Packet? */\n    if (ep->xfer_len == 0U)\n    {\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\n    }\n    else\n    {\n      /* Program the transfer size and packet count\n      * as follows: xfersize = N * maxpacket +\n      * short_packet pktcnt = N + (short_packet\n      * exist ? 1 : 0)\n      */\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);\n      USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);\n\n      if (ep->xfer_len > ep->maxpacket)\n      {\n        ep->xfer_len = ep->maxpacket;\n      }\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));\n      USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);\n    }\n\n    if (dma == 1U)\n    {\n      if ((uint32_t)ep->dma_addr != 0U)\n      {\n        USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr);\n      }\n\n      /* EP enable, IN data in FIFO */\n      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\n    }\n    else\n    {\n      /* EP enable, IN data in FIFO */\n      USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);\n\n      /* Enable the Tx FIFO Empty Interrupt for this EP */\n      if (ep->xfer_len > 0U)\n      {\n        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK);\n      }\n    }\n  }\n  else /* OUT endpoint */\n  {\n    /* Program the transfer size and packet count as follows:\n    * pktcnt = N\n    * xfersize = N * maxpacket\n    */\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);\n    USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);\n\n    if (ep->xfer_len > 0U)\n    {\n      ep->xfer_len = ep->maxpacket;\n    }\n\n    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\n    USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));\n\n    if (dma == 1U)\n    {\n      if ((uint32_t)ep->xfer_buff != 0U)\n      {\n        USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff);\n      }\n    }\n\n    /* EP enable */\n    USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_WritePacket : Writes a packet into the Tx FIFO associated\n  *         with the EP/channel\n  * @param  USBx  Selected device\n  * @param  src   pointer to source buffer\n  * @param  ch_ep_num  endpoint or host channel number\n  * @param  len  Number of bytes to write\n  * @param  dma USB dma enabled or disabled\n  *          This parameter can be one of these values:\n  *           0 : DMA feature not used\n  *           1 : DMA feature used\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src,\n                                  uint8_t ch_ep_num, uint16_t len, uint8_t dma)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t *pSrc = (uint32_t *)src;\n  uint32_t count32b, i;\n\n  if (dma == 0U)\n  {\n    count32b = ((uint32_t)len + 3U) / 4U;\n    for (i = 0U; i < count32b; i++)\n    {\n      USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc);\n      pSrc++;\n    }\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_ReadPacket : read a packet from the RX FIFO\n  * @param  USBx  Selected device\n  * @param  dest  source pointer\n  * @param  len  Number of bytes to read\n  * @retval pointer to destination buffer\n  */\nvoid *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t *pDest = (uint32_t *)dest;\n  uint32_t i;\n  uint32_t count32b = ((uint32_t)len + 3U) / 4U;\n\n  for (i = 0U; i < count32b; i++)\n  {\n    __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U));\n    pDest++;\n  }\n\n  return ((void *)pDest);\n}\n\n/**\n  * @brief  USB_EPSetStall : set a stall condition over an EP\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  if (ep->is_in == 1U)\n  {\n    if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U))\n    {\n      USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);\n    }\n    USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;\n  }\n  else\n  {\n    if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U))\n    {\n      USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);\n    }\n    USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_EPClearStall : Clear a stall condition over an EP\n  * @param  USBx  Selected device\n  * @param  ep pointer to endpoint structure\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t epnum = (uint32_t)ep->num;\n\n  if (ep->is_in == 1U)\n  {\n    USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;\n    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\n    {\n      USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */\n    }\n  }\n  else\n  {\n    USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;\n    if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK))\n    {\n      USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */\n    }\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_StopDevice : Stop the usb device mode\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)\n{\n  HAL_StatusTypeDef ret;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t i;\n\n  /* Clear Pending interrupt */\n  for (i = 0U; i < 15U; i++)\n  {\n    USBx_INEP(i)->DIEPINT = 0xFB7FU;\n    USBx_OUTEP(i)->DOEPINT = 0xFB7FU;\n  }\n\n  /* Clear interrupt masks */\n  USBx_DEVICE->DIEPMSK  = 0U;\n  USBx_DEVICE->DOEPMSK  = 0U;\n  USBx_DEVICE->DAINTMSK = 0U;\n\n  /* Flush the FIFO */\n  ret = USB_FlushRxFifo(USBx);\n  if (ret != HAL_OK)\n  {\n    return ret;\n  }\n\n  ret = USB_FlushTxFifo(USBx,  0x10U);\n  if (ret != HAL_OK)\n  {\n    return ret;\n  }\n\n  return ret;\n}\n\n/**\n  * @brief  USB_SetDevAddress : Stop the usb device mode\n  * @param  USBx  Selected device\n  * @param  address  new device address to be assigned\n  *          This parameter can be a value from 0 to 255\n  * @retval HAL status\n  */\nHAL_StatusTypeDef  USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD);\n  USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DevConnect : Connect the USB device by enabling Rpu\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef  USB_DevConnect(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  /* In case phy is stopped, ensure to ungate and restore the phy CLK */\n  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);\n\n  USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DevDisconnect : Disconnect the USB device by disabling Rpu\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef  USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  /* In case phy is stopped, ensure to ungate and restore the phy CLK */\n  USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK);\n\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_ReadInterrupts: return the global USB interrupt status\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nuint32_t  USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t tmpreg;\n\n  tmpreg = USBx->GINTSTS;\n  tmpreg &= USBx->GINTMSK;\n\n  return tmpreg;\n}\n\n/**\n  * @brief  USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nuint32_t USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t tmpreg;\n\n  tmpreg  = USBx_DEVICE->DAINT;\n  tmpreg &= USBx_DEVICE->DAINTMSK;\n\n  return ((tmpreg & 0xffff0000U) >> 16);\n}\n\n/**\n  * @brief  USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nuint32_t USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t tmpreg;\n\n  tmpreg  = USBx_DEVICE->DAINT;\n  tmpreg &= USBx_DEVICE->DAINTMSK;\n\n  return ((tmpreg & 0xFFFFU));\n}\n\n/**\n  * @brief  Returns Device OUT EP Interrupt register\n  * @param  USBx  Selected device\n  * @param  epnum  endpoint number\n  *          This parameter can be a value from 0 to 15\n  * @retval Device OUT EP Interrupt register\n  */\nuint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t tmpreg;\n\n  tmpreg  = USBx_OUTEP((uint32_t)epnum)->DOEPINT;\n  tmpreg &= USBx_DEVICE->DOEPMSK;\n\n  return tmpreg;\n}\n\n/**\n  * @brief  Returns Device IN EP Interrupt register\n  * @param  USBx  Selected device\n  * @param  epnum  endpoint number\n  *          This parameter can be a value from 0 to 15\n  * @retval Device IN EP Interrupt register\n  */\nuint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t tmpreg, msk, emp;\n\n  msk = USBx_DEVICE->DIEPMSK;\n  emp = USBx_DEVICE->DIEPEMPMSK;\n  msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7;\n  tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk;\n\n  return tmpreg;\n}\n\n/**\n  * @brief  USB_ClearInterrupts: clear a USB interrupt\n  * @param  USBx  Selected device\n  * @param  interrupt  flag\n  * @retval None\n  */\nvoid  USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)\n{\n  USBx->GINTSTS |= interrupt;\n}\n\n/**\n  * @brief  Returns USB core mode\n  * @param  USBx  Selected device\n  * @retval return core mode : Host or Device\n  *          This parameter can be one of these values:\n  *           0 : Host\n  *           1 : Device\n  */\nuint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)\n{\n  return ((USBx->GINTSTS) & 0x1U);\n}\n\n/**\n  * @brief  Activate EP0 for Setup transactions\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef  USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  /* Set the MPS of the IN EP0 to 64 bytes */\n  USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;\n\n  USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Prepare the EP0 to start the first control setup\n  * @param  USBx  Selected device\n  * @param  dma USB dma enabled or disabled\n  *          This parameter can be one of these values:\n  *           0 : DMA feature not used\n  *           1 : DMA feature used\n  * @param  psetup  pointer to setup packet\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U);\n\n  if (gSNPSiD > USB_OTG_CORE_ID_300A)\n  {\n    if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)\n    {\n      return HAL_OK;\n    }\n  }\n\n  USBx_OUTEP(0U)->DOEPTSIZ = 0U;\n  USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));\n  USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);\n  USBx_OUTEP(0U)->DOEPTSIZ |=  USB_OTG_DOEPTSIZ_STUPCNT;\n\n  if (dma == 1U)\n  {\n    USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup;\n    /* EP enable */\n    USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Reset the USB Core (needed after USB clock settings change)\n  * @param  USBx  Selected device\n  * @retval HAL status\n  */\nstatic HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t count = 0U;\n\n  /* Wait for AHB master IDLE state. */\n  do\n  {\n    if (++count > 200000U)\n    {\n      return HAL_TIMEOUT;\n    }\n  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);\n\n  /* Core Soft Reset */\n  count = 0U;\n  USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;\n\n  do\n  {\n    if (++count > 200000U)\n    {\n      return HAL_TIMEOUT;\n    }\n  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_HostInit : Initializes the USB OTG controller registers\n  *         for Host mode\n  * @param  USBx  Selected device\n  * @param  cfg   pointer to a USB_OTG_CfgTypeDef structure that contains\n  *         the configuration information for the specified USBx peripheral.\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t i;\n\n  /* Restart the Phy Clock */\n  USBx_PCGCCTL = 0U;\n\n#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  /* Disable HW VBUS sensing */\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN);\n#else\n  /*\n  * Disable HW VBUS sensing. VBUS is internally considered to be always\n  * at VBUS-Valid level (5V).\n  */\n  USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;\n  USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;\n  USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;\n#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)\n  /* Disable Battery chargin detector */\n  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);\n#endif /* defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) */\n\n  if ((USBx->CID & (0x1U << 8)) != 0U)\n  {\n    if (cfg.speed == USBH_FSLS_SPEED)\n    {\n      /* Force Device Enumeration to FS/LS mode only */\n      USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;\n    }\n    else\n    {\n      /* Set default Max speed support */\n      USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\n    }\n  }\n  else\n  {\n    /* Set default Max speed support */\n    USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);\n  }\n\n  /* Make sure the FIFOs are flushed. */\n  (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */\n  (void)USB_FlushRxFifo(USBx);\n\n  /* Clear all pending HC Interrupts */\n  for (i = 0U; i < cfg.Host_channels; i++)\n  {\n    USBx_HC(i)->HCINT = 0xFFFFFFFFU;\n    USBx_HC(i)->HCINTMSK = 0U;\n  }\n\n  /* Enable VBUS driving */\n  (void)USB_DriveVbus(USBx, 1U);\n\n  HAL_Delay(200U);\n\n  /* Disable all interrupts. */\n  USBx->GINTMSK = 0U;\n\n  /* Clear any pending interrupts */\n  USBx->GINTSTS = 0xFFFFFFFFU;\n\n  if ((USBx->CID & (0x1U << 8)) != 0U)\n  {\n    /* set Rx FIFO size */\n    USBx->GRXFSIZ  = 0x200U;\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U);\n    USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U);\n  }\n  else\n  {\n    /* set Rx FIFO size */\n    USBx->GRXFSIZ  = 0x80U;\n    USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U);\n    USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U);\n  }\n\n  /* Enable the common interrupts */\n  if (cfg.dma_enable == 0U)\n  {\n    USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;\n  }\n\n  /* Enable interrupts matching to the Host mode ONLY */\n  USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM            | USB_OTG_GINTMSK_HCIM | \\\n                    USB_OTG_GINTMSK_SOFM             | USB_OTG_GINTSTS_DISCINT | \\\n                    USB_OTG_GINTMSK_PXFRM_IISOOXFRM  | USB_OTG_GINTMSK_WUIM);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the\n  *         HCFG register on the PHY type and set the right frame interval\n  * @param  USBx  Selected device\n  * @param  freq  clock frequency\n  *          This parameter can be one of these values:\n  *           HCFG_48_MHZ : Full Speed 48 MHz Clock\n  *           HCFG_6_MHZ : Low Speed 6 MHz Clock\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);\n  USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS;\n\n  if (freq == HCFG_48_MHZ)\n  {\n    USBx_HOST->HFIR = 48000U;\n  }\n  else if (freq == HCFG_6_MHZ)\n  {\n    USBx_HOST->HFIR = 6000U;\n  }\n  else\n  {\n    /* ... */\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_OTG_ResetPort : Reset Host Port\n  * @param  USBx  Selected device\n  * @retval HAL status\n  * @note (1)The application must wait at least 10 ms\n  *   before clearing the reset bit.\n  */\nHAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  __IO uint32_t hprt0 = 0U;\n\n  hprt0 = USBx_HPRT0;\n\n  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\n             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\n\n  USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);\n  HAL_Delay(100U);                                 /* See Note #1 */\n  USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);\n  HAL_Delay(10U);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DriveVbus : activate or de-activate vbus\n  * @param  state  VBUS state\n  *          This parameter can be one of these values:\n  *           0 : Deactivate VBUS\n  *           1 : Activate VBUS\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  __IO uint32_t hprt0 = 0U;\n\n  hprt0 = USBx_HPRT0;\n\n  hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\n             USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);\n\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U))\n  {\n    USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);\n  }\n  if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U))\n  {\n    USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);\n  }\n  return HAL_OK;\n}\n\n/**\n  * @brief  Return Host Core speed\n  * @param  USBx  Selected device\n  * @retval speed : Host speed\n  *          This parameter can be one of these values:\n  *            @arg HCD_SPEED_HIGH: High speed mode\n  *            @arg HCD_SPEED_FULL: Full speed mode\n  *            @arg HCD_SPEED_LOW: Low speed mode\n  */\nuint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  __IO uint32_t hprt0 = 0U;\n\n  hprt0 = USBx_HPRT0;\n  return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);\n}\n\n/**\n  * @brief  Return Host Current Frame number\n  * @param  USBx  Selected device\n  * @retval current frame number\n  */\nuint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);\n}\n\n/**\n  * @brief  Initialize a host channel\n  * @param  USBx  Selected device\n  * @param  ch_num  Channel number\n  *         This parameter can be a value from 1 to 15\n  * @param  epnum  Endpoint number\n  *          This parameter can be a value from 1 to 15\n  * @param  dev_address  Current device address\n  *          This parameter can be a value from 0 to 255\n  * @param  speed  Current device speed\n  *          This parameter can be one of these values:\n  *            @arg USB_OTG_SPEED_HIGH: High speed mode\n  *            @arg USB_OTG_SPEED_FULL: Full speed mode\n  *            @arg USB_OTG_SPEED_LOW: Low speed mode\n  * @param  ep_type  Endpoint Type\n  *          This parameter can be one of these values:\n  *            @arg EP_TYPE_CTRL: Control type\n  *            @arg EP_TYPE_ISOC: Isochronous type\n  *            @arg EP_TYPE_BULK: Bulk type\n  *            @arg EP_TYPE_INTR: Interrupt type\n  * @param  mps  Max Packet Size\n  *          This parameter can be a value from 0 to 32K\n  * @retval HAL state\n  */\nHAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num,\n                              uint8_t epnum, uint8_t dev_address, uint8_t speed,\n                              uint8_t ep_type, uint16_t mps)\n{\n  HAL_StatusTypeDef ret = HAL_OK;\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t HCcharEpDir, HCcharLowSpeed;\n  uint32_t HostCoreSpeed;\n\n  /* Clear old interrupt conditions for this host channel. */\n  USBx_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU;\n\n  /* Enable channel interrupts required for this transfer. */\n  switch (ep_type)\n  {\n    case EP_TYPE_CTRL:\n    case EP_TYPE_BULK:\n      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\n                                            USB_OTG_HCINTMSK_STALLM |\n                                            USB_OTG_HCINTMSK_TXERRM |\n                                            USB_OTG_HCINTMSK_DTERRM |\n                                            USB_OTG_HCINTMSK_AHBERR |\n                                            USB_OTG_HCINTMSK_NAKM;\n\n      if ((epnum & 0x80U) == 0x80U)\n      {\n        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\n      }\n      else\n      {\n        if ((USBx->CID & (0x1U << 8)) != 0U)\n        {\n          USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET |\n                                                 USB_OTG_HCINTMSK_ACKM;\n        }\n      }\n      break;\n\n    case EP_TYPE_INTR:\n      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\n                                            USB_OTG_HCINTMSK_STALLM |\n                                            USB_OTG_HCINTMSK_TXERRM |\n                                            USB_OTG_HCINTMSK_DTERRM |\n                                            USB_OTG_HCINTMSK_NAKM   |\n                                            USB_OTG_HCINTMSK_AHBERR |\n                                            USB_OTG_HCINTMSK_FRMORM;\n\n      if ((epnum & 0x80U) == 0x80U)\n      {\n        USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;\n      }\n\n      break;\n\n    case EP_TYPE_ISOC:\n      USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM  |\n                                            USB_OTG_HCINTMSK_ACKM   |\n                                            USB_OTG_HCINTMSK_AHBERR |\n                                            USB_OTG_HCINTMSK_FRMORM;\n\n      if ((epnum & 0x80U) == 0x80U)\n      {\n        USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);\n      }\n      break;\n\n    default:\n      ret = HAL_ERROR;\n      break;\n  }\n\n  /* Enable the top level host channel interrupt. */\n  USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU);\n\n  /* Make sure host channel interrupts are enabled. */\n  USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;\n\n  /* Program the HCCHAR register */\n  if ((epnum & 0x80U) == 0x80U)\n  {\n    HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR;\n  }\n  else\n  {\n    HCcharEpDir = 0U;\n  }\n\n  HostCoreSpeed = USB_GetHostSpeed(USBx);\n\n  /* LS device plugged to HUB */\n  if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED))\n  {\n    HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV;\n  }\n  else\n  {\n    HCcharLowSpeed = 0U;\n  }\n\n  USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) |\n                                      ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) |\n                                      (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) |\n                                      ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed;\n\n  if (ep_type == EP_TYPE_INTR)\n  {\n    USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;\n  }\n\n  return ret;\n}\n\n/**\n  * @brief  Start a transfer over a host channel\n  * @param  USBx  Selected device\n  * @param  hc  pointer to host channel structure\n  * @param  dma USB dma enabled or disabled\n  *          This parameter can be one of these values:\n  *           0 : DMA feature not used\n  *           1 : DMA feature used\n  * @retval HAL state\n  */\nHAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t ch_num = (uint32_t)hc->ch_num;\n  __IO uint32_t tmpreg;\n  uint8_t  is_oddframe;\n  uint16_t len_words;\n  uint16_t num_packets;\n  uint16_t max_hc_pkt_count = 256U;\n\n  if (((USBx->CID & (0x1U << 8)) != 0U) && (hc->speed == USBH_HS_SPEED))\n  {\n    /* in DMA mode host Core automatically issues ping  in case of NYET/NAK */\n    if ((dma == 1U) && ((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)))\n    {\n      USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET |\n                                               USB_OTG_HCINTMSK_ACKM |\n                                               USB_OTG_HCINTMSK_NAKM);\n    }\n\n    if ((dma == 0U) && (hc->do_ping == 1U))\n    {\n      (void)USB_DoPing(USBx, hc->ch_num);\n      return HAL_OK;\n    }\n\n  }\n\n  /* Compute the expected number of packets associated to the transfer */\n  if (hc->xfer_len > 0U)\n  {\n    num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet);\n\n    if (num_packets > max_hc_pkt_count)\n    {\n      num_packets = max_hc_pkt_count;\n      hc->XferSize = (uint32_t)num_packets * hc->max_packet;\n    }\n  }\n  else\n  {\n    num_packets = 1U;\n  }\n\n  /*\n   * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of\n   * max_packet size.\n   */\n  if (hc->ep_is_in != 0U)\n  {\n    hc->XferSize = (uint32_t)num_packets * hc->max_packet;\n  }\n  else\n  {\n    hc->XferSize = hc->xfer_len;\n  }\n\n  /* Initialize the HCTSIZn register */\n  USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) |\n                            (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\n                            (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID);\n\n  if (dma != 0U)\n  {\n    /* xfer_buff MUST be 32-bits aligned */\n    USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff;\n  }\n\n  is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U;\n  USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;\n  USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29;\n\n  /* Set host channel enable */\n  tmpreg = USBx_HC(ch_num)->HCCHAR;\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\n\n  /* make sure to set the correct ep direction */\n  if (hc->ep_is_in != 0U)\n  {\n    tmpreg |= USB_OTG_HCCHAR_EPDIR;\n  }\n  else\n  {\n    tmpreg &= ~USB_OTG_HCCHAR_EPDIR;\n  }\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\n  USBx_HC(ch_num)->HCCHAR = tmpreg;\n\n  if (dma != 0U) /* dma mode */\n  {\n    return HAL_OK;\n  }\n\n  if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U))\n  {\n    switch (hc->ep_type)\n    {\n      /* Non periodic transfer */\n      case EP_TYPE_CTRL:\n      case EP_TYPE_BULK:\n\n        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\n\n        /* check if there is enough space in FIFO space */\n        if (len_words > (USBx->HNPTXSTS & 0xFFFFU))\n        {\n          /* need to process data in nptxfempty interrupt */\n          USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;\n        }\n        break;\n\n      /* Periodic transfer */\n      case EP_TYPE_INTR:\n      case EP_TYPE_ISOC:\n        len_words = (uint16_t)((hc->xfer_len + 3U) / 4U);\n        /* check if there is enough space in FIFO space */\n        if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */\n        {\n          /* need to process data in ptxfempty interrupt */\n          USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;\n        }\n        break;\n\n      default:\n        break;\n    }\n\n    /* Write packet into the Tx FIFO. */\n    (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0);\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief Read all host channel interrupts status\n  * @param  USBx  Selected device\n  * @retval HAL state\n  */\nuint32_t USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  return ((USBx_HOST->HAINT) & 0xFFFFU);\n}\n\n/**\n  * @brief  Halt a host channel\n  * @param  USBx  Selected device\n  * @param  hc_num  Host Channel number\n  *         This parameter can be a value from 1 to 15\n  * @retval HAL state\n  */\nHAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t hcnum = (uint32_t)hc_num;\n  uint32_t count = 0U;\n  uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18;\n  uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31;\n\n  if (((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) &&\n      (ChannelEna == 0U))\n  {\n    return HAL_OK;\n  }\n\n  /* Check for space in the request queue to issue the halt. */\n  if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK))\n  {\n    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\n\n    if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U)\n    {\n      if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U)\n      {\n        USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\n        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\n        USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\n        do\n        {\n          if (++count > 1000U)\n          {\n            break;\n          }\n        } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\n      }\n      else\n      {\n        USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\n      }\n    }\n  }\n  else\n  {\n    USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;\n\n    if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U)\n    {\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;\n      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\n      USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;\n      do\n      {\n        if (++count > 1000U)\n        {\n          break;\n        }\n      } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\n    }\n    else\n    {\n      USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA;\n    }\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Initiate Do Ping protocol\n  * @param  USBx  Selected device\n  * @param  hc_num  Host Channel number\n  *         This parameter can be a value from 1 to 15\n  * @retval HAL state\n  */\nHAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t chnum = (uint32_t)ch_num;\n  uint32_t num_packets = 1U;\n  uint32_t tmpreg;\n\n  USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\n                           USB_OTG_HCTSIZ_DOPING;\n\n  /* Set host channel enable */\n  tmpreg = USBx_HC(chnum)->HCCHAR;\n  tmpreg &= ~USB_OTG_HCCHAR_CHDIS;\n  tmpreg |= USB_OTG_HCCHAR_CHENA;\n  USBx_HC(chnum)->HCCHAR = tmpreg;\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  Stop Host Core\n  * @param  USBx  Selected device\n  * @retval HAL state\n  */\nHAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n  uint32_t count = 0U;\n  uint32_t value;\n  uint32_t i;\n\n  (void)USB_DisableGlobalInt(USBx);\n\n  /* Flush FIFO */\n  (void)USB_FlushTxFifo(USBx, 0x10U);\n  (void)USB_FlushRxFifo(USBx);\n\n  /* Flush out any leftover queued requests. */\n  for (i = 0U; i <= 15U; i++)\n  {\n    value = USBx_HC(i)->HCCHAR;\n    value |=  USB_OTG_HCCHAR_CHDIS;\n    value &= ~USB_OTG_HCCHAR_CHENA;\n    value &= ~USB_OTG_HCCHAR_EPDIR;\n    USBx_HC(i)->HCCHAR = value;\n  }\n\n  /* Halt all channels to put them into a known state. */\n  for (i = 0U; i <= 15U; i++)\n  {\n    value = USBx_HC(i)->HCCHAR;\n    value |= USB_OTG_HCCHAR_CHDIS;\n    value |= USB_OTG_HCCHAR_CHENA;\n    value &= ~USB_OTG_HCCHAR_EPDIR;\n    USBx_HC(i)->HCCHAR = value;\n\n    do\n    {\n      if (++count > 1000U)\n      {\n        break;\n      }\n    } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);\n  }\n\n  /* Clear any pending Host interrupts */\n  USBx_HOST->HAINT = 0xFFFFFFFFU;\n  USBx->GINTSTS = 0xFFFFFFFFU;\n\n  (void)USB_EnableGlobalInt(USBx);\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_ActivateRemoteWakeup active remote wakeup signalling\n  * @param  USBx Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)\n  {\n    /* active Remote wakeup signalling */\n    USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;\n  }\n\n  return HAL_OK;\n}\n\n/**\n  * @brief  USB_DeActivateRemoteWakeup de-active remote wakeup signalling\n  * @param  USBx Selected device\n  * @retval HAL status\n  */\nHAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx)\n{\n  uint32_t USBx_BASE = (uint32_t)USBx;\n\n  /* active Remote wakeup signalling */\n  USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);\n\n  return HAL_OK;\n}\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */\n#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Inc/usbd_cdc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_cdc.h\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   header file for the usbd_cdc.c file.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USB_CDC_H\n#define __USB_CDC_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include  \"usbd_ioreq.h\"\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n\n/** @defgroup usbd_cdc\n  * @brief This file is the Header file for usbd_cdc.c\n  * @{\n  */\n\n\n/** @defgroup usbd_cdc_Exported_Defines\n  * @{\n  */\n#define CDC_IN_EP                                   0x81  /* EP1 for data IN */\n#define CDC_OUT_EP                                  0x01  /* EP1 for data OUT */\n#define CDC_CMD_EP                                  0x82  /* EP2 for CDC commands */\n#define ODRIVE_IN_EP                                0x83  /* EP3 IN: ODrive device TX endpoint */\n#define ODRIVE_OUT_EP                               0x03  /* EP3 OUT: ODrive device RX endpoint */\n\n/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrates and performance. */\n#define CDC_DATA_HS_MAX_PACKET_SIZE                 64  /* Endpoint IN & OUT Packet size */\n#define CDC_DATA_FS_MAX_PACKET_SIZE                 64  /* Endpoint IN & OUT Packet size */\n#define CDC_CMD_PACKET_SIZE                         8  /* Control Endpoint Packet size */\n\n#define USB_CDC_CONFIG_DESC_SIZ                     (67 + 39)\n#define CDC_DATA_HS_IN_PACKET_SIZE                  CDC_DATA_HS_MAX_PACKET_SIZE\n#define CDC_DATA_HS_OUT_PACKET_SIZE                 CDC_DATA_HS_MAX_PACKET_SIZE\n\n#define CDC_DATA_FS_IN_PACKET_SIZE                  CDC_DATA_FS_MAX_PACKET_SIZE\n#define CDC_DATA_FS_OUT_PACKET_SIZE                 CDC_DATA_FS_MAX_PACKET_SIZE\n\n/*---------------------------------------------------------------------*/\n/*  CDC definitions                                                    */\n/*---------------------------------------------------------------------*/\n#define CDC_SEND_ENCAPSULATED_COMMAND               0x00\n#define CDC_GET_ENCAPSULATED_RESPONSE               0x01\n#define CDC_SET_COMM_FEATURE                        0x02\n#define CDC_GET_COMM_FEATURE                        0x03\n#define CDC_CLEAR_COMM_FEATURE                      0x04\n#define CDC_SET_LINE_CODING                         0x20\n#define CDC_GET_LINE_CODING                         0x21\n#define CDC_SET_CONTROL_LINE_STATE                  0x22\n#define CDC_SEND_BREAK                              0x23\n\n/**\n  * @}\n  */\n\n\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\ntypedef struct\n{\n    uint32_t bitrate;\n    uint8_t  format;\n    uint8_t  paritytype;\n    uint8_t  datatype;\n}USBD_CDC_LineCodingTypeDef;\n\ntypedef struct _USBD_CDC_Itf\n{\n    int8_t (* Init)          (void);\n    int8_t (* DeInit)        (void);\n    int8_t (* Control)       (uint8_t, uint8_t * , uint16_t);\n    int8_t (* Receive)       (uint8_t *, uint32_t *, uint8_t);\n\n}USBD_CDC_ItfTypeDef;\n\ntypedef struct\n{\n    uint8_t* Buffer;\n    uint32_t Length;\n    volatile uint8_t State;\n}\n    USBD_CDC_EP_HandleTypeDef;\n\ntypedef struct\n{\n    uint32_t data[CDC_DATA_HS_MAX_PACKET_SIZE/4];      /* Force 32bits alignment */\n    uint8_t  CmdOpCode;\n    uint8_t  CmdLength;\n\n    USBD_CDC_EP_HandleTypeDef CDC_Tx;\n    USBD_CDC_EP_HandleTypeDef CDC_Rx;\n\n    USBD_CDC_EP_HandleTypeDef REF_Tx;\n    USBD_CDC_EP_HandleTypeDef ODRIVE_Rx;\n}\n    USBD_CDC_HandleTypeDef;\n\n\n\n/** @defgroup USBD_CORE_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CORE_Exported_Variables\n  * @{\n  */\n\nextern USBD_ClassTypeDef  USBD_CDC;\n#define USBD_CDC_CLASS    &USBD_CDC\n/**\n  * @}\n  */\n\n/** @defgroup USB_CORE_Exported_Functions\n  * @{\n  */\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev,\n                                      USBD_CDC_ItfTypeDef *fops);\n\nuint8_t  USBD_CDC_SetTxBuffer        (USBD_HandleTypeDef   *pdev,\n                                      uint8_t  *pbuff,\n                                      uint16_t length,\n                                      uint8_t endpoint_pair);\n\nuint8_t  USBD_CDC_SetRxBuffer        (USBD_HandleTypeDef   *pdev,\n                                      uint8_t  *pbuff, uint8_t endpoint_pair);\n\nuint8_t  USBD_CDC_ReceivePacket      (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair);\n\nuint8_t  USBD_CDC_TransmitPacket     (USBD_HandleTypeDef *pdev, uint8_t endpoint_pair);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif  /* __USB_CDC_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Class/CDC/Src/usbd_cdc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_cdc.c\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   This file provides the high layer firmware functions to manage the\n  *          following functionalities of the USB CDC Class:\n  *           - Initialization and Configuration of high and low layer\n  *           - Enumeration as CDC Device (and enumeration for each implemented memory interface)\n  *           - OUT/IN data transfer\n  *           - Command IN transfer (class requests management)\n  *           - Error management\n  *\n  *  @verbatim\n  *\n  *          ===================================================================\n  *                                CDC Class Driver Description\n  *          ===================================================================\n  *           This driver manages the \"Universal Serial Bus Class Definitions for Communications Devices\n  *           Revision 1.2 November 16, 2007\" and the sub-protocol specification of \"Universal Serial Bus\n  *           Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007\"\n  *           This driver implements the following aspects of the specification:\n  *             - Device descriptor management\n  *             - Configuration descriptor management\n  *             - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)\n  *             - Requests management (as described in section 6.2 in specification)\n  *             - Abstract Control Model compliant\n  *             - Union Functional collection (using 1 IN endpoint for control)\n  *             - Data interface class\n  *\n  *           These aspects may be enriched or modified for a specific user application.\n  *\n  *            This driver doesn't implement the following aspects of the specification\n  *            (but it is possible to manage these features with some modifications on this driver):\n  *             - Any class-specific aspect relative to communication classes should be managed by user application.\n  *             - All communication classes other than PSTN are not managed\n  *\n  *  @endverbatim\n  *\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software\n  * distributed under the License is distributed on an \"AS IS\" BASIS,\n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_cdc.h\"\n#include \"usbd_desc.h\"\n#include \"usbd_ctlreq.h\"\n#include <cmsis_os.h>\n#include <freertos_inc.h>\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n\n\n/** @defgroup USBD_CDC\n  * @brief usbd core module\n  * @{\n  */\n\n/** @defgroup USBD_CDC_Private_TypesDefinitions\n  * @{\n  */\n/**\n  * @}\n  */\n\n\n/** @defgroup USBD_CDC_Private_Defines\n  * @{\n  */\n/**\n  * @}\n  */\n\n\n/** @defgroup USBD_CDC_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @defgroup USBD_CDC_Private_FunctionPrototypes\n  * @{\n  */\n\n\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev,\n                               uint8_t cfgidx);\n\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,\n                                 uint8_t cfgidx);\n\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev,\n                                USBD_SetupReqTypedef *req);\n\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev,\n                                 uint8_t epnum);\n\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev,\n                                  uint8_t epnum);\n\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev);\n\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length);\n\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length);\n\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\n\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length);\n\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length);\n\nstatic uint8_t  USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req);\n//static uint8_t * USBD_GetUsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);\n\n/* USB Standard Device Descriptor */\n__ALIGN_BEGIN static uint8_t USBD_CDC_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END =\n    {\n        USB_LEN_DEV_QUALIFIER_DESC,\n        USB_DESC_TYPE_DEVICE_QUALIFIER,\n        0x00,\n        0x02,\n        0x00,\n        0x00,\n        0x00,\n        0x40,\n        0x01,\n        0x00,\n    };\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_Private_Variables\n  * @{\n  */\n\n\n/* CDC interface class callbacks structure */\nUSBD_ClassTypeDef  USBD_CDC =\n    {\n        USBD_CDC_Init,\n        USBD_CDC_DeInit,\n        USBD_CDC_Setup,\n        NULL,                 /* EP0_TxSent, */\n        USBD_CDC_EP0_RxReady,\n        USBD_CDC_DataIn,\n        USBD_CDC_DataOut,\n        NULL,\n        NULL,\n        NULL,\n        USBD_CDC_GetHSCfgDesc,\n        USBD_CDC_GetFSCfgDesc,\n        USBD_CDC_GetOtherSpeedCfgDesc,\n        USBD_CDC_GetDeviceQualifierDescriptor,\n        USBD_UsrStrDescriptor\n    };\n\n/* USB CDC device Configuration Descriptor */\n__ALIGN_BEGIN uint8_t USBD_CDC_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END =\n    {\n        /*Configuration Descriptor*/\n        0x09,   /* bLength: Configuration Descriptor size */\n        USB_DESC_TYPE_CONFIGURATION,      /* bDescriptorType: Configuration */\n        USB_CDC_CONFIG_DESC_SIZ,                /* wTotalLength:no of returned bytes */\n        0x00,\n        0x03,   /* bNumInterfaces: 3 interfaces (2 for CDC, 1 custom) */\n        0x01,   /* bConfigurationValue: Configuration value */\n        0x00,   /* iConfiguration: Index of string descriptor describing the configuration */\n        0xC0,   /* bmAttributes: self powered */\n        0x32,   /* MaxPower 0 mA */\n\n        ///////////////////////////////////////////////////////////////////////////////\n\n        /* Interface Association Descriptor: CDC device (virtual com port) */\n        0x08,   /* bLength: IAD size */\n        0x0B,   /* bDescriptorType: Interface Association Descriptor */\n        0x00,   /* bFirstInterface */\n        0x02,   /* bInterfaceCount */\n        0x02,   /* bFunctionClass: Communication Interface Class */\n        0x02,   /* bFunctionSubClass: Abstract Control Model */\n        0x01,   /* bFunctionProtocol: Common AT commands */\n        0x00,   /* iFunction */\n\n        /*---------------------------------------------------------------------------*/\n\n        /*Interface Descriptor */\n        0x09,   /* bLength: Interface Descriptor size */\n        USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: Interface */\n        /* Interface descriptor type */\n        0x00,   /* bInterfaceNumber: Number of Interface */\n        0x00,   /* bAlternateSetting: Alternate setting */\n        0x01,   /* bNumEndpoints: One endpoints used */\n        0x02,   /* bInterfaceClass: Communication Interface Class */\n        0x02,   /* bInterfaceSubClass: Abstract Control Model */\n        0x01,   /* bInterfaceProtocol: Common AT commands */\n        0x00,   /* iInterface: */\n\n        /*Header Functional Descriptor*/\n        0x05,   /* bLength: Endpoint Descriptor size */\n        0x24,   /* bDescriptorType: CS_INTERFACE */\n        0x00,   /* bDescriptorSubtype: Header Func Desc */\n        0x10,   /* bcdCDC: spec release number */\n        0x01,\n\n        /*Call Management Functional Descriptor*/\n        0x05,   /* bFunctionLength */\n        0x24,   /* bDescriptorType: CS_INTERFACE */\n        0x01,   /* bDescriptorSubtype: Call Management Func Desc */\n        0x00,   /* bmCapabilities: D0+D1 */\n        0x01,   /* bDataInterface: 1 */\n\n        /*ACM Functional Descriptor*/\n        0x04,   /* bFunctionLength */\n        0x24,   /* bDescriptorType: CS_INTERFACE */\n        0x02,   /* bDescriptorSubtype: Abstract Control Management desc */\n        0x02,   /* bmCapabilities */\n\n        /*Union Functional Descriptor*/\n        0x05,   /* bFunctionLength */\n        0x24,   /* bDescriptorType: CS_INTERFACE */\n        0x06,   /* bDescriptorSubtype: Union func desc */\n        0x00,   /* bMasterInterface: Communication class interface */\n        0x01,   /* bSlaveInterface0: Data Class Interface */\n\n        /*Endpoint 2 Descriptor*/\n        0x07,                           /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_ENDPOINT,   /* bDescriptorType: Endpoint */\n        CDC_CMD_EP,                     /* bEndpointAddress */\n        0x03,                           /* bmAttributes: Interrupt */\n        LOBYTE(CDC_CMD_PACKET_SIZE),     /* wMaxPacketSize: */\n        HIBYTE(CDC_CMD_PACKET_SIZE),\n        0x10,                           /* bInterval: */\n        /*---------------------------------------------------------------------------*/\n\n        /*Data class interface descriptor*/\n        0x09,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\n        0x01,   /* bInterfaceNumber: Number of Interface */\n        0x00,   /* bAlternateSetting: Alternate setting */\n        0x02,   /* bNumEndpoints: Two endpoints used */\n        0x0A,   /* bInterfaceClass: CDC */\n        0x00,   /* bInterfaceSubClass: */\n        0x00,   /* bInterfaceProtocol: */\n        0x00,   /* iInterface: */\n\n        /*Endpoint OUT Descriptor*/\n        0x07,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\n        CDC_OUT_EP,                        /* bEndpointAddress */\n        0x02,                              /* bmAttributes: Bulk */\n        LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\n        HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\n        0x00,                              /* bInterval: ignore for Bulk transfer */\n\n        /*Endpoint IN Descriptor*/\n        0x07,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\n        CDC_IN_EP,                         /* bEndpointAddress */\n        0x02,                              /* bmAttributes: Bulk */\n        LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\n        HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\n        0x00,                              /* bInterval: ignore for Bulk transfer */\n\n        ///////////////////////////////////////////////////////////////////////////////\n\n        /* Interface Association Descriptor: custom device */\n        0x08,   /* bLength: IAD size */\n        0x0B,   /* bDescriptorType: Interface Association Descriptor */\n        0x02,   /* bFirstInterface */\n        0x01,   /* bInterfaceCount */\n        0x00,   /* bFunctionClass: */\n        0x00,   /* bFunctionSubClass: */\n        0x00,   /* bFunctionProtocol: */\n        0x06,   /* iFunction */\n\n        /*---------------------------------------------------------------------------*/\n\n        /*Data class interface descriptor*/\n        0x09,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_INTERFACE,  /* bDescriptorType: */\n        0x02,   /* bInterfaceNumber: Number of Interface */\n        0x00,   /* bAlternateSetting: Alternate setting */\n        0x02,   /* bNumEndpoints: Two endpoints used */\n        0x00,   /* bInterfaceClass: vendor specific */\n        0x01,   /* bInterfaceSubClass: ODrive Communication */\n        0x00,   /* bInterfaceProtocol: */\n        0x00,   /* iInterface: */\n\n        /*Endpoint OUT Descriptor*/\n        0x07,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\n        ODRIVE_OUT_EP,                        /* bEndpointAddress */\n        0x02,                              /* bmAttributes: Bulk */\n        LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\n        HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\n        0x00,                              /* bInterval: ignore for Bulk transfer */\n\n        /*Endpoint IN Descriptor*/\n        0x07,   /* bLength: Endpoint Descriptor size */\n        USB_DESC_TYPE_ENDPOINT,      /* bDescriptorType: Endpoint */\n        ODRIVE_IN_EP,                         /* bEndpointAddress */\n        0x02,                              /* bmAttributes: Bulk */\n        LOBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),  /* wMaxPacketSize: */\n        HIBYTE(CDC_DATA_HS_MAX_PACKET_SIZE),\n        0x00,                              /* bInterval: ignore for Bulk transfer */\n    } ;\n\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  USBD_CDC_Init\n  *         Initialize the CDC interface\n  * @param  pdev: device instance\n  * @param  cfgidx: Configuration index\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_Init (USBD_HandleTypeDef *pdev,\n                               uint8_t cfgidx)\n{\n    uint8_t ret = 0;\n    USBD_CDC_HandleTypeDef   *hcdc;\n\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )\n    {\n        /* Open EP IN */\n        USBD_LL_OpenEP(pdev,\n                       CDC_IN_EP,\n                       USBD_EP_TYPE_BULK,\n                       CDC_DATA_HS_IN_PACKET_SIZE);\n\n        /* Open EP OUT */\n        USBD_LL_OpenEP(pdev,\n                       CDC_OUT_EP,\n                       USBD_EP_TYPE_BULK,\n                       CDC_DATA_HS_OUT_PACKET_SIZE);\n\n    }\n    else\n    {\n        /* Open EP IN */\n        USBD_LL_OpenEP(pdev,\n                       CDC_IN_EP,\n                       USBD_EP_TYPE_BULK,\n                       CDC_DATA_FS_IN_PACKET_SIZE);\n\n        /* Open EP OUT */\n        USBD_LL_OpenEP(pdev,\n                       CDC_OUT_EP,\n                       USBD_EP_TYPE_BULK,\n                       CDC_DATA_FS_OUT_PACKET_SIZE);\n    }\n\n    /* Open ODrive IN endpoint */\n    USBD_LL_OpenEP(pdev,\n                   ODRIVE_IN_EP,\n                   USBD_EP_TYPE_BULK,\n                   pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_IN_PACKET_SIZE : CDC_DATA_FS_IN_PACKET_SIZE);\n\n    /* Open ODrive OUT endpoint */\n    USBD_LL_OpenEP(pdev,\n                   ODRIVE_OUT_EP,\n                   USBD_EP_TYPE_BULK,\n                   pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE);\n\n    /* Open Command IN EP */\n    USBD_LL_OpenEP(pdev,\n                   CDC_CMD_EP,\n                   USBD_EP_TYPE_INTR,\n                   CDC_CMD_PACKET_SIZE);\n\n\n    pdev->pClassData = USBD_malloc(sizeof (USBD_CDC_HandleTypeDef));\n\n    if(pdev->pClassData == NULL)\n    {\n        ret = 1;\n    }\n    else\n    {\n        hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n        /* Init  physical Interface components */\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Init();\n\n        /* Init Xfer states */\n        hcdc->CDC_Tx.State =0;\n        hcdc->CDC_Rx.State =0;\n        hcdc->REF_Tx.State =0;\n        hcdc->ODRIVE_Rx.State =0;\n\n        if(pdev->dev_speed == USBD_SPEED_HIGH  )\n        {\n            /* Prepare Out endpoint to receive next packet */\n            USBD_LL_PrepareReceive(pdev,\n                                   CDC_OUT_EP,\n                                   hcdc->CDC_Rx.Buffer,\n                                   CDC_DATA_HS_OUT_PACKET_SIZE);\n        }\n        else\n        {\n            /* Prepare Out endpoint to receive next packet */\n            USBD_LL_PrepareReceive(pdev,\n                                   CDC_OUT_EP,\n                                   hcdc->CDC_Rx.Buffer,\n                                   CDC_DATA_FS_OUT_PACKET_SIZE);\n        }\n\n        /* Prepare ODrive Out endpoint to receive next packet */\n        USBD_LL_PrepareReceive(pdev,\n                               ODRIVE_OUT_EP,\n                               hcdc->ODRIVE_Rx.Buffer,\n                               CDC_DATA_FS_OUT_PACKET_SIZE);\n    }\n    return ret;\n}\n\n/**\n  * @brief  USBD_CDC_Init\n  *         DeInitialize the CDC layer\n  * @param  pdev: device instance\n  * @param  cfgidx: Configuration index\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_DeInit (USBD_HandleTypeDef *pdev,\n                                 uint8_t cfgidx)\n{\n    uint8_t ret = 0;\n\n    /* Close EP IN */\n    USBD_LL_CloseEP(pdev,\n                    CDC_IN_EP);\n\n    /* Close EP OUT */\n    USBD_LL_CloseEP(pdev,\n                    CDC_OUT_EP);\n\n    /* Close Command IN EP */\n    USBD_LL_CloseEP(pdev,\n                    CDC_CMD_EP);\n\n    /* Close EP IN */\n    USBD_LL_CloseEP(pdev,\n                    ODRIVE_IN_EP);\n\n    /* Close EP OUT */\n    USBD_LL_CloseEP(pdev,\n                    ODRIVE_OUT_EP);\n\n\n    /* DeInit  physical Interface components */\n    if(pdev->pClassData != NULL)\n    {\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->DeInit();\n        USBD_free(pdev->pClassData);\n        pdev->pClassData = NULL;\n    }\n\n    return ret;\n}\n\n/**\n  * @brief  USBD_CDC_Setup\n  *         Handle the CDC specific requests\n  * @param  pdev: instance\n  * @param  req: usb requests\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_Setup (USBD_HandleTypeDef *pdev,\n                                USBD_SetupReqTypedef *req)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n    static uint8_t ifalt = 0;\n\n    switch (req->bmRequest & USB_REQ_TYPE_MASK)\n    {\n        case USB_REQ_TYPE_CLASS :\n            if (req->wLength)\n            {\n                if (req->bmRequest & 0x80)\n                {\n                    ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\n                                                                      (uint8_t *)hcdc->data,\n                                                                      req->wLength);\n                    USBD_CtlSendData (pdev,\n                                      (uint8_t *)hcdc->data,\n                                      req->wLength);\n                }\n                else\n                {\n                    hcdc->CmdOpCode = req->bRequest;\n                    hcdc->CmdLength = req->wLength;\n\n                    USBD_CtlPrepareRx (pdev,\n                                       (uint8_t *)hcdc->data,\n                                       req->wLength);\n                }\n\n            }\n            else\n            {\n                ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(req->bRequest,\n                                                                  (uint8_t*)req,\n                                                                  0);\n            }\n            break;\n\n        case USB_REQ_TYPE_STANDARD:\n            switch (req->bRequest)\n            {\n                case USB_REQ_GET_INTERFACE :\n                    USBD_CtlSendData (pdev,\n                                      &ifalt,\n                                      1);\n                    break;\n\n                case USB_REQ_SET_INTERFACE :\n                    break;\n            }\n\n        case USB_REQ_TYPE_VENDOR:\n            return USBD_WinUSBComm_SetupVendor(pdev, req);\n\n        default:\n            break;\n    }\n    return USBD_OK;\n}\n\n/**\n  * @brief  USBD_CDC_DataIn\n  *         Data sent on non-control IN endpoint\n  * @param  pdev: device instance\n  * @param  epnum: endpoint number\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_DataIn (USBD_HandleTypeDef *pdev, uint8_t epnum)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    if(pdev->pClassData != NULL)\n    {\n        // NOTE: We would logically expect xx_IN_EP here, but we actually get the xx_OUT_EP\n        if (epnum == CDC_OUT_EP)\n            hcdc->CDC_Tx.State = 0;\n        if (epnum == ODRIVE_OUT_EP)\n            hcdc->REF_Tx.State = 0;\n        //Note: We could use independent semaphores for simoultainous USB transmission.\n        osSemaphoreRelease(sem_usb_tx);\n        return USBD_OK;\n    }\n    else\n    {\n        return USBD_FAIL;\n    }\n}\n\n/**\n  * @brief  USBD_CDC_DataOut\n  *         Data received on non-control Out endpoint\n  * @param  pdev: device instance\n  * @param  epnum: endpoint number\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_DataOut (USBD_HandleTypeDef *pdev, uint8_t epnum)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    USBD_CDC_EP_HandleTypeDef* hEP_Rx;\n    if (epnum == CDC_OUT_EP) {\n        hEP_Rx = &hcdc->CDC_Rx;\n    } else if (epnum == ODRIVE_OUT_EP) {\n        hEP_Rx = &hcdc->ODRIVE_Rx;\n    } else {\n        return USBD_FAIL;\n    }\n\n    /* Get the received data length */\n    hEP_Rx->Length = USBD_LL_GetRxDataSize (pdev, epnum);\n\n    /* USB data will be immediately processed, this allow next USB traffic being\n    NAKed till the end of the application Xfer */\n    if(pdev->pClassData != NULL)\n    {\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Receive(hEP_Rx->Buffer, &hEP_Rx->Length, epnum);\n\n        return USBD_OK;\n    }\n    else\n    {\n        return USBD_FAIL;\n    }\n}\n\n\n\n/**\n  * @brief  USBD_CDC_DataOut\n  *         Data received on non-control Out endpoint\n  * @param  pdev: device instance\n  * @param  epnum: endpoint number\n  * @retval status\n  */\nstatic uint8_t  USBD_CDC_EP0_RxReady (USBD_HandleTypeDef *pdev)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    if((pdev->pUserData != NULL) && (hcdc->CmdOpCode != 0xFF))\n    {\n        ((USBD_CDC_ItfTypeDef *)pdev->pUserData)->Control(hcdc->CmdOpCode,\n                                                          (uint8_t *)hcdc->data,\n                                                          hcdc->CmdLength);\n        hcdc->CmdOpCode = 0xFF;\n\n    }\n    return USBD_OK;\n}\n\n/**\n  * @brief  USBD_CDC_GetFSCfgDesc\n  *         Return configuration descriptor\n  * @param  speed : current device speed\n  * @param  length : pointer data length\n  * @retval pointer to descriptor buffer\n  */\nstatic uint8_t  *USBD_CDC_GetFSCfgDesc (uint16_t *length)\n{\n    *length = sizeof (USBD_CDC_CfgDesc);\n    return USBD_CDC_CfgDesc;\n}\n\n/**\n  * @brief  USBD_CDC_GetHSCfgDesc\n  *         Return configuration descriptor\n  * @param  speed : current device speed\n  * @param  length : pointer data length\n  * @retval pointer to descriptor buffer\n  */\nstatic uint8_t  *USBD_CDC_GetHSCfgDesc (uint16_t *length)\n{\n    *length = sizeof (USBD_CDC_CfgDesc);\n    return USBD_CDC_CfgDesc;\n}\n\n/**\n  * @brief  USBD_CDC_GetCfgDesc\n  *         Return configuration descriptor\n  * @param  speed : current device speed\n  * @param  length : pointer data length\n  * @retval pointer to descriptor buffer\n  */\nstatic uint8_t  *USBD_CDC_GetOtherSpeedCfgDesc (uint16_t *length)\n{\n    *length = sizeof (USBD_CDC_CfgDesc);\n    return USBD_CDC_CfgDesc;\n}\n\n/**\n* @brief  DeviceQualifierDescriptor\n*         return Device Qualifier descriptor\n* @param  length : pointer data length\n* @retval pointer to descriptor buffer\n*/\nuint8_t  *USBD_CDC_GetDeviceQualifierDescriptor (uint16_t *length)\n{\n    *length = sizeof (USBD_CDC_DeviceQualifierDesc);\n    return USBD_CDC_DeviceQualifierDesc;\n}\n\n/**\n* @brief  USBD_CDC_RegisterInterface\n  * @param  pdev: device instance\n  * @param  fops: CD  Interface callback\n  * @retval status\n  */\nuint8_t  USBD_CDC_RegisterInterface  (USBD_HandleTypeDef   *pdev,\n                                      USBD_CDC_ItfTypeDef *fops)\n{\n    uint8_t  ret = USBD_FAIL;\n\n    if(fops != NULL)\n    {\n        pdev->pUserData= fops;\n        ret = USBD_OK;\n    }\n\n    return ret;\n}\n\n/**\n  * @brief  USBD_CDC_SetTxBuffer\n  * @param  pdev: device instance\n  * @param  pbuff: Tx Buffer\n  * @retval status\n  */\nuint8_t  USBD_CDC_SetTxBuffer  (USBD_HandleTypeDef   *pdev,\n                                uint8_t  *pbuff,\n                                uint16_t length,\n                                uint8_t endpoint_pair)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    USBD_CDC_EP_HandleTypeDef* hEP_Tx;\n    if (endpoint_pair == CDC_OUT_EP) {\n        hEP_Tx = &hcdc->CDC_Tx;\n    } else if (endpoint_pair == ODRIVE_OUT_EP) {\n        hEP_Tx = &hcdc->REF_Tx;\n    } else {\n        return USBD_FAIL;\n    }\n\n    hEP_Tx->Buffer = pbuff;\n    hEP_Tx->Length = length;\n\n    return USBD_OK;\n}\n\n\n/**\n  * @brief  USBD_CDC_SetRxBuffer\n  * @param  pdev: device instance\n  * @param  pbuff: Rx Buffer\n  * @retval status\n  */\nuint8_t  USBD_CDC_SetRxBuffer  (USBD_HandleTypeDef   *pdev,\n                                uint8_t  *pbuff, uint8_t endpoint_pair)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    USBD_CDC_EP_HandleTypeDef* hEP_Rx;\n    if (endpoint_pair == CDC_OUT_EP) {\n        hEP_Rx = &hcdc->CDC_Rx;\n    } else if (endpoint_pair == ODRIVE_OUT_EP) {\n        hEP_Rx = &hcdc->ODRIVE_Rx;\n    } else {\n        return USBD_FAIL;\n    }\n\n    hEP_Rx->Buffer = pbuff;\n\n    return USBD_OK;\n}\n\n/**\n  * @brief  USBD_CDC_DataOut\n  *         Data received on non-control Out endpoint\n  * @param  pdev: device instance\n  * @param  epnum: endpoint number\n  * @retval status\n  */\nuint8_t  USBD_CDC_TransmitPacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    if(pdev->pClassData != NULL)\n    {\n        // Select Endpoint\n        USBD_CDC_EP_HandleTypeDef* hEP_Tx;\n        uint8_t in_ep;\n        if (endpoint_pair == CDC_OUT_EP) {\n            hEP_Tx = &hcdc->CDC_Tx;\n            in_ep = CDC_IN_EP;\n        } else if (endpoint_pair == ODRIVE_OUT_EP) {\n            hEP_Tx = &hcdc->REF_Tx;\n            in_ep = ODRIVE_IN_EP;\n        } else {\n            return USBD_FAIL;\n        }\n\n        if(hEP_Tx->State == 0)\n        {\n            /* Tx Transfer in progress */\n            hEP_Tx->State = 1;\n\n            /* Transmit next packet */\n            USBD_LL_Transmit(pdev,\n                             in_ep,\n                             hEP_Tx->Buffer,\n                             hEP_Tx->Length);\n\n            return USBD_OK;\n        }\n        else\n        {\n            return USBD_BUSY;\n        }\n    }\n    else\n    {\n        return USBD_FAIL;\n    }\n}\n\n\n/**\n  * @brief  USBD_CDC_ReceivePacket\n  *         prepare OUT Endpoint for reception\n  * @param  pdev: device instance\n  * @retval status\n  */\nuint8_t  USBD_CDC_ReceivePacket(USBD_HandleTypeDef *pdev, uint8_t endpoint_pair)\n{\n    USBD_CDC_HandleTypeDef   *hcdc = (USBD_CDC_HandleTypeDef*) pdev->pClassData;\n\n    /* Suspend or Resume USB Out process */\n    if(pdev->pClassData != NULL)\n    {\n        // Select Endpoint\n        USBD_CDC_EP_HandleTypeDef* hEP_Rx;\n        uint8_t out_ep;\n        if (endpoint_pair == CDC_OUT_EP) {\n            hEP_Rx = &hcdc->CDC_Rx;\n            out_ep = CDC_OUT_EP;\n        } else if (endpoint_pair == ODRIVE_OUT_EP) {\n            hEP_Rx = &hcdc->ODRIVE_Rx;\n            out_ep = ODRIVE_OUT_EP;\n        } else {\n            return USBD_FAIL;\n        }\n\n        /* Prepare Out endpoint to receive next packet */\n        USBD_LL_PrepareReceive(pdev,\n                               out_ep,\n                               hEP_Rx->Buffer,\n                               pdev->dev_speed == USBD_SPEED_HIGH ? CDC_DATA_HS_OUT_PACKET_SIZE : CDC_DATA_FS_OUT_PACKET_SIZE);\n\n        return USBD_OK;\n    }\n    else\n    {\n        return USBD_FAIL;\n    }\n}\n\n\n/* WinUSB support ------------------------------------------------------------*/\n/*\n* This section tells Windows that it should automatically load the WinUSB driver\n* for the device (more specifically, interface 2 because it's a composite device).\n* This allows for driverless communication with the device.\n*/\n\n#define NUM_INTERFACES 1\n\n#if NUM_INTERFACES == 2\n#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ       (16 + 24 + 24)\n#else\n#define USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ       (16 + 24)\n#endif\n\n\n// This associates winusb driver with the device\n__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Compat_ID_OS_Desc[USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ]  __ALIGN_END =\n    {\n        //    +-- Offset in descriptor\n        //    |             +-- Size\n        //    v             v\n        USB_WINUSBCOMM_COMPAT_ID_OS_DESC_SIZ, 0, 0, 0,    //    0 dwLength    4 DWORD The length, in bytes, of the complete extended compat ID descriptor\n        0x00, 0x01,                                       //    4 bcdVersion  2 BCD The descriptor’s version number, in binary coded decimal (BCD) format\n        0x04, 0x00,                                       //    6 wIndex      2 WORD  An index that identifies the particular OS feature descriptor\n        NUM_INTERFACES,                                   //    8 bCount      1 BYTE  The number of custom property sections\n        0, 0, 0, 0, 0, 0, 0,                              //    9 RESERVED    7 BYTEs Reserved\n        //    =====================\n        //                 16\n\n        //   +-- Offset from function section start\n        //   |                        +-- Size\n        //   v                        v\n        2,                                                //   0  bFirstInterfaceNumber 1 BYTE  The interface or function number\n        0,                                                //   1  RESERVED              1 BYTE  Reserved\n        0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00,   //   2  compatibleID          8 BYTEs The function’s compatible ID      (\"WINUSB\")\n        0, 0, 0, 0, 0, 0, 0, 0,                           //  10  subCompatibleID       8 BYTEs The function’s subcompatible ID\n        0, 0, 0, 0, 0, 0,                                 //  18  RESERVED              6 BYTEs Reserved\n        //  =================================\n        //                           24\n#if NUM_INTERFACES == 2\n        //   +-- Offset from function section start\n                                                    //   |                        +-- Size\n                                                    //   v                        v\n  2,                                                //   0  bFirstInterfaceNumber 1 BYTE  The interface or function number\n  0,                                                //   1  RESERVED              1 BYTE  Reserved\n  0x57, 0x49, 0x4E, 0x55, 0x53, 0x42, 0x00, 0x00,   //   2  compatibleID          8 BYTEs The function’s compatible ID      (\"WINUSB\")\n  0, 0, 0, 0, 0, 0, 0, 0,                           //  10  subCompatibleID       8 BYTEs The function’s subcompatible ID\n  0, 0, 0, 0, 0, 0,                                 //  18  RESERVED              6 BYTEs Reserved\n                                                    //  =================================\n                                                    //                           24\n#endif\n    };\n\n\n// Properties are added to:\n// HKEY_LOCAL_MACHINE\\SYSTEM\\CurrentControlSet\\Enum\\USB\\VID_xxxx&PID_xxxx\\sssssssss\\Device Parameters\n// Use USBDeview or similar to uninstall\n\n__ALIGN_BEGIN uint8_t USBD_WinUSBComm_Extended_Properties_OS_Desc[0xB6]  __ALIGN_END =\n    {\n        0xB6, 0x00, 0x00, 0x00,   // 0 dwLength   4 DWORD The length, in bytes, of the complete extended properties descriptor\n        0x00, 0x01,               // 4 bcdVersion 2 BCD   The descriptor’s version number, in binary coded decimal (BCD) format\n        0x05, 0x00,               // 6 wIndex     2 WORD  The index for extended properties OS descriptors\n        0x02, 0x00,               // 8 wCount     2 WORD  The number of custom property sections that follow the header section\n        // ====================\n        //             10\n///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n        0x84, 0x00, 0x00, 0x00,   //  0       dwSize                  4 DWORD             The size of this custom properties section\n        0x01, 0x00, 0x00, 0x00,   //  4       dwPropertyDataType      4 DWORD             Property data format\n        0x28, 0x00,               //  8       wPropertyNameLength     2 DWORD             Property name length\n        // ========================================\n        //                                 10\n        // 10       bPropertyName         PNL WCHAR[]           The property name\n        'D',0, 'e',0, 'v',0, 'i',0, 'c',0, 'e',0, 'I',0, 'n',0,\n        't',0, 'e',0, 'r',0, 'f',0, 'a',0, 'c',0, 'e',0, 'G',0,\n        'U',0, 'I',0, 'D',0, 0,0,\n        // ========================================\n        //                                 40 (0x28)\n\n        0x4E, 0x00, 0x00, 0x00,   // 10 + PNL dwPropertyDataLength    4 DWORD             Length of the buffer holding the property data\n        // ========================================\n        //                                  4\n        // 14 + PNL bPropertyData         PDL Format-dependent  Property data\n        '{',0, 'E',0, 'A',0, '0',0, 'B',0, 'D',0, '5',0, 'C',0,\n        '3',0, '-',0, '5',0, '0',0, 'F',0, '3',0, '-',0, '4',0,\n        '8',0, '8',0, '8',0, '-',0, '8',0, '4',0, 'B',0, '4',0,\n        '-',0, '7',0, '4',0, 'E',0, '5',0, '0',0, 'E',0, '1',0,\n        '6',0, '4',0, '9',0, 'D',0, 'B',0, '}',0,  0 ,0,\n        // ========================================\n        //                                 78 (0x4E)\n///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////\n        0x3E, 0x00, 0x00, 0x00,   //  0 dwSize 0x00000030 (62 bytes)\n        0x01, 0x00, 0x00, 0x00,   //  4 dwPropertyDataType 0x00000001 (Unicode string)\n        0x0C, 0x00,               //  8 wPropertyNameLength 0x000C (12 bytes)\n        // ========================================\n        //                                  10\n        'L',0, 'a',0, 'b',0, 'e',0, 'l',0, 0,0,\n        // 10 bPropertyName “Label”\n        // ========================================\n        //                                  12\n        0x24, 0x00, 0x00, 0x00,   // 22 dwPropertyDataLength 0x00000016 (36 bytes)\n        // ========================================\n        //                                  4\n        'O',0, 'D',0, 'r',0, 'i',0, 'v',0, 'e',0, 0,0\n        // 26 bPropertyData “ODrive”\n        // ========================================\n        //                                  14\n\n    };\n\n\n\nstatic uint8_t  USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\n{\n    switch (req->wIndex)\n    {\n        case 0x04:\n            USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Compat_ID_OS_Desc, req->wLength);\n            break;\n        default:\n            USBD_CtlError(pdev , req);\n            return USBD_FAIL;\n    }\n    return USBD_OK;\n}\nstatic uint8_t  USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor (USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\n{\n    uint8_t byInterfaceIndex = (uint8_t)req->wValue;\n    if ( req->wIndex != 0x05 )\n    {\n        USBD_CtlError(pdev , req);\n        return USBD_FAIL;\n    }\n    switch ( byInterfaceIndex )\n    {\n        case 0:\n#if NUM_INTERFACES == 2\n            case 1:\n#endif\n            USBD_CtlSendData (pdev, USBD_WinUSBComm_Extended_Properties_OS_Desc, req->wLength);\n            break;\n        default:\n            USBD_CtlError(pdev , req);\n            return USBD_FAIL;\n    }\n    return USBD_OK;\n}\nstatic uint8_t  USBD_WinUSBComm_SetupVendorDevice(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\n{\n    USBD_CtlError(pdev , req);\n    return USBD_FAIL;\n}\nstatic uint8_t  USBD_WinUSBComm_SetupVendorInterface(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\n{\n    USBD_CtlError(pdev , req);\n    // TODO: check if this is important\n    return USBD_FAIL;\n}\nstatic uint8_t  USBD_WinUSBComm_SetupVendor(USBD_HandleTypeDef *pdev, USBD_SetupReqTypedef *req)\n{\n    switch ( req->bmRequest & USB_REQ_RECIPIENT_MASK )\n    {\n        case USB_REQ_RECIPIENT_DEVICE:\n            return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedCompatIDOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorDevice(pdev, req);\n        case USB_REQ_RECIPIENT_INTERFACE:\n            return ( MS_VendorCode == req->bRequest ) ? USBD_WinUSBComm_GetMSExtendedPropertiesOSDescriptor(pdev, req) : USBD_WinUSBComm_SetupVendorInterface(pdev, req);\n        case USB_REQ_RECIPIENT_ENDPOINT:\n            // fall through\n        default:\n            break;\n    }\n    USBD_CtlError(pdev , req);\n    return USBD_FAIL;\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_core.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_core.h\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   Header file for usbd_core.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_CORE_H\n#define __USBD_CORE_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_conf.h\"\n#include \"usbd_def.h\"\n#include \"usbd_ioreq.h\"\n#include \"usbd_ctlreq.h\"\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n  \n/** @defgroup USBD_CORE\n  * @brief This file is the Header file for usbd_core.c file\n  * @{\n  */ \n\n\n/** @defgroup USBD_CORE_Exported_Defines\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_CORE_Exported_TypesDefinitions\n  * @{\n  */\n \n\n/**\n  * @}\n  */ \n\n\n\n/** @defgroup USBD_CORE_Exported_Macros\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_CORE_Exported_Variables\n  * @{\n  */ \n#define USBD_SOF          USBD_LL_SOF\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_CORE_Exported_FunctionsPrototype\n  * @{\n  */ \nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id);\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef USBD_Start  (USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef USBD_Stop   (USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass);\n\nUSBD_StatusTypeDef USBD_RunTestMode (USBD_HandleTypeDef  *pdev); \nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx);\n\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup);\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata);\n\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev);\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed);\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev);\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev);\n\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev);\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum);\n\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev);\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev);\n\n/* USBD Low Level Driver */\nUSBD_StatusTypeDef  USBD_LL_Init (USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef  USBD_LL_DeInit (USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef  USBD_LL_Start(USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef  USBD_LL_Stop (USBD_HandleTypeDef *pdev);\nUSBD_StatusTypeDef  USBD_LL_OpenEP  (USBD_HandleTypeDef *pdev, \n                                      uint8_t  ep_addr,                                      \n                                      uint8_t  ep_type,\n                                      uint16_t ep_mps);\n\nUSBD_StatusTypeDef  USBD_LL_CloseEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \nUSBD_StatusTypeDef  USBD_LL_FlushEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \nUSBD_StatusTypeDef  USBD_LL_StallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \nUSBD_StatusTypeDef  USBD_LL_ClearStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \nuint8_t             USBD_LL_IsStallEP (USBD_HandleTypeDef *pdev, uint8_t ep_addr);   \nUSBD_StatusTypeDef  USBD_LL_SetUSBAddress (USBD_HandleTypeDef *pdev, uint8_t dev_addr);   \nUSBD_StatusTypeDef  USBD_LL_Transmit (USBD_HandleTypeDef *pdev, \n                                      uint8_t  ep_addr,                                      \n                                      uint8_t  *pbuf,\n                                      uint16_t  size);\n\nUSBD_StatusTypeDef  USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, \n                                           uint8_t  ep_addr,                                      \n                                           uint8_t  *pbuf,\n                                           uint16_t  size);\n\nuint32_t USBD_LL_GetRxDataSize  (USBD_HandleTypeDef *pdev, uint8_t  ep_addr);  \nvoid  USBD_LL_Delay (uint32_t Delay);\n\n/**\n  * @}\n  */ \n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_CORE_H */\n\n/**\n  * @}\n  */ \n\n/**\n* @}\n*/ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ctlreq.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_req.h\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   Header file for the usbd_req.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USB_REQUEST_H\n#define __USB_REQUEST_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include  \"usbd_def.h\"\n\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n  \n/** @defgroup USBD_REQ\n  * @brief header file for the usbd_req.c file\n  * @{\n  */ \n\n/** @defgroup USBD_REQ_Exported_Defines\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Exported_Types\n  * @{\n  */\n/**\n  * @}\n  */ \n\n\n\n/** @defgroup USBD_REQ_Exported_Macros\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n/** @defgroup USBD_REQ_Exported_Variables\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n/** @defgroup USBD_REQ_Exported_FunctionsPrototype\n  * @{\n  */ \n\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\nUSBD_StatusTypeDef  USBD_StdEPReq  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef  *req);\n\n\nvoid USBD_CtlError  (USBD_HandleTypeDef  *pdev, USBD_SetupReqTypedef *req);\n\nvoid USBD_ParseSetupRequest (USBD_SetupReqTypedef *req, uint8_t *pdata);\n\nvoid USBD_GetString         (uint8_t *desc, uint8_t *unicode, uint16_t *len);\n/**\n  * @}\n  */ \n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USB_REQUEST_H */\n\n/**\n  * @}\n  */ \n\n/**\n* @}\n*/ \n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_def.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_def.h\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   General defines for the usb device library \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_DEF_H\n#define __USBD_DEF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_conf.h\"\n\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\n  * @{\n  */\n  \n/** @defgroup USB_DEF\n  * @brief general defines for the usb device library file\n  * @{\n  */ \n\n/** @defgroup USB_DEF_Exported_Defines\n  * @{\n  */ \n\n#ifndef NULL\n#define NULL  0\n#endif\n\n\n#define  USB_LEN_DEV_QUALIFIER_DESC                     0x0A\n#define  USB_LEN_DEV_DESC                               0x12\n#define  USB_LEN_CFG_DESC                               0x09\n#define  USB_LEN_IF_DESC                                0x09\n#define  USB_LEN_EP_DESC                                0x07\n#define  USB_LEN_OTG_DESC                               0x03\n#define  USB_LEN_LANGID_STR_DESC                        0x04\n#define  USB_LEN_OTHER_SPEED_DESC_SIZ                   0x09\n\n#define  USBD_IDX_LANGID_STR                            0x00 \n#define  USBD_IDX_MFC_STR                               0x01 \n#define  USBD_IDX_PRODUCT_STR                           0x02\n#define  USBD_IDX_SERIAL_STR                            0x03 \n#define  USBD_IDX_CONFIG_STR                            0x04 \n#define  USBD_IDX_INTERFACE_STR                         0x05\n#define  USBD_IDX_REF_INTF_STR                       0x06\n#define  USBD_IDX_MICROSOFT_DESC_STR                    0xEE\n\n#define  USB_REQ_TYPE_STANDARD                          0x00\n#define  USB_REQ_TYPE_CLASS                             0x20\n#define  USB_REQ_TYPE_VENDOR                            0x40\n#define  USB_REQ_TYPE_MASK                              0x60\n\n#define  USB_REQ_RECIPIENT_DEVICE                       0x00\n#define  USB_REQ_RECIPIENT_INTERFACE                    0x01\n#define  USB_REQ_RECIPIENT_ENDPOINT                     0x02\n#define  USB_REQ_RECIPIENT_MASK                         0x03\n\n#define  USB_REQ_GET_STATUS                             0x00\n#define  USB_REQ_CLEAR_FEATURE                          0x01\n#define  USB_REQ_SET_FEATURE                            0x03\n#define  USB_REQ_SET_ADDRESS                            0x05\n#define  USB_REQ_GET_DESCRIPTOR                         0x06\n#define  USB_REQ_SET_DESCRIPTOR                         0x07\n#define  USB_REQ_GET_CONFIGURATION                      0x08\n#define  USB_REQ_SET_CONFIGURATION                      0x09\n#define  USB_REQ_GET_INTERFACE                          0x0A\n#define  USB_REQ_SET_INTERFACE                          0x0B\n#define  USB_REQ_SYNCH_FRAME                            0x0C\n\n#define  USB_DESC_TYPE_DEVICE                              1\n#define  USB_DESC_TYPE_CONFIGURATION                       2\n#define  USB_DESC_TYPE_STRING                              3\n#define  USB_DESC_TYPE_INTERFACE                           4\n#define  USB_DESC_TYPE_ENDPOINT                            5\n#define  USB_DESC_TYPE_DEVICE_QUALIFIER                    6\n#define  USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION           7\n#define  USB_DESC_TYPE_BOS                                 0x0F\n\n#define USB_CONFIG_REMOTE_WAKEUP                           2\n#define USB_CONFIG_SELF_POWERED                            1\n\n#define USB_FEATURE_EP_HALT                                0\n#define USB_FEATURE_REMOTE_WAKEUP                          1\n#define USB_FEATURE_TEST_MODE                              2\n\n#define USB_DEVICE_CAPABITY_TYPE                           0x10\n\n#define USB_HS_MAX_PACKET_SIZE                            512\n#define USB_FS_MAX_PACKET_SIZE                            64\n#define USB_MAX_EP0_SIZE                                  64\n\n/*  Device Status */\n#define USBD_STATE_DEFAULT                                1\n#define USBD_STATE_ADDRESSED                              2\n#define USBD_STATE_CONFIGURED                             3\n#define USBD_STATE_SUSPENDED                              4\n\n\n/*  EP0 State */    \n#define USBD_EP0_IDLE                                     0\n#define USBD_EP0_SETUP                                    1\n#define USBD_EP0_DATA_IN                                  2\n#define USBD_EP0_DATA_OUT                                 3\n#define USBD_EP0_STATUS_IN                                4\n#define USBD_EP0_STATUS_OUT                               5\n#define USBD_EP0_STALL                                    6    \n\n#define USBD_EP_TYPE_CTRL                                 0\n#define USBD_EP_TYPE_ISOC                                 1\n#define USBD_EP_TYPE_BULK                                 2\n#define USBD_EP_TYPE_INTR                                 3\n\n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_DEF_Exported_TypesDefinitions\n  * @{\n  */\n\ntypedef  struct  usb_setup_req \n{\n    \n    uint8_t   bmRequest;                      \n    uint8_t   bRequest;                           \n    uint16_t  wValue;                             \n    uint16_t  wIndex;                             \n    uint16_t  wLength;                            \n}USBD_SetupReqTypedef;\n\nstruct _USBD_HandleTypeDef;\n    \ntypedef struct _Device_cb\n{\n  uint8_t  (*Init)             (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\n  uint8_t  (*DeInit)           (struct _USBD_HandleTypeDef *pdev , uint8_t cfgidx);\n /* Control Endpoints*/\n  uint8_t  (*Setup)            (struct _USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req);  \n  uint8_t  (*EP0_TxSent)       (struct _USBD_HandleTypeDef *pdev );    \n  uint8_t  (*EP0_RxReady)      (struct _USBD_HandleTypeDef *pdev );  \n  /* Class Specific Endpoints*/\n  uint8_t  (*DataIn)           (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \n  uint8_t  (*DataOut)          (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \n  uint8_t  (*SOF)              (struct _USBD_HandleTypeDef *pdev); \n  uint8_t  (*IsoINIncomplete)  (struct _USBD_HandleTypeDef *pdev , uint8_t epnum); \n  uint8_t  (*IsoOUTIncomplete) (struct _USBD_HandleTypeDef *pdev , uint8_t epnum);   \n\n  uint8_t  *(*GetHSConfigDescriptor)(uint16_t *length); \n  uint8_t  *(*GetFSConfigDescriptor)(uint16_t *length);   \n  uint8_t  *(*GetOtherSpeedConfigDescriptor)(uint16_t *length);\n  uint8_t  *(*GetDeviceQualifierDescriptor)(uint16_t *length);\n#if (USBD_SUPPORT_USER_STRING == 1)\n  uint8_t  *(*GetUsrStrDescriptor)(struct _USBD_HandleTypeDef *pdev ,uint8_t index,  uint16_t *length);   \n#endif  \n  \n} USBD_ClassTypeDef;\n\n/* Following USB Device Speed */\ntypedef enum \n{\n  USBD_SPEED_HIGH  = 0,\n  USBD_SPEED_FULL  = 1,\n  USBD_SPEED_LOW   = 2,  \n}USBD_SpeedTypeDef;\n\n/* Following USB Device status */\ntypedef enum {\n  USBD_OK   = 0,\n  USBD_BUSY,\n  USBD_FAIL,\n}USBD_StatusTypeDef;\n\n/* USB Device descriptors structure */\ntypedef struct\n{\n  uint8_t  *(*GetDeviceDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \n  uint8_t  *(*GetLangIDStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \n  uint8_t  *(*GetManufacturerStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \n  uint8_t  *(*GetProductStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \n  uint8_t  *(*GetSerialStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \n  uint8_t  *(*GetConfigurationStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length);  \n  uint8_t  *(*GetInterfaceStrDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \n#if (USBD_LPM_ENABLED == 1)\n  uint8_t  *(*GetBOSDescriptor)( USBD_SpeedTypeDef speed , uint16_t *length); \n#endif  \n} USBD_DescriptorsTypeDef;\n\n/* USB Device handle structure */\ntypedef struct\n{ \n  uint32_t                status;\n  uint32_t                total_length;    \n  uint32_t                rem_length; \n  uint32_t                maxpacket;   \n} USBD_EndpointTypeDef;\n\n/* USB Device handle structure */\ntypedef struct _USBD_HandleTypeDef\n{\n  uint8_t                 id;\n  uint32_t                dev_config;\n  uint32_t                dev_default_config;\n  uint32_t                dev_config_status; \n  USBD_SpeedTypeDef       dev_speed; \n  USBD_EndpointTypeDef    ep_in[15];\n  USBD_EndpointTypeDef    ep_out[15];  \n  uint32_t                ep0_state;  \n  uint32_t                ep0_data_len;     \n  uint8_t                 dev_state;\n  uint8_t                 dev_old_state;\n  uint8_t                 dev_address;\n  uint8_t                 dev_connection_status;  \n  uint8_t                 dev_test_mode;\n  uint32_t                dev_remote_wakeup;\n\n  USBD_SetupReqTypedef    request;\n  USBD_DescriptorsTypeDef *pDesc;\n  USBD_ClassTypeDef       *pClass;\n  void                    *pClassData;  \n  void                    *pUserData;    \n  void                    *pData;    \n} USBD_HandleTypeDef;\n\n/**\n  * @}\n  */ \n\n\n\n/** @defgroup USBD_DEF_Exported_Macros\n  * @{\n  */ \n#define  SWAPBYTE(addr)        (((uint16_t)(*((uint8_t *)(addr)))) + \\\n                               (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))\n\n#define LOBYTE(x)  ((uint8_t)(x & 0x00FF))\n#define HIBYTE(x)  ((uint8_t)((x & 0xFF00) >>8))\n#define MIN(a, b)  (((a) < (b)) ? (a) : (b))\n#define MAX(a, b)  (((a) > (b)) ? (a) : (b))\n\n\n#if  defined ( __GNUC__ )\n  #ifndef __weak\n    #define __weak   __attribute__((weak))\n  #endif /* __weak */\n  #ifndef __packed\n    #define __packed __attribute__((__packed__))\n  #endif /* __packed */\n#endif /* __GNUC__ */\n\n\n/* In HS mode and when the DMA is used, all variables and data structures dealing\n   with the DMA during the transaction process should be 4-bytes aligned */    \n\n#if defined   (__GNUC__)        /* GNU Compiler */\n  #define __ALIGN_END    __attribute__ ((aligned (4)))\n  #define __ALIGN_BEGIN         \n#else                           \n  #define __ALIGN_END\n  #if defined   (__CC_ARM)      /* ARM Compiler */\n    #define __ALIGN_BEGIN    __align(4)  \n  #elif defined (__ICCARM__)    /* IAR Compiler */\n    #define __ALIGN_BEGIN \n  #elif defined  (__TASKING__)  /* TASKING Compiler */\n    #define __ALIGN_BEGIN    __align(4) \n  #endif /* __CC_ARM */  \n#endif /* __GNUC__ */ \n  \n\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_DEF_Exported_Variables\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_DEF_Exported_FunctionsPrototype\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_DEF_H */\n\n/**\n  * @}\n  */ \n\n/**\n* @}\n*/ \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Inc/usbd_ioreq.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_ioreq.h\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   Header file for the usbd_ioreq.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_IOREQ_H\n#define __USBD_IOREQ_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include  \"usbd_def.h\"\n#include  \"usbd_core.h\"\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n  \n/** @defgroup USBD_IOREQ\n  * @brief header file for the usbd_ioreq.c file\n  * @{\n  */ \n\n/** @defgroup USBD_IOREQ_Exported_Defines\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Exported_Types\n  * @{\n  */\n\n\n/**\n  * @}\n  */ \n\n\n\n/** @defgroup USBD_IOREQ_Exported_Macros\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_IOREQ_Exported_Variables\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype\n  * @{\n  */ \n\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \n                               uint8_t *buf,\n                               uint16_t len);\n\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \n                               uint8_t *pbuf,\n                               uint16_t len);\n\nUSBD_StatusTypeDef USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev, \n                               uint8_t *pbuf,                                 \n                               uint16_t len);\n\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \n                              uint8_t *pbuf,                                          \n                              uint16_t len);\n\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev);\n\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev);\n\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , \n                           uint8_t epnum);\n\n/**\n  * @}\n  */ \n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_IOREQ_H */\n\n/**\n  * @}\n  */ \n\n/**\n* @}\n*/ \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_core.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_core.c\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   This file provides all the USBD core functions.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_core.h\"\n\n/** @addtogroup STM32_USBD_DEVICE_LIBRARY\n* @{\n*/\n\n\n/** @defgroup USBD_CORE \n* @brief usbd core module\n* @{\n*/ \n\n/** @defgroup USBD_CORE_Private_TypesDefinitions\n* @{\n*/ \n/**\n* @}\n*/ \n\n\n/** @defgroup USBD_CORE_Private_Defines\n* @{\n*/ \n\n/**\n* @}\n*/ \n\n\n/** @defgroup USBD_CORE_Private_Macros\n* @{\n*/ \n/**\n* @}\n*/ \n\n\n\n\n/** @defgroup USBD_CORE_Private_FunctionPrototypes\n* @{\n*/ \n\n/**\n* @}\n*/ \n\n/** @defgroup USBD_CORE_Private_Variables\n* @{\n*/ \n\n/**\n* @}\n*/ \n\n/** @defgroup USBD_CORE_Private_Functions\n* @{\n*/ \n\n/**\n* @brief  USBD_Init\n*         Initializes the device stack and load the class driver\n* @param  pdev: device instance\n* @param  pdesc: Descriptor structure address\n* @param  id: Low level core index\n* @retval None\n*/\nUSBD_StatusTypeDef USBD_Init(USBD_HandleTypeDef *pdev, USBD_DescriptorsTypeDef *pdesc, uint8_t id)\n{\n  /* Check whether the USB Host handle is valid */\n  if(pdev == NULL)\n  {\n    USBD_ErrLog(\"Invalid Device handle\");\n    return USBD_FAIL; \n  }\n  \n  /* Unlink previous class*/\n  if(pdev->pClass != NULL)\n  {\n    pdev->pClass = NULL;\n  }\n  \n  /* Assign USBD Descriptors */\n  if(pdesc != NULL)\n  {\n    pdev->pDesc = pdesc;\n  }\n  \n  /* Set Device initial State */\n  pdev->dev_state  = USBD_STATE_DEFAULT;\n  pdev->id = id;\n  /* Initialize low level driver */\n  USBD_LL_Init(pdev);\n  \n  return USBD_OK; \n}\n\n/**\n* @brief  USBD_DeInit \n*         Re-Initialize th device library\n* @param  pdev: device instance\n* @retval status: status\n*/\nUSBD_StatusTypeDef USBD_DeInit(USBD_HandleTypeDef *pdev)\n{\n  /* Set Default State */\n  pdev->dev_state  = USBD_STATE_DEFAULT;\n  \n  /* Free Class Resources */\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \n  \n    /* Stop the low level driver  */\n  USBD_LL_Stop(pdev); \n  \n  /* Initialize low level driver */\n  USBD_LL_DeInit(pdev);\n  \n  return USBD_OK;\n}\n\n\n/**\n  * @brief  USBD_RegisterClass \n  *         Link class driver to Device Core.\n  * @param  pDevice : Device Handle\n  * @param  pclass: Class handle\n  * @retval USBD Status\n  */\nUSBD_StatusTypeDef  USBD_RegisterClass(USBD_HandleTypeDef *pdev, USBD_ClassTypeDef *pclass)\n{\n  USBD_StatusTypeDef   status = USBD_OK;\n  if(pclass != 0)\n  {\n    /* link the class to the USB Device handle */\n    pdev->pClass = pclass;\n    status = USBD_OK;\n  }\n  else\n  {\n    USBD_ErrLog(\"Invalid Class handle\");\n    status = USBD_FAIL; \n  }\n  \n  return status;\n}\n\n/**\n  * @brief  USBD_Start \n  *         Start the USB Device Core.\n  * @param  pdev: Device Handle\n  * @retval USBD Status\n  */\nUSBD_StatusTypeDef  USBD_Start  (USBD_HandleTypeDef *pdev)\n{\n  \n  /* Start the low level driver  */\n  USBD_LL_Start(pdev); \n  \n  return USBD_OK;  \n}\n\n/**\n  * @brief  USBD_Stop \n  *         Stop the USB Device Core.\n  * @param  pdev: Device Handle\n  * @retval USBD Status\n  */\nUSBD_StatusTypeDef  USBD_Stop   (USBD_HandleTypeDef *pdev)\n{\n  /* Free Class Resources */\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \n\n  /* Stop the low level driver  */\n  USBD_LL_Stop(pdev); \n  \n  return USBD_OK;  \n}\n\n/**\n* @brief  USBD_RunTestMode \n*         Launch test mode process\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_RunTestMode (USBD_HandleTypeDef  *pdev) \n{\n  return USBD_OK;\n}\n\n\n/**\n* @brief  USBD_SetClassConfig \n*        Configure device and start the interface\n* @param  pdev: device instance\n* @param  cfgidx: configuration index\n* @retval status\n*/\n\nUSBD_StatusTypeDef USBD_SetClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\n{\n  USBD_StatusTypeDef   ret = USBD_FAIL;\n  \n  if(pdev->pClass != NULL)\n  {\n    /* Set configuration  and Start the Class*/\n    if(pdev->pClass->Init(pdev, cfgidx) == 0)\n    {\n      ret = USBD_OK;\n    }\n  }\n  return ret; \n}\n\n/**\n* @brief  USBD_ClrClassConfig \n*         Clear current configuration\n* @param  pdev: device instance\n* @param  cfgidx: configuration index\n* @retval status: USBD_StatusTypeDef\n*/\nUSBD_StatusTypeDef USBD_ClrClassConfig(USBD_HandleTypeDef  *pdev, uint8_t cfgidx)\n{\n  /* Clear configuration  and De-initialize the Class process*/\n  pdev->pClass->DeInit(pdev, cfgidx);  \n  return USBD_OK;\n}\n\n\n/**\n* @brief  USBD_SetupStage \n*         Handle the setup stage\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_SetupStage(USBD_HandleTypeDef *pdev, uint8_t *psetup)\n{\n\n  USBD_ParseSetupRequest(&pdev->request, psetup);\n  \n  pdev->ep0_state = USBD_EP0_SETUP;\n  pdev->ep0_data_len = pdev->request.wLength;\n  \n  switch (pdev->request.bmRequest & 0x1F) \n  {\n  case USB_REQ_RECIPIENT_DEVICE:   \n    USBD_StdDevReq (pdev, &pdev->request);\n    break;\n    \n  case USB_REQ_RECIPIENT_INTERFACE:     \n    USBD_StdItfReq(pdev, &pdev->request);\n    break;\n    \n  case USB_REQ_RECIPIENT_ENDPOINT:        \n    USBD_StdEPReq(pdev, &pdev->request);   \n    break;\n    \n  default:           \n    USBD_LL_StallEP(pdev , pdev->request.bmRequest & 0x80);\n    break;\n  }  \n  return USBD_OK;  \n}\n\n/**\n* @brief  USBD_DataOutStage \n*         Handle data OUT stage\n* @param  pdev: device instance\n* @param  epnum: endpoint index\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_DataOutStage(USBD_HandleTypeDef *pdev , uint8_t epnum, uint8_t *pdata)\n{\n  USBD_EndpointTypeDef    *pep;\n  \n  if(epnum == 0) \n  {\n    pep = &pdev->ep_out[0];\n    \n    if ( pdev->ep0_state == USBD_EP0_DATA_OUT)\n    {\n      if(pep->rem_length > pep->maxpacket)\n      {\n        pep->rem_length -=  pep->maxpacket;\n       \n        USBD_CtlContinueRx (pdev, \n                            pdata,\n                            MIN(pep->rem_length ,pep->maxpacket));\n      }\n      else\n      {\n        if((pdev->pClass->EP0_RxReady != NULL)&&\n           (pdev->dev_state == USBD_STATE_CONFIGURED))\n        {\n          pdev->pClass->EP0_RxReady(pdev); \n        }\n        USBD_CtlSendStatus(pdev);\n      }\n    }\n  }\n  else if((pdev->pClass->DataOut != NULL)&&\n          (pdev->dev_state == USBD_STATE_CONFIGURED))\n  {\n    pdev->pClass->DataOut(pdev, epnum); \n  }  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_DataInStage \n*         Handle data in stage\n* @param  pdev: device instance\n* @param  epnum: endpoint index\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_DataInStage(USBD_HandleTypeDef *pdev ,uint8_t epnum, uint8_t *pdata)\n{\n  USBD_EndpointTypeDef    *pep;\n    \n  if(epnum == 0) \n  {\n    pep = &pdev->ep_in[0];\n    \n    if ( pdev->ep0_state == USBD_EP0_DATA_IN)\n    {\n      if(pep->rem_length > pep->maxpacket)\n      {\n        pep->rem_length -=  pep->maxpacket;\n        \n        USBD_CtlContinueSendData (pdev, \n                                  pdata, \n                                  pep->rem_length);\n        \n        /* Prepare endpoint for premature end of transfer */\n        USBD_LL_PrepareReceive (pdev,\n                                0,\n                                NULL,\n                                0);  \n      }\n      else\n      { /* last packet is MPS multiple, so send ZLP packet */\n        if((pep->total_length % pep->maxpacket == 0) &&\n           (pep->total_length >= pep->maxpacket) &&\n             (pep->total_length < pdev->ep0_data_len ))\n        {\n          \n          USBD_CtlContinueSendData(pdev , NULL, 0);\n          pdev->ep0_data_len = 0;\n          \n        /* Prepare endpoint for premature end of transfer */\n        USBD_LL_PrepareReceive (pdev,\n                                0,\n                                NULL,\n                                0);\n        }\n        else\n        {\n          if((pdev->pClass->EP0_TxSent != NULL)&&\n             (pdev->dev_state == USBD_STATE_CONFIGURED))\n          {\n            pdev->pClass->EP0_TxSent(pdev); \n          }          \n          USBD_CtlReceiveStatus(pdev);\n        }\n      }\n    }\n    if (pdev->dev_test_mode == 1)\n    {\n      USBD_RunTestMode(pdev); \n      pdev->dev_test_mode = 0;\n    }\n  }\n  else if((pdev->pClass->DataIn != NULL)&& \n          (pdev->dev_state == USBD_STATE_CONFIGURED))\n  {\n    pdev->pClass->DataIn(pdev, epnum); \n  }  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_LL_Reset \n*         Handle Reset event\n* @param  pdev: device instance\n* @retval status\n*/\n\nUSBD_StatusTypeDef USBD_LL_Reset(USBD_HandleTypeDef  *pdev)\n{\n  /* Open EP0 OUT */\n  USBD_LL_OpenEP(pdev,\n              0x00,\n              USBD_EP_TYPE_CTRL,\n              USB_MAX_EP0_SIZE);\n  \n  pdev->ep_out[0].maxpacket = USB_MAX_EP0_SIZE;\n  \n  /* Open EP0 IN */\n  USBD_LL_OpenEP(pdev,\n              0x80,\n              USBD_EP_TYPE_CTRL,\n              USB_MAX_EP0_SIZE);\n  \n  pdev->ep_in[0].maxpacket = USB_MAX_EP0_SIZE;\n  /* Upon Reset call user call back */\n  pdev->dev_state = USBD_STATE_DEFAULT;\n  \n  if (pdev->pClassData) \n    pdev->pClass->DeInit(pdev, pdev->dev_config);  \n \n  \n  return USBD_OK;\n}\n\n\n\n\n/**\n* @brief  USBD_LL_Reset \n*         Handle Reset event\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_SetSpeed(USBD_HandleTypeDef  *pdev, USBD_SpeedTypeDef speed)\n{\n  pdev->dev_speed = speed;\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_Suspend \n*         Handle Suspend event\n* @param  pdev: device instance\n* @retval status\n*/\n\nUSBD_StatusTypeDef USBD_LL_Suspend(USBD_HandleTypeDef  *pdev)\n{\n  pdev->dev_old_state =  pdev->dev_state;\n  pdev->dev_state  = USBD_STATE_SUSPENDED;\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_Resume \n*         Handle Resume event\n* @param  pdev: device instance\n* @retval status\n*/\n\nUSBD_StatusTypeDef USBD_LL_Resume(USBD_HandleTypeDef  *pdev)\n{\n  pdev->dev_state = pdev->dev_old_state;  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_SOF \n*         Handle SOF event\n* @param  pdev: device instance\n* @retval status\n*/\n\nUSBD_StatusTypeDef USBD_LL_SOF(USBD_HandleTypeDef  *pdev)\n{\n  if(pdev->dev_state == USBD_STATE_CONFIGURED)\n  {\n    if(pdev->pClass->SOF != NULL)\n    {\n      pdev->pClass->SOF(pdev);\n    }\n  }\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_IsoINIncomplete \n*         Handle iso in incomplete event\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_IsoINIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\n{\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_IsoOUTIncomplete \n*         Handle iso out incomplete event\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_IsoOUTIncomplete(USBD_HandleTypeDef  *pdev, uint8_t epnum)\n{\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_DevConnected \n*         Handle device connection event\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_DevConnected(USBD_HandleTypeDef  *pdev)\n{\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_DevDisconnected \n*         Handle device disconnection event\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef USBD_LL_DevDisconnected(USBD_HandleTypeDef  *pdev)\n{\n  /* Free Class Resources */\n  pdev->dev_state = USBD_STATE_DEFAULT;\n  pdev->pClass->DeInit(pdev, pdev->dev_config);  \n   \n  return USBD_OK;\n}\n/**\n* @}\n*/ \n\n\n/**\n* @}\n*/ \n\n\n/**\n* @}\n*/ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ctlreq.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_req.c\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015 \n  * @brief   This file provides the standard USB requests following chapter 9.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_ctlreq.h\"\n#include \"usbd_ioreq.h\"\n\n\n/** @addtogroup STM32_USBD_STATE_DEVICE_LIBRARY\n  * @{\n  */\n\n\n/** @defgroup USBD_REQ \n  * @brief USB standard requests module\n  * @{\n  */ \n\n/** @defgroup USBD_REQ_Private_TypesDefinitions\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Private_Defines\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Private_Macros\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Private_Variables\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Private_FunctionPrototypes\n  * @{\n  */ \nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \n                               USBD_SetupReqTypedef *req);\n\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req);\n\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req);\n\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req);\n\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req);\n\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req);\n\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req);\n\nstatic uint8_t USBD_GetLen(uint8_t *buf);\n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_REQ_Private_Functions\n  * @{\n  */ \n\n\n/**\n* @brief  USBD_StdDevReq\n*         Handle standard usb device requests\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_StdDevReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\n{\n  USBD_StatusTypeDef ret = USBD_OK;  \n  \n  switch (req->bRequest) \n  {\n  case USB_REQ_GET_DESCRIPTOR: \n    \n    USBD_GetDescriptor (pdev, req) ;\n    break;\n    \n  case USB_REQ_SET_ADDRESS:                      \n    USBD_SetAddress(pdev, req);\n    break;\n    \n  case USB_REQ_SET_CONFIGURATION:                    \n    USBD_SetConfig (pdev , req);\n    break;\n    \n  case USB_REQ_GET_CONFIGURATION:                 \n    USBD_GetConfig (pdev , req);\n    break;\n    \n  case USB_REQ_GET_STATUS:                                  \n    USBD_GetStatus (pdev , req);\n    break;\n    \n    \n  case USB_REQ_SET_FEATURE:   \n    USBD_SetFeature (pdev , req);    \n    break;\n    \n  case USB_REQ_CLEAR_FEATURE:                                   \n    USBD_ClrFeature (pdev , req);\n    break;\n    \n  default:  \n    USBD_CtlError(pdev , req);\n    break;\n  }\n  \n  return ret;\n}\n\n/**\n* @brief  USBD_StdItfReq\n*         Handle standard usb interface requests\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_StdItfReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\n{\n  USBD_StatusTypeDef ret = USBD_OK; \n  \n  switch (pdev->dev_state) \n  {\n  case USBD_STATE_CONFIGURED:\n    \n    if (LOBYTE(req->wIndex) <= USBD_MAX_NUM_INTERFACES) \n    {\n      pdev->pClass->Setup (pdev, req); \n      \n      if((req->wLength == 0)&& (ret == USBD_OK))\n      {\n         USBD_CtlSendStatus(pdev);\n      }\n    } \n    else \n    {                                               \n       USBD_CtlError(pdev , req);\n    }\n    break;\n    \n  default:\n     USBD_CtlError(pdev , req);\n    break;\n  }\n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_StdEPReq\n*         Handle standard usb endpoint requests\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_StdEPReq (USBD_HandleTypeDef *pdev , USBD_SetupReqTypedef  *req)\n{\n  \n  uint8_t   ep_addr;\n  USBD_StatusTypeDef ret = USBD_OK; \n  USBD_EndpointTypeDef   *pep;\n  ep_addr  = LOBYTE(req->wIndex);   \n  \n  /* Check if it is a class request */\n  if ((req->bmRequest & 0x60) == 0x20)\n  {\n    pdev->pClass->Setup (pdev, req);\n    \n    return USBD_OK;\n  }\n  \n  switch (req->bRequest) \n  {\n    \n  case USB_REQ_SET_FEATURE :\n    \n    switch (pdev->dev_state) \n    {\n    case USBD_STATE_ADDRESSED:          \n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \n      {\n        USBD_LL_StallEP(pdev , ep_addr);\n      }\n      break;\t\n      \n    case USBD_STATE_CONFIGURED:   \n      if (req->wValue == USB_FEATURE_EP_HALT)\n      {\n        if ((ep_addr != 0x00) && (ep_addr != 0x80)) \n        { \n          USBD_LL_StallEP(pdev , ep_addr);\n          \n        }\n      }\n      pdev->pClass->Setup (pdev, req);   \n      USBD_CtlSendStatus(pdev);\n      \n      break;\n      \n    default:                         \n      USBD_CtlError(pdev , req);\n      break;    \n    }\n    break;\n    \n  case USB_REQ_CLEAR_FEATURE :\n    \n    switch (pdev->dev_state) \n    {\n    case USBD_STATE_ADDRESSED:          \n      if ((ep_addr != 0x00) && (ep_addr != 0x80)) \n      {\n        USBD_LL_StallEP(pdev , ep_addr);\n      }\n      break;\t\n      \n    case USBD_STATE_CONFIGURED:   \n      if (req->wValue == USB_FEATURE_EP_HALT)\n      {\n        if ((ep_addr & 0x7F) != 0x00) \n        {        \n          USBD_LL_ClearStallEP(pdev , ep_addr);\n          pdev->pClass->Setup (pdev, req);\n        }\n        USBD_CtlSendStatus(pdev);\n      }\n      break;\n      \n    default:                         \n      USBD_CtlError(pdev , req);\n      break;    \n    }\n    break;\n    \n  case USB_REQ_GET_STATUS:                  \n    switch (pdev->dev_state) \n    {\n    case USBD_STATE_ADDRESSED:          \n      if ((ep_addr & 0x7F) != 0x00) \n      {\n        USBD_LL_StallEP(pdev , ep_addr);\n      }\n      break;\t\n      \n    case USBD_STATE_CONFIGURED:\n      pep = ((ep_addr & 0x80) == 0x80) ? &pdev->ep_in[ep_addr & 0x7F]:\\\n                                         &pdev->ep_out[ep_addr & 0x7F];\n      if(USBD_LL_IsStallEP(pdev, ep_addr))\n      {\n        pep->status = 0x0001;     \n      }\n      else\n      {\n        pep->status = 0x0000;  \n      }\n      \n      USBD_CtlSendData (pdev,\n                        (uint8_t *)&pep->status,\n                        2);\n      break;\n      \n    default:                         \n      USBD_CtlError(pdev , req);\n      break;\n    }\n    break;\n    \n  default:\n    break;\n  }\n  return ret;\n}\n/**\n* @brief  USBD_GetDescriptor\n*         Handle Get Descriptor requests\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_GetDescriptor(USBD_HandleTypeDef *pdev , \n                               USBD_SetupReqTypedef *req)\n{\n  uint16_t len;\n  uint8_t *pbuf;\n  \n    \n  switch (req->wValue >> 8)\n  { \n#if (USBD_LPM_ENABLED == 1)\n  case USB_DESC_TYPE_BOS:\n    pbuf = pdev->pDesc->GetBOSDescriptor(pdev->dev_speed, &len);\n    break;\n#endif    \n  case USB_DESC_TYPE_DEVICE:\n    pbuf = pdev->pDesc->GetDeviceDescriptor(pdev->dev_speed, &len);\n    break;\n    \n  case USB_DESC_TYPE_CONFIGURATION:     \n    if(pdev->dev_speed == USBD_SPEED_HIGH )   \n    {\n      pbuf   = (uint8_t *)pdev->pClass->GetHSConfigDescriptor(&len);\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\n    }\n    else\n    {\n      pbuf   = (uint8_t *)pdev->pClass->GetFSConfigDescriptor(&len);\n      pbuf[1] = USB_DESC_TYPE_CONFIGURATION;\n    }\n    break;\n    \n  case USB_DESC_TYPE_STRING:\n    switch ((uint8_t)(req->wValue))\n    {\n    case USBD_IDX_LANGID_STR:\n     pbuf = pdev->pDesc->GetLangIDStrDescriptor(pdev->dev_speed, &len);        \n      break;\n      \n    case USBD_IDX_MFC_STR:\n      pbuf = pdev->pDesc->GetManufacturerStrDescriptor(pdev->dev_speed, &len);\n      break;\n      \n    case USBD_IDX_PRODUCT_STR:\n      pbuf = pdev->pDesc->GetProductStrDescriptor(pdev->dev_speed, &len);\n      break;\n      \n    case USBD_IDX_SERIAL_STR:\n      pbuf = pdev->pDesc->GetSerialStrDescriptor(pdev->dev_speed, &len);\n      break;\n      \n    case USBD_IDX_CONFIG_STR:\n      pbuf = pdev->pDesc->GetConfigurationStrDescriptor(pdev->dev_speed, &len);\n      break;\n      \n    case USBD_IDX_INTERFACE_STR:\n      pbuf = pdev->pDesc->GetInterfaceStrDescriptor(pdev->dev_speed, &len);\n      break;\n      \n    default:\n#if (USBD_SUPPORT_USER_STRING == 1)\n      pbuf = pdev->pClass->GetUsrStrDescriptor(pdev, (req->wValue) , &len);\n      break;\n#else      \n       USBD_CtlError(pdev , req);\n      return;\n#endif   \n    }\n    break;\n  case USB_DESC_TYPE_DEVICE_QUALIFIER:                   \n\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \n    {\n      pbuf   = (uint8_t *)pdev->pClass->GetDeviceQualifierDescriptor(&len);\n      break;\n    }\n    else\n    {\n      USBD_CtlError(pdev , req);\n      return;\n    } \n\n  case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:\n    if(pdev->dev_speed == USBD_SPEED_HIGH  )   \n    {\n      pbuf   = (uint8_t *)pdev->pClass->GetOtherSpeedConfigDescriptor(&len);\n      pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION;\n      break; \n    }\n    else\n    {\n      USBD_CtlError(pdev , req);\n      return;\n    }\n\n  default: \n     USBD_CtlError(pdev , req);\n    return;\n  }\n  \n  if((len != 0)&& (req->wLength != 0))\n  {\n    \n    len = MIN(len , req->wLength);\n    \n    USBD_CtlSendData (pdev, \n                      pbuf,\n                      len);\n  }\n  \n}\n\n/**\n* @brief  USBD_SetAddress\n*         Set device address\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_SetAddress(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req)\n{\n  uint8_t  dev_addr; \n  \n  if ((req->wIndex == 0) && (req->wLength == 0)) \n  {\n    dev_addr = (uint8_t)(req->wValue) & 0x7F;     \n    \n    if (pdev->dev_state == USBD_STATE_CONFIGURED) \n    {\n      USBD_CtlError(pdev , req);\n    } \n    else \n    {\n      pdev->dev_address = dev_addr;\n      USBD_LL_SetUSBAddress(pdev, dev_addr);               \n      USBD_CtlSendStatus(pdev);                         \n      \n      if (dev_addr != 0) \n      {\n        pdev->dev_state  = USBD_STATE_ADDRESSED;\n      } \n      else \n      {\n        pdev->dev_state  = USBD_STATE_DEFAULT; \n      }\n    }\n  } \n  else \n  {\n     USBD_CtlError(pdev , req);                        \n  } \n}\n\n/**\n* @brief  USBD_SetConfig\n*         Handle Set device configuration request\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_SetConfig(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req)\n{\n  \n  static uint8_t  cfgidx;\n  \n  cfgidx = (uint8_t)(req->wValue);                 \n  \n  if (cfgidx > USBD_MAX_NUM_CONFIGURATION ) \n  {            \n     USBD_CtlError(pdev , req);                              \n  } \n  else \n  {\n    switch (pdev->dev_state) \n    {\n    case USBD_STATE_ADDRESSED:\n      if (cfgidx) \n      {                                \t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\t\t\t   \t\t\t\t\n        pdev->dev_config = cfgidx;\n        pdev->dev_state = USBD_STATE_CONFIGURED;\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\n        {\n          USBD_CtlError(pdev , req);  \n          return;\n        }\n        USBD_CtlSendStatus(pdev);\n      }\n      else \n      {\n         USBD_CtlSendStatus(pdev);\n      }\n      break;\n      \n    case USBD_STATE_CONFIGURED:\n      if (cfgidx == 0) \n      {                           \n        pdev->dev_state = USBD_STATE_ADDRESSED;\n        pdev->dev_config = cfgidx;          \n        USBD_ClrClassConfig(pdev , cfgidx);\n        USBD_CtlSendStatus(pdev);\n        \n      } \n      else  if (cfgidx != pdev->dev_config) \n      {\n        /* Clear old configuration */\n        USBD_ClrClassConfig(pdev , pdev->dev_config);\n        \n        /* set new configuration */\n        pdev->dev_config = cfgidx;\n        if(USBD_SetClassConfig(pdev , cfgidx) == USBD_FAIL)\n        {\n          USBD_CtlError(pdev , req);  \n          return;\n        }\n        USBD_CtlSendStatus(pdev);\n      }\n      else\n      {\n        USBD_CtlSendStatus(pdev);\n      }\n      break;\n      \n    default:\t\t\t\t\t\n       USBD_CtlError(pdev , req);                     \n      break;\n    }\n  }\n}\n\n/**\n* @brief  USBD_GetConfig\n*         Handle Get device configuration request\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_GetConfig(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req)\n{\n\n  if (req->wLength != 1) \n  {                   \n     USBD_CtlError(pdev , req);\n  }\n  else \n  {\n    switch (pdev->dev_state )  \n    {\n    case USBD_STATE_ADDRESSED:                     \n      pdev->dev_default_config = 0;\n      USBD_CtlSendData (pdev, \n                        (uint8_t *)&pdev->dev_default_config,\n                        1);\n      break;\n      \n    case USBD_STATE_CONFIGURED:   \n      \n      USBD_CtlSendData (pdev, \n                        (uint8_t *)&pdev->dev_config,\n                        1);\n      break;\n      \n    default:\n       USBD_CtlError(pdev , req);\n      break;\n    }\n  }\n}\n\n/**\n* @brief  USBD_GetStatus\n*         Handle Get Status request\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_GetStatus(USBD_HandleTypeDef *pdev , \n                           USBD_SetupReqTypedef *req)\n{\n  \n    \n  switch (pdev->dev_state) \n  {\n  case USBD_STATE_ADDRESSED:\n  case USBD_STATE_CONFIGURED:\n    \n#if ( USBD_SELF_POWERED == 1)\n    pdev->dev_config_status = USB_CONFIG_SELF_POWERED;                                  \n#else\n    pdev->dev_config_status = 0;                                   \n#endif\n                      \n    if (pdev->dev_remote_wakeup) \n    {\n       pdev->dev_config_status |= USB_CONFIG_REMOTE_WAKEUP;                                \n    }\n    \n    USBD_CtlSendData (pdev, \n                      (uint8_t *)& pdev->dev_config_status,\n                      2);\n    break;\n    \n  default :\n    USBD_CtlError(pdev , req);                        \n    break;\n  }\n}\n\n\n/**\n* @brief  USBD_SetFeature\n*         Handle Set device feature request\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_SetFeature(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req)\n{\n\n  if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)\n  {\n    pdev->dev_remote_wakeup = 1;  \n    pdev->pClass->Setup (pdev, req);   \n    USBD_CtlSendStatus(pdev);\n  }\n\n}\n\n\n/**\n* @brief  USBD_ClrFeature\n*         Handle clear device feature request\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval status\n*/\nstatic void USBD_ClrFeature(USBD_HandleTypeDef *pdev , \n                            USBD_SetupReqTypedef *req)\n{\n  switch (pdev->dev_state)\n  {\n  case USBD_STATE_ADDRESSED:\n  case USBD_STATE_CONFIGURED:\n    if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) \n    {\n      pdev->dev_remote_wakeup = 0; \n      pdev->pClass->Setup (pdev, req);   \n      USBD_CtlSendStatus(pdev);\n    }\n    break;\n    \n  default :\n     USBD_CtlError(pdev , req);\n    break;\n  }\n}\n\n/**\n* @brief  USBD_ParseSetupRequest \n*         Copy buffer into setup structure\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval None\n*/\n\nvoid USBD_ParseSetupRequest(USBD_SetupReqTypedef *req, uint8_t *pdata)\n{\n  req->bmRequest     = *(uint8_t *)  (pdata);\n  req->bRequest      = *(uint8_t *)  (pdata +  1);\n  req->wValue        = SWAPBYTE      (pdata +  2);\n  req->wIndex        = SWAPBYTE      (pdata +  4);\n  req->wLength       = SWAPBYTE      (pdata +  6);\n\n}\n\n/**\n* @brief  USBD_CtlError \n*         Handle USB low level Error\n* @param  pdev: device instance\n* @param  req: usb request\n* @retval None\n*/\n\nvoid USBD_CtlError( USBD_HandleTypeDef *pdev ,\n                            USBD_SetupReqTypedef *req)\n{\n  USBD_LL_StallEP(pdev , 0x80);\n  USBD_LL_StallEP(pdev , 0);\n}\n\n\n/**\n  * @brief  USBD_GetString\n  *         Convert Ascii string into unicode one\n  * @param  desc : descriptor buffer\n  * @param  unicode : Formatted string buffer (unicode)\n  * @param  len : descriptor length\n  * @retval None\n  */\nvoid USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)\n{\n  uint8_t idx = 0;\n  \n  if (desc != NULL) \n  {\n    *len =  USBD_GetLen(desc) * 2 + 2;    \n    unicode[idx++] = *len;\n    unicode[idx++] =  USB_DESC_TYPE_STRING;\n    \n    while (*desc != '\\0') \n    {\n      unicode[idx++] = *desc++;\n      unicode[idx++] =  0x00;\n    }\n  } \n}\n\n/**\n  * @brief  USBD_GetLen\n  *         return the string length\n   * @param  buf : pointer to the ascii string buffer\n  * @retval string length\n  */\nstatic uint8_t USBD_GetLen(uint8_t *buf)\n{\n    uint8_t  len = 0;\n\n    while (*buf != '\\0') \n    {\n        len++;\n        buf++;\n    }\n\n    return len;\n}\n/**\n  * @}\n  */ \n\n\n/**\n  * @}\n  */ \n\n\n/**\n  * @}\n  */ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/ST/STM32_USB_Device_Library/Core/Src/usbd_ioreq.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usbd_ioreq.c\n  * @author  MCD Application Team\n  * @version V2.4.2\n  * @date    11-December-2015\n  * @brief   This file provides the IO requests APIs for control endpoints.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>\n  *\n  * Licensed under MCD-ST Liberty SW License Agreement V2, (the \"License\");\n  * You may not use this file except in compliance with the License.\n  * You may obtain a copy of the License at:\n  *\n  *        http://www.st.com/software_license_agreement_liberty_v2\n  *\n  * Unless required by applicable law or agreed to in writing, software \n  * distributed under the License is distributed on an \"AS IS\" BASIS, \n  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n  * See the License for the specific language governing permissions and\n  * limitations under the License.\n  *\n  ******************************************************************************\n  */ \n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_ioreq.h\"\n\n/** @addtogroup STM32_USB_DEVICE_LIBRARY\n  * @{\n  */\n\n\n/** @defgroup USBD_IOREQ \n  * @brief control I/O requests module\n  * @{\n  */ \n\n/** @defgroup USBD_IOREQ_Private_TypesDefinitions\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Private_Defines\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Private_Macros\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Private_Variables\n  * @{\n  */ \n\n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Private_FunctionPrototypes\n  * @{\n  */ \n/**\n  * @}\n  */ \n\n\n/** @defgroup USBD_IOREQ_Private_Functions\n  * @{\n  */ \n\n/**\n* @brief  USBD_CtlSendData\n*         send data on the ctl pipe\n* @param  pdev: device instance\n* @param  buff: pointer to data buffer\n* @param  len: length of data to be sent\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlSendData (USBD_HandleTypeDef  *pdev, \n                               uint8_t *pbuf,\n                               uint16_t len)\n{\n  /* Set EP0 State */\n  pdev->ep0_state          = USBD_EP0_DATA_IN;                                      \n  pdev->ep_in[0].total_length = len;\n  pdev->ep_in[0].rem_length   = len;\n /* Start the transfer */\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);  \n  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_CtlContinueSendData\n*         continue sending data on the ctl pipe\n* @param  pdev: device instance\n* @param  buff: pointer to data buffer\n* @param  len: length of data to be sent\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlContinueSendData (USBD_HandleTypeDef  *pdev, \n                                       uint8_t *pbuf,\n                                       uint16_t len)\n{\n /* Start the next transfer */\n  USBD_LL_Transmit (pdev, 0x00, pbuf, len);   \n  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_CtlPrepareRx\n*         receive data on the ctl pipe\n* @param  pdev: device instance\n* @param  buff: pointer to data buffer\n* @param  len: length of data to be received\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlPrepareRx (USBD_HandleTypeDef  *pdev,\n                                  uint8_t *pbuf,                                  \n                                  uint16_t len)\n{\n  /* Set EP0 State */\n  pdev->ep0_state = USBD_EP0_DATA_OUT; \n  pdev->ep_out[0].total_length = len;\n  pdev->ep_out[0].rem_length   = len;\n  /* Start the transfer */\n  USBD_LL_PrepareReceive (pdev,\n                          0,\n                          pbuf,\n                         len);\n  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_CtlContinueRx\n*         continue receive data on the ctl pipe\n* @param  pdev: device instance\n* @param  buff: pointer to data buffer\n* @param  len: length of data to be received\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlContinueRx (USBD_HandleTypeDef  *pdev, \n                                          uint8_t *pbuf,                                          \n                                          uint16_t len)\n{\n\n  USBD_LL_PrepareReceive (pdev,\n                          0,                     \n                          pbuf,                         \n                          len);\n  return USBD_OK;\n}\n/**\n* @brief  USBD_CtlSendStatus\n*         send zero lzngth packet on the ctl pipe\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlSendStatus (USBD_HandleTypeDef  *pdev)\n{\n\n  /* Set EP0 State */\n  pdev->ep0_state = USBD_EP0_STATUS_IN;\n  \n /* Start the transfer */\n  USBD_LL_Transmit (pdev, 0x00, NULL, 0);   \n  \n  return USBD_OK;\n}\n\n/**\n* @brief  USBD_CtlReceiveStatus\n*         receive zero lzngth packet on the ctl pipe\n* @param  pdev: device instance\n* @retval status\n*/\nUSBD_StatusTypeDef  USBD_CtlReceiveStatus (USBD_HandleTypeDef  *pdev)\n{\n  /* Set EP0 State */\n  pdev->ep0_state = USBD_EP0_STATUS_OUT; \n  \n /* Start the transfer */  \n  USBD_LL_PrepareReceive ( pdev,\n                    0,\n                    NULL,\n                    0);  \n\n  return USBD_OK;\n}\n\n\n/**\n* @brief  USBD_GetRxCount\n*         returns the received data length\n* @param  pdev: device instance\n* @param  ep_addr: endpoint address\n* @retval Rx Data blength\n*/\nuint16_t  USBD_GetRxCount (USBD_HandleTypeDef  *pdev , uint8_t ep_addr)\n{\n  return USBD_LL_GetRxDataSize(pdev, ep_addr);\n}\n\n/**\n  * @}\n  */ \n\n\n/**\n  * @}\n  */ \n\n\n/**\n  * @}\n  */ \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os.h",
    "content": "/*\n * Copyright (c) 2013-2019 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n * ----------------------------------------------------------------------\n *\n * $Date:        10. January 2017\n * $Revision:    V2.1.0\n *\n * Project:      CMSIS-RTOS API\n * Title:        cmsis_os.h FreeRTOS header file\n *\n * Version 0.02\n *    Initial Proposal Phase\n * Version 0.03\n *    osKernelStart added, optional feature: main started as thread\n *    osSemaphores have standard behavior\n *    osTimerCreate does not start the timer, added osTimerStart\n *    osThreadPass is renamed to osThreadYield\n * Version 1.01\n *    Support for C++ interface\n *     - const attribute removed from the osXxxxDef_t typedefs\n *     - const attribute added to the osXxxxDef macros\n *    Added: osTimerDelete, osMutexDelete, osSemaphoreDelete\n *    Added: osKernelInitialize\n * Version 1.02\n *    Control functions for short timeouts in microsecond resolution:\n *    Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec\n *    Removed: osSignalGet \n * Version 2.0.0\n *    OS objects creation without macros (dynamic creation and resource allocation):\n *     - added: osXxxxNew functions which replace osXxxxCreate\n *     - added: osXxxxAttr_t structures\n *     - deprecated: osXxxxCreate functions, osXxxxDef_t structures\n *     - deprecated: osXxxxDef and osXxxx macros\n *    osStatus codes simplified and renamed to osStatus_t\n *    osEvent return structure deprecated\n *    Kernel:\n *     - added: osKernelInfo_t and osKernelGetInfo\n *     - added: osKernelState_t and osKernelGetState (replaces osKernelRunning)\n *     - added: osKernelLock, osKernelUnlock\n *     - added: osKernelSuspend, osKernelResume\n *     - added: osKernelGetTickCount, osKernelGetTickFreq\n *     - renamed osKernelSysTick to osKernelGetSysTimerCount\n *     - replaced osKernelSysTickFrequency with osKernelGetSysTimerFreq\n *     - deprecated osKernelSysTickMicroSec\n *    Thread:\n *     - extended number of thread priorities\n *     - renamed osPrioriry to osPrioriry_t\n *     - replaced osThreadCreate with osThreadNew\n *     - added: osThreadGetName\n *     - added: osThreadState_t and osThreadGetState\n *     - added: osThreadGetStackSize, osThreadGetStackSpace\n *     - added: osThreadSuspend, osThreadResume\n *     - added: osThreadJoin, osThreadDetach, osThreadExit\n *     - added: osThreadGetCount, osThreadEnumerate\n *     - added: Thread Flags (moved from Signals) \n *    Signals:\n *     - renamed osSignals to osThreadFlags (moved to Thread Flags)\n *     - changed return value of Set/Clear/Wait functions\n *     - Clear function limited to current running thread\n *     - extended Wait function (options)\n *     - added: osThreadFlagsGet\n *    Event Flags:\n *     - added new independent object for handling Event Flags\n *    Delay and Wait functions:\n *     - added: osDelayUntil\n *     - deprecated: osWait\n *    Timer:\n *     - replaced osTimerCreate with osTimerNew\n *     - added: osTimerGetName, osTimerIsRunning\n *    Mutex:\n *     - extended: attributes (Recursive, Priority Inherit, Robust)\n *     - replaced osMutexCreate with osMutexNew\n *     - renamed osMutexWait to osMutexAcquire\n *     - added: osMutexGetName, osMutexGetOwner\n *    Semaphore:\n *     - extended: maximum and initial token count\n *     - replaced osSemaphoreCreate with osSemaphoreNew\n *     - renamed osSemaphoreWait to osSemaphoreAcquire (changed return value)\n *     - added: osSemaphoreGetName, osSemaphoreGetCount\n *    Memory Pool:\n *     - using osMemoryPool prefix instead of osPool\n *     - replaced osPoolCreate with osMemoryPoolNew\n *     - extended osMemoryPoolAlloc (timeout)\n *     - added: osMemoryPoolGetName\n *     - added: osMemoryPoolGetCapacity, osMemoryPoolGetBlockSize\n *     - added: osMemoryPoolGetCount, osMemoryPoolGetSpace\n *     - added: osMemoryPoolDelete\n *     - deprecated: osPoolCAlloc\n *    Message Queue:\n *     - extended: fixed size message instead of a single 32-bit value\n *     - using osMessageQueue prefix instead of osMessage\n *     - replaced osMessageCreate with osMessageQueueNew\n *     - updated: osMessageQueuePut, osMessageQueueGet\n *     - added: osMessageQueueGetName\n *     - added: osMessageQueueGetCapacity, osMessageQueueGetMsgSize\n *     - added: osMessageQueueGetCount, osMessageQueueGetSpace\n *     - added: osMessageQueueReset, osMessageQueueDelete\n *    Mail Queue: \n *     - deprecated (superseded by extended Message Queue functionality)\n * Version 2.1.0\n *    Support for critical and uncritical sections (nesting safe):\n *    - updated: osKernelLock, osKernelUnlock\n *    - added: osKernelRestoreLock\n *    Updated Thread and Event Flags:\n *    - changed flags parameter and return type from int32_t to uint32_t\n *---------------------------------------------------------------------------*/\n \n#ifndef CMSIS_OS_H_\n#define CMSIS_OS_H_\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#define RTOS_ID_n             ((tskKERNEL_VERSION_MAJOR << 16) | (tskKERNEL_VERSION_MINOR))\n#define RTOS_ID_s             (\"FreeRTOS \" tskKERNEL_VERSION_NUMBER)\n\n#define osCMSIS               0x20001U  ///< API version (main[31:16].sub[15:0])\n\n#define osCMSIS_FreeRTOS      RTOS_ID_n ///< RTOS identification and version (main[31:16].sub[15:0])\n \n#define osKernelSystemId      RTOS_ID_s ///< RTOS identification string\n \n#define osFeature_MainThread  0         ///< main thread      1=main can be thread, 0=not available\n#define osFeature_Signals     24U       ///< maximum number of Signal Flags available per thread\n#define osFeature_Semaphore   65535U    ///< maximum count for \\ref osSemaphoreCreate function\n#define osFeature_Wait        0         ///< osWait function: 1=available, 0=not available\n#define osFeature_SysTick     1         ///< osKernelSysTick functions: 1=available, 0=not available\n#define osFeature_Pool        0         ///< Memory Pools:    1=available, 0=not available\n#define osFeature_MessageQ    1         ///< Message Queues:  1=available, 0=not available\n#define osFeature_MailQ       0         ///< Mail Queues:     1=available, 0=not available\n \n#if   defined(__CC_ARM)\n#define os_InRegs __value_in_regs\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define os_InRegs __attribute__((value_in_regs))\n#else\n#define os_InRegs\n#endif\n \n#include \"cmsis_os2.h\"\n \n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n \n \n// ==== Enumerations, structures, defines ====\n \n/// Priority values.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osPriorityIdle          = -3,         ///< Priority: idle (lowest)\n  osPriorityLow           = -2,         ///< Priority: low\n  osPriorityBelowNormal   = -1,         ///< Priority: below normal\n  osPriorityNormal        =  0,         ///< Priority: normal (default)\n  osPriorityAboveNormal   = +1,         ///< Priority: above normal\n  osPriorityHigh          = +2,         ///< Priority: high\n  osPriorityRealtime      = +3,         ///< Priority: realtime (highest)\n  osPriorityError         = 0x84,       ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority;\n#else\n#define osPriority osPriority_t\n#endif\n\n/// Entry point of a thread.\ntypedef void (*os_pthread) (void const *argument);\n \n/// Entry point of a timer call back function.\ntypedef void (*os_ptimer) (void const *argument);\n \n/// Timer type.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osTimerOnce             = 0,          ///< One-shot timer.\n  osTimerPeriodic         = 1           ///< Repeating timer.\n} os_timer_type;\n#else\n#define os_timer_type osTimerType_t\n#endif\n \n/// Timeout value.\n#define osWaitForever       0xFFFFFFFFU ///< Wait forever timeout value.\n \n/// Status code values returned by CMSIS-RTOS functions.\n#if (osCMSIS < 0x20000U)\ntypedef enum {\n  osOK                    =    0,       ///< Function completed; no error or event occurred.\n  osEventSignal           = 0x08,       ///< Function completed; signal event occurred.\n  osEventMessage          = 0x10,       ///< Function completed; message event occurred.\n  osEventMail             = 0x20,       ///< Function completed; mail event occurred.\n  osEventTimeout          = 0x40,       ///< Function completed; timeout occurred.\n  osErrorParameter        = 0x80,       ///< Parameter error: a mandatory parameter was missing or specified an incorrect object.\n  osErrorResource         = 0x81,       ///< Resource not available: a specified resource was not available.\n  osErrorTimeoutResource  = 0xC1,       ///< Resource not available within given time: a specified resource was not available within the timeout period.\n  osErrorISR              = 0x82,       ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osErrorISRRecursive     = 0x83,       ///< Function called multiple times from ISR with same object.\n  osErrorPriority         = 0x84,       ///< System cannot determine priority or thread has illegal priority.\n  osErrorNoMemory         = 0x85,       ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorValue            = 0x86,       ///< Value of a parameter is out of range.\n  osErrorOS               = 0xFF,       ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osStatusReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus;\n#else\ntypedef int32_t                  osStatus;\n#define osEventSignal           (0x08)\n#define osEventMessage          (0x10)\n#define osEventMail             (0x20)\n#define osEventTimeout          (0x40)\n#define osErrorOS               osError\n#define osErrorTimeoutResource  osErrorTimeout\n#define osErrorISRRecursive     (-126)\n#define osErrorValue            (-127)\n#define osErrorPriority         (-128)\n#endif\n \n \n// >>> the following data type definitions may be adapted towards a specific RTOS\n \n/// Thread ID identifies the thread.\n#if (osCMSIS < 0x20000U)\ntypedef void *osThreadId;\n#else\n#define osThreadId osThreadId_t\n#endif\n \n/// Timer ID identifies the timer.\n#if (osCMSIS < 0x20000U)\ntypedef void *osTimerId;\n#else\n#define osTimerId osTimerId_t\n#endif\n \n/// Mutex ID identifies the mutex.\n#if (osCMSIS < 0x20000U)\ntypedef void *osMutexId;\n#else\n#define osMutexId osMutexId_t\n#endif\n \n/// Semaphore ID identifies the semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef void *osSemaphoreId;\n#else\n#define osSemaphoreId osSemaphoreId_t\n#endif\n \n/// Pool ID identifies the memory pool.\ntypedef void *osPoolId;\n \n/// Message ID identifies the message queue.\ntypedef void *osMessageQId;\n \n/// Mail ID identifies the mail queue.\ntypedef void *osMailQId;\n \n \n/// Thread Definition structure contains startup information of a thread.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osPriority               tpriority;   ///< initial thread priority\n  uint32_t                 instances;   ///< maximum number of instances of that thread function\n  uint32_t                 stacksize;   ///< stack size requirements in bytes; 0 is default stack size\n} osThreadDef_t;\n#else\ntypedef struct os_thread_def {\n  os_pthread                 pthread;   ///< start address of thread function\n  osThreadAttr_t                attr;   ///< thread attributes\n} osThreadDef_t;\n#endif\n \n/// Timer Definition structure contains timer parameters.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n} osTimerDef_t;\n#else\ntypedef struct os_timer_def {\n  os_ptimer                   ptimer;   ///< start address of a timer function\n  osTimerAttr_t                 attr;   ///< timer attributes\n} osTimerDef_t;\n#endif\n \n/// Mutex Definition structure contains setup information for a mutex.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mutex_def {\n  uint32_t                     dummy;   ///< dummy value\n} osMutexDef_t;\n#else\n#define osMutexDef_t osMutexAttr_t\n#endif\n \n/// Semaphore Definition structure contains setup information for a semaphore.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_semaphore_def {\n  uint32_t                     dummy;   ///< dummy value\n} osSemaphoreDef_t;\n#else\n#define osSemaphoreDef_t osSemaphoreAttr_t\n#endif\n \n/// Definition structure for memory block allocation.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< pointer to memory for pool\n} osPoolDef_t;\n#else\ntypedef struct os_pool_def {\n  uint32_t                   pool_sz;   ///< number of items (elements) in the pool\n  uint32_t                   item_sz;   ///< size of an item\n  osMemoryPoolAttr_t            attr;   ///< memory pool attributes\n} osPoolDef_t;\n#endif\n \n/// Definition structure for message queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  void                         *pool;   ///< memory array for messages\n} osMessageQDef_t;\n#else\ntypedef struct os_messageQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  osMessageQueueAttr_t          attr;   ///< message queue attributes\n} osMessageQDef_t;\n#endif\n \n/// Definition structure for mail queue.\n#if (osCMSIS < 0x20000U)\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *pool;   ///< memory array for mail\n} osMailQDef_t;\n#else\ntypedef struct os_mailQ_def {\n  uint32_t                  queue_sz;   ///< number of elements in the queue\n  uint32_t                   item_sz;   ///< size of an item\n  void                         *mail;   ///< pointer to mail\n  osMemoryPoolAttr_t         mp_attr;   ///< memory pool attributes\n  osMessageQueueAttr_t       mq_attr;   ///< message queue attributes\n} osMailQDef_t;\n#endif\n \n \n/// Event structure contains detailed information about an event.\ntypedef struct {\n  osStatus                    status;   ///< status code: event or error information\n  union {\n    uint32_t                       v;   ///< message as 32-bit value\n    void                          *p;   ///< message or mail as void pointer\n    int32_t                  signals;   ///< signal flags\n  } value;                              ///< event value\n  union {\n    osMailQId                mail_id;   ///< mail id obtained by \\ref osMailCreate\n    osMessageQId          message_id;   ///< message id obtained by \\ref osMessageCreate\n  } def;                                ///< event definition\n} osEvent;\n \n \n//  ==== Kernel Management Functions ====\n \n/// Initialize the RTOS Kernel for creating objects.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelInitialize (void);\n#endif\n \n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osKernelStart (void);\n#endif\n \n/// Check if the RTOS kernel is already started.\n/// \\return 0 RTOS is not started, 1 RTOS is started.\n#if (osCMSIS < 0x20000U)\nint32_t osKernelRunning(void);\n#endif\n \n#if (defined(osFeature_SysTick) && (osFeature_SysTick != 0))  // System Timer available\n \n/// Get the RTOS kernel system timer counter.\n/// \\return RTOS kernel system timer as 32-bit value \n#if (osCMSIS < 0x20000U)\nuint32_t osKernelSysTick (void);\n#else\n#define  osKernelSysTick osKernelGetSysTimerCount\n#endif\n \n/// The RTOS kernel system timer frequency in Hz.\n/// \\note Reflects the system timer setting and is typically defined in a configuration file.\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickFrequency 100000000\n#endif\n \n/// Convert a microseconds value to a RTOS kernel system timer value.\n/// \\param         microsec     time value in microseconds.\n/// \\return time value normalized to the \\ref osKernelSysTickFrequency\n#if (osCMSIS < 0x20000U)\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)\n#else\n#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec *  osKernelGetSysTimerFreq()) / 1000000)\n#endif\n \n#endif  // System Timer available\n \n \n//  ==== Thread Management Functions ====\n \n/// Create a Thread Definition with function, priority, and stack requirements.\n/// \\param         name          name of the thread function.\n/// \\param         priority      initial priority of the thread function.\n/// \\param         instances     number of possible thread instances.\n/// \\param         stacksz       stack size (in bytes) requirements for the thread function.\n#if defined (osObjectsExternal)  // object is external\n#define osThreadDef(name, priority, instances, stacksz) \\\nextern const osThreadDef_t os_thread_def_##name\n#else                            // define the object\n#define osThreadDef(name, priority, instances, stacksz) \\\nstatic uint64_t os_thread_stack##name[(stacksz)?(((stacksz+7)/8)):1]; \\\nstatic StaticTask_t os_thread_cb_##name; \\\nconst osThreadDef_t os_thread_def_##name = \\\n{ (name), \\\n  { NULL, osThreadDetached, \\\n    (instances == 1) ? (&os_thread_cb_##name) : NULL,\\\n    (instances == 1) ? sizeof(StaticTask_t) : 0U, \\\n    ((stacksz) && (instances == 1)) ? (&os_thread_stack##name) : NULL, \\\n    8*((stacksz+7)/8), \\\n    (priority), 0U, 0U } }\n#endif\n \n/// Access a Thread definition.\n/// \\param         name          name of the thread definition object.\n#define osThread(name) \\\n&os_thread_def_##name\n \n/// Create a thread and add it to Active Threads and set it to state READY.\n/// \\param[in]     thread_def    thread definition referenced with \\ref osThread.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);\n \n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\n#if (osCMSIS < 0x20000U)\nosThreadId osThreadGetId (void);\n#endif\n \n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);\n#endif\n \n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\n#if (osCMSIS < 0x20000U)\nosPriority osThreadGetPriority (osThreadId thread_id);\n#endif\n \n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadYield (void);\n#endif\n \n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osThreadTerminate (osThreadId thread_id);\n#endif\n \n \n//  ==== Signal Management ====\n \n/// Set the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that should be set.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.\nint32_t osSignalSet (osThreadId thread_id, int32_t signals);\n \n/// Clear the specified Signal Flags of an active thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadCreate or \\ref osThreadGetId.\n/// \\param[in]     signals       specifies the signal flags of the thread that shall be cleared.\n/// \\return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.\nint32_t osSignalClear (osThreadId thread_id, int32_t signals);\n \n/// Wait for one or more Signal Flags to become signaled for the current \\b RUNNING thread.\n/// \\param[in]     signals       wait until all specified signal flags set or 0 for any single signal flag.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flag information or error code.\nos_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);\n \n \n//  ==== Generic Wait Functions ====\n \n/// Wait for Timeout (Time Delay).\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osDelay (uint32_t millisec);\n#endif\n \n#if (defined (osFeature_Wait) && (osFeature_Wait != 0))  // Generic Wait available\n \n/// Wait for Signal, Message, Mail, or Timeout.\n/// \\param[in] millisec          \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return event that contains signal, message, or mail information or error code.\nos_InRegs osEvent osWait (uint32_t millisec);\n \n#endif  // Generic Wait available\n \n \n//  ==== Timer Management Functions ====\n \n/// Define a Timer object.\n/// \\param         name          name of the timer object.\n/// \\param         function      name of the timer call back function.\n#if defined (osObjectsExternal)  // object is external\n#define osTimerDef(name, function) \\\nextern const osTimerDef_t os_timer_def_##name\n#else                            // define the object\n#define osTimerDef(name, function) \\\nstatic StaticTimer_t os_timer_cb_##name; \\\nconst osTimerDef_t os_timer_def_##name = \\\n{ (function), { NULL, 0U, (&os_timer_cb_##name), sizeof(StaticTimer_t) } }\n#endif\n \n/// Access a Timer definition.\n/// \\param         name          name of the timer object.\n#define osTimer(name) \\\n&os_timer_def_##name\n \n/// Create and Initialize a timer.\n/// \\param[in]     timer_def     timer object referenced with \\ref osTimer.\n/// \\param[in]     type          osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer call back function.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);\n \n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue \"time delay\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStart (osTimerId timer_id, uint32_t millisec);\n#endif\n \n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerStop (osTimerId timer_id);\n#endif\n \n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osTimerDelete (osTimerId timer_id);\n#endif\n \n \n//  ==== Mutex Management Functions ====\n \n/// Define a Mutex.\n/// \\param         name          name of the mutex object.\n#if defined (osObjectsExternal)  // object is external\n#define osMutexDef(name) \\\nextern const osMutexDef_t os_mutex_def_##name\n#else                            // define the object\n#define osMutexDef(name) \\\nstatic StaticSemaphore_t os_mutex_cb_##name; \\\nconst osMutexDef_t os_mutex_def_##name = \\\n{ NULL, osMutexRecursive | osMutexPrioInherit, (&os_mutex_cb_##name), sizeof(StaticSemaphore_t) }\n#endif\n \n/// Access a Mutex definition.\n/// \\param         name          name of the mutex object.\n#define osMutex(name) \\\n&os_mutex_def_##name\n \n/// Create and Initialize a Mutex object.\n/// \\param[in]     mutex_def     mutex definition referenced with \\ref osMutex.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId osMutexCreate (const osMutexDef_t *mutex_def);\n \n/// Wait until a Mutex becomes available.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);\n#else\n#define  osMutexWait osMutexAcquire\n#endif\n \n/// Release a Mutex that was obtained by \\ref osMutexWait.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexRelease (osMutexId mutex_id);\n#endif\n \n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osMutexDelete (osMutexId mutex_id);\n#endif\n \n \n//  ==== Semaphore Management Functions ====\n \n#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0U))  // Semaphore available\n \n/// Define a Semaphore object.\n/// \\param         name          name of the semaphore object.\n#if defined (osObjectsExternal)  // object is external\n#define osSemaphoreDef(name) \\\nextern const osSemaphoreDef_t os_semaphore_def_##name\n#else                            // define the object\n#define osSemaphoreDef(name) \\\nstatic StaticSemaphore_t os_semaphore_cb_##name; \\\nconst osSemaphoreDef_t os_semaphore_def_##name = \\\n{ NULL, 0U, (&os_semaphore_cb_##name), sizeof(StaticSemaphore_t) }\n#endif\n \n/// Access a Semaphore definition.\n/// \\param         name          name of the semaphore object.\n#define osSemaphore(name) \\\n&os_semaphore_def_##name\n \n/// Create and Initialize a Semaphore object.\n/// \\param[in]     semaphore_def semaphore definition referenced with \\ref osSemaphore.\n/// \\param[in]     count         maximum and initial number of available tokens.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);\n \n/// Wait until a Semaphore token becomes available.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return number of available tokens, or -1 in case of incorrect parameters.\nint32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);\n \n/// Release a Semaphore token.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreRelease (osSemaphoreId semaphore_id);\n#endif\n \n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore object referenced with \\ref osSemaphoreCreate.\n/// \\return status code that indicates the execution status of the function.\n#if (osCMSIS < 0x20000U)\nosStatus osSemaphoreDelete (osSemaphoreId semaphore_id);\n#endif\n \n#endif  // Semaphore available\n \n \n//  ==== Memory Pool Management Functions ====\n\n#if (defined(osFeature_Pool) && (osFeature_Pool != 0))  // Memory Pool available\n \n/// \\brief Define a Memory Pool.\n/// \\param         name          name of the memory pool.\n/// \\param         no            maximum number of blocks (objects) in the memory pool.\n/// \\param         type          data type of a single block (object).\n#if defined (osObjectsExternal)  // object is external\n#define osPoolDef(name, no, type) \\\nextern const osPoolDef_t os_pool_def_##name\n#else                            // define the object\n#define osPoolDef(name, no, type) \\\nconst osPoolDef_t os_pool_def_##name = \\\n{ (no), sizeof(type), {NULL} }\n#endif\n \n/// \\brief Access a Memory Pool definition.\n/// \\param         name          name of the memory pool\n#define osPool(name) \\\n&os_pool_def_##name\n \n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     pool_def      memory pool definition referenced with \\ref osPool.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosPoolId osPoolCreate (const osPoolDef_t *pool_def);\n \n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolAlloc (osPoolId pool_id);\n \n/// Allocate a memory block from a Memory Pool and set memory block to zero.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\return address of the allocated memory block or NULL in case of no memory available.\nvoid *osPoolCAlloc (osPoolId pool_id);\n \n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     pool_id       memory pool ID obtain referenced with \\ref osPoolCreate.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus osPoolFree (osPoolId pool_id, void *block);\n \n#endif  // Memory Pool available\n \n \n//  ==== Message Queue Management Functions ====\n \n#if (defined(osFeature_MessageQ) && (osFeature_MessageQ != 0))  // Message Queue available\n  \n/// \\brief Create a Message Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of messages in the queue.\n/// \\param         type          data type of a single message element (for debugger).\n#if defined (osObjectsExternal)  // object is external\n#define osMessageQDef(name, queue_sz, type) \\\nextern const osMessageQDef_t os_messageQ_def_##name\n#else                            // define the object\n#define osMessageQDef(name, queue_sz, type) \\\nstatic StaticQueue_t os_mq_cb_##name; \\\nstatic uint32_t os_mq_data_##name[(queue_sz) * sizeof(type)]; \\\nconst osMessageQDef_t os_messageQ_def_##name = \\\n{ (queue_sz), \\\n  { NULL, 0U, (&os_mq_cb_##name), sizeof(StaticQueue_t), \\\n              (&os_mq_data_##name), sizeof(os_mq_data_##name) } }\n#endif\n \n/// \\brief Access a Message Queue Definition.\n/// \\param         name          name of the queue\n#define osMessageQ(name) \\\n&os_messageQ_def_##name\n \n/// Create and Initialize a Message Queue object.\n/// \\param[in]     queue_def     message queue definition referenced with \\ref osMessageQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);\n \n/// Put a Message to a Queue.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     info          message information.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);\n \n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      message queue ID obtained with \\ref osMessageCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);\n \n#endif  // Message Queue available\n \n \n//  ==== Mail Queue Management Functions ====\n \n#if (defined(osFeature_MailQ) && (osFeature_MailQ != 0))  // Mail Queue available\n \n/// \\brief Create a Mail Queue Definition.\n/// \\param         name          name of the queue.\n/// \\param         queue_sz      maximum number of mails in the queue.\n/// \\param         type          data type of a single mail element.\n#if defined (osObjectsExternal)  // object is external\n#define osMailQDef(name, queue_sz, type) \\\nextern const osMailQDef_t os_mailQ_def_##name\n#else                            // define the object\n#define osMailQDef(name, queue_sz, type) \\\nconst osMailQDef_t os_mailQ_def_##name = \\\n{ (queue_sz), sizeof(type), NULL }\n#endif\n \n/// \\brief Access a Mail Queue Definition.\n/// \\param         name          name of the queue\n#define osMailQ(name) \\\n&os_mailQ_def_##name\n \n/// Create and Initialize a Mail Queue object.\n/// \\param[in]     queue_def     mail queue definition referenced with \\ref osMailQ.\n/// \\param[in]     thread_id     thread ID (obtained by \\ref osThreadCreate or \\ref osThreadGetId) or NULL.\n/// \\return mail queue ID for reference by other functions or NULL in case of error.\nosMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);\n \n/// Allocate a memory block for mail from a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Allocate a memory block for mail from a mail memory pool and set memory block to zero.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out\n/// \\return pointer to memory block that can be filled with mail or NULL in case of error.\nvoid *osMailCAlloc (osMailQId queue_id, uint32_t millisec);\n \n/// Put a Mail into a Queue.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory with mail to put into a queue.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailPut (osMailQId queue_id, const void *mail);\n \n/// Get a Mail from a Queue or timeout if Queue is empty.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     millisec      \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event information that includes status code.\nos_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);\n \n/// Free a memory block by returning it to a mail memory pool.\n/// \\param[in]     queue_id      mail queue ID obtained with \\ref osMailCreate.\n/// \\param[in]     mail          pointer to memory block that was obtained with \\ref osMailGet.\n/// \\return status code that indicates the execution status of the function.\nosStatus osMailFree (osMailQId queue_id, void *mail);\n \n#endif  // Mail Queue available\n \n \n#ifdef  __cplusplus\n}\n#endif\n \n#endif  // CMSIS_OS_H_\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.c",
    "content": "/* --------------------------------------------------------------------------\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    cmsis_os2.c\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#include <string.h>\n\n#include \"cmsis_os2.h\"                  // ::CMSIS:RTOS2\n#include \"cmsis_compiler.h\"             // Compiler agnostic definitions\n\n#include \"FreeRTOS.h\"                   // ARM.FreeRTOS::RTOS:Core\n#include \"task.h\"                       // ARM.FreeRTOS::RTOS:Core\n#include \"event_groups.h\"               // ARM.FreeRTOS::RTOS:Event Groups\n#include \"semphr.h\"                     // ARM.FreeRTOS::RTOS:Core\n\n#include \"freertos_mpool.h\"             // osMemoryPool definitions\n#include \"freertos_os2.h\"               // Configuration check and setup\n\n/*---------------------------------------------------------------------------*/\n#ifndef __ARM_ARCH_6M__\n  #define __ARM_ARCH_6M__         0\n#endif\n#ifndef __ARM_ARCH_7M__\n  #define __ARM_ARCH_7M__         0\n#endif\n#ifndef __ARM_ARCH_7EM__\n  #define __ARM_ARCH_7EM__        0\n#endif\n#ifndef __ARM_ARCH_8M_MAIN__\n  #define __ARM_ARCH_8M_MAIN__    0\n#endif\n#ifndef __ARM_ARCH_7A__\n  #define __ARM_ARCH_7A__         0\n#endif\n\n#if   ((__ARM_ARCH_7M__      == 1U) || \\\n       (__ARM_ARCH_7EM__     == 1U) || \\\n       (__ARM_ARCH_8M_MAIN__ == 1U))\n#define IS_IRQ_MASKED()           ((__get_PRIMASK() != 0U) || (__get_BASEPRI() != 0U))\n#elif  (__ARM_ARCH_6M__      == 1U)\n#define IS_IRQ_MASKED()           (__get_PRIMASK() != 0U)\n#elif (__ARM_ARCH_7A__       == 1U)\n/* CPSR mask bits */\n#define CPSR_MASKBIT_I            0x80U\n\n#define IS_IRQ_MASKED()           ((__get_CPSR() & CPSR_MASKBIT_I) != 0U)\n#else\n#define IS_IRQ_MASKED()           (__get_PRIMASK() != 0U)\n#endif\n\n#if    (__ARM_ARCH_7A__      == 1U)\n/* CPSR mode bitmasks */\n#define CPSR_MODE_USER            0x10U\n#define CPSR_MODE_SYSTEM          0x1FU\n\n#define IS_IRQ_MODE()             ((__get_mode() != CPSR_MODE_USER) && (__get_mode() != CPSR_MODE_SYSTEM))\n#else\n#define IS_IRQ_MODE()             (__get_IPSR() != 0U)\n#endif\n\n#define IS_IRQ()                  IS_IRQ_MODE()\n\n#define SVCall_IRQ_NBR            (IRQn_Type) -5\t/* SVCall_IRQ_NBR added as SV_Call handler name is not the same for CM0 and for all other CMx */\n\n/* Limits */\n#define MAX_BITS_TASK_NOTIFY      31U\n#define MAX_BITS_EVENT_GROUPS     24U\n\n#define THREAD_FLAGS_INVALID_BITS (~((1UL << MAX_BITS_TASK_NOTIFY)  - 1U))\n#define EVENT_FLAGS_INVALID_BITS  (~((1UL << MAX_BITS_EVENT_GROUPS) - 1U))\n\n/* Kernel version and identification string definition (major.minor.rev: mmnnnrrrr dec) */\n#define KERNEL_VERSION            (((uint32_t)tskKERNEL_VERSION_MAJOR * 10000000UL) | \\\n                                   ((uint32_t)tskKERNEL_VERSION_MINOR *    10000UL) | \\\n                                   ((uint32_t)tskKERNEL_VERSION_BUILD *        1UL))\n\n#define KERNEL_ID                 (\"FreeRTOS \" tskKERNEL_VERSION_NUMBER)\n\n/* Timer callback information structure definition */\ntypedef struct {\n  osTimerFunc_t func;\n  void         *arg;\n} TimerCallback_t;\n\n/* Kernel initialization state */\nstatic osKernelState_t KernelState = osKernelInactive;\n\n/*\n  Heap region definition used by heap_5 variant\n\n  Define configAPPLICATION_ALLOCATED_HEAP as nonzero value in FreeRTOSConfig.h if\n  heap regions are already defined and vPortDefineHeapRegions is called in application.\n\n  Otherwise vPortDefineHeapRegions will be called by osKernelInitialize using\n  definition configHEAP_5_REGIONS as parameter. Overriding configHEAP_5_REGIONS\n  is possible by defining it globally or in FreeRTOSConfig.h.\n*/\n#if defined(USE_FreeRTOS_HEAP_5)\n#if (configAPPLICATION_ALLOCATED_HEAP == 0)\n  /*\n    FreeRTOS heap is not defined by the application.\n    Single region of size configTOTAL_HEAP_SIZE (defined in FreeRTOSConfig.h)\n    is provided by default. Define configHEAP_5_REGIONS to provide custom\n    HeapRegion_t array.\n  */\n  #define HEAP_5_REGION_SETUP   1\n  \n  #ifndef configHEAP_5_REGIONS\n    #define configHEAP_5_REGIONS xHeapRegions\n\n    static uint8_t ucHeap[configTOTAL_HEAP_SIZE];\n\n    static HeapRegion_t xHeapRegions[] = {\n      { ucHeap, configTOTAL_HEAP_SIZE },\n      { NULL,   0                     }\n    };\n  #else\n    /* Global definition is provided to override default heap array */\n    extern HeapRegion_t configHEAP_5_REGIONS[];\n  #endif\n#else\n  /*\n    The application already defined the array used for the FreeRTOS heap and\n    called vPortDefineHeapRegions to initialize heap.\n  */\n  #define HEAP_5_REGION_SETUP   0\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n#endif /* USE_FreeRTOS_HEAP_5 */\n\n#if defined(SysTick)\n#undef SysTick_Handler\n\n/* CMSIS SysTick interrupt handler prototype */\nextern void SysTick_Handler     (void);\n/* FreeRTOS tick timer interrupt handler prototype */\nextern void xPortSysTickHandler (void);\n\n/*\n  SysTick handler implementation that also clears overflow flag.\n*/\n#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)\nvoid SysTick_Handler (void) {\n  /* Clear overflow flag */\n  SysTick->CTRL;\n\n  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {\n    /* Call tick handler */\n    xPortSysTickHandler();\n  }\n}\n#endif\n#endif /* SysTick */\n\n/*\n  Setup SVC to reset value.\n*/\n__STATIC_INLINE void SVC_Setup (void) {\n#if (__ARM_ARCH_7A__ == 0U)\n  /* Service Call interrupt might be configured before kernel start     */\n  /* and when its priority is lower or equal to BASEPRI, svc intruction */\n  /* causes a Hard Fault.                                               */\n  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);\n#endif\n}\n\n/*\n  Function macro used to retrieve semaphore count from ISR\n*/\n#ifndef uxSemaphoreGetCountFromISR\n#define uxSemaphoreGetCountFromISR( xSemaphore ) uxQueueMessagesWaitingFromISR( ( QueueHandle_t ) ( xSemaphore ) )\n#endif\n\n/* Get OS Tick count value */\nstatic uint32_t OS_Tick_GetCount (void);\n/* Get OS Tick overflow status */\nstatic uint32_t OS_Tick_GetOverflow (void);\n/* Get OS Tick interval */\nstatic uint32_t OS_Tick_GetInterval (void);\n/*---------------------------------------------------------------------------*/\n\nosStatus_t osKernelInitialize (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    if (KernelState == osKernelInactive) {\n      #if defined(USE_TRACE_EVENT_RECORDER)\n        EvrFreeRTOSSetup(0U);\n      #endif\n      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)\n        vPortDefineHeapRegions (configHEAP_5_REGIONS);\n      #endif\n      KernelState = osKernelReady;\n      stat = osOK;\n    } else {\n      stat = osError;\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size) {\n\n  if (version != NULL) {\n    /* Version encoding is major.minor.rev: mmnnnrrrr dec */\n    version->api    = KERNEL_VERSION;\n    version->kernel = KERNEL_VERSION;\n  }\n\n  if ((id_buf != NULL) && (id_size != 0U)) {\n    if (id_size > sizeof(KERNEL_ID)) {\n      id_size = sizeof(KERNEL_ID);\n    }\n    memcpy(id_buf, KERNEL_ID, id_size);\n  }\n\n  return (osOK);\n}\n\nosKernelState_t osKernelGetState (void) {\n  osKernelState_t state;\n\n  switch (xTaskGetSchedulerState()) {\n    case taskSCHEDULER_RUNNING:\n      state = osKernelRunning;\n      break;\n\n    case taskSCHEDULER_SUSPENDED:\n      state = osKernelLocked;\n      break;\n\n    case taskSCHEDULER_NOT_STARTED:\n    default:\n      if (KernelState == osKernelReady) {\n        state = osKernelReady;\n      } else {\n        state = osKernelInactive;\n      }\n      break;\n  }\n\n  return (state);\n}\n\nosStatus_t osKernelStart (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    if (KernelState == osKernelReady) {\n      /* Ensure SVC priority is at the reset value */\n      SVC_Setup();\n      /* Change state to enable IRQ masking check */\n      KernelState = osKernelRunning;\n      /* Start the kernel scheduler */\n      vTaskStartScheduler();\n      stat = osOK;\n    } else {\n      stat = osError;\n    }\n  }\n\n  return (stat);\n}\n\nint32_t osKernelLock (void) {\n  int32_t lock;\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n        lock = 1;\n        break;\n\n      case taskSCHEDULER_RUNNING:\n        vTaskSuspendAll();\n        lock = 0;\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nint32_t osKernelUnlock (void) {\n  int32_t lock;\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n        lock = 1;\n\n        if (xTaskResumeAll() != pdTRUE) {\n          if (xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED) {\n            lock = (int32_t)osError;\n          }\n        }\n        break;\n\n      case taskSCHEDULER_RUNNING:\n        lock = 0;\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nint32_t osKernelRestoreLock (int32_t lock) {\n\n  if (IS_IRQ()) {\n    lock = (int32_t)osErrorISR;\n  }\n  else {\n    switch (xTaskGetSchedulerState()) {\n      case taskSCHEDULER_SUSPENDED:\n      case taskSCHEDULER_RUNNING:\n        if (lock == 1) {\n          vTaskSuspendAll();\n        }\n        else {\n          if (lock != 0) {\n            lock = (int32_t)osError;\n          }\n          else {\n            if (xTaskResumeAll() != pdTRUE) {\n              if (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING) {\n                lock = (int32_t)osError;\n              }\n            }\n          }\n        }\n        break;\n\n      case taskSCHEDULER_NOT_STARTED:\n      default:\n        lock = (int32_t)osError;\n        break;\n    }\n  }\n\n  return (lock);\n}\n\nuint32_t osKernelGetTickCount (void) {\n  TickType_t ticks;\n\n  if (IS_IRQ()) {\n    ticks = xTaskGetTickCountFromISR();\n  } else {\n    ticks = xTaskGetTickCount();\n  }\n\n  return (ticks);\n}\n\nuint32_t osKernelGetTickFreq (void) {\n  return (configTICK_RATE_HZ);\n}\n\n/* Get OS Tick count value */\nstatic uint32_t OS_Tick_GetCount (void) {\n  uint32_t load = SysTick->LOAD;\n  return  (load - SysTick->VAL);\n}\n\n/* Get OS Tick overflow status */\nstatic uint32_t OS_Tick_GetOverflow (void) {\n  return ((SysTick->CTRL >> 16) & 1U);\n}\n\n/* Get OS Tick interval */\nstatic uint32_t OS_Tick_GetInterval (void) {\n  return (SysTick->LOAD + 1U);\n}\n\nuint32_t osKernelGetSysTimerCount (void) {\n  uint32_t irqmask = IS_IRQ_MASKED();\n  TickType_t ticks;\n  uint32_t val;\n\n  __disable_irq();\n\n  ticks = xTaskGetTickCount();\n  val   = OS_Tick_GetCount();\n\n  if (OS_Tick_GetOverflow() != 0U) {\n    val = OS_Tick_GetCount();\n    ticks++;\n  }\n  val += ticks * OS_Tick_GetInterval();\n\n  if (irqmask == 0U) {\n    __enable_irq();\n  }\n\n  return (val);\n}\n\nuint32_t osKernelGetSysTimerFreq (void) {\n  return (configCPU_CLOCK_HZ);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {\n  const char *name;\n  uint32_t stack;\n  TaskHandle_t hTask;\n  UBaseType_t prio;\n  int32_t mem;\n\n  hTask = NULL;\n\n  if (!IS_IRQ() && (func != NULL)) {\n    stack = configMINIMAL_STACK_SIZE;\n    prio  = (UBaseType_t)osPriorityNormal;\n\n    name = NULL;\n    mem  = -1;\n\n    if (attr != NULL) {\n      if (attr->name != NULL) {\n        name = attr->name;\n      }\n      if (attr->priority != osPriorityNone) {\n        prio = (UBaseType_t)attr->priority;\n      }\n\n      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {\n        return (NULL);\n      }\n\n      if (attr->stack_size > 0U) {\n        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */\n        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */\n        stack = attr->stack_size / sizeof(StackType_t);\n      }\n\n      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&\n          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      #if (configSUPPORT_STATIC_ALLOCATION == 1)\n        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,\n                                                                                      (StaticTask_t *)attr->cb_mem);\n      #endif\n    }\n    else {\n      if (mem == 0) {\n        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {\n            hTask = NULL;\n          }\n        #endif\n      }\n    }\n  }\n\n  return ((osThreadId_t)hTask);\n}\n\nconst char *osThreadGetName (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  const char *name;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    name = NULL;\n  } else {\n    name = pcTaskGetName (hTask);\n  }\n\n  return (name);\n}\n\nosThreadId_t osThreadGetId (void) {\n  osThreadId_t id;\n\n  id = (osThreadId_t)xTaskGetCurrentTaskHandle();\n\n  return (id);\n}\n\nosThreadState_t osThreadGetState (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osThreadState_t state;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    state = osThreadError;\n  }\n  else {\n    switch (eTaskGetState (hTask)) {\n      case eRunning:   state = osThreadRunning;    break;\n      case eReady:     state = osThreadReady;      break;\n      case eBlocked:\n      case eSuspended: state = osThreadBlocked;    break;\n      case eDeleted:   state = osThreadTerminated; break;\n      case eInvalid:\n      default:         state = osThreadError;      break;\n    }\n  }\n\n  return (state);\n}\n\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  uint32_t sz;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    sz = 0U;\n  } else {\n    sz = (uint32_t)(uxTaskGetStackHighWaterMark(hTask) * sizeof(StackType_t));\n  }\n\n  return (sz);\n}\n\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if ((hTask == NULL) || (priority < osPriorityIdle) || (priority > osPriorityISR)) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskPrioritySet (hTask, (UBaseType_t)priority);\n  }\n\n  return (stat);\n}\n\nosPriority_t osThreadGetPriority (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osPriority_t prio;\n\n  if (IS_IRQ() || (hTask == NULL)) {\n    prio = osPriorityError;\n  } else {\n    prio = (osPriority_t)((int32_t)uxTaskPriorityGet (hTask));\n  }\n\n  return (prio);\n}\n\nosStatus_t osThreadYield (void) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  } else {\n    stat = osOK;\n    taskYIELD();\n  }\n\n  return (stat);\n}\n\n#if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1)\nosStatus_t osThreadSuspend (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskSuspend (hTask);\n  }\n\n  return (stat);\n}\n\nosStatus_t osThreadResume (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vTaskResume (hTask);\n  }\n\n  return (stat);\n}\n#endif /* (configUSE_OS2_THREAD_SUSPEND_RESUME == 1) */\n\n__NO_RETURN void osThreadExit (void) {\n#ifndef USE_FreeRTOS_HEAP_1\n  vTaskDelete (NULL);\n#endif\n  for (;;);\n}\n\nosStatus_t osThreadTerminate (osThreadId_t thread_id) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  eTaskState tstate;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTask == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    tstate = eTaskGetState (hTask);\n\n    if (tstate != eDeleted) {\n      stat = osOK;\n      vTaskDelete (hTask);\n    } else {\n      stat = osErrorResource;\n    }\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\nuint32_t osThreadGetCount (void) {\n  uint32_t count;\n\n  if (IS_IRQ()) {\n    count = 0U;\n  } else {\n    count = uxTaskGetNumberOfTasks();\n  }\n\n  return (count);\n}\n\n#if (configUSE_OS2_THREAD_ENUMERATE == 1)\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items) {\n  uint32_t i, count;\n  TaskStatus_t *task;\n\n  if (IS_IRQ() || (thread_array == NULL) || (array_items == 0U)) {\n    count = 0U;\n  } else {\n    vTaskSuspendAll();\n\n    count = uxTaskGetNumberOfTasks();\n    task  = pvPortMalloc (count * sizeof(TaskStatus_t));\n\n    if (task != NULL) {\n      count = uxTaskGetSystemState (task, count, NULL);\n\n      for (i = 0U; (i < count) && (i < array_items); i++) {\n        thread_array[i] = (osThreadId_t)task[i].xHandle;\n      }\n      count = i;\n    }\n    (void)xTaskResumeAll();\n\n    vPortFree (task);\n  }\n\n  return (count);\n}\n#endif /* (configUSE_OS2_THREAD_ENUMERATE == 1) */\n\n#if (configUSE_OS2_THREAD_FLAGS == 1)\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags) {\n  TaskHandle_t hTask = (TaskHandle_t)thread_id;\n  uint32_t rflags;\n  BaseType_t yield;\n\n  if ((hTask == NULL) || ((flags & THREAD_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    rflags = (uint32_t)osError;\n\n    if (IS_IRQ()) {\n      yield = pdFALSE;\n\n      (void)xTaskNotifyFromISR (hTask, flags, eSetBits, &yield);\n      (void)xTaskNotifyAndQueryFromISR (hTask, 0, eNoAction, &rflags, NULL);\n\n      portYIELD_FROM_ISR (yield);\n    }\n    else {\n      (void)xTaskNotify (hTask, flags, eSetBits);\n      (void)xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags);\n    }\n  }\n  /* Return flags after setting */\n  return (rflags);\n}\n\nuint32_t osThreadFlagsClear (uint32_t flags) {\n  TaskHandle_t hTask;\n  uint32_t rflags, cflags;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    hTask = xTaskGetCurrentTaskHandle();\n\n    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &cflags) == pdPASS) {\n      rflags = cflags;\n      cflags &= ~flags;\n\n      if (xTaskNotify (hTask, cflags, eSetValueWithOverwrite) != pdPASS) {\n        rflags = (uint32_t)osError;\n      }\n    }\n    else {\n      rflags = (uint32_t)osError;\n    }\n  }\n\n  /* Return flags before clearing */\n  return (rflags);\n}\n\nuint32_t osThreadFlagsGet (void) {\n  TaskHandle_t hTask;\n  uint32_t rflags;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else {\n    hTask = xTaskGetCurrentTaskHandle();\n\n    if (xTaskNotifyAndQuery (hTask, 0, eNoAction, &rflags) != pdPASS) {\n      rflags = (uint32_t)osError;\n    }\n  }\n\n  return (rflags);\n}\n\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout) {\n  uint32_t rflags, nval;\n  uint32_t clear;\n  TickType_t t0, td, tout;\n  BaseType_t rval;\n\n  if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else if ((flags & THREAD_FLAGS_INVALID_BITS) != 0U) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else {\n    if ((options & osFlagsNoClear) == osFlagsNoClear) {\n      clear = 0U;\n    } else {\n      clear = flags;\n    }\n\n    rflags = 0U;\n    tout   = timeout;\n\n    t0 = xTaskGetTickCount();\n    do {\n      rval = xTaskNotifyWait (0, clear, &nval, tout);\n\n      if (rval == pdPASS) {\n        rflags &= flags;\n        rflags |= nval;\n\n        if ((options & osFlagsWaitAll) == osFlagsWaitAll) {\n          if ((flags & rflags) == flags) {\n            break;\n          } else {\n            if (timeout == 0U) {\n              rflags = (uint32_t)osErrorResource;\n              break;\n            }\n          }\n        }\n        else {\n          if ((flags & rflags) != 0) {\n            break;\n          } else {\n            if (timeout == 0U) {\n              rflags = (uint32_t)osErrorResource;\n              break;\n            }\n          }\n        }\n\n        /* Update timeout */\n        td = xTaskGetTickCount() - t0;\n\n        if (td > tout) {\n          tout  = 0;\n        } else {\n          tout -= td;\n        }\n      }\n      else {\n        if (timeout == 0) {\n          rflags = (uint32_t)osErrorResource;\n        } else {\n          rflags = (uint32_t)osErrorTimeout;\n        }\n      }\n    }\n    while (rval != pdFAIL);\n  }\n\n  /* Return flags before clearing */\n  return (rflags);\n}\n#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */\n\nosStatus_t osDelay (uint32_t ticks) {\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    stat = osOK;\n\n    if (ticks != 0U) {\n      vTaskDelay(ticks);\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osDelayUntil (uint32_t ticks) {\n  TickType_t tcnt, delay;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    stat = osOK;\n    tcnt = xTaskGetTickCount();\n\n    /* Determine remaining number of ticks to delay */\n    delay = (TickType_t)ticks - tcnt;\n\n    /* Check if target tick has not expired */\n    if((delay != 0U) && (0 == (delay >> (8 * sizeof(TickType_t) - 1)))) {\n      vTaskDelayUntil (&tcnt, delay);\n    }\n    else\n    {\n      /* No delay or already expired */\n      stat = osErrorParameter;\n    }\n  }\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n#if (configUSE_OS2_TIMER == 1)\n\nstatic void TimerCallback (TimerHandle_t hTimer) {\n  TimerCallback_t *callb;\n\n  callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);\n\n  if (callb != NULL) {\n    callb->func (callb->arg);\n  }\n}\n\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr) {\n  const char *name;\n  TimerHandle_t hTimer;\n  TimerCallback_t *callb;\n  UBaseType_t reload;\n  int32_t mem;\n\n  hTimer = NULL;\n\n  if (!IS_IRQ() && (func != NULL)) {\n    /* Allocate memory to store callback function and argument */\n    callb = pvPortMalloc (sizeof(TimerCallback_t));\n\n    if (callb != NULL) {\n      callb->func = func;\n      callb->arg  = argument;\n\n      if (type == osTimerOnce) {\n        reload = pdFALSE;\n      } else {\n        reload = pdTRUE;\n      }\n\n      mem  = -1;\n      name = NULL;\n\n      if (attr != NULL) {\n        if (attr->name != NULL) {\n          name = attr->name;\n        }\n\n        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTimer_t))) {\n          mem = 1;\n        }\n        else {\n          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n            mem = 0;\n          }\n        }\n      }\n      else {\n        mem = 0;\n      }\n\n      if (mem == 1) {\n        #if (configSUPPORT_STATIC_ALLOCATION == 1)\n          hTimer = xTimerCreateStatic (name, 1, reload, callb, TimerCallback, (StaticTimer_t *)attr->cb_mem);\n        #endif\n      }\n      else {\n        if (mem == 0) {\n          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n            hTimer = xTimerCreate (name, 1, reload, callb, TimerCallback);\n          #endif\n        }\n      }\n\n      if ((hTimer == NULL) && (callb != NULL)) {\n        vPortFree (callb);\n      }\n    }\n  }\n\n  return ((osTimerId_t)hTimer);\n}\n\nconst char *osTimerGetName (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  const char *p;\n\n  if (IS_IRQ() || (hTimer == NULL)) {\n    p = NULL;\n  } else {\n    p = pcTimerGetName (hTimer);\n  }\n\n  return (p);\n}\n\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (xTimerChangePeriod (hTimer, ticks, 0) == pdPASS) {\n      stat = osOK;\n    } else {\n      stat = osErrorResource;\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osTimerStop (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (xTimerIsTimerActive (hTimer) == pdFALSE) {\n      stat = osErrorResource;\n    }\n    else {\n      if (xTimerStop (hTimer, 0) == pdPASS) {\n        stat = osOK;\n      } else {\n        stat = osError;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osTimerIsRunning (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  uint32_t running;\n\n  if (IS_IRQ() || (hTimer == NULL)) {\n    running = 0U;\n  } else {\n    running = (uint32_t)xTimerIsTimerActive (hTimer);\n  }\n\n  return (running);\n}\n\nosStatus_t osTimerDelete (osTimerId_t timer_id) {\n  TimerHandle_t hTimer = (TimerHandle_t)timer_id;\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  TimerCallback_t *callb;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hTimer == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    callb = (TimerCallback_t *)pvTimerGetTimerID (hTimer);\n\n    if (xTimerDelete (hTimer, 0) == pdPASS) {\n      vPortFree (callb);\n      stat = osOK;\n    } else {\n      stat = osErrorResource;\n    }\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n#endif /* (configUSE_OS2_TIMER == 1) */\n\n/*---------------------------------------------------------------------------*/\n\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr) {\n  EventGroupHandle_t hEventGroup;\n  int32_t mem;\n\n  hEventGroup = NULL;\n\n  if (!IS_IRQ()) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticEventGroup_t))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      #if (configSUPPORT_STATIC_ALLOCATION == 1)\n      hEventGroup = xEventGroupCreateStatic (attr->cb_mem);\n      #endif\n    }\n    else {\n      if (mem == 0) {\n        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n          hEventGroup = xEventGroupCreate();\n        #endif\n      }\n    }\n  }\n\n  return ((osEventFlagsId_t)hEventGroup);\n}\n\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n  BaseType_t yield;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0)\n    (void)yield;\n    /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */\n    rflags = (uint32_t)osErrorResource;\n  #else\n    yield = pdFALSE;\n\n    if (xEventGroupSetBitsFromISR (hEventGroup, (EventBits_t)flags, &yield) == pdFAIL) {\n      rflags = (uint32_t)osErrorResource;\n    } else {\n      rflags = flags;\n      portYIELD_FROM_ISR (yield);\n    }\n  #endif\n  }\n  else {\n    rflags = xEventGroupSetBits (hEventGroup, (EventBits_t)flags);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 0)\n    /* Enable timers and xTimerPendFunctionCall function to support osEventFlagsSet from ISR */\n    rflags = (uint32_t)osErrorResource;\n  #else\n    rflags = xEventGroupGetBitsFromISR (hEventGroup);\n\n    if (xEventGroupClearBitsFromISR (hEventGroup, (EventBits_t)flags) == pdFAIL) {\n      rflags = (uint32_t)osErrorResource;\n    }\n  #endif\n  }\n  else {\n    rflags = xEventGroupClearBits (hEventGroup, (EventBits_t)flags);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  uint32_t rflags;\n\n  if (ef_id == NULL) {\n    rflags = 0U;\n  }\n  else if (IS_IRQ()) {\n    rflags = xEventGroupGetBitsFromISR (hEventGroup);\n  }\n  else {\n    rflags = xEventGroupGetBits (hEventGroup);\n  }\n\n  return (rflags);\n}\n\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  BaseType_t wait_all;\n  BaseType_t exit_clr;\n  uint32_t rflags;\n\n  if ((hEventGroup == NULL) || ((flags & EVENT_FLAGS_INVALID_BITS) != 0U)) {\n    rflags = (uint32_t)osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    rflags = (uint32_t)osErrorISR;\n  }\n  else {\n    if (options & osFlagsWaitAll) {\n      wait_all = pdTRUE;\n    } else {\n      wait_all = pdFAIL;\n    }\n\n    if (options & osFlagsNoClear) {\n      exit_clr = pdFAIL;\n    } else {\n      exit_clr = pdTRUE;\n    }\n\n    rflags = xEventGroupWaitBits (hEventGroup, (EventBits_t)flags, exit_clr, wait_all, (TickType_t)timeout);\n\n    if (options & osFlagsWaitAll) {\n      if ((flags & rflags) != flags) {\n        if (timeout > 0U) {\n          rflags = (uint32_t)osErrorTimeout;\n        } else {\n          rflags = (uint32_t)osErrorResource;\n        }\n      }\n    }\n    else {\n      if ((flags & rflags) == 0U) {\n        if (timeout > 0U) {\n          rflags = (uint32_t)osErrorTimeout;\n        } else {\n          rflags = (uint32_t)osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (rflags);\n}\n\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id) {\n  EventGroupHandle_t hEventGroup = (EventGroupHandle_t)ef_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hEventGroup == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    vEventGroupDelete (hEventGroup);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n#if (configUSE_OS2_MUTEX == 1)\n\nosMutexId_t osMutexNew (const osMutexAttr_t *attr) {\n  SemaphoreHandle_t hMutex;\n  uint32_t type;\n  uint32_t rmtx;\n  int32_t  mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hMutex = NULL;\n\n  if (!IS_IRQ()) {\n    if (attr != NULL) {\n      type = attr->attr_bits;\n    } else {\n      type = 0U;\n    }\n\n    if ((type & osMutexRecursive) == osMutexRecursive) {\n      rmtx = 1U;\n    } else {\n      rmtx = 0U;\n    }\n\n    if ((type & osMutexRobust) != osMutexRobust) {\n      mem = -1;\n\n      if (attr != NULL) {\n        if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {\n          mem = 1;\n        }\n        else {\n          if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n            mem = 0;\n          }\n        }\n      }\n      else {\n        mem = 0;\n      }\n\n      if (mem == 1) {\n        #if (configSUPPORT_STATIC_ALLOCATION == 1)\n          if (rmtx != 0U) {\n            #if (configUSE_RECURSIVE_MUTEXES == 1)\n            hMutex = xSemaphoreCreateRecursiveMutexStatic (attr->cb_mem);\n            #endif\n          }\n          else {\n            hMutex = xSemaphoreCreateMutexStatic (attr->cb_mem);\n          }\n        #endif\n      }\n      else {\n        if (mem == 0) {\n          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n            if (rmtx != 0U) {\n              #if (configUSE_RECURSIVE_MUTEXES == 1)\n              hMutex = xSemaphoreCreateRecursiveMutex ();\n              #endif\n            } else {\n              hMutex = xSemaphoreCreateMutex ();\n            }\n          #endif\n        }\n      }\n\n      #if (configQUEUE_REGISTRY_SIZE > 0)\n      if (hMutex != NULL) {\n        if (attr != NULL) {\n          name = attr->name;\n        } else {\n          name = NULL;\n        }\n        vQueueAddToRegistry (hMutex, name);\n      }\n      #endif\n\n      if ((hMutex != NULL) && (rmtx != 0U)) {\n        hMutex = (SemaphoreHandle_t)((uint32_t)hMutex | 1U);\n      }\n    }\n  }\n\n  return ((osMutexId_t)hMutex);\n}\n\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout) {\n  SemaphoreHandle_t hMutex;\n  osStatus_t stat;\n  uint32_t rmtx;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  rmtx = (uint32_t)mutex_id & 1U;\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (rmtx != 0U) {\n      #if (configUSE_RECURSIVE_MUTEXES == 1)\n      if (xSemaphoreTakeRecursive (hMutex, timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n      #endif\n    }\n    else {\n      if (xSemaphoreTake (hMutex, timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osMutexRelease (osMutexId_t mutex_id) {\n  SemaphoreHandle_t hMutex;\n  osStatus_t stat;\n  uint32_t rmtx;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  rmtx = (uint32_t)mutex_id & 1U;\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    if (rmtx != 0U) {\n      #if (configUSE_RECURSIVE_MUTEXES == 1)\n      if (xSemaphoreGiveRecursive (hMutex) != pdPASS) {\n        stat = osErrorResource;\n      }\n      #endif\n    }\n    else {\n      if (xSemaphoreGive (hMutex) != pdPASS) {\n        stat = osErrorResource;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id) {\n  SemaphoreHandle_t hMutex;\n  osThreadId_t owner;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  if (IS_IRQ() || (hMutex == NULL)) {\n    owner = NULL;\n  } else {\n    owner = (osThreadId_t)xSemaphoreGetMutexHolder (hMutex);\n  }\n\n  return (owner);\n}\n\nosStatus_t osMutexDelete (osMutexId_t mutex_id) {\n  osStatus_t stat;\n#ifndef USE_FreeRTOS_HEAP_1\n  SemaphoreHandle_t hMutex;\n\n  hMutex = (SemaphoreHandle_t)((uint32_t)mutex_id & ~1U);\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hMutex == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hMutex);\n    #endif\n    stat = osOK;\n    vSemaphoreDelete (hMutex);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n#endif /* (configUSE_OS2_MUTEX == 1) */\n\n/*---------------------------------------------------------------------------*/\n\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr) {\n  SemaphoreHandle_t hSemaphore;\n  int32_t mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hSemaphore = NULL;\n\n  if (!IS_IRQ() && (max_count > 0U) && (initial_count <= max_count)) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticSemaphore_t))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem != -1) {\n      if (max_count == 1U) {\n        if (mem == 1) {\n          #if (configSUPPORT_STATIC_ALLOCATION == 1)\n            hSemaphore = xSemaphoreCreateBinaryStatic ((StaticSemaphore_t *)attr->cb_mem);\n          #endif\n        }\n        else {\n          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n            hSemaphore = xSemaphoreCreateBinary();\n          #endif\n        }\n\n        if ((hSemaphore != NULL) && (initial_count != 0U)) {\n          if (xSemaphoreGive (hSemaphore) != pdPASS) {\n            vSemaphoreDelete (hSemaphore);\n            hSemaphore = NULL;\n          }\n        }\n      }\n      else {\n        if (mem == 1) {\n          #if (configSUPPORT_STATIC_ALLOCATION == 1)\n            hSemaphore = xSemaphoreCreateCountingStatic (max_count, initial_count, (StaticSemaphore_t *)attr->cb_mem);\n          #endif\n        }\n        else {\n          #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n            hSemaphore = xSemaphoreCreateCounting (max_count, initial_count);\n          #endif\n        }\n      }\n      \n      #if (configQUEUE_REGISTRY_SIZE > 0)\n      if (hSemaphore != NULL) {\n        if (attr != NULL) {\n          name = attr->name;\n        } else {\n          name = NULL;\n        }\n        vQueueAddToRegistry (hSemaphore, name);\n      }\n      #endif\n    }\n  }\n\n  return ((osSemaphoreId_t)hSemaphore);\n}\n\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  stat = osOK;\n\n  if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    if (timeout != 0U) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xSemaphoreTakeFromISR (hSemaphore, &yield) != pdPASS) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if (xSemaphoreTake (hSemaphore, (TickType_t)timeout) != pdPASS) {\n      if (timeout != 0U) {\n        stat = osErrorTimeout;\n      } else {\n        stat = osErrorResource;\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  stat = osOK;\n\n  if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    yield = pdFALSE;\n\n    if (xSemaphoreGiveFromISR (hSemaphore, &yield) != pdTRUE) {\n      stat = osErrorResource;\n    } else {\n      portYIELD_FROM_ISR (yield);\n    }\n  }\n  else {\n    if (xSemaphoreGive (hSemaphore) != pdPASS) {\n      stat = osErrorResource;\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  uint32_t count;\n\n  if (hSemaphore == NULL) {\n    count = 0U;\n  }\n  else if (IS_IRQ()) {\n    count = uxQueueMessagesWaitingFromISR (hSemaphore);\n  } else {\n    count = (uint32_t)uxSemaphoreGetCount (hSemaphore);\n  }\n\n  return (count);\n}\n\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id) {\n  SemaphoreHandle_t hSemaphore = (SemaphoreHandle_t)semaphore_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hSemaphore == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hSemaphore);\n    #endif\n\n    stat = osOK;\n    vSemaphoreDelete (hSemaphore);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr) {\n  QueueHandle_t hQueue;\n  int32_t mem;\n  #if (configQUEUE_REGISTRY_SIZE > 0)\n  const char *name;\n  #endif\n\n  hQueue = NULL;\n\n  if (!IS_IRQ() && (msg_count > 0U) && (msg_size > 0U)) {\n    mem = -1;\n\n    if (attr != NULL) {\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticQueue_t)) &&\n          (attr->mq_mem != NULL) && (attr->mq_size >= (msg_count * msg_size))) {\n        mem = 1;\n      }\n      else {\n        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) &&\n            (attr->mq_mem == NULL) && (attr->mq_size == 0U)) {\n          mem = 0;\n        }\n      }\n    }\n    else {\n      mem = 0;\n    }\n\n    if (mem == 1) {\n      #if (configSUPPORT_STATIC_ALLOCATION == 1)\n        hQueue = xQueueCreateStatic (msg_count, msg_size, attr->mq_mem, attr->cb_mem);\n      #endif\n    }\n    else {\n      if (mem == 0) {\n        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n          hQueue = xQueueCreate (msg_count, msg_size);\n        #endif\n      }\n    }\n\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    if (hQueue != NULL) {\n      if (attr != NULL) {\n        name = attr->name;\n      } else {\n        name = NULL;\n      }\n      vQueueAddToRegistry (hQueue, name);\n    }\n    #endif\n\n  }\n\n  return ((osMessageQueueId_t)hQueue);\n}\n\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  (void)msg_prio; /* Message priority is ignored */\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xQueueSendToBackFromISR (hQueue, msg_ptr, &yield) != pdTRUE) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if ((hQueue == NULL) || (msg_ptr == NULL)) {\n      stat = osErrorParameter;\n    }\n    else {\n      if (xQueueSendToBack (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n  BaseType_t yield;\n\n  (void)msg_prio; /* Message priority is ignored */\n\n  stat = osOK;\n\n  if (IS_IRQ()) {\n    if ((hQueue == NULL) || (msg_ptr == NULL) || (timeout != 0U)) {\n      stat = osErrorParameter;\n    }\n    else {\n      yield = pdFALSE;\n\n      if (xQueueReceiveFromISR (hQueue, msg_ptr, &yield) != pdPASS) {\n        stat = osErrorResource;\n      } else {\n        portYIELD_FROM_ISR (yield);\n      }\n    }\n  }\n  else {\n    if ((hQueue == NULL) || (msg_ptr == NULL)) {\n      stat = osErrorParameter;\n    }\n    else {\n      if (xQueueReceive (hQueue, msg_ptr, (TickType_t)timeout) != pdPASS) {\n        if (timeout != 0U) {\n          stat = osErrorTimeout;\n        } else {\n          stat = osErrorResource;\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t capacity;\n\n  if (mq == NULL) {\n    capacity = 0U;\n  } else {\n    /* capacity = pxQueue->uxLength */\n    capacity = mq->uxDummy4[1];\n  }\n\n  return (capacity);\n}\n\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t size;\n\n  if (mq == NULL) {\n    size = 0U;\n  } else {\n    /* size = pxQueue->uxItemSize */\n    size = mq->uxDummy4[2];\n  }\n\n  return (size);\n}\n\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  UBaseType_t count;\n\n  if (hQueue == NULL) {\n    count = 0U;\n  }\n  else if (IS_IRQ()) {\n    count = uxQueueMessagesWaitingFromISR (hQueue);\n  }\n  else {\n    count = uxQueueMessagesWaiting (hQueue);\n  }\n\n  return ((uint32_t)count);\n}\n\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id) {\n  StaticQueue_t *mq = (StaticQueue_t *)mq_id;\n  uint32_t space;\n  uint32_t isrm;\n\n  if (mq == NULL) {\n    space = 0U;\n  }\n  else if (IS_IRQ()) {\n    isrm = taskENTER_CRITICAL_FROM_ISR();\n\n    /* space = pxQueue->uxLength - pxQueue->uxMessagesWaiting; */\n    space = mq->uxDummy4[1] - mq->uxDummy4[0];\n\n    taskEXIT_CRITICAL_FROM_ISR(isrm);\n  }\n  else {\n    space = (uint32_t)uxQueueSpacesAvailable ((QueueHandle_t)mq);\n  }\n\n  return (space);\n}\n\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hQueue == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    stat = osOK;\n    (void)xQueueReset (hQueue);\n  }\n\n  return (stat);\n}\n\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id) {\n  QueueHandle_t hQueue = (QueueHandle_t)mq_id;\n  osStatus_t stat;\n\n#ifndef USE_FreeRTOS_HEAP_1\n  if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else if (hQueue == NULL) {\n    stat = osErrorParameter;\n  }\n  else {\n    #if (configQUEUE_REGISTRY_SIZE > 0)\n    vQueueUnregisterQueue (hQueue);\n    #endif\n\n    stat = osOK;\n    vQueueDelete (hQueue);\n  }\n#else\n  stat = osError;\n#endif\n\n  return (stat);\n}\n\n/*---------------------------------------------------------------------------*/\n#ifdef FREERTOS_MPOOL_H_\n\n/* Static memory pool functions */\nstatic void  FreeBlock   (MemPool_t *mp, void *block);\nstatic void *AllocBlock  (MemPool_t *mp);\nstatic void *CreateBlock (MemPool_t *mp);\n\nosMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr) {\n  MemPool_t *mp;\n  const char *name;\n  int32_t mem_cb, mem_mp;\n  uint32_t sz;\n\n  if (IS_IRQ()) {\n    mp = NULL;\n  }\n  else if ((block_count == 0U) || (block_size == 0U)) {\n    mp = NULL;\n  }\n  else {\n    mp = NULL;\n    sz = MEMPOOL_ARR_SIZE (block_count, block_size);\n\n    name = NULL;\n    mem_cb = -1;\n    mem_mp = -1;\n\n    if (attr != NULL) {\n      if (attr->name != NULL) {\n        name = attr->name;\n      }\n\n      if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(MemPool_t))) {\n        /* Static control block is provided */\n        mem_cb = 1;\n      }\n      else if ((attr->cb_mem == NULL) && (attr->cb_size == 0U)) {\n        /* Allocate control block memory on heap */\n        mem_cb = 0;\n      }\n\n      if ((attr->mp_mem == NULL) && (attr->mp_size == 0U)) {\n        /* Allocate memory array on heap */\n          mem_mp = 0;\n      }\n      else {\n        if (attr->mp_mem != NULL) {\n          /* Check if array is 4-byte aligned */\n          if (((uint32_t)attr->mp_mem & 3U) == 0U) {\n            /* Check if array big enough */\n            if (attr->mp_size >= sz) {\n              /* Static memory pool array is provided */\n              mem_mp = 1;\n            }\n          }\n        }\n      }\n    }\n    else {\n      /* Attributes not provided, allocate memory on heap */\n      mem_cb = 0;\n      mem_mp = 0;\n    }\n\n    if (mem_cb == 0) {\n      mp = pvPortMalloc (sizeof(MemPool_t));\n    } else {\n      mp = attr->cb_mem;\n    }\n\n    if (mp != NULL) {\n      /* Create a semaphore (max count == initial count == block_count) */\n      #if (configSUPPORT_STATIC_ALLOCATION == 1)\n        mp->sem = xSemaphoreCreateCountingStatic (block_count, block_count, &mp->mem_sem);\n      #elif (configSUPPORT_DYNAMIC_ALLOCATION == 1)\n        mp->sem = xSemaphoreCreateCounting (block_count, block_count);\n      #else\n        mp->sem == NULL;\n      #endif\n\n      if (mp->sem != NULL) {\n        /* Setup memory array */\n        if (mem_mp == 0) {\n          mp->mem_arr = pvPortMalloc (sz);\n        } else {\n          mp->mem_arr = attr->mp_mem;\n        }\n      }\n    }\n\n    if ((mp != NULL) && (mp->mem_arr != NULL)) {\n      /* Memory pool can be created */\n      mp->head    = NULL;\n      mp->mem_sz  = sz;\n      mp->name    = name;\n      mp->bl_sz   = block_size;\n      mp->bl_cnt  = block_count;\n      mp->n       = 0U;\n\n      /* Set heap allocated memory flags */\n      mp->status = MPOOL_STATUS;\n\n      if (mem_cb == 0) {\n        /* Control block on heap */\n        mp->status |= 1U;\n      }\n      if (mem_mp == 0) {\n        /* Memory array on heap */\n        mp->status |= 2U;\n      }\n    }\n    else {\n      /* Memory pool cannot be created, release allocated resources */\n      if ((mem_cb == 0) && (mp != NULL)) {\n        /* Free control block memory */\n        vPortFree (mp);\n      }\n      mp = NULL;\n    }\n  }\n\n  return (mp);\n}\n\nconst char *osMemoryPoolGetName (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp = (osMemoryPoolId_t)mp_id;\n  const char *p;\n\n  if (IS_IRQ()) {\n    p = NULL;\n  }\n  else if (mp_id == NULL) {\n    p = NULL;\n  }\n  else {\n    p = mp->name;\n  }\n\n  return (p);\n}\n\nvoid *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout) {\n  MemPool_t *mp;\n  void *block;\n  uint32_t isrm;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    block = NULL;\n  }\n  else {\n    block = NULL;\n\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {\n      if (IS_IRQ()) {\n        if (timeout == 0U) {\n          if (xSemaphoreTakeFromISR (mp->sem, NULL) == pdTRUE) {\n            if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {\n              isrm  = taskENTER_CRITICAL_FROM_ISR();\n\n              /* Get a block from the free-list */\n              block = AllocBlock(mp);\n\n              if (block == NULL) {\n                /* List of free blocks is empty, 'create' new block */\n                block = CreateBlock(mp);\n              }\n\n              taskEXIT_CRITICAL_FROM_ISR(isrm);\n            }\n          }\n        }\n      }\n      else {\n        if (xSemaphoreTake (mp->sem, (TickType_t)timeout) == pdTRUE) {\n          if ((mp->status & MPOOL_STATUS) == MPOOL_STATUS) {\n            taskENTER_CRITICAL();\n\n            /* Get a block from the free-list */\n            block = AllocBlock(mp);\n\n            if (block == NULL) {\n              /* List of free blocks is empty, 'create' new block */\n              block = CreateBlock(mp);\n            }\n\n            taskEXIT_CRITICAL();\n          }\n        }\n      }\n    }\n  }\n\n  return (block);\n}\n\nosStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block) {\n  MemPool_t *mp;\n  osStatus_t stat;\n  uint32_t isrm;\n  BaseType_t yield;\n\n  if ((mp_id == NULL) || (block == NULL)) {\n    /* Invalid input parameters */\n    stat = osErrorParameter;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {\n      /* Invalid object status */\n      stat = osErrorResource;\n    }\n    else if ((block < (void *)&mp->mem_arr[0]) || (block > (void*)&mp->mem_arr[mp->mem_sz-1])) {\n      /* Block pointer outside of memory array area */\n      stat = osErrorParameter;\n    }\n    else {\n      stat = osOK;\n\n      if (IS_IRQ()) {\n        if (uxSemaphoreGetCountFromISR (mp->sem) == mp->bl_cnt) {\n          stat = osErrorResource;\n        }\n        else {\n          isrm = taskENTER_CRITICAL_FROM_ISR();\n\n          /* Add block to the list of free blocks */\n          FreeBlock(mp, block);\n\n          taskEXIT_CRITICAL_FROM_ISR(isrm);\n\n          yield = pdFALSE;\n          xSemaphoreGiveFromISR (mp->sem, &yield);\n          portYIELD_FROM_ISR (yield);\n        }\n      }\n      else {\n        if (uxSemaphoreGetCount (mp->sem) == mp->bl_cnt) {\n          stat = osErrorResource;\n        }\n        else {\n          taskENTER_CRITICAL();\n\n          /* Add block to the list of free blocks */\n          FreeBlock(mp, block);\n\n          taskEXIT_CRITICAL();\n\n          xSemaphoreGive (mp->sem);\n        }\n      }\n    }\n  }\n\n  return (stat);\n}\n\nuint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp;\n  uint32_t  n;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    n = 0U;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {\n      /* Invalid object status */\n      n = 0U;\n    }\n    else {\n      n = mp->bl_cnt;\n    }\n  }\n\n  /* Return maximum number of memory blocks */\n  return (n);\n}\n\nuint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp;\n  uint32_t  sz;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    sz = 0U;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {\n      /* Invalid object status */\n      sz = 0U;\n    }\n    else {\n      sz = mp->bl_sz;\n    }\n  }\n\n  /* Return memory block size in bytes */\n  return (sz);\n}\n\nuint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp;\n  uint32_t  n;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    n = 0U;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {\n      /* Invalid object status */\n      n = 0U;\n    }\n    else {\n      if (IS_IRQ()) {\n        n = uxSemaphoreGetCountFromISR (mp->sem);\n      } else {\n        n = uxSemaphoreGetCount        (mp->sem);\n      }\n\n      n = mp->bl_cnt - n;\n    }\n  }\n\n  /* Return number of memory blocks used */\n  return (n);\n}\n\nuint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp;\n  uint32_t  n;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    n = 0U;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    if ((mp->status & MPOOL_STATUS) != MPOOL_STATUS) {\n      /* Invalid object status */\n      n = 0U;\n    }\n    else {\n      if (IS_IRQ()) {\n        n = uxSemaphoreGetCountFromISR (mp->sem);\n      } else {\n        n = uxSemaphoreGetCount        (mp->sem);\n      }\n    }\n  }\n\n  /* Return number of memory blocks available */\n  return (n);\n}\n\nosStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id) {\n  MemPool_t *mp;\n  osStatus_t stat;\n\n  if (mp_id == NULL) {\n    /* Invalid input parameters */\n    stat = osErrorParameter;\n  }\n  else if (IS_IRQ()) {\n    stat = osErrorISR;\n  }\n  else {\n    mp = (MemPool_t *)mp_id;\n\n    taskENTER_CRITICAL();\n\n    /* Invalidate control block status */\n    mp->status  = mp->status & 3U;\n\n    /* Wake-up tasks waiting for pool semaphore */\n    while (xSemaphoreGive (mp->sem) == pdTRUE);\n\n    mp->head    = NULL;\n    mp->bl_sz   = 0U;\n    mp->bl_cnt  = 0U;\n\n    if ((mp->status & 2U) != 0U) {\n      /* Memory pool array allocated on heap */\n      vPortFree (mp->mem_arr);\n    }\n    if ((mp->status & 1U) != 0U) {\n      /* Memory pool control block allocated on heap */\n      vPortFree (mp);\n    }\n\n    taskEXIT_CRITICAL();\n\n    stat = osOK;\n  }\n\n  return (stat);\n}\n\n/*\n  Create new block given according to the current block index.\n*/\nstatic void *CreateBlock (MemPool_t *mp) {\n  MemPoolBlock_t *p = NULL;\n\n  if (mp->n < mp->bl_cnt) {\n    /* Unallocated blocks exist, set pointer to new block */\n    p = (void *)(mp->mem_arr + (mp->bl_sz * mp->n));\n\n    /* Increment block index */\n    mp->n += 1U;\n  }\n\n  return (p);\n}\n\n/*\n  Allocate a block by reading the list of free blocks.\n*/\nstatic void *AllocBlock (MemPool_t *mp) {\n  MemPoolBlock_t *p = NULL;\n\n  if (mp->head != NULL) {\n    /* List of free block exists, get head block */\n    p = mp->head;\n\n    /* Head block is now next on the list */\n    mp->head = p->next;\n  }\n\n  return (p);\n}\n\n/*\n  Free block by putting it to the list of free blocks.\n*/\nstatic void FreeBlock (MemPool_t *mp, void *block) {\n  MemPoolBlock_t *p = block;\n\n  /* Store current head into block memory space */\n  p->next = mp->head;\n\n  /* Store current block as new head */\n  mp->head = p;\n}\n#endif /* FREERTOS_MPOOL_H_ */\n/*---------------------------------------------------------------------------*/\n\n/* Callback function prototypes */\nextern void vApplicationIdleHook (void);\nextern void vApplicationTickHook (void);\nextern void vApplicationMallocFailedHook (void);\nextern void vApplicationDaemonTaskStartupHook (void);\nextern void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName);\n\n/**\n  Dummy implementation of the callback function vApplicationIdleHook().\n*/\n#if (configUSE_IDLE_HOOK == 1)\n__WEAK void vApplicationIdleHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationTickHook().\n*/\n#if (configUSE_TICK_HOOK == 1)\n __WEAK void vApplicationTickHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationMallocFailedHook().\n*/\n#if (configUSE_MALLOC_FAILED_HOOK == 1)\n__WEAK void vApplicationMallocFailedHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationDaemonTaskStartupHook().\n*/\n#if (configUSE_DAEMON_TASK_STARTUP_HOOK == 1)\n__WEAK void vApplicationDaemonTaskStartupHook (void){}\n#endif\n\n/**\n  Dummy implementation of the callback function vApplicationStackOverflowHook().\n*/\n#if (configCHECK_FOR_STACK_OVERFLOW > 0)\n__WEAK void vApplicationStackOverflowHook (TaskHandle_t xTask, signed char *pcTaskName) {\n  (void)xTask;\n  (void)pcTaskName;\n  configASSERT(0);\n}\n#endif\n\n/*---------------------------------------------------------------------------*/\n#if (configSUPPORT_STATIC_ALLOCATION == 1)\n/* External Idle and Timer task static memory allocation functions */\nextern void vApplicationGetIdleTaskMemory  (StaticTask_t **ppxIdleTaskTCBBuffer,  StackType_t **ppxIdleTaskStackBuffer,  uint32_t *pulIdleTaskStackSize);\nextern void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize);\n\n/*\n  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION\n  equals to 1 and is required for static memory allocation support.\n*/\n__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {\n  /* Idle task control block and stack */\n  static StaticTask_t Idle_TCB;\n  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];\n\n  *ppxIdleTaskTCBBuffer   = &Idle_TCB;\n  *ppxIdleTaskStackBuffer = &Idle_Stack[0];\n  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;\n}\n\n/*\n  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION\n  equals to 1 and is required for static memory allocation support.\n*/\n__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {\n  /* Timer task control block and stack */\n  static StaticTask_t Timer_TCB;\n  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];\n\n  *ppxTimerTaskTCBBuffer   = &Timer_TCB;\n  *ppxTimerTaskStackBuffer = &Timer_Stack[0];\n  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;\n}\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.h",
    "content": "/* --------------------------------------------------------------------------\n * Portions Copyright © 2017 STMicroelectronics International N.V. All rights reserved.\n * Portions Copyright (c) 2013-2017 ARM Limited. All rights reserved.\n * --------------------------------------------------------------------------\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    cmsis_os2.h\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#ifndef CMSIS_OS2_H_\n#define CMSIS_OS2_H_\n\n#ifndef __NO_RETURN\n#if   defined(__CC_ARM)\n#define __NO_RETURN __declspec(noreturn)\n#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__GNUC__)\n#define __NO_RETURN __attribute__((__noreturn__))\n#elif defined(__ICCARM__)\n#define __NO_RETURN __noreturn\n#else\n#define __NO_RETURN\n#endif\n#endif\n\n#include <stdint.h>\n#include <stddef.h>\n\n#ifdef  __cplusplus\nextern \"C\"\n{\n#endif\n\n\n//  ==== Enumerations, structures, defines ====\n\n/// Version information.\ntypedef struct {\n  uint32_t                       api;   ///< API version (major.minor.rev: mmnnnrrrr dec).\n  uint32_t                    kernel;   ///< Kernel version (major.minor.rev: mmnnnrrrr dec).\n} osVersion_t;\n\n/// Kernel state.\ntypedef enum {\n  osKernelInactive        =  0,         ///< Inactive.\n  osKernelReady           =  1,         ///< Ready.\n  osKernelRunning         =  2,         ///< Running.\n  osKernelLocked          =  3,         ///< Locked.\n  osKernelSuspended       =  4,         ///< Suspended.\n  osKernelError           = -1,         ///< Error.\n  osKernelReserved        = 0x7FFFFFFFU ///< Prevents enum down-size compiler optimization.\n} osKernelState_t;\n\n/// Thread state.\ntypedef enum {\n  osThreadInactive        =  0,         ///< Inactive.\n  osThreadReady           =  1,         ///< Ready.\n  osThreadRunning         =  2,         ///< Running.\n  osThreadBlocked         =  3,         ///< Blocked.\n  osThreadTerminated      =  4,         ///< Terminated.\n  osThreadError           = -1,         ///< Error.\n  osThreadReserved        = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osThreadState_t;\n\n/// Priority values.\ntypedef enum {\n  osPriorityNone          =  0,         ///< No priority (not initialized).\n  osPriorityIdle          =  1,         ///< Reserved for Idle thread.\n  osPriorityLow           =  8,         ///< Priority: low\n  osPriorityLow1          =  8+1,       ///< Priority: low + 1\n  osPriorityLow2          =  8+2,       ///< Priority: low + 2\n  osPriorityLow3          =  8+3,       ///< Priority: low + 3\n  osPriorityLow4          =  8+4,       ///< Priority: low + 4\n  osPriorityLow5          =  8+5,       ///< Priority: low + 5\n  osPriorityLow6          =  8+6,       ///< Priority: low + 6\n  osPriorityLow7          =  8+7,       ///< Priority: low + 7\n  osPriorityBelowNormal   = 16,         ///< Priority: below normal\n  osPriorityBelowNormal1  = 16+1,       ///< Priority: below normal + 1\n  osPriorityBelowNormal2  = 16+2,       ///< Priority: below normal + 2\n  osPriorityBelowNormal3  = 16+3,       ///< Priority: below normal + 3\n  osPriorityBelowNormal4  = 16+4,       ///< Priority: below normal + 4\n  osPriorityBelowNormal5  = 16+5,       ///< Priority: below normal + 5\n  osPriorityBelowNormal6  = 16+6,       ///< Priority: below normal + 6\n  osPriorityBelowNormal7  = 16+7,       ///< Priority: below normal + 7\n  osPriorityNormal        = 24,         ///< Priority: normal\n  osPriorityNormal1       = 24+1,       ///< Priority: normal + 1\n  osPriorityNormal2       = 24+2,       ///< Priority: normal + 2\n  osPriorityNormal3       = 24+3,       ///< Priority: normal + 3\n  osPriorityNormal4       = 24+4,       ///< Priority: normal + 4\n  osPriorityNormal5       = 24+5,       ///< Priority: normal + 5\n  osPriorityNormal6       = 24+6,       ///< Priority: normal + 6\n  osPriorityNormal7       = 24+7,       ///< Priority: normal + 7\n  osPriorityAboveNormal   = 32,         ///< Priority: above normal\n  osPriorityAboveNormal1  = 32+1,       ///< Priority: above normal + 1\n  osPriorityAboveNormal2  = 32+2,       ///< Priority: above normal + 2\n  osPriorityAboveNormal3  = 32+3,       ///< Priority: above normal + 3\n  osPriorityAboveNormal4  = 32+4,       ///< Priority: above normal + 4\n  osPriorityAboveNormal5  = 32+5,       ///< Priority: above normal + 5\n  osPriorityAboveNormal6  = 32+6,       ///< Priority: above normal + 6\n  osPriorityAboveNormal7  = 32+7,       ///< Priority: above normal + 7\n  osPriorityHigh          = 40,         ///< Priority: high\n  osPriorityHigh1         = 40+1,       ///< Priority: high + 1\n  osPriorityHigh2         = 40+2,       ///< Priority: high + 2\n  osPriorityHigh3         = 40+3,       ///< Priority: high + 3\n  osPriorityHigh4         = 40+4,       ///< Priority: high + 4\n  osPriorityHigh5         = 40+5,       ///< Priority: high + 5\n  osPriorityHigh6         = 40+6,       ///< Priority: high + 6\n  osPriorityHigh7         = 40+7,       ///< Priority: high + 7\n  osPriorityRealtime      = 48,         ///< Priority: realtime\n  osPriorityRealtime1     = 48+1,       ///< Priority: realtime + 1\n  osPriorityRealtime2     = 48+2,       ///< Priority: realtime + 2\n  osPriorityRealtime3     = 48+3,       ///< Priority: realtime + 3\n  osPriorityRealtime4     = 48+4,       ///< Priority: realtime + 4\n  osPriorityRealtime5     = 48+5,       ///< Priority: realtime + 5\n  osPriorityRealtime6     = 48+6,       ///< Priority: realtime + 6\n  osPriorityRealtime7     = 48+7,       ///< Priority: realtime + 7\n  osPriorityISR           = 56,         ///< Reserved for ISR deferred thread.\n  osPriorityError         = -1,         ///< System cannot determine priority or illegal priority.\n  osPriorityReserved      = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osPriority_t;\n\n/// Entry point of a thread.\ntypedef void (*osThreadFunc_t) (void *argument);\n\n/// Timer callback function.\ntypedef void (*osTimerFunc_t) (void *argument);\n\n/// Timer type.\ntypedef enum {\n  osTimerOnce               = 0,          ///< One-shot timer.\n  osTimerPeriodic           = 1           ///< Repeating timer.\n} osTimerType_t;\n\n// Timeout value.\n#define osWaitForever         0xFFFFFFFFU ///< Wait forever timeout value.\n\n// Flags options (\\ref osThreadFlagsWait and \\ref osEventFlagsWait).\n#define osFlagsWaitAny        0x00000000U ///< Wait for any flag (default).\n#define osFlagsWaitAll        0x00000001U ///< Wait for all flags.\n#define osFlagsNoClear        0x00000002U ///< Do not clear flags which have been specified to wait for.\n\n// Flags errors (returned by osThreadFlagsXxxx and osEventFlagsXxxx).\n#define osFlagsError          0x80000000U ///< Error indicator.\n#define osFlagsErrorUnknown   0xFFFFFFFFU ///< osError (-1).\n#define osFlagsErrorTimeout   0xFFFFFFFEU ///< osErrorTimeout (-2).\n#define osFlagsErrorResource  0xFFFFFFFDU ///< osErrorResource (-3).\n#define osFlagsErrorParameter 0xFFFFFFFCU ///< osErrorParameter (-4).\n#define osFlagsErrorISR       0xFFFFFFFAU ///< osErrorISR (-6).\n\n// Thread attributes (attr_bits in \\ref osThreadAttr_t).\n#define osThreadDetached      0x00000000U ///< Thread created in detached mode (default)\n#define osThreadJoinable      0x00000001U ///< Thread created in joinable mode\n\n// Mutex attributes (attr_bits in \\ref osMutexAttr_t).\n#define osMutexRecursive      0x00000001U ///< Recursive mutex.\n#define osMutexPrioInherit    0x00000002U ///< Priority inherit protocol.\n#define osMutexRobust         0x00000008U ///< Robust mutex.\n\n/// Status code values returned by CMSIS-RTOS functions.\ntypedef enum {\n  osOK                      =  0,         ///< Operation completed successfully.\n  osError                   = -1,         ///< Unspecified RTOS error: run-time error but no other error message fits.\n  osErrorTimeout            = -2,         ///< Operation not completed within the timeout period.\n  osErrorResource           = -3,         ///< Resource not available.\n  osErrorParameter          = -4,         ///< Parameter error.\n  osErrorNoMemory           = -5,         ///< System is out of memory: it was impossible to allocate or reserve memory for the operation.\n  osErrorISR                = -6,         ///< Not allowed in ISR context: the function cannot be called from interrupt service routines.\n  osStatusReserved          = 0x7FFFFFFF  ///< Prevents enum down-size compiler optimization.\n} osStatus_t;\n\n\n/// \\details Thread ID identifies the thread.\ntypedef void *osThreadId_t;\n\n/// \\details Timer ID identifies the timer.\ntypedef void *osTimerId_t;\n\n/// \\details Event Flags ID identifies the event flags.\ntypedef void *osEventFlagsId_t;\n\n/// \\details Mutex ID identifies the mutex.\ntypedef void *osMutexId_t;\n\n/// \\details Semaphore ID identifies the semaphore.\ntypedef void *osSemaphoreId_t;\n\n/// \\details Memory Pool ID identifies the memory pool.\ntypedef void *osMemoryPoolId_t;\n\n/// \\details Message Queue ID identifies the message queue.\ntypedef void *osMessageQueueId_t;\n\n\n#ifndef TZ_MODULEID_T\n#define TZ_MODULEID_T\n/// \\details Data type that identifies secure software modules called by a process.\ntypedef uint32_t TZ_ModuleId_t;\n#endif\n\n\n/// Attributes structure for thread.\ntypedef struct {\n  const char                   *name;   ///< name of the thread\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                   *stack_mem;    ///< memory for stack\n  uint32_t                stack_size;   ///< size of stack\n  osPriority_t              priority;   ///< initial thread priority (default: osPriorityNormal)\n  TZ_ModuleId_t            tz_module;   ///< TrustZone module identifier\n  uint32_t                  reserved;   ///< reserved (must be 0)\n} osThreadAttr_t;\n\n/// Attributes structure for timer.\ntypedef struct {\n  const char                   *name;   ///< name of the timer\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osTimerAttr_t;\n\n/// Attributes structure for event flags.\ntypedef struct {\n  const char                   *name;   ///< name of the event flags\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osEventFlagsAttr_t;\n\n/// Attributes structure for mutex.\ntypedef struct {\n  const char                   *name;   ///< name of the mutex\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osMutexAttr_t;\n\n/// Attributes structure for semaphore.\ntypedef struct {\n  const char                   *name;   ///< name of the semaphore\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n} osSemaphoreAttr_t;\n\n/// Attributes structure for memory pool.\ntypedef struct {\n  const char                   *name;   ///< name of the memory pool\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mp_mem;    ///< memory for data storage\n  uint32_t                   mp_size;   ///< size of provided memory for data storage\n} osMemoryPoolAttr_t;\n\n/// Attributes structure for message queue.\ntypedef struct {\n  const char                   *name;   ///< name of the message queue\n  uint32_t                 attr_bits;   ///< attribute bits\n  void                      *cb_mem;    ///< memory for control block\n  uint32_t                   cb_size;   ///< size of provided memory for control block\n  void                      *mq_mem;    ///< memory for data storage\n  uint32_t                   mq_size;   ///< size of provided memory for data storage\n} osMessageQueueAttr_t;\n\n\n//  ==== Kernel Management Functions ====\n\n/// Initialize the RTOS Kernel.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelInitialize (void);\n\n///  Get RTOS Kernel Information.\n/// \\param[out]    version       pointer to buffer for retrieving version information.\n/// \\param[out]    id_buf        pointer to buffer for retrieving kernel identification string.\n/// \\param[in]     id_size       size of buffer for kernel identification string.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelGetInfo (osVersion_t *version, char *id_buf, uint32_t id_size);\n\n/// Get the current RTOS Kernel state.\n/// \\return current RTOS Kernel state.\nosKernelState_t osKernelGetState (void);\n\n/// Start the RTOS Kernel scheduler.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osKernelStart (void);\n\n/// Lock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelLock (void);\n\n/// Unlock the RTOS Kernel scheduler.\n/// \\return previous lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelUnlock (void);\n\n/// Restore the RTOS Kernel scheduler lock state.\n/// \\param[in]     lock          lock state obtained by \\ref osKernelLock or \\ref osKernelUnlock.\n/// \\return new lock state (1 - locked, 0 - not locked, error code if negative).\nint32_t osKernelRestoreLock (int32_t lock);\n\n/// Suspend the RTOS Kernel scheduler.\n/// \\return time in ticks, for how long the system can sleep or power-down.\nuint32_t osKernelSuspend (void);\n\n/// Resume the RTOS Kernel scheduler.\n/// \\param[in]     sleep_ticks   time in ticks for how long the system was in sleep or power-down mode.\nvoid osKernelResume (uint32_t sleep_ticks);\n\n/// Get the RTOS kernel tick count.\n/// \\return RTOS kernel current tick count.\nuint32_t osKernelGetTickCount (void);\n\n/// Get the RTOS kernel tick frequency.\n/// \\return frequency of the kernel tick in hertz, i.e. kernel ticks per second.\nuint32_t osKernelGetTickFreq (void);\n\n/// Get the RTOS kernel system timer count.\n/// \\return RTOS kernel current system timer count as 32-bit value.\nuint32_t osKernelGetSysTimerCount (void);\n\n/// Get the RTOS kernel system timer frequency.\n/// \\return frequency of the system timer in hertz, i.e. timer ticks per second.\nuint32_t osKernelGetSysTimerFreq (void);\n\n\n//  ==== Thread Management Functions ====\n\n/// Create a thread and add it to Active Threads.\n/// \\param[in]     func          thread function.\n/// \\param[in]     argument      pointer that is passed to the thread function as start argument.\n/// \\param[in]     attr          thread attributes; NULL: default values.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr);\n\n/// Get name of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return name as NULL terminated string.\nconst char *osThreadGetName (osThreadId_t thread_id);\n\n/// Return the thread ID of the current running thread.\n/// \\return thread ID for reference by other functions or NULL in case of error.\nosThreadId_t osThreadGetId (void);\n\n/// Get current thread state of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current thread state of the specified thread.\nosThreadState_t osThreadGetState (osThreadId_t thread_id);\n\n/// Get stack size of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return stack size in bytes.\nuint32_t osThreadGetStackSize (osThreadId_t thread_id);\n\n/// Get available stack space of a thread based on stack watermark recording during execution.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return remaining stack space in bytes.\nuint32_t osThreadGetStackSpace (osThreadId_t thread_id);\n\n/// Change priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     priority      new priority value for the thread function.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSetPriority (osThreadId_t thread_id, osPriority_t priority);\n\n/// Get current priority of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return current priority value of the specified thread.\nosPriority_t osThreadGetPriority (osThreadId_t thread_id);\n\n/// Pass control to next thread that is in state \\b READY.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadYield (void);\n\n/// Suspend execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadSuspend (osThreadId_t thread_id);\n\n/// Resume execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadResume (osThreadId_t thread_id);\n\n/// Detach a thread (thread storage can be reclaimed when thread terminates).\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadDetach (osThreadId_t thread_id);\n\n/// Wait for specified thread to terminate.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadJoin (osThreadId_t thread_id);\n\n/// Terminate execution of current running thread.\n__NO_RETURN void osThreadExit (void);\n\n/// Terminate execution of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osThreadTerminate (osThreadId_t thread_id);\n\n/// Get number of active threads.\n/// \\return number of active threads.\nuint32_t osThreadGetCount (void);\n\n/// Enumerate active threads.\n/// \\param[out]    thread_array  pointer to array for retrieving thread IDs.\n/// \\param[in]     array_items   maximum number of items in array for retrieving thread IDs.\n/// \\return number of enumerated threads.\nuint32_t osThreadEnumerate (osThreadId_t *thread_array, uint32_t array_items);\n\n\n//  ==== Thread Flags Functions ====\n\n/// Set the specified Thread Flags of a thread.\n/// \\param[in]     thread_id     thread ID obtained by \\ref osThreadNew or \\ref osThreadGetId.\n/// \\param[in]     flags         specifies the flags of the thread that shall be set.\n/// \\return thread flags after setting or error code if highest bit set.\nuint32_t osThreadFlagsSet (osThreadId_t thread_id, uint32_t flags);\n\n/// Clear the specified Thread Flags of current running thread.\n/// \\param[in]     flags         specifies the flags of the thread that shall be cleared.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsClear (uint32_t flags);\n\n/// Get the current Thread Flags of current running thread.\n/// \\return current thread flags.\nuint32_t osThreadFlagsGet (void);\n\n/// Wait for one or more Thread Flags of the current running thread to become signaled.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return thread flags before clearing or error code if highest bit set.\nuint32_t osThreadFlagsWait (uint32_t flags, uint32_t options, uint32_t timeout);\n\n\n//  ==== Generic Wait Functions ====\n\n/// Wait for Timeout (Time Delay).\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelay (uint32_t ticks);\n\n/// Wait until specified time.\n/// \\param[in]     ticks         absolute time in ticks\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osDelayUntil (uint32_t ticks);\n\n\n//  ==== Timer Management Functions ====\n\n/// Create and Initialize a timer.\n/// \\param[in]     func          function pointer to callback function.\n/// \\param[in]     type          \\ref osTimerOnce for one-shot or \\ref osTimerPeriodic for periodic behavior.\n/// \\param[in]     argument      argument to the timer callback function.\n/// \\param[in]     attr          timer attributes; NULL: default values.\n/// \\return timer ID for reference by other functions or NULL in case of error.\nosTimerId_t osTimerNew (osTimerFunc_t func, osTimerType_t type, void *argument, const osTimerAttr_t *attr);\n\n/// Get name of a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return name as NULL terminated string.\nconst char *osTimerGetName (osTimerId_t timer_id);\n\n/// Start or restart a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\param[in]     ticks         \\ref CMSIS_RTOS_TimeOutValue \"time ticks\" value of the timer.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStart (osTimerId_t timer_id, uint32_t ticks);\n\n/// Stop a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerStop (osTimerId_t timer_id);\n\n/// Check if a timer is running.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return 0 not running, 1 running.\nuint32_t osTimerIsRunning (osTimerId_t timer_id);\n\n/// Delete a timer.\n/// \\param[in]     timer_id      timer ID obtained by \\ref osTimerNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osTimerDelete (osTimerId_t timer_id);\n\n\n//  ==== Event Flags Management Functions ====\n\n/// Create and Initialize an Event Flags object.\n/// \\param[in]     attr          event flags attributes; NULL: default values.\n/// \\return event flags ID for reference by other functions or NULL in case of error.\nosEventFlagsId_t osEventFlagsNew (const osEventFlagsAttr_t *attr);\n\n/// Get name of an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return name as NULL terminated string.\nconst char *osEventFlagsGetName (osEventFlagsId_t ef_id);\n\n/// Set the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be set.\n/// \\return event flags after setting or error code if highest bit set.\nuint32_t osEventFlagsSet (osEventFlagsId_t ef_id, uint32_t flags);\n\n/// Clear the specified Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags that shall be cleared.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsClear (osEventFlagsId_t ef_id, uint32_t flags);\n\n/// Get the current Event Flags.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return current event flags.\nuint32_t osEventFlagsGet (osEventFlagsId_t ef_id);\n\n/// Wait for one or more Event Flags to become signaled.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\param[in]     flags         specifies the flags to wait for.\n/// \\param[in]     options       specifies flags options (osFlagsXxxx).\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return event flags before clearing or error code if highest bit set.\nuint32_t osEventFlagsWait (osEventFlagsId_t ef_id, uint32_t flags, uint32_t options, uint32_t timeout);\n\n/// Delete an Event Flags object.\n/// \\param[in]     ef_id         event flags ID obtained by \\ref osEventFlagsNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osEventFlagsDelete (osEventFlagsId_t ef_id);\n\n\n//  ==== Mutex Management Functions ====\n\n/// Create and Initialize a Mutex object.\n/// \\param[in]     attr          mutex attributes; NULL: default values.\n/// \\return mutex ID for reference by other functions or NULL in case of error.\nosMutexId_t osMutexNew (const osMutexAttr_t *attr);\n\n/// Get name of a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return name as NULL terminated string.\nconst char *osMutexGetName (osMutexId_t mutex_id);\n\n/// Acquire a Mutex or timeout if it is locked.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexAcquire (osMutexId_t mutex_id, uint32_t timeout);\n\n/// Release a Mutex that was acquired by \\ref osMutexAcquire.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexRelease (osMutexId_t mutex_id);\n\n/// Get Thread which owns a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return thread ID of owner thread or NULL when mutex was not acquired.\nosThreadId_t osMutexGetOwner (osMutexId_t mutex_id);\n\n/// Delete a Mutex object.\n/// \\param[in]     mutex_id      mutex ID obtained by \\ref osMutexNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMutexDelete (osMutexId_t mutex_id);\n\n\n//  ==== Semaphore Management Functions ====\n\n/// Create and Initialize a Semaphore object.\n/// \\param[in]     max_count     maximum number of available tokens.\n/// \\param[in]     initial_count initial number of available tokens.\n/// \\param[in]     attr          semaphore attributes; NULL: default values.\n/// \\return semaphore ID for reference by other functions or NULL in case of error.\nosSemaphoreId_t osSemaphoreNew (uint32_t max_count, uint32_t initial_count, const osSemaphoreAttr_t *attr);\n\n/// Get name of a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return name as NULL terminated string.\nconst char *osSemaphoreGetName (osSemaphoreId_t semaphore_id);\n\n/// Acquire a Semaphore token or timeout if no tokens are available.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreAcquire (osSemaphoreId_t semaphore_id, uint32_t timeout);\n\n/// Release a Semaphore token up to the initial maximum count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreRelease (osSemaphoreId_t semaphore_id);\n\n/// Get current Semaphore token count.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return number of tokens available.\nuint32_t osSemaphoreGetCount (osSemaphoreId_t semaphore_id);\n\n/// Delete a Semaphore object.\n/// \\param[in]     semaphore_id  semaphore ID obtained by \\ref osSemaphoreNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osSemaphoreDelete (osSemaphoreId_t semaphore_id);\n\n\n//  ==== Memory Pool Management Functions ====\n\n/// Create and Initialize a Memory Pool object.\n/// \\param[in]     block_count   maximum number of memory blocks in memory pool.\n/// \\param[in]     block_size    memory block size in bytes.\n/// \\param[in]     attr          memory pool attributes; NULL: default values.\n/// \\return memory pool ID for reference by other functions or NULL in case of error.\nosMemoryPoolId_t osMemoryPoolNew (uint32_t block_count, uint32_t block_size, const osMemoryPoolAttr_t *attr);\n\n/// Get name of a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return name as NULL terminated string.\nconst char *osMemoryPoolGetName (osMemoryPoolId_t mp_id);\n\n/// Allocate a memory block from a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return address of the allocated memory block or NULL in case of no memory is available.\nvoid *osMemoryPoolAlloc (osMemoryPoolId_t mp_id, uint32_t timeout);\n\n/// Return an allocated memory block back to a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\param[in]     block         address of the allocated memory block to be returned to the memory pool.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolFree (osMemoryPoolId_t mp_id, void *block);\n\n/// Get maximum number of memory blocks in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return maximum number of memory blocks.\nuint32_t osMemoryPoolGetCapacity (osMemoryPoolId_t mp_id);\n\n/// Get memory block size in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return memory block size in bytes.\nuint32_t osMemoryPoolGetBlockSize (osMemoryPoolId_t mp_id);\n\n/// Get number of memory blocks used in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks used.\nuint32_t osMemoryPoolGetCount (osMemoryPoolId_t mp_id);\n\n/// Get number of memory blocks available in a Memory Pool.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return number of memory blocks available.\nuint32_t osMemoryPoolGetSpace (osMemoryPoolId_t mp_id);\n\n/// Delete a Memory Pool object.\n/// \\param[in]     mp_id         memory pool ID obtained by \\ref osMemoryPoolNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMemoryPoolDelete (osMemoryPoolId_t mp_id);\n\n\n//  ==== Message Queue Management Functions ====\n\n/// Create and Initialize a Message Queue object.\n/// \\param[in]     msg_count     maximum number of messages in queue.\n/// \\param[in]     msg_size      maximum message size in bytes.\n/// \\param[in]     attr          message queue attributes; NULL: default values.\n/// \\return message queue ID for reference by other functions or NULL in case of error.\nosMessageQueueId_t osMessageQueueNew (uint32_t msg_count, uint32_t msg_size, const osMessageQueueAttr_t *attr);\n\n/// Get name of a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return name as NULL terminated string.\nconst char *osMessageQueueGetName (osMessageQueueId_t mq_id);\n\n/// Put a Message into a Queue or timeout if Queue is full.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[in]     msg_ptr       pointer to buffer with message to put into a queue.\n/// \\param[in]     msg_prio      message priority.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueuePut (osMessageQueueId_t mq_id, const void *msg_ptr, uint8_t msg_prio, uint32_t timeout);\n\n/// Get a Message from a Queue or timeout if Queue is empty.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\param[out]    msg_ptr       pointer to buffer for message to get from a queue.\n/// \\param[out]    msg_prio      pointer to buffer for message priority or NULL.\n/// \\param[in]     timeout       \\ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueGet (osMessageQueueId_t mq_id, void *msg_ptr, uint8_t *msg_prio, uint32_t timeout);\n\n/// Get maximum number of messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum number of messages.\nuint32_t osMessageQueueGetCapacity (osMessageQueueId_t mq_id);\n\n/// Get maximum message size in a Memory Pool.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return maximum message size in bytes.\nuint32_t osMessageQueueGetMsgSize (osMessageQueueId_t mq_id);\n\n/// Get number of queued messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of queued messages.\nuint32_t osMessageQueueGetCount (osMessageQueueId_t mq_id);\n\n/// Get number of available slots for messages in a Message Queue.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return number of available slots for messages.\nuint32_t osMessageQueueGetSpace (osMessageQueueId_t mq_id);\n\n/// Reset a Message Queue to initial empty state.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueReset (osMessageQueueId_t mq_id);\n\n/// Delete a Message Queue object.\n/// \\param[in]     mq_id         message queue ID obtained by \\ref osMessageQueueNew.\n/// \\return status code that indicates the execution status of the function.\nosStatus_t osMessageQueueDelete (osMessageQueueId_t mq_id);\n\n\n#ifdef  __cplusplus\n}\n#endif\n\n#endif  // CMSIS_OS2_H_\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_mpool.h",
    "content": "/* --------------------------------------------------------------------------\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    freertos_mpool.h\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#ifndef FREERTOS_MPOOL_H_\n#define FREERTOS_MPOOL_H_\n\n#include <stdint.h>\n#include \"FreeRTOS.h\"\n#include \"semphr.h\"\n\n/* Memory Pool implementation definitions */\n#define MPOOL_STATUS              0x5EED0000U\n\n/* Memory Block header */\ntypedef struct {\n  void *next;                   /* Pointer to next block  */\n} MemPoolBlock_t;\n\n/* Memory Pool control block */\ntypedef struct MemPoolDef_t {\n  MemPoolBlock_t    *head;      /* Pointer to head block   */\n  SemaphoreHandle_t  sem;       /* Pool semaphore handle   */\n  uint8_t           *mem_arr;   /* Pool memory array       */\n  uint32_t           mem_sz;    /* Pool memory array size  */\n  const char        *name;      /* Pointer to name string  */\n  uint32_t           bl_sz;     /* Size of a single block  */\n  uint32_t           bl_cnt;    /* Number of blocks        */\n  uint32_t           n;         /* Block allocation index  */\n  volatile uint32_t  status;    /* Object status flags     */\n#if (configSUPPORT_STATIC_ALLOCATION == 1)\n  StaticSemaphore_t  mem_sem;   /* Semaphore object memory */\n#endif\n} MemPool_t;\n\n/* No need to hide static object type, just align to coding style */\n#define StaticMemPool_t         MemPool_t\n\n/* Define memory pool control block size */\n#define MEMPOOL_CB_SIZE         (sizeof(StaticMemPool_t))\n\n/* Define size of the byte array required to create count of blocks of given size */\n#define MEMPOOL_ARR_SIZE(bl_count, bl_size) (((((bl_size) + (4 - 1)) / 4) * 4)*(bl_count))\n\n#endif /* FREERTOS_MPOOL_H_ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/freertos_os2.h",
    "content": "/* --------------------------------------------------------------------------\n * Copyright (c) 2013-2020 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n *\n *      Name:    freertos_os2.h\n *      Purpose: CMSIS RTOS2 wrapper for FreeRTOS\n *\n *---------------------------------------------------------------------------*/\n\n#ifndef FREERTOS_OS2_H_\n#define FREERTOS_OS2_H_\n\n#include <string.h>\n#include <stdint.h>\n\n#include \"FreeRTOS.h\"                   // ARM.FreeRTOS::RTOS:Core\n\n#include CMSIS_device_header\n\n/*\n  CMSIS-RTOS2 FreeRTOS image size optimization definitions.\n\n  Note: Definitions configUSE_OS2 can be used to optimize FreeRTOS image size when\n        certain functionality is not required when using CMSIS-RTOS2 API.\n        In general optimization decisions are left to the tool chain but in cases\n        when coding style prevents it to optimize the code following optional\n        definitions can be used.\n*/\n\n/*\n  Option to exclude CMSIS-RTOS2 functions osThreadSuspend and osThreadResume from\n  the application image.\n*/\n#ifndef configUSE_OS2_THREAD_SUSPEND_RESUME\n#define configUSE_OS2_THREAD_SUSPEND_RESUME   1\n#endif\n\n/*\n  Option to exclude CMSIS-RTOS2 function osThreadEnumerate from the application image.\n*/\n#ifndef configUSE_OS2_THREAD_ENUMERATE\n#define configUSE_OS2_THREAD_ENUMERATE        1\n#endif\n\n/*\n  Option to disable CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear\n  operation from ISR.\n*/\n#ifndef configUSE_OS2_EVENTFLAGS_FROM_ISR\n#define configUSE_OS2_EVENTFLAGS_FROM_ISR     1\n#endif\n\n/*\n  Option to exclude CMSIS-RTOS2 Thread Flags API functions from the application image.\n*/\n#ifndef configUSE_OS2_THREAD_FLAGS\n#define configUSE_OS2_THREAD_FLAGS            configUSE_TASK_NOTIFICATIONS\n#endif\n\n/*\n  Option to exclude CMSIS-RTOS2 Timer API functions from the application image.\n*/\n#ifndef configUSE_OS2_TIMER\n#define configUSE_OS2_TIMER                   configUSE_TIMERS\n#endif\n\n/*\n  Option to exclude CMSIS-RTOS2 Mutex API functions from the application image.\n*/\n#ifndef configUSE_OS2_MUTEX\n#define configUSE_OS2_MUTEX                   configUSE_MUTEXES\n#endif\n\n\n/*\n  CMSIS-RTOS2 FreeRTOS configuration check (FreeRTOSConfig.h).\n\n  Note: CMSIS-RTOS API requires functions included by using following definitions.\n        In case if certain API function is not used compiler will optimize it away.\n*/\n#if (INCLUDE_xSemaphoreGetMutexHolder == 0)\n  /*\n    CMSIS-RTOS2 function osMutexGetOwner uses FreeRTOS function xSemaphoreGetMutexHolder. In case if\n    osMutexGetOwner is not used in the application image, compiler will optimize it away.\n    Set #define INCLUDE_xSemaphoreGetMutexHolder 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_xSemaphoreGetMutexHolder must equal 1 to implement Mutex Management API.\"\n#endif\n#if (INCLUDE_vTaskDelay == 0)\n  /*\n    CMSIS-RTOS2 function osDelay uses FreeRTOS function vTaskDelay. In case if\n    osDelay is not used in the application image, compiler will optimize it away.\n    Set #define INCLUDE_vTaskDelay 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_vTaskDelay must equal 1 to implement Generic Wait Functions API.\"\n#endif\n#if (INCLUDE_vTaskDelayUntil == 0)\n  /*\n    CMSIS-RTOS2 function osDelayUntil uses FreeRTOS function vTaskDelayUntil. In case if\n    osDelayUntil is not used in the application image, compiler will optimize it away.\n    Set #define INCLUDE_vTaskDelayUntil 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_vTaskDelayUntil must equal 1 to implement Generic Wait Functions API.\"\n#endif\n#if (INCLUDE_vTaskDelete == 0)\n  /*\n    CMSIS-RTOS2 function osThreadTerminate and osThreadExit uses FreeRTOS function\n    vTaskDelete. In case if they are not used in the application image, compiler\n    will optimize them away.\n    Set #define INCLUDE_vTaskDelete 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_vTaskDelete must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_xTaskGetCurrentTaskHandle == 0)\n  /*\n    CMSIS-RTOS2 API uses FreeRTOS function xTaskGetCurrentTaskHandle to implement\n    functions osThreadGetId, osThreadFlagsClear and osThreadFlagsGet. In case if these\n    functions are not used in the application image, compiler will optimize them away.\n    Set #define INCLUDE_xTaskGetCurrentTaskHandle 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_xTaskGetCurrentTaskHandle must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_xTaskGetSchedulerState == 0)\n  /*\n    CMSIS-RTOS2 API uses FreeRTOS function xTaskGetSchedulerState to implement Kernel\n    tick handling and therefore it is vital that xTaskGetSchedulerState is included into\n    the application image.\n    Set #define INCLUDE_xTaskGetSchedulerState 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_xTaskGetSchedulerState must equal 1 to implement Kernel Information and Control API.\"\n#endif\n#if (INCLUDE_uxTaskGetStackHighWaterMark == 0)\n  /*\n    CMSIS-RTOS2 function osThreadGetStackSpace uses FreeRTOS function uxTaskGetStackHighWaterMark.\n    In case if osThreadGetStackSpace is not used in the application image, compiler will\n    optimize it away.\n    Set #define INCLUDE_uxTaskGetStackHighWaterMark 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_uxTaskGetStackHighWaterMark must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_uxTaskPriorityGet == 0)\n  /*\n    CMSIS-RTOS2 function osThreadGetPriority uses FreeRTOS function uxTaskPriorityGet. In case if\n    osThreadGetPriority is not used in the application image, compiler will optimize it away.\n    Set #define INCLUDE_uxTaskPriorityGet 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_uxTaskPriorityGet must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_vTaskPrioritySet == 0)\n  /*\n    CMSIS-RTOS2 function osThreadSetPriority uses FreeRTOS function vTaskPrioritySet. In case if\n    osThreadSetPriority is not used in the application image, compiler will optimize it away.\n    Set #define INCLUDE_vTaskPrioritySet 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_vTaskPrioritySet must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_eTaskGetState == 0)\n  /*\n    CMSIS-RTOS2 API uses FreeRTOS function vTaskDelayUntil to implement functions osThreadGetState\n    and osThreadTerminate. In case if these functions are not used in the application image,\n    compiler will optimize them away.\n    Set #define INCLUDE_eTaskGetState 1 to fix this error.\n  */\n  #error \"Definition INCLUDE_eTaskGetState must equal 1 to implement Thread Management API.\"\n#endif\n#if (INCLUDE_vTaskSuspend == 0)\n  /*\n    CMSIS-RTOS2 API uses FreeRTOS functions vTaskSuspend and vTaskResume to implement\n    functions osThreadSuspend and osThreadResume. In case if these functions are not\n    used in the application image, compiler will optimize them away.\n    Set #define INCLUDE_vTaskSuspend 1 to fix this error.\n\n    Alternatively, if the application does not use osThreadSuspend and\n    osThreadResume they can be excluded from the image code by setting:\n    #define configUSE_OS2_THREAD_SUSPEND_RESUME 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_THREAD_SUSPEND_RESUME == 1)\n    #error \"Definition INCLUDE_vTaskSuspend must equal 1 to implement Kernel Information and Control API.\"\n  #endif\n#endif\n#if (INCLUDE_xTimerPendFunctionCall == 0)\n  /*\n    CMSIS-RTOS2 function osEventFlagsSet and osEventFlagsClear, when called from\n    the ISR, call FreeRTOS functions xEventGroupSetBitsFromISR and\n    xEventGroupClearBitsFromISR which are only enabled if timers are operational and\n    xTimerPendFunctionCall in enabled.\n    Set #define INCLUDE_xTimerPendFunctionCall 1 and #define configUSE_TIMERS 1\n    to fix this error.\n\n    Alternatively, if the application does not use osEventFlagsSet and osEventFlagsClear\n    from the ISR their operation from ISR can be restricted by setting:\n    #define configUSE_OS2_EVENTFLAGS_FROM_ISR 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_EVENTFLAGS_FROM_ISR == 1)\n    #error \"Definition INCLUDE_xTimerPendFunctionCall must equal 1 to implement Event Flags API.\"\n  #endif\n#endif\n\n#if (configUSE_TIMERS == 0)\n  /*\n    CMSIS-RTOS2 Timer Management API functions use FreeRTOS timer functions to implement\n    timer management. In case if these functions are not used in the application image,\n    compiler will optimize them away.\n    Set #define configUSE_TIMERS 1 to fix this error.\n\n    Alternatively, if the application does not use timer functions they can be\n    excluded from the image code by setting:\n    #define configUSE_OS2_TIMER 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_TIMER == 1)\n    #error \"Definition configUSE_TIMERS must equal 1 to implement Timer Management API.\"\n  #endif\n#endif\n\n#if (configUSE_MUTEXES == 0)\n  /*\n    CMSIS-RTOS2 Mutex Management API functions use FreeRTOS mutex functions to implement\n    mutex management. In case if these functions are not used in the application image,\n    compiler will optimize them away.\n    Set #define configUSE_MUTEXES 1 to fix this error.\n\n    Alternatively, if the application does not use mutex functions they can be\n    excluded from the image code by setting:\n    #define configUSE_OS2_MUTEX 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_MUTEX == 1)\n    #error \"Definition configUSE_MUTEXES must equal 1 to implement Mutex Management API.\"\n  #endif\n#endif\n\n#if (configUSE_COUNTING_SEMAPHORES == 0)\n  /*\n    CMSIS-RTOS2 Memory Pool functions use FreeRTOS function xSemaphoreCreateCounting\n    to implement memory pools. In case if these functions are not used in the application image,\n    compiler will optimize them away.\n    Set #define configUSE_COUNTING_SEMAPHORES 1 to fix this error.\n  */\n  #error \"Definition configUSE_COUNTING_SEMAPHORES must equal 1 to implement Memory Pool API.\"\n#endif\n#if (configUSE_TASK_NOTIFICATIONS == 0)\n  /*\n    CMSIS-RTOS2 Thread Flags API functions use FreeRTOS Task Notification functions to implement\n    thread flag management. In case if these functions are not used in the application image,\n    compiler will optimize them away.\n    Set #define configUSE_TASK_NOTIFICATIONS 1 to fix this error.\n\n    Alternatively, if the application does not use thread flags functions they can be\n    excluded from the image code by setting:\n    #define configUSE_OS2_THREAD_FLAGS 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_THREAD_FLAGS == 1)\n    #error \"Definition configUSE_TASK_NOTIFICATIONS must equal 1 to implement Thread Flags API.\"\n  #endif\n#endif\n\n#if (configUSE_TRACE_FACILITY == 0)\n  /*\n    CMSIS-RTOS2 function osThreadEnumerate requires FreeRTOS function uxTaskGetSystemState\n    which is only enabled if configUSE_TRACE_FACILITY == 1.\n    Set #define configUSE_TRACE_FACILITY 1 to fix this error.\n\n    Alternatively, if the application does not use osThreadEnumerate it can be\n    excluded from the image code by setting:\n    #define configUSE_OS2_THREAD_ENUMERATE 0 (in FreeRTOSConfig.h)\n  */\n  #if (configUSE_OS2_THREAD_ENUMERATE == 1)\n    #error \"Definition configUSE_TRACE_FACILITY must equal 1 to implement osThreadEnumerate.\"\n  #endif\n#endif\n\n#if (configUSE_16_BIT_TICKS == 1)\n  /*\n    CMSIS-RTOS2 wrapper for FreeRTOS relies on 32-bit tick timer which is also optimal on\n    a 32-bit CPU architectures.\n    Set #define configUSE_16_BIT_TICKS 0 to fix this error.\n  */\n  #error \"Definition configUSE_16_BIT_TICKS must be zero to implement CMSIS-RTOS2 API.\"\n#endif\n\n#if (configMAX_PRIORITIES != 56)\n  /*\n    CMSIS-RTOS2 defines 56 different priorities (see osPriority_t) and portable CMSIS-RTOS2\n    implementation should implement the same number of priorities.\n    Set #define configMAX_PRIORITIES 56 to fix this error.\n  */\n  #error \"Definition configMAX_PRIORITIES must equal 56 to implement Thread Management API.\"\n#endif\n#if (configUSE_PORT_OPTIMISED_TASK_SELECTION != 0)\n  /*\n    CMSIS-RTOS2 requires handling of 56 different priorities (see osPriority_t) while FreeRTOS port\n    optimised selection for Cortex core only handles 32 different priorities.\n    Set #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 to fix this error.\n  */\n  #error \"Definition configUSE_PORT_OPTIMISED_TASK_SELECTION must be zero to implement Thread Management API.\"\n#endif\n\n#endif /* FREERTOS_OS2_H_ */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/croutine.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"croutine.h\"\n\n/* Remove the whole file is co-routines are not being used. */\n#if( configUSE_CO_ROUTINES != 0 )\n\n/*\n * Some kernel aware debuggers require data to be viewed to be global, rather\n * than file scope.\n */\n#ifdef portREMOVE_STATIC_QUALIFIER\n\t#define static\n#endif\n\n\n/* Lists for ready and blocked co-routines. --------------------*/\nstatic List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];\t/*< Prioritised ready co-routines. */\nstatic List_t xDelayedCoRoutineList1;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines. */\nstatic List_t xDelayedCoRoutineList2;\t\t\t\t\t\t\t\t\t/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */\nstatic List_t * pxDelayedCoRoutineList;\t\t\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used. */\nstatic List_t * pxOverflowDelayedCoRoutineList;\t\t\t\t\t\t\t/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */\nstatic List_t xPendingReadyCoRoutineList;\t\t\t\t\t\t\t\t/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */\n\n/* Other file private variables. --------------------------------*/\nCRCB_t * pxCurrentCoRoutine = NULL;\nstatic UBaseType_t uxTopCoRoutineReadyPriority = 0;\nstatic TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;\n\n/* The initial state of the co-routine when it is created. */\n#define corINITIAL_STATE\t( 0 )\n\n/*\n * Place the co-routine represented by pxCRCB into the appropriate ready queue\n * for the priority.  It is inserted at the end of the list.\n *\n * This macro accesses the co-routine ready lists and therefore must not be\n * used from within an ISR.\n */\n#define prvAddCoRoutineToReadyQueue( pxCRCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxTopCoRoutineReadyPriority = pxCRCB->uxPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tvListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );\t\\\n}\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first co-routine.\n */\nstatic void prvInitialiseCoRoutineLists( void );\n\n/*\n * Co-routines that are readied by an interrupt cannot be placed directly into\n * the ready lists (there is no mutual exclusion).  Instead they are placed in\n * in the pending ready list in order that they can later be moved to the ready\n * list by the co-routine scheduler.\n */\nstatic void prvCheckPendingReadyList( void );\n\n/*\n * Macro that looks at the list of co-routines that are currently delayed to\n * see if any require waking.\n *\n * Co-routines are stored in the queue in the order of their wake time -\n * meaning once one co-routine has been found whose timer has not expired\n * we need not look any further down the list.\n */\nstatic void prvCheckDelayedList( void );\n\n/*-----------------------------------------------------------*/\n\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )\n{\nBaseType_t xReturn;\nCRCB_t *pxCoRoutine;\n\n\t/* Allocate the memory that will store the co-routine control block. */\n\tpxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );\n\tif( pxCoRoutine )\n\t{\n\t\t/* If pxCurrentCoRoutine is NULL then this is the first co-routine to\n\t\tbe created and the co-routine data structures need initialising. */\n\t\tif( pxCurrentCoRoutine == NULL )\n\t\t{\n\t\t\tpxCurrentCoRoutine = pxCoRoutine;\n\t\t\tprvInitialiseCoRoutineLists();\n\t\t}\n\n\t\t/* Check the priority is within limits. */\n\t\tif( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )\n\t\t{\n\t\t\tuxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;\n\t\t}\n\n\t\t/* Fill out the co-routine control block from the function parameters. */\n\t\tpxCoRoutine->uxState = corINITIAL_STATE;\n\t\tpxCoRoutine->uxPriority = uxPriority;\n\t\tpxCoRoutine->uxIndex = uxIndex;\n\t\tpxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;\n\n\t\t/* Initialise all the other co-routine control block parameters. */\n\t\tvListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );\n\t\tvListInitialiseItem( &( pxCoRoutine->xEventListItem ) );\n\n\t\t/* Set the co-routine control block as a link back from the ListItem_t.\n\t\tThis is so we can get back to the containing CRCB from a generic item\n\t\tin a list. */\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );\n\t\tlistSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );\n\n\t\t/* Event lists are always in priority order. */\n\t\tlistSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );\n\n\t\t/* Now the co-routine has been initialised it can be added to the ready\n\t\tlist at the correct priority. */\n\t\tprvAddCoRoutineToReadyQueue( pxCoRoutine );\n\n\t\txReturn = pdPASS;\n\t}\n\telse\n\t{\n\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )\n{\nTickType_t xTimeToWake;\n\n\t/* Calculate the time to wake - this may overflow but this is\n\tnot a problem. */\n\txTimeToWake = xCoRoutineTickCount + xTicksToDelay;\n\n\t/* We must remove ourselves from the ready list before adding\n\tourselves to the blocked list as the same list item is used for\n\tboth lists. */\n\t( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\n\t/* The list item will be inserted in wake time order. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );\n\n\tif( xTimeToWake < xCoRoutineTickCount )\n\t{\n\t\t/* Wake time has overflowed.  Place this item in the\n\t\toverflow list. */\n\t\tvListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\t}\n\telse\n\t{\n\t\t/* The wake time has not overflowed, so we can use the\n\t\tcurrent block list. */\n\t\tvListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );\n\t}\n\n\tif( pxEventList )\n\t{\n\t\t/* Also add the co-routine to an event list.  If this is done then the\n\t\tfunction must be called with interrupts disabled. */\n\t\tvListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckPendingReadyList( void )\n{\n\t/* Are there any co-routines waiting to get moved to the ready list?  These\n\tare co-routines that have been readied by an ISR.  The ISR cannot access\n\tthe\tready lists itself. */\n\twhile( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )\n\t{\n\t\tCRCB_t *pxUnblockedCRCB;\n\n\t\t/* The pending ready list can be accessed by an ISR. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );\n\t\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\t( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );\n\t\tprvAddCoRoutineToReadyQueue( pxUnblockedCRCB );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckDelayedList( void )\n{\nCRCB_t *pxCRCB;\n\n\txPassedTicks = xTaskGetTickCount() - xLastTickCount;\n\twhile( xPassedTicks )\n\t{\n\t\txCoRoutineTickCount++;\n\t\txPassedTicks--;\n\n\t\t/* If the tick count has overflowed we need to swap the ready lists. */\n\t\tif( xCoRoutineTickCount == 0 )\n\t\t{\n\t\t\tList_t * pxTemp;\n\n\t\t\t/* Tick count has overflowed so we need to swap the delay lists.  If there are\n\t\t\tany items in pxDelayedCoRoutineList here then there is an error! */\n\t\t\tpxTemp = pxDelayedCoRoutineList;\n\t\t\tpxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;\n\t\t\tpxOverflowDelayedCoRoutineList = pxTemp;\n\t\t}\n\n\t\t/* See if this tick has made a timeout expire. */\n\t\twhile( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )\n\t\t{\n\t\t\tpxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );\n\n\t\t\tif( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )\n\t\t\t{\n\t\t\t\t/* Timeout not yet expired. */\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\tportDISABLE_INTERRUPTS();\n\t\t\t{\n\t\t\t\t/* The event could have occurred just before this critical\n\t\t\t\tsection.  If this is the case then the generic list item will\n\t\t\t\thave been moved to the pending ready list and the following\n\t\t\t\tline is still valid.  Also the pvContainer parameter will have\n\t\t\t\tbeen set to NULL so the following lines are also valid. */\n\t\t\t\t( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );\n\n\t\t\t\t/* Is the co-routine waiting on an event also? */\n\t\t\t\tif( pxCRCB->xEventListItem.pxContainer )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxCRCB->xEventListItem ) );\n\t\t\t\t}\n\t\t\t}\n\t\t\tportENABLE_INTERRUPTS();\n\n\t\t\tprvAddCoRoutineToReadyQueue( pxCRCB );\n\t\t}\n\t}\n\n\txLastTickCount = xCoRoutineTickCount;\n}\n/*-----------------------------------------------------------*/\n\nvoid vCoRoutineSchedule( void )\n{\n\t/* See if any co-routines readied by events need moving to the ready lists. */\n\tprvCheckPendingReadyList();\n\n\t/* See if any delayed co-routines have timed out. */\n\tprvCheckDelayedList();\n\n\t/* Find the highest priority queue that contains ready co-routines. */\n\twhile( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )\n\t{\n\t\tif( uxTopCoRoutineReadyPriority == 0 )\n\t\t{\n\t\t\t/* No more co-routines to check. */\n\t\t\treturn;\n\t\t}\n\t\t--uxTopCoRoutineReadyPriority;\n\t}\n\n\t/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines\n\t of the\tsame priority get an equal share of the processor time. */\n\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );\n\n\t/* Call the co-routine. */\n\t( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );\n\n\treturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseCoRoutineLists( void )\n{\nUBaseType_t uxPriority;\n\n\tfor( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )\n\t{\n\t\tvListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );\n\t}\n\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );\n\tvListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );\n\tvListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );\n\n\t/* Start with pxDelayedCoRoutineList using list1 and the\n\tpxOverflowDelayedCoRoutineList using list2. */\n\tpxDelayedCoRoutineList = &xDelayedCoRoutineList1;\n\tpxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )\n{\nCRCB_t *pxUnblockedCRCB;\nBaseType_t xReturn;\n\n\t/* This function is called from within an interrupt.  It can only access\n\tevent lists and the pending ready list.  This function assumes that a\n\tcheck has already been made to ensure pxEventList is not empty. */\n\tpxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );\n\t( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );\n\tvListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );\n\n\tif( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n\n#endif /* configUSE_CO_ROUTINES == 0 */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/event_groups.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"event_groups.h\"\n\n/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */\n\n/* The following bit fields convey control information in a task's event list\nitem value.  It is important they don't clash with the\ntaskEVENT_LIST_ITEM_VALUE_IN_USE definition. */\n#if configUSE_16_BIT_TICKS == 1\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x0100U\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x0200U\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x0400U\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff00U\n#else\n\t#define eventCLEAR_EVENTS_ON_EXIT_BIT\t0x01000000UL\n\t#define eventUNBLOCKED_DUE_TO_BIT_SET\t0x02000000UL\n\t#define eventWAIT_FOR_ALL_BITS\t\t\t0x04000000UL\n\t#define eventEVENT_BITS_CONTROL_BYTES\t0xff000000UL\n#endif\n\ntypedef struct EventGroupDef_t\n{\n\tEventBits_t uxEventBits;\n\tList_t xTasksWaitingForBits;\t\t/*< List of tasks waiting for a bit to be set. */\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxEventGroupNumber;\n\t#endif\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n} EventGroup_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Test the bits set in uxCurrentEventBits to see if the wait condition is met.\n * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is\n * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor\n * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the\n * wait condition is met if any of the bits set in uxBitsToWait for are also set\n * in uxCurrentEventBits.\n */\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tEventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )\n\t{\n\tEventGroup_t *pxEventBits;\n\n\t\t/* A StaticEventGroup_t object must be provided. */\n\t\tconfigASSERT( pxEventGroupBuffer );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticEventGroup_t equals the size of the real\n\t\t\tevent group structure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticEventGroup_t );\n\t\t\tconfigASSERT( xSize == sizeof( EventGroup_t ) );\n\t\t} /*lint !e529 xSize is referenced if configASSERT() is defined. */\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* The user has provided a statically allocated event group - use it. */\n\t\tpxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */\n\n\t\tif( pxEventBits != NULL )\n\t\t{\n\t\t\tpxEventBits->uxEventBits = 0;\n\t\t\tvListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n\t\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Both static and dynamic allocation can be used, so note that\n\t\t\t\tthis event group was created statically in case the event group\n\t\t\t\tis later deleted. */\n\t\t\t\tpxEventBits->ucStaticallyAllocated = pdTRUE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n\t\t\ttraceEVENT_GROUP_CREATE( pxEventBits );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* xEventGroupCreateStatic should only ever be called with\n\t\t\tpxEventGroupBuffer pointing to a pre-allocated (compile time\n\t\t\tallocated) StaticEventGroup_t variable. */\n\t\t\ttraceEVENT_GROUP_CREATE_FAILED();\n\t\t}\n\n\t\treturn pxEventBits;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tEventGroupHandle_t xEventGroupCreate( void )\n\t{\n\tEventGroup_t *pxEventBits;\n\n\t\t/* Allocate the event group.  Justification for MISRA deviation as\n\t\tfollows:  pvPortMalloc() always ensures returned memory blocks are\n\t\taligned per the requirements of the MCU stack.  In this case\n\t\tpvPortMalloc() must return a pointer that is guaranteed to meet the\n\t\talignment requirements of the EventGroup_t structure - which (if you\n\t\tfollow it through) is the alignment requirements of the TickType_t type\n\t\t(EventBits_t being of TickType_t itself).  Therefore, whenever the\n\t\tstack alignment requirements are greater than or equal to the\n\t\tTickType_t alignment requirements the cast is safe.  In other cases,\n\t\twhere the natural word size of the architecture is less than\n\t\tsizeof( TickType_t ), the TickType_t variables will be accessed in two\n\t\tor more reads operations, and the alignment requirements is only that\n\t\tof each individual read. */\n\t\tpxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */\n\n\t\tif( pxEventBits != NULL )\n\t\t{\n\t\t\tpxEventBits->uxEventBits = 0;\n\t\t\tvListInitialise( &( pxEventBits->xTasksWaitingForBits ) );\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Both static and dynamic allocation can be used, so note this\n\t\t\t\tevent group was allocated statically in case the event group is\n\t\t\t\tlater deleted. */\n\t\t\t\tpxEventBits->ucStaticallyAllocated = pdFALSE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t\t\ttraceEVENT_GROUP_CREATE( pxEventBits );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */\n\t\t}\n\n\t\treturn pxEventBits;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )\n{\nEventBits_t uxOriginalBitValue, uxReturn;\nEventGroup_t *pxEventBits = xEventGroup;\nBaseType_t xAlreadyYielded;\nBaseType_t xTimeoutOccurred = pdFALSE;\n\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\tconfigASSERT( uxBitsToWaitFor != 0 );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\tvTaskSuspendAll();\n\t{\n\t\tuxOriginalBitValue = pxEventBits->uxEventBits;\n\n\t\t( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );\n\n\t\tif( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t{\n\t\t\t/* All the rendezvous bits are now set - no need to block. */\n\t\t\tuxReturn = ( uxOriginalBitValue | uxBitsToSet );\n\n\t\t\t/* Rendezvous always clear the bits.  They will have been cleared\n\t\t\talready unless this is the only task in the rendezvous. */\n\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\n\t\t\txTicksToWait = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif( xTicksToWait != ( TickType_t ) 0 )\n\t\t\t{\n\t\t\t\ttraceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );\n\n\t\t\t\t/* Store the bits that the calling task is waiting for in the\n\t\t\t\ttask's event list item so the kernel knows when a match is\n\t\t\t\tfound.  Then enter the blocked state. */\n\t\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );\n\n\t\t\t\t/* This assignment is obsolete as uxReturn will get set after\n\t\t\t\tthe task unblocks, but some compilers mistakenly generate a\n\t\t\t\twarning about uxReturn being returned without being set if the\n\t\t\t\tassignment is omitted. */\n\t\t\t\tuxReturn = 0;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The rendezvous bits were not set, but no block time was\n\t\t\t\tspecified - just return the current event bit value. */\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\t\t\t\txTimeoutOccurred = pdTRUE;\n\t\t\t}\n\t\t}\n\t}\n\txAlreadyYielded = xTaskResumeAll();\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* The task blocked to wait for its required bits to be set - at this\n\t\tpoint either the required bits were set or the block time expired.  If\n\t\tthe required bits were set they will have been stored in the task's\n\t\tevent list item, and they should now be retrieved then cleared. */\n\t\tuxReturn = uxTaskResetEventItemValue();\n\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n\t\t{\n\t\t\t/* The task timed out, just return the current event bit value. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t\t\t/* Although the task got here because it timed out before the\n\t\t\t\tbits it was waiting for were set, it is possible that since it\n\t\t\t\tunblocked another task has set the bits.  If this is the case\n\t\t\t\tthen it needs to clear the bits before exiting. */\n\t\t\t\tif( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t\t\t{\n\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\txTimeoutOccurred = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task unblocked because the bits were set. */\n\t\t}\n\n\t\t/* Control bits might be set as the task had blocked should not be\n\t\treturned. */\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n\t}\n\n\ttraceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );\n\n\t/* Prevent compiler warnings when trace macros are not used. */\n\t( void ) xTimeoutOccurred;\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nEventBits_t uxReturn, uxControlBits = 0;\nBaseType_t xWaitConditionMet, xAlreadyYielded;\nBaseType_t xTimeoutOccurred = pdFALSE;\n\n\t/* Check the user is not attempting to wait on the bits used by the kernel\n\titself, and that at least one bit is being requested. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\tconfigASSERT( uxBitsToWaitFor != 0 );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\tvTaskSuspendAll();\n\t{\n\t\tconst EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;\n\n\t\t/* Check to see if the wait condition is already met or not. */\n\t\txWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );\n\n\t\tif( xWaitConditionMet != pdFALSE )\n\t\t{\n\t\t\t/* The wait condition has already been met so there is no need to\n\t\t\tblock. */\n\t\t\tuxReturn = uxCurrentEventBits;\n\t\t\txTicksToWait = ( TickType_t ) 0;\n\n\t\t\t/* Clear the wait bits if requested to do so. */\n\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t{\n\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse if( xTicksToWait == ( TickType_t ) 0 )\n\t\t{\n\t\t\t/* The wait condition has not been met, but no block time was\n\t\t\tspecified, so just return the current value. */\n\t\t\tuxReturn = uxCurrentEventBits;\n\t\t\txTimeoutOccurred = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task is going to block to wait for its required bits to be\n\t\t\tset.  uxControlBits are used to remember the specified behaviour of\n\t\t\tthis call to xEventGroupWaitBits() - for use when the event bits\n\t\t\tunblock the task. */\n\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t{\n\t\t\t\tuxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tif( xWaitForAllBits != pdFALSE )\n\t\t\t{\n\t\t\t\tuxControlBits |= eventWAIT_FOR_ALL_BITS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Store the bits that the calling task is waiting for in the\n\t\t\ttask's event list item so the kernel knows when a match is\n\t\t\tfound.  Then enter the blocked state. */\n\t\t\tvTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );\n\n\t\t\t/* This is obsolete as it will get set after the task unblocks, but\n\t\t\tsome compilers mistakenly generate a warning about the variable\n\t\t\tbeing returned without being set if it is not done. */\n\t\t\tuxReturn = 0;\n\n\t\t\ttraceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );\n\t\t}\n\t}\n\txAlreadyYielded = xTaskResumeAll();\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* The task blocked to wait for its required bits to be set - at this\n\t\tpoint either the required bits were set or the block time expired.  If\n\t\tthe required bits were set they will have been stored in the task's\n\t\tevent list item, and they should now be retrieved then cleared. */\n\t\tuxReturn = uxTaskResetEventItemValue();\n\n\t\tif( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\t/* The task timed out, just return the current event bit value. */\n\t\t\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t\t\t/* It is possible that the event bits were updated between this\n\t\t\t\ttask leaving the Blocked state and running again. */\n\t\t\t\tif( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xClearOnExit != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxEventBits->uxEventBits &= ~uxBitsToWaitFor;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t\txTimeoutOccurred = pdTRUE;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The task unblocked because the bits were set. */\n\t\t}\n\n\t\t/* The task blocked so control bits may have been set. */\n\t\tuxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;\n\t}\n\ttraceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );\n\n\t/* Prevent compiler warnings when trace macros are not used. */\n\t( void ) xTimeoutOccurred;\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nEventBits_t uxReturn;\n\n\t/* Check the user is not attempting to clear the bits used by the kernel\n\titself. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\ttraceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );\n\n\t\t/* The value returned is the event group value prior to the bits being\n\t\tcleared. */\n\t\tuxReturn = pxEventBits->uxEventBits;\n\n\t\t/* Clear the bits. */\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )\n\t{\n\t\tBaseType_t xReturn;\n\n\t\ttraceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n\t\treturn xReturn;\n\t}\n\n#endif\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )\n{\nUBaseType_t uxSavedInterruptStatus;\nEventGroup_t const * const pxEventBits = xEventGroup;\nEventBits_t uxReturn;\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tuxReturn = pxEventBits->uxEventBits;\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn uxReturn;\n} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */\n/*-----------------------------------------------------------*/\n\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )\n{\nListItem_t *pxListItem, *pxNext;\nListItem_t const *pxListEnd;\nList_t const * pxList;\nEventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;\nEventGroup_t *pxEventBits = xEventGroup;\nBaseType_t xMatchFound = pdFALSE;\n\n\t/* Check the user is not attempting to set the bits used by the kernel\n\titself. */\n\tconfigASSERT( xEventGroup );\n\tconfigASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );\n\n\tpxList = &( pxEventBits->xTasksWaitingForBits );\n\tpxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\tvTaskSuspendAll();\n\t{\n\t\ttraceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );\n\n\t\tpxListItem = listGET_HEAD_ENTRY( pxList );\n\n\t\t/* Set the bits. */\n\t\tpxEventBits->uxEventBits |= uxBitsToSet;\n\n\t\t/* See if the new bit value should unblock any tasks. */\n\t\twhile( pxListItem != pxListEnd )\n\t\t{\n\t\t\tpxNext = listGET_NEXT( pxListItem );\n\t\t\tuxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );\n\t\t\txMatchFound = pdFALSE;\n\n\t\t\t/* Split the bits waited for from the control bits. */\n\t\t\tuxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;\n\t\t\tuxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;\n\n\t\t\tif( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Just looking for single bit being set. */\n\t\t\t\tif( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\txMatchFound = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )\n\t\t\t{\n\t\t\t\t/* All bits are set. */\n\t\t\t\txMatchFound = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Need all bits to be set, but not all the bits were set. */\n\t\t\t}\n\n\t\t\tif( xMatchFound != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The bits match.  Should the bits be cleared on exit? */\n\t\t\t\tif( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tuxBitsToClear |= uxBitsWaitedFor;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* Store the actual event flag value in the task's event list\n\t\t\t\titem before removing the task from the event list.  The\n\t\t\t\teventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows\n\t\t\t\tthat is was unblocked due to its required bits matching, rather\n\t\t\t\tthan because it timed out. */\n\t\t\t\tvTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );\n\t\t\t}\n\n\t\t\t/* Move onto the next list item.  Note pxListItem->pxNext is not\n\t\t\tused here as the list item may have been removed from the event list\n\t\t\tand inserted into the ready/pending reading list. */\n\t\t\tpxListItem = pxNext;\n\t\t}\n\n\t\t/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT\n\t\tbit was set in the control word. */\n\t\tpxEventBits->uxEventBits &= ~uxBitsToClear;\n\t}\n\t( void ) xTaskResumeAll();\n\n\treturn pxEventBits->uxEventBits;\n}\n/*-----------------------------------------------------------*/\n\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup )\n{\nEventGroup_t *pxEventBits = xEventGroup;\nconst List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );\n\n\tvTaskSuspendAll();\n\t{\n\t\ttraceEVENT_GROUP_DELETE( xEventGroup );\n\n\t\twhile( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* Unblock the task, returning 0 as the event list is being deleted\n\t\t\tand cannot therefore have any bits set. */\n\t\t\tconfigASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );\n\t\t\tvTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );\n\t\t}\n\n\t\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n\t\t{\n\t\t\t/* The event group can only have been allocated dynamically - free\n\t\t\tit again. */\n\t\t\tvPortFree( pxEventBits );\n\t\t}\n\t\t#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t\t{\n\t\t\t/* The event group could have been allocated statically or\n\t\t\tdynamically, so check before attempting to free the memory. */\n\t\t\tif( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n\t\t\t{\n\t\t\t\tvPortFree( pxEventBits );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t}\n\t( void ) xTaskResumeAll();\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'set bits' command that was pended from\nan interrupt. */\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )\n{\n\t( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\n/* For internal use only - execute a 'clear bits' command that was pended from\nan interrupt. */\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )\n{\n\t( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )\n{\nBaseType_t xWaitConditionMet = pdFALSE;\n\n\tif( xWaitForAllBits == pdFALSE )\n\t{\n\t\t/* Task only has to wait for one bit within uxBitsToWaitFor to be\n\t\tset.  Is one already set? */\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )\n\t\t{\n\t\t\txWaitConditionMet = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* Task has to wait for all the bits in uxBitsToWaitFor to be set.\n\t\tAre they set already? */\n\t\tif( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )\n\t\t{\n\t\t\txWaitConditionMet = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\treturn xWaitConditionMet;\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttraceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );\n\t\txReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */\n\n\t\treturn xReturn;\n\t}\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if (configUSE_TRACE_FACILITY == 1)\n\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup )\n\t{\n\tUBaseType_t xReturn;\n\tEventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n\n\t\tif( xEventGroup == NULL )\n\t\t{\n\t\t\txReturn = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pxEventBits->uxEventGroupNumber;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )\n\t{\n\t\t( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/FreeRTOS.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef INC_FREERTOS_H\n#define INC_FREERTOS_H\n\n/*\n * Include the generic headers required for the FreeRTOS port being used.\n */\n#include <stddef.h>\n\n/*\n * If stdint.h cannot be located then:\n *   + If using GCC ensure the -nostdint options is *not* being used.\n *   + Ensure the project's include path includes the directory in which your\n *     compiler stores stdint.h.\n *   + Set any compiler options necessary for it to support C99, as technically\n *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any\n *     other way).\n *   + The FreeRTOS download includes a simple stdint.h definition that can be\n *     used in cases where none is provided by the compiler.  The files only\n *     contains the typedefs required to build FreeRTOS.  Read the instructions\n *     in FreeRTOS/source/stdint.readme for more information.\n */\n#include <stdint.h> /* READ COMMENT ABOVE. */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Application specific configuration options. */\n#include \"FreeRTOSConfig.h\"\n\n/* Basic FreeRTOS definitions. */\n#include \"projdefs.h\"\n\n/* Definitions specific to the port being used. */\n#include \"portable.h\"\n\n/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */\n#ifndef configUSE_NEWLIB_REENTRANT\n\t#define configUSE_NEWLIB_REENTRANT 0\n#endif\n\n/* Required if struct _reent is used. */\n#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t#include <reent.h>\n#endif\n/*\n * Check all the required application specific macros have been defined.\n * These macros are application specific and (as downloaded) are defined\n * within FreeRTOSConfig.h.\n */\n\n#ifndef configMINIMAL_STACK_SIZE\n\t#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.\n#endif\n\n#ifndef configMAX_PRIORITIES\n\t#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#if configMAX_PRIORITIES < 1\n\t#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.\n#endif\n\n#ifndef configUSE_PREEMPTION\n\t#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_IDLE_HOOK\n\t#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_TICK_HOOK\n\t#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_16_BIT_TICKS\n\t#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.\n#endif\n\n#ifndef configUSE_CO_ROUTINES\n\t#define configUSE_CO_ROUTINES 0\n#endif\n\n#ifndef INCLUDE_vTaskPrioritySet\n\t#define INCLUDE_vTaskPrioritySet 0\n#endif\n\n#ifndef INCLUDE_uxTaskPriorityGet\n\t#define INCLUDE_uxTaskPriorityGet 0\n#endif\n\n#ifndef INCLUDE_vTaskDelete\n\t#define INCLUDE_vTaskDelete 0\n#endif\n\n#ifndef INCLUDE_vTaskSuspend\n\t#define INCLUDE_vTaskSuspend 0\n#endif\n\n#ifndef INCLUDE_vTaskDelayUntil\n\t#define INCLUDE_vTaskDelayUntil 0\n#endif\n\n#ifndef INCLUDE_vTaskDelay\n\t#define INCLUDE_vTaskDelay 0\n#endif\n\n#ifndef INCLUDE_xTaskGetIdleTaskHandle\n\t#define INCLUDE_xTaskGetIdleTaskHandle 0\n#endif\n\n#ifndef INCLUDE_xTaskAbortDelay\n\t#define INCLUDE_xTaskAbortDelay 0\n#endif\n\n#ifndef INCLUDE_xQueueGetMutexHolder\n\t#define INCLUDE_xQueueGetMutexHolder 0\n#endif\n\n#ifndef INCLUDE_xSemaphoreGetMutexHolder\n\t#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder\n#endif\n\n#ifndef INCLUDE_xTaskGetHandle\n\t#define INCLUDE_xTaskGetHandle 0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark\n\t#define INCLUDE_uxTaskGetStackHighWaterMark 0\n#endif\n\n#ifndef INCLUDE_uxTaskGetStackHighWaterMark2\n\t#define INCLUDE_uxTaskGetStackHighWaterMark2 0\n#endif\n\n#ifndef INCLUDE_eTaskGetState\n\t#define INCLUDE_eTaskGetState 0\n#endif\n\n#ifndef INCLUDE_xTaskResumeFromISR\n\t#define INCLUDE_xTaskResumeFromISR 1\n#endif\n\n#ifndef INCLUDE_xTimerPendFunctionCall\n\t#define INCLUDE_xTimerPendFunctionCall 0\n#endif\n\n#ifndef INCLUDE_xTaskGetSchedulerState\n\t#define INCLUDE_xTaskGetSchedulerState 0\n#endif\n\n#ifndef INCLUDE_xTaskGetCurrentTaskHandle\n\t#define INCLUDE_xTaskGetCurrentTaskHandle 0\n#endif\n\n#if configUSE_CO_ROUTINES != 0\n\t#ifndef configMAX_CO_ROUTINE_PRIORITIES\n\t\t#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.\n\t#endif\n#endif\n\n#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK\n\t#define configUSE_DAEMON_TASK_STARTUP_HOOK 0\n#endif\n\n#ifndef configUSE_APPLICATION_TASK_TAG\n\t#define configUSE_APPLICATION_TASK_TAG 0\n#endif\n\n#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS\n\t#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0\n#endif\n\n#ifndef configUSE_RECURSIVE_MUTEXES\n\t#define configUSE_RECURSIVE_MUTEXES 0\n#endif\n\n#ifndef configUSE_MUTEXES\n\t#define configUSE_MUTEXES 0\n#endif\n\n#ifndef configUSE_TIMERS\n\t#define configUSE_TIMERS 0\n#endif\n\n#ifndef configUSE_COUNTING_SEMAPHORES\n\t#define configUSE_COUNTING_SEMAPHORES 0\n#endif\n\n#ifndef configUSE_ALTERNATIVE_API\n\t#define configUSE_ALTERNATIVE_API 0\n#endif\n\n#ifndef portCRITICAL_NESTING_IN_TCB\n\t#define portCRITICAL_NESTING_IN_TCB 0\n#endif\n\n#ifndef configMAX_TASK_NAME_LEN\n\t#define configMAX_TASK_NAME_LEN 16\n#endif\n\n#ifndef configIDLE_SHOULD_YIELD\n\t#define configIDLE_SHOULD_YIELD\t\t1\n#endif\n\n#if configMAX_TASK_NAME_LEN < 1\n\t#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h\n#endif\n\n#ifndef configASSERT\n\t#define configASSERT( x )\n\t#define configASSERT_DEFINED 0\n#else\n\t#define configASSERT_DEFINED 1\n#endif\n\n/* configPRECONDITION should be defined as configASSERT.\nThe CBMC proofs need a way to track assumptions and assertions.\nA configPRECONDITION statement should express an implicit invariant or\nassumption made.  A configASSERT statement should express an invariant that must\nhold explicit before calling the code. */\n#ifndef configPRECONDITION\n\t#define configPRECONDITION( X ) configASSERT(X)\n\t#define configPRECONDITION_DEFINED 0\n#else\n\t#define configPRECONDITION_DEFINED 1\n#endif\n\n#ifndef portMEMORY_BARRIER\n\t#define portMEMORY_BARRIER()\n#endif\n\n#ifndef portSOFTWARE_BARRIER\n\t#define portSOFTWARE_BARRIER()\n#endif\n\n/* The timers module relies on xTaskGetSchedulerState(). */\n#if configUSE_TIMERS == 1\n\n\t#ifndef configTIMER_TASK_PRIORITY\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.\n\t#endif /* configTIMER_TASK_PRIORITY */\n\n\t#ifndef configTIMER_QUEUE_LENGTH\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.\n\t#endif /* configTIMER_QUEUE_LENGTH */\n\n\t#ifndef configTIMER_TASK_STACK_DEPTH\n\t\t#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.\n\t#endif /* configTIMER_TASK_STACK_DEPTH */\n\n#endif /* configUSE_TIMERS */\n\n#ifndef portSET_INTERRUPT_MASK_FROM_ISR\n\t#define portSET_INTERRUPT_MASK_FROM_ISR() 0\n#endif\n\n#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR\n\t#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue\n#endif\n\n#ifndef portCLEAN_UP_TCB\n\t#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB\n#endif\n\n#ifndef portPRE_TASK_DELETE_HOOK\n\t#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )\n#endif\n\n#ifndef portSETUP_TCB\n\t#define portSETUP_TCB( pxTCB ) ( void ) pxTCB\n#endif\n\n#ifndef configQUEUE_REGISTRY_SIZE\n\t#define configQUEUE_REGISTRY_SIZE 0U\n#endif\n\n#if ( configQUEUE_REGISTRY_SIZE < 1 )\n\t#define vQueueAddToRegistry( xQueue, pcName )\n\t#define vQueueUnregisterQueue( xQueue )\n\t#define pcQueueGetName( xQueue )\n#endif\n\n#ifndef portPOINTER_SIZE_TYPE\n\t#define portPOINTER_SIZE_TYPE uint32_t\n#endif\n\n/* Remove any unused trace macros. */\n#ifndef traceSTART\n\t/* Used to perform any necessary initialisation - for example, open a file\n\tinto which trace is to be written. */\n\t#define traceSTART()\n#endif\n\n#ifndef traceEND\n\t/* Use to close a trace, for example close a file into which trace has been\n\twritten. */\n\t#define traceEND()\n#endif\n\n#ifndef traceTASK_SWITCHED_IN\n\t/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer\n\tto the task control block of the selected task. */\n\t#define traceTASK_SWITCHED_IN()\n#endif\n\n#ifndef traceINCREASE_TICK_COUNT\n\t/* Called before stepping the tick count after waking from tickless idle\n\tsleep. */\n\t#define traceINCREASE_TICK_COUNT( x )\n#endif\n\n#ifndef traceLOW_POWER_IDLE_BEGIN\n\t/* Called immediately before entering tickless idle. */\n\t#define traceLOW_POWER_IDLE_BEGIN()\n#endif\n\n#ifndef\ttraceLOW_POWER_IDLE_END\n\t/* Called when returning to the Idle task after a tickless idle. */\n\t#define traceLOW_POWER_IDLE_END()\n#endif\n\n#ifndef traceTASK_SWITCHED_OUT\n\t/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer\n\tto the task control block of the task being switched out. */\n\t#define traceTASK_SWITCHED_OUT()\n#endif\n\n#ifndef traceTASK_PRIORITY_INHERIT\n\t/* Called when a task attempts to take a mutex that is already held by a\n\tlower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task\n\tthat holds the mutex.  uxInheritedPriority is the priority the mutex holder\n\twill inherit (the priority of the task that is attempting to obtain the\n\tmuted. */\n\t#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )\n#endif\n\n#ifndef traceTASK_PRIORITY_DISINHERIT\n\t/* Called when a task releases a mutex, the holding of which had resulted in\n\tthe task inheriting the priority of a higher priority task.\n\tpxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the\n\tmutex.  uxOriginalPriority is the task's configured (base) priority. */\n\t#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_RECEIVE\n\t/* Task is about to block because it cannot read from a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the read was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the read. */\n\t#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_PEEK\n\t/* Task is about to block because it cannot read from a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the read was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the read. */\n\t#define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceBLOCKING_ON_QUEUE_SEND\n\t/* Task is about to block because it cannot write to a\n\tqueue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore\n\tupon which the write was attempted.  pxCurrentTCB points to the TCB of the\n\ttask that attempted the write. */\n\t#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )\n#endif\n\n#ifndef configCHECK_FOR_STACK_OVERFLOW\n\t#define configCHECK_FOR_STACK_OVERFLOW 0\n#endif\n\n#ifndef configRECORD_STACK_HIGH_ADDRESS\n\t#define configRECORD_STACK_HIGH_ADDRESS 0\n#endif\n\n#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H\n\t#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0\n#endif\n\n/* The following event macros are embedded in the kernel API calls. */\n\n#ifndef traceMOVED_TASK_TO_READY_STATE\n\t#define traceMOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef tracePOST_MOVED_TASK_TO_READY_STATE\n\t#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n#endif\n\n#ifndef traceQUEUE_CREATE\n\t#define traceQUEUE_CREATE( pxNewQueue )\n#endif\n\n#ifndef traceQUEUE_CREATE_FAILED\n\t#define traceQUEUE_CREATE_FAILED( ucQueueType )\n#endif\n\n#ifndef traceCREATE_MUTEX\n\t#define traceCREATE_MUTEX( pxNewQueue )\n#endif\n\n#ifndef traceCREATE_MUTEX_FAILED\n\t#define traceCREATE_MUTEX_FAILED()\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE\n\t#define traceGIVE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED\n\t#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE\n\t#define traceTAKE_MUTEX_RECURSIVE( pxMutex )\n#endif\n\n#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED\n\t#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE\n\t#define traceCREATE_COUNTING_SEMAPHORE()\n#endif\n\n#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED\n\t#define traceCREATE_COUNTING_SEMAPHORE_FAILED()\n#endif\n\n#ifndef traceQUEUE_SEND\n\t#define traceQUEUE_SEND( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FAILED\n\t#define traceQUEUE_SEND_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE\n\t#define traceQUEUE_RECEIVE( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK\n\t#define traceQUEUE_PEEK( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FAILED\n\t#define traceQUEUE_PEEK_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR\n\t#define traceQUEUE_PEEK_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FAILED\n\t#define traceQUEUE_RECEIVE_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR\n\t#define traceQUEUE_SEND_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_SEND_FROM_ISR_FAILED\n\t#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR\n\t#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )\n#endif\n\n#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED\n\t#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED\n\t#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )\n#endif\n\n#ifndef traceQUEUE_DELETE\n\t#define traceQUEUE_DELETE( pxQueue )\n#endif\n\n#ifndef traceTASK_CREATE\n\t#define traceTASK_CREATE( pxNewTCB )\n#endif\n\n#ifndef traceTASK_CREATE_FAILED\n\t#define traceTASK_CREATE_FAILED()\n#endif\n\n#ifndef traceTASK_DELETE\n\t#define traceTASK_DELETE( pxTaskToDelete )\n#endif\n\n#ifndef traceTASK_DELAY_UNTIL\n\t#define traceTASK_DELAY_UNTIL( x )\n#endif\n\n#ifndef traceTASK_DELAY\n\t#define traceTASK_DELAY()\n#endif\n\n#ifndef traceTASK_PRIORITY_SET\n\t#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )\n#endif\n\n#ifndef traceTASK_SUSPEND\n\t#define traceTASK_SUSPEND( pxTaskToSuspend )\n#endif\n\n#ifndef traceTASK_RESUME\n\t#define traceTASK_RESUME( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_RESUME_FROM_ISR\n\t#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )\n#endif\n\n#ifndef traceTASK_INCREMENT_TICK\n\t#define traceTASK_INCREMENT_TICK( xTickCount )\n#endif\n\n#ifndef traceTIMER_CREATE\n\t#define traceTIMER_CREATE( pxNewTimer )\n#endif\n\n#ifndef traceTIMER_CREATE_FAILED\n\t#define traceTIMER_CREATE_FAILED()\n#endif\n\n#ifndef traceTIMER_COMMAND_SEND\n\t#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )\n#endif\n\n#ifndef traceTIMER_EXPIRED\n\t#define traceTIMER_EXPIRED( pxTimer )\n#endif\n\n#ifndef traceTIMER_COMMAND_RECEIVED\n\t#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )\n#endif\n\n#ifndef traceMALLOC\n    #define traceMALLOC( pvAddress, uiSize )\n#endif\n\n#ifndef traceFREE\n    #define traceFREE( pvAddress, uiSize )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE\n\t#define traceEVENT_GROUP_CREATE( xEventGroup )\n#endif\n\n#ifndef traceEVENT_GROUP_CREATE_FAILED\n\t#define traceEVENT_GROUP_CREATE_FAILED()\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_BLOCK\n\t#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_SYNC_END\n\t#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK\n\t#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )\n#endif\n\n#ifndef traceEVENT_GROUP_WAIT_BITS_END\n\t#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS\n\t#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR\n\t#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS\n\t#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR\n\t#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )\n#endif\n\n#ifndef traceEVENT_GROUP_DELETE\n\t#define traceEVENT_GROUP_DELETE( xEventGroup )\n#endif\n\n#ifndef tracePEND_FUNC_CALL\n\t#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)\n#endif\n\n#ifndef tracePEND_FUNC_CALL_FROM_ISR\n\t#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)\n#endif\n\n#ifndef traceQUEUE_REGISTRY_ADD\n\t#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE_BLOCK\n\t#define traceTASK_NOTIFY_TAKE_BLOCK()\n#endif\n\n#ifndef traceTASK_NOTIFY_TAKE\n\t#define traceTASK_NOTIFY_TAKE()\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT_BLOCK\n\t#define traceTASK_NOTIFY_WAIT_BLOCK()\n#endif\n\n#ifndef traceTASK_NOTIFY_WAIT\n\t#define traceTASK_NOTIFY_WAIT()\n#endif\n\n#ifndef traceTASK_NOTIFY\n\t#define traceTASK_NOTIFY()\n#endif\n\n#ifndef traceTASK_NOTIFY_FROM_ISR\n\t#define traceTASK_NOTIFY_FROM_ISR()\n#endif\n\n#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR\n\t#define traceTASK_NOTIFY_GIVE_FROM_ISR()\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_FAILED\n\t#define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED\n\t#define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_CREATE\n\t#define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_DELETE\n\t#define traceSTREAM_BUFFER_DELETE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RESET\n\t#define traceSTREAM_BUFFER_RESET( xStreamBuffer )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND\n\t#define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND\n\t#define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FAILED\n\t#define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR\n\t#define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )\n#endif\n\n#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE\n\t#define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE\n\t#define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED\n\t#define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )\n#endif\n\n#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR\n\t#define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )\n#endif\n\n#ifndef configGENERATE_RUN_TIME_STATS\n\t#define configGENERATE_RUN_TIME_STATS 0\n#endif\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n\t#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n\t\t#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.\n\t#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */\n\n\t#ifndef portGET_RUN_TIME_COUNTER_VALUE\n\t\t#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.\n\t\t#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */\n\t#endif /* portGET_RUN_TIME_COUNTER_VALUE */\n\n#endif /* configGENERATE_RUN_TIME_STATS */\n\n#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS\n\t#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()\n#endif\n\n#ifndef configUSE_MALLOC_FAILED_HOOK\n\t#define configUSE_MALLOC_FAILED_HOOK 0\n#endif\n\n#ifndef portPRIVILEGE_BIT\n\t#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )\n#endif\n\n#ifndef portYIELD_WITHIN_API\n\t#define portYIELD_WITHIN_API portYIELD\n#endif\n\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )\n#endif\n\n#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP\n\t#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2\n#endif\n\n#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2\n\t#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2\n#endif\n\n#ifndef configUSE_TICKLESS_IDLE\n\t#define configUSE_TICKLESS_IDLE 0\n#endif\n\n#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING\n\t#define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPRE_SLEEP_PROCESSING\n\t#define configPRE_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configPOST_SLEEP_PROCESSING\n\t#define configPOST_SLEEP_PROCESSING( x )\n#endif\n\n#ifndef configUSE_QUEUE_SETS\n\t#define configUSE_QUEUE_SETS 0\n#endif\n\n#ifndef portTASK_USES_FLOATING_POINT\n\t#define portTASK_USES_FLOATING_POINT()\n#endif\n\n#ifndef portALLOCATE_SECURE_CONTEXT\n\t#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )\n#endif\n\n#ifndef portDONT_DISCARD\n\t#define portDONT_DISCARD\n#endif\n\n#ifndef configUSE_TIME_SLICING\n\t#define configUSE_TIME_SLICING 1\n#endif\n\n#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS\n\t#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0\n#endif\n\n#ifndef configUSE_STATS_FORMATTING_FUNCTIONS\n\t#define configUSE_STATS_FORMATTING_FUNCTIONS 0\n#endif\n\n#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()\n#endif\n\n#ifndef configUSE_TRACE_FACILITY\n\t#define configUSE_TRACE_FACILITY 0\n#endif\n\n#ifndef mtCOVERAGE_TEST_MARKER\n\t#define mtCOVERAGE_TEST_MARKER()\n#endif\n\n#ifndef mtCOVERAGE_TEST_DELAY\n\t#define mtCOVERAGE_TEST_DELAY()\n#endif\n\n#ifndef portASSERT_IF_IN_ISR\n\t#define portASSERT_IF_IN_ISR()\n#endif\n\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0\n#endif\n\n#ifndef configAPPLICATION_ALLOCATED_HEAP\n\t#define configAPPLICATION_ALLOCATED_HEAP 0\n#endif\n\n#ifndef configUSE_TASK_NOTIFICATIONS\n\t#define configUSE_TASK_NOTIFICATIONS 1\n#endif\n\n#ifndef configUSE_POSIX_ERRNO\n\t#define configUSE_POSIX_ERRNO 0\n#endif\n\n#ifndef portTICK_TYPE_IS_ATOMIC\n\t#define portTICK_TYPE_IS_ATOMIC 0\n#endif\n\n#ifndef configSUPPORT_STATIC_ALLOCATION\n\t/* Defaults to 0 for backward compatibility. */\n\t#define configSUPPORT_STATIC_ALLOCATION 0\n#endif\n\n#ifndef configSUPPORT_DYNAMIC_ALLOCATION\n\t/* Defaults to 1 for backward compatibility. */\n\t#define configSUPPORT_DYNAMIC_ALLOCATION 1\n#endif\n\n#ifndef configSTACK_DEPTH_TYPE\n\t/* Defaults to uint16_t for backward compatibility, but can be overridden\n\tin FreeRTOSConfig.h if uint16_t is too restrictive. */\n\t#define configSTACK_DEPTH_TYPE uint16_t\n#endif\n\n#ifndef configMESSAGE_BUFFER_LENGTH_TYPE\n\t/* Defaults to size_t for backward compatibility, but can be overridden\n\tin FreeRTOSConfig.h if lengths will always be less than the number of bytes\n\tin a size_t. */\n\t#define configMESSAGE_BUFFER_LENGTH_TYPE size_t\n#endif\n\n/* Sanity check the configuration. */\n#if( configUSE_TICKLESS_IDLE != 0 )\n\t#if( INCLUDE_vTaskSuspend != 1 )\n\t\t#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0\n\t#endif /* INCLUDE_vTaskSuspend */\n#endif /* configUSE_TICKLESS_IDLE */\n\n#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )\n\t#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.\n#endif\n\n#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )\n\t#error configUSE_MUTEXES must be set to 1 to use recursive mutexes\n#endif\n\n#ifndef configINITIAL_TICK_COUNT\n\t#define configINITIAL_TICK_COUNT 0\n#endif\n\n#if( portTICK_TYPE_IS_ATOMIC == 0 )\n\t/* Either variables of tick type cannot be read atomically, or\n\tportTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when\n\tthe tick count is returned to the standard critical section macros. */\n\t#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()\n\t#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )\n#else\n\t/* The tick type can be read atomically, so critical sections used when the\n\ttick count is returned can be defined away. */\n\t#define portTICK_TYPE_ENTER_CRITICAL()\n\t#define portTICK_TYPE_EXIT_CRITICAL()\n\t#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0\n\t#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x\n#endif\n\n/* Definitions to allow backward compatibility with FreeRTOS versions prior to\nV8 if desired. */\n#ifndef configENABLE_BACKWARD_COMPATIBILITY\n\t#define configENABLE_BACKWARD_COMPATIBILITY 1\n#endif\n\n#ifndef configPRINTF\n\t/* configPRINTF() was not defined, so define it away to nothing.  To use\n\tconfigPRINTF() then define it as follows (where MyPrintFunction() is\n\tprovided by the application writer):\n\n\tvoid MyPrintFunction(const char *pcFormat, ... );\n\t#define configPRINTF( X )   MyPrintFunction X\n\n\tThen call like a standard printf() function, but placing brackets around\n\tall parameters so they are passed as a single parameter.  For example:\n\tconfigPRINTF( (\"Value = %d\", MyVariable) ); */\n\t#define configPRINTF( X )\n#endif\n\n#ifndef configMAX\n\t/* The application writer has not provided their own MAX macro, so define\n\tthe following generic implementation. */\n\t#define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#ifndef configMIN\n\t/* The application writer has not provided their own MAX macro, so define\n\tthe following generic implementation. */\n\t#define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )\n#endif\n\n#if configENABLE_BACKWARD_COMPATIBILITY == 1\n\t#define eTaskStateGet eTaskGetState\n\t#define portTickType TickType_t\n\t#define xTaskHandle TaskHandle_t\n\t#define xQueueHandle QueueHandle_t\n\t#define xSemaphoreHandle SemaphoreHandle_t\n\t#define xQueueSetHandle QueueSetHandle_t\n\t#define xQueueSetMemberHandle QueueSetMemberHandle_t\n\t#define xTimeOutType TimeOut_t\n\t#define xMemoryRegion MemoryRegion_t\n\t#define xTaskParameters TaskParameters_t\n\t#define xTaskStatusType\tTaskStatus_t\n\t#define xTimerHandle TimerHandle_t\n\t#define xCoRoutineHandle CoRoutineHandle_t\n\t#define pdTASK_HOOK_CODE TaskHookFunction_t\n\t#define portTICK_RATE_MS portTICK_PERIOD_MS\n\t#define pcTaskGetTaskName pcTaskGetName\n\t#define pcTimerGetTimerName pcTimerGetName\n\t#define pcQueueGetQueueName pcQueueGetName\n\t#define vTaskGetTaskInfo vTaskGetInfo\n\t#define xTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter\n\n\t/* Backward compatibility within the scheduler code only - these definitions\n\tare not really required but are included for completeness. */\n\t#define tmrTIMER_CALLBACK TimerCallbackFunction_t\n\t#define pdTASK_CODE TaskFunction_t\n\t#define xListItem ListItem_t\n\t#define xList List_t\n\n\t/* For libraries that break the list data hiding, and access list structure\n\tmembers directly (which is not supposed to be done). */\n\t#define pxContainer pvContainer\n#endif /* configENABLE_BACKWARD_COMPATIBILITY */\n\n#if( configUSE_ALTERNATIVE_API != 0 )\n\t#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0\n#endif\n\n/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even\nif floating point hardware is otherwise supported by the FreeRTOS port in use.\nThis constant is not supported by all FreeRTOS ports that include floating\npoint support. */\n#ifndef configUSE_TASK_FPU_SUPPORT\n\t#define configUSE_TASK_FPU_SUPPORT 1\n#endif\n\n/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is\ncurrently used in ARMv8M ports. */\n#ifndef configENABLE_MPU\n\t#define configENABLE_MPU 0\n#endif\n\n/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is\ncurrently used in ARMv8M ports. */\n#ifndef configENABLE_FPU\n\t#define configENABLE_FPU 1\n#endif\n\n/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.\nThis is currently used in ARMv8M ports. */\n#ifndef configENABLE_TRUSTZONE\n\t#define configENABLE_TRUSTZONE 1\n#endif\n\n/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on\nthe Secure Side only. */\n#ifndef configRUN_FREERTOS_SECURE_ONLY\n\t#define configRUN_FREERTOS_SECURE_ONLY 0\n#endif\n\n/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using\n * dynamically allocated RAM, in which case when any task is deleted it is known\n * that both the task's stack and TCB need to be freed.  Sometimes the\n * FreeRTOSConfig.h settings only allow a task to be created using statically\n * allocated RAM, in which case when any task is deleted it is known that neither\n * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h\n * settings allow a task to be created using either statically or dynamically\n * allocated RAM, in which case a member of the TCB is used to record whether the\n * stack and/or TCB were allocated statically or dynamically, so when a task is\n * deleted the RAM that was allocated dynamically is freed again and no attempt is\n * made to free the RAM that was allocated statically.\n * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a\n * task to be created using either statically or dynamically allocated RAM.  Note\n * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with\n * a statically allocated stack and a dynamically allocated TCB.\n *\n * The following table lists various combinations of portUSING_MPU_WRAPPERS,\n * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and\n * when it is possible to have both static and dynamic allocation:\n *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |\n * |     |         |        |                             |                                   | Static Possible  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|\n * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |\n * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |\n * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |\n * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |\n * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+\n */\n#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE\t( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \\\n\t\t\t\t\t\t\t\t\t\t\t\t\t  ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )\n\n/*\n * In line with software engineering best practice, FreeRTOS implements a strict\n * data hiding policy, so the real structures used by FreeRTOS to maintain the\n * state of tasks, queues, semaphores, etc. are not accessible to the application\n * code.  However, if the application writer wants to statically allocate such\n * an object then the size of the object needs to be know.  Dummy structures\n * that are guaranteed to have the same size and alignment requirements of the\n * real objects are used for this purpose.  The dummy list and list item\n * structures below are used for inclusion in such a dummy structure.\n */\nstruct xSTATIC_LIST_ITEM\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tTickType_t xDummy2;\n\tvoid *pvDummy3[ 4 ];\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy4;\n\t#endif\n};\ntypedef struct xSTATIC_LIST_ITEM StaticListItem_t;\n\n/* See the comments above the struct xSTATIC_LIST_ITEM definition. */\nstruct xSTATIC_MINI_LIST_ITEM\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tTickType_t xDummy2;\n\tvoid *pvDummy3[ 2 ];\n};\ntypedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;\n\n/* See the comments above the struct xSTATIC_LIST_ITEM definition. */\ntypedef struct xSTATIC_LIST\n{\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy1;\n\t#endif\n\tUBaseType_t uxDummy2;\n\tvoid *pvDummy3;\n\tStaticMiniListItem_t xDummy4;\n\t#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )\n\t\tTickType_t xDummy5;\n\t#endif\n} StaticList_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Task structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a task then\n * the size of the task object needs to be know.  The StaticTask_t structure\n * below is provided for this purpose.  Its sizes and alignment requirements are\n * guaranteed to match those of the genuine structure, no matter which\n * architecture is being used, and no matter how the values in FreeRTOSConfig.h\n * are set.  Its contents are somewhat obfuscated in the hope users will\n * recognise that it would be unwise to make direct use of the structure members.\n */\ntypedef struct xSTATIC_TCB\n{\n\tvoid\t\t\t\t*pxDummy1;\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t\txMPU_SETTINGS\txDummy2;\n\t#endif\n\tStaticListItem_t\txDummy3[ 2 ];\n\tUBaseType_t\t\t\tuxDummy5;\n\tvoid\t\t\t\t*pxDummy6;\n\tuint8_t\t\t\t\tucDummy7[ configMAX_TASK_NAME_LEN ];\n\t#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n\t\tvoid\t\t\t*pxDummy8;\n\t#endif\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t\tUBaseType_t\t\tuxDummy9;\n\t#endif\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxDummy10[ 2 ];\n\t#endif\n\t#if ( configUSE_MUTEXES == 1 )\n\t\tUBaseType_t\t\tuxDummy12[ 2 ];\n\t#endif\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t\tvoid\t\t\t*pxDummy14;\n\t#endif\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\t\tvoid\t\t\t*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n\t#endif\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\tuint32_t\t\tulDummy16;\n\t#endif\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\tstruct\t_reent\txDummy17;\n\t#endif\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\tuint32_t \t\tulDummy18;\n\t\tuint8_t \t\tucDummy19;\n\t#endif\n\t#if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\tuint8_t\t\t\tuxDummy20;\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\tuint8_t ucDummy21;\n\t#endif\n\t#if ( configUSE_POSIX_ERRNO == 1 )\n\t\tint\t\t\t\tiDummy22;\n\t#endif\n} StaticTask_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the Queue structure used internally by\n * FreeRTOS is not accessible to application code.  However, if the application\n * writer wants to statically allocate the memory required to create a queue\n * then the size of the queue object needs to be know.  The StaticQueue_t\n * structure below is provided for this purpose.  Its sizes and alignment\n * requirements are guaranteed to match those of the genuine structure, no\n * matter which architecture is being used, and no matter how the values in\n * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope\n * users will recognise that it would be unwise to make direct use of the\n * structure members.\n */\ntypedef struct xSTATIC_QUEUE\n{\n\tvoid *pvDummy1[ 3 ];\n\n\tunion\n\t{\n\t\tvoid *pvDummy2;\n\t\tUBaseType_t uxDummy2;\n\t} u;\n\n\tStaticList_t xDummy3[ 2 ];\n\tUBaseType_t uxDummy4[ 3 ];\n\tuint8_t ucDummy5[ 2 ];\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucDummy6;\n\t#endif\n\n\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\tvoid *pvDummy7;\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy8;\n\t\tuint8_t ucDummy9;\n\t#endif\n\n} StaticQueue_t;\ntypedef StaticQueue_t StaticSemaphore_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the event group structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create an event group then the size of the event group object needs to be\n * know.  The StaticEventGroup_t structure below is provided for this purpose.\n * Its sizes and alignment requirements are guaranteed to match those of the\n * genuine structure, no matter which architecture is being used, and no matter\n * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat\n * obfuscated in the hope users will recognise that it would be unwise to make\n * direct use of the structure members.\n */\ntypedef struct xSTATIC_EVENT_GROUP\n{\n\tTickType_t xDummy1;\n\tStaticList_t xDummy2;\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy3;\n\t#endif\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\t\tuint8_t ucDummy4;\n\t#endif\n\n} StaticEventGroup_t;\n\n/*\n * In line with software engineering best practice, especially when supplying a\n * library that is likely to change in future versions, FreeRTOS implements a\n * strict data hiding policy.  This means the software timer structure used\n * internally by FreeRTOS is not accessible to application code.  However, if\n * the application writer wants to statically allocate the memory required to\n * create a software timer then the size of the queue object needs to be know.\n * The StaticTimer_t structure below is provided for this purpose.  Its sizes\n * and alignment requirements are guaranteed to match those of the genuine\n * structure, no matter which architecture is being used, and no matter how the\n * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in\n * the hope users will recognise that it would be unwise to make direct use of\n * the structure members.\n */\ntypedef struct xSTATIC_TIMER\n{\n\tvoid\t\t\t\t*pvDummy1;\n\tStaticListItem_t\txDummy2;\n\tTickType_t\t\t\txDummy3;\n\tvoid \t\t\t\t*pvDummy5;\n\tTaskFunction_t\t\tpvDummy6;\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxDummy7;\n\t#endif\n\tuint8_t \t\t\tucDummy8;\n\n} StaticTimer_t;\n\n/*\n* In line with software engineering best practice, especially when supplying a\n* library that is likely to change in future versions, FreeRTOS implements a\n* strict data hiding policy.  This means the stream buffer structure used\n* internally by FreeRTOS is not accessible to application code.  However, if\n* the application writer wants to statically allocate the memory required to\n* create a stream buffer then the size of the stream buffer object needs to be\n* know.  The StaticStreamBuffer_t structure below is provided for this purpose.\n* Its size and alignment requirements are guaranteed to match those of the\n* genuine structure, no matter which architecture is being used, and no matter\n* how the values in FreeRTOSConfig.h are set.  Its contents are somewhat\n* obfuscated in the hope users will recognise that it would be unwise to make\n* direct use of the structure members.\n*/\ntypedef struct xSTATIC_STREAM_BUFFER\n{\n\tsize_t uxDummy1[ 4 ];\n\tvoid * pvDummy2[ 3 ];\n\tuint8_t ucDummy3;\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxDummy4;\n\t#endif\n} StaticStreamBuffer_t;\n\n/* Message buffers are built on stream buffers. */\ntypedef StaticStreamBuffer_t StaticMessageBuffer_t;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* INC_FREERTOS_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/StackMacros.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef STACK_MACROS_H\n#define STACK_MACROS_H\n\n#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */\n\t#warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.\n#endif\n\n/*\n * Call the stack overflow hook function if the stack of the task being swapped\n * out is currently overflowed, or looks like it might have overflowed in the\n * past.\n *\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\n * the current stack state only - comparing the current top of stack value to\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\n * will also cause the last few stack bytes to be checked to ensure the value\n * to which the bytes were set when the task was created have not been\n * overwritten.  Note this second test does not guarantee that an overflowed\n * stack will always be recognised.\n */\n\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tconst uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;\t\t\t\t\t\t\t\\\n\t\tconst uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pulStack[ 0 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 1 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 2 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 3 ] != ulCheckValue ) )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tint8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tpcEndOfStack -= sizeof( ucExpectedStackBytes );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n/* Remove stack overflow macro if not being used. */\n#ifndef taskCHECK_FOR_STACK_OVERFLOW\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\n#endif\n\n\n\n#endif /* STACK_MACROS_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/atomic.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/**\n * @file atomic.h\n * @brief FreeRTOS atomic operation support.\n *\n * This file implements atomic functions by disabling interrupts globally.\n * Implementations with architecture specific atomic instructions can be\n * provided under each compiler directory.\n */\n\n#ifndef ATOMIC_H\n#define ATOMIC_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include atomic.h\"\n#endif\n\n/* Standard includes. */\n#include <stdint.h>\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*\n * Port specific definitions -- entering/exiting critical section.\n * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h\n *\n * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with\n * ATOMIC_ENTER_CRITICAL().\n *\n */\n#if defined( portSET_INTERRUPT_MASK_FROM_ISR )\n\n\t/* Nested interrupt scheme is supported in this port. */\n\t#define ATOMIC_ENTER_CRITICAL()\t \\\n\t\tUBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()\n\n\t#define ATOMIC_EXIT_CRITICAL()\t  \\\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )\n\n#else\n\n\t/* Nested interrupt scheme is NOT supported in this port. */\n\t#define ATOMIC_ENTER_CRITICAL()\t portENTER_CRITICAL()\n\t#define ATOMIC_EXIT_CRITICAL()\t  portEXIT_CRITICAL()\n\n#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */\n\n/*\n * Port specific definition -- \"always inline\".\n * Inline is compiler specific, and may not always get inlined depending on your\n * optimization level.  Also, inline is considered as performance optimization\n * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,\n * instead of resulting error, simply define it away.\n */\n#ifndef portFORCE_INLINE\n\t#define portFORCE_INLINE\n#endif\n\n#define ATOMIC_COMPARE_AND_SWAP_SUCCESS\t 0x1U\t\t/**< Compare and swap succeeded, swapped. */\n#define ATOMIC_COMPARE_AND_SWAP_FAILURE\t 0x0U\t\t/**< Compare and swap failed, did not swap. */\n\n/*----------------------------- Swap && CAS ------------------------------*/\n\n/**\n * Atomic compare-and-swap\n *\n * @brief Performs an atomic compare-and-swap operation on the specified values.\n *\n * @param[in, out] pulDestination  Pointer to memory location from where value is\n *                               to be loaded and checked.\n * @param[in] ulExchange         If condition meets, write this value to memory.\n * @param[in] ulComparand        Swap condition.\n *\n * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\n *\n * @note This function only swaps *pulDestination with ulExchange, if previous\n *       *pulDestination value equals ulComparand.\n */\nstatic portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tuint32_t ulExchange,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tuint32_t ulComparand )\n{\nuint32_t ulReturnValue;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tif( *pulDestination == ulComparand )\n\t\t{\n\t\t\t*pulDestination = ulExchange;\n\t\t\tulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\n\t\t}\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulReturnValue;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic swap (pointers)\n *\n * @brief Atomically sets the address pointed to by *ppvDestination to the value\n *        of *pvExchange.\n *\n * @param[in, out] ppvDestination  Pointer to memory location from where a pointer\n *                                 value is to be loaded and written back to.\n * @param[in] pvExchange           Pointer value to be written to *ppvDestination.\n *\n * @return The initial value of *ppvDestination.\n */\nstatic portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\tvoid * pvExchange )\n{\nvoid * pReturnValue;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tpReturnValue = *ppvDestination;\n\t\t*ppvDestination = pvExchange;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn pReturnValue;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic compare-and-swap (pointers)\n *\n * @brief Performs an atomic compare-and-swap operation on the specified pointer\n *        values.\n *\n * @param[in, out] ppvDestination  Pointer to memory location from where a pointer\n *                                 value is to be loaded and checked.\n * @param[in] pvExchange           If condition meets, write this value to memory.\n * @param[in] pvComparand          Swap condition.\n *\n * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.\n *\n * @note This function only swaps *ppvDestination with pvExchange, if previous\n *       *ppvDestination value equals pvComparand.\n */\nstatic portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tvoid * pvExchange,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\tvoid * pvComparand )\n{\nuint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tif( *ppvDestination == pvComparand )\n\t\t{\n\t\t\t*ppvDestination = pvExchange;\n\t\t\tulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;\n\t\t}\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulReturnValue;\n}\n\n\n/*----------------------------- Arithmetic ------------------------------*/\n\n/**\n * Atomic add\n *\n * @brief Atomically adds count to the value of the specified pointer points to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n * @param[in] ulCount      Value to be added to *pulAddend.\n *\n * @return previous *pulAddend value.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,\n\t\t\t\t\t\t\t\t\t\t\t\t uint32_t ulCount )\n{\n\tuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulAddend;\n\t\t*pulAddend += ulCount;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic subtract\n *\n * @brief Atomically subtracts count from the value of the specified pointer\n *        pointers to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n * @param[in] ulCount      Value to be subtract from *pulAddend.\n *\n * @return previous *pulAddend value.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,\n\t\t\t\t\t\t\t\t\t\t\t\t\t  uint32_t ulCount )\n{\n\tuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulAddend;\n\t\t*pulAddend -= ulCount;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic increment\n *\n * @brief Atomically increments the value of the specified pointer points to.\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n *\n * @return *pulAddend value before increment.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulAddend;\n\t\t*pulAddend += 1;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic decrement\n *\n * @brief Atomically decrements the value of the specified pointer points to\n *\n * @param[in,out] pulAddend  Pointer to memory location from where value is to be\n *                         loaded and written back to.\n *\n * @return *pulAddend value before decrement.\n */\nstatic portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulAddend;\n\t\t*pulAddend -= 1;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n\n/*----------------------------- Bitwise Logical ------------------------------*/\n\n/**\n * Atomic OR\n *\n * @brief Performs an atomic OR operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be ORed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,\n\t\t\t\t\t\t\t\t\t\t\t\tuint32_t ulValue )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulDestination;\n\t\t*pulDestination |= ulValue;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic AND\n *\n * @brief Performs an atomic AND operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be ANDed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t uint32_t ulValue )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulDestination;\n\t\t*pulDestination &= ulValue;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic NAND\n *\n * @brief Performs an atomic NAND operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be NANDed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t  uint32_t ulValue )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulDestination;\n\t\t*pulDestination = ~( ulCurrent & ulValue );\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n/*-----------------------------------------------------------*/\n\n/**\n * Atomic XOR\n *\n * @brief Performs an atomic XOR operation on the specified values.\n *\n * @param [in, out] pulDestination  Pointer to memory location from where value is\n *                                to be loaded and written back to.\n * @param [in] ulValue            Value to be XORed with *pulDestination.\n *\n * @return The original value of *pulDestination.\n */\nstatic portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,\n\t\t\t\t\t\t\t\t\t\t\t\t uint32_t ulValue )\n{\nuint32_t ulCurrent;\n\n\tATOMIC_ENTER_CRITICAL();\n\t{\n\t\tulCurrent = *pulDestination;\n\t\t*pulDestination ^= ulValue;\n\t}\n\tATOMIC_EXIT_CRITICAL();\n\n\treturn ulCurrent;\n}\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* ATOMIC_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/croutine.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef CO_ROUTINE_H\n#define CO_ROUTINE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include croutine.h\"\n#endif\n\n#include \"list.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Used to hide the implementation of the co-routine control block.  The\ncontrol block structure however has to be included in the header due to\nthe macro implementation of the co-routine functionality. */\ntypedef void * CoRoutineHandle_t;\n\n/* Defines the prototype to which co-routine functions must conform. */\ntypedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );\n\ntypedef struct corCoRoutineControlBlock\n{\n\tcrCOROUTINE_CODE \tpxCoRoutineFunction;\n\tListItem_t\t\t\txGenericListItem;\t/*< List item used to place the CRCB in ready and blocked queues. */\n\tListItem_t\t\t\txEventListItem;\t\t/*< List item used to place the CRCB in event lists. */\n\tUBaseType_t \t\tuxPriority;\t\t\t/*< The priority of the co-routine in relation to other co-routines. */\n\tUBaseType_t \t\tuxIndex;\t\t\t/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */\n\tuint16_t \t\t\tuxState;\t\t\t/*< Used internally by the co-routine implementation. */\n} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */\n\n/**\n * croutine. h\n *<pre>\n BaseType_t xCoRoutineCreate(\n                                 crCOROUTINE_CODE pxCoRoutineCode,\n                                 UBaseType_t uxPriority,\n                                 UBaseType_t uxIndex\n                               );</pre>\n *\n * Create a new co-routine and add it to the list of co-routines that are\n * ready to run.\n *\n * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine\n * functions require special syntax - see the co-routine section of the WEB\n * documentation for more information.\n *\n * @param uxPriority The priority with respect to other co-routines at which\n *  the co-routine will run.\n *\n * @param uxIndex Used to distinguish between different co-routines that\n * execute the same function.  See the example below and the co-routine section\n * of the WEB documentation for further information.\n *\n * @return pdPASS if the co-routine was successfully created and added to a ready\n * list, otherwise an error code defined with ProjDefs.h.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n // This may not be necessary for const variables.\n static const char cLedToFlash[ 2 ] = { 5, 6 };\n static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // This co-routine just delays for a fixed period, then toggles\n         // an LED.  Two co-routines are created using this function, so\n         // the uxIndex parameter is used to tell the co-routine which\n         // LED to flash and how int32_t to delay.  This assumes xQueue has\n         // already been created.\n         vParTestToggleLED( cLedToFlash[ uxIndex ] );\n         crDELAY( xHandle, uxFlashRates[ uxIndex ] );\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }\n\n // Function that creates two co-routines.\n void vOtherFunction( void )\n {\n uint8_t ucParameterToPass;\n TaskHandle_t xHandle;\n\n     // Create two co-routines at priority 0.  The first is given index 0\n     // so (from the code above) toggles LED 5 every 200 ticks.  The second\n     // is given index 1 so toggles LED 6 every 400 ticks.\n     for( uxIndex = 0; uxIndex < 2; uxIndex++ )\n     {\n         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );\n     }\n }\n   </pre>\n * \\defgroup xCoRoutineCreate xCoRoutineCreate\n * \\ingroup Tasks\n */\nBaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );\n\n\n/**\n * croutine. h\n *<pre>\n void vCoRoutineSchedule( void );</pre>\n *\n * Run a co-routine.\n *\n * vCoRoutineSchedule() executes the highest priority co-routine that is able\n * to run.  The co-routine will execute until it either blocks, yields or is\n * preempted by a task.  Co-routines execute cooperatively so one\n * co-routine cannot be preempted by another, but can be preempted by a task.\n *\n * If an application comprises of both tasks and co-routines then\n * vCoRoutineSchedule should be called from the idle task (in an idle task\n * hook).\n *\n * Example usage:\n   <pre>\n // This idle task hook will schedule a co-routine each time it is called.\n // The rest of the idle task will execute between co-routine calls.\n void vApplicationIdleHook( void )\n {\n\tvCoRoutineSchedule();\n }\n\n // Alternatively, if you do not require any other part of the idle task to\n // execute, the idle task hook can call vCoRoutineSchedule() within an\n // infinite loop.\n void vApplicationIdleHook( void )\n {\n    for( ;; )\n    {\n        vCoRoutineSchedule();\n    }\n }\n </pre>\n * \\defgroup vCoRoutineSchedule vCoRoutineSchedule\n * \\ingroup Tasks\n */\nvoid vCoRoutineSchedule( void );\n\n/**\n * croutine. h\n * <pre>\n crSTART( CoRoutineHandle_t xHandle );</pre>\n *\n * This macro MUST always be called at the start of a co-routine function.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static int32_t ulAVariable;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n          // Co-routine functionality goes here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:\n\n/**\n * croutine. h\n * <pre>\n crEND();</pre>\n *\n * This macro MUST always be called at the end of a co-routine function.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static int32_t ulAVariable;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n          // Co-routine functionality goes here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crSTART crSTART\n * \\ingroup Tasks\n */\n#define crEND() }\n\n/*\n * These macros are intended for internal use by the co-routine implementation\n * only.  The macros should not be used directly by application writers.\n */\n#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):\n#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):\n\n/**\n * croutine. h\n *<pre>\n crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>\n *\n * Delay a co-routine for a fixed period of time.\n *\n * crDELAY can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * @param xHandle The handle of the co-routine to delay.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param xTickToDelay The number of ticks that the co-routine should delay\n * for.  The actual amount of time this equates to is defined by\n * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS\n * can be used to convert ticks to milliseconds.\n *\n * Example usage:\n   <pre>\n // Co-routine to be created.\n void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n // This may not be necessary for const variables.\n // We are to delay for 200ms.\n static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;\n\n     // Must start every co-routine with a call to crSTART();\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n        // Delay for 200ms.\n        crDELAY( xHandle, xDelayTime );\n\n        // Do something here.\n     }\n\n     // Must end every co-routine with a call to crEND();\n     crEND();\n }</pre>\n * \\defgroup crDELAY crDELAY\n * \\ingroup Tasks\n */\n#define crDELAY( xHandle, xTicksToDelay )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( ( xTicksToDelay ) > 0 )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tvCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tcrSET_STATE0( ( xHandle ) );\n\n/**\n * <pre>\n crQUEUE_SEND(\n                  CoRoutineHandle_t xHandle,\n                  QueueHandle_t pxQueue,\n                  void *pvItemToQueue,\n                  TickType_t xTicksToWait,\n                  BaseType_t *pxResult\n             )</pre>\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_SEND can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue on which the data will be posted.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvItemToQueue A pointer to the data being posted onto the queue.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied from pvItemToQueue into the queue\n * itself.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for space to become available on the queue, should space not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example\n * below).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully posted onto the queue, otherwise it will be set to an\n * error defined within ProjDefs.h.\n *\n * Example usage:\n   <pre>\n // Co-routine function that blocks for a fixed period then posts a number onto\n // a queue.\n static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static BaseType_t xNumberToPost = 0;\n static BaseType_t xResult;\n\n    // Co-routines must begin with a call to crSTART().\n    crSTART( xHandle );\n\n    for( ;; )\n    {\n        // This assumes the queue has already been created.\n        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );\n\n        if( xResult != pdPASS )\n        {\n            // The message was not posted!\n        }\n\n        // Increment the number to be posted onto the queue.\n        xNumberToPost++;\n\n        // Delay for 100 ticks.\n        crDELAY( xHandle, 100 );\n    }\n\n    // Co-routines must end with a call to crEND().\n    crEND();\n }</pre>\n * \\defgroup crQUEUE_SEND crQUEUE_SEND\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );\t\\\n\tif( *( pxResult ) == errQUEUE_BLOCKED )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( *pxResult == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*pxResult = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_RECEIVE(\n                     CoRoutineHandle_t xHandle,\n                     QueueHandle_t pxQueue,\n                     void *pvBuffer,\n                     TickType_t xTicksToWait,\n                     BaseType_t *pxResult\n                 )</pre>\n *\n * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine\n * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.\n *\n * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas\n * xQueueSend() and xQueueReceive() can only be used from tasks.\n *\n * crQUEUE_RECEIVE can only be called from the co-routine function itself - not\n * from within a function called by the co-routine function.  This is because\n * co-routines do not maintain their own stack.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xHandle The handle of the calling co-routine.  This is the xHandle\n * parameter of the co-routine function.\n *\n * @param pxQueue The handle of the queue from which the data will be received.\n * The handle is obtained as the return value when the queue is created using\n * the xQueueCreate() API function.\n *\n * @param pvBuffer The buffer into which the received item is to be copied.\n * The number of bytes of each queued item is specified when the queue is\n * created.  This number of bytes is copied into pvBuffer.\n *\n * @param xTickToDelay The number of ticks that the co-routine should block\n * to wait for data to become available from the queue, should data not be\n * available immediately. The actual amount of time this equates to is defined\n * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant\n * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the\n * crQUEUE_SEND example).\n *\n * @param pxResult The variable pointed to by pxResult will be set to pdPASS if\n * data was successfully retrieved from the queue, otherwise it will be set to\n * an error code as defined within ProjDefs.h.\n *\n * Example usage:\n <pre>\n // A co-routine receives the number of an LED to flash from a queue.  It\n // blocks on the queue until the number is received.\n static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // Variables in co-routines must be declared static if they must maintain value across a blocking call.\n static BaseType_t xResult;\n static UBaseType_t uxLEDToFlash;\n\n    // All co-routines must start with a call to crSTART().\n    crSTART( xHandle );\n\n    for( ;; )\n    {\n        // Wait for data to become available on the queue.\n        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n\n        if( xResult == pdPASS )\n        {\n            // We received the LED to flash - flash it!\n            vParTestToggleLED( uxLEDToFlash );\n        }\n    }\n\n    crEND();\n }</pre>\n * \\defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );\t\t\\\n\tif( *( pxResult ) == errQUEUE_BLOCKED ) \t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE0( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tif( *( pxResult ) == errQUEUE_YIELD )\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tcrSET_STATE1( ( xHandle ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t*( pxResult ) = pdPASS;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_SEND_FROM_ISR(\n                            QueueHandle_t pxQueue,\n                            void *pvItemToQueue,\n                            BaseType_t xCoRoutinePreviouslyWoken\n                       )</pre>\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue\n * that is being used from within a co-routine.\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto\n * the same queue multiple times from a single interrupt.  The first call\n * should always pass in pdFALSE.  Subsequent calls should pass in\n * the value returned from the previous call.\n *\n * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is\n * used by the ISR to determine if a context switch may be required following\n * the ISR.\n *\n * Example usage:\n <pre>\n // A co-routine that blocks on a queue waiting for characters to be received.\n static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n char cRxedChar;\n BaseType_t xResult;\n\n     // All co-routines must start with a call to crSTART().\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // Wait for data to become available on the queue.  This assumes the\n         // queue xCommsRxQueue has already been created!\n         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );\n\n         // Was a character received?\n         if( xResult == pdPASS )\n         {\n             // Process the character here.\n         }\n     }\n\n     // All co-routines must end with a call to crEND().\n     crEND();\n }\n\n // An ISR that uses a queue to send characters received on a serial port to\n // a co-routine.\n void vUART_ISR( void )\n {\n char cRxedChar;\n BaseType_t xCRWokenByPost = pdFALSE;\n\n     // We loop around reading characters until there are none left in the UART.\n     while( UART_RX_REG_NOT_EMPTY() )\n     {\n         // Obtain the character from the UART.\n         cRxedChar = UART_RX_REG;\n\n         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE\n         // the first time around the loop.  If the post causes a co-routine\n         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.\n         // In this manner we can ensure that if more than one co-routine is\n         // blocked on the queue only one is woken by this ISR no matter how\n         // many characters are posted to the queue.\n         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );\n     }\n }</pre>\n * \\defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )\n\n\n/**\n * croutine. h\n * <pre>\n  crQUEUE_SEND_FROM_ISR(\n                            QueueHandle_t pxQueue,\n                            void *pvBuffer,\n                            BaseType_t * pxCoRoutineWoken\n                       )</pre>\n *\n * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the\n * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()\n * functions used by tasks.\n *\n * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to\n * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and\n * xQueueReceiveFromISR() can only be used to pass data between a task and and\n * ISR.\n *\n * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data\n * from a queue that is being used from within a co-routine (a co-routine\n * posted to the queue).\n *\n * See the co-routine section of the WEB documentation for information on\n * passing data between tasks and co-routines and between ISR's and\n * co-routines.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvBuffer A pointer to a buffer into which the received item will be\n * placed.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from the queue into\n * pvBuffer.\n *\n * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become\n * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a\n * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise\n * *pxCoRoutineWoken will remain unchanged.\n *\n * @return pdTRUE an item was successfully received from the queue, otherwise\n * pdFALSE.\n *\n * Example usage:\n <pre>\n // A co-routine that posts a character to a queue then blocks for a fixed\n // period.  The character is incremented each time.\n static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )\n {\n // cChar holds its value while this co-routine is blocked and must therefore\n // be declared static.\n static char cCharToTx = 'a';\n BaseType_t xResult;\n\n     // All co-routines must start with a call to crSTART().\n     crSTART( xHandle );\n\n     for( ;; )\n     {\n         // Send the next character to the queue.\n         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );\n\n         if( xResult == pdPASS )\n         {\n             // The character was successfully posted to the queue.\n         }\n\t\t else\n\t\t {\n\t\t\t// Could not post the character to the queue.\n\t\t }\n\n         // Enable the UART Tx interrupt to cause an interrupt in this\n\t\t // hypothetical UART.  The interrupt will obtain the character\n\t\t // from the queue and send it.\n\t\t ENABLE_RX_INTERRUPT();\n\n\t\t // Increment to the next character then block for a fixed period.\n\t\t // cCharToTx will maintain its value across the delay as it is\n\t\t // declared static.\n\t\t cCharToTx++;\n\t\t if( cCharToTx > 'x' )\n\t\t {\n\t\t\tcCharToTx = 'a';\n\t\t }\n\t\t crDELAY( 100 );\n     }\n\n     // All co-routines must end with a call to crEND().\n     crEND();\n }\n\n // An ISR that uses a queue to receive characters to send on a UART.\n void vUART_ISR( void )\n {\n char cCharToTx;\n BaseType_t xCRWokenByPost = pdFALSE;\n\n     while( UART_TX_REG_EMPTY() )\n     {\n         // Are there any characters in the queue waiting to be sent?\n\t\t // xCRWokenByPost will automatically be set to pdTRUE if a co-routine\n\t\t // is woken by the post - ensuring that only a single co-routine is\n\t\t // woken no matter how many times we go around this loop.\n         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )\n\t\t {\n\t\t\t SEND_CHARACTER( cCharToTx );\n\t\t }\n     }\n }</pre>\n * \\defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR\n * \\ingroup Tasks\n */\n#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )\n\n/*\n * This function is intended for internal use by the co-routine macros only.\n * The macro nature of the co-routine implementation requires that the\n * prototype appears here.  The function should not be used by application\n * writers.\n *\n * Removes the current co-routine from its ready list and places it in the\n * appropriate delayed list.\n */\nvoid vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );\n\n/*\n * This function is intended for internal use by the queue implementation only.\n * The function should not be used by application writers.\n *\n * Removes the highest priority co-routine from the event list and places it in\n * the pending ready list.\n */\nBaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* CO_ROUTINE_H */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/deprecated_definitions.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef DEPRECATED_DEFINITIONS_H\n#define DEPRECATED_DEFINITIONS_H\n\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\npre-processor definition was used to ensure the pre-processor found the correct\nportmacro.h file for the port being used.  That scheme was deprecated in favour\nof setting the compiler's include path such that it found the correct\nportmacro.h file - removing the need for the constant and allowing the\nportmacro.h file to be located anywhere in relation to the port being used.  The\ndefinitions below remain in the code for backward compatibility only.  New\nprojects should not use them. */\n\n#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\pc\\portmacro.h\"\n\ttypedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT\n\t#include \"..\\..\\Source\\portable\\owatcom\\16bitdos\\flsh186\\portmacro.h\"\n\ttypedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef GCC_MEGA_AVR\n\t#include \"../portable/GCC/ATMega323/portmacro.h\"\n#endif\n\n#ifdef IAR_MEGA_AVR\n\t#include \"../portable/IAR/ATMega323/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC24_PORT\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_DSPIC_PORT\n\t#include \"../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC18F_PORT\n\t#include \"../../Source/portable/MPLAB/PIC18F/portmacro.h\"\n#endif\n\n#ifdef MPLAB_PIC32MX_PORT\n\t#include \"../../Source/portable/MPLAB/PIC32MX/portmacro.h\"\n#endif\n\n#ifdef _FEDPICC\n\t#include \"libFreeRTOS/Include/portmacro.h\"\n#endif\n\n#ifdef SDCC_CYGNAL\n\t#include \"../../Source/portable/SDCC/Cygnal/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7\n\t#include \"../../Source/portable/GCC/ARM7_LPC2000/portmacro.h\"\n#endif\n\n#ifdef GCC_ARM7_ECLIPSE\n\t#include \"portmacro.h\"\n#endif\n\n#ifdef ROWLEY_LPC23xx\n\t#include \"../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h\"\n#endif\n\n#ifdef IAR_MSP430\n\t#include \"..\\..\\Source\\portable\\IAR\\MSP430\\portmacro.h\"\n#endif\n\n#ifdef GCC_MSP430\n\t#include \"../../Source/portable/GCC/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ROWLEY_MSP430\n\t#include \"../../Source/portable/Rowley/MSP430F449/portmacro.h\"\n#endif\n\n#ifdef ARM7_LPC21xx_KEIL_RVDS\n\t#include \"..\\..\\Source\\portable\\RVDS\\ARM7_LPC21xx\\portmacro.h\"\n#endif\n\n#ifdef SAM7_GCC\n\t#include \"../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h\"\n#endif\n\n#ifdef SAM7_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM7S64\\portmacro.h\"\n#endif\n\n#ifdef SAM9XE_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\AtmelSAM9XE\\portmacro.h\"\n#endif\n\n#ifdef LPC2000_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\LPC2000\\portmacro.h\"\n#endif\n\n#ifdef STR71X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR71x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR75X_GCC\n\t#include \"..\\..\\Source\\portable\\GCC\\STR75x\\portmacro.h\"\n#endif\n\n#ifdef STR91X_IAR\n\t#include \"..\\..\\Source\\portable\\IAR\\STR91x\\portmacro.h\"\n#endif\n\n#ifdef GCC_H8S\n\t#include \"../../Source/portable/GCC/H8S2329/portmacro.h\"\n#endif\n\n#ifdef GCC_AT91FR40008\n\t#include \"../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h\"\n#endif\n\n#ifdef RVDS_ARMCM3_LM3S102\n\t#include \"../../Source/portable/RVDS/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3_LM3S102\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef GCC_ARMCM3\n\t#include \"../../Source/portable/GCC/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARM_CM3\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef IAR_ARMCM3_LM\n\t#include \"../../Source/portable/IAR/ARM_CM3/portmacro.h\"\n#endif\n\n#ifdef HCS12_CODE_WARRIOR\n\t#include \"../../Source/portable/CodeWarrior/HCS12/portmacro.h\"\n#endif\n\n#ifdef MICROBLAZE_GCC\n\t#include \"../../Source/portable/GCC/MicroBlaze/portmacro.h\"\n#endif\n\n#ifdef TERN_EE\n\t#include \"..\\..\\Source\\portable\\Paradigm\\Tern_EE\\small\\portmacro.h\"\n#endif\n\n#ifdef GCC_HCS12\n\t#include \"../../Source/portable/GCC/HCS12/portmacro.h\"\n#endif\n\n#ifdef GCC_MCF5235\n    #include \"../../Source/portable/GCC/MCF5235/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_GCC\n\t#include \"../../../Source/portable/GCC/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef COLDFIRE_V2_CODEWARRIOR\n\t#include \"../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC405\n\t#include \"../../Source/portable/GCC/PPC405_Xilinx/portmacro.h\"\n#endif\n\n#ifdef GCC_PPC440\n\t#include \"../../Source/portable/GCC/PPC440_Xilinx/portmacro.h\"\n#endif\n\n#ifdef _16FX_SOFTUNE\n\t#include \"..\\..\\Source\\portable\\Softune\\MB96340\\portmacro.h\"\n#endif\n\n#ifdef BCC_INDUSTRIAL_PC_PORT\n\t/* A short file name has to be used in place of the normal\n\tFreeRTOSConfig.h when using the Borland compiler. */\n\t#include \"frconfig.h\"\n\t#include \"..\\portable\\BCC\\16BitDOS\\PC\\prtmacro.h\"\n    typedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef BCC_FLASH_LITE_186_PORT\n\t/* A short file name has to be used in place of the normal\n\tFreeRTOSConfig.h when using the Borland compiler. */\n\t#include \"frconfig.h\"\n\t#include \"..\\portable\\BCC\\16BitDOS\\flsh186\\prtmacro.h\"\n    typedef void ( __interrupt __far *pxISR )();\n#endif\n\n#ifdef __GNUC__\n   #ifdef __AVR32_AVR32A__\n\t   #include \"portmacro.h\"\n   #endif\n#endif\n\n#ifdef __ICCAVR32__\n   #ifdef __CORE__\n      #if __CORE__ == __AVR32A__\n\t      #include \"portmacro.h\"\n      #endif\n   #endif\n#endif\n\n#ifdef __91467D\n\t#include \"portmacro.h\"\n#endif\n\n#ifdef __96340\n\t#include \"portmacro.h\"\n#endif\n\n\n#ifdef __IAR_V850ES_Fx3__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx3_L__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Jx2__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_V850ES_Hx2__\n\t#include \"../../Source/portable/IAR/V850ES/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3__\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#ifdef __IAR_78K0R_Kx3L__\n\t#include \"../../Source/portable/IAR/78K0R/portmacro.h\"\n#endif\n\n#endif /* DEPRECATED_DEFINITIONS_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/event_groups.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef EVENT_GROUPS_H\n#define EVENT_GROUPS_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include event_groups.h\"\n#endif\n\n/* FreeRTOS includes. */\n#include \"timers.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/**\n * An event group is a collection of bits to which an application can assign a\n * meaning.  For example, an application may create an event group to convey\n * the status of various CAN bus related events in which bit 0 might mean \"A CAN\n * message has been received and is ready for processing\", bit 1 might mean \"The\n * application has queued a message that is ready for sending onto the CAN\n * network\", and bit 2 might mean \"It is time to send a SYNC message onto the\n * CAN network\" etc.  A task can then test the bit values to see which events\n * are active, and optionally enter the Blocked state to wait for a specified\n * bit or a group of specified bits to be active.  To continue the CAN bus\n * example, a CAN controlling task can enter the Blocked state (and therefore\n * not consume any processing time) until either bit 0, bit 1 or bit 2 are\n * active, at which time the bit that was actually active would inform the task\n * which action it had to take (process a received message, send a message, or\n * send a SYNC).\n *\n * The event groups implementation contains intelligence to avoid race\n * conditions that would otherwise occur were an application to use a simple\n * variable for the same purpose.  This is particularly important with respect\n * to when a bit within an event group is to be cleared, and when bits have to\n * be set and then tested atomically - as is the case where event groups are\n * used to create a synchronisation point between multiple tasks (a\n * 'rendezvous').\n *\n * \\defgroup EventGroup\n */\n\n\n\n/**\n * event_groups.h\n *\n * Type by which event groups are referenced.  For example, a call to\n * xEventGroupCreate() returns an EventGroupHandle_t variable that can then\n * be used as a parameter to other event group functions.\n *\n * \\defgroup EventGroupHandle_t EventGroupHandle_t\n * \\ingroup EventGroup\n */\nstruct EventGroupDef_t;\ntypedef struct EventGroupDef_t * EventGroupHandle_t;\n\n/*\n * The type that holds event bits always matches TickType_t - therefore the\n * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,\n * 32 bits if set to 0.\n *\n * \\defgroup EventBits_t EventBits_t\n * \\ingroup EventGroup\n */\ntypedef TickType_t EventBits_t;\n\n/**\n * event_groups.h\n *<pre>\n EventGroupHandle_t xEventGroupCreate( void );\n </pre>\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGropuCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see http://www.freertos.org/a00111.html).  If an event group is created\n * using xEventGropuCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If there was insufficient FreeRTOS heap available to create the\n * event group then NULL is returned.  See http://www.freertos.org/a00111.html\n *\n * Example usage:\n   <pre>\n\t// Declare a variable to hold the created event group.\n\tEventGroupHandle_t xCreatedEventGroup;\n\n\t// Attempt to create the event group.\n\txCreatedEventGroup = xEventGroupCreate();\n\n\t// Was the event group created successfully?\n\tif( xCreatedEventGroup == NULL )\n\t{\n\t\t// The event group was not created because there was insufficient\n\t\t// FreeRTOS heap available.\n\t}\n\telse\n\t{\n\t\t// The event group was created.\n\t}\n   </pre>\n * \\defgroup xEventGroupCreate xEventGroupCreate\n * \\ingroup EventGroup\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tEventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n *<pre>\n EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );\n </pre>\n *\n * Create a new event group.\n *\n * Internally, within the FreeRTOS implementation, event groups use a [small]\n * block of memory, in which the event group's structure is stored.  If an event\n * groups is created using xEventGropuCreate() then the required memory is\n * automatically dynamically allocated inside the xEventGroupCreate() function.\n * (see http://www.freertos.org/a00111.html).  If an event group is created\n * using xEventGropuCreateStatic() then the application writer must instead\n * provide the memory that will get used by the event group.\n * xEventGroupCreateStatic() therefore allows an event group to be created\n * without using any dynamic memory allocation.\n *\n * Although event groups are not related to ticks, for internal implementation\n * reasons the number of bits available for use in an event group is dependent\n * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If\n * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit\n * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has\n * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store\n * event bits within an event group.\n *\n * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type\n * StaticEventGroup_t, which will be then be used to hold the event group's data\n * structures, removing the need for the memory to be allocated dynamically.\n *\n * @return If the event group was created then a handle to the event group is\n * returned.  If pxEventGroupBuffer was NULL then NULL is returned.\n *\n * Example usage:\n   <pre>\n\t// StaticEventGroup_t is a publicly accessible structure that has the same\n\t// size and alignment requirements as the real event group structure.  It is\n\t// provided as a mechanism for applications to know the size of the event\n\t// group (which is dependent on the architecture and configuration file\n\t// settings) without breaking the strict data hiding policy by exposing the\n\t// real event group internals.  This StaticEventGroup_t variable is passed\n\t// into the xSemaphoreCreateEventGroupStatic() function and is used to store\n\t// the event group's data structures\n\tStaticEventGroup_t xEventGroupBuffer;\n\n\t// Create the event group without dynamically allocating any memory.\n\txEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );\n   </pre>\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tEventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupWaitBits( \tEventGroupHandle_t xEventGroup,\n\t\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xClearOnExit,\n\t\t\t\t\t\t\t\t\t\tconst BaseType_t xWaitForAllBits,\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTicksToWait );\n </pre>\n *\n * [Potentially] block to wait for one or more bits to be set within a\n * previously created event group.\n *\n * This function cannot be called from an interrupt.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and/or bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within\n * uxBitsToWaitFor that are set within the event group will be cleared before\n * xEventGroupWaitBits() returns if the wait condition was met (if the function\n * returns for a reason other than a timeout).  If xClearOnExit is set to\n * pdFALSE then the bits set in the event group are not altered when the call to\n * xEventGroupWaitBits() returns.\n *\n * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then\n * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor\n * are set or the specified block time expires.  If xWaitForAllBits is set to\n * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set\n * in uxBitsToWaitFor is set or the specified block time expires.  The block\n * time is specified by the xTicksToWait parameter.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for one/all (depending on the xWaitForAllBits value) of the bits specified by\n * uxBitsToWaitFor to become set.\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupWaitBits() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupWaitBits() returned because the bits it was waiting for were set\n * then the returned value is the event group value before any bits were\n * automatically cleared in the case that xClearOnExit parameter was set to\n * pdTRUE.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n\n\t\t// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within\n\t\t// the event group.  Clear the bits before exiting.\n\t\tuxBits = xEventGroupWaitBits(\n\t\t\t\t\txEventGroup,\t// The event group being tested.\n\t\t\t\t\tBIT_0 | BIT_4,\t// The bits within the event group to wait for.\n\t\t\t\t\tpdTRUE,\t\t\t// BIT_0 and BIT_4 should be cleared before returning.\n\t\t\t\t\tpdFALSE,\t\t// Don't wait for both bits, either bit will do.\n\t\t\t\t\txTicksToWait );\t// Wait a maximum of 100ms for either bit to be set.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because both bits were set.\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because just BIT_0 was set.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because just BIT_4 was set.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// xEventGroupWaitBits() returned because xTicksToWait ticks passed\n\t\t\t// without either BIT_0 or BIT_4 becoming set.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupWaitBits xEventGroupWaitBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );\n </pre>\n *\n * Clear bits within an event group.  This function cannot be called from an\n * interrupt.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear\n * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to\n * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.\n *\n * @return The value of the event group before the specified bits were cleared.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\n\t\tuxBits = xEventGroupClearBits(\n\t\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being cleared.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// Both bit 0 and bit 4 were set before xEventGroupClearBits() was\n\t\t\t// called.  Both will now be clear (not set).\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// Bit 0 was set before xEventGroupClearBits() was called.  It will\n\t\t\t// now be clear.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// Bit 4 was set before xEventGroupClearBits() was called.  It will\n\t\t\t// now be clear.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// Neither bit 0 nor bit 4 were set in the first place.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupClearBits xEventGroupClearBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n </pre>\n *\n * A version of xEventGroupClearBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed\n * while interrupts are disabled, so protects event groups that are accessed\n * from tasks by suspending the scheduler rather than disabling interrupts.  As\n * a result event groups cannot be accessed directly from an interrupt service\n * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the\n * timer task to have the clear operation performed in the context of the timer\n * task.\n *\n * @param xEventGroup The event group in which the bits are to be cleared.\n *\n * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.\n * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3\n * and bit 0 set uxBitsToClear to 0x09.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   // An event group which it is assumed has already been created by a call to\n   // xEventGroupCreate().\n   EventGroupHandle_t xEventGroup;\n\n   void anInterruptHandler( void )\n   {\n\t\t// Clear bit 0 and bit 4 in xEventGroup.\n\t\txResult = xEventGroupClearBitsFromISR(\n\t\t\t\t\t\t\txEventGroup,\t // The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4 ); // The bits being set.\n\n\t\tif( xResult == pdPASS )\n\t\t{\n\t\t\t// The message was posted successfully.\n\t\t}\n  }\n   </pre>\n * \\defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR\n * \\ingroup EventGroup\n */\n#if( configUSE_TRACE_FACILITY == 1 )\n\tBaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;\n#else\n\t#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );\n </pre>\n *\n * Set bits within an event group.\n * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()\n * is a version that can be called from an interrupt.\n *\n * Setting bits in an event group will automatically unblock tasks that are\n * blocked waiting for the bits.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @return The value of the event group at the time the call to\n * xEventGroupSetBits() returns.  There are two reasons why the returned value\n * might have the bits specified by the uxBitsToSet parameter cleared.  First,\n * if setting a bit results in a task that was waiting for the bit leaving the\n * blocked state then it is possible the bit will be cleared automatically\n * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any\n * unblocked (or otherwise Ready state) task that has a priority above that of\n * the task that called xEventGroupSetBits() will execute and may change the\n * event group value before the call to xEventGroupSetBits() returns.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   void aFunction( EventGroupHandle_t xEventGroup )\n   {\n   EventBits_t uxBits;\n\n\t\t// Set bit 0 and bit 4 in xEventGroup.\n\t\tuxBits = xEventGroupSetBits(\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4 );// The bits being set.\n\n\t\tif( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )\n\t\t{\n\t\t\t// Both bit 0 and bit 4 remained set when the function returned.\n\t\t}\n\t\telse if( ( uxBits & BIT_0 ) != 0 )\n\t\t{\n\t\t\t// Bit 0 remained set when the function returned, but bit 4 was\n\t\t\t// cleared.  It might be that bit 4 was cleared automatically as a\n\t\t\t// task that was waiting for bit 4 was removed from the Blocked\n\t\t\t// state.\n\t\t}\n\t\telse if( ( uxBits & BIT_4 ) != 0 )\n\t\t{\n\t\t\t// Bit 4 remained set when the function returned, but bit 0 was\n\t\t\t// cleared.  It might be that bit 0 was cleared automatically as a\n\t\t\t// task that was waiting for bit 0 was removed from the Blocked\n\t\t\t// state.\n\t\t}\n\t\telse\n\t\t{\n\t\t\t// Neither bit 0 nor bit 4 remained set.  It might be that a task\n\t\t\t// was waiting for both of the bits to be set, and the bits were\n\t\t\t// cleared as the task left the Blocked state.\n\t\t}\n   }\n   </pre>\n * \\defgroup xEventGroupSetBits xEventGroupSetBits\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );\n </pre>\n *\n * A version of xEventGroupSetBits() that can be called from an interrupt.\n *\n * Setting bits in an event group is not a deterministic operation because there\n * are an unknown number of tasks that may be waiting for the bit or bits being\n * set.  FreeRTOS does not allow nondeterministic operations to be performed in\n * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()\n * sends a message to the timer task to have the set operation performed in the\n * context of the timer task - where a scheduler lock is used in place of a\n * critical section.\n *\n * @param xEventGroup The event group in which the bits are to be set.\n *\n * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.\n * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3\n * and bit 0 set uxBitsToSet to 0x09.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task is higher than the priority of the\n * currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE by\n * xEventGroupSetBitsFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return If the request to execute the function was posted successfully then\n * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned\n * if the timer service queue was full.\n *\n * Example usage:\n   <pre>\n   #define BIT_0\t( 1 << 0 )\n   #define BIT_4\t( 1 << 4 )\n\n   // An event group which it is assumed has already been created by a call to\n   // xEventGroupCreate().\n   EventGroupHandle_t xEventGroup;\n\n   void anInterruptHandler( void )\n   {\n   BaseType_t xHigherPriorityTaskWoken, xResult;\n\n\t\t// xHigherPriorityTaskWoken must be initialised to pdFALSE.\n\t\txHigherPriorityTaskWoken = pdFALSE;\n\n\t\t// Set bit 0 and bit 4 in xEventGroup.\n\t\txResult = xEventGroupSetBitsFromISR(\n\t\t\t\t\t\t\txEventGroup,\t// The event group being updated.\n\t\t\t\t\t\t\tBIT_0 | BIT_4   // The bits being set.\n\t\t\t\t\t\t\t&xHigherPriorityTaskWoken );\n\n\t\t// Was the message posted successfully?\n\t\tif( xResult == pdPASS )\n\t\t{\n\t\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n\t\t\t// switch should be requested.  The macro used is port specific and\n\t\t\t// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -\n\t\t\t// refer to the documentation page for the port being used.\n\t\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n\t\t}\n  }\n   </pre>\n * \\defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR\n * \\ingroup EventGroup\n */\n#if( configUSE_TRACE_FACILITY == 1 )\n\tBaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#else\n\t#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )\n#endif\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupSync(\tEventGroupHandle_t xEventGroup,\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToSet,\n\t\t\t\t\t\t\t\t\tconst EventBits_t uxBitsToWaitFor,\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\n </pre>\n *\n * Atomically set bits within an event group, then wait for a combination of\n * bits to be set within the same event group.  This functionality is typically\n * used to synchronise multiple tasks, where each task has to wait for the other\n * tasks to reach a synchronisation point before proceeding.\n *\n * This function cannot be used from an interrupt.\n *\n * The function will return before its block time expires if the bits specified\n * by the uxBitsToWait parameter are set, or become set within that time.  In\n * this case all the bits specified by uxBitsToWait will be automatically\n * cleared before the function returns.\n *\n * @param xEventGroup The event group in which the bits are being tested.  The\n * event group must have previously been created using a call to\n * xEventGroupCreate().\n *\n * @param uxBitsToSet The bits to set in the event group before determining\n * if, and possibly waiting for, all the bits specified by the uxBitsToWait\n * parameter are set.\n *\n * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test\n * inside the event group.  For example, to wait for bit 0 and bit 2 set\n * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set\n * uxBitsToWaitFor to 0x07.  Etc.\n *\n * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait\n * for all of the bits specified by uxBitsToWaitFor to become set.\n *\n * @return The value of the event group at the time either the bits being waited\n * for became set, or the block time expired.  Test the return value to know\n * which bits were set.  If xEventGroupSync() returned because its timeout\n * expired then not all the bits being waited for will be set.  If\n * xEventGroupSync() returned because all the bits it was waiting for were\n * set then the returned value is the event group value before any bits were\n * automatically cleared.\n *\n * Example usage:\n <pre>\n // Bits used by the three tasks.\n #define TASK_0_BIT\t\t( 1 << 0 )\n #define TASK_1_BIT\t\t( 1 << 1 )\n #define TASK_2_BIT\t\t( 1 << 2 )\n\n #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )\n\n // Use an event group to synchronise three tasks.  It is assumed this event\n // group has already been created elsewhere.\n EventGroupHandle_t xEventBits;\n\n void vTask0( void *pvParameters )\n {\n EventBits_t uxReturn;\n TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;\n\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 0 in the event flag to note this task has reached the\n\t\t// sync point.  The other two tasks will set the other two bits defined\n\t\t// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation\n\t\t// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms\n\t\t// for this to happen.\n\t\tuxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );\n\n\t\tif( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )\n\t\t{\n\t\t\t// All three tasks reached the synchronisation point before the call\n\t\t\t// to xEventGroupSync() timed out.\n\t\t}\n\t}\n }\n\n void vTask1( void *pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 1 in the event flag to note this task has reached the\n\t\t// synchronisation point.  The other two tasks will set the other two\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n\t\t// indefinitely for this to happen.\n\t\txEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n\n\t\t// xEventGroupSync() was called with an indefinite block time, so\n\t\t// this task will only reach here if the syncrhonisation was made by all\n\t\t// three tasks, so there is no need to test the return value.\n\t }\n }\n\n void vTask2( void *pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t// Perform task functionality here.\n\n\t\t// Set bit 2 in the event flag to note this task has reached the\n\t\t// synchronisation point.  The other two tasks will set the other two\n\t\t// bits defined by ALL_SYNC_BITS.  All three tasks have reached the\n\t\t// synchronisation point when all the ALL_SYNC_BITS are set.  Wait\n\t\t// indefinitely for this to happen.\n\t\txEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );\n\n\t\t// xEventGroupSync() was called with an indefinite block time, so\n\t\t// this task will only reach here if the syncrhonisation was made by all\n\t\t// three tasks, so there is no need to test the return value.\n\t}\n }\n\n </pre>\n * \\defgroup xEventGroupSync xEventGroupSync\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * Returns the current value of the bits in an event group.  This function\n * cannot be used from an interrupt.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBits() was called.\n *\n * \\defgroup xEventGroupGetBits xEventGroupGetBits\n * \\ingroup EventGroup\n */\n#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )\n\n/**\n * event_groups.h\n *<pre>\n\tEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * A version of xEventGroupGetBits() that can be called from an ISR.\n *\n * @param xEventGroup The event group being queried.\n *\n * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.\n *\n * \\defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR\n * \\ingroup EventGroup\n */\nEventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/**\n * event_groups.h\n *<pre>\n\tvoid xEventGroupDelete( EventGroupHandle_t xEventGroup );\n </pre>\n *\n * Delete an event group that was previously created by a call to\n * xEventGroupCreate().  Tasks that are blocked on the event group will be\n * unblocked and obtain 0 as the event group's value.\n *\n * @param xEventGroup The event group being deleted.\n */\nvoid vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;\n\n/* For internal use only. */\nvoid vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;\nvoid vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;\n\n\n#if (configUSE_TRACE_FACILITY == 1)\n\tUBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;\n\tvoid vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* EVENT_GROUPS_H */\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/list.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * This is the list implementation used by the scheduler.  While it is tailored\n * heavily for the schedulers needs, it is also available for use by\n * application code.\n *\n * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a\n * numeric value (xItemValue).  Most of the time the lists are sorted in\n * descending item value order.\n *\n * Lists are created already containing one list item.  The value of this\n * item is the maximum possible that can be stored, it is therefore always at\n * the end of the list and acts as a marker.  The list member pxHead always\n * points to this marker - even though it is at the tail of the list.  This\n * is because the tail contains a wrap back pointer to the true head of\n * the list.\n *\n * In addition to it's value, each list item contains a pointer to the next\n * item in the list (pxNext), a pointer to the list it is in (pxContainer)\n * and a pointer to back to the object that contains it.  These later two\n * pointers are included for efficiency of list manipulation.  There is\n * effectively a two way link between the object containing the list item and\n * the list item itself.\n *\n *\n * \\page ListIntroduction List Implementation\n * \\ingroup FreeRTOSIntro\n */\n\n#ifndef INC_FREERTOS_H\n\t#error FreeRTOS.h must be included before list.h\n#endif\n\n#ifndef LIST_H\n#define LIST_H\n\n/*\n * The list structure members are modified from within interrupts, and therefore\n * by rights should be declared volatile.  However, they are only modified in a\n * functionally atomic way (within critical sections of with the scheduler\n * suspended) and are either passed by reference into a function or indexed via\n * a volatile variable.  Therefore, in all use cases tested so far, the volatile\n * qualifier can be omitted in order to provide a moderate performance\n * improvement without adversely affecting functional behaviour.  The assembly\n * instructions generated by the IAR, ARM and GCC compilers when the respective\n * compiler's options were set for maximum optimisation has been inspected and\n * deemed to be as intended.  That said, as compiler technology advances, and\n * especially if aggressive cross module optimisation is used (a use case that\n * has not been exercised to any great extend) then it is feasible that the\n * volatile qualifier will be needed for correct optimisation.  It is expected\n * that a compiler removing essential code because, without the volatile\n * qualifier on the list structure members and with aggressive cross module\n * optimisation, the compiler deemed the code unnecessary will result in\n * complete and obvious failure of the scheduler.  If this is ever experienced\n * then the volatile qualifier can be inserted in the relevant places within the\n * list structures by simply defining configLIST_VOLATILE to volatile in\n * FreeRTOSConfig.h (as per the example at the bottom of this comment block).\n * If configLIST_VOLATILE is not defined then the preprocessor directives below\n * will simply #define configLIST_VOLATILE away completely.\n *\n * To use volatile list structure members then add the following line to\n * FreeRTOSConfig.h (without the quotes):\n * \"#define configLIST_VOLATILE volatile\"\n */\n#ifndef configLIST_VOLATILE\n\t#define configLIST_VOLATILE\n#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Macros that can be used to place known values within the list structures,\nthen check that the known values do not get corrupted during the execution of\nthe application.   These may catch the list data structures being overwritten in\nmemory.  They will not catch data errors caused by incorrect configuration or\nuse of FreeRTOS.*/\n#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )\n\t/* Define the macros to do nothing. */\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\n\t#define listTEST_LIST_INTEGRITY( pxList )\n#else\n\t/* Define macros that add new members into the list structures. */\n\t#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue1;\n\t#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t\tTickType_t xListItemIntegrityValue2;\n\t#define listFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue1;\n\t#define listSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t\tTickType_t xListIntegrityValue2;\n\n\t/* Define macros that set the new structure members to known values. */\n\t#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t\t( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )\t( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )\t\t( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE\n\t#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )\t\t( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE\n\n\t/* Define macros that will assert if one of the structure members does not\n\tcontain its expected value. */\n\t#define listTEST_LIST_ITEM_INTEGRITY( pxItem )\t\tconfigASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n\t#define listTEST_LIST_INTEGRITY( pxList )\t\t\tconfigASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )\n#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */\n\n\n/*\n * Definition of the only type of object that a list can contain.\n */\nstruct xLIST;\nstruct xLIST_ITEM\n{\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tconfigLIST_VOLATILE TickType_t xItemValue;\t\t\t/*< The value being listed.  In most cases this is used to sort the list in descending order. */\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\t\t/*< Pointer to the next ListItem_t in the list. */\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\t/*< Pointer to the previous ListItem_t in the list. */\n\tvoid * pvOwner;\t\t\t\t\t\t\t\t\t\t/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */\n\tstruct xLIST * configLIST_VOLATILE pxContainer;\t\t/*< Pointer to the list in which this list item is placed (if any). */\n\tlistSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n};\ntypedef struct xLIST_ITEM ListItem_t;\t\t\t\t\t/* For some reason lint wants this as two separate definitions. */\n\nstruct xMINI_LIST_ITEM\n{\n\tlistFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tconfigLIST_VOLATILE TickType_t xItemValue;\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxNext;\n\tstruct xLIST_ITEM * configLIST_VOLATILE pxPrevious;\n};\ntypedef struct xMINI_LIST_ITEM MiniListItem_t;\n\n/*\n * Definition of the type of queue used by the scheduler.\n */\ntypedef struct xLIST\n{\n\tlistFIRST_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tvolatile UBaseType_t uxNumberOfItems;\n\tListItem_t * configLIST_VOLATILE pxIndex;\t\t\t/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */\n\tMiniListItem_t xListEnd;\t\t\t\t\t\t\t/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */\n\tlistSECOND_LIST_INTEGRITY_CHECK_VALUE\t\t\t\t/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n} List_t;\n\n/*\n * Access macro to set the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )\t\t( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )\n\n/*\n * Access macro to get the owner of a list item.  The owner of a list item\n * is the object (usually a TCB) that contains the list item.\n *\n * \\page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_OWNER( pxListItem )\t( ( pxListItem )->pvOwner )\n\n/*\n * Access macro to set the value of the list item.  In most cases the value is\n * used to sort the list in descending order.\n *\n * \\page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )\t( ( pxListItem )->xItemValue = ( xValue ) )\n\n/*\n * Access macro to retrieve the value of the list item.  The value can\n * represent anything - for example the priority of a task, or the time at\n * which a task should be unblocked.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_LIST_ITEM_VALUE( pxListItem )\t( ( pxListItem )->xItemValue )\n\n/*\n * Access macro to retrieve the value of the list item at the head of a given\n * list.\n *\n * \\page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE\n * \\ingroup LinkedList\n */\n#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext->xItemValue )\n\n/*\n * Return the list item at the head of the list.\n *\n * \\page listGET_HEAD_ENTRY listGET_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_HEAD_ENTRY( pxList )\t( ( ( pxList )->xListEnd ).pxNext )\n\n/*\n * Return the next list item.\n *\n * \\page listGET_NEXT listGET_NEXT\n * \\ingroup LinkedList\n */\n#define listGET_NEXT( pxListItem )\t( ( pxListItem )->pxNext )\n\n/*\n * Return the list item that marks the end of the list\n *\n * \\page listGET_END_MARKER listGET_END_MARKER\n * \\ingroup LinkedList\n */\n#define listGET_END_MARKER( pxList )\t( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )\n\n/*\n * Access macro to determine if a list contains any items.  The macro will\n * only have the value true if the list is empty.\n *\n * \\page listLIST_IS_EMPTY listLIST_IS_EMPTY\n * \\ingroup LinkedList\n */\n#define listLIST_IS_EMPTY( pxList )\t( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )\n\n/*\n * Access macro to return the number of items in the list.\n */\n#define listCURRENT_LIST_LENGTH( pxList )\t( ( pxList )->uxNumberOfItems )\n\n/*\n * Access function to obtain the owner of the next entry in a list.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list\n * and returns that entry's pxOwner parameter.  Using multiple calls to this\n * function it is therefore possible to move through every item contained in\n * a list.\n *\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxTCB pxTCB is set to the address of the owner of the next list item.\n * @param pxList The list from which the next item owner is to be returned.\n *\n * \\page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\nList_t * const pxConstList = ( pxList );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Increment the index to the next item and return the item, ensuring */\t\t\t\t\\\n\t/* we don't return the marker used at the end of the list.  */\t\t\t\t\t\t\t\\\n\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\t\\\n\tif( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n\n/*\n * Access function to obtain the owner of the first entry in a list.  Lists\n * are normally sorted in ascending item value order.\n *\n * This function returns the pxOwner member of the first item in the list.\n * The pxOwner parameter of a list item is a pointer to the object that owns\n * the list item.  In the scheduler this is normally a task control block.\n * The pxOwner parameter effectively creates a two way link between the list\n * item and its owner.\n *\n * @param pxList The list from which the owner of the head item is to be\n * returned.\n *\n * \\page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY\n * \\ingroup LinkedList\n */\n#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )\n\n/*\n * Check to see if a list item is within a list.  The list item maintains a\n * \"container\" pointer that points to the list it is in.  All this macro does\n * is check to see if the container and the list match.\n *\n * @param pxList The list we want to know if the list item is within.\n * @param pxListItem The list item we want to know if is in the list.\n * @return pdTRUE if the list item is in the list, otherwise pdFALSE.\n */\n#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )\n\n/*\n * Return the list a list item is contained within (referenced from).\n *\n * @param pxListItem The list item being queried.\n * @return A pointer to the List_t object that references the pxListItem\n */\n#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )\n\n/*\n * This provides a crude means of knowing if a list has been initialised, as\n * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()\n * function.\n */\n#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )\n\n/*\n * Must be called before a list is used!  This initialises all the members\n * of the list structure and inserts the xListEnd item into the list as a\n * marker to the back of the list.\n *\n * @param pxList Pointer to the list being initialised.\n *\n * \\page vListInitialise vListInitialise\n * \\ingroup LinkedList\n */\nvoid vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;\n\n/*\n * Must be called before a list item is used.  This sets the list container to\n * null so the item does not think that it is already contained in a list.\n *\n * @param pxItem Pointer to the list item being initialised.\n *\n * \\page vListInitialiseItem vListInitialiseItem\n * \\ingroup LinkedList\n */\nvoid vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted into the list in\n * a position determined by its item value (descending item value order).\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The item that is to be placed in the list.\n *\n * \\page vListInsert vListInsert\n * \\ingroup LinkedList\n */\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert a list item into a list.  The item will be inserted in a position\n * such that it will be the last item within the list returned by multiple\n * calls to listGET_OWNER_OF_NEXT_ENTRY.\n *\n * The list member pxIndex is used to walk through a list.  Calling\n * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.\n * Placing an item in a list using vListInsertEnd effectively places the item\n * in the list position pointed to by pxIndex.  This means that every other\n * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before\n * the pxIndex parameter again points to the item being inserted.\n *\n * @param pxList The list into which the item is to be inserted.\n *\n * @param pxNewListItem The list item to be inserted into the list.\n *\n * \\page vListInsertEnd vListInsertEnd\n * \\ingroup LinkedList\n */\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;\n\n/*\n * Remove an item from a list.  The list item has a pointer to the list that\n * it is in, so only the list item need be passed into the function.\n *\n * @param uxListRemove The item to be removed.  The item will remove itself from\n * the list pointed to by it's pxContainer parameter.\n *\n * @return The number of items that remain in the list after the list item has\n * been removed.\n *\n * \\page uxListRemove uxListRemove\n * \\ingroup LinkedList\n */\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/message_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n/*\n * Message buffers build functionality on top of FreeRTOS stream buffers.\n * Whereas stream buffers are used to send a continuous stream of data from one\n * task or interrupt to another, message buffers are used to send variable\n * length discrete messages from one task or interrupt to another.  Their\n * implementation is light weight, making them particularly suited for interrupt\n * to task and core to core communication scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * timeout to 0.\n *\n * Message buffers hold variable length messages.  To enable that, when a\n * message is written to the message buffer an additional sizeof( size_t ) bytes\n * are also written to store the message's length (that happens internally, with\n * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so writing a 10 byte message to a message buffer on a 32-bit\n * architecture will actually reduce the available space in the message buffer\n * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length\n * of the message).\n */\n\n#ifndef FREERTOS_MESSAGE_BUFFER_H\n#define FREERTOS_MESSAGE_BUFFER_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include message_buffer.h\"\n#endif\n\n/* Message buffers are built onto of stream buffers. */\n#include \"stream_buffer.h\"\n\n#if defined( __cplusplus )\nextern \"C\" {\n#endif\n\n/**\n * Type by which message buffers are referenced.  For example, a call to\n * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can\n * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),\n * etc.\n */\ntypedef void * MessageBufferHandle_t;\n\n/*-----------------------------------------------------------*/\n\n/**\n * message_buffer.h\n *\n<pre>\nMessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );\n</pre>\n *\n * Creates a new message buffer using dynamically allocated memory.  See\n * xMessageBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xMessageBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes (not messages) the message\n * buffer will be able to hold at any one time.  When a message is written to\n * the message buffer an additional sizeof( size_t ) bytes are also written to\n * store the message's length.  sizeof( size_t ) is typically 4 bytes on a\n * 32-bit architecture, so on most 32-bit architectures a 10 byte message will\n * take up 14 bytes of message buffer space.\n *\n * @return If NULL is returned, then the message buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the message buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the message buffer has been created successfully -\n * the returned value should be stored as the handle to the created message\n * buffer.\n *\n * Example use:\n<pre>\n\nvoid vAFunction( void )\n{\nMessageBufferHandle_t xMessageBuffer;\nconst size_t xMessageBufferSizeBytes = 100;\n\n    // Create a message buffer that can hold 100 bytes.  The memory used to hold\n    // both the message buffer structure and the messages themselves is allocated\n    // dynamically.  Each message added to the buffer consumes an additional 4\n    // bytes which are used to hold the lengh of the message.\n    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );\n\n    if( xMessageBuffer == NULL )\n    {\n        // There was not enough heap memory space available to create the\n        // message buffer.\n    }\n    else\n    {\n        // The message buffer was created successfully and can now be used.\n    }\n\n</pre>\n * \\defgroup xMessageBufferCreate xMessageBufferCreate\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )\n\n/**\n * message_buffer.h\n *\n<pre>\nMessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,\n                                                  uint8_t *pucMessageBufferStorageArea,\n                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );\n</pre>\n * Creates a new message buffer using statically allocated memory.  See\n * xMessageBufferCreate() for a version that uses dynamically allocated memory.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucMessageBufferStorageArea parameter.  When a message is written to the\n * message buffer an additional sizeof( size_t ) bytes are also written to store\n * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so on most 32-bit architecture a 10 byte message will take up\n * 14 bytes of message buffer space.  The maximum number of bytes that can be\n * stored in the message buffer is actually (xBufferSizeBytes - 1).\n *\n * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes + 1 big.  This is the array to which messages are\n * copied when they are written to the message buffer.\n *\n * @param pxStaticMessageBuffer Must point to a variable of type\n * StaticMessageBuffer_t, which will be used to hold the message buffer's data\n * structure.\n *\n * @return If the message buffer is created successfully then a handle to the\n * created message buffer is returned. If either pucMessageBufferStorageArea or\n * pxStaticmessageBuffer are NULL then NULL is returned.\n *\n * Example use:\n<pre>\n\n// Used to dimension the array used to hold the messages.  The available space\n// will actually be one less than this, so 999.\n#define STORAGE_SIZE_BYTES 1000\n\n// Defines the memory that will actually hold the messages within the message\n// buffer.\nstatic uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n\n// The variable used to hold the message buffer structure.\nStaticMessageBuffer_t xMessageBufferStruct;\n\nvoid MyFunction( void )\n{\nMessageBufferHandle_t xMessageBuffer;\n\n    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),\n                                                 ucBufferStorage,\n                                                 &xMessageBufferStruct );\n\n    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer\n    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to\n    // reference the created message buffer in other message buffer API calls.\n\n    // Other code that uses the message buffer can go here.\n}\n\n</pre>\n * \\defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,\n                           const void *pvTxData,\n                           size_t xDataLengthBytes,\n                           TickType_t xTicksToWait );\n<pre>\n *\n * Sends a discrete message to the message buffer.  The message can be any\n * length that fits within the buffer's free space, and is copied into the\n * buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param xTicksToWait The maximum amount of time the calling task should remain\n * in the Blocked state to wait for enough space to become available in the\n * message buffer, should the message buffer have insufficient space when\n * xMessageBufferSend() is called.  The calling task will never block if\n * xTicksToWait is zero.  The block time is specified in tick periods, so the\n * absolute time it represents is dependent on the tick frequency.  The macro\n * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into\n * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause\n * the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The number of bytes written to the message buffer.  If the call to\n * xMessageBufferSend() times out before there was enough space to write the\n * message into the message buffer then zero is returned.  If the call did not\n * time out then xDataLengthBytes is returned.\n *\n * Example use:\n<pre>\nvoid vAFunction( MessageBufferHandle_t xMessageBuffer )\n{\nsize_t xBytesSent;\nuint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\nchar *pcStringToSend = \"String to send\";\nconst TickType_t x100ms = pdMS_TO_TICKS( 100 );\n\n    // Send an array to the message buffer, blocking for a maximum of 100ms to\n    // wait for enough space to be available in the message buffer.\n    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n\n    if( xBytesSent != sizeof( ucArrayToSend ) )\n    {\n        // The call to xMessageBufferSend() times out before there was enough\n        // space in the buffer for the data to be written.\n    }\n\n    // Send the string to the message buffer.  Return immediately if there is\n    // not enough space in the buffer.\n    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The string could not be added to the message buffer because there was\n        // not enough free space in the buffer.\n    }\n}\n</pre>\n * \\defgroup xMessageBufferSend xMessageBufferSend\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,\n                                  const void *pvTxData,\n                                  size_t xDataLengthBytes,\n                                  BaseType_t *pxHigherPriorityTaskWoken );\n<pre>\n *\n * Interrupt safe version of the API function that sends a discrete message to\n * the message buffer.  The message can be any length that fits within the\n * buffer's free space, and is copied into the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferSend() to write to a message buffer from a task.  Use\n * xMessageBufferSendFromISR() to write to a message buffer from an interrupt\n * service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer to which a message is\n * being sent.\n *\n * @param pvTxData A pointer to the message that is to be copied into the\n * message buffer.\n *\n * @param xDataLengthBytes The length of the message.  That is, the number of\n * bytes to copy from pvTxData into the message buffer.  When a message is\n * written to the message buffer an additional sizeof( size_t ) bytes are also\n * written to store the message's length.  sizeof( size_t ) is typically 4 bytes\n * on a 32-bit architecture, so on most 32-bit architecture setting\n * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24\n * bytes (20 bytes of message data and 4 bytes to hold the message length).\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for data.  Calling\n * xMessageBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xMessageBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes actually written to the message buffer.  If the\n * message buffer didn't have enough free space for the message to be stored\n * then 0 is returned, otherwise xDataLengthBytes is returned.\n *\n * Example use:\n<pre>\n// A message buffer that has already been created.\nMessageBufferHandle_t xMessageBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nsize_t xBytesSent;\nchar *pcStringToSend = \"String to send\";\nBaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n\n    // Attempt to send the string to the message buffer.\n    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,\n                                            ( void * ) pcStringToSend,\n                                            strlen( pcStringToSend ),\n                                            &xHigherPriorityTaskWoken );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The string could not be added to the message buffer because there was\n        // not enough free space in the buffer.\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xMessageBufferSendFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,\n                              void *pvRxData,\n                              size_t xBufferLengthBytes,\n                              TickType_t xTicksToWait );\n</pre>\n *\n * Receives a discrete message from a message buffer.  Messages can be of\n * variable length and are copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for a message, should the message buffer be empty.\n * xMessageBufferReceive() will return immediately if xTicksToWait is zero and\n * the message buffer is empty.  The block time is specified in tick periods, so\n * the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any\n * CPU time when they are in the Blocked state.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.  If xMessageBufferReceive() times out before a message became available\n * then zero is returned.  If the length of the message is greater than\n * xBufferLengthBytes then the message will be left in the message buffer and\n * zero is returned.\n *\n * Example use:\n<pre>\nvoid vAFunction( MessageBuffer_t xMessageBuffer )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nconst TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n\n    // Receive the next message from the message buffer.  Wait in the Blocked\n    // state (so not using any CPU processing time) for a maximum of 100ms for\n    // a message to become available.\n    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,\n                                            ( void * ) ucRxData,\n                                            sizeof( ucRxData ),\n                                            xBlockTime );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains a message that is xReceivedBytes long.  Process\n        // the message here....\n    }\n}\n</pre>\n * \\defgroup xMessageBufferReceive xMessageBufferReceive\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )\n\n\n/**\n * message_buffer.h\n *\n<pre>\nsize_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,\n                                     void *pvRxData,\n                                     size_t xBufferLengthBytes,\n                                     BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * An interrupt safe version of the API function that receives a discrete\n * message from a message buffer.  Messages can be of variable length and are\n * copied out of the buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xMessageBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xMessageBufferRead()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xMessageBufferReceive() to read from a message buffer from a task.  Use\n * xMessageBufferReceiveFromISR() to read from a message buffer from an\n * interrupt service routine (ISR).\n *\n * @param xMessageBuffer The handle of the message buffer from which a message\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received message is\n * to be copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData\n * parameter.  This sets the maximum length of the message that can be received.\n * If xBufferLengthBytes is too small to hold the next message then the message\n * will be left in the message buffer and 0 will be returned.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xMessageBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The length, in bytes, of the message read from the message buffer, if\n * any.\n *\n * Example use:\n<pre>\n// A message buffer that has already been created.\nMessageBuffer_t xMessageBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n\n    // Receive the next message from the message buffer.\n    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,\n                                                  ( void * ) ucRxData,\n                                                  sizeof( ucRxData ),\n                                                  &xHigherPriorityTaskWoken );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains a message that is xReceivedBytes long.  Process\n        // the message here....\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xMessageBufferReceiveFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    portYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nvoid vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );\n</pre>\n *\n * Deletes a message buffer that was previously created using a call to\n * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message\n * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),\n * then the allocated memory is freed.\n *\n * A message buffer handle must not be used after the message buffer has been\n * deleted.\n *\n * @param xMessageBuffer The handle of the message buffer to be deleted.\n *\n */\n#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n *\n * Tests to see if a message buffer is full.  A message buffer is full if it\n * cannot accept any more messages, of any size, until space is made available\n * by a message being removed from the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is full then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n */\n#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n *\n * Tests to see if a message buffer is empty (does not contain any messages).\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return If the message buffer referenced by xMessageBuffer is empty then\n * pdTRUE is returned.  Otherwise pdFALSE is returned.\n *\n */\n#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )\n\n/**\n * message_buffer.h\n<pre>\nBaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );\n</pre>\n *\n * Resets a message buffer to its initial empty state, discarding any message it\n * contained.\n *\n * A message buffer can only be reset if there are no tasks blocked on it.\n *\n * @param xMessageBuffer The handle of the message buffer being reset.\n *\n * @return If the message buffer was reset then pdPASS is returned.  If the\n * message buffer could not be reset because either there was a task blocked on\n * the message queue to wait for space to become available, or to wait for a\n * a message to be available, then pdFAIL is returned.\n *\n * \\defgroup xMessageBufferReset xMessageBufferReset\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )\n\n\n/**\n * message_buffer.h\n<pre>\nsize_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );\n</pre>\n * Returns the number of bytes of free space in the message buffer.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The number of bytes that can be written to the message buffer before\n * the message buffer would be full.  When a message is written to the message\n * buffer an additional sizeof( size_t ) bytes are also written to store the\n * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit\n * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size\n * of the largest message that can be written to the message buffer is 6 bytes.\n *\n * \\defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )\n#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */\n\n/**\n * message_buffer.h\n <pre>\n size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );\n </pre>\n * Returns the length (in bytes) of the next message in a message buffer.\n * Useful if xMessageBufferReceive() returned 0 because the size of the buffer\n * passed into xMessageBufferReceive() was too small to hold the next message.\n *\n * @param xMessageBuffer The handle of the message buffer being queried.\n *\n * @return The length (in bytes) of the next message in the message buffer, or 0\n * if the message buffer is empty.\n *\n * \\defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes\n * \\ingroup MessageBufferManagement\n */\n#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * message_buffer.h\n *\n<pre>\nBaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferSendCompletedFromISR().  If calling\n * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )\n\n/**\n * message_buffer.h\n *\n<pre>\nBaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xMessageBufferReceiveCompletedFromISR().  If calling\n * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\n#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )\n\n#if defined( __cplusplus )\n} /* extern \"C\" */\n#endif\n\n#endif\t/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_prototypes.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * When the MPU is used the standard (non MPU) API functions are mapped to\n * equivalents that start \"MPU_\", the prototypes for which are defined in this\n * header files.  This will cause the application code to call the MPU_ version\n * which wraps the non-MPU version with privilege promoting then demoting code,\n * so the kernel code always runs will full privileges.\n */\n\n\n#ifndef MPU_PROTOTYPES_H\n#define MPU_PROTOTYPES_H\n\n/* MPU versions of tasks.h API functions. */\nBaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\neTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;\nchar * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nconfigSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;\nTaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;\nuint32_t MPU_ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of queue.h API functions. */\nBaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;\nQueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;\nQueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\nuint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of timers.h API functions. */\nTimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;\nTimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;\nvoid * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nconst char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nTickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of event_group.h API functions. */\nEventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;\nEventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;\nEventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;\nUBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;\n\n/* MPU versions of message/stream_buffer.h API functions. */\nsize_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nvoid MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nsize_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;\nBaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;\nStreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;\n\n\n\n#endif /* MPU_PROTOTYPES_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/mpu_wrappers.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef MPU_WRAPPERS_H\n#define MPU_WRAPPERS_H\n\n/* This file redefines API functions to be called through a wrapper macro, but\nonly for ports that are using the MPU. */\n#ifdef portUSING_MPU_WRAPPERS\n\n\t/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is\n\tincluded from queue.c or task.c to prevent it from having an effect within\n\tthose files. */\n\t#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n\t\t/*\n\t\t * Map standard (non MPU) API functions to equivalents that start\n\t\t * \"MPU_\".  This will cause the application code to call the MPU_\n\t\t * version, which wraps the non-MPU version with privilege promoting\n\t\t * then demoting code, so the kernel code always runs will full\n\t\t * privileges.\n\t\t */\n\n\t\t/* Map standard tasks.h API functions to the MPU equivalents. */\n\t\t#define xTaskCreate\t\t\t\t\t\t\t\tMPU_xTaskCreate\n\t\t#define xTaskCreateStatic\t\t\t\t\t\tMPU_xTaskCreateStatic\n\t\t#define xTaskCreateRestricted\t\t\t\t\tMPU_xTaskCreateRestricted\n\t\t#define vTaskAllocateMPURegions\t\t\t\t\tMPU_vTaskAllocateMPURegions\n\t\t#define vTaskDelete\t\t\t\t\t\t\t\tMPU_vTaskDelete\n\t\t#define vTaskDelay\t\t\t\t\t\t\t\tMPU_vTaskDelay\n\t\t#define vTaskDelayUntil\t\t\t\t\t\t\tMPU_vTaskDelayUntil\n\t\t#define xTaskAbortDelay\t\t\t\t\t\t\tMPU_xTaskAbortDelay\n\t\t#define uxTaskPriorityGet\t\t\t\t\t\tMPU_uxTaskPriorityGet\n\t\t#define eTaskGetState\t\t\t\t\t\t\tMPU_eTaskGetState\n\t\t#define vTaskGetInfo\t\t\t\t\t\t\tMPU_vTaskGetInfo\n\t\t#define vTaskPrioritySet\t\t\t\t\t\tMPU_vTaskPrioritySet\n\t\t#define vTaskSuspend\t\t\t\t\t\t\tMPU_vTaskSuspend\n\t\t#define vTaskResume\t\t\t\t\t\t\t\tMPU_vTaskResume\n\t\t#define vTaskSuspendAll\t\t\t\t\t\t\tMPU_vTaskSuspendAll\n\t\t#define xTaskResumeAll\t\t\t\t\t\t\tMPU_xTaskResumeAll\n\t\t#define xTaskGetTickCount\t\t\t\t\t\tMPU_xTaskGetTickCount\n\t\t#define uxTaskGetNumberOfTasks\t\t\t\t\tMPU_uxTaskGetNumberOfTasks\n\t\t#define pcTaskGetName\t\t\t\t\t\t\tMPU_pcTaskGetName\n\t\t#define xTaskGetHandle\t\t\t\t\t\t\tMPU_xTaskGetHandle\n\t\t#define uxTaskGetStackHighWaterMark\t\t\t\tMPU_uxTaskGetStackHighWaterMark\n\t\t#define uxTaskGetStackHighWaterMark2\t\t\tMPU_uxTaskGetStackHighWaterMark2\n\t\t#define vTaskSetApplicationTaskTag\t\t\t\tMPU_vTaskSetApplicationTaskTag\n\t\t#define xTaskGetApplicationTaskTag\t\t\t\tMPU_xTaskGetApplicationTaskTag\n\t\t#define vTaskSetThreadLocalStoragePointer\t\tMPU_vTaskSetThreadLocalStoragePointer\n\t\t#define pvTaskGetThreadLocalStoragePointer\t\tMPU_pvTaskGetThreadLocalStoragePointer\n\t\t#define xTaskCallApplicationTaskHook\t\t\tMPU_xTaskCallApplicationTaskHook\n\t\t#define xTaskGetIdleTaskHandle\t\t\t\t\tMPU_xTaskGetIdleTaskHandle\n\t\t#define uxTaskGetSystemState\t\t\t\t\tMPU_uxTaskGetSystemState\n\t\t#define vTaskList\t\t\t\t\t\t\t\tMPU_vTaskList\n\t\t#define vTaskGetRunTimeStats\t\t\t\t\tMPU_vTaskGetRunTimeStats\n\t\t#define ulTaskGetIdleRunTimeCounter\t\t\t\tMPU_ulTaskGetIdleRunTimeCounter\n\t\t#define xTaskGenericNotify\t\t\t\t\t\tMPU_xTaskGenericNotify\n\t\t#define xTaskNotifyWait\t\t\t\t\t\t\tMPU_xTaskNotifyWait\n\t\t#define ulTaskNotifyTake\t\t\t\t\t\tMPU_ulTaskNotifyTake\n\t\t#define xTaskNotifyStateClear\t\t\t\t\tMPU_xTaskNotifyStateClear\n\t\t#define ulTaskNotifyValueClear\t\t\t\t\tMPU_ulTaskNotifyValueClear\n\t\t#define xTaskCatchUpTicks\t\t\t\t\t\tMPU_xTaskCatchUpTicks\n\n\t\t#define xTaskGetCurrentTaskHandle\t\t\t\tMPU_xTaskGetCurrentTaskHandle\n\t\t#define vTaskSetTimeOutState\t\t\t\t\tMPU_vTaskSetTimeOutState\n\t\t#define xTaskCheckForTimeOut\t\t\t\t\tMPU_xTaskCheckForTimeOut\n\t\t#define xTaskGetSchedulerState\t\t\t\t\tMPU_xTaskGetSchedulerState\n\n\t\t/* Map standard queue.h API functions to the MPU equivalents. */\n\t\t#define xQueueGenericSend\t\t\t\t\t\tMPU_xQueueGenericSend\n\t\t#define xQueueReceive\t\t\t\t\t\t\tMPU_xQueueReceive\n\t\t#define xQueuePeek\t\t\t\t\t\t\t\tMPU_xQueuePeek\n\t\t#define xQueueSemaphoreTake\t\t\t\t\t\tMPU_xQueueSemaphoreTake\n\t\t#define uxQueueMessagesWaiting\t\t\t\t\tMPU_uxQueueMessagesWaiting\n\t\t#define uxQueueSpacesAvailable\t\t\t\t\tMPU_uxQueueSpacesAvailable\n\t\t#define vQueueDelete\t\t\t\t\t\t\tMPU_vQueueDelete\n\t\t#define xQueueCreateMutex\t\t\t\t\t\tMPU_xQueueCreateMutex\n\t\t#define xQueueCreateMutexStatic\t\t\t\t\tMPU_xQueueCreateMutexStatic\n\t\t#define xQueueCreateCountingSemaphore\t\t\tMPU_xQueueCreateCountingSemaphore\n\t\t#define xQueueCreateCountingSemaphoreStatic\t\tMPU_xQueueCreateCountingSemaphoreStatic\n\t\t#define xQueueGetMutexHolder\t\t\t\t\tMPU_xQueueGetMutexHolder\n\t\t#define xQueueTakeMutexRecursive\t\t\t\tMPU_xQueueTakeMutexRecursive\n\t\t#define xQueueGiveMutexRecursive\t\t\t\tMPU_xQueueGiveMutexRecursive\n\t\t#define xQueueGenericCreate\t\t\t\t\t\tMPU_xQueueGenericCreate\n\t\t#define xQueueGenericCreateStatic\t\t\t\tMPU_xQueueGenericCreateStatic\n\t\t#define xQueueCreateSet\t\t\t\t\t\t\tMPU_xQueueCreateSet\n\t\t#define xQueueAddToSet\t\t\t\t\t\t\tMPU_xQueueAddToSet\n\t\t#define xQueueRemoveFromSet\t\t\t\t\t\tMPU_xQueueRemoveFromSet\n\t\t#define xQueueSelectFromSet\t\t\t\t\t\tMPU_xQueueSelectFromSet\n\t\t#define xQueueGenericReset\t\t\t\t\t\tMPU_xQueueGenericReset\n\n\t\t#if( configQUEUE_REGISTRY_SIZE > 0 )\n\t\t\t#define vQueueAddToRegistry\t\t\t\t\t\tMPU_vQueueAddToRegistry\n\t\t\t#define vQueueUnregisterQueue\t\t\t\t\tMPU_vQueueUnregisterQueue\n\t\t\t#define pcQueueGetName\t\t\t\t\t\t\tMPU_pcQueueGetName\n\t\t#endif\n\n\t\t/* Map standard timer.h API functions to the MPU equivalents. */\n\t\t#define xTimerCreate\t\t\t\t\t\t\tMPU_xTimerCreate\n\t\t#define xTimerCreateStatic\t\t\t\t\t\tMPU_xTimerCreateStatic\n\t\t#define pvTimerGetTimerID\t\t\t\t\t\tMPU_pvTimerGetTimerID\n\t\t#define vTimerSetTimerID\t\t\t\t\t\tMPU_vTimerSetTimerID\n\t\t#define xTimerIsTimerActive\t\t\t\t\t\tMPU_xTimerIsTimerActive\n\t\t#define xTimerGetTimerDaemonTaskHandle\t\t\tMPU_xTimerGetTimerDaemonTaskHandle\n\t\t#define xTimerPendFunctionCall\t\t\t\t\tMPU_xTimerPendFunctionCall\n\t\t#define pcTimerGetName\t\t\t\t\t\t\tMPU_pcTimerGetName\n\t\t#define vTimerSetReloadMode\t\t\t\t\t\tMPU_vTimerSetReloadMode\n\t\t#define uxTimerGetReloadMode\t\t\t\t\tMPU_uxTimerGetReloadMode\n\t\t#define xTimerGetPeriod\t\t\t\t\t\t\tMPU_xTimerGetPeriod\n\t\t#define xTimerGetExpiryTime\t\t\t\t\t\tMPU_xTimerGetExpiryTime\n\t\t#define xTimerGenericCommand\t\t\t\t\tMPU_xTimerGenericCommand\n\n\t\t/* Map standard event_group.h API functions to the MPU equivalents. */\n\t\t#define xEventGroupCreate\t\t\t\t\t\tMPU_xEventGroupCreate\n\t\t#define xEventGroupCreateStatic\t\t\t\t\tMPU_xEventGroupCreateStatic\n\t\t#define xEventGroupWaitBits\t\t\t\t\t\tMPU_xEventGroupWaitBits\n\t\t#define xEventGroupClearBits\t\t\t\t\tMPU_xEventGroupClearBits\n\t\t#define xEventGroupSetBits\t\t\t\t\t\tMPU_xEventGroupSetBits\n\t\t#define xEventGroupSync\t\t\t\t\t\t\tMPU_xEventGroupSync\n\t\t#define vEventGroupDelete\t\t\t\t\t\tMPU_vEventGroupDelete\n\n\t\t/* Map standard message/stream_buffer.h API functions to the MPU\n\t\tequivalents. */\n\t\t#define xStreamBufferSend\t\t\t\t\t\tMPU_xStreamBufferSend\n\t\t#define xStreamBufferReceive\t\t\t\t\tMPU_xStreamBufferReceive\n\t\t#define xStreamBufferNextMessageLengthBytes\t\tMPU_xStreamBufferNextMessageLengthBytes\n\t\t#define vStreamBufferDelete\t\t\t\t\t\tMPU_vStreamBufferDelete\n\t\t#define xStreamBufferIsFull\t\t\t\t\t\tMPU_xStreamBufferIsFull\n\t\t#define xStreamBufferIsEmpty\t\t\t\t\tMPU_xStreamBufferIsEmpty\n\t\t#define xStreamBufferReset\t\t\t\t\t\tMPU_xStreamBufferReset\n\t\t#define xStreamBufferSpacesAvailable\t\t\tMPU_xStreamBufferSpacesAvailable\n\t\t#define xStreamBufferBytesAvailable\t\t\t\tMPU_xStreamBufferBytesAvailable\n\t\t#define xStreamBufferSetTriggerLevel\t\t\tMPU_xStreamBufferSetTriggerLevel\n\t\t#define xStreamBufferGenericCreate\t\t\t\tMPU_xStreamBufferGenericCreate\n\t\t#define xStreamBufferGenericCreateStatic\t\tMPU_xStreamBufferGenericCreateStatic\n\n\n\t\t/* Remove the privileged function macro, but keep the PRIVILEGED_DATA\n\t\tmacro so applications can place data in privileged access sections\n\t\t(useful when using statically allocated objects). */\n\t\t#define PRIVILEGED_FUNCTION\n\t\t#define PRIVILEGED_DATA __attribute__((section(\"privileged_data\")))\n\t\t#define FREERTOS_SYSTEM_CALL\n\n\t#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n\t\t/* Ensure API functions go in the privileged execution section. */\n\t\t#define PRIVILEGED_FUNCTION __attribute__((section(\"privileged_functions\")))\n\t\t#define PRIVILEGED_DATA __attribute__((section(\"privileged_data\")))\n\t\t#define FREERTOS_SYSTEM_CALL __attribute__((section( \"freertos_system_calls\")))\n\n\t#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */\n\n#else /* portUSING_MPU_WRAPPERS */\n\n\t#define PRIVILEGED_FUNCTION\n\t#define PRIVILEGED_DATA\n\t#define FREERTOS_SYSTEM_CALL\n\t#define portUSING_MPU_WRAPPERS 0\n\n#endif /* portUSING_MPU_WRAPPERS */\n\n\n#endif /* MPU_WRAPPERS_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/portable.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*-----------------------------------------------------------\n * Portable layer API.  Each function must be defined for each port.\n *----------------------------------------------------------*/\n\n#ifndef PORTABLE_H\n#define PORTABLE_H\n\n/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a\npre-processor definition was used to ensure the pre-processor found the correct\nportmacro.h file for the port being used.  That scheme was deprecated in favour\nof setting the compiler's include path such that it found the correct\nportmacro.h file - removing the need for the constant and allowing the\nportmacro.h file to be located anywhere in relation to the port being used.\nPurely for reasons of backward compatibility the old method is still valid, but\nto make it clear that new projects should not use it, support for the port\nspecific constants has been moved into the deprecated_definitions.h header\nfile. */\n#include \"deprecated_definitions.h\"\n\n/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h\ndid not result in a portmacro.h header file being included - and it should be\nincluded here.  In this case the path to the correct portmacro.h header file\nmust be set in the compiler's include path. */\n#ifndef portENTER_CRITICAL\n\t#include \"portmacro.h\"\n#endif\n\n#if portBYTE_ALIGNMENT == 32\n\t#define portBYTE_ALIGNMENT_MASK ( 0x001f )\n#endif\n\n#if portBYTE_ALIGNMENT == 16\n\t#define portBYTE_ALIGNMENT_MASK ( 0x000f )\n#endif\n\n#if portBYTE_ALIGNMENT == 8\n\t#define portBYTE_ALIGNMENT_MASK ( 0x0007 )\n#endif\n\n#if portBYTE_ALIGNMENT == 4\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0003 )\n#endif\n\n#if portBYTE_ALIGNMENT == 2\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0001 )\n#endif\n\n#if portBYTE_ALIGNMENT == 1\n\t#define portBYTE_ALIGNMENT_MASK\t( 0x0000 )\n#endif\n\n#ifndef portBYTE_ALIGNMENT_MASK\n\t#error \"Invalid portBYTE_ALIGNMENT definition\"\n#endif\n\n#ifndef portNUM_CONFIGURABLE_REGIONS\n\t#define portNUM_CONFIGURABLE_REGIONS 1\n#endif\n\n#ifndef portHAS_STACK_OVERFLOW_CHECKING\n\t#define portHAS_STACK_OVERFLOW_CHECKING 0\n#endif\n\n#ifndef portARCH_NAME\n\t#define portARCH_NAME NULL\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"mpu_wrappers.h\"\n\n/*\n * Setup the stack of a new task so it is ready to be placed under the\n * scheduler control.  The registers have to be placed on the stack in\n * the order that the port expects to find them.\n *\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n\t#else\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;\n\t#endif\n#else\n\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\n\t#else\n\t\tStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;\n\t#endif\n#endif\n\n/* Used by heap_5.c to define the start address and size of each memory region\nthat together comprise the total FreeRTOS heap space. */\ntypedef struct HeapRegion\n{\n\tuint8_t *pucStartAddress;\n\tsize_t xSizeInBytes;\n} HeapRegion_t;\n\n/* Used to pass information about the heap out of vPortGetHeapStats(). */\ntypedef struct xHeapStats\n{\n\tsize_t xAvailableHeapSpaceInBytes;\t\t/* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */\n\tsize_t xSizeOfLargestFreeBlockInBytes; \t/* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */\n\tsize_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */\n\tsize_t xNumberOfFreeBlocks;\t\t\t\t/* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */\n\tsize_t xMinimumEverFreeBytesRemaining;\t/* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */\n\tsize_t xNumberOfSuccessfulAllocations;\t/* The number of calls to pvPortMalloc() that have returned a valid memory block. */\n\tsize_t xNumberOfSuccessfulFrees;\t\t/* The number of calls to vPortFree() that has successfully freed a block of memory. */\n} HeapStats_t;\n\n/*\n * Used to define multiple heap regions for use by heap_5.c.  This function\n * must be called before any calls to pvPortMalloc() - not creating a task,\n * queue, semaphore, mutex, software timer, event group, etc. will result in\n * pvPortMalloc being called.\n *\n * pxHeapRegions passes in an array of HeapRegion_t structures - each of which\n * defines a region of memory that can be used as the heap.  The array is\n * terminated by a HeapRegions_t structure that has a size of 0.  The region\n * with the lowest start address must appear first in the array.\n */\nvoid vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;\n\n/*\n * Returns a HeapStats_t structure filled with information about the current\n * heap state.\n */\nvoid vPortGetHeapStats( HeapStats_t *pxHeapStats );\n\n/*\n * Map to the memory management routines required for the port.\n */\nvoid *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;\nvoid vPortFree( void *pv ) PRIVILEGED_FUNCTION;\nvoid vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;\nsize_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Setup the hardware ready for the scheduler to take control.  This generally\n * sets up a tick interrupt and sets timers for the correct tick frequency.\n */\nBaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so\n * the hardware is left in its original condition after the scheduler stops\n * executing.\n */\nvoid vPortEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The structures and methods of manipulating the MPU are contained within the\n * port layer.\n *\n * Fills the xMPUSettings structure with the memory region information\n * contained in xRegions.\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\tstruct xMEMORY_REGION;\n\tvoid vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTABLE_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/projdefs.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef PROJDEFS_H\n#define PROJDEFS_H\n\n/*\n * Defines the prototype to which task functions must conform.  Defined in this\n * file to ensure the type is known before portable.h is included.\n */\ntypedef void (*TaskFunction_t)( void * );\n\n/* Converts a time in milliseconds to a time in ticks.  This macro can be\noverridden by a macro of the same name defined in FreeRTOSConfig.h in case the\ndefinition here is not suitable for your application. */\n#ifndef pdMS_TO_TICKS\n\t#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )\n#endif\n\n#define pdFALSE\t\t\t( ( BaseType_t ) 0 )\n#define pdTRUE\t\t\t( ( BaseType_t ) 1 )\n\n#define pdPASS\t\t\t( pdTRUE )\n#define pdFAIL\t\t\t( pdFALSE )\n#define errQUEUE_EMPTY\t( ( BaseType_t ) 0 )\n#define errQUEUE_FULL\t( ( BaseType_t ) 0 )\n\n/* FreeRTOS error definitions. */\n#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY\t( -1 )\n#define errQUEUE_BLOCKED\t\t\t\t\t\t( -4 )\n#define errQUEUE_YIELD\t\t\t\t\t\t\t( -5 )\n\n/* Macros used for basic data corruption checks. */\n#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES\n\t#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0\n#endif\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a\n#else\n\t#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL\n#endif\n\n/* The following errno values are used by FreeRTOS+ components, not FreeRTOS\nitself. */\n#define pdFREERTOS_ERRNO_NONE\t\t\t0\t/* No errors */\n#define\tpdFREERTOS_ERRNO_ENOENT\t\t\t2\t/* No such file or directory */\n#define\tpdFREERTOS_ERRNO_EINTR\t\t\t4\t/* Interrupted system call */\n#define\tpdFREERTOS_ERRNO_EIO\t\t\t5\t/* I/O error */\n#define\tpdFREERTOS_ERRNO_ENXIO\t\t\t6\t/* No such device or address */\n#define\tpdFREERTOS_ERRNO_EBADF\t\t\t9\t/* Bad file number */\n#define\tpdFREERTOS_ERRNO_EAGAIN\t\t\t11\t/* No more processes */\n#define\tpdFREERTOS_ERRNO_EWOULDBLOCK\t11\t/* Operation would block */\n#define\tpdFREERTOS_ERRNO_ENOMEM\t\t\t12\t/* Not enough memory */\n#define\tpdFREERTOS_ERRNO_EACCES\t\t\t13\t/* Permission denied */\n#define\tpdFREERTOS_ERRNO_EFAULT\t\t\t14\t/* Bad address */\n#define\tpdFREERTOS_ERRNO_EBUSY\t\t\t16\t/* Mount device busy */\n#define\tpdFREERTOS_ERRNO_EEXIST\t\t\t17\t/* File exists */\n#define\tpdFREERTOS_ERRNO_EXDEV\t\t\t18\t/* Cross-device link */\n#define\tpdFREERTOS_ERRNO_ENODEV\t\t\t19\t/* No such device */\n#define\tpdFREERTOS_ERRNO_ENOTDIR\t\t20\t/* Not a directory */\n#define\tpdFREERTOS_ERRNO_EISDIR\t\t\t21\t/* Is a directory */\n#define\tpdFREERTOS_ERRNO_EINVAL\t\t\t22\t/* Invalid argument */\n#define\tpdFREERTOS_ERRNO_ENOSPC\t\t\t28\t/* No space left on device */\n#define\tpdFREERTOS_ERRNO_ESPIPE\t\t\t29\t/* Illegal seek */\n#define\tpdFREERTOS_ERRNO_EROFS\t\t\t30\t/* Read only file system */\n#define\tpdFREERTOS_ERRNO_EUNATCH\t\t42\t/* Protocol driver not attached */\n#define\tpdFREERTOS_ERRNO_EBADE\t\t\t50\t/* Invalid exchange */\n#define\tpdFREERTOS_ERRNO_EFTYPE\t\t\t79\t/* Inappropriate file type or format */\n#define\tpdFREERTOS_ERRNO_ENMFILE\t\t89\t/* No more files */\n#define\tpdFREERTOS_ERRNO_ENOTEMPTY\t\t90\t/* Directory not empty */\n#define\tpdFREERTOS_ERRNO_ENAMETOOLONG \t91\t/* File or path name too long */\n#define\tpdFREERTOS_ERRNO_EOPNOTSUPP\t\t95\t/* Operation not supported on transport endpoint */\n#define\tpdFREERTOS_ERRNO_ENOBUFS\t\t105\t/* No buffer space available */\n#define\tpdFREERTOS_ERRNO_ENOPROTOOPT\t109\t/* Protocol not available */\n#define\tpdFREERTOS_ERRNO_EADDRINUSE\t\t112\t/* Address already in use */\n#define\tpdFREERTOS_ERRNO_ETIMEDOUT\t\t116\t/* Connection timed out */\n#define\tpdFREERTOS_ERRNO_EINPROGRESS\t119\t/* Connection already in progress */\n#define\tpdFREERTOS_ERRNO_EALREADY\t\t120\t/* Socket already connected */\n#define\tpdFREERTOS_ERRNO_EADDRNOTAVAIL \t125\t/* Address not available */\n#define\tpdFREERTOS_ERRNO_EISCONN\t\t127\t/* Socket is already connected */\n#define\tpdFREERTOS_ERRNO_ENOTCONN\t\t128\t/* Socket is not connected */\n#define\tpdFREERTOS_ERRNO_ENOMEDIUM\t\t135\t/* No medium inserted */\n#define\tpdFREERTOS_ERRNO_EILSEQ\t\t\t138\t/* An invalid UTF-16 sequence was encountered. */\n#define\tpdFREERTOS_ERRNO_ECANCELED\t\t140\t/* Operation canceled. */\n\n/* The following endian values are used by FreeRTOS+ components, not FreeRTOS\nitself. */\n#define pdFREERTOS_LITTLE_ENDIAN\t\t0\n#define pdFREERTOS_BIG_ENDIAN\t\t\t1\n\n/* Re-defining endian values for generic naming. */\n#define pdLITTLE_ENDIAN\t\t\t\t\tpdFREERTOS_LITTLE_ENDIAN\n#define pdBIG_ENDIAN\t\t\t\t\tpdFREERTOS_BIG_ENDIAN\n\n\n#endif /* PROJDEFS_H */\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/queue.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef QUEUE_H\n#define QUEUE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include queue.h\"\n#endif\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"task.h\"\n\n/**\n * Type by which queues are referenced.  For example, a call to xQueueCreate()\n * returns an QueueHandle_t variable that can then be used as a parameter to\n * xQueueSend(), xQueueReceive(), etc.\n */\nstruct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */\ntypedef struct QueueDefinition * QueueHandle_t;\n\n/**\n * Type by which queue sets are referenced.  For example, a call to\n * xQueueCreateSet() returns an xQueueSet variable that can then be used as a\n * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.\n */\ntypedef struct QueueDefinition * QueueSetHandle_t;\n\n/**\n * Queue sets can contain both queues and semaphores, so the\n * QueueSetMemberHandle_t is defined as a type to be used where a parameter or\n * return value can be either an QueueHandle_t or an SemaphoreHandle_t.\n */\ntypedef struct QueueDefinition * QueueSetMemberHandle_t;\n\n/* For internal use only. */\n#define\tqueueSEND_TO_BACK\t\t( ( BaseType_t ) 0 )\n#define\tqueueSEND_TO_FRONT\t\t( ( BaseType_t ) 1 )\n#define queueOVERWRITE\t\t\t( ( BaseType_t ) 2 )\n\n/* For internal use only.  These definitions *must* match those in queue.c. */\n#define queueQUEUE_TYPE_BASE\t\t\t\t( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_SET\t\t\t\t\t( ( uint8_t ) 0U )\n#define queueQUEUE_TYPE_MUTEX \t\t\t\t( ( uint8_t ) 1U )\n#define queueQUEUE_TYPE_COUNTING_SEMAPHORE\t( ( uint8_t ) 2U )\n#define queueQUEUE_TYPE_BINARY_SEMAPHORE\t( ( uint8_t ) 3U )\n#define queueQUEUE_TYPE_RECURSIVE_MUTEX\t\t( ( uint8_t ) 4U )\n\n/**\n * queue. h\n * <pre>\n QueueHandle_t xQueueCreate(\n\t\t\t\t\t\t\t  UBaseType_t uxQueueLength,\n\t\t\t\t\t\t\t  UBaseType_t uxItemSize\n\t\t\t\t\t\t  );\n * </pre>\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @return If the queue is successfully create then a handle to the newly\n * created queue is returned.  If the queue cannot be created then 0 is\n * returned.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n };\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\tif( xQueue1 == 0 )\n\t{\n\t\t// Queue was not created and must not be used.\n\t}\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue2 == 0 )\n\t{\n\t\t// Queue was not created and must not be used.\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueCreate xQueueCreate\n * \\ingroup QueueManagement\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )\n#endif\n\n/**\n * queue. h\n * <pre>\n QueueHandle_t xQueueCreateStatic(\n\t\t\t\t\t\t\t  UBaseType_t uxQueueLength,\n\t\t\t\t\t\t\t  UBaseType_t uxItemSize,\n\t\t\t\t\t\t\t  uint8_t *pucQueueStorageBuffer,\n\t\t\t\t\t\t\t  StaticQueue_t *pxQueueBuffer\n\t\t\t\t\t\t  );\n * </pre>\n *\n * Creates a new queue instance, and returns a handle by which the new queue\n * can be referenced.\n *\n * Internally, within the FreeRTOS implementation, queues use two blocks of\n * memory.  The first block is used to hold the queue's data structures.  The\n * second block is used to hold items placed into the queue.  If a queue is\n * created using xQueueCreate() then both blocks of memory are automatically\n * dynamically allocated inside the xQueueCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a queue is created using\n * xQueueCreateStatic() then the application writer must provide the memory that\n * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to\n * be created without using any dynamic memory allocation.\n *\n * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html\n *\n * @param uxQueueLength The maximum number of items that the queue can contain.\n *\n * @param uxItemSize The number of bytes each item in the queue will require.\n * Items are queued by copy, not by reference, so this is the number of bytes\n * that will be copied for each posted item.  Each item on the queue must be\n * the same size.\n *\n * @param pucQueueStorageBuffer If uxItemSize is not zero then\n * pucQueueStorageBuffer must point to a uint8_t array that is at least large\n * enough to hold the maximum number of items that can be in the queue at any\n * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is\n * zero then pucQueueStorageBuffer can be NULL.\n *\n * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which\n * will be used to hold the queue's data structure.\n *\n * @return If the queue is created then a handle to the created queue is\n * returned.  If pxQueueBuffer is NULL then NULL is returned.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n };\n\n #define QUEUE_LENGTH 10\n #define ITEM_SIZE sizeof( uint32_t )\n\n // xQueueBuffer will hold the queue structure.\n StaticQueue_t xQueueBuffer;\n\n // ucQueueStorage will hold the items posted to the queue.  Must be at least\n // [(queue length) * ( queue item size)] bytes long.\n uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.\n\t\t\t\t\t\t\tITEM_SIZE\t  // The size of each item in the queue\n\t\t\t\t\t\t\t&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.\n\t\t\t\t\t\t\t&xQueueBuffer ); // The buffer that will hold the queue structure.\n\n\t// The queue is guaranteed to be created successfully as no dynamic memory\n\t// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueCreateStatic xQueueCreateStatic\n * \\ingroup QueueManagement\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToToFront(\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\n\t\t\t\t\t\t\t   );\n * </pre>\n *\n * Post an item to the front of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToBack(\n\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t   const void\t\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t   TickType_t\t\txTicksToWait\n\t\t\t\t\t\t\t   );\n * </pre>\n *\n * This is a macro that calls xQueueGenericSend().\n *\n * Post an item to the back of a queue.  The item is queued by copy, not by\n * reference.  This function must not be called from an interrupt service\n * routine.  See xQueueSendFromISR () for an alternative which may be used\n * in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the queue\n * is full.  The  time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSend(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\n\t\t\t\t\t\t\t  TickType_t xTicksToWait\n\t\t\t\t\t\t );\n * </pre>\n *\n * This is a macro that calls xQueueGenericSend().  It is included for\n * backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is\n * equivalent to xQueueSendToBack().\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\n#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueOverwrite(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue\n\t\t\t\t\t\t );\n * </pre>\n *\n * Only for use with queues that have a length of one - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * This function must not be called from an interrupt service routine.\n * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle of the queue to which the data is being sent.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and\n * therefore has the same return values as xQueueSendToFront().  However, pdPASS\n * is the only value that can be returned because xQueueOverwrite() will write\n * to the queue even when the queue is already full.\n *\n * Example usage:\n   <pre>\n\n void vFunction( void *pvParameters )\n {\n QueueHandle_t xQueue;\n uint32_t ulVarToSend, ulValReceived;\n\n\t// Create a queue to hold one uint32_t value.  It is strongly\n\t// recommended *not* to use xQueueOverwrite() on queues that can\n\t// contain more than one value, and doing so will trigger an assertion\n\t// if configASSERT() is defined.\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n\n\t// Write the value 10 to the queue using xQueueOverwrite().\n\tulVarToSend = 10;\n\txQueueOverwrite( xQueue, &ulVarToSend );\n\n\t// Peeking the queue should now return 10, but leave the value 10 in\n\t// the queue.  A block time of zero is used as it is known that the\n\t// queue holds a value.\n\tulValReceived = 0;\n\txQueuePeek( xQueue, &ulValReceived, 0 );\n\n\tif( ulValReceived != 10 )\n\t{\n\t\t// Error unless the item was removed by a different task.\n\t}\n\n\t// The queue is still full.  Use xQueueOverwrite() to overwrite the\n\t// value held in the queue with 100.\n\tulVarToSend = 100;\n\txQueueOverwrite( xQueue, &ulVarToSend );\n\n\t// This time read from the queue, leaving the queue empty once more.\n\t// A block time of 0 is used again.\n\txQueueReceive( xQueue, &ulValReceived, 0 );\n\n\t// The value read should be the last value written, even though the\n\t// queue was already full when the value was written.\n\tif( ulValReceived != 100 )\n\t{\n\t\t// Error!\n\t}\n\n\t// ...\n}\n </pre>\n * \\defgroup xQueueOverwrite xQueueOverwrite\n * \\ingroup QueueManagement\n */\n#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )\n\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueGenericSend(\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\tconst void * pvItemToQueue,\n\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait\n\t\t\t\t\t\t\t\t\tBaseType_t xCopyPosition\n\t\t\t\t\t\t\t\t);\n * </pre>\n *\n * It is preferred that the macros xQueueSend(), xQueueSendToFront() and\n * xQueueSendToBack() are used in place of calling this function directly.\n *\n * Post an item on a queue.  The item is queued by copy, not by reference.\n * This function must not be called from an interrupt service routine.\n * See xQueueSendFromISR () for an alternative which may be used in an ISR.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for space to become available on the queue, should it already\n * be full.  The call will return immediately if this is set to 0 and the\n * queue is full.  The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n uint32_t ulVar = 10UL;\n\n void vATask( void *pvParameters )\n {\n QueueHandle_t xQueue1, xQueue2;\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 uint32_t values.\n\txQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\n\t// ...\n\n\tif( xQueue1 != 0 )\n\t{\n\t\t// Send an uint32_t.  Wait for 10 ticks for space to become\n\t\t// available if necessary.\n\t\tif( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )\n\t\t{\n\t\t\t// Failed to post the message, even after 10 ticks.\n\t\t}\n\t}\n\n\tif( xQueue2 != 0 )\n\t{\n\t\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t\t// queue is already full.\n\t\tpxMessage = & xMessage;\n\t\txQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueSend xQueueSend\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueuePeek(\n\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t void * const pvBuffer,\n\t\t\t\t\t\t\t TickType_t xTicksToWait\n\t\t\t\t\t\t );</pre>\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * This macro must not be used in an interrupt service routine.  See\n * xQueuePeekFromISR() for an alternative that can be called from an interrupt\n * service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call.\t The time is defined in tick periods so the constant\n * portTICK_PERIOD_MS should be used to convert to real time if this is required.\n * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue\n * is empty.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n QueueHandle_t xQueue;\n\n // Task to create a queue and post a value.\n void vATask( void *pvParameters )\n {\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t// queue is already full.\n\tpxMessage = & xMessage;\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\n\t// ... Rest of task code.\n }\n\n // Task to peek the data from the queue.\n void vADifferentTask( void *pvParameters )\n {\n struct AMessage *pxRxedMessage;\n\n\tif( xQueue != 0 )\n\t{\n\t\t// Peek a message on the created queue.  Block for 10 ticks if a\n\t\t// message is not immediately available.\n\t\tif( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n\t\t{\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\n\t\t\t// by vATask, but the item still remains on the queue.\n\t\t}\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueuePeek xQueuePeek\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueuePeekFromISR(\n\t\t\t\t\t\t\t\t\tQueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\tvoid *pvBuffer,\n\t\t\t\t\t\t\t\t);</pre>\n *\n * A version of xQueuePeek() that can be called from an interrupt service\n * routine (ISR).\n *\n * Receive an item from a queue without removing the item from the queue.\n * The item is received by copy so a buffer of adequate size must be\n * provided.  The number of bytes copied into the buffer was defined when\n * the queue was created.\n *\n * Successfully received items remain on the queue so will be returned again\n * by the next call, or a call to xQueueReceive().\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * \\defgroup xQueuePeekFromISR xQueuePeekFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueReceive(\n\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t void *pvBuffer,\n\t\t\t\t\t\t\t\t TickType_t xTicksToWait\n\t\t\t\t\t\t\t);</pre>\n *\n * Receive an item from a queue.  The item is received by copy so a buffer of\n * adequate size must be provided.  The number of bytes copied into the buffer\n * was defined when the queue was created.\n *\n * Successfully received items are removed from the queue.\n *\n * This function must not be used in an interrupt service routine.  See\n * xQueueReceiveFromISR for an alternative that can.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param xTicksToWait The maximum amount of time the task should block\n * waiting for an item to receive should the queue be empty at the time\n * of the call.\t xQueueReceive() will return immediately if xTicksToWait\n * is zero and the queue is empty.  The time is defined in tick periods so the\n * constant portTICK_PERIOD_MS should be used to convert to real time if this is\n * required.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n struct AMessage\n {\n\tchar ucMessageID;\n\tchar ucData[ 20 ];\n } xMessage;\n\n QueueHandle_t xQueue;\n\n // Task to create a queue and post a value.\n void vATask( void *pvParameters )\n {\n struct AMessage *pxMessage;\n\n\t// Create a queue capable of containing 10 pointers to AMessage structures.\n\t// These should be passed by pointer as they contain a lot of data.\n\txQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Send a pointer to a struct AMessage object.  Don't block if the\n\t// queue is already full.\n\tpxMessage = & xMessage;\n\txQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );\n\n\t// ... Rest of task code.\n }\n\n // Task to receive from the queue.\n void vADifferentTask( void *pvParameters )\n {\n struct AMessage *pxRxedMessage;\n\n\tif( xQueue != 0 )\n\t{\n\t\t// Receive a message on the created queue.  Block for 10 ticks if a\n\t\t// message is not immediately available.\n\t\tif( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )\n\t\t{\n\t\t\t// pcRxedMessage now points to the struct AMessage variable posted\n\t\t\t// by vATask.\n\t\t}\n\t}\n\n\t// ... Rest of task code.\n }\n </pre>\n * \\defgroup xQueueReceive xQueueReceive\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>\n *\n * Return the number of messages stored in a queue.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of messages available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>\n *\n * Return the number of free spaces available in a queue.  This is equal to the\n * number of items that can be sent to the queue before the queue becomes full\n * if no items are removed.\n *\n * @param xQueue A handle to the queue being queried.\n *\n * @return The number of spaces available in the queue.\n *\n * \\defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting\n * \\ingroup QueueManagement\n */\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>\n *\n * Delete a queue - freeing all the memory allocated for storing of items\n * placed on the queue.\n *\n * @param xQueue A handle to the queue to be deleted.\n *\n * \\defgroup vQueueDelete vQueueDelete\n * \\ingroup QueueManagement\n */\nvoid vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToFrontFromISR(\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t\t  );\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the front of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPrioritTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )\n\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendToBackFromISR(\n\t\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t\t  );\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().\n *\n * Post an item to the back of a queue.  It is safe to use this macro from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueOverwriteFromISR(\n\t\t\t\t\t\t\t  QueueHandle_t xQueue,\n\t\t\t\t\t\t\t  const void * pvItemToQueue,\n\t\t\t\t\t\t\t  BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t );\n * </pre>\n *\n * A version of xQueueOverwrite() that can be used in an interrupt service\n * routine (ISR).\n *\n * Only for use with queues that can hold a single item - so the queue is either\n * empty or full.\n *\n * Post an item on a queue.  If the queue is already full then overwrite the\n * value held in the queue.  The item is queued by copy, not by reference.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return xQueueOverwriteFromISR() is a macro that calls\n * xQueueGenericSendFromISR(), and therefore has the same return values as\n * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be\n * returned because xQueueOverwriteFromISR() will write to the queue even when\n * the queue is already full.\n *\n * Example usage:\n   <pre>\n\n QueueHandle_t xQueue;\n\n void vFunction( void *pvParameters )\n {\n \t// Create a queue to hold one uint32_t value.  It is strongly\n\t// recommended *not* to use xQueueOverwriteFromISR() on queues that can\n\t// contain more than one value, and doing so will trigger an assertion\n\t// if configASSERT() is defined.\n\txQueue = xQueueCreate( 1, sizeof( uint32_t ) );\n}\n\nvoid vAnInterruptHandler( void )\n{\n// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;\nuint32_t ulVarToSend, ulValReceived;\n\n\t// Write the value 10 to the queue using xQueueOverwriteFromISR().\n\tulVarToSend = 10;\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n\n\t// The queue is full, but calling xQueueOverwriteFromISR() again will still\n\t// pass because the value held in the queue will be overwritten with the\n\t// new value.\n\tulVarToSend = 100;\n\txQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );\n\n\t// Reading from the queue will now return 100.\n\n\t// ...\n\n\tif( xHigherPrioritytaskWoken == pdTRUE )\n\t{\n\t\t// Writing to the queue caused a task to unblock and the unblocked task\n\t\t// has a priority higher than or equal to the priority of the currently\n\t\t// executing task (the task this interrupt interrupted).  Perform a context\n\t\t// switch so this interrupt returns directly to the unblocked task.\n\t\tportYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.\n\t}\n}\n </pre>\n * \\defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueSendFromISR(\n\t\t\t\t\t\t\t\t\t QueueHandle_t xQueue,\n\t\t\t\t\t\t\t\t\t const void *pvItemToQueue,\n\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken\n\t\t\t\t\t\t\t\t);\n </pre>\n *\n * This is a macro that calls xQueueGenericSendFromISR().  It is included\n * for backward compatibility with versions of FreeRTOS.org that did not\n * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()\n * macros.\n *\n * Post an item to the back of a queue.  It is safe to use this function from\n * within an interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWoken;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWoken = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post the byte.\n\t\txQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.\n\tif( xHigherPriorityTaskWoken )\n\t{\n\t\t// Actual macro used here is port specific.\n\t\tportYIELD_FROM_ISR ();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\n#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueGenericSendFromISR(\n\t\t\t\t\t\t\t\t\t\t   QueueHandle_t\t\txQueue,\n\t\t\t\t\t\t\t\t\t\t   const\tvoid\t*pvItemToQueue,\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\t*pxHigherPriorityTaskWoken,\n\t\t\t\t\t\t\t\t\t\t   BaseType_t\txCopyPosition\n\t\t\t\t\t\t\t\t\t   );\n </pre>\n *\n * It is preferred that the macros xQueueSendFromISR(),\n * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place\n * of calling this function directly.  xQueueGiveFromISR() is an\n * equivalent for use by semaphores that don't actually copy any data.\n *\n * Post an item on a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * Items are queued by copy not reference so it is preferable to only\n * queue small items, especially when called from an ISR.  In most cases\n * it would be preferable to store a pointer to the item being queued.\n *\n * @param xQueue The handle to the queue on which the item is to be posted.\n *\n * @param pvItemToQueue A pointer to the item that is to be placed on the\n * queue.  The size of the items the queue will hold was defined when the\n * queue was created, so this many bytes will be copied from pvItemToQueue\n * into the queue storage area.\n *\n * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the\n * item at the back of the queue, or queueSEND_TO_FRONT to place the item\n * at the front of the queue (for high priority messages).\n *\n * @return pdTRUE if the data was successfully sent to the queue, otherwise\n * errQUEUE_FULL.\n *\n * Example usage for buffered IO (where the ISR can obtain more than one value\n * per call):\n   <pre>\n void vBufferISR( void )\n {\n char cIn;\n BaseType_t xHigherPriorityTaskWokenByPost;\n\n\t// We have not woken a task at the start of the ISR.\n\txHigherPriorityTaskWokenByPost = pdFALSE;\n\n\t// Loop until the buffer is empty.\n\tdo\n\t{\n\t\t// Obtain a byte from the buffer.\n\t\tcIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );\n\n\t\t// Post each byte.\n\t\txQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );\n\n\t} while( portINPUT_BYTE( BUFFER_COUNT ) );\n\n\t// Now the buffer is empty we can switch context if necessary.  Note that the\n\t// name of the yield function required is port specific.\n\tif( xHigherPriorityTaskWokenByPost )\n\t{\n\t\tportYIELD_FROM_ISR();\n\t}\n }\n </pre>\n *\n * \\defgroup xQueueSendFromISR xQueueSendFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * queue. h\n * <pre>\n BaseType_t xQueueReceiveFromISR(\n\t\t\t\t\t\t\t\t\t   QueueHandle_t\txQueue,\n\t\t\t\t\t\t\t\t\t   void\t*pvBuffer,\n\t\t\t\t\t\t\t\t\t   BaseType_t *pxTaskWoken\n\t\t\t\t\t\t\t\t   );\n * </pre>\n *\n * Receive an item from a queue.  It is safe to use this function from within an\n * interrupt service routine.\n *\n * @param xQueue The handle to the queue from which the item is to be\n * received.\n *\n * @param pvBuffer Pointer to the buffer into which the received item will\n * be copied.\n *\n * @param pxTaskWoken A task may be blocked waiting for space to become\n * available on the queue.  If xQueueReceiveFromISR causes such a task to\n * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will\n * remain unchanged.\n *\n * @return pdTRUE if an item was successfully received from the queue,\n * otherwise pdFALSE.\n *\n * Example usage:\n   <pre>\n\n QueueHandle_t xQueue;\n\n // Function to create a queue and post some values.\n void vAFunction( void *pvParameters )\n {\n char cValueToPost;\n const TickType_t xTicksToWait = ( TickType_t )0xff;\n\n\t// Create a queue capable of containing 10 characters.\n\txQueue = xQueueCreate( 10, sizeof( char ) );\n\tif( xQueue == 0 )\n\t{\n\t\t// Failed to create the queue.\n\t}\n\n\t// ...\n\n\t// Post some characters that will be used within an ISR.  If the queue\n\t// is full then this task will block for xTicksToWait ticks.\n\tcValueToPost = 'a';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n\tcValueToPost = 'b';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n\n\t// ... keep posting characters ... this task may block when the queue\n\t// becomes full.\n\n\tcValueToPost = 'c';\n\txQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );\n }\n\n // ISR that outputs all the characters received on the queue.\n void vISR_Routine( void )\n {\n BaseType_t xTaskWokenByReceive = pdFALSE;\n char cRxedChar;\n\n\twhile( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )\n\t{\n\t\t// A character was received.  Output the character now.\n\t\tvOutputCharacter( cRxedChar );\n\n\t\t// If removing the character from the queue woke the task that was\n\t\t// posting onto the queue cTaskWokenByReceive will have been set to\n\t\t// pdTRUE.  No matter how many times this loop iterates only one\n\t\t// task will be woken.\n\t}\n\n\tif( cTaskWokenByPost != ( char ) pdFALSE;\n\t{\n\t\ttaskYIELD ();\n\t}\n }\n </pre>\n * \\defgroup xQueueReceiveFromISR xQueueReceiveFromISR\n * \\ingroup QueueManagement\n */\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/*\n * Utilities to query queues that are safe to use from an ISR.  These utilities\n * should be used only from witin an ISR, or within a critical section.\n */\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * The functions defined above are for passing data to and from tasks.  The\n * functions below are the equivalents for passing data to and from\n * co-routines.\n *\n * These functions are called from the co-routine macro implementation and\n * should not be called directly from application code.  Instead use the macro\n * wrappers defined within croutine.h.\n */\nBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );\nBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );\nBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );\nBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );\n\n/*\n * For internal use only.  Use xSemaphoreCreateMutex(),\n * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling\n * these functions directly.\n */\nQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;\nQueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\nTaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Use xSemaphoreTakeMutexRecursive() or\n * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.\n */\nBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;\n\n/*\n * Reset a queue back to its original empty state.  The return value is now\n * obsolete and is always set to pdPASS.\n */\n#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger.  If you are not using a kernel\n * aware debugger then this function can be ignored.\n *\n * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the\n * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0\n * within FreeRTOSConfig.h for the registry to be available.  Its value\n * does not effect the number of queues, semaphores and mutexes that can be\n * created - just the number that the registry can hold.\n *\n * @param xQueue The handle of the queue being added to the registry.  This\n * is the handle returned by a call to xQueueCreate().  Semaphore and mutex\n * handles can also be passed in here.\n *\n * @param pcName The name to be associated with the handle.  This is the\n * name that the kernel aware debugger will display.  The queue registry only\n * stores a pointer to the string - so the string must be persistent (global or\n * preferably in ROM/Flash), not on the stack.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * The registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add\n * a queue, semaphore or mutex handle to the registry if you want the handle\n * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to\n * remove the queue, semaphore or mutex from the register.  If you are not using\n * a kernel aware debugger then this function can be ignored.\n *\n * @param xQueue The handle of the queue being removed from the registry.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * The queue registry is provided as a means for kernel aware debuggers to\n * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look\n * up and return the name of a queue in the queue registry from the queue's\n * handle.\n *\n * @param xQueue The handle of the queue the name of which will be returned.\n * @return If the queue is in the registry then a pointer to the name of the\n * queue is returned.  If the queue is not in the registry then NULL is\n * returned.\n */\n#if( configQUEUE_REGISTRY_SIZE > 0 )\n\tconst char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n#endif\n\n/*\n * Generic version of the function used to creaet a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Generic version of the function used to creaet a queue using dynamic memory\n * allocation.  This is called by other functions and macros that create other\n * RTOS objects that use the queue structure as their base.\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tQueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Queue sets provide a mechanism to allow a task to block (pend) on a read\n * operation from multiple queues or semaphores simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * A queue set must be explicitly created using a call to xQueueCreateSet()\n * before it can be used.  Once created, standard FreeRTOS queues and semaphores\n * can be added to the set using calls to xQueueAddToSet().\n * xQueueSelectFromSet() is then used to determine which, if any, of the queues\n * or semaphores contained in the set is in a state where a queue read or\n * semaphore take operation would be successful.\n *\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  An additional 4 bytes of RAM is required for each space in a every\n * queue added to a queue set.  Therefore counting semaphores that have a high\n * maximum count value should not be added to a queue set.\n *\n * Note 4:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param uxEventQueueLength Queue sets store events that occur on\n * the queues and semaphores contained in the set.  uxEventQueueLength specifies\n * the maximum number of events that can be queued at once.  To be absolutely\n * certain that events are not lost uxEventQueueLength should be set to the\n * total sum of the length of the queues added to the set, where binary\n * semaphores and mutexes have a length of 1, and counting semaphores have a\n * length set by their maximum count value.  Examples:\n *  + If a queue set is to hold a queue of length 5, another queue of length 12,\n *    and a binary semaphore, then uxEventQueueLength should be set to\n *    (5 + 12 + 1), or 18.\n *  + If a queue set is to hold three binary semaphores then uxEventQueueLength\n *    should be set to (1 + 1 + 1 ), or 3.\n *  + If a queue set is to hold a counting semaphore that has a maximum count of\n *    5, and a counting semaphore that has a maximum count of 3, then\n *    uxEventQueueLength should be set to (5 + 3), or 8.\n *\n * @return If the queue set is created successfully then a handle to the created\n * queue set is returned.  Otherwise NULL is returned.\n */\nQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;\n\n/*\n * Adds a queue or semaphore to a queue set that was previously created by a\n * call to xQueueCreateSet().\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being added to\n * the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set to which the queue or semaphore\n * is being added.\n *\n * @return If the queue or semaphore was successfully added to the queue set\n * then pdPASS is returned.  If the queue could not be successfully added to the\n * queue set because it is already a member of a different queue set then pdFAIL\n * is returned.\n */\nBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * Removes a queue or semaphore from a queue set.  A queue or semaphore can only\n * be removed from a set if the queue or semaphore is empty.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * @param xQueueOrSemaphore The handle of the queue or semaphore being removed\n * from the queue set (cast to an QueueSetMemberHandle_t type).\n *\n * @param xQueueSet The handle of the queue set in which the queue or semaphore\n * is included.\n *\n * @return If the queue or semaphore was successfully removed from the queue set\n * then pdPASS is returned.  If the queue was not in the queue set, or the\n * queue (or semaphore) was not empty, then pdFAIL is returned.\n */\nBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/*\n * xQueueSelectFromSet() selects from the members of a queue set a queue or\n * semaphore that either contains data (in the case of a queue) or is available\n * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively\n * allows a task to block (pend) on a read operation on all the queues and\n * semaphores in a queue set simultaneously.\n *\n * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this\n * function.\n *\n * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html\n * for reasons why queue sets are very rarely needed in practice as there are\n * simpler methods of blocking on multiple objects.\n *\n * Note 2:  Blocking on a queue set that contains a mutex will not cause the\n * mutex holder to inherit the priority of the blocked task.\n *\n * Note 3:  A receive (in the case of a queue) or take (in the case of a\n * semaphore) operation must not be performed on a member of a queue set unless\n * a call to xQueueSelectFromSet() has first returned a handle to that set member.\n *\n * @param xQueueSet The queue set on which the task will (potentially) block.\n *\n * @param xTicksToWait The maximum time, in ticks, that the calling task will\n * remain in the Blocked state (with other tasks executing) to wait for a member\n * of the queue set to be ready for a successful queue read or semaphore take\n * operation.\n *\n * @return xQueueSelectFromSet() will return the handle of a queue (cast to\n * a QueueSetMemberHandle_t type) contained in the queue set that contains data,\n * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained\n * in the queue set that is available, or NULL if no such queue or semaphore\n * exists before before the specified block time expires.\n */\nQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * A version of xQueueSelectFromSet() that can be used from an ISR.\n */\nQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;\n\n/* Not public API functions. */\nvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;\nvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;\nUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\nuint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* QUEUE_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/semphr.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef SEMAPHORE_H\n#define SEMAPHORE_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h\" must appear in source files before \"include semphr.h\"\n#endif\n\n#include \"queue.h\"\n\ntypedef QueueHandle_t SemaphoreHandle_t;\n\n#define semBINARY_SEMAPHORE_QUEUE_LENGTH\t( ( uint8_t ) 1U )\n#define semSEMAPHORE_QUEUE_ITEM_LENGTH\t\t( ( uint8_t ) 0U )\n#define semGIVE_BLOCK_TIME\t\t\t\t\t( ( TickType_t ) 0U )\n\n\n/**\n * semphr. h\n * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.\n * The queue length is 1 as this is a binary semaphore.  The data size is 0\n * as we don't want to actually store any data - we just want to know if the\n * queue is empty or full.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().\n    // This is a macro so pass the variable in directly.\n    vSemaphoreCreateBinary( xSemaphore );\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define vSemaphoreCreateBinary( xSemaphore )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );\t\\\n\t\t\tif( ( xSemaphore ) != NULL )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xSemaphoreGive( ( xSemaphore ) );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this\n * xSemaphoreCreateBinary() function.  Note that binary semaphores created using\n * the vSemaphoreCreateBinary() macro are created in a state such that the\n * first call to 'take' the semaphore would pass, whereas binary semaphores\n * created using xSemaphoreCreateBinary() are created in a state such that the\n * the semaphore must first be 'given' before it can be 'taken'.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @return Handle to the created semaphore, or NULL if the memory required to\n * hold the semaphore's data structures could not be allocated.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateBinary();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>\n *\n * Creates a new binary semaphore instance, and returns a handle by which the\n * new semaphore can be referenced.\n *\n * NOTE: In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a binary semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, binary semaphores use a block\n * of memory, in which the semaphore structure is stored.  If a binary semaphore\n * is created using xSemaphoreCreateBinary() then the required memory is\n * automatically dynamically allocated inside the xSemaphoreCreateBinary()\n * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore\n * is created using xSemaphoreCreateBinaryStatic() then the application writer\n * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a\n * binary semaphore to be created without using any dynamic memory allocation.\n *\n * This type of semaphore can be used for pure synchronisation between tasks or\n * between an interrupt and a task.  The semaphore need not be given back once\n * obtained, so one task/interrupt can continuously 'give' the semaphore while\n * another continuously 'takes' the semaphore.  For this reason this type of\n * semaphore does not use a priority inheritance mechanism.  For an alternative\n * that does use priority inheritance see xSemaphoreCreateMutex().\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the semaphore is created then a handle to the created semaphore is\n * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n StaticSemaphore_t xSemaphoreBuffer;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().\n    // The semaphore's data structures will be placed in the xSemaphoreBuffer\n    // variable, the address of which is passed into the function.  The\n    // function's parameter is not NULL, so the function will not attempt any\n    // dynamic memory allocation, and therefore the function will not return\n    // return NULL.\n    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );\n\n    // Rest of task code goes here.\n }\n </pre>\n * \\defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>xSemaphoreTake(\n *                   SemaphoreHandle_t xSemaphore,\n *                   TickType_t xBlockTime\n *               )</pre>\n *\n * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting().\n *\n * @param xSemaphore A handle to the semaphore being taken - obtained when\n * the semaphore was created.\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  A block\n * time of portMAX_DELAY can be used to block indefinitely (provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE\n * if xBlockTime expired without the semaphore becoming available.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n // A task that creates a semaphore.\n void vATask( void * pvParameters )\n {\n    // Create the semaphore to guard a shared resource.\n    xSemaphore = xSemaphoreCreateBinary();\n }\n\n // A task that uses the semaphore.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xSemaphore != NULL )\n    {\n        // See if we can obtain the semaphore.  If the semaphore is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the semaphore and can now access the\n            // shared resource.\n\n            // ...\n\n            // We have finished accessing the shared resource.  Release the\n            // semaphore.\n            xSemaphoreGive( xSemaphore );\n        }\n        else\n        {\n            // We could not obtain the semaphore and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreTake xSemaphoreTake\n * \\ingroup Semaphores\n */\n#define xSemaphoreTake( xSemaphore, xBlockTime )\t\txQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )\n\n/**\n * semphr. h\n * xSemaphoreTakeRecursive(\n *                          SemaphoreHandle_t xMutex,\n *                          TickType_t xBlockTime\n *                        )\n *\n * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being obtained.  This is the\n * handle returned by xSemaphoreCreateRecursiveMutex();\n *\n * @param xBlockTime The time in ticks to wait for the semaphore to become\n * available.  The macro portTICK_PERIOD_MS can be used to convert this to a\n * real time.  A block time of zero can be used to poll the semaphore.  If\n * the task already owns the semaphore then xSemaphoreTakeRecursive() will\n * return immediately no matter what the value of xBlockTime.\n *\n * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime\n * expired without the semaphore becoming available.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xMutex = NULL;\n\n // A task that creates a mutex.\n void vATask( void * pvParameters )\n {\n    // Create the mutex to guard a shared resource.\n    xMutex = xSemaphoreCreateRecursiveMutex();\n }\n\n // A task that uses the mutex.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xMutex != NULL )\n    {\n        // See if we can obtain the mutex.  If the mutex is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the mutex and can now access the\n            // shared resource.\n\n            // ...\n            // For some reason due to the nature of the code further calls to\n            // xSemaphoreTakeRecursive() are made on the same mutex.  In real\n            // code these would not be just sequential calls as this would make\n            // no sense.  Instead the calls are likely to be buried inside\n            // a more complex call structure.\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n\n            // The mutex has now been 'taken' three times, so will not be\n            // available to another task until it has also been given back\n            // three times.  Again it is unlikely that real code would have\n            // these calls sequentially, but instead buried in a more complex\n            // call structure.  This is just for illustrative purposes.\n            xSemaphoreGiveRecursive( xMutex );\n            xSemaphoreGiveRecursive( xMutex );\n            xSemaphoreGiveRecursive( xMutex );\n\n            // Now the mutex can be taken by other tasks.\n        }\n        else\n        {\n            // We could not obtain the mutex and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive\n * \\ingroup Semaphores\n */\n#if( configUSE_RECURSIVE_MUTEXES == 1 )\n\t#define xSemaphoreTakeRecursive( xMutex, xBlockTime )\txQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )\n#endif\n\n/**\n * semphr. h\n * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>\n *\n * <i>Macro</i> to release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or\n * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().\n *\n * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for\n * an alternative which can be used from an ISR.\n *\n * This macro must also not be used on semaphores created using\n * xSemaphoreCreateRecursiveMutex().\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.\n * Semaphores are implemented using queues.  An error can occur if there is\n * no space on the queue to post a message - indicating that the\n * semaphore was not first obtained correctly.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore = NULL;\n\n void vATask( void * pvParameters )\n {\n    // Create the semaphore to guard a shared resource.\n    xSemaphore = vSemaphoreCreateBinary();\n\n    if( xSemaphore != NULL )\n    {\n        if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n        {\n            // We would expect this call to fail because we cannot give\n            // a semaphore without first \"taking\" it!\n        }\n\n        // Obtain the semaphore - don't block if the semaphore is not\n        // immediately available.\n        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )\n        {\n            // We now have the semaphore and can access the shared resource.\n\n            // ...\n\n            // We have finished accessing the shared resource so can free the\n            // semaphore.\n            if( xSemaphoreGive( xSemaphore ) != pdTRUE )\n            {\n                // We would not expect this call to fail because we must have\n                // obtained the semaphore to get here.\n            }\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGive xSemaphoreGive\n * \\ingroup Semaphores\n */\n#define xSemaphoreGive( xSemaphore )\t\txQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )\n\n/**\n * semphr. h\n * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>\n *\n * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.\n * The mutex must have previously been created using a call to\n * xSemaphoreCreateRecursiveMutex();\n *\n * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this\n * macro to be available.\n *\n * This macro must not be used on mutexes created using xSemaphoreCreateMutex().\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * @param xMutex A handle to the mutex being released, or 'given'.  This is the\n * handle returned by xSemaphoreCreateMutex();\n *\n * @return pdTRUE if the semaphore was given.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xMutex = NULL;\n\n // A task that creates a mutex.\n void vATask( void * pvParameters )\n {\n    // Create the mutex to guard a shared resource.\n    xMutex = xSemaphoreCreateRecursiveMutex();\n }\n\n // A task that uses the mutex.\n void vAnotherTask( void * pvParameters )\n {\n    // ... Do other things.\n\n    if( xMutex != NULL )\n    {\n        // See if we can obtain the mutex.  If the mutex is not available\n        // wait 10 ticks to see if it becomes free.\n        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )\n        {\n            // We were able to obtain the mutex and can now access the\n            // shared resource.\n\n            // ...\n            // For some reason due to the nature of the code further calls to\n\t\t\t// xSemaphoreTakeRecursive() are made on the same mutex.  In real\n\t\t\t// code these would not be just sequential calls as this would make\n\t\t\t// no sense.  Instead the calls are likely to be buried inside\n\t\t\t// a more complex call structure.\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );\n\n            // The mutex has now been 'taken' three times, so will not be\n\t\t\t// available to another task until it has also been given back\n\t\t\t// three times.  Again it is unlikely that real code would have\n\t\t\t// these calls sequentially, it would be more likely that the calls\n\t\t\t// to xSemaphoreGiveRecursive() would be called as a call stack\n\t\t\t// unwound.  This is just for demonstrative purposes.\n            xSemaphoreGiveRecursive( xMutex );\n\t\t\txSemaphoreGiveRecursive( xMutex );\n\t\t\txSemaphoreGiveRecursive( xMutex );\n\n\t\t\t// Now the mutex can be taken by other tasks.\n        }\n        else\n        {\n            // We could not obtain the mutex and can therefore not access\n            // the shared resource safely.\n        }\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive\n * \\ingroup Semaphores\n */\n#if( configUSE_RECURSIVE_MUTEXES == 1 )\n\t#define xSemaphoreGiveRecursive( xMutex )\txQueueGiveMutexRecursive( ( xMutex ) )\n#endif\n\n/**\n * semphr. h\n * <pre>\n xSemaphoreGiveFromISR(\n                          SemaphoreHandle_t xSemaphore,\n                          BaseType_t *pxHigherPriorityTaskWoken\n                      )</pre>\n *\n * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been\n * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR.\n *\n * @param xSemaphore A handle to the semaphore being released.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.\n *\n * Example usage:\n <pre>\n \\#define LONG_TIME 0xffff\n \\#define TICKS_TO_WAIT\t10\n SemaphoreHandle_t xSemaphore = NULL;\n\n // Repetitive task.\n void vATask( void * pvParameters )\n {\n    for( ;; )\n    {\n        // We want this task to run every 10 ticks of a timer.  The semaphore\n        // was created before this task was started.\n\n        // Block waiting for the semaphore to become available.\n        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )\n        {\n            // It is time to execute.\n\n            // ...\n\n            // We have finished our task.  Return to the top of the loop where\n            // we will block on the semaphore until it is time to execute\n            // again.  Note when using the semaphore for synchronisation with an\n\t\t\t// ISR in this manner there is no need to 'give' the semaphore back.\n        }\n    }\n }\n\n // Timer ISR\n void vTimerISR( void * pvParameters )\n {\n static uint8_t ucLocalTickCount = 0;\n static BaseType_t xHigherPriorityTaskWoken;\n\n    // A timer tick has occurred.\n\n    // ... Do other time functions.\n\n    // Is it time for vATask () to run?\n\txHigherPriorityTaskWoken = pdFALSE;\n    ucLocalTickCount++;\n    if( ucLocalTickCount >= TICKS_TO_WAIT )\n    {\n        // Unblock the task by releasing the semaphore.\n        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );\n\n        // Reset the count so we release the semaphore again in 10 ticks time.\n        ucLocalTickCount = 0;\n    }\n\n    if( xHigherPriorityTaskWoken != pdFALSE )\n    {\n        // We can force a context switch here.  Context switching from an\n        // ISR uses port specific syntax.  Check the demo task for your port\n        // to find the syntax required.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR\n * \\ingroup Semaphores\n */\n#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * <pre>\n xSemaphoreTakeFromISR(\n                          SemaphoreHandle_t xSemaphore,\n                          BaseType_t *pxHigherPriorityTaskWoken\n                      )</pre>\n *\n * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have\n * previously been created with a call to xSemaphoreCreateBinary() or\n * xSemaphoreCreateCounting().\n *\n * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())\n * must not be used with this macro.\n *\n * This macro can be used from an ISR, however taking a semaphore from an ISR\n * is not a common operation.  It is likely to only be useful when taking a\n * counting semaphore when an interrupt is obtaining an object from a resource\n * pool (when the semaphore count indicates the number of resources available).\n *\n * @param xSemaphore A handle to the semaphore being taken.  This is the\n * handle returned when the semaphore was created.\n *\n * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task\n * to unblock, and the unblocked task has a priority higher than the currently\n * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then\n * a context switch should be requested before the interrupt is exited.\n *\n * @return pdTRUE if the semaphore was successfully taken, otherwise\n * pdFALSE\n */\n#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )\txQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return If the mutex was successfully created then a handle to the created\n * semaphore is returned.  If there was not enough heap to allocate the mutex\n * data structures then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateMutex();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>\n *\n * Creates a new mutex type semaphore instance, and returns a handle by which\n * the new mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, mutex semaphores use a block\n * of memory, in which the mutex structure is stored.  If a mutex is created\n * using xSemaphoreCreateMutex() then the required memory is automatically\n * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a mutex is created using\n * xSemaphoreCreateMutexStatic() then the application writer must provided the\n * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created\n * without using any dynamic memory allocation.\n *\n * Mutexes created using this function can be accessed using the xSemaphoreTake()\n * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and\n * xSemaphoreGiveRecursive() macros must not be used.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will be used to hold the mutex's data structure, removing the need for\n * the memory to be allocated dynamically.\n *\n * @return If the mutex was successfully created then a handle to the created\n * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xMutexBuffer;\n\n void vATask( void * pvParameters )\n {\n    // A mutex cannot be used before it has been created.  xMutexBuffer is\n    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is\n    // attempted.\n    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );\n\n    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n    // so there is no need to check it.\n }\n </pre>\n * \\defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic\n * \\ingroup Semaphores\n */\n #if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexs use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @return xSemaphore Handle to the created mutex semaphore.  Should be of type\n * SemaphoreHandle_t.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().\n    // This is a macro so pass the variable in directly.\n    xSemaphore = xSemaphoreCreateRecursiveMutex();\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex\n * \\ingroup Semaphores\n */\n#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n\t#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>\n *\n * Creates a new recursive mutex type semaphore instance, and returns a handle\n * by which the new recursive mutex can be referenced.\n *\n * Internally, within the FreeRTOS implementation, recursive mutexs use a block\n * of memory, in which the mutex structure is stored.  If a recursive mutex is\n * created using xSemaphoreCreateRecursiveMutex() then the required memory is\n * automatically dynamically allocated inside the\n * xSemaphoreCreateRecursiveMutex() function.  (see\n * http://www.freertos.org/a00111.html).  If a recursive mutex is created using\n * xSemaphoreCreateRecursiveMutexStatic() then the application writer must\n * provide the memory that will get used by the mutex.\n * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to\n * be created without using any dynamic memory allocation.\n *\n * Mutexes created using this macro can be accessed using the\n * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The\n * xSemaphoreTake() and xSemaphoreGive() macros must not be used.\n *\n * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex\n * doesn't become available again until the owner has called\n * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,\n * if a task successfully 'takes' the same mutex 5 times then the mutex will\n * not be available to any other task until it has also  'given' the mutex back\n * exactly five times.\n *\n * This type of semaphore uses a priority inheritance mechanism so a task\n * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the\n * semaphore it is no longer required.\n *\n * Mutex type semaphores cannot be used from within interrupt service routines.\n *\n * See xSemaphoreCreateBinary() for an alternative implementation that can be\n * used for pure synchronisation (where one task or interrupt always 'gives' the\n * semaphore and another always 'takes' the semaphore) and from within interrupt\n * service routines.\n *\n * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the recursive mutex's data structure,\n * removing the need for the memory to be allocated dynamically.\n *\n * @return If the recursive mutex was successfully created then a handle to the\n * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is\n * returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xMutexBuffer;\n\n void vATask( void * pvParameters )\n {\n    // A recursive semaphore cannot be used before it is created.  Here a\n    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().\n    // The address of xMutexBuffer is passed into the function, and will hold\n    // the mutexes data structures - so no dynamic memory allocation will be\n    // attempted.\n    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );\n\n    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,\n    // so there is no need to check it.\n }\n </pre>\n * \\defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic\n * \\ingroup Semaphores\n */\n#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )\n\t#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * http://www.freertos.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer can\n * instead optionally provide the memory that will get used by the counting\n * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting\n * semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @return Handle to the created semaphore.  Null if the semaphore could not be\n *         created.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n\n void vATask( void * pvParameters )\n {\n SemaphoreHandle_t xSemaphore = NULL;\n\n    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().\n    // The max value to which the semaphore can count should be 10, and the\n    // initial value assigned to the count should be 0.\n    xSemaphore = xSemaphoreCreateCounting( 10, 0 );\n\n    if( xSemaphore != NULL )\n    {\n        // The semaphore was created successfully.\n        // The semaphore can now be used.\n    }\n }\n </pre>\n * \\defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )\n#endif\n\n/**\n * semphr. h\n * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>\n *\n * Creates a new counting semaphore instance, and returns a handle by which the\n * new counting semaphore can be referenced.\n *\n * In many usage scenarios it is faster and more memory efficient to use a\n * direct to task notification in place of a counting semaphore!\n * http://www.freertos.org/RTOS-task-notifications.html\n *\n * Internally, within the FreeRTOS implementation, counting semaphores use a\n * block of memory, in which the counting semaphore structure is stored.  If a\n * counting semaphore is created using xSemaphoreCreateCounting() then the\n * required memory is automatically dynamically allocated inside the\n * xSemaphoreCreateCounting() function.  (see\n * http://www.freertos.org/a00111.html).  If a counting semaphore is created\n * using xSemaphoreCreateCountingStatic() then the application writer must\n * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a\n * counting semaphore to be created without using any dynamic memory allocation.\n *\n * Counting semaphores are typically used for two things:\n *\n * 1) Counting events.\n *\n *    In this usage scenario an event handler will 'give' a semaphore each time\n *    an event occurs (incrementing the semaphore count value), and a handler\n *    task will 'take' a semaphore each time it processes an event\n *    (decrementing the semaphore count value).  The count value is therefore\n *    the difference between the number of events that have occurred and the\n *    number that have been processed.  In this case it is desirable for the\n *    initial count value to be zero.\n *\n * 2) Resource management.\n *\n *    In this usage scenario the count value indicates the number of resources\n *    available.  To obtain control of a resource a task must first obtain a\n *    semaphore - decrementing the semaphore count value.  When the count value\n *    reaches zero there are no free resources.  When a task finishes with the\n *    resource it 'gives' the semaphore back - incrementing the semaphore count\n *    value.  In this case it is desirable for the initial count value to be\n *    equal to the maximum count value, indicating that all resources are free.\n *\n * @param uxMaxCount The maximum count value that can be reached.  When the\n *        semaphore reaches this value it can no longer be 'given'.\n *\n * @param uxInitialCount The count value assigned to the semaphore when it is\n *        created.\n *\n * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,\n * which will then be used to hold the semaphore's data structure, removing the\n * need for the memory to be allocated dynamically.\n *\n * @return If the counting semaphore was successfully created then a handle to\n * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL\n * then NULL is returned.\n *\n * Example usage:\n <pre>\n SemaphoreHandle_t xSemaphore;\n StaticSemaphore_t xSemaphoreBuffer;\n\n void vATask( void * pvParameters )\n {\n SemaphoreHandle_t xSemaphore = NULL;\n\n    // Counting semaphore cannot be used before they have been created.  Create\n    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max\n    // value to which the semaphore can count is 10, and the initial value\n    // assigned to the count will be 0.  The address of xSemaphoreBuffer is\n    // passed in and will be used to hold the semaphore structure, so no dynamic\n    // memory allocation will be used.\n    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );\n\n    // No memory allocation was attempted so xSemaphore cannot be NULL, so there\n    // is no need to check its value.\n }\n </pre>\n * \\defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic\n * \\ingroup Semaphores\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * semphr. h\n * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>\n *\n * Delete a semaphore.  This function must be used with care.  For example,\n * do not delete a mutex type semaphore if the mutex is held by a task.\n *\n * @param xSemaphore A handle to the semaphore to be deleted.\n *\n * \\defgroup vSemaphoreDelete vSemaphoreDelete\n * \\ingroup Semaphores\n */\n#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n * Note: This is a good way of determining if the calling task is the mutex\n * holder, but not a good way of determining the identity of the mutex holder as\n * the holder may change between the function exiting and the returned value\n * being tested.\n */\n#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );</pre>\n *\n * If xMutex is indeed a mutex type semaphore, return the current mutex holder.\n * If xMutex is not a mutex type semaphore, or the mutex is available (not held\n * by a task), return NULL.\n *\n */\n#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )\n\n/**\n * semphr.h\n * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>\n *\n * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns\n * its current count value.  If the semaphore is a binary semaphore then\n * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the\n * semaphore is not available.\n *\n */\n#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )\n\n#endif /* SEMAPHORE_H */\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/stack_macros.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#ifndef STACK_MACROS_H\n#define STACK_MACROS_H\n\n/*\n * Call the stack overflow hook function if the stack of the task being swapped\n * out is currently overflowed, or looks like it might have overflowed in the\n * past.\n *\n * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check\n * the current stack state only - comparing the current top of stack value to\n * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1\n * will also cause the last few stack bytes to be checked to ensure the value\n * to which the bytes were set when the task was created have not been\n * overwritten.  Note this second test does not guarantee that an overflowed\n * stack will always be recognised.\n */\n\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t/* Only the current stack state is to be checked. */\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Is the currently saved stack pointer within the stack limit? */\t\t\t\t\t\t\t\t\\\n\t\tif( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tconst uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;\t\t\t\t\t\t\t\\\n\t\tconst uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pulStack[ 0 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 1 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 2 ] != ulCheckValue ) ||\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pulStack[ 3 ] != ulCheckValue ) )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )\n\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tint8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tstatic const uint8_t ucExpectedStackBytes[] = {\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\ttskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tpcEndOfStack -= sizeof( ucExpectedStackBytes );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Has the extremity of the task stack ever been written over? */\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tvApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */\n/*-----------------------------------------------------------*/\n\n/* Remove stack overflow macro if not being used. */\n#ifndef taskCHECK_FOR_STACK_OVERFLOW\n\t#define taskCHECK_FOR_STACK_OVERFLOW()\n#endif\n\n\n\n#endif /* STACK_MACROS_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/stream_buffer.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * Stream buffers are used to send a continuous stream of data from one task or\n * interrupt to another.  Their implementation is light weight, making them\n * particularly suited for interrupt to task and core to core communication\n * scenarios.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section section and set the\n * receive block time to 0.\n *\n */\n\n#ifndef STREAM_BUFFER_H\n#define STREAM_BUFFER_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include stream_buffer.h\"\n#endif\n\n#if defined( __cplusplus )\nextern \"C\" {\n#endif\n\n/**\n * Type by which stream buffers are referenced.  For example, a call to\n * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can\n * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),\n * etc.\n */\nstruct StreamBufferDef_t;\ntypedef struct StreamBufferDef_t * StreamBufferHandle_t;\n\n\n/**\n * message_buffer.h\n *\n<pre>\nStreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );\n</pre>\n *\n * Creates a new stream buffer using dynamically allocated memory.  See\n * xStreamBufferCreateStatic() for a version that uses statically allocated\n * memory (memory that is allocated at compile time).\n *\n * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in\n * FreeRTOSConfig.h for xStreamBufferCreate() to be available.\n *\n * @param xBufferSizeBytes The total number of bytes the stream buffer will be\n * able to hold at any one time.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @return If NULL is returned, then the stream buffer cannot be created\n * because there is insufficient heap memory available for FreeRTOS to allocate\n * the stream buffer data structures and storage area.  A non-NULL value being\n * returned indicates that the stream buffer has been created successfully -\n * the returned value should be stored as the handle to the created stream\n * buffer.\n *\n * Example use:\n<pre>\n\nvoid vAFunction( void )\n{\nStreamBufferHandle_t xStreamBuffer;\nconst size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;\n\n    // Create a stream buffer that can hold 100 bytes.  The memory used to hold\n    // both the stream buffer structure and the data in the stream buffer is\n    // allocated dynamically.\n    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );\n\n    if( xStreamBuffer == NULL )\n    {\n        // There was not enough heap memory space available to create the\n        // stream buffer.\n    }\n    else\n    {\n        // The stream buffer was created successfully and can now be used.\n    }\n}\n</pre>\n * \\defgroup xStreamBufferCreate xStreamBufferCreate\n * \\ingroup StreamBufferManagement\n */\n#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )\n\n/**\n * stream_buffer.h\n *\n<pre>\nStreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,\n                                                size_t xTriggerLevelBytes,\n                                                uint8_t *pucStreamBufferStorageArea,\n                                                StaticStreamBuffer_t *pxStaticStreamBuffer );\n</pre>\n * Creates a new stream buffer using statically allocated memory.  See\n * xStreamBufferCreate() for a version that uses dynamically allocated memory.\n *\n * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for\n * xStreamBufferCreateStatic() to be available.\n *\n * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the\n * pucStreamBufferStorageArea parameter.\n *\n * @param xTriggerLevelBytes The number of bytes that must be in the stream\n * buffer before a task that is blocked on the stream buffer to wait for data is\n * moved out of the blocked state.  For example, if a task is blocked on a read\n * of an empty stream buffer that has a trigger level of 1 then the task will be\n * unblocked when a single byte is written to the buffer or the task's block\n * time expires.  As another example, if a task is blocked on a read of an empty\n * stream buffer that has a trigger level of 10 then the task will not be\n * unblocked until the stream buffer contains at least 10 bytes or the task's\n * block time expires.  If a reading task's block time expires before the\n * trigger level is reached then the task will still receive however many bytes\n * are actually available.  Setting a trigger level of 0 will result in a\n * trigger level of 1 being used.  It is not valid to specify a trigger level\n * that is greater than the buffer size.\n *\n * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at\n * least xBufferSizeBytes + 1 big.  This is the array to which streams are\n * copied when they are written to the stream buffer.\n *\n * @param pxStaticStreamBuffer Must point to a variable of type\n * StaticStreamBuffer_t, which will be used to hold the stream buffer's data\n * structure.\n *\n * @return If the stream buffer is created successfully then a handle to the\n * created stream buffer is returned. If either pucStreamBufferStorageArea or\n * pxStaticstreamBuffer are NULL then NULL is returned.\n *\n * Example use:\n<pre>\n\n// Used to dimension the array used to hold the streams.  The available space\n// will actually be one less than this, so 999.\n#define STORAGE_SIZE_BYTES 1000\n\n// Defines the memory that will actually hold the streams within the stream\n// buffer.\nstatic uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];\n\n// The variable used to hold the stream buffer structure.\nStaticStreamBuffer_t xStreamBufferStruct;\n\nvoid MyFunction( void )\n{\nStreamBufferHandle_t xStreamBuffer;\nconst size_t xTriggerLevel = 1;\n\n    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),\n                                               xTriggerLevel,\n                                               ucBufferStorage,\n                                               &xStreamBufferStruct );\n\n    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer\n    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to\n    // reference the created stream buffer in other stream buffer API calls.\n\n    // Other code that uses the stream buffer can go here.\n}\n\n</pre>\n * \\defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic\n * \\ingroup StreamBufferManagement\n */\n#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n                          const void *pvTxData,\n                          size_t xDataLengthBytes,\n                          TickType_t xTicksToWait );\n</pre>\n *\n * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the buffer that holds the bytes to be copied\n * into the stream buffer.\n *\n * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for enough space to become available in the stream\n * buffer, should the stream buffer contain too little space to hold the\n * another xDataLengthBytes bytes.  The block time is specified in tick periods,\n * so the absolute time it represents is dependent on the tick frequency.  The\n * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds\n * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will\n * cause the task to wait indefinitely (without timing out), provided\n * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out\n * before it can write all xDataLengthBytes into the buffer it will still write\n * as many bytes as possible.  A task does not use any CPU time when it is in\n * the blocked state.\n *\n * @return The number of bytes written to the stream buffer.  If a task times\n * out before it can write all xDataLengthBytes into the buffer it will still\n * write as many bytes as possible.\n *\n * Example use:\n<pre>\nvoid vAFunction( StreamBufferHandle_t xStreamBuffer )\n{\nsize_t xBytesSent;\nuint8_t ucArrayToSend[] = { 0, 1, 2, 3 };\nchar *pcStringToSend = \"String to send\";\nconst TickType_t x100ms = pdMS_TO_TICKS( 100 );\n\n    // Send an array to the stream buffer, blocking for a maximum of 100ms to\n    // wait for enough space to be available in the stream buffer.\n    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );\n\n    if( xBytesSent != sizeof( ucArrayToSend ) )\n    {\n        // The call to xStreamBufferSend() times out before there was enough\n        // space in the buffer for the data to be written, but it did\n        // successfully write xBytesSent bytes.\n    }\n\n    // Send the string to the stream buffer.  Return immediately if there is not\n    // enough space in the buffer.\n    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // The entire string could not be added to the stream buffer because\n        // there was not enough free space in the buffer, but xBytesSent bytes\n        // were sent.  Could try again to send the remaining bytes.\n    }\n}\n</pre>\n * \\defgroup xStreamBufferSend xStreamBufferSend\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t  const void *pvTxData,\n\t\t\t\t\t\t  size_t xDataLengthBytes,\n\t\t\t\t\t\t  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n                                 const void *pvTxData,\n                                 size_t xDataLengthBytes,\n                                 BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * Interrupt safe version of the API function that sends a stream of bytes to\n * the stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferSend() to write to a stream buffer from a task.  Use\n * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt\n * service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer to which a stream is\n * being sent.\n *\n * @param pvTxData A pointer to the data that is to be copied into the stream\n * buffer.\n *\n * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData\n * into the stream buffer.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for data.  Calling\n * xStreamBufferSendFromISR() can make data available, and so cause a task that\n * was waiting for data to leave the Blocked state.  If calling\n * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently executing task (the\n * task that was interrupted), then, internally, xStreamBufferSendFromISR()\n * will set *pxHigherPriorityTaskWoken to pdTRUE.  If\n * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  This will\n * ensure that the interrupt returns directly to the highest priority Ready\n * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it\n * is passed into the function.  See the example code below for an example.\n *\n * @return The number of bytes actually written to the stream buffer, which will\n * be less than xDataLengthBytes if the stream buffer didn't have enough free\n * space for all the bytes to be written.\n *\n * Example use:\n<pre>\n// A stream buffer that has already been created.\nStreamBufferHandle_t xStreamBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nsize_t xBytesSent;\nchar *pcStringToSend = \"String to send\";\nBaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.\n\n    // Attempt to send the string to the stream buffer.\n    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,\n                                           ( void * ) pcStringToSend,\n                                           strlen( pcStringToSend ),\n                                           &xHigherPriorityTaskWoken );\n\n    if( xBytesSent != strlen( pcStringToSend ) )\n    {\n        // There was not enough free space in the stream buffer for the entire\n        // string to be written, ut xBytesSent bytes were written.\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xStreamBufferSendFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t const void *pvTxData,\n\t\t\t\t\t\t\t\t size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n                             void *pvRxData,\n                             size_t xBufferLengthBytes,\n                             TickType_t xTicksToWait );\n</pre>\n *\n * Receives bytes from a stream buffer.\n *\n * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer\n * implementation (so also the message buffer implementation, as message buffers\n * are built on top of stream buffers) assumes there is only one task or\n * interrupt that will write to the buffer (the writer), and only one task or\n * interrupt that will read from the buffer (the reader).  It is safe for the\n * writer and reader to be different tasks or interrupts, but, unlike other\n * FreeRTOS objects, it is not safe to have multiple different writers or\n * multiple different readers.  If there are to be multiple different writers\n * then the application writer must place each call to a writing API function\n * (such as xStreamBufferSend()) inside a critical section and set the send\n * block time to 0.  Likewise, if there are to be multiple different readers\n * then the application writer must place each call to a reading API function\n * (such as xStreamBufferReceive()) inside a critical section and set the receive\n * block time to 0.\n *\n * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use\n * xStreamBufferReceiveFromISR() to read from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which bytes are to\n * be received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes will be\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param xTicksToWait The maximum amount of time the task should remain in the\n * Blocked state to wait for data to become available if the stream buffer is\n * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is\n * zero.  The block time is specified in tick periods, so the absolute time it\n * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can\n * be used to convert a time specified in milliseconds into a time specified in\n * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait\n * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1\n * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the\n * Blocked state.\n *\n * @return The number of bytes actually read from the stream buffer, which will\n * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed\n * out before xBufferLengthBytes were available.\n *\n * Example use:\n<pre>\nvoid vAFunction( StreamBuffer_t xStreamBuffer )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nconst TickType_t xBlockTime = pdMS_TO_TICKS( 20 );\n\n    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.\n    // Wait in the Blocked state (so not using any CPU processing time) for a\n    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be\n    // available.\n    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,\n                                           ( void * ) ucRxData,\n                                           sizeof( ucRxData ),\n                                           xBlockTime );\n\n    if( xReceivedBytes > 0 )\n    {\n        // A ucRxData contains another xRecievedBytes bytes of data, which can\n        // be processed here....\n    }\n}\n</pre>\n * \\defgroup xStreamBufferReceive xStreamBufferReceive\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t void *pvRxData,\n\t\t\t\t\t\t\t size_t xBufferLengthBytes,\n\t\t\t\t\t\t\t TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n                                    void *pvRxData,\n                                    size_t xBufferLengthBytes,\n                                    BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * An interrupt safe version of the API function that receives bytes from a\n * stream buffer.\n *\n * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.\n * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an\n * interrupt service routine (ISR).\n *\n * @param xStreamBuffer The handle of the stream buffer from which a stream\n * is being received.\n *\n * @param pvRxData A pointer to the buffer into which the received bytes are\n * copied.\n *\n * @param xBufferLengthBytes The length of the buffer pointed to by the\n * pvRxData parameter.  This sets the maximum number of bytes to receive in one\n * call.  xStreamBufferReceive will return as many bytes as possible up to a\n * maximum set by xBufferLengthBytes.\n *\n * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will\n * have a task blocked on it waiting for space to become available.  Calling\n * xStreamBufferReceiveFromISR() can make space available, and so cause a task\n * that is waiting for space to leave the Blocked state.  If calling\n * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and\n * the unblocked task has a priority higher than the currently executing task\n * (the task that was interrupted), then, internally,\n * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.\n * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a\n * context switch should be performed before the interrupt is exited.  That will\n * ensure the interrupt returns directly to the highest priority Ready state\n * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is\n * passed into the function.  See the code example below for an example.\n *\n * @return The number of bytes read from the stream buffer, if any.\n *\n * Example use:\n<pre>\n// A stream buffer that has already been created.\nStreamBuffer_t xStreamBuffer;\n\nvoid vAnInterruptServiceRoutine( void )\n{\nuint8_t ucRxData[ 20 ];\nsize_t xReceivedBytes;\nBaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.\n\n    // Receive the next stream from the stream buffer.\n    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,\n                                                  ( void * ) ucRxData,\n                                                  sizeof( ucRxData ),\n                                                  &xHigherPriorityTaskWoken );\n\n    if( xReceivedBytes > 0 )\n    {\n        // ucRxData contains xReceivedBytes read from the stream buffer.\n        // Process the stream here....\n    }\n\n    // If xHigherPriorityTaskWoken was set to pdTRUE inside\n    // xStreamBufferReceiveFromISR() then a task that has a priority above the\n    // priority of the currently executing task was unblocked and a context\n    // switch should be performed to ensure the ISR returns to the unblocked\n    // task.  In most FreeRTOS ports this is done by simply passing\n    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the\n    // variables value, and perform the context switch if necessary.  Check the\n    // documentation for the port in use for port specific instructions.\n    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n}\n</pre>\n * \\defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\tBaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Deletes a stream buffer that was previously created using a call to\n * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream\n * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),\n * then the allocated memory is freed.\n *\n * A stream buffer handle must not be used after the stream buffer has been\n * deleted.\n *\n * @param xStreamBuffer The handle of the stream buffer to be deleted.\n *\n * \\defgroup vStreamBufferDelete vStreamBufferDelete\n * \\ingroup StreamBufferManagement\n */\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see if it is full.  A stream buffer is full if it\n * does not have any free space, and therefore cannot accept any more data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is full then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsFull xStreamBufferIsFull\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see if it is empty.  A stream buffer is empty if\n * it does not contain any data.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Resets a stream buffer to its initial, empty, state.  Any data that was in\n * the stream buffer is discarded.  A stream buffer can only be reset if there\n * are no tasks blocked waiting to either send to or receive from the stream\n * buffer.\n *\n * @param xStreamBuffer The handle of the stream buffer being reset.\n *\n * @return If the stream buffer is reset then pdPASS is returned.  If there was\n * a task blocked waiting to send to or read from the stream buffer then the\n * stream buffer is not reset and pdFAIL is returned.\n *\n * \\defgroup xStreamBufferReset xStreamBufferReset\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see how much free space it contains, which is\n * equal to the amount of data that can be sent to the stream buffer before it\n * is full.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be written to the stream buffer before\n * the stream buffer would be full.\n *\n * \\defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );\n</pre>\n *\n * Queries a stream buffer to see how much data it contains, which is equal to\n * the number of bytes that can be read from the stream buffer before the stream\n * buffer would be empty.\n *\n * @param xStreamBuffer The handle of the stream buffer being queried.\n *\n * @return The number of bytes that can be read from the stream buffer before\n * the stream buffer would be empty.\n *\n * \\defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable\n * \\ingroup StreamBufferManagement\n */\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );\n</pre>\n *\n * A stream buffer's trigger level is the number of bytes that must be in the\n * stream buffer before a task that is blocked on the stream buffer to\n * wait for data is moved out of the blocked state.  For example, if a task is\n * blocked on a read of an empty stream buffer that has a trigger level of 1\n * then the task will be unblocked when a single byte is written to the buffer\n * or the task's block time expires.  As another example, if a task is blocked\n * on a read of an empty stream buffer that has a trigger level of 10 then the\n * task will not be unblocked until the stream buffer contains at least 10 bytes\n * or the task's block time expires.  If a reading task's block time expires\n * before the trigger level is reached then the task will still receive however\n * many bytes are actually available.  Setting a trigger level of 0 will result\n * in a trigger level of 1 being used.  It is not valid to specify a trigger\n * level that is greater than the buffer size.\n *\n * A trigger level is set when the stream buffer is created, and can be modified\n * using xStreamBufferSetTriggerLevel().\n *\n * @param xStreamBuffer The handle of the stream buffer being updated.\n *\n * @param xTriggerLevel The new trigger level for the stream buffer.\n *\n * @return If xTriggerLevel was less than or equal to the stream buffer's length\n * then the trigger level will be updated and pdTRUE is returned.  Otherwise\n * pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is sent to a message buffer or stream buffer.  If there was a task that\n * was blocked on the message or stream buffer waiting for data to arrive then\n * the sbSEND_COMPLETED() macro sends a notification to the task to remove it\n * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same\n * thing.  It is provided to enable application writers to implement their own\n * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer to which data was\n * written.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferSendCompletedFromISR().  If calling\n * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * stream_buffer.h\n *\n<pre>\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );\n</pre>\n *\n * For advanced users only.\n *\n * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when\n * data is read out of a message buffer or stream buffer.  If there was a task\n * that was blocked on the message or stream buffer waiting for data to arrive\n * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to\n * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()\n * does the same thing.  It is provided to enable application writers to\n * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT\n * ANY OTHER TIME.\n *\n * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for\n * additional information.\n *\n * @param xStreamBuffer The handle of the stream buffer from which data was\n * read.\n *\n * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be\n * initialised to pdFALSE before it is passed into\n * xStreamBufferReceiveCompletedFromISR().  If calling\n * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,\n * and the task has a priority above the priority of the currently running task,\n * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a\n * context switch should be performed before exiting the ISR.\n *\n * @return If a task was removed from the Blocked state then pdTRUE is returned.\n * Otherwise pdFALSE is returned.\n *\n * \\defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR\n * \\ingroup StreamBufferManagement\n */\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/* Functions below here are not part of the public API. */\nStreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;\n\nStreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   BaseType_t xIsMessageBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   uint8_t * const pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t\t\t\t   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tvoid vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;\n\tUBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n\tuint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;\n#endif\n\n#if defined( __cplusplus )\n}\n#endif\n\n#endif\t/* !defined( STREAM_BUFFER_H ) */\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/task.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef INC_TASK_H\n#define INC_TASK_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include task.h\"\n#endif\n\n#include \"list.h\"\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * MACROS AND DEFINITIONS\n *----------------------------------------------------------*/\n\n#define tskKERNEL_VERSION_NUMBER \"V10.3.1\"\n#define tskKERNEL_VERSION_MAJOR 10\n#define tskKERNEL_VERSION_MINOR 3\n#define tskKERNEL_VERSION_BUILD 1\n\n/* MPU region parameters passed in ulParameters\n * of MemoryRegion_t struct. */\n#define tskMPU_REGION_READ_ONLY\t\t\t( 1UL << 0UL )\n#define tskMPU_REGION_READ_WRITE\t\t( 1UL << 1UL )\n#define tskMPU_REGION_EXECUTE_NEVER\t\t( 1UL << 2UL )\n#define tskMPU_REGION_NORMAL_MEMORY\t\t( 1UL << 3UL )\n#define tskMPU_REGION_DEVICE_MEMORY\t\t( 1UL << 4UL )\n\n/**\n * task. h\n *\n * Type by which tasks are referenced.  For example, a call to xTaskCreate\n * returns (via a pointer parameter) an TaskHandle_t variable that can then\n * be used as a parameter to vTaskDelete to delete the task.\n *\n * \\defgroup TaskHandle_t TaskHandle_t\n * \\ingroup Tasks\n */\nstruct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tskTaskControlBlock* TaskHandle_t;\n\n/*\n * Defines the prototype to which the application task hook function must\n * conform.\n */\ntypedef BaseType_t (*TaskHookFunction_t)( void * );\n\n/* Task states returned by eTaskGetState. */\ntypedef enum\n{\n\teRunning = 0,\t/* A task is querying the state of itself, so must be running. */\n\teReady,\t\t\t/* The task being queried is in a read or pending ready list. */\n\teBlocked,\t\t/* The task being queried is in the Blocked state. */\n\teSuspended,\t\t/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */\n\teDeleted,\t\t/* The task being queried has been deleted, but its TCB has not yet been freed. */\n\teInvalid\t\t/* Used as an 'invalid state' value. */\n} eTaskState;\n\n/* Actions that can be performed when vTaskNotify() is called. */\ntypedef enum\n{\n\teNoAction = 0,\t\t\t\t/* Notify the task without updating its notify value. */\n\teSetBits,\t\t\t\t\t/* Set bits in the task's notification value. */\n\teIncrement,\t\t\t\t\t/* Increment the task's notification value. */\n\teSetValueWithOverwrite,\t\t/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */\n\teSetValueWithoutOverwrite\t/* Set the task's notification value if the previous value has been read by the task. */\n} eNotifyAction;\n\n/*\n * Used internally only.\n */\ntypedef struct xTIME_OUT\n{\n\tBaseType_t xOverflowCount;\n\tTickType_t xTimeOnEntering;\n} TimeOut_t;\n\n/*\n * Defines the memory ranges allocated to the task when an MPU is used.\n */\ntypedef struct xMEMORY_REGION\n{\n\tvoid *pvBaseAddress;\n\tuint32_t ulLengthInBytes;\n\tuint32_t ulParameters;\n} MemoryRegion_t;\n\n/*\n * Parameters required to create an MPU protected task.\n */\ntypedef struct xTASK_PARAMETERS\n{\n\tTaskFunction_t pvTaskCode;\n\tconst char * const pcName;\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tconfigSTACK_DEPTH_TYPE usStackDepth;\n\tvoid *pvParameters;\n\tUBaseType_t uxPriority;\n\tStackType_t *puxStackBuffer;\n\tMemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];\n\t#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t\tStaticTask_t * const pxTaskBuffer;\n\t#endif\n} TaskParameters_t;\n\n/* Used with the uxTaskGetSystemState() function to return the state of each task\nin the system. */\ntypedef struct xTASK_STATUS\n{\n\tTaskHandle_t xHandle;\t\t\t/* The handle of the task to which the rest of the information in the structure relates. */\n\tconst char *pcTaskName;\t\t\t/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tUBaseType_t xTaskNumber;\t\t/* A number unique to the task. */\n\teTaskState eCurrentState;\t\t/* The state in which the task existed when the structure was populated. */\n\tUBaseType_t uxCurrentPriority;\t/* The priority at which the task was running (may be inherited) when the structure was populated. */\n\tUBaseType_t uxBasePriority;\t\t/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */\n\tuint32_t ulRunTimeCounter;\t\t/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */\n\tStackType_t *pxStackBase;\t\t/* Points to the lowest address of the task's stack area. */\n\tconfigSTACK_DEPTH_TYPE usStackHighWaterMark;\t/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */\n} TaskStatus_t;\n\n/* Possible return values for eTaskConfirmSleepModeStatus(). */\ntypedef enum\n{\n\teAbortSleep = 0,\t\t/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */\n\teStandardSleep,\t\t\t/* Enter a sleep mode that will not last any longer than the expected idle time. */\n\teNoTasksWaitingTimeout\t/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */\n} eSleepModeStatus;\n\n/**\n * Defines the priority used by the idle task.  This must not be modified.\n *\n * \\ingroup TaskUtils\n */\n#define tskIDLE_PRIORITY\t\t\t( ( UBaseType_t ) 0U )\n\n/**\n * task. h\n *\n * Macro for forcing a context switch.\n *\n * \\defgroup taskYIELD taskYIELD\n * \\ingroup SchedulerControl\n */\n#define taskYIELD()\t\t\t\t\tportYIELD()\n\n/**\n * task. h\n *\n * Macro to mark the start of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskENTER_CRITICAL taskENTER_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskENTER_CRITICAL()\t\tportENTER_CRITICAL()\n#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()\n\n/**\n * task. h\n *\n * Macro to mark the end of a critical code region.  Preemptive context\n * switches cannot occur when in a critical region.\n *\n * NOTE: This may alter the stack (depending on the portable implementation)\n * so must be used with care!\n *\n * \\defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL\n * \\ingroup SchedulerControl\n */\n#define taskEXIT_CRITICAL()\t\t\tportEXIT_CRITICAL()\n#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )\n/**\n * task. h\n *\n * Macro to disable all maskable interrupts.\n *\n * \\defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskDISABLE_INTERRUPTS()\tportDISABLE_INTERRUPTS()\n\n/**\n * task. h\n *\n * Macro to enable microcontroller interrupts.\n *\n * \\defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS\n * \\ingroup SchedulerControl\n */\n#define taskENABLE_INTERRUPTS()\t\tportENABLE_INTERRUPTS()\n\n/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is\n0 to generate more optimal code when configASSERT() is defined as the constant\nis used in assert() statements. */\n#define taskSCHEDULER_SUSPENDED\t\t( ( BaseType_t ) 0 )\n#define taskSCHEDULER_NOT_STARTED\t( ( BaseType_t ) 1 )\n#define taskSCHEDULER_RUNNING\t\t( ( BaseType_t ) 2 )\n\n\n/*-----------------------------------------------------------\n * TASK CREATION API\n *----------------------------------------------------------*/\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreate(\n\t\t\t\t\t\t\t  TaskFunction_t pvTaskCode,\n\t\t\t\t\t\t\t  const char * const pcName,\n\t\t\t\t\t\t\t  configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\t  void *pvParameters,\n\t\t\t\t\t\t\t  UBaseType_t uxPriority,\n\t\t\t\t\t\t\t  TaskHandle_t *pvCreatedTask\n\t\t\t\t\t\t  );</pre>\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * See xTaskCreateStatic() for a version that does not use any dynamic memory\n * allocation.\n *\n * xTaskCreate() can only be used to create a task that has unrestricted\n * access to the entire microcontroller memory map.  Systems that include MPU\n * support can alternatively create an MPU constrained task using\n * xTaskCreateRestricted().\n *\n * @param pvTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default\n * is 16.\n *\n * @param usStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task should run.  Systems that\n * include MPU support can optionally create tasks in a privileged (system)\n * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For\n * example, to create a privileged task at priority 2 the uxPriority parameter\n * should be set to ( 2 | portPRIVILEGE_BIT ).\n *\n * @param pvCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n // Task to be created.\n void vTaskCode( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\t }\n }\n\n // Function that creates a task.\n void vOtherFunction( void )\n {\n static uint8_t ucParameterToPass;\n TaskHandle_t xHandle = NULL;\n\n\t // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass\n\t // must exist for the lifetime of the task, so in this case is declared static.  If it was just an\n\t // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time\n\t // the new task attempts to access it.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );\n\t configASSERT( xHandle );\n\n\t // Use the handle to delete the task.\n\t if( xHandle != NULL )\n\t {\n\t \tvTaskDelete( xHandle );\n\t }\n }\n   </pre>\n * \\defgroup xTaskCreate xTaskCreate\n * \\ingroup Tasks\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tBaseType_t xTaskCreate(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\tconst char * const pcName,\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\tconst configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,\n\t\t\t\t\t\t\t\t const char * const pcName,\n\t\t\t\t\t\t\t\t uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t void *pvParameters,\n\t\t\t\t\t\t\t\t UBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t StackType_t *pxStackBuffer,\n\t\t\t\t\t\t\t\t StaticTask_t *pxTaskBuffer );</pre>\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreate() then both blocks of memory are automatically dynamically\n * allocated inside the xTaskCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a task is created using\n * xTaskCreateStatic() then the application writer must provide the required\n * memory.  xTaskCreateStatic() therefore allows a task to be created without\n * using any dynamic memory allocation.\n *\n * @param pvTaskCode Pointer to the task entry function.  Tasks\n * must be implemented to never return (i.e. continuous loop).\n *\n * @param pcName A descriptive name for the task.  This is mainly used to\n * facilitate debugging.  The maximum length of the string is defined by\n * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.\n *\n * @param ulStackDepth The size of the task stack specified as the number of\n * variables the stack can hold - not the number of bytes.  For example, if\n * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes\n * will be allocated for stack storage.\n *\n * @param pvParameters Pointer that will be used as the parameter for the task\n * being created.\n *\n * @param uxPriority The priority at which the task will run.\n *\n * @param pxStackBuffer Must point to a StackType_t array that has at least\n * ulStackDepth indexes - the array will then be used as the task's stack,\n * removing the need for the stack to be allocated dynamically.\n *\n * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will\n * then be used to hold the task's data structures, removing the need for the\n * memory to be allocated dynamically.\n *\n * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will\n * be created and a handle to the created task is returned.  If either\n * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and\n * NULL is returned.\n *\n * Example usage:\n   <pre>\n\n    // Dimensions the buffer that the task being created will use as its stack.\n    // NOTE:  This is the number of words the stack will hold, not the number of\n    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,\n    // then 400 bytes (100 * 32-bits) will be allocated.\n    #define STACK_SIZE 200\n\n    // Structure that will hold the TCB of the task being created.\n    StaticTask_t xTaskBuffer;\n\n    // Buffer that the task being created will use as its stack.  Note this is\n    // an array of StackType_t variables.  The size of StackType_t is dependent on\n    // the RTOS port.\n    StackType_t xStack[ STACK_SIZE ];\n\n    // Function that implements the task being created.\n    void vTaskCode( void * pvParameters )\n    {\n        // The parameter value is expected to be 1 as 1 is passed in the\n        // pvParameters value in the call to xTaskCreateStatic().\n        configASSERT( ( uint32_t ) pvParameters == 1UL );\n\n        for( ;; )\n        {\n            // Task code goes here.\n        }\n    }\n\n    // Function that creates a task.\n    void vOtherFunction( void )\n    {\n        TaskHandle_t xHandle = NULL;\n\n        // Create the task without using any dynamic memory allocation.\n        xHandle = xTaskCreateStatic(\n                      vTaskCode,       // Function that implements the task.\n                      \"NAME\",          // Text name for the task.\n                      STACK_SIZE,      // Stack size in words, not bytes.\n                      ( void * ) 1,    // Parameter passed into the task.\n                      tskIDLE_PRIORITY,// Priority at which the task is created.\n                      xStack,          // Array to use as the task's stack.\n                      &xTaskBuffer );  // Variable to hold the task's data structure.\n\n        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have\n        // been created, and xHandle will be the task's handle.  Use the handle\n        // to suspend the task.\n        vTaskSuspend( xHandle );\n    }\n   </pre>\n * \\defgroup xTaskCreateStatic xTaskCreateStatic\n * \\ingroup Tasks\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tTaskHandle_t xTaskCreateStatic(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tStackType_t * const puxStackBuffer,\n\t\t\t\t\t\t\t\t\tStaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>\n *\n * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestricted() should only be used in systems that include an MPU\n * implementation.\n *\n * Create a new task and add it to the list of tasks that are ready to run.\n * The function parameters define the memory regions and associated access\n * permissions allocated to the task.\n *\n * See xTaskCreateRestrictedStatic() for a version that does not use any\n * dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n// Create an TaskParameters_t structure that defines the task to be created.\nstatic const TaskParameters_t xCheckTaskParameters =\n{\n\tvATask,\t\t// pvTaskCode - the function that implements the task.\n\t\"ATask\",\t// pcName - just a text name for the task to assist debugging.\n\t100,\t\t// usStackDepth\t- the stack size DEFINED IN WORDS.\n\tNULL,\t\t// pvParameters - passed into the task function as the function parameters.\n\t( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n\tcStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n\n\t// xRegions - Allocate up to three separate memory regions for access by\n\t// the task, with appropriate access permissions.  Different processors have\n\t// different memory alignment requirements - refer to the FreeRTOS documentation\n\t// for full information.\n\t{\n\t\t// Base address\t\t\t\t\tLength\tParameters\n\t\t{ cReadWriteArray,\t\t\t\t32,\t\tportMPU_REGION_READ_WRITE },\n\t\t{ cReadOnlyArray,\t\t\t\t32,\t\tportMPU_REGION_READ_ONLY },\n\t\t{ cPrivilegedOnlyAccessArray,\t128,\tportMPU_REGION_PRIVILEGED_READ_WRITE }\n\t}\n};\n\nint main( void )\n{\nTaskHandle_t xHandle;\n\n\t// Create a task from the const structure defined above.  The task handle\n\t// is requested (the second parameter is not NULL) but in this case just for\n\t// demonstration purposes as its not actually used.\n\txTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\n\n\t// Start the scheduler.\n\tvTaskStartScheduler();\n\n\t// Will only get here if there was insufficient memory to create the idle\n\t// and/or timer task.\n\tfor( ;; );\n}\n   </pre>\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\n * \\ingroup Tasks\n */\n#if( portUSING_MPU_WRAPPERS == 1 )\n\tBaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>\n *\n * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.\n *\n * xTaskCreateRestrictedStatic() should only be used in systems that include an\n * MPU implementation.\n *\n * Internally, within the FreeRTOS implementation, tasks use two blocks of\n * memory.  The first block is used to hold the task's data structures.  The\n * second block is used by the task as its stack.  If a task is created using\n * xTaskCreateRestricted() then the stack is provided by the application writer,\n * and the memory used to hold the task's data structure is automatically\n * dynamically allocated inside the xTaskCreateRestricted() function.  If a task\n * is created using xTaskCreateRestrictedStatic() then the application writer\n * must provide the memory used to hold the task's data structures too.\n * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be\n * created without using any dynamic memory allocation.\n *\n * @param pxTaskDefinition Pointer to a structure that contains a member\n * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API\n * documentation) plus an optional stack buffer and the memory region\n * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure\n * contains an additional member, which is used to point to a variable of type\n * StaticTask_t - which is then used to hold the task's data structure.\n *\n * @param pxCreatedTask Used to pass back a handle by which the created task\n * can be referenced.\n *\n * @return pdPASS if the task was successfully created and added to a ready\n * list, otherwise an error code defined in the file projdefs.h\n *\n * Example usage:\n   <pre>\n// Create an TaskParameters_t structure that defines the task to be created.\n// The StaticTask_t variable is only included in the structure when\n// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can\n// be used to force the variable into the RTOS kernel's privileged data area.\nstatic PRIVILEGED_DATA StaticTask_t xTaskBuffer;\nstatic const TaskParameters_t xCheckTaskParameters =\n{\n\tvATask,\t\t// pvTaskCode - the function that implements the task.\n\t\"ATask\",\t// pcName - just a text name for the task to assist debugging.\n\t100,\t\t// usStackDepth\t- the stack size DEFINED IN WORDS.\n\tNULL,\t\t// pvParameters - passed into the task function as the function parameters.\n\t( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.\n\tcStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.\n\n\t// xRegions - Allocate up to three separate memory regions for access by\n\t// the task, with appropriate access permissions.  Different processors have\n\t// different memory alignment requirements - refer to the FreeRTOS documentation\n\t// for full information.\n\t{\n\t\t// Base address\t\t\t\t\tLength\tParameters\n\t\t{ cReadWriteArray,\t\t\t\t32,\t\tportMPU_REGION_READ_WRITE },\n\t\t{ cReadOnlyArray,\t\t\t\t32,\t\tportMPU_REGION_READ_ONLY },\n\t\t{ cPrivilegedOnlyAccessArray,\t128,\tportMPU_REGION_PRIVILEGED_READ_WRITE }\n\t}\n\n\t&xTaskBuffer; // Holds the task's data structure.\n};\n\nint main( void )\n{\nTaskHandle_t xHandle;\n\n\t// Create a task from the const structure defined above.  The task handle\n\t// is requested (the second parameter is not NULL) but in this case just for\n\t// demonstration purposes as its not actually used.\n\txTaskCreateRestricted( &xRegTest1Parameters, &xHandle );\n\n\t// Start the scheduler.\n\tvTaskStartScheduler();\n\n\t// Will only get here if there was insufficient memory to create the idle\n\t// and/or timer task.\n\tfor( ;; );\n}\n   </pre>\n * \\defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic\n * \\ingroup Tasks\n */\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\tBaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * task. h\n *<pre>\n void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>\n *\n * Memory regions are assigned to a restricted task when the task is created by\n * a call to xTaskCreateRestricted().  These regions can be redefined using\n * vTaskAllocateMPURegions().\n *\n * @param xTask The handle of the task being updated.\n *\n * @param xRegions A pointer to an MemoryRegion_t structure that contains the\n * new memory region definitions.\n *\n * Example usage:\n   <pre>\n// Define an array of MemoryRegion_t structures that configures an MPU region\n// allowing read/write access for 1024 bytes starting at the beginning of the\n// ucOneKByte array.  The other two of the maximum 3 definable regions are\n// unused so set to zero.\nstatic const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =\n{\n\t// Base address\t\tLength\t\tParameters\n\t{ ucOneKByte,\t\t1024,\t\tportMPU_REGION_READ_WRITE },\n\t{ 0,\t\t\t\t0,\t\t\t0 },\n\t{ 0,\t\t\t\t0,\t\t\t0 }\n};\n\nvoid vATask( void *pvParameters )\n{\n\t// This task was created such that it has access to certain regions of\n\t// memory as defined by the MPU configuration.  At some point it is\n\t// desired that these MPU regions are replaced with that defined in the\n\t// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()\n\t// for this purpose.  NULL is used as the task handle to indicate that this\n\t// function should modify the MPU regions of the calling task.\n\tvTaskAllocateMPURegions( NULL, xAltRegions );\n\n\t// Now the task can continue its function, but from this point on can only\n\t// access its stack and the ucOneKByte array (unless any other statically\n\t// defined or shared regions have been declared elsewhere).\n}\n   </pre>\n * \\defgroup xTaskCreateRestricted xTaskCreateRestricted\n * \\ingroup Tasks\n */\nvoid vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Remove a task from the RTOS real time kernel's management.  The task being\n * deleted will be removed from all ready, blocked, suspended and event lists.\n *\n * NOTE:  The idle task is responsible for freeing the kernel allocated\n * memory from tasks that have been deleted.  It is therefore important that\n * the idle task is not starved of microcontroller processing time if your\n * application makes any calls to vTaskDelete ().  Memory allocated by the\n * task code is not automatically freed, and should be freed before the task\n * is deleted.\n *\n * See the demo application file death.c for sample code that utilises\n * vTaskDelete ().\n *\n * @param xTask The handle of the task to be deleted.  Passing NULL will\n * cause the calling task to be deleted.\n *\n * Example usage:\n   <pre>\n void vOtherFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create the task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // Use the handle to delete the task.\n\t vTaskDelete( xHandle );\n }\n   </pre>\n * \\defgroup vTaskDelete vTaskDelete\n * \\ingroup Tasks\n */\nvoid vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * TASK CONTROL API\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>\n *\n * Delay a task for a given number of ticks.  The actual time that the\n * task remains blocked depends on the tick rate.  The constant\n * portTICK_PERIOD_MS can be used to calculate real time from the tick\n * rate - with the resolution of one tick period.\n *\n * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n *\n * vTaskDelay() specifies a time at which the task wishes to unblock relative to\n * the time at which vTaskDelay() is called.  For example, specifying a block\n * period of 100 ticks will cause the task to unblock 100 ticks after\n * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method\n * of controlling the frequency of a periodic task as the path taken through the\n * code, as well as other task and interrupt activity, will effect the frequency\n * at which vTaskDelay() gets called and therefore the time at which the task\n * next executes.  See vTaskDelayUntil() for an alternative API function designed\n * to facilitate fixed frequency execution.  It does this by specifying an\n * absolute time (rather than a relative time) at which the calling task should\n * unblock.\n *\n * @param xTicksToDelay The amount of time, in tick periods, that\n * the calling task should block.\n *\n * Example usage:\n\n void vTaskFunction( void * pvParameters )\n {\n // Block for 500ms.\n const TickType_t xDelay = 500 / portTICK_PERIOD_MS;\n\n\t for( ;; )\n\t {\n\t\t // Simply toggle the LED every 500ms, blocking between each toggle.\n\t\t vToggleLED();\n\t\t vTaskDelay( xDelay );\n\t }\n }\n\n * \\defgroup vTaskDelay vTaskDelay\n * \\ingroup TaskCtrl\n */\nvoid vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>\n *\n * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Delay a task until a specified time.  This function can be used by periodic\n * tasks to ensure a constant execution frequency.\n *\n * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will\n * cause a task to block for the specified number of ticks from the time vTaskDelay () is\n * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed\n * execution frequency as the time between a task starting to execute and that task\n * calling vTaskDelay () may not be fixed [the task may take a different path though the\n * code between calls, or may get interrupted or preempted a different number of times\n * each time it executes].\n *\n * Whereas vTaskDelay () specifies a wake time relative to the time at which the function\n * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to\n * unblock.\n *\n * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick\n * rate - with the resolution of one tick period.\n *\n * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the\n * task was last unblocked.  The variable must be initialised with the current time\n * prior to its first use (see the example below).  Following this the variable is\n * automatically updated within vTaskDelayUntil ().\n *\n * @param xTimeIncrement The cycle time period.  The task will be unblocked at\n * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the\n * same xTimeIncrement parameter value will cause the task to execute with\n * a fixed interface period.\n *\n * Example usage:\n   <pre>\n // Perform an action every 10 ticks.\n void vTaskFunction( void * pvParameters )\n {\n TickType_t xLastWakeTime;\n const TickType_t xFrequency = 10;\n\n\t // Initialise the xLastWakeTime variable with the current time.\n\t xLastWakeTime = xTaskGetTickCount ();\n\t for( ;; )\n\t {\n\t\t // Wait for the next cycle.\n\t\t vTaskDelayUntil( &xLastWakeTime, xFrequency );\n\n\t\t // Perform action here.\n\t }\n }\n   </pre>\n * \\defgroup vTaskDelayUntil vTaskDelayUntil\n * \\ingroup TaskCtrl\n */\nvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this\n * function to be available.\n *\n * A task will enter the Blocked state when it is waiting for an event.  The\n * event it is waiting for can be a temporal event (waiting for a time), such\n * as when vTaskDelay() is called, or an event on an object, such as when\n * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task\n * that is in the Blocked state is used in a call to xTaskAbortDelay() then the\n * task will leave the Blocked state, and return from whichever function call\n * placed the task into the Blocked state.\n *\n * There is no 'FromISR' version of this function as an interrupt would need to\n * know which object a task was blocked on in order to know which actions to\n * take.  For example, if the task was blocked on a queue the interrupt handler\n * would then need to know if the queue was locked.\n *\n * @param xTask The handle of the task to remove from the Blocked state.\n *\n * @return If the task referenced by xTask was not in the Blocked state then\n * pdFAIL is returned.  Otherwise pdPASS is returned.\n *\n * \\defgroup xTaskAbortDelay xTaskAbortDelay\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );</pre>\n *\n * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the priority of any task.\n *\n * @param xTask Handle of the task to be queried.  Passing a NULL\n * handle results in the priority of the calling task being returned.\n *\n * @return The priority of xTask.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to obtain the priority of the created task.\n\t // It was created with tskIDLE_PRIORITY, but may have changed\n\t // it itself.\n\t if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )\n\t {\n\t\t // The task has changed it's priority.\n\t }\n\n\t // ...\n\n\t // Is our priority higher than the created task?\n\t if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )\n\t {\n\t\t // Our priority (obtained using NULL handle) is higher.\n\t }\n }\n   </pre>\n * \\defgroup uxTaskPriorityGet uxTaskPriorityGet\n * \\ingroup TaskCtrl\n */\nUBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );</pre>\n *\n * A version of uxTaskPriorityGet() that can be used from an ISR.\n */\nUBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>\n *\n * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Obtain the state of any task.  States are encoded by the eTaskState\n * enumerated type.\n *\n * @param xTask Handle of the task to be queried.\n *\n * @return The state of xTask at the time the function was called.  Note the\n * state of the task might change between the function being called, and the\n * functions return value being tested by the calling task.\n */\neTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>\n *\n * configUSE_TRACE_FACILITY must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * Populates a TaskStatus_t structure with information about a task.\n *\n * @param xTask Handle of the task being queried.  If xTask is NULL then\n * information will be returned about the calling task.\n *\n * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be\n * filled with information about the task referenced by the handle passed using\n * the xTask parameter.\n *\n * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report\n * the stack high water mark of the task being queried.  Calculating the stack\n * high water mark takes a relatively long time, and can make the system\n * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to\n * allow the high water mark checking to be skipped.  The high watermark value\n * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is\n * not set to pdFALSE;\n *\n * @param eState The TaskStatus_t structure contains a member to report the\n * state of the task being queried.  Obtaining the task state is not as fast as\n * a simple assignment - so the eState parameter is provided to allow the state\n * information to be omitted from the TaskStatus_t structure.  To obtain state\n * information then set eState to eInvalid - otherwise the value passed in\n * eState will be reported as the task state in the TaskStatus_t structure.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n TaskStatus_t xTaskDetails;\n\n    // Obtain the handle of a task from its name.\n    xHandle = xTaskGetHandle( \"Task_Name\" );\n\n    // Check the handle is not NULL.\n    configASSERT( xHandle );\n\n    // Use the handle to obtain further information about the task.\n    vTaskGetInfo( xHandle,\n                  &xTaskDetails,\n                  pdTRUE, // Include the high water mark in xTaskDetails.\n                  eInvalid ); // Include the task state in xTaskDetails.\n }\n   </pre>\n * \\defgroup vTaskGetInfo vTaskGetInfo\n * \\ingroup TaskCtrl\n */\nvoid vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>\n *\n * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Set the priority of any task.\n *\n * A context switch will occur before the function returns if the priority\n * being set is higher than the currently executing task.\n *\n * @param xTask Handle to the task for which the priority is being set.\n * Passing a NULL handle results in the priority of the calling task being set.\n *\n * @param uxNewPriority The priority to which the task will be set.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to raise the priority of the created task.\n\t vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );\n\n\t // ...\n\n\t // Use a NULL handle to raise our priority to the same value.\n\t vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );\n }\n   </pre>\n * \\defgroup vTaskPrioritySet vTaskPrioritySet\n * \\ingroup TaskCtrl\n */\nvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Suspend any task.  When suspended a task will never get any microcontroller\n * processing time, no matter what its priority.\n *\n * Calls to vTaskSuspend are not accumulative -\n * i.e. calling vTaskSuspend () twice on the same task still only requires one\n * call to vTaskResume () to ready the suspended task.\n *\n * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL\n * handle will cause the calling task to be suspended.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to suspend the created task.\n\t vTaskSuspend( xHandle );\n\n\t // ...\n\n\t // The created task will not run during this period, unless\n\t // another task calls vTaskResume( xHandle ).\n\n\t //...\n\n\n\t // Suspend ourselves.\n\t vTaskSuspend( NULL );\n\n\t // We cannot get here unless another task calls vTaskResume\n\t // with our handle as the parameter.\n }\n   </pre>\n * \\defgroup vTaskSuspend vTaskSuspend\n * \\ingroup TaskCtrl\n */\nvoid vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>\n *\n * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.\n * See the configuration section for more information.\n *\n * Resumes a suspended task.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * vTaskResume ().\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n TaskHandle_t xHandle;\n\n\t // Create a task, storing the handle.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );\n\n\t // ...\n\n\t // Use the handle to suspend the created task.\n\t vTaskSuspend( xHandle );\n\n\t // ...\n\n\t // The created task will not run during this period, unless\n\t // another task calls vTaskResume( xHandle ).\n\n\t //...\n\n\n\t // Resume the suspended task ourselves.\n\t vTaskResume( xHandle );\n\n\t // The created task will once again get microcontroller processing\n\t // time in accordance with its priority within the system.\n }\n   </pre>\n * \\defgroup vTaskResume vTaskResume\n * \\ingroup TaskCtrl\n */\nvoid vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>\n *\n * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be\n * available.  See the configuration section for more information.\n *\n * An implementation of vTaskResume() that can be called from within an ISR.\n *\n * A task that has been suspended by one or more calls to vTaskSuspend ()\n * will be made available for running again by a single call to\n * xTaskResumeFromISR ().\n *\n * xTaskResumeFromISR() should not be used to synchronise a task with an\n * interrupt if there is a chance that the interrupt could arrive prior to the\n * task being suspended - as this can lead to interrupts being missed. Use of a\n * semaphore as a synchronisation mechanism would avoid this eventuality.\n *\n * @param xTaskToResume Handle to the task being readied.\n *\n * @return pdTRUE if resuming the task should result in a context switch,\n * otherwise pdFALSE. This is used by the ISR to determine if a context switch\n * may be required following the ISR.\n *\n * \\defgroup vTaskResumeFromISR vTaskResumeFromISR\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * SCHEDULER CONTROL\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <pre>void vTaskStartScheduler( void );</pre>\n *\n * Starts the real time kernel tick processing.  After calling the kernel\n * has control over which tasks are executed and when.\n *\n * See the demo application file main.c for an example of creating\n * tasks and starting the kernel.\n *\n * Example usage:\n   <pre>\n void vAFunction( void )\n {\n\t // Create at least one task before starting the kernel.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n\n\t // Start the real time kernel with preemption.\n\t vTaskStartScheduler ();\n\n\t // Will not get here unless a task calls vTaskEndScheduler ()\n }\n   </pre>\n *\n * \\defgroup vTaskStartScheduler vTaskStartScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskEndScheduler( void );</pre>\n *\n * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC\n * in place of DOS, implements this function.\n *\n * Stops the real time kernel tick.  All created tasks will be automatically\n * deleted and multitasking (either preemptive or cooperative) will\n * stop.  Execution then resumes from the point where vTaskStartScheduler ()\n * was called, as if vTaskStartScheduler () had just returned.\n *\n * See the demo application file main. c in the demo/PC directory for an\n * example that uses vTaskEndScheduler ().\n *\n * vTaskEndScheduler () requires an exit function to be defined within the\n * portable layer (see vPortEndScheduler () in port. c for the PC port).  This\n * performs hardware specific operations such as stopping the kernel tick.\n *\n * vTaskEndScheduler () will cause all of the resources allocated by the\n * kernel to be freed - but will not free resources allocated by application\n * tasks.\n *\n * Example usage:\n   <pre>\n void vTaskCode( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // At some point we want to end the real time kernel processing\n\t\t // so call ...\n\t\t vTaskEndScheduler ();\n\t }\n }\n\n void vAFunction( void )\n {\n\t // Create at least one task before starting the kernel.\n\t xTaskCreate( vTaskCode, \"NAME\", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );\n\n\t // Start the real time kernel with preemption.\n\t vTaskStartScheduler ();\n\n\t // Will only get here when the vTaskCode () task has called\n\t // vTaskEndScheduler ().  When we get here we are back to single task\n\t // execution.\n }\n   </pre>\n *\n * \\defgroup vTaskEndScheduler vTaskEndScheduler\n * \\ingroup SchedulerControl\n */\nvoid vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>void vTaskSuspendAll( void );</pre>\n *\n * Suspends the scheduler without disabling interrupts.  Context switches will\n * not occur while the scheduler is suspended.\n *\n * After calling vTaskSuspendAll () the calling task will continue to execute\n * without risk of being swapped out until a call to xTaskResumeAll () has been\n * made.\n *\n * API functions that have the potential to cause a context switch (for example,\n * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler\n * is suspended.\n *\n * Example usage:\n   <pre>\n void vTask1( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // ...\n\n\t\t // At some point the task wants to perform a long operation during\n\t\t // which it does not want to get swapped out.  It cannot use\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n\t\t // operation may cause interrupts to be missed - including the\n\t\t // ticks.\n\n\t\t // Prevent the real time kernel swapping out the task.\n\t\t vTaskSuspendAll ();\n\n\t\t // Perform the operation here.  There is no need to use critical\n\t\t // sections as we have all the microcontroller processing time.\n\t\t // During this time interrupts will still operate and the kernel\n\t\t // tick count will be maintained.\n\n\t\t // ...\n\n\t\t // The operation is complete.  Restart the kernel.\n\t\t xTaskResumeAll ();\n\t }\n }\n   </pre>\n * \\defgroup vTaskSuspendAll vTaskSuspendAll\n * \\ingroup SchedulerControl\n */\nvoid vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <pre>BaseType_t xTaskResumeAll( void );</pre>\n *\n * Resumes scheduler activity after it was suspended by a call to\n * vTaskSuspendAll().\n *\n * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks\n * that were previously suspended by a call to vTaskSuspend().\n *\n * @return If resuming the scheduler caused a context switch then pdTRUE is\n *\t\t  returned, otherwise pdFALSE is returned.\n *\n * Example usage:\n   <pre>\n void vTask1( void * pvParameters )\n {\n\t for( ;; )\n\t {\n\t\t // Task code goes here.\n\n\t\t // ...\n\n\t\t // At some point the task wants to perform a long operation during\n\t\t // which it does not want to get swapped out.  It cannot use\n\t\t // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the\n\t\t // operation may cause interrupts to be missed - including the\n\t\t // ticks.\n\n\t\t // Prevent the real time kernel swapping out the task.\n\t\t vTaskSuspendAll ();\n\n\t\t // Perform the operation here.  There is no need to use critical\n\t\t // sections as we have all the microcontroller processing time.\n\t\t // During this time interrupts will still operate and the real\n\t\t // time kernel tick count will be maintained.\n\n\t\t // ...\n\n\t\t // The operation is complete.  Restart the kernel.  We want to force\n\t\t // a context switch - but there is no point if resuming the scheduler\n\t\t // caused a context switch already.\n\t\t if( !xTaskResumeAll () )\n\t\t {\n\t\t\t  taskYIELD ();\n\t\t }\n\t }\n }\n   </pre>\n * \\defgroup xTaskResumeAll xTaskResumeAll\n * \\ingroup SchedulerControl\n */\nBaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * TASK UTILITIES\n *----------------------------------------------------------*/\n\n/**\n * task. h\n * <PRE>TickType_t xTaskGetTickCount( void );</PRE>\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * \\defgroup xTaskGetTickCount xTaskGetTickCount\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>\n *\n * @return The count of ticks since vTaskStartScheduler was called.\n *\n * This is a version of xTaskGetTickCount() that is safe to be called from an\n * ISR - provided that TickType_t is the natural word size of the\n * microcontroller being used or interrupt nesting is either not supported or\n * not being used.\n *\n * \\defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR\n * \\ingroup TaskUtils\n */\nTickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>\n *\n * @return The number of tasks that the real time kernel is currently managing.\n * This includes all ready, blocked and suspended tasks.  A task that\n * has been deleted but not yet freed by the idle task will also be\n * included in the count.\n *\n * \\defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks\n * \\ingroup TaskUtils\n */\nUBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>\n *\n * @return The text (human readable) name of the task referenced by the handle\n * xTaskToQuery.  A task can query its own name by either passing in its own\n * handle, or by setting xTaskToQuery to NULL.\n *\n * \\defgroup pcTaskGetName pcTaskGetName\n * \\ingroup TaskUtils\n */\nchar *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>\n *\n * NOTE:  This function takes a relatively long time to complete and should be\n * used sparingly.\n *\n * @return The handle of the task that has the human readable name pcNameToQuery.\n * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle\n * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.\n *\n * \\defgroup pcTaskGetHandle pcTaskGetHandle\n * \\ingroup TaskUtils\n */\nTaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task.h\n * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>\n *\n * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>\n *\n * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for\n * this function to be available.\n *\n * Returns the high water mark of the stack associated with xTask.  That is,\n * the minimum free stack space there has been (in words, so on a 32 bit machine\n * a value of 1 means 4 bytes) since the task started.  The smaller the returned\n * number the closer the task has come to overflowing its stack.\n *\n * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n * user to determine the return type.  It gets around the problem of the value\n * overflowing on 8-bit types without breaking backward compatibility for\n * applications that expect an 8-bit return type.\n *\n * @param xTask Handle of the task associated with the stack to be checked.\n * Set xTask to NULL to check the stack of the calling task.\n *\n * @return The smallest amount of free stack space there has been (in words, so\n * actual spaces on the stack rather than bytes) since the task referenced by\n * xTask was created.\n */\nconfigSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/* When using trace macros it is sometimes necessary to include task.h before\nFreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,\nso the following two prototypes will cause a compilation error.  This can be\nfixed by simply guarding against the inclusion of these two prototypes unless\nthey are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration\nconstant. */\n#ifdef configUSE_APPLICATION_TASK_TAG\n\t#if configUSE_APPLICATION_TASK_TAG == 1\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>\n\t\t *\n\t\t * Sets pxHookFunction to be the task hook function used by the task xTask.\n\t\t * Passing xTask as NULL has the effect of setting the calling tasks hook\n\t\t * function.\n\t\t */\n\t\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;\n\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>\n\t\t *\n\t\t * Returns the pxHookFunction value assigned to the task xTask.  Do not\n\t\t * call from an interrupt service routine - call\n\t\t * xTaskGetApplicationTaskTagFromISR() instead.\n\t\t */\n\t\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n\t\t/**\n\t\t * task.h\n\t\t * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>\n\t\t *\n\t\t * Returns the pxHookFunction value assigned to the task xTask.  Can\n\t\t * be called from an interrupt service routine.\n\t\t */\n\t\tTaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\t#endif /* configUSE_APPLICATION_TASK_TAG ==1 */\n#endif /* ifdef configUSE_APPLICATION_TASK_TAG */\n\n#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\n\t/* Each task contains an array of pointers that is dimensioned by the\n\tconfigNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The\n\tkernel does not use the pointers itself, so the application writer can use\n\tthe pointers for any purpose they wish.  The following two functions are\n\tused to set and query a pointer respectively. */\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/**\n * task.h\n * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>\n *\n * Calls the hook function associated with xTask.  Passing xTask as NULL has\n * the effect of calling the Running tasks (the calling task) hook function.\n *\n * pvParameter is passed to the hook function for the task to interpret as it\n * wants.  The return value is the value returned by the task hook function\n * registered by the user.\n */\nBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;\n\n/**\n * xTaskGetIdleTaskHandle() is only available if\n * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.\n *\n * Simply returns the handle of the idle task.  It is not valid to call\n * xTaskGetIdleTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for\n * uxTaskGetSystemState() to be available.\n *\n * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in\n * the system.  TaskStatus_t structures contain, among other things, members\n * for the task handle, task name, task priority, task state, and total amount\n * of run time consumed by the task.  See the TaskStatus_t structure\n * definition in this file for the full member list.\n *\n * NOTE:  This function is intended for debugging use only as its use results in\n * the scheduler remaining suspended for an extended period.\n *\n * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.\n * The array must contain at least one TaskStatus_t structure for each task\n * that is under the control of the RTOS.  The number of tasks under the control\n * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.\n *\n * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray\n * parameter.  The size is specified as the number of indexes in the array, or\n * the number of TaskStatus_t structures contained in the array, not by the\n * number of bytes in the array.\n *\n * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in\n * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the\n * total run time (as defined by the run time stats clock, see\n * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.\n * pulTotalRunTime can be set to NULL to omit the total run time information.\n *\n * @return The number of TaskStatus_t structures that were populated by\n * uxTaskGetSystemState().  This should equal the number returned by the\n * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed\n * in the uxArraySize parameter was too small.\n *\n * Example usage:\n   <pre>\n    // This example demonstrates how a human readable table of run time stats\n\t// information is generated from raw data provided by uxTaskGetSystemState().\n\t// The human readable table is written to pcWriteBuffer\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tvolatile UBaseType_t uxArraySize, x;\n\tuint32_t ulTotalRunTime, ulStatsAsPercentage;\n\n\t\t// Make sure the write buffer does not contain a string.\n\t\t*pcWriteBuffer = 0x00;\n\n\t\t// Take a snapshot of the number of tasks in case it changes while this\n\t\t// function is executing.\n\t\tuxArraySize = uxTaskGetNumberOfTasks();\n\n\t\t// Allocate a TaskStatus_t structure for each task.  An array could be\n\t\t// allocated statically at compile time.\n\t\tpxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t// Generate raw status information about each task.\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );\n\n\t\t\t// For percentage calculations.\n\t\t\tulTotalRunTime /= 100UL;\n\n\t\t\t// Avoid divide by zero errors.\n\t\t\tif( ulTotalRunTime > 0 )\n\t\t\t{\n\t\t\t\t// For each populated position in the pxTaskStatusArray array,\n\t\t\t\t// format the raw data as human readable ASCII data\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t\t{\n\t\t\t\t\t// What percentage of the total run time has the task used?\n\t\t\t\t\t// This will always be rounded down to the nearest integer.\n\t\t\t\t\t// ulTotalRunTimeDiv100 has already been divided by 100.\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;\n\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t// If the percentage is zero here then the task has\n\t\t\t\t\t\t// consumed less than 1% of the total run time.\n\t\t\t\t\t\tsprintf( pcWriteBuffer, \"%s\\t\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );\n\t\t\t\t\t}\n\n\t\t\t\t\tpcWriteBuffer += strlen( ( char * ) pcWriteBuffer );\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t// The array is no longer needed, free the memory it consumes.\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t}\n\t</pre>\n */\nUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>\n *\n * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must\n * both be defined as 1 for this function to be available.  See the\n * configuration section of the FreeRTOS.org website for more information.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Lists all the current tasks, along with their current state and stack\n * usage high water mark.\n *\n * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or\n * suspended ('S').\n *\n * PLEASE NOTE:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays task\n * names, states and stack usage.\n *\n * vTaskList() has a dependency on the sprintf() C library function that might\n * bloat the code size, use a lot of stack, and provide different results on\n * different platforms.  An alternative, tiny, third party, and limited\n * functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState()\n * directly to get access to raw stats data, rather than indirectly through a\n * call to vTaskList().\n *\n * @param pcWriteBuffer A buffer into which the above mentioned details\n * will be written, in ASCII form.  This buffer is assumed to be large\n * enough to contain the generated report.  Approximately 40 bytes per\n * task should be sufficient.\n *\n * \\defgroup vTaskList vTaskList\n * \\ingroup TaskUtils\n */\nvoid vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * task. h\n * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>\n *\n * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\n * must both be defined as 1 for this function to be available.  The application\n * must also then provide definitions for\n * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n * to configure a peripheral timer/counter and return the timers current count\n * value respectively.  The counter should be at least 10 times the frequency of\n * the tick count.\n *\n * NOTE 1: This function will disable interrupts for its duration.  It is\n * not intended for normal application runtime use but as a debug aid.\n *\n * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n * accumulated execution time being stored for each task.  The resolution\n * of the accumulated time value depends on the frequency of the timer\n * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n * Calling vTaskGetRunTimeStats() writes the total execution time of each\n * task into a buffer, both as an absolute count value and as a percentage\n * of the total system execution time.\n *\n * NOTE 2:\n *\n * This function is provided for convenience only, and is used by many of the\n * demo applications.  Do not consider it to be part of the scheduler.\n *\n * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the\n * uxTaskGetSystemState() output into a human readable table that displays the\n * amount of time each task has spent in the Running state in both absolute and\n * percentage terms.\n *\n * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function\n * that might bloat the code size, use a lot of stack, and provide different\n * results on different platforms.  An alternative, tiny, third party, and\n * limited functionality implementation of sprintf() is provided in many of the\n * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note\n * printf-stdarg.c does not provide a full snprintf() implementation!).\n *\n * It is recommended that production systems call uxTaskGetSystemState() directly\n * to get access to raw stats data, rather than indirectly through a call to\n * vTaskGetRunTimeStats().\n *\n * @param pcWriteBuffer A buffer into which the execution times will be\n * written, in ASCII form.  This buffer is assumed to be large enough to\n * contain the generated report.  Approximately 40 bytes per task should\n * be sufficient.\n *\n * \\defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats\n * \\ingroup TaskUtils\n */\nvoid vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n* task. h\n* <PRE>uint32_t ulTaskGetIdleRunTimeCounter( void );</PRE>\n*\n* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS\n* must both be defined as 1 for this function to be available.  The application\n* must also then provide definitions for\n* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()\n* to configure a peripheral timer/counter and return the timers current count\n* value respectively.  The counter should be at least 10 times the frequency of\n* the tick count.\n*\n* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total\n* accumulated execution time being stored for each task.  The resolution\n* of the accumulated time value depends on the frequency of the timer\n* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.\n* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total\n* execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()\n* returns the total execution time of just the idle task.\n*\n* @return The total run time of the idle task.  This is the amount of time the\n* idle task has actually been executing.  The unit of time is dependent on the\n* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and\n* portGET_RUN_TIME_COUNTER_VALUE() macros.\n*\n* \\defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter\n* \\ingroup TaskUtils\n*/\nuint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()\n * always returns pdPASS in this case.\n *\n * eIncrement -\n * The task's notification value is incremented.  ulValue is not used and\n * xTaskNotify() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The task's notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification (the\n * task already had a notification pending).  xTaskNotify() always returns\n * pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending then\n * the task's notification value is set to ulValue and xTaskNotify() will\n * return pdPASS.  If the task being notified already had a notification\n * pending then no action is performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification without its notification value being\n * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in\n * this case.\n *\n *  pulPreviousNotificationValue -\n *  Can be used to pass out the subject task's notification value before any\n *  bits are modified by the notify function.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotify xTaskNotify\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;\n#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )\n#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * A version of xTaskNotify() that can be used from an interrupt service routine\n * (ISR).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param ulValue Data that can be sent with the notification.  How the data is\n * used depends on the value of the eAction parameter.\n *\n * @param eAction Specifies how the notification updates the task's notification\n * value, if at all.  Valid values for eAction are as follows:\n *\n * eSetBits -\n * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()\n * always returns pdPASS in this case.\n *\n * eIncrement -\n * The task's notification value is incremented.  ulValue is not used and\n * xTaskNotify() always returns pdPASS in this case.\n *\n * eSetValueWithOverwrite -\n * The task's notification value is set to the value of ulValue, even if the\n * task being notified had not yet processed the previous notification (the\n * task already had a notification pending).  xTaskNotify() always returns\n * pdPASS in this case.\n *\n * eSetValueWithoutOverwrite -\n * If the task being notified did not already have a notification pending then\n * the task's notification value is set to ulValue and xTaskNotify() will\n * return pdPASS.  If the task being notified already had a notification\n * pending then no action is performed and pdFAIL is returned.\n *\n * eNoAction -\n * The task receives a notification without its notification value being\n * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in\n * this case.\n *\n * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should\n * be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * @return Dependent on the value of eAction.  See the description of the\n * eAction parameter.\n *\n * \\defgroup xTaskNotify xTaskNotify\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )\n#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * A notification sent to a task will remain pending until it is cleared by the\n * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was\n * already in the Blocked state to wait for a notification when the notification\n * arrives then the task will automatically be removed from the Blocked state\n * (unblocked) and the notification cleared.\n *\n * A task can use xTaskNotifyWait() to [optionally] block to wait for a\n * notification to be pending, or ulTaskNotifyTake() to [optionally] block\n * to wait for its notification value to have a non-zero value.  The task does\n * not consume any CPU time while it is in the Blocked state.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value\n * will be cleared in the calling task's notification value before the task\n * checks to see if any notifications are pending, and optionally blocks if no\n * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if\n * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have\n * the effect of resetting the task's notification value to 0.  Setting\n * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.\n *\n * @param ulBitsToClearOnExit If a notification is pending or received before\n * the calling task exits the xTaskNotifyWait() function then the task's\n * notification value (see the xTaskNotify() API function) is passed out using\n * the pulNotificationValue parameter.  Then any bits that are set in\n * ulBitsToClearOnExit will be cleared in the task's notification value (note\n * *pulNotificationValue is set before any bits are cleared).  Setting\n * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL\n * (if limits.h is not included) will have the effect of resetting the task's\n * notification value to 0 before the function exits.  Setting\n * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged\n * when the function exits (in which case the value passed out in\n * pulNotificationValue will match the task's notification value).\n *\n * @param pulNotificationValue Used to pass the task's notification value out\n * of the function.  Note the value passed out will not be effected by the\n * clearing of any bits caused by ulBitsToClearOnExit being non-zero.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for a notification to be received, should a notification\n * not already be pending when xTaskNotifyWait() was called.  The task\n * will not consume any processing time while it is in the Blocked state.  This\n * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be\n * used to convert a time specified in milliseconds to a time specified in\n * ticks.\n *\n * @return If a notification was received (including notifications that were\n * already pending when xTaskNotifyWait was called) then pdPASS is\n * returned.  Otherwise pdFAIL is returned.\n *\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\n * to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * xTaskNotifyGive() is a helper macro intended for use when task notifications\n * are used as light weight and faster binary or counting semaphore equivalents.\n * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,\n * the equivalent action that instead uses a task notification is\n * xTaskNotifyGive().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotificationTake() API function rather than the\n * xTaskNotifyWait() API function.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the\n * eAction parameter set to eIncrement - so pdPASS is always returned.\n *\n * \\defgroup xTaskNotifyGive xTaskNotifyGive\n * \\ingroup TaskNotifications\n */\n#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )\n\n/**\n * task. h\n * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro\n * to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * A version of xTaskNotifyGive() that can be called from an interrupt service\n * routine (ISR).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * vTaskNotifyGiveFromISR() is intended for use when task notifications are\n * used as light weight and faster binary or counting semaphore equivalents.\n * Actual FreeRTOS semaphores are given from an ISR using the\n * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses\n * a task notification is vTaskNotifyGiveFromISR().\n *\n * When task notifications are being used as a binary or counting semaphore\n * equivalent then the task being notified should wait for the notification\n * using the ulTaskNotificationTake() API function rather than the\n * xTaskNotifyWait() API function.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.\n *\n * @param xTaskToNotify The handle of the task being notified.  The handle to a\n * task can be returned from the xTaskCreate() API function used to create the\n * task, and the handle of the currently running task can be obtained by calling\n * xTaskGetCurrentTaskHandle().\n *\n * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set\n * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the\n * task to which the notification was sent to leave the Blocked state, and the\n * unblocked task has a priority higher than the currently running task.  If\n * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch\n * should be requested before the interrupt is exited.  How a context switch is\n * requested from an ISR is dependent on the port - see the documentation page\n * for the port in use.\n *\n * \\defgroup xTaskNotifyWait xTaskNotifyWait\n * \\ingroup TaskNotifications\n */\nvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>\n *\n * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this\n * function to be available.\n *\n * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private\n * \"notification value\", which is a 32-bit unsigned integer (uint32_t).\n *\n * Events can be sent to a task using an intermediary object.  Examples of such\n * objects are queues, semaphores, mutexes and event groups.  Task notifications\n * are a method of sending an event directly to a task without the need for such\n * an intermediary object.\n *\n * A notification sent to a task can optionally perform an action, such as\n * update, overwrite or increment the task's notification value.  In that way\n * task notifications can be used to send data to a task, or be used as light\n * weight and fast binary or counting semaphores.\n *\n * ulTaskNotifyTake() is intended for use when a task notification is used as a\n * faster and lighter weight binary or counting semaphore alternative.  Actual\n * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the\n * equivalent action that instead uses a task notification is\n * ulTaskNotifyTake().\n *\n * When a task is using its notification value as a binary or counting semaphore\n * other tasks should send notifications to it using the xTaskNotifyGive()\n * macro, or xTaskNotify() function with the eAction parameter set to\n * eIncrement.\n *\n * ulTaskNotifyTake() can either clear the task's notification value to\n * zero on exit, in which case the notification value acts like a binary\n * semaphore, or decrement the task's notification value on exit, in which case\n * the notification value acts like a counting semaphore.\n *\n * A task can use ulTaskNotifyTake() to [optionally] block to wait for a\n * the task's notification value to be non-zero.  The task does not consume any\n * CPU time while it is in the Blocked state.\n *\n * Where as xTaskNotifyWait() will return when a notification is pending,\n * ulTaskNotifyTake() will return when the task's notification value is\n * not zero.\n *\n * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.\n *\n * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's\n * notification value is decremented when the function exits.  In this way the\n * notification value acts like a counting semaphore.  If xClearCountOnExit is\n * not pdFALSE then the task's notification value is cleared to zero when the\n * function exits.  In this way the notification value acts like a binary\n * semaphore.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait in\n * the Blocked state for the task's notification value to be greater than zero,\n * should the count not already be greater than zero when\n * ulTaskNotifyTake() was called.  The task will not consume any processing\n * time while it is in the Blocked state.  This is specified in kernel ticks,\n * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time\n * specified in milliseconds to a time specified in ticks.\n *\n * @return The task's notification count before it is either cleared to zero or\n * decremented (see the xClearCountOnExit parameter).\n *\n * \\defgroup ulTaskNotifyTake ulTaskNotifyTake\n * \\ingroup TaskNotifications\n */\nuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * task. h\n * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>\n *\n * If the notification state of the task referenced by the handle xTask is\n * eNotified, then set the task's notification state to eNotWaitingNotification.\n * The task's notification value is not altered.  Set xTask to NULL to clear the\n * notification state of the calling task.\n *\n * @return pdTRUE if the task's notification state was set to\n * eNotWaitingNotification, otherwise pdFALSE.\n * \\defgroup xTaskNotifyStateClear xTaskNotifyStateClear\n * \\ingroup TaskNotifications\n */\nBaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );\n\n/**\n* task. h\n* <PRE>uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );</pre>\n*\n* Clears the bits specified by the ulBitsToClear bit mask in the notification\n* value of the task referenced by xTask.\n*\n* Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear\n* the notification value to 0.  Set ulBitsToClear to 0 to query the task's\n* notification value without clearing any bits.\n*\n* @return The value of the target task's notification value before the bits\n* specified by ulBitsToClear were cleared.\n* \\defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear\n* \\ingroup TaskNotifications\n*/\nuint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * <pre>void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )</pre>\n *\n * Capture the current time for future use with xTaskCheckForTimeOut().\n *\n * @param pxTimeOut Pointer to a timeout object into which the current time\n * is to be captured.  The captured time includes the tick count and the number\n * of times the tick count has overflowed since the system first booted.\n * \\defgroup vTaskSetTimeOutState vTaskSetTimeOutState\n * \\ingroup TaskCtrl\n */\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n/**\n * task.h\n * <pre>BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );</pre>\n *\n * Determines if pxTicksToWait ticks has passed since a time was captured\n * using a call to vTaskSetTimeOutState().  The captured time includes the tick\n * count and the number of times the tick count has overflowed.\n *\n * @param pxTimeOut The time status as captured previously using\n * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated\n * to reflect the current time status.\n * @param pxTicksToWait The number of ticks to check for timeout i.e. if\n * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by\n * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.\n * If the timeout has not occurred, pxTIcksToWait is updated to reflect the\n * number of remaining ticks.\n *\n * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is\n * returned and pxTicksToWait is updated to reflect the number of remaining\n * ticks.\n *\n * @see https://www.freertos.org/xTaskCheckForTimeOut.html\n *\n * Example Usage:\n * <pre>\n\t// Driver library function used to receive uxWantedBytes from an Rx buffer\n\t// that is filled by a UART interrupt. If there are not enough bytes in the\n\t// Rx buffer then the task enters the Blocked state until it is notified that\n\t// more data has been placed into the buffer. If there is still not enough\n\t// data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()\n\t// is used to re-calculate the Block time to ensure the total amount of time\n\t// spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This\n\t// continues until either the buffer contains at least uxWantedBytes bytes,\n\t// or the total amount of time spent in the Blocked state reaches\n\t// MAX_TIME_TO_WAIT – at which point the task reads however many bytes are\n\t// available up to a maximum of uxWantedBytes.\n\n\tsize_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )\n\t{\n\tsize_t uxReceived = 0;\n\tTickType_t xTicksToWait = MAX_TIME_TO_WAIT;\n\tTimeOut_t xTimeOut;\n\n\t\t// Initialize xTimeOut.  This records the time at which this function\n\t\t// was entered.\n\t\tvTaskSetTimeOutState( &xTimeOut );\n\n\t\t// Loop until the buffer contains the wanted number of bytes, or a\n\t\t// timeout occurs.\n\t\twhile( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )\n\t\t{\n\t\t\t// The buffer didn't contain enough data so this task is going to\n\t\t\t// enter the Blocked state. Adjusting xTicksToWait to account for\n\t\t\t// any time that has been spent in the Blocked state within this\n\t\t\t// function so far to ensure the total amount of time spent in the\n\t\t\t// Blocked state does not exceed MAX_TIME_TO_WAIT.\n\t\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )\n\t\t\t{\n\t\t\t\t//Timed out before the wanted number of bytes were available,\n\t\t\t\t// exit the loop.\n\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\t// Wait for a maximum of xTicksToWait ticks to be notified that the\n\t\t\t// receive interrupt has placed more data into the buffer.\n\t\t\tulTaskNotifyTake( pdTRUE, xTicksToWait );\n\t\t}\n\n\t\t// Attempt to read uxWantedBytes from the receive buffer into pucBuffer.\n\t\t// The actual number of bytes read (which might be less than\n\t\t// uxWantedBytes) is returned.\n\t\tuxReceived = UART_read_from_receive_buffer( pxUARTInstance,\n\t\t\t\t\t\t\t\t\t\t\t\t\tpucBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\tuxWantedBytes );\n\n\t\treturn uxReceived;\n\t}\n </pre>\n * \\defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut\n * \\ingroup TaskCtrl\n */\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------\n * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES\n *----------------------------------------------------------*/\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Called from the real time kernel tick (either preemptive or cooperative),\n * this increments the tick count and checks if any tasks that are blocked\n * for a finite period required removing from a blocked list and placing on\n * a ready list.  If a non-zero value is returned then a context switch is\n * required because either:\n *   + A task was removed from a blocked list because its timeout had expired,\n *     or\n *   + Time slicing is in use and there is a task of equal priority to the\n *     currently running task.\n */\nBaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes the calling task from the ready list and places it both\n * on the list of tasks waiting for a particular event, and the\n * list of delayed tasks.  The task will be removed from both lists\n * and replaced on the ready list should either the event occur (and\n * there be no higher priority tasks waiting on the same event) or\n * the delay period expires.\n *\n * The 'unordered' version replaces the event list item value with the\n * xItemValue value, and inserts the list item at the end of the list.\n *\n * The 'ordered' version uses the existing event list item value (which is the\n * owning tasks priority) to insert the list item into the event list is task\n * priority order.\n *\n * @param pxEventList The list containing tasks that are blocked waiting\n * for the event to occur.\n *\n * @param xItemValue The item value to use for the event list item when the\n * event list is not ordered by task priority.\n *\n * @param xTicksToWait The maximum amount of time that the task should wait\n * for the event to occur.  This is specified in kernel ticks,the constant\n * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time\n * period.\n */\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * This function performs nearly the same function as vTaskPlaceOnEventList().\n * The difference being that this function does not permit tasks to block\n * indefinitely, whereas vTaskPlaceOnEventList() does.\n *\n */\nvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN\n * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.\n *\n * Removes a task from both the specified event list and the list of blocked\n * tasks, and places it on a ready queue.\n *\n * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called\n * if either an event occurs to unblock a task, or the block timeout period\n * expires.\n *\n * xTaskRemoveFromEventList() is used when the event list is in task priority\n * order.  It removes the list item from the head of the event list as that will\n * have the highest priority owning task of all the tasks on the event list.\n * vTaskRemoveFromUnorderedEventList() is used when the event list is not\n * ordered and the event list items hold something other than the owning tasks\n * priority.  In this case the event list item value is updated to the value\n * passed in the xItemValue parameter.\n *\n * @return pdTRUE if the task being removed has a higher priority than the task\n * making the call, otherwise pdFALSE.\n */\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;\n\n/*\n * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY\n * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS\n * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.\n *\n * Sets the pointer to the current TCB to the TCB of the highest priority task\n * that is ready to run.\n */\nportDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;\n\n/*\n * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY\n * THE EVENT BITS MODULE.\n */\nTickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Return the handle of the calling task.\n */\nTaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Shortcut used by the queue implementation to prevent unnecessary call to\n * taskYIELD();\n */\nvoid vTaskMissedYield( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Returns the scheduler state as taskSCHEDULER_RUNNING,\n * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.\n */\nBaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Raises the priority of the mutex holder to that of the calling task should\n * the mutex holder have a priority less than the calling task.\n */\nBaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the priority of a task back to its proper priority in the case that it\n * inherited a higher priority while it was holding a semaphore.\n */\nBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;\n\n/*\n * If a higher priority task attempting to obtain a mutex caused a lower\n * priority task to inherit the higher priority task's priority - but the higher\n * priority task then timed out without obtaining the mutex, then the lower\n * priority task will disinherit the priority again - but only down as far as\n * the highest priority task that is still waiting for the mutex (if there were\n * more than one task waiting for the mutex).\n */\nvoid vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.\n */\nUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n/*\n * Set the uxTaskNumber of the task referenced by the xTask parameter to\n * uxHandle.\n */\nvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * If tickless mode is being used, or a low power mode is implemented, then\n * the tick interrupt will not execute during idle periods.  When this is the\n * case, the tick count value maintained by the scheduler needs to be kept up\n * to date with the actual execution time by being skipped forward by a time\n * equal to the idle period.\n */\nvoid vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;\n\n/* Correct the tick count value after the application code has held\ninterrupts disabled for an extended period.  xTicksToCatchUp is the number\nof tick interrupts that have been missed due to interrupts being disabled.\nIts value is not computed automatically, so must be computed by the\napplication writer.\n\nThis function is similar to vTaskStepTick(), however, unlike\nvTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a\ntime at which a task should be removed from the blocked state.  That means\ntasks may have to be removed from the blocked state as the tick count is\nmoved. */\nBaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;\n\n/*\n * Only available when configUSE_TICKLESS_IDLE is set to 1.\n * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port\n * specific sleep function to determine if it is ok to proceed with the sleep,\n * and if it is ok to proceed, if it is ok to sleep indefinitely.\n *\n * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only\n * called with the scheduler suspended, not from within a critical section.  It\n * is therefore possible for an interrupt to request a context switch between\n * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being\n * entered.  eTaskConfirmSleepModeStatus() should be called from a short\n * critical section between the timer being stopped and the sleep mode being\n * entered to ensure it is ok to proceed into the sleep mode.\n */\neSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Increment the mutex held count when a mutex is\n * taken and return the handle of the task that has taken the mutex.\n */\nTaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;\n\n/*\n * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial\n * section.\n */\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;\n\n\n#ifdef __cplusplus\n}\n#endif\n#endif /* INC_TASK_H */\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/include/timers.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef TIMERS_H\n#define TIMERS_H\n\n#ifndef INC_FREERTOS_H\n\t#error \"include FreeRTOS.h must appear in source files before include timers.h\"\n#endif\n\n/*lint -save -e537 This headers are only multiply included if the application code\nhappens to also be including task.h. */\n#include \"task.h\"\n/*lint -restore */\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * MACROS AND DEFINITIONS\n *----------------------------------------------------------*/\n\n/* IDs for commands that can be sent/received on the timer queue.  These are to\nbe used solely through the macros that make up the public software timer API,\nas defined below.  The commands that are sent from interrupts must use the\nhighest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task\nor interrupt version of the queue send function should be used. */\n#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR \t( ( BaseType_t ) -2 )\n#define tmrCOMMAND_EXECUTE_CALLBACK\t\t\t\t( ( BaseType_t ) -1 )\n#define tmrCOMMAND_START_DONT_TRACE\t\t\t\t( ( BaseType_t ) 0 )\n#define tmrCOMMAND_START\t\t\t\t\t    ( ( BaseType_t ) 1 )\n#define tmrCOMMAND_RESET\t\t\t\t\t\t( ( BaseType_t ) 2 )\n#define tmrCOMMAND_STOP\t\t\t\t\t\t\t( ( BaseType_t ) 3 )\n#define tmrCOMMAND_CHANGE_PERIOD\t\t\t\t( ( BaseType_t ) 4 )\n#define tmrCOMMAND_DELETE\t\t\t\t\t\t( ( BaseType_t ) 5 )\n\n#define tmrFIRST_FROM_ISR_COMMAND\t\t\t\t( ( BaseType_t ) 6 )\n#define tmrCOMMAND_START_FROM_ISR\t\t\t\t( ( BaseType_t ) 6 )\n#define tmrCOMMAND_RESET_FROM_ISR\t\t\t\t( ( BaseType_t ) 7 )\n#define tmrCOMMAND_STOP_FROM_ISR\t\t\t\t( ( BaseType_t ) 8 )\n#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR\t\t( ( BaseType_t ) 9 )\n\n\n/**\n * Type by which software timers are referenced.  For example, a call to\n * xTimerCreate() returns an TimerHandle_t variable that can then be used to\n * reference the subject timer in calls to other software timer API functions\n * (for example, xTimerStart(), xTimerReset(), etc.).\n */\nstruct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */\ntypedef struct tmrTimerControl * TimerHandle_t;\n\n/*\n * Defines the prototype to which timer callback functions must conform.\n */\ntypedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );\n\n/*\n * Defines the prototype to which functions used with the\n * xTimerPendFunctionCallFromISR() function must conform.\n */\ntypedef void (*PendedFunction_t)( void *, uint32_t );\n\n/**\n * TimerHandle_t xTimerCreate( \tconst char * const pcTimerName,\n * \t\t\t\t\t\t\t\tTickType_t xTimerPeriodInTicks,\n * \t\t\t\t\t\t\t\tUBaseType_t uxAutoReload,\n * \t\t\t\t\t\t\t\tvoid * pvTimerID,\n * \t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.  Time timer period must be greater than 0.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is\t\"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @return If the timer is successfully created then a handle to the newly\n * created timer is returned.  If the timer cannot be created because there is\n * insufficient FreeRTOS heap remaining to allocate the timer\n * structures then NULL is returned.\n *\n * Example usage:\n * @verbatim\n * #define NUM_TIMERS 5\n *\n * // An array to hold handles to the created timers.\n * TimerHandle_t xTimers[ NUM_TIMERS ];\n *\n * // An array to hold a count of the number of times each timer expires.\n * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };\n *\n * // Define a callback function that will be used by multiple timer instances.\n * // The callback function does nothing but count the number of times the\n * // associated timer expires, and stop the timer once the timer has expired\n * // 10 times.\n * void vTimerCallback( TimerHandle_t pxTimer )\n * {\n * int32_t lArrayIndex;\n * const int32_t xMaxExpiryCountBeforeStopping = 10;\n *\n * \t   // Optionally do something if the pxTimer parameter is NULL.\n * \t   configASSERT( pxTimer );\n *\n *     // Which timer expired?\n *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );\n *\n *     // Increment the number of times that pxTimer has expired.\n *     lExpireCounters[ lArrayIndex ] += 1;\n *\n *     // If the timer has expired 10 times then stop it from running.\n *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )\n *     {\n *         // Do not use a block time if calling a timer API function from a\n *         // timer callback function, as doing so could cause a deadlock!\n *         xTimerStop( pxTimer, 0 );\n *     }\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start some timers.  Starting the timers before the scheduler\n *     // has been started means the timers will start running immediately that\n *     // the scheduler starts.\n *     for( x = 0; x < NUM_TIMERS; x++ )\n *     {\n *         xTimers[ x ] = xTimerCreate(    \"Timer\",       // Just a text name, not used by the kernel.\n *                                         ( 100 * x ),   // The timer period in ticks.\n *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.\n *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.\n *                                         vTimerCallback // Each timer calls the same callback when it expires.\n *                                     );\n *\n *         if( xTimers[ x ] == NULL )\n *         {\n *             // The timer was not created.\n *         }\n *         else\n *         {\n *             // Start the timer.  No block time is specified, and even if one was\n *             // it would be ignored because the scheduler has not yet been\n *             // started.\n *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )\n *             {\n *                 // The timer could not be set into the Active state.\n *             }\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\tTimerHandle_t xTimerCreate(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;\n#endif\n\n/**\n * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,\n * \t\t\t\t\t\t\t\t\tTickType_t xTimerPeriodInTicks,\n * \t\t\t\t\t\t\t\t\tUBaseType_t uxAutoReload,\n * \t\t\t\t\t\t\t\t\tvoid * pvTimerID,\n * \t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n *\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer );\n *\n * Creates a new software timer instance, and returns a handle by which the\n * created software timer can be referenced.\n *\n * Internally, within the FreeRTOS implementation, software timers use a block\n * of memory, in which the timer data structure is stored.  If a software timer\n * is created using xTimerCreate() then the required memory is automatically\n * dynamically allocated inside the xTimerCreate() function.  (see\n * http://www.freertos.org/a00111.html).  If a software timer is created using\n * xTimerCreateStatic() then the application writer must provide the memory that\n * will get used by the software timer.  xTimerCreateStatic() therefore allows a\n * software timer to be created without using any dynamic memory allocation.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a\n * timer into the active state.\n *\n * @param pcTimerName A text name that is assigned to the timer.  This is done\n * purely to assist debugging.  The kernel itself only ever references a timer\n * by its handle, and never by its name.\n *\n * @param xTimerPeriodInTicks The timer period.  The time is defined in tick\n * periods so the constant portTICK_PERIOD_MS can be used to convert a time that\n * has been specified in milliseconds.  For example, if the timer must expire\n * after 100 ticks, then xTimerPeriodInTicks should be set to 100.\n * Alternatively, if the timer must expire after 500ms, then xPeriod can be set\n * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or\n * equal to 1000.  The timer period must be greater than 0.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.\n * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n *\n * @param pvTimerID An identifier that is assigned to the timer being created.\n * Typically this would be used in the timer callback function to identify which\n * timer expired when the same callback function is assigned to more than one\n * timer.\n *\n * @param pxCallbackFunction The function to call when the timer expires.\n * Callback functions must have the prototype defined by TimerCallbackFunction_t,\n * which is \"void vCallbackFunction( TimerHandle_t xTimer );\".\n *\n * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which\n * will be then be used to hold the software timer's data structures, removing\n * the need for the memory to be allocated dynamically.\n *\n * @return If the timer is created then a handle to the created timer is\n * returned.  If pxTimerBuffer was NULL then NULL is returned.\n *\n * Example usage:\n * @verbatim\n *\n * // The buffer used to hold the software timer's data structure.\n * static StaticTimer_t xTimerBuffer;\n *\n * // A variable that will be incremented by the software timer's callback\n * // function.\n * UBaseType_t uxVariableToIncrement = 0;\n *\n * // A software timer callback function that increments a variable passed to\n * // it when the software timer was created.  After the 5th increment the\n * // callback function stops the software timer.\n * static void prvTimerCallback( TimerHandle_t xExpiredTimer )\n * {\n * UBaseType_t *puxVariableToIncrement;\n * BaseType_t xReturned;\n *\n *     // Obtain the address of the variable to increment from the timer ID.\n *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );\n *\n *     // Increment the variable to show the timer callback has executed.\n *     ( *puxVariableToIncrement )++;\n *\n *     // If this callback has executed the required number of times, stop the\n *     // timer.\n *     if( *puxVariableToIncrement == 5 )\n *     {\n *         // This is called from a timer callback so must not block.\n *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );\n *     }\n * }\n *\n *\n * void main( void )\n * {\n *     // Create the software time.  xTimerCreateStatic() has an extra parameter\n *     // than the normal xTimerCreate() API function.  The parameter is a pointer\n *     // to the StaticTimer_t structure that will hold the software timer\n *     // structure.  If the parameter is passed as NULL then the structure will be\n *     // allocated dynamically, just as if xTimerCreate() had been called.\n *     xTimer = xTimerCreateStatic( \"T1\",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.\n *                                  xTimerPeriod,     // The period of the timer in ticks.\n *                                  pdTRUE,           // This is an auto-reload timer.\n *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function\n *                                  prvTimerCallback, // The function to execute when the timer expires.\n *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.\n *\n *     // The scheduler has not started yet so a block time is not used.\n *     xReturned = xTimerStart( xTimer, 0 );\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timers running as they have already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\tTimerHandle_t xTimerCreateStatic(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n/**\n * void *pvTimerGetTimerID( TimerHandle_t xTimer );\n *\n * Returns the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer, and by calling the\n * vTimerSetTimerID() API function.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being queried.\n *\n * @return The ID assigned to the timer being queried.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );\n *\n * Sets the ID assigned to the timer.\n *\n * IDs are assigned to timers using the pvTimerID parameter of the call to\n * xTimerCreated() that was used to create the timer.\n *\n * If the same callback function is assigned to multiple timers then the timer\n * ID can be used as time specific (timer local) storage.\n *\n * @param xTimer The timer being updated.\n *\n * @param pvNewID The ID to assign to the timer.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n */\nvoid vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );\n *\n * Queries a timer to see if it is active or dormant.\n *\n * A timer will be dormant if:\n *     1) It has been created but not started, or\n *     2) It is an expired one-shot timer that has not been restarted.\n *\n * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),\n * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and\n * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the\n * active state.\n *\n * @param xTimer The timer being queried.\n *\n * @return pdFALSE will be returned if the timer is dormant.  A value other than\n * pdFALSE will be returned if the timer is active.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is active, do something.\n *     }\n *     else\n *     {\n *         // xTimer is not active, do something else.\n *     }\n * }\n * @endverbatim\n */\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );\n *\n * Simply returns the handle of the timer service/daemon task.  It it not valid\n * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.\n */\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;\n\n/**\n * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStart() starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerStart() has equivalent functionality\n * to the xTimerReset() API function.\n *\n * Starting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerStart() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerStart() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerStart() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()\n * to be available.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the start command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerStop() stops a timer that was previously started using either of the\n * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),\n * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.\n *\n * Stopping a timer ensures the timer is not in the active state.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()\n * to be available.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the stop command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerCreate() API function example usage scenario.\n *\n */\n#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerChangePeriod( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\t\tTickType_t xNewPeriod,\n *\t\t\t\t\t\t\t\t\t\tTickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerChangePeriod() changes the period of a timer that was previously\n * created using the xTimerCreate() API function.\n *\n * xTimerChangePeriod() can be called to change the period of an active or\n * dormant state timer.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerChangePeriod() to be available.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the change period command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if\n * xTimerChangePeriod() is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the change period command could not be\n * sent to the timer command queue even after xTicksToWait ticks had passed.\n * pdPASS will be returned if the command was successfully sent to the timer\n * command queue.  When the command is actually processed will depend on the\n * priority of the timer service/daemon task relative to other tasks in the\n * system.  The timer service/daemon task priority is set by the\n * configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This function assumes xTimer has already been created.  If the timer\n * // referenced by xTimer is already active when it is called, then the timer\n * // is deleted.  If the timer referenced by xTimer is not active when it is\n * // called, then the period of the timer is set to 500ms and the timer is\n * // started.\n * void vAFunction( TimerHandle_t xTimer )\n * {\n *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently \"if( xTimerIsTimerActive( xTimer ) )\"\n *     {\n *         // xTimer is already active - delete it.\n *         xTimerDelete( xTimer );\n *     }\n *     else\n *     {\n *         // xTimer is not active, change its period to 500ms.  This will also\n *         // cause the timer to start.  Block for a maximum of 100 ticks if the\n *         // change period command cannot immediately be sent to the timer\n *         // command queue.\n *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )\n *         {\n *             // The command was successfully sent.\n *         }\n *         else\n *         {\n *             // The command could not be sent, even after waiting for 100 ticks\n *             // to pass.  Take appropriate action here.\n *         }\n *     }\n * }\n * @endverbatim\n */\n #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerDelete() deletes a timer that was previously created using the\n * xTimerCreate() API function.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for\n * xTimerDelete() to be available.\n *\n * @param xTimer The handle of the timer being deleted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the delete command to be\n * successfully sent to the timer command queue, should the queue already be\n * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()\n * is called before the scheduler is started.\n *\n * @return pdFAIL will be returned if the delete command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n *\n * See the xTimerChangePeriod() API function example usage scenario.\n */\n#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );\n *\n * Timer functionality is provided by a timer service/daemon task.  Many of the\n * public FreeRTOS timer API functions send commands to the timer service task\n * through a queue called the timer command queue.  The timer command queue is\n * private to the kernel itself and is not directly accessible to application\n * code.  The length of the timer command queue is set by the\n * configTIMER_QUEUE_LENGTH configuration constant.\n *\n * xTimerReset() re-starts a timer that was previously created using the\n * xTimerCreate() API function.  If the timer had already been started and was\n * already in the active state, then xTimerReset() will cause the timer to\n * re-evaluate its expiry time so that it is relative to when xTimerReset() was\n * called.  If the timer was in the dormant state then xTimerReset() has\n * equivalent functionality to the xTimerStart() API function.\n *\n * Resetting a timer ensures the timer is in the active state.  If the timer\n * is not stopped, deleted, or reset in the mean time, the callback function\n * associated with the timer will get called 'n' ticks after xTimerReset() was\n * called, where 'n' is the timers defined period.\n *\n * It is valid to call xTimerReset() before the scheduler has been started, but\n * when this is done the timer will not actually start until the scheduler is\n * started, and the timers expiry time will be relative to when the scheduler is\n * started, not relative to when xTimerReset() was called.\n *\n * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()\n * to be available.\n *\n * @param xTimer The handle of the timer being reset/started/restarted.\n *\n * @param xTicksToWait Specifies the time, in ticks, that the calling task should\n * be held in the Blocked state to wait for the reset command to be successfully\n * sent to the timer command queue, should the queue already be full when\n * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called\n * before the scheduler is started.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will\n * be returned if the command was successfully sent to the timer command queue.\n * When the command is actually processed will depend on the priority of the\n * timer service/daemon task relative to other tasks in the system, although the\n * timers expiry time is relative to when xTimerStart() is actually called.  The\n * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer.\n *\n * TimerHandle_t xBacklightTimer = NULL;\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press event handler.\n * void vKeyPressEventHandler( char cKey )\n * {\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  Wait 10 ticks for the command to be successfully sent\n *     // if it cannot be sent immediately.\n *     vSetBacklightState( BACKLIGHT_ON );\n *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n * }\n *\n * void main( void )\n * {\n * int32_t x;\n *\n *     // Create then start the one-shot timer that is responsible for turning\n *     // the back-light off if no keys are pressed within a 5 second period.\n *     xBacklightTimer = xTimerCreate( \"BacklightTimer\",           // Just a text name, not used by the kernel.\n *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.\n *                                     pdFALSE,                    // The timer is a one-shot timer.\n *                                     0,                          // The id is not used by the callback so can take any value.\n *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.\n *                                   );\n *\n *     if( xBacklightTimer == NULL )\n *     {\n *         // The timer was not created.\n *     }\n *     else\n *     {\n *         // Start the timer.  No block time is specified, and even if one was\n *         // it would be ignored because the scheduler has not yet been\n *         // started.\n *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )\n *         {\n *             // The timer could not be set into the Active state.\n *         }\n *     }\n *\n *     // ...\n *     // Create tasks here.\n *     // ...\n *\n *     // Starting the scheduler will start the timer running as it has already\n *     // been set into the active state.\n *     vTaskStartScheduler();\n *\n *     // Should not reach here.\n *     for( ;; );\n * }\n * @endverbatim\n */\n#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )\n\n/**\n * BaseType_t xTimerStartFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStart() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being started/restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStartFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStartFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStartFromISR() function.  If\n * xTimerStartFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the start command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerStartFromISR() is actually called.  The timer\n * service/daemon task priority is set by the configTIMER_TASK_PRIORITY\n * configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then restart the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The start command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerStopFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerStop() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer being stopped.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerStopFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerStopFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerStopFromISR() function.  If\n * xTimerStopFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the stop command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the timer should be simply stopped.\n *\n * // The interrupt service routine that stops the timer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - simply stop the timer.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The stop command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\t\t TickType_t xNewPeriod,\n *\t\t\t\t\t\t\t\t\t\t BaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerChangePeriod() that can be called from an interrupt\n * service routine.\n *\n * @param xTimer The handle of the timer that is having its period changed.\n *\n * @param xNewPeriod The new period for xTimer. Timer periods are specified in\n * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time\n * that has been specified in milliseconds.  For example, if the timer must\n * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,\n * if the timer must expire after 500ms, then xNewPeriod can be set to\n * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than\n * or equal to 1000.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the\n * timer command queue, so has the potential to transition the timer service/\n * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()\n * causes the timer service/daemon task to leave the Blocked state, and the\n * timer service/daemon task has a priority equal to or greater than the\n * currently executing task (the task that was interrupted), then\n * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the\n * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets\n * this value to pdTRUE then a context switch should be performed before the\n * interrupt exits.\n *\n * @return pdFAIL will be returned if the command to change the timers period\n * could not be sent to the timer command queue.  pdPASS will be returned if the\n * command was successfully sent to the timer command queue.  When the command\n * is actually processed will depend on the priority of the timer service/daemon\n * task relative to other tasks in the system.  The timer service/daemon task\n * priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xTimer has already been created and started.  When\n * // an interrupt occurs, the period of xTimer should be changed to 500ms.\n *\n * // The interrupt service routine that changes the period of xTimer.\n * void vAnExampleInterruptServiceRoutine( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // The interrupt has occurred - change the period of xTimer to 500ms.\n *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined\n *     // (within this function).  As this is an interrupt service routine, only\n *     // FreeRTOS API functions that end in \"FromISR\" can be used.\n *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The command to change the timers period was not executed\n *         // successfully.  Take appropriate action here.\n *     }\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )\n\n/**\n * BaseType_t xTimerResetFromISR( \tTimerHandle_t xTimer,\n *\t\t\t\t\t\t\t\t\tBaseType_t *pxHigherPriorityTaskWoken );\n *\n * A version of xTimerReset() that can be called from an interrupt service\n * routine.\n *\n * @param xTimer The handle of the timer that is to be started, reset, or\n * restarted.\n *\n * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most\n * of its time in the Blocked state, waiting for messages to arrive on the timer\n * command queue.  Calling xTimerResetFromISR() writes a message to the timer\n * command queue, so has the potential to transition the timer service/daemon\n * task out of the Blocked state.  If calling xTimerResetFromISR() causes the\n * timer service/daemon task to leave the Blocked state, and the timer service/\n * daemon task has a priority equal to or greater than the currently executing\n * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will\n * get set to pdTRUE internally within the xTimerResetFromISR() function.  If\n * xTimerResetFromISR() sets this value to pdTRUE then a context switch should\n * be performed before the interrupt exits.\n *\n * @return pdFAIL will be returned if the reset command could not be sent to\n * the timer command queue.  pdPASS will be returned if the command was\n * successfully sent to the timer command queue.  When the command is actually\n * processed will depend on the priority of the timer service/daemon task\n * relative to other tasks in the system, although the timers expiry time is\n * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon\n * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.\n *\n * Example usage:\n * @verbatim\n * // This scenario assumes xBacklightTimer has already been created.  When a\n * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass\n * // without a key being pressed, then the LCD back-light is switched off.  In\n * // this case, the timer is a one-shot timer, and unlike the example given for\n * // the xTimerReset() function, the key press event handler is an interrupt\n * // service routine.\n *\n * // The callback function assigned to the one-shot timer.  In this case the\n * // parameter is not used.\n * void vBacklightTimerCallback( TimerHandle_t pxTimer )\n * {\n *     // The timer expired, therefore 5 seconds must have passed since a key\n *     // was pressed.  Switch off the LCD back-light.\n *     vSetBacklightState( BACKLIGHT_OFF );\n * }\n *\n * // The key press interrupt service routine.\n * void vKeyPressEventInterruptHandler( void )\n * {\n * BaseType_t xHigherPriorityTaskWoken = pdFALSE;\n *\n *     // Ensure the LCD back-light is on, then reset the timer that is\n *     // responsible for turning the back-light off after 5 seconds of\n *     // key inactivity.  This is an interrupt service routine so can only\n *     // call FreeRTOS API functions that end in \"FromISR\".\n *     vSetBacklightState( BACKLIGHT_ON );\n *\n *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here\n *     // as both cause the timer to re-calculate its expiry time.\n *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was\n *     // declared (in this function).\n *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )\n *     {\n *         // The reset command was not executed successfully.  Take appropriate\n *         // action here.\n *     }\n *\n *     // Perform the rest of the key processing here.\n *\n *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch\n *     // should be performed.  The syntax required to perform a context switch\n *     // from inside an ISR varies from port to port, and from compiler to\n *     // compiler.  Inspect the demos for the port you are using to find the\n *     // actual syntax required.\n *     if( xHigherPriorityTaskWoken != pdFALSE )\n *     {\n *         // Call the interrupt safe yield function here (actual function\n *         // depends on the FreeRTOS port being used).\n *     }\n * }\n * @endverbatim\n */\n#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )\n\n\n/**\n * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,\n *                                          void *pvParameter1,\n *                                          uint32_t ulParameter2,\n *                                          BaseType_t *pxHigherPriorityTaskWoken );\n *\n *\n * Used from application interrupt service routines to defer the execution of a\n * function to the RTOS daemon task (the timer service task, hence this function\n * is implemented in timers.c and is prefixed with 'Timer').\n *\n * Ideally an interrupt service routine (ISR) is kept as short as possible, but\n * sometimes an ISR either has a lot of processing to do, or needs to perform\n * processing that is not deterministic.  In these cases\n * xTimerPendFunctionCallFromISR() can be used to defer processing of a function\n * to the RTOS daemon task.\n *\n * A mechanism is provided that allows the interrupt to return directly to the\n * task that will subsequently execute the pended callback function.  This\n * allows the callback function to execute contiguously in time with the\n * interrupt - just as if the callback had executed in the interrupt itself.\n *\n * @param xFunctionToPend The function to execute from the timer service/\n * daemon task.  The function must conform to the PendedFunction_t\n * prototype.\n *\n * @param pvParameter1 The value of the callback function's first parameter.\n * The parameter has a void * type to allow it to be used to pass any type.\n * For example, unsigned longs can be cast to a void *, or the void * can be\n * used to point to a structure.\n *\n * @param ulParameter2 The value of the callback function's second parameter.\n *\n * @param pxHigherPriorityTaskWoken As mentioned above, calling this function\n * will result in a message being sent to the timer daemon task.  If the\n * priority of the timer daemon task (which is set using\n * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of\n * the currently running task (the task the interrupt interrupted) then\n * *pxHigherPriorityTaskWoken will be set to pdTRUE within\n * xTimerPendFunctionCallFromISR(), indicating that a context switch should be\n * requested before the interrupt exits.  For that reason\n * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the\n * example code below.\n *\n * @return pdPASS is returned if the message was successfully sent to the\n * timer daemon task, otherwise pdFALSE is returned.\n *\n * Example usage:\n * @verbatim\n *\n *\t// The callback function that will execute in the context of the daemon task.\n *  // Note callback functions must all use this same prototype.\n *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )\n *\t{\n *\t\tBaseType_t xInterfaceToService;\n *\n *\t\t// The interface that requires servicing is passed in the second\n *      // parameter.  The first parameter is not used in this case.\n *\t\txInterfaceToService = ( BaseType_t ) ulParameter2;\n *\n *\t\t// ...Perform the processing here...\n *\t}\n *\n *\t// An ISR that receives data packets from multiple interfaces\n *  void vAnISR( void )\n *\t{\n *\t\tBaseType_t xInterfaceToService, xHigherPriorityTaskWoken;\n *\n *\t\t// Query the hardware to determine which interface needs processing.\n *\t\txInterfaceToService = prvCheckInterfaces();\n *\n *      // The actual processing is to be deferred to a task.  Request the\n *      // vProcessInterface() callback function is executed, passing in the\n *\t\t// number of the interface that needs processing.  The interface to\n *\t\t// service is passed in the second parameter.  The first parameter is\n *\t\t// not used in this case.\n *\t\txHigherPriorityTaskWoken = pdFALSE;\n *\t\txTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );\n *\n *\t\t// If xHigherPriorityTaskWoken is now set to pdTRUE then a context\n *\t\t// switch should be requested.  The macro used is port specific and will\n *\t\t// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to\n *\t\t// the documentation page for the port being used.\n *\t\tportYIELD_FROM_ISR( xHigherPriorityTaskWoken );\n *\n *\t}\n * @endverbatim\n */\nBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;\n\n /**\n  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,\n  *                                    void *pvParameter1,\n  *                                    uint32_t ulParameter2,\n  *                                    TickType_t xTicksToWait );\n  *\n  *\n  * Used to defer the execution of a function to the RTOS daemon task (the timer\n  * service task, hence this function is implemented in timers.c and is prefixed\n  * with 'Timer').\n  *\n  * @param xFunctionToPend The function to execute from the timer service/\n  * daemon task.  The function must conform to the PendedFunction_t\n  * prototype.\n  *\n  * @param pvParameter1 The value of the callback function's first parameter.\n  * The parameter has a void * type to allow it to be used to pass any type.\n  * For example, unsigned longs can be cast to a void *, or the void * can be\n  * used to point to a structure.\n  *\n  * @param ulParameter2 The value of the callback function's second parameter.\n  *\n  * @param xTicksToWait Calling this function will result in a message being\n  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of\n  * time the calling task should remain in the Blocked state (so not using any\n  * processing time) for space to become available on the timer queue if the\n  * queue is found to be full.\n  *\n  * @return pdPASS is returned if the message was successfully sent to the\n  * timer daemon task, otherwise pdFALSE is returned.\n  *\n  */\nBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n/**\n * const char * const pcTimerGetName( TimerHandle_t xTimer );\n *\n * Returns the name that was assigned to a timer when the timer was created.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The name assigned to the timer specified by the xTimer parameter.\n */\nconst char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n/**\n * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );\n *\n * Updates a timer to be either an auto-reload timer, in which case the timer\n * automatically resets itself each time it expires, or a one-shot timer, in\n * which case the timer will only expire once unless it is manually restarted.\n *\n * @param xTimer The handle of the timer being updated.\n *\n * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will\n * expire repeatedly with a frequency set by the timer's period (see the\n * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If\n * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and\n * enter the dormant state after it expires.\n */\nvoid vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;\n\n/**\n* UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );\n*\n* Queries a timer to determine if it is an auto-reload timer, in which case the timer\n* automatically resets itself each time it expires, or a one-shot timer, in\n* which case the timer will only expire once unless it is manually restarted.\n*\n* @param xTimer The handle of the timer being queried.\n*\n* @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise\n* pdFALSE is returned.\n*/\nUBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );\n *\n * Returns the period of a timer.\n *\n * @param xTimer The handle of the timer being queried.\n *\n * @return The period of the timer in ticks.\n */\nTickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/**\n* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );\n*\n* Returns the time in ticks at which the timer will expire.  If this is less\n* than the current tick count then the expiry time has overflowed from the\n* current time.\n*\n* @param xTimer The handle of the timer being queried.\n*\n* @return If the timer is running then the time in ticks at which the timer\n* will next expire is returned.  If the timer is not running then the return\n* value is undefined.\n*/\nTickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n\n/*\n * Functions beyond this part are not part of the public API and are intended\n * for use by the kernel only.\n */\nBaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tvoid vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;\n\tUBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;\n#endif\n\n#ifdef __cplusplus\n}\n#endif\n#endif /* TIMERS_H */\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/list.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#include <stdlib.h>\n#include \"FreeRTOS.h\"\n#include \"list.h\"\n\n/*-----------------------------------------------------------\n * PUBLIC LIST API documented in list.h\n *----------------------------------------------------------*/\n\nvoid vListInitialise( List_t * const pxList )\n{\n\t/* The list structure contains a list item which is used to mark the\n\tend of the list.  To initialise the list the list end is inserted\n\tas the only list entry. */\n\tpxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );\t\t\t/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n\t/* The list end value is the highest possible value in the list to\n\tensure it remains at the end of the list. */\n\tpxList->xListEnd.xItemValue = portMAX_DELAY;\n\n\t/* The list end next and previous pointers point to itself so we know\n\twhen the list is empty. */\n\tpxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );\t/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\tpxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */\n\n\tpxList->uxNumberOfItems = ( UBaseType_t ) 0U;\n\n\t/* Write known values into the list if\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tlistSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );\n\tlistSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInitialiseItem( ListItem_t * const pxItem )\n{\n\t/* Make sure the list item is not recorded as being on a list. */\n\tpxItem->pxContainer = NULL;\n\n\t/* Write known values into the list item if\n\tconfigUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */\n\tlistSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n\tlistSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )\n{\nListItem_t * const pxIndex = pxList->pxIndex;\n\n\t/* Only effective when configASSERT() is also defined, these tests may catch\n\tthe list data structures being overwritten in memory.  They will not catch\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\n\tlistTEST_LIST_INTEGRITY( pxList );\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n\t/* Insert a new list item into pxList, but rather than sort the list,\n\tmakes the new list item the last item to be removed by a call to\n\tlistGET_OWNER_OF_NEXT_ENTRY(). */\n\tpxNewListItem->pxNext = pxIndex;\n\tpxNewListItem->pxPrevious = pxIndex->pxPrevious;\n\n\t/* Only used during decision coverage testing. */\n\tmtCOVERAGE_TEST_DELAY();\n\n\tpxIndex->pxPrevious->pxNext = pxNewListItem;\n\tpxIndex->pxPrevious = pxNewListItem;\n\n\t/* Remember which list the item is in. */\n\tpxNewListItem->pxContainer = pxList;\n\n\t( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nvoid vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )\n{\nListItem_t *pxIterator;\nconst TickType_t xValueOfInsertion = pxNewListItem->xItemValue;\n\n\t/* Only effective when configASSERT() is also defined, these tests may catch\n\tthe list data structures being overwritten in memory.  They will not catch\n\tdata errors caused by incorrect configuration or use of FreeRTOS. */\n\tlistTEST_LIST_INTEGRITY( pxList );\n\tlistTEST_LIST_ITEM_INTEGRITY( pxNewListItem );\n\n\t/* Insert the new list item into the list, sorted in xItemValue order.\n\n\tIf the list already contains a list item with the same item value then the\n\tnew list item should be placed after it.  This ensures that TCBs which are\n\tstored in ready lists (all of which have the same xItemValue value) get a\n\tshare of the CPU.  However, if the xItemValue is the same as the back marker\n\tthe iteration loop below will not end.  Therefore the value is checked\n\tfirst, and the algorithm slightly modified if necessary. */\n\tif( xValueOfInsertion == portMAX_DELAY )\n\t{\n\t\tpxIterator = pxList->xListEnd.pxPrevious;\n\t}\n\telse\n\t{\n\t\t/* *** NOTE ***********************************************************\n\t\tIf you find your application is crashing here then likely causes are\n\t\tlisted below.  In addition see https://www.freertos.org/FAQHelp.html for\n\t\tmore tips, and ensure configASSERT() is defined!\n\t\thttps://www.freertos.org/a00110.html#configASSERT\n\n\t\t\t1) Stack overflow -\n\t\t\t   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html\n\t\t\t2) Incorrect interrupt priority assignment, especially on Cortex-M\n\t\t\t   parts where numerically high priority values denote low actual\n\t\t\t   interrupt priorities, which can seem counter intuitive.  See\n\t\t\t   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition\n\t\t\t   of configMAX_SYSCALL_INTERRUPT_PRIORITY on\n\t\t\t   https://www.freertos.org/a00110.html\n\t\t\t3) Calling an API function from within a critical section or when\n\t\t\t   the scheduler is suspended, or calling an API function that does\n\t\t\t   not end in \"FromISR\" from an interrupt.\n\t\t\t4) Using a queue or semaphore before it has been initialised or\n\t\t\t   before the scheduler has been started (are interrupts firing\n\t\t\t   before vTaskStartScheduler() has been called?).\n\t\t**********************************************************************/\n\n\t\tfor( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */\n\t\t{\n\t\t\t/* There is nothing to do here, just iterating to the wanted\n\t\t\tinsertion position. */\n\t\t}\n\t}\n\n\tpxNewListItem->pxNext = pxIterator->pxNext;\n\tpxNewListItem->pxNext->pxPrevious = pxNewListItem;\n\tpxNewListItem->pxPrevious = pxIterator;\n\tpxIterator->pxNext = pxNewListItem;\n\n\t/* Remember which list the item is in.  This allows fast removal of the\n\titem later. */\n\tpxNewListItem->pxContainer = pxList;\n\n\t( pxList->uxNumberOfItems )++;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )\n{\n/* The list item knows which list it is in.  Obtain the list from the list\nitem. */\nList_t * const pxList = pxItemToRemove->pxContainer;\n\n\tpxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;\n\tpxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;\n\n\t/* Only used during decision coverage testing. */\n\tmtCOVERAGE_TEST_DELAY();\n\n\t/* Make sure the index is left pointing to a valid item. */\n\tif( pxList->pxIndex == pxItemToRemove )\n\t{\n\t\tpxList->pxIndex = pxItemToRemove->pxPrevious;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxItemToRemove->pxContainer = NULL;\n\t( pxList->uxNumberOfItems )--;\n\n\treturn pxList->uxNumberOfItems;\n}\n/*-----------------------------------------------------------*/\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*-----------------------------------------------------------\n * Implementation of functions defined in portable.h for the ARM CM4F port.\n *----------------------------------------------------------*/\n\n/* Scheduler includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#ifndef __VFP_FP__\n\t#error This port can only be used when the project options are configured to enable hardware floating point support.\n#endif\n\n#ifndef configSYSTICK_CLOCK_HZ\n\t#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\n\t/* Ensure the SysTick is clocked at the same frequency as the core. */\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 1UL << 2UL )\n#else\n\t/* The way the SysTick is clocked is not modified in case it is not the same\n\tas the core. */\n\t#define portNVIC_SYSTICK_CLK_BIT\t( 0 )\n#endif\n\n/* Constants required to manipulate the core.  Registers first... */\n#define portNVIC_SYSTICK_CTRL_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e010 ) )\n#define portNVIC_SYSTICK_LOAD_REG\t\t\t( * ( ( volatile uint32_t * ) 0xe000e014 ) )\n#define portNVIC_SYSTICK_CURRENT_VALUE_REG\t( * ( ( volatile uint32_t * ) 0xe000e018 ) )\n#define portNVIC_SYSPRI2_REG\t\t\t\t( * ( ( volatile uint32_t * ) 0xe000ed20 ) )\n/* ...then bits in the registers. */\n#define portNVIC_SYSTICK_INT_BIT\t\t\t( 1UL << 1UL )\n#define portNVIC_SYSTICK_ENABLE_BIT\t\t\t( 1UL << 0UL )\n#define portNVIC_SYSTICK_COUNT_FLAG_BIT\t\t( 1UL << 16UL )\n#define portNVIC_PENDSVCLEAR_BIT \t\t\t( 1UL << 27UL )\n#define portNVIC_PEND_SYSTICK_CLEAR_BIT\t\t( 1UL << 25UL )\n\n/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7\nr0p1 port. */\n#define portCPUID\t\t\t\t\t\t\t( * ( ( volatile uint32_t * ) 0xE000ed00 ) )\n#define portCORTEX_M7_r0p1_ID\t\t\t\t( 0x410FC271UL )\n#define portCORTEX_M7_r0p0_ID\t\t\t\t( 0x410FC270UL )\n\n#define portNVIC_PENDSV_PRI\t\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\n#define portNVIC_SYSTICK_PRI\t\t\t\t( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\n\n/* Constants required to check the validity of an interrupt priority. */\n#define portFIRST_USER_INTERRUPT_NUMBER\t\t( 16 )\n#define portNVIC_IP_REGISTERS_OFFSET_16 \t( 0xE000E3F0 )\n#define portAIRCR_REG\t\t\t\t\t\t( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\n#define portMAX_8_BIT_VALUE\t\t\t\t\t( ( uint8_t ) 0xff )\n#define portTOP_BIT_OF_BYTE\t\t\t\t\t( ( uint8_t ) 0x80 )\n#define portMAX_PRIGROUP_BITS\t\t\t\t( ( uint8_t ) 7 )\n#define portPRIORITY_GROUP_MASK\t\t\t\t( 0x07UL << 8UL )\n#define portPRIGROUP_SHIFT\t\t\t\t\t( 8UL )\n\n/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */\n#define portVECTACTIVE_MASK\t\t\t\t\t( 0xFFUL )\n\n/* Constants required to manipulate the VFP. */\n#define portFPCCR\t\t\t\t\t\t\t( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */\n#define portASPEN_AND_LSPEN_BITS\t\t\t( 0x3UL << 30UL )\n\n/* Constants required to set up the initial stack. */\n#define portINITIAL_XPSR\t\t\t\t\t( 0x01000000 )\n#define portINITIAL_EXC_RETURN\t\t\t\t( 0xfffffffd )\n\n/* The systick is a 24-bit counter. */\n#define portMAX_24_BIT_NUMBER\t\t\t\t( 0xffffffUL )\n\n/* For strict compliance with the Cortex-M spec the task start address should\nhave bit-0 clear, as it is loaded into the PC on exit from an ISR. */\n#define portSTART_ADDRESS_MASK\t\t( ( StackType_t ) 0xfffffffeUL )\n\n/* A fiddle factor to estimate the number of SysTick counts that would have\noccurred while the SysTick counter is stopped during tickless idle\ncalculations. */\n#define portMISSED_COUNTS_FACTOR\t\t\t( 45UL )\n\n/* Let the user override the pre-loading of the initial LR with the address of\nprvTaskExitError() in case it messes up unwinding of the stack in the\ndebugger. */\n#ifdef configTASK_RETURN_ADDRESS\n\t#define portTASK_RETURN_ADDRESS\tconfigTASK_RETURN_ADDRESS\n#else\n\t#define portTASK_RETURN_ADDRESS\tprvTaskExitError\n#endif\n\n/*\n * Setup the timer to generate the tick interrupts.  The implementation in this\n * file is weak to allow application writers to change the timer used to\n * generate the tick interrupt.\n */\nvoid vPortSetupTimerInterrupt( void );\n\n/*\n * Exception handlers.\n */\nvoid xPortPendSVHandler( void ) __attribute__ (( naked ));\nvoid xPortSysTickHandler( void );\nvoid vPortSVCHandler( void ) __attribute__ (( naked ));\n\n/*\n * Start first task is a separate function so it can be tested in isolation.\n */\nstatic void prvPortStartFirstTask( void ) __attribute__ (( naked ));\n\n/*\n * Function to enable the VFP.\n */\nstatic void vPortEnableVFP( void ) __attribute__ (( naked ));\n\n/*\n * Used to catch tasks that attempt to return from their implementing function.\n */\nstatic void prvTaskExitError( void );\n\n/*-----------------------------------------------------------*/\n\n/* Each task maintains its own interrupt status in the critical nesting\nvariable. */\nstatic UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\n\n/*\n * The number of SysTick increments that make up one tick period.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t ulTimerCountsForOneTick = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * The maximum number of tick periods that can be suppressed is limited by the\n * 24 bit resolution of the SysTick timer.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t xMaximumPossibleSuppressedTicks = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Compensate for the CPU cycles that pass while the SysTick is stopped (low\n * power functionality only.\n */\n#if( configUSE_TICKLESS_IDLE == 1 )\n\tstatic uint32_t ulStoppedTimerCompensation = 0;\n#endif /* configUSE_TICKLESS_IDLE */\n\n/*\n * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\n * FreeRTOS API functions are not called from interrupts that have been assigned\n * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\n */\n#if( configASSERT_DEFINED == 1 )\n\t static uint8_t ucMaxSysCallPriority = 0;\n\t static uint32_t ulMaxPRIGROUPValue = 0;\n\t static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\n#endif /* configASSERT_DEFINED */\n\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nStackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\n{\n\t/* Simulate the stack frame as it would be created by a context switch\n\tinterrupt. */\n\n\t/* Offset added to account for the way the MCU uses the stack on entry/exit\n\tof interrupts, and to ensure alignment. */\n\tpxTopOfStack--;\n\n\t*pxTopOfStack = portINITIAL_XPSR;\t/* xPSR */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;\t/* PC */\n\tpxTopOfStack--;\n\t*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;\t/* LR */\n\n\t/* Save code space by skipping register initialisation. */\n\tpxTopOfStack -= 5;\t/* R12, R3, R2 and R1. */\n\t*pxTopOfStack = ( StackType_t ) pvParameters;\t/* R0 */\n\n\t/* A save method is being used that requires each task to maintain its\n\town exec return value. */\n\tpxTopOfStack--;\n\t*pxTopOfStack = portINITIAL_EXC_RETURN;\n\n\tpxTopOfStack -= 8;\t/* R11, R10, R9, R8, R7, R6, R5 and R4. */\n\n\treturn pxTopOfStack;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvTaskExitError( void )\n{\nvolatile uint32_t ulDummy = 0;\n\n\t/* A function that implements a task must not exit or attempt to return to\n\tits caller as there is nothing to return to.  If a task wants to exit it\n\tshould instead call vTaskDelete( NULL ).\n\n\tArtificially force an assert() to be triggered if configASSERT() is\n\tdefined, then stop here so application writers can catch the error. */\n\tconfigASSERT( uxCriticalNesting == ~0UL );\n\tportDISABLE_INTERRUPTS();\n\twhile( ulDummy == 0 )\n\t{\n\t\t/* This file calls prvTaskExitError() after the scheduler has been\n\t\tstarted to remove a compiler warning about the function being defined\n\t\tbut never called.  ulDummy is used purely to quieten other warnings\n\t\tabout code appearing after this function is called - making ulDummy\n\t\tvolatile makes the compiler think the function could return and\n\t\ttherefore not output an 'unreachable code' warning for code that appears\n\t\tafter it. */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortSVCHandler( void )\n{\n\t__asm volatile (\n\t\t\t\t\t\"\tldr\tr3, pxCurrentTCBConst2\t\t\\n\" /* Restore the context. */\n\t\t\t\t\t\"\tldr r1, [r3]\t\t\t\t\t\\n\" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */\n\t\t\t\t\t\"\tldr r0, [r1]\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\n\t\t\t\t\t\"\tldmia r0!, {r4-r11, r14}\t\t\\n\" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */\n\t\t\t\t\t\"\tmsr psp, r0\t\t\t\t\t\t\\n\" /* Restore the task stack pointer. */\n\t\t\t\t\t\"\tisb\t\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tmov r0, #0 \t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tmsr\tbasepri, r0\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\tbx r14\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\t\t\t\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"\t.align 4\t\t\t\t\t\t\\n\"\n\t\t\t\t\t\"pxCurrentTCBConst2: .word pxCurrentTCB\t\t\t\t\\n\"\n\t\t\t\t);\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvPortStartFirstTask( void )\n{\n\t/* Start the first task.  This also clears the bit that indicates the FPU is\n\tin use in case the FPU was used before the scheduler was started - which\n\twould otherwise result in the unnecessary leaving of space in the SVC stack\n\tfor lazy saving of FPU registers. */\n\t__asm volatile(\n\t\t\t\t\t\" ldr r0, =0xE000ED08 \t\\n\" /* Use the NVIC offset register to locate the stack. */\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\n\t\t\t\t\t\" ldr r0, [r0] \t\t\t\\n\"\n\t\t\t\t\t\" msr msp, r0\t\t\t\\n\" /* Set the msp back to the start of the stack. */\n\t\t\t\t\t\" mov r0, #0\t\t\t\\n\" /* Clear the bit that indicates the FPU is in use, see comment above. */\n\t\t\t\t\t\" msr control, r0\t\t\\n\"\n\t\t\t\t\t\" cpsie i\t\t\t\t\\n\" /* Globally enable interrupts. */\n\t\t\t\t\t\" cpsie f\t\t\t\t\\n\"\n\t\t\t\t\t\" dsb\t\t\t\t\t\\n\"\n\t\t\t\t\t\" isb\t\t\t\t\t\\n\"\n\t\t\t\t\t\" svc 0\t\t\t\t\t\\n\" /* System call to start first task. */\n\t\t\t\t\t\" nop\t\t\t\t\t\\n\"\n\t\t\t\t);\n}\n/*-----------------------------------------------------------*/\n\n/*\n * See header file for description.\n */\nBaseType_t xPortStartScheduler( void )\n{\n\t/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.\n\tSee http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\n\tconfigASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );\n\n\t/* This port can be used on all revisions of the Cortex-M7 core other than\n\tthe r0p1 parts.  r0p1 parts should use the port from the\n\t/source/portable/GCC/ARM_CM7/r0p1 directory. */\n\tconfigASSERT( portCPUID != portCORTEX_M7_r0p1_ID );\n\tconfigASSERT( portCPUID != portCORTEX_M7_r0p0_ID );\n\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\tvolatile uint32_t ulOriginalPriority;\n\t\tvolatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\n\t\tvolatile uint8_t ucMaxPriorityValue;\n\n\t\t/* Determine the maximum priority from which ISR safe FreeRTOS API\n\t\tfunctions can be called.  ISR safe functions are those that end in\n\t\t\"FromISR\".  FreeRTOS maintains separate thread and ISR API functions to\n\t\tensure interrupt entry is as fast and simple as possible.\n\n\t\tSave the interrupt priority value that is about to be clobbered. */\n\t\tulOriginalPriority = *pucFirstUserPriorityRegister;\n\n\t\t/* Determine the number of priority bits available.  First write to all\n\t\tpossible bits. */\n\t\t*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\n\n\t\t/* Read the value back to see how many bits stuck. */\n\t\tucMaxPriorityValue = *pucFirstUserPriorityRegister;\n\n\t\t/* Use the same mask on the maximum system call priority. */\n\t\tucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\n\n\t\t/* Calculate the maximum acceptable priority group value for the number\n\t\tof bits read back. */\n\t\tulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\n\t\twhile( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\n\t\t{\n\t\t\tulMaxPRIGROUPValue--;\n\t\t\tucMaxPriorityValue <<= ( uint8_t ) 0x01;\n\t\t}\n\n\t\t#ifdef __NVIC_PRIO_BITS\n\t\t{\n\t\t\t/* Check the CMSIS configuration that defines the number of\n\t\t\tpriority bits matches the number of priority bits actually queried\n\t\t\tfrom the hardware. */\n\t\t\tconfigASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\n\t\t}\n\t\t#endif\n\n\t\t#ifdef configPRIO_BITS\n\t\t{\n\t\t\t/* Check the FreeRTOS configuration that defines the number of\n\t\t\tpriority bits matches the number of priority bits actually queried\n\t\t\tfrom the hardware. */\n\t\t\tconfigASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\n\t\t}\n\t\t#endif\n\n\t\t/* Shift the priority group value back to its position within the AIRCR\n\t\tregister. */\n\t\tulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\n\t\tulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\n\n\t\t/* Restore the clobbered interrupt priority register to its original\n\t\tvalue. */\n\t\t*pucFirstUserPriorityRegister = ulOriginalPriority;\n\t}\n\t#endif /* conifgASSERT_DEFINED */\n\n\t/* Make PendSV and SysTick the lowest priority interrupts. */\n\tportNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\n\tportNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\n\n\t/* Start the timer that generates the tick ISR.  Interrupts are disabled\n\there already. */\n\tvPortSetupTimerInterrupt();\n\n\t/* Initialise the critical nesting count ready for the first task. */\n\tuxCriticalNesting = 0;\n\n\t/* Ensure the VFP is enabled - it should be anyway. */\n\tvPortEnableVFP();\n\n\t/* Lazy save always. */\n\t*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\n\n\t/* Start the first task. */\n\tprvPortStartFirstTask();\n\n\t/* Should never get here as the tasks will now be executing!  Call the task\n\texit error function to prevent compiler warnings about a static function\n\tnot being called in the case that the application writer overrides this\n\tfunctionality by defining configTASK_RETURN_ADDRESS.  Call\n\tvTaskSwitchContext() so link time optimisation does not remove the\n\tsymbol. */\n\tvTaskSwitchContext();\n\tprvTaskExitError();\n\n\t/* Should not get here! */\n\treturn 0;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEndScheduler( void )\n{\n\t/* Not implemented in ports where there is nothing to return to.\n\tArtificially force an assert. */\n\tconfigASSERT( uxCriticalNesting == 1000UL );\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortEnterCritical( void )\n{\n\tportDISABLE_INTERRUPTS();\n\tuxCriticalNesting++;\n\n\t/* This is not the interrupt safe version of the enter critical function so\n\tassert() if it is being called from an interrupt context.  Only API\n\tfunctions that end in \"FromISR\" can be used in an interrupt.  Only assert if\n\tthe critical nesting count is 1 to protect against recursive calls if the\n\tassert function also uses a critical section. */\n\tif( uxCriticalNesting == 1 )\n\t{\n\t\tconfigASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortExitCritical( void )\n{\n\tconfigASSERT( uxCriticalNesting );\n\tuxCriticalNesting--;\n\tif( uxCriticalNesting == 0 )\n\t{\n\t\tportENABLE_INTERRUPTS();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortPendSVHandler( void )\n{\n\t/* This is a naked function. */\n\n\t__asm volatile\n\t(\n\t\"\tmrs r0, psp\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldr\tr3, pxCurrentTCBConst\t\t\t\\n\" /* Get the location of the current TCB. */\n\t\"\tldr\tr2, [r3]\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, push high vfp registers. */\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\n\t\"\tvstmdbeq r0!, {s16-s31}\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tstmdb r0!, {r4-r11, r14}\t\t\t\\n\" /* Save the core registers. */\n\t\"\tstr r0, [r2]\t\t\t\t\t\t\\n\" /* Save the new top of stack into the first member of the TCB. */\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tstmdb sp!, {r0, r3}\t\t\t\t\t\\n\"\n\t\"\tmov r0, %0 \t\t\t\t\t\t\t\\n\"\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n\t\"\tdsb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tbl vTaskSwitchContext\t\t\t\t\\n\"\n\t\"\tmov r0, #0\t\t\t\t\t\t\t\\n\"\n\t\"\tmsr basepri, r0\t\t\t\t\t\t\\n\"\n\t\"\tldmia sp!, {r0, r3}\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldr r1, [r3]\t\t\t\t\t\t\\n\" /* The first item in pxCurrentTCB is the task top of stack. */\n\t\"\tldr r0, [r1]\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tldmia r0!, {r4-r11, r14}\t\t\t\\n\" /* Pop the core registers. */\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\ttst r14, #0x10\t\t\t\t\t\t\\n\" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\n\t\"\tit eq\t\t\t\t\t\t\t\t\\n\"\n\t\"\tvldmiaeq r0!, {s16-s31}\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tmsr psp, r0\t\t\t\t\t\t\t\\n\"\n\t\"\tisb\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */\n\t\t#if WORKAROUND_PMU_CM001 == 1\n\t\"\t\t\tpush { r14 }\t\t\t\t\\n\"\n\t\"\t\t\tpop { pc }\t\t\t\t\t\\n\"\n\t\t#endif\n\t#endif\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\tbx r14\t\t\t\t\t\t\t\t\\n\"\n\t\"\t\t\t\t\t\t\t\t\t\t\\n\"\n\t\"\t.align 4\t\t\t\t\t\t\t\\n\"\n\t\"pxCurrentTCBConst: .word pxCurrentTCB\t\\n\"\n\t::\"i\"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\n\t);\n}\n/*-----------------------------------------------------------*/\n\nvoid xPortSysTickHandler( void )\n{\n\t/* The SysTick runs at the lowest interrupt priority, so when this interrupt\n\texecutes all interrupts must be unmasked.  There is therefore no need to\n\tsave and then restore the interrupt mask value as its value is already\n\tknown. */\n\tportDISABLE_INTERRUPTS();\n\t{\n\t\t/* Increment the RTOS tick. */\n\t\tif( xTaskIncrementTick() != pdFALSE )\n\t\t{\n\t\t\t/* A context switch is required.  Context switching is performed in\n\t\t\tthe PendSV interrupt.  Pend the PendSV interrupt. */\n\t\t\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\n\t\t}\n\t}\n\tportENABLE_INTERRUPTS();\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TICKLESS_IDLE == 1 )\n\n\t__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )\n\t{\n\tuint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;\n\tTickType_t xModifiableIdleTime;\n\n\t\t/* Make sure the SysTick reload value does not overflow the counter. */\n\t\tif( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )\n\t\t{\n\t\t\txExpectedIdleTime = xMaximumPossibleSuppressedTicks;\n\t\t}\n\n\t\t/* Stop the SysTick momentarily.  The time the SysTick is stopped for\n\t\tis accounted for as best it can be, but using the tickless mode will\n\t\tinevitably result in some tiny drift of the time maintained by the\n\t\tkernel with respect to calendar time. */\n\t\tportNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t/* Calculate the reload value required to wait xExpectedIdleTime\n\t\ttick periods.  -1 is used because this code will execute part way\n\t\tthrough one of the tick periods. */\n\t\tulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );\n\t\tif( ulReloadValue > ulStoppedTimerCompensation )\n\t\t{\n\t\t\tulReloadValue -= ulStoppedTimerCompensation;\n\t\t}\n\n\t\t/* Enter a critical section but don't use the taskENTER_CRITICAL()\n\t\tmethod as that will mask interrupts that should exit sleep mode. */\n\t\t__asm volatile( \"cpsid i\" ::: \"memory\" );\n\t\t__asm volatile( \"dsb\" );\n\t\t__asm volatile( \"isb\" );\n\n\t\t/* If a context switch is pending or a task is waiting for the scheduler\n\t\tto be unsuspended then abandon the low power entry. */\n\t\tif( eTaskConfirmSleepModeStatus() == eAbortSleep )\n\t\t{\n\t\t\t/* Restart from whatever is left in the count register to complete\n\t\t\tthis tick period. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n\t\t\t/* Restart SysTick. */\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t\t/* Reset the reload register to the value required for normal tick\n\t\t\tperiods. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n\n\t\t\t/* Re-enable interrupts - see comments above the cpsid instruction()\n\t\t\tabove. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Set the new reload value. */\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulReloadValue;\n\n\t\t\t/* Clear the SysTick count flag and set the count value back to\n\t\t\tzero. */\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n\t\t\t/* Restart SysTick. */\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\n\t\t\t/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can\n\t\t\tset its parameter to 0 to indicate that its implementation contains\n\t\t\tits own wait for interrupt or wait for event instruction, and so wfi\n\t\t\tshould not be executed again.  However, the original expected idle\n\t\t\ttime variable must remain unmodified, so a copy is taken. */\n\t\t\txModifiableIdleTime = xExpectedIdleTime;\n\t\t\tconfigPRE_SLEEP_PROCESSING( xModifiableIdleTime );\n\t\t\tif( xModifiableIdleTime > 0 )\n\t\t\t{\n\t\t\t\t__asm volatile( \"dsb\" ::: \"memory\" );\n\t\t\t\t__asm volatile( \"wfi\" );\n\t\t\t\t__asm volatile( \"isb\" );\n\t\t\t}\n\t\t\tconfigPOST_SLEEP_PROCESSING( xExpectedIdleTime );\n\n\t\t\t/* Re-enable interrupts to allow the interrupt that brought the MCU\n\t\t\tout of sleep mode to execute immediately.  see comments above\n\t\t\t__disable_interrupt() call above. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t\t__asm volatile( \"dsb\" );\n\t\t\t__asm volatile( \"isb\" );\n\n\t\t\t/* Disable interrupts again because the clock is about to be stopped\n\t\t\tand interrupts that execute while the clock is stopped will increase\n\t\t\tany slippage between the time maintained by the RTOS and calendar\n\t\t\ttime. */\n\t\t\t__asm volatile( \"cpsid i\" ::: \"memory\" );\n\t\t\t__asm volatile( \"dsb\" );\n\t\t\t__asm volatile( \"isb\" );\n\n\t\t\t/* Disable the SysTick clock without reading the\n\t\t\tportNVIC_SYSTICK_CTRL_REG register to ensure the\n\t\t\tportNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,\n\t\t\tthe time the SysTick is stopped for is accounted for as best it can\n\t\t\tbe, but using the tickless mode will inevitably result in some tiny\n\t\t\tdrift of the time maintained by the kernel with respect to calendar\n\t\t\ttime*/\n\t\t\tportNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );\n\n\t\t\t/* Determine if the SysTick clock has already counted to zero and\n\t\t\tbeen set back to the current reload value (the reload back being\n\t\t\tcorrect for the entire expected idle time) or if the SysTick is yet\n\t\t\tto count to zero (in which case an interrupt other than the SysTick\n\t\t\tmust have brought the system out of sleep mode). */\n\t\t\tif( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )\n\t\t\t{\n\t\t\t\tuint32_t ulCalculatedLoadValue;\n\n\t\t\t\t/* The tick interrupt is already pending, and the SysTick count\n\t\t\t\treloaded with ulReloadValue.  Reset the\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG with whatever remains of this tick\n\t\t\t\tperiod. */\n\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );\n\n\t\t\t\t/* Don't allow a tiny value, or values that have somehow\n\t\t\t\tunderflowed because the post sleep hook did something\n\t\t\t\tthat took too long. */\n\t\t\t\tif( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )\n\t\t\t\t{\n\t\t\t\t\tulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );\n\t\t\t\t}\n\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;\n\n\t\t\t\t/* As the pending tick will be processed as soon as this\n\t\t\t\tfunction exits, the tick value maintained by the tick is stepped\n\t\t\t\tforward by one less than the time spent waiting. */\n\t\t\t\tulCompleteTickPeriods = xExpectedIdleTime - 1UL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Something other than the tick interrupt ended the sleep.\n\t\t\t\tWork out how long the sleep lasted rounded to complete tick\n\t\t\t\tperiods (not the ulReload value which accounted for part\n\t\t\t\tticks). */\n\t\t\t\tulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;\n\n\t\t\t\t/* How many complete tick periods passed while the processor\n\t\t\t\twas waiting? */\n\t\t\t\tulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;\n\n\t\t\t\t/* The reload value is set to whatever fraction of a single tick\n\t\t\t\tperiod remains. */\n\t\t\t\tportNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;\n\t\t\t}\n\n\t\t\t/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG\n\t\t\tagain, then set portNVIC_SYSTICK_LOAD_REG back to its standard\n\t\t\tvalue. */\n\t\t\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\t\t\tportNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;\n\t\t\tvTaskStepTick( ulCompleteTickPeriods );\n\t\t\tportNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;\n\n\t\t\t/* Exit with interrupts enabled. */\n\t\t\t__asm volatile( \"cpsie i\" ::: \"memory\" );\n\t\t}\n\t}\n\n#endif /* #if configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n/*\n * Setup the systick timer to generate the tick interrupts at the required\n * frequency.\n */\n__attribute__(( weak )) void vPortSetupTimerInterrupt( void )\n{\n\t/* Calculate the constants required to configure the tick interrupt. */\n\t#if( configUSE_TICKLESS_IDLE == 1 )\n\t{\n\t\tulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );\n\t\txMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;\n\t\tulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );\n\t}\n\t#endif /* configUSE_TICKLESS_IDLE */\n\n\t/* Stop and clear the SysTick. */\n\tportNVIC_SYSTICK_CTRL_REG = 0UL;\n\tportNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\n\n\t/* Configure SysTick to interrupt at the requested rate. */\n\tportNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\n\tportNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );\n}\n/*-----------------------------------------------------------*/\n\n/* This is a naked function. */\nstatic void vPortEnableVFP( void )\n{\n\t__asm volatile\n\t(\n\t\t\"\tldr.w r0, =0xE000ED88\t\t\\n\" /* The FPU enable bits are in the CPACR. */\n\t\t\"\tldr r1, [r0]\t\t\t\t\\n\"\n\t\t\"\t\t\t\t\t\t\t\t\\n\"\n\t\t\"\torr r1, r1, #( 0xf << 20 )\t\\n\" /* Enable CP10 and CP11 coprocessors, then save back. */\n\t\t\"\tstr r1, [r0]\t\t\t\t\\n\"\n\t\t\"\tbx r14\t\t\t\t\t\t\"\n\t);\n}\n/*-----------------------------------------------------------*/\n\n#if( configASSERT_DEFINED == 1 )\n\n\tvoid vPortValidateInterruptPriority( void )\n\t{\n\tuint32_t ulCurrentInterrupt;\n\tuint8_t ucCurrentPriority;\n\n\t\t/* Obtain the number of the currently executing interrupt. */\n\t\t__asm volatile( \"mrs %0, ipsr\" : \"=r\"( ulCurrentInterrupt ) :: \"memory\" );\n\n\t\t/* Is the interrupt number a user defined interrupt? */\n\t\tif( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\n\t\t{\n\t\t\t/* Look up the interrupt's priority. */\n\t\t\tucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\n\n\t\t\t/* The following assertion will fail if a service routine (ISR) for\n\t\t\tan interrupt that has been assigned a priority above\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\n\t\t\tfunction.  ISR safe FreeRTOS API functions must *only* be called\n\t\t\tfrom interrupts that have been assigned a priority at or below\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\t\tNumerically low interrupt priority numbers represent logically high\n\t\t\tinterrupt priorities, therefore the priority of the interrupt must\n\t\t\tbe set to a value equal to or numerically *higher* than\n\t\t\tconfigMAX_SYSCALL_INTERRUPT_PRIORITY.\n\n\t\t\tInterrupts that\tuse the FreeRTOS API must not be left at their\n\t\t\tdefault priority of\tzero as that is the highest possible priority,\n\t\t\twhich is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\n\t\t\tand\ttherefore also guaranteed to be invalid.\n\n\t\t\tFreeRTOS maintains separate thread and ISR API functions to ensure\n\t\t\tinterrupt entry is as fast and simple as possible.\n\n\t\t\tThe following links provide detailed information:\n\t\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html\n\t\t\thttp://www.freertos.org/FAQHelp.html */\n\t\t\tconfigASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\n\t\t}\n\n\t\t/* Priority grouping:  The interrupt controller (NVIC) allows the bits\n\t\tthat define each interrupt's priority to be split between bits that\n\t\tdefine the interrupt's pre-emption priority bits and bits that define\n\t\tthe interrupt's sub-priority.  For simplicity all bits must be defined\n\t\tto be pre-emption priority bits.  The following assertion will fail if\n\t\tthis is not the case (if some bits represent a sub-priority).\n\n\t\tIf the application only uses CMSIS libraries for interrupt\n\t\tconfiguration then the correct setting can be achieved on all Cortex-M\n\t\tdevices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\n\t\tscheduler.  Note however that some vendor specific peripheral libraries\n\t\tassume a non-zero priority group setting, in which cases using a value\n\t\tof zero will result in unpredictable behaviour. */\n\t\tconfigASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\n\t}\n\n#endif /* configASSERT_DEFINED */\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n\n#ifndef PORTMACRO_H\n#define PORTMACRO_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/*-----------------------------------------------------------\n * Port specific definitions.\n *\n * The settings in this file configure FreeRTOS correctly for the\n * given hardware and compiler.\n *\n * These settings should not be altered.\n *-----------------------------------------------------------\n */\n\n/* Type definitions. */\n#define portCHAR\t\tchar\n#define portFLOAT\t\tfloat\n#define portDOUBLE\t\tdouble\n#define portLONG\t\tlong\n#define portSHORT\t\tshort\n#define portSTACK_TYPE\tuint32_t\n#define portBASE_TYPE\tlong\n\ntypedef portSTACK_TYPE StackType_t;\ntypedef long BaseType_t;\ntypedef unsigned long UBaseType_t;\n\n#if( configUSE_16_BIT_TICKS == 1 )\n\ttypedef uint16_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffff\n#else\n\ttypedef uint32_t TickType_t;\n\t#define portMAX_DELAY ( TickType_t ) 0xffffffffUL\n\n\t/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do\n\tnot need to be guarded with a critical section. */\n\t#define portTICK_TYPE_IS_ATOMIC 1\n#endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specifics. */\n#define portSTACK_GROWTH\t\t\t( -1 )\n#define portTICK_PERIOD_MS\t\t\t( ( TickType_t ) 1000 / configTICK_RATE_HZ )\n#define portBYTE_ALIGNMENT\t\t\t8\n/*-----------------------------------------------------------*/\n\n/* Scheduler utilities. */\n#define portYIELD() \t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Set a PendSV to request a context switch. */\t\t\t\t\t\t\t\t\\\n\tportNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* Barriers are normally not required but do ensure the code is completely\t\\\n\twithin the specified behaviour for the architecture. */\t\t\t\t\t\t\\\n\t__asm volatile( \"dsb\" ::: \"memory\" );\t\t\t\t\t\t\t\t\t\t\\\n\t__asm volatile( \"isb\" );\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n#define portNVIC_INT_CTRL_REG\t\t( * ( ( volatile uint32_t * ) 0xe000ed04 ) )\n#define portNVIC_PENDSVSET_BIT\t\t( 1UL << 28UL )\n#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()\n#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )\n/*-----------------------------------------------------------*/\n\n/* Critical section management. */\nextern void vPortEnterCritical( void );\nextern void vPortExitCritical( void );\n#define portSET_INTERRUPT_MASK_FROM_ISR()\t\tulPortRaiseBASEPRI()\n#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)\tvPortSetBASEPRI(x)\n#define portDISABLE_INTERRUPTS()\t\t\t\tvPortRaiseBASEPRI()\n#define portENABLE_INTERRUPTS()\t\t\t\t\tvPortSetBASEPRI(0)\n#define portENTER_CRITICAL()\t\t\t\t\tvPortEnterCritical()\n#define portEXIT_CRITICAL()\t\t\t\t\t\tvPortExitCritical()\n\n/*-----------------------------------------------------------*/\n\n/* Task function macros as described on the FreeRTOS.org WEB site.  These are\nnot necessary for to use this port.  They are defined so the common demo files\n(which build with all the ports) will build. */\n#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )\n#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )\n/*-----------------------------------------------------------*/\n\n/* Tickless idle/low power functionality. */\n#ifndef portSUPPRESS_TICKS_AND_SLEEP\n\textern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );\n\t#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )\n#endif\n/*-----------------------------------------------------------*/\n\n/* Architecture specific optimisations. */\n#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION\n\t#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1\n#endif\n\n#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1\n\n\t/* Generic helper function. */\n\t__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )\n\t{\n\tuint8_t ucReturn;\n\n\t\t__asm volatile ( \"clz %0, %1\" : \"=r\" ( ucReturn ) : \"r\" ( ulBitmap ) : \"memory\" );\n\t\treturn ucReturn;\n\t}\n\n\t/* Check the configuration. */\n\t#if( configMAX_PRIORITIES > 32 )\n\t\t#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.\n\t#endif\n\n\t/* Store/clear the ready priorities in a bit map. */\n\t#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n#ifdef configASSERT\n\tvoid vPortValidateInterruptPriority( void );\n\t#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() \tvPortValidateInterruptPriority()\n#endif\n\n/* portNOP() is not required by this port. */\n#define portNOP()\n\n#define portINLINE\t__inline\n\n#ifndef portFORCE_INLINE\n\t#define portFORCE_INLINE inline __attribute__(( always_inline))\n#endif\n\nportFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )\n{\nuint32_t ulCurrentInterrupt;\nBaseType_t xReturn;\n\n\t/* Obtain the number of the currently executing interrupt. */\n\t__asm volatile( \"mrs %0, ipsr\" : \"=r\"( ulCurrentInterrupt ) :: \"memory\" );\n\n\tif( ulCurrentInterrupt == 0 )\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\telse\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\n\treturn xReturn;\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortRaiseBASEPRI( void )\n{\nuint32_t ulNewBASEPRI;\n\n\t__asm volatile\n\t(\n\t\t\"\tmov %0, %1\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\n\t\t\"\tmsr basepri, %0\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t:\"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n\t);\n}\n\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )\n{\nuint32_t ulOriginalBASEPRI, ulNewBASEPRI;\n\n\t__asm volatile\n\t(\n\t\t\"\tmrs %0, basepri\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tmov %1, %2\t\t\t\t\t\t\t\t\t\t\t\t\\n\"\t\\\n\t\t\"\tmsr basepri, %1\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tisb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t\"\tdsb\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\n\" \\\n\t\t:\"=r\" (ulOriginalBASEPRI), \"=r\" (ulNewBASEPRI) : \"i\" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : \"memory\"\n\t);\n\n\t/* This return will not be reached but is necessary to prevent compiler\n\twarnings. */\n\treturn ulOriginalBASEPRI;\n}\n/*-----------------------------------------------------------*/\n\nportFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )\n{\n\t__asm volatile\n\t(\n\t\t\"\tmsr basepri, %0\t\" :: \"r\" ( ulNewMaskValue ) : \"memory\"\n\t);\n}\n/*-----------------------------------------------------------*/\n\n#define portMEMORY_BARRIER() __asm volatile( \"\" ::: \"memory\" )\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* PORTMACRO_H */\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/*\n * A sample implementation of pvPortMalloc() and vPortFree() that combines\n * (coalescences) adjacent memory blocks as they are freed, and in so doing\n * limits memory fragmentation.\n *\n * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the\n * memory management pages of http://www.FreeRTOS.org for more information.\n */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )\n\t#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0\n#endif\n\n/* Block sizes must not get too small. */\n#define heapMINIMUM_BLOCK_SIZE\t( ( size_t ) ( xHeapStructSize << 1 ) )\n\n/* Assumes 8bit bytes! */\n#define heapBITS_PER_BYTE\t\t( ( size_t ) 8 )\n\n/* Allocate the memory for the heap. */\n#if( configAPPLICATION_ALLOCATED_HEAP == 1 )\n\t/* The application writer has already defined the array used for the RTOS\n\theap - probably so it can be placed in a special segment or address. */\n\textern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#else\n\tstatic uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];\n#endif /* configAPPLICATION_ALLOCATED_HEAP */\n\n/* Define the linked list structure.  This is used to link free blocks in order\nof their memory address. */\ntypedef struct A_BLOCK_LINK\n{\n\tstruct A_BLOCK_LINK *pxNextFreeBlock;\t/*<< The next free block in the list. */\n\tsize_t xBlockSize;\t\t\t\t\t\t/*<< The size of the free block. */\n} BlockLink_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * Inserts a block of memory that is being freed into the correct position in\n * the list of free memory blocks.  The block being freed will be merged with\n * the block in front it and/or the block behind it if the memory blocks are\n * adjacent to each other.\n */\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );\n\n/*\n * Called automatically to setup the required heap structures the first time\n * pvPortMalloc() is called.\n */\nstatic void prvHeapInit( void );\n\n/*-----------------------------------------------------------*/\n\n/* The size of the structure placed at the beginning of each allocated memory\nblock must by correctly byte aligned. */\nstatic const size_t xHeapStructSize\t= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\n/* Create a couple of list links to mark the start and end of the list. */\nstatic BlockLink_t xStart, *pxEnd = NULL;\n\n/* Keeps track of the number of calls to allocate and free memory as well as the\nnumber of free bytes remaining, but says nothing about fragmentation. */\nstatic size_t xFreeBytesRemaining = 0U;\nstatic size_t xMinimumEverFreeBytesRemaining = 0U;\nstatic size_t xNumberOfSuccessfulAllocations = 0;\nstatic size_t xNumberOfSuccessfulFrees = 0;\n\n/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize\nmember of an BlockLink_t structure is set then the block belongs to the\napplication.  When the bit is free the block is still part of the free heap\nspace. */\nstatic size_t xBlockAllocatedBit = 0;\n\n/*-----------------------------------------------------------*/\n\nvoid *pvPortMalloc( size_t xWantedSize )\n{\nBlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;\nvoid *pvReturn = NULL;\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* If this is the first call to malloc then the heap will require\n\t\tinitialisation to setup the list of free blocks. */\n\t\tif( pxEnd == NULL )\n\t\t{\n\t\t\tprvHeapInit();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Check the requested block size is not so large that the top bit is\n\t\tset.  The top bit of the block size member of the BlockLink_t structure\n\t\tis used to determine who owns the block - the application or the\n\t\tkernel, so it must be free. */\n\t\tif( ( xWantedSize & xBlockAllocatedBit ) == 0 )\n\t\t{\n\t\t\t/* The wanted size is increased so it can contain a BlockLink_t\n\t\t\tstructure in addition to the requested amount of bytes. */\n\t\t\tif( xWantedSize > 0 )\n\t\t\t{\n\t\t\t\txWantedSize += xHeapStructSize;\n\n\t\t\t\t/* Ensure that blocks are always aligned to the required number\n\t\t\t\tof bytes. */\n\t\t\t\tif( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )\n\t\t\t\t{\n\t\t\t\t\t/* Byte alignment required. */\n\t\t\t\t\txWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );\n\t\t\t\t\tconfigASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tif( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )\n\t\t\t{\n\t\t\t\t/* Traverse the list from the start\t(lowest address) block until\n\t\t\t\tone\tof adequate size is found. */\n\t\t\t\tpxPreviousBlock = &xStart;\n\t\t\t\tpxBlock = xStart.pxNextFreeBlock;\n\t\t\t\twhile( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )\n\t\t\t\t{\n\t\t\t\t\tpxPreviousBlock = pxBlock;\n\t\t\t\t\tpxBlock = pxBlock->pxNextFreeBlock;\n\t\t\t\t}\n\n\t\t\t\t/* If the end marker was reached then a block of adequate size\n\t\t\t\twas\tnot found. */\n\t\t\t\tif( pxBlock != pxEnd )\n\t\t\t\t{\n\t\t\t\t\t/* Return the memory space pointed to - jumping over the\n\t\t\t\t\tBlockLink_t structure at its start. */\n\t\t\t\t\tpvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );\n\n\t\t\t\t\t/* This block is being returned for use so must be taken out\n\t\t\t\t\tof the list of free blocks. */\n\t\t\t\t\tpxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;\n\n\t\t\t\t\t/* If the block is larger than required it can be split into\n\t\t\t\t\ttwo. */\n\t\t\t\t\tif( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This block is to be split into two.  Create a new\n\t\t\t\t\t\tblock following the number of bytes requested. The void\n\t\t\t\t\t\tcast is used to prevent byte alignment warnings from the\n\t\t\t\t\t\tcompiler. */\n\t\t\t\t\t\tpxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );\n\t\t\t\t\t\tconfigASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );\n\n\t\t\t\t\t\t/* Calculate the sizes of two blocks split from the\n\t\t\t\t\t\tsingle block. */\n\t\t\t\t\t\tpxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;\n\t\t\t\t\t\tpxBlock->xBlockSize = xWantedSize;\n\n\t\t\t\t\t\t/* Insert the new block into the list of free blocks. */\n\t\t\t\t\t\tprvInsertBlockIntoFreeList( pxNewBlockLink );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\txFreeBytesRemaining -= pxBlock->xBlockSize;\n\n\t\t\t\t\tif( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )\n\t\t\t\t\t{\n\t\t\t\t\t\txMinimumEverFreeBytesRemaining = xFreeBytesRemaining;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* The block is being returned - it is allocated and owned\n\t\t\t\t\tby the application and has no \"next\" block. */\n\t\t\t\t\tpxBlock->xBlockSize |= xBlockAllocatedBit;\n\t\t\t\t\tpxBlock->pxNextFreeBlock = NULL;\n\t\t\t\t\txNumberOfSuccessfulAllocations++;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\ttraceMALLOC( pvReturn, xWantedSize );\n\t}\n\t( void ) xTaskResumeAll();\n\n\t#if( configUSE_MALLOC_FAILED_HOOK == 1 )\n\t{\n\t\tif( pvReturn == NULL )\n\t\t{\n\t\t\textern void vApplicationMallocFailedHook( void );\n\t\t\tvApplicationMallocFailedHook();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif\n\n\tconfigASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortFree( void *pv )\n{\nuint8_t *puc = ( uint8_t * ) pv;\nBlockLink_t *pxLink;\n\n\tif( pv != NULL )\n\t{\n\t\t/* The memory being freed will have an BlockLink_t structure immediately\n\t\tbefore it. */\n\t\tpuc -= xHeapStructSize;\n\n\t\t/* This casting is to keep the compiler from issuing warnings. */\n\t\tpxLink = ( void * ) puc;\n\n\t\t/* Check the block is actually allocated. */\n\t\tconfigASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );\n\t\tconfigASSERT( pxLink->pxNextFreeBlock == NULL );\n\n\t\tif( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )\n\t\t{\n\t\t\tif( pxLink->pxNextFreeBlock == NULL )\n\t\t\t{\n\t\t\t\t/* The block is being returned to the heap - it is no longer\n\t\t\t\tallocated. */\n\t\t\t\tpxLink->xBlockSize &= ~xBlockAllocatedBit;\n\n\t\t\t\tvTaskSuspendAll();\n\t\t\t\t{\n\t\t\t\t\t/* Add this block to the list of free blocks. */\n\t\t\t\t\txFreeBytesRemaining += pxLink->xBlockSize;\n\t\t\t\t\ttraceFREE( pv, pxLink->xBlockSize );\n\t\t\t\t\tprvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );\n\t\t\t\t\txNumberOfSuccessfulFrees++;\n\t\t\t\t}\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetFreeHeapSize( void )\n{\n\treturn xFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xPortGetMinimumEverFreeHeapSize( void )\n{\n\treturn xMinimumEverFreeBytesRemaining;\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortInitialiseBlocks( void )\n{\n\t/* This just exists to keep the linker quiet. */\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvHeapInit( void )\n{\nBlockLink_t *pxFirstFreeBlock;\nuint8_t *pucAlignedHeap;\nsize_t uxAddress;\nsize_t xTotalHeapSize = configTOTAL_HEAP_SIZE;\n\n\t/* Ensure the heap starts on a correctly aligned boundary. */\n\tuxAddress = ( size_t ) ucHeap;\n\n\tif( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )\n\t{\n\t\tuxAddress += ( portBYTE_ALIGNMENT - 1 );\n\t\tuxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\t\txTotalHeapSize -= uxAddress - ( size_t ) ucHeap;\n\t}\n\n\tpucAlignedHeap = ( uint8_t * ) uxAddress;\n\n\t/* xStart is used to hold a pointer to the first item in the list of free\n\tblocks.  The void cast is used to prevent compiler warnings. */\n\txStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;\n\txStart.xBlockSize = ( size_t ) 0;\n\n\t/* pxEnd is used to mark the end of the list of free blocks and is inserted\n\tat the end of the heap space. */\n\tuxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;\n\tuxAddress -= xHeapStructSize;\n\tuxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );\n\tpxEnd = ( void * ) uxAddress;\n\tpxEnd->xBlockSize = 0;\n\tpxEnd->pxNextFreeBlock = NULL;\n\n\t/* To start with there is a single free block that is sized to take up the\n\tentire heap space, minus the space taken by pxEnd. */\n\tpxFirstFreeBlock = ( void * ) pucAlignedHeap;\n\tpxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;\n\tpxFirstFreeBlock->pxNextFreeBlock = pxEnd;\n\n\t/* Only one block exists - and it covers the entire usable heap space. */\n\txMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\txFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;\n\n\t/* Work out the position of the top bit in a size_t variable. */\n\txBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )\n{\nBlockLink_t *pxIterator;\nuint8_t *puc;\n\n\t/* Iterate through the list until a block is found that has a higher address\n\tthan the block being inserted. */\n\tfor( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )\n\t{\n\t\t/* Nothing to do here, just iterate to the right position. */\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted after\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxIterator;\n\tif( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )\n\t{\n\t\tpxIterator->xBlockSize += pxBlockToInsert->xBlockSize;\n\t\tpxBlockToInsert = pxIterator;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t/* Do the block being inserted, and the block it is being inserted before\n\tmake a contiguous block of memory? */\n\tpuc = ( uint8_t * ) pxBlockToInsert;\n\tif( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )\n\t{\n\t\tif( pxIterator->pxNextFreeBlock != pxEnd )\n\t\t{\n\t\t\t/* Form one big block from the two blocks. */\n\t\t\tpxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxBlockToInsert->pxNextFreeBlock = pxEnd;\n\t\t}\n\t}\n\telse\n\t{\n\t\tpxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;\n\t}\n\n\t/* If the block being inserted plugged a gab, so was merged with the block\n\tbefore and the block after, then it's pxNextFreeBlock pointer will have\n\talready been set, and should not be set here as that would make it point\n\tto itself. */\n\tif( pxIterator != pxBlockToInsert )\n\t{\n\t\tpxIterator->pxNextFreeBlock = pxBlockToInsert;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vPortGetHeapStats( HeapStats_t *pxHeapStats )\n{\nBlockLink_t *pxBlock;\nsize_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */\n\n\tvTaskSuspendAll();\n\t{\n\t\tpxBlock = xStart.pxNextFreeBlock;\n\n\t\t/* pxBlock will be NULL if the heap has not been initialised.  The heap\n\t\tis initialised automatically when the first allocation is made. */\n\t\tif( pxBlock != NULL )\n\t\t{\n\t\t\tdo\n\t\t\t{\n\t\t\t\t/* Increment the number of blocks and record the largest block seen\n\t\t\t\tso far. */\n\t\t\t\txBlocks++;\n\n\t\t\t\tif( pxBlock->xBlockSize > xMaxSize )\n\t\t\t\t{\n\t\t\t\t\txMaxSize = pxBlock->xBlockSize;\n\t\t\t\t}\n\n\t\t\t\tif( pxBlock->xBlockSize < xMinSize )\n\t\t\t\t{\n\t\t\t\t\txMinSize = pxBlock->xBlockSize;\n\t\t\t\t}\n\n\t\t\t\t/* Move to the next block in the chain until the last block is\n\t\t\t\treached. */\n\t\t\t\tpxBlock = pxBlock->pxNextFreeBlock;\n\t\t\t} while( pxBlock != pxEnd );\n\t\t}\n\t}\n\txTaskResumeAll();\n\n\tpxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;\n\tpxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;\n\tpxHeapStats->xNumberOfFreeBlocks = xBlocks;\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;\n\t\tpxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;\n\t\tpxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;\n\t\tpxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/queue.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\t#include \"croutine.h\"\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n\n/* Constants used with the cRxLock and cTxLock structure members. */\n#define queueUNLOCKED\t\t\t\t\t( ( int8_t ) -1 )\n#define queueLOCKED_UNMODIFIED\t\t\t( ( int8_t ) 0 )\n\n/* When the Queue_t structure is used to represent a base queue its pcHead and\npcTail members are used as pointers into the queue storage area.  When the\nQueue_t structure is used to represent a mutex pcHead and pcTail pointers are\nnot necessary, and the pcHead pointer is set to NULL to indicate that the\nstructure instead holds a pointer to the mutex holder (if any).  Map alternative\nnames to the pcHead and structure member to ensure the readability of the code\nis maintained.  The QueuePointers_t and SemaphoreData_t types are used to form\na union as their usage is mutually exclusive dependent on what the queue is\nbeing used for. */\n#define uxQueueType\t\t\t\t\t\tpcHead\n#define queueQUEUE_IS_MUTEX\t\t\t\tNULL\n\ntypedef struct QueuePointers\n{\n\tint8_t *pcTail;\t\t\t\t\t/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */\n\tint8_t *pcReadFrom;\t\t\t\t/*< Points to the last place that a queued item was read from when the structure is used as a queue. */\n} QueuePointers_t;\n\ntypedef struct SemaphoreData\n{\n\tTaskHandle_t xMutexHolder;\t\t /*< The handle of the task that holds the mutex. */\n\tUBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */\n} SemaphoreData_t;\n\n/* Semaphores do not actually store or copy data, so have an item size of\nzero. */\n#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )\n#define queueMUTEX_GIVE_BLOCK_TIME\t\t ( ( TickType_t ) 0U )\n\n#if( configUSE_PREEMPTION == 0 )\n\t/* If the cooperative scheduler is being used then a yield should not be\n\tperformed just because a higher priority task has been woken. */\n\t#define queueYIELD_IF_USING_PREEMPTION()\n#else\n\t#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\n#endif\n\n/*\n * Definition of the queue used by the scheduler.\n * Items are queued by copy, not reference.  See the following link for the\n * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html\n */\ntypedef struct QueueDefinition \t\t/* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tint8_t *pcHead;\t\t\t\t\t/*< Points to the beginning of the queue storage area. */\n\tint8_t *pcWriteTo;\t\t\t\t/*< Points to the free next place in the storage area. */\n\n\tunion\n\t{\n\t\tQueuePointers_t xQueue;\t\t/*< Data required exclusively when this structure is used as a queue. */\n\t\tSemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */\n\t} u;\n\n\tList_t xTasksWaitingToSend;\t\t/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */\n\tList_t xTasksWaitingToReceive;\t/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */\n\n\tvolatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */\n\tUBaseType_t uxLength;\t\t\t/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */\n\tUBaseType_t uxItemSize;\t\t\t/*< The size of each items that the queue will hold. */\n\n\tvolatile int8_t cRxLock;\t\t/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n\tvolatile int8_t cTxLock;\t\t/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */\n\n\t#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\t\tuint8_t ucStaticallyAllocated;\t/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n\n\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\tstruct QueueDefinition *pxQueueSetContainer;\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxQueueNumber;\n\t\tuint8_t ucQueueType;\n\t#endif\n\n} xQUEUE;\n\n/* The old xQUEUE name is maintained above then typedefed to the new Queue_t\nname below to enable the use of older kernel aware debuggers. */\ntypedef xQUEUE Queue_t;\n\n/*-----------------------------------------------------------*/\n\n/*\n * The queue registry is just a means for kernel aware debuggers to locate\n * queue structures.  It has no other purpose so is an optional component.\n */\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\t/* The type stored within the queue registry array.  This allows a name\n\tto be assigned to each queue making kernel aware debugging a little\n\tmore user friendly. */\n\ttypedef struct QUEUE_REGISTRY_ITEM\n\t{\n\t\tconst char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\tQueueHandle_t xHandle;\n\t} xQueueRegistryItem;\n\n\t/* The old xQueueRegistryItem name is maintained above then typedefed to the\n\tnew xQueueRegistryItem name below to enable the use of older kernel aware\n\tdebuggers. */\n\ttypedef xQueueRegistryItem QueueRegistryItem_t;\n\n\t/* The queue registry is simply an array of QueueRegistryItem_t structures.\n\tThe pcQueueName member of a structure being NULL is indicative of the\n\tarray position being vacant. */\n\tPRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n\n/*\n * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not\n * prevent an ISR from adding or removing items to the queue, but does prevent\n * an ISR from removing tasks from the queue event lists.  If an ISR finds a\n * queue is locked it will instead increment the appropriate queue lock count\n * to indicate that a task may require unblocking.  When the queue in unlocked\n * these lock counts are inspected, and the appropriate action taken.\n */\nstatic void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any data in a queue.\n *\n * @return pdTRUE if the queue contains no items, otherwise pdFALSE.\n */\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Uses a critical section to determine if there is any space in a queue.\n *\n * @return pdTRUE if there is no space, otherwise pdFALSE;\n */\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item into the queue, either at the front of the queue or the\n * back of the queue.\n */\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;\n\n/*\n * Copies an item out of a queue.\n */\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\t/*\n\t * Checks to see if a queue is a member of a queue set, and if so, notifies\n\t * the queue set that the queue contains data.\n\t */\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n/*\n * Called after a Queue_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;\n\n/*\n * Mutexes are a special type of queue.  When a mutex is created, first the\n * queue is created, then prvInitialiseMutex() is called to configure the queue\n * as a mutex.\n */\n#if( configUSE_MUTEXES == 1 )\n\tstatic void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;\n#endif\n\n#if( configUSE_MUTEXES == 1 )\n\t/*\n\t * If a task waiting for a mutex causes the mutex holder to inherit a\n\t * priority, but the waiting task times out, then the holder should\n\t * disinherit the priority - but only down to the highest priority of any\n\t * other tasks that are waiting for the same mutex.  This function returns\n\t * that priority.\n\t */\n\tstatic UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;\n#endif\n/*-----------------------------------------------------------*/\n\n/*\n * Macro to mark a queue as locked.  Locking a queue prevents an ISR from\n * accessing the queue event lists.\n */\n#define prvLockQueue( pxQueue )\t\t\t\t\t\t\t\t\\\n\ttaskENTER_CRITICAL();\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pxQueue )->cRxLock == queueUNLOCKED )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( pxQueue )->cTxLock == queueUNLOCKED )\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttaskEXIT_CRITICAL()\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )\n{\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\t\tpxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;\n\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\n\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\t\tpxQueue->cRxLock = queueUNLOCKED;\n\t\tpxQueue->cTxLock = queueUNLOCKED;\n\n\t\tif( xNewQueue == pdFALSE )\n\t\t{\n\t\t\t/* If there are tasks blocked waiting to read from the queue, then\n\t\t\tthe tasks will remain blocked as after this function exits the queue\n\t\t\twill still be empty.  If there are tasks blocked waiting to write to\n\t\t\tthe queue, then one should be unblocked as after this function exits\n\t\t\tit will be possible to write to it. */\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Ensure the event queues start in the correct state. */\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToSend ) );\n\t\t\tvListInitialise( &( pxQueue->xTasksWaitingToReceive ) );\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\t/* A value is returned for calling semantic consistency with previous\n\tversions. */\n\treturn pdPASS;\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tQueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )\n\t{\n\tQueue_t *pxNewQueue;\n\n\t\tconfigASSERT( uxQueueLength > ( UBaseType_t ) 0 );\n\n\t\t/* The StaticQueue_t structure and the queue storage area must be\n\t\tsupplied. */\n\t\tconfigASSERT( pxStaticQueue != NULL );\n\n\t\t/* A queue storage area should be provided if the item size is not 0, and\n\t\tshould not be provided if the item size is 0. */\n\t\tconfigASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );\n\t\tconfigASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticQueue_t or StaticSemaphore_t equals the size of\n\t\t\tthe real queue and semaphore structures. */\n\t\t\tvolatile size_t xSize = sizeof( StaticQueue_t );\n\t\t\tconfigASSERT( xSize == sizeof( Queue_t ) );\n\t\t\t( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* The address of a statically allocated queue was passed in, use it.\n\t\tThe address of a statically allocated storage area was also passed in\n\t\tbut is already set. */\n\t\tpxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Queues can be allocated wither statically or dynamically, so\n\t\t\t\tnote this queue was allocated statically in case the queue is\n\t\t\t\tlater deleted. */\n\t\t\t\tpxNewQueue->ucStaticallyAllocated = pdTRUE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\n\t\t\tprvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_CREATE_FAILED( ucQueueType );\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxNewQueue;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tQueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )\n\t{\n\tQueue_t *pxNewQueue;\n\tsize_t xQueueSizeInBytes;\n\tuint8_t *pucQueueStorage;\n\n\t\tconfigASSERT( uxQueueLength > ( UBaseType_t ) 0 );\n\n\t\t/* Allocate enough space to hold the maximum number of items that\n\t\tcan be in the queue at any time.  It is valid for uxItemSize to be\n\t\tzero in the case the queue is used as a semaphore. */\n\t\txQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t/* Allocate the queue and storage area.  Justification for MISRA\n\t\tdeviation as follows:  pvPortMalloc() always ensures returned memory\n\t\tblocks are aligned per the requirements of the MCU stack.  In this case\n\t\tpvPortMalloc() must return a pointer that is guaranteed to meet the\n\t\talignment requirements of the Queue_t structure - which in this case\n\t\tis an int8_t *.  Therefore, whenever the stack alignment requirements\n\t\tare greater than or equal to the pointer to char requirements the cast\n\t\tis safe.  In other cases alignment requirements are not strict (one or\n\t\ttwo bytes). */\n\t\tpxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */\n\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t/* Jump past the queue structure to find the location of the queue\n\t\t\tstorage area. */\n\t\t\tpucQueueStorage = ( uint8_t * ) pxNewQueue;\n\t\t\tpucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* Queues can be created either statically or dynamically, so\n\t\t\t\tnote this task was created dynamically in case it is later\n\t\t\t\tdeleted. */\n\t\t\t\tpxNewQueue->ucStaticallyAllocated = pdFALSE;\n\t\t\t}\n\t\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t\t\tprvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_CREATE_FAILED( ucQueueType );\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxNewQueue;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )\n{\n\t/* Remove compiler warnings about unused parameters should\n\tconfigUSE_TRACE_FACILITY not be set to 1. */\n\t( void ) ucQueueType;\n\n\tif( uxItemSize == ( UBaseType_t ) 0 )\n\t{\n\t\t/* No RAM was allocated for the queue storage area, but PC head cannot\n\t\tbe set to NULL because NULL is used as a key to say the queue is used as\n\t\ta mutex.  Therefore just set pcHead to point to the queue as a benign\n\t\tvalue that is known to be within the memory map. */\n\t\tpxNewQueue->pcHead = ( int8_t * ) pxNewQueue;\n\t}\n\telse\n\t{\n\t\t/* Set the head to the start of the queue storage area. */\n\t\tpxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;\n\t}\n\n\t/* Initialise the queue members as described where the queue type is\n\tdefined. */\n\tpxNewQueue->uxLength = uxQueueLength;\n\tpxNewQueue->uxItemSize = uxItemSize;\n\t( void ) xQueueGenericReset( pxNewQueue, pdTRUE );\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t{\n\t\tpxNewQueue->ucQueueType = ucQueueType;\n\t}\n\t#endif /* configUSE_TRACE_FACILITY */\n\n\t#if( configUSE_QUEUE_SETS == 1 )\n\t{\n\t\tpxNewQueue->pxQueueSetContainer = NULL;\n\t}\n\t#endif /* configUSE_QUEUE_SETS */\n\n\ttraceQUEUE_CREATE( pxNewQueue );\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_MUTEXES == 1 )\n\n\tstatic void prvInitialiseMutex( Queue_t *pxNewQueue )\n\t{\n\t\tif( pxNewQueue != NULL )\n\t\t{\n\t\t\t/* The queue create function will set all the queue structure members\n\t\t\tcorrectly for a generic queue, but this function is creating a\n\t\t\tmutex.  Overwrite those members that need to be set differently -\n\t\t\tin particular the information required for priority inheritance. */\n\t\t\tpxNewQueue->u.xSemaphore.xMutexHolder = NULL;\n\t\t\tpxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;\n\n\t\t\t/* In case this is a recursive mutex. */\n\t\t\tpxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;\n\n\t\t\ttraceCREATE_MUTEX( pxNewQueue );\n\n\t\t\t/* Start with the semaphore in the expected state. */\n\t\t\t( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_MUTEX_FAILED();\n\t\t}\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )\n\t{\n\tQueueHandle_t xNewQueue;\n\tconst UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n\t\txNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );\n\t\tprvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n\t\treturn xNewQueue;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )\n\t{\n\tQueueHandle_t xNewQueue;\n\tconst UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;\n\n\t\t/* Prevent compiler warnings about unused parameters if\n\t\tconfigUSE_TRACE_FACILITY does not equal 1. */\n\t\t( void ) ucQueueType;\n\n\t\txNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );\n\t\tprvInitialiseMutex( ( Queue_t * ) xNewQueue );\n\n\t\treturn xNewQueue;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n\tTaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )\n\t{\n\tTaskHandle_t pxReturn;\n\tQueue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;\n\n\t\t/* This function is called by xSemaphoreGetMutexHolder(), and should not\n\t\tbe called directly.  Note:  This is a good way of determining if the\n\t\tcalling task is the mutex holder, but not a good way of determining the\n\t\tidentity of the mutex holder, as the holder may change between the\n\t\tfollowing critical section exiting and the function returning. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t{\n\t\t\t\tpxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxReturn = NULL;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn pxReturn;\n\t} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )\n\n\tTaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )\n\t{\n\tTaskHandle_t pxReturn;\n\n\t\tconfigASSERT( xSemaphore );\n\n\t\t/* Mutexes cannot be used in interrupt service routines, so the mutex\n\t\tholder should not change in an ISR, and therefore a critical section is\n\t\tnot required here. */\n\t\tif( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t{\n\t\t\tpxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxReturn = NULL;\n\t\t}\n\n\t\treturn pxReturn;\n\t} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */\n\n#endif\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n\tBaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n\t\tconfigASSERT( pxMutex );\n\n\t\t/* If this is the task that holds the mutex then xMutexHolder will not\n\t\tchange outside of this task.  If this task does not hold the mutex then\n\t\tpxMutexHolder can never coincidentally equal the tasks handle, and as\n\t\tthis is the only condition we are interested in it does not matter if\n\t\tpxMutexHolder is accessed simultaneously by another task.  Therefore no\n\t\tmutual exclusion is required to test the pxMutexHolder variable. */\n\t\tif( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n\t\t{\n\t\t\ttraceGIVE_MUTEX_RECURSIVE( pxMutex );\n\n\t\t\t/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to\n\t\t\tthe task handle, therefore no underflow check is required.  Also,\n\t\t\tuxRecursiveCallCount is only modified by the mutex holder, and as\n\t\t\tthere can only be one, no mutual exclusion is required to modify the\n\t\t\tuxRecursiveCallCount member. */\n\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;\n\n\t\t\t/* Has the recursive call count unwound to 0? */\n\t\t\tif( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Return the mutex.  This will automatically unblock any other\n\t\t\t\ttask that might be waiting to access the mutex. */\n\t\t\t\t( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The mutex cannot be given because the calling task is not the\n\t\t\tholder. */\n\t\t\txReturn = pdFAIL;\n\n\t\t\ttraceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_RECURSIVE_MUTEXES == 1 )\n\n\tBaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxMutex = ( Queue_t * ) xMutex;\n\n\t\tconfigASSERT( pxMutex );\n\n\t\t/* Comments regarding mutual exclusion as per those within\n\t\txQueueGiveMutexRecursive(). */\n\n\t\ttraceTAKE_MUTEX_RECURSIVE( pxMutex );\n\n\t\tif( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )\n\t\t{\n\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );\n\n\t\t\t/* pdPASS will only be returned if the mutex was successfully\n\t\t\tobtained.  The calling task may have entered the Blocked state\n\t\t\tbefore reaching here. */\n\t\t\tif( xReturn != pdFAIL )\n\t\t\t{\n\t\t\t\t( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\ttraceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_RECURSIVE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )\n\t{\n\tQueueHandle_t xHandle;\n\n\t\tconfigASSERT( uxMaxCount != 0 );\n\t\tconfigASSERT( uxInitialCount <= uxMaxCount );\n\n\t\txHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n\t\tif( xHandle != NULL )\n\t\t{\n\t\t\t( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE();\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE_FAILED();\n\t\t}\n\n\t\treturn xHandle;\n\t}\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )\n\t{\n\tQueueHandle_t xHandle;\n\n\t\tconfigASSERT( uxMaxCount != 0 );\n\t\tconfigASSERT( uxInitialCount <= uxMaxCount );\n\n\t\txHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );\n\n\t\tif( xHandle != NULL )\n\t\t{\n\t\t\t( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;\n\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE();\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceCREATE_COUNTING_SEMAPHORE_FAILED();\n\t\t}\n\n\t\treturn xHandle;\n\t}\n\n#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )\n{\nBaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904 This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Is there room on the queue now?  The running task must be the\n\t\t\thighest priority task wanting to access the queue.  If the head item\n\t\t\tin the queue is to be overwritten then it does not matter if the\n\t\t\tqueue is full. */\n\t\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n\t\t\t{\n\t\t\t\ttraceQUEUE_SEND( pxQueue );\n\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\tconst UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t\t\txYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* Do not notify the queue set as an existing item\n\t\t\t\t\t\t\twas overwritten in the queue so the number of items\n\t\t\t\t\t\t\tin the queue has not changed. */\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\n\t\t\t\t\t\t\tunblock. A context switch is required. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If there was a task waiting for data to arrive on the\n\t\t\t\t\t\tqueue then unblock it now. */\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\n\t\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to\n\t\t\t\t\t\t\t\tdo this from within the critical section - the\n\t\t\t\t\t\t\t\tkernel takes care of that. */\n\t\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse if( xYieldRequired != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* This path is a special case that will only get\n\t\t\t\t\t\t\texecuted if the task was holding multiple mutexes\n\t\t\t\t\t\t\tand the mutexes were given back in an order that is\n\t\t\t\t\t\t\tdifferent to that in which they were taken. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\txYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t\t\t/* If there was a task waiting for data to arrive on the\n\t\t\t\t\tqueue then unblock it now. */\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The unblocked task has a priority higher than\n\t\t\t\t\t\t\tour own so yield immediately.  Yes it is ok to do\n\t\t\t\t\t\t\tthis from within the critical section - the kernel\n\t\t\t\t\t\t\ttakes care of that. */\n\t\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse if( xYieldRequired != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This path is a special case that will only get\n\t\t\t\t\t\texecuted if the task was holding multiple mutexes and\n\t\t\t\t\t\tthe mutexes were given back in an order that is\n\t\t\t\t\t\tdifferent to that in which they were taken. */\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was full and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\t\t\t/* Return to the original privilege level before exiting\n\t\t\t\t\tthe function. */\n\t\t\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was full and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_SEND( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );\n\n\t\t\t\t/* Unlocking the queue means queue events can effect the\n\t\t\t\tevent list.  It is possible that interrupts occurring now\n\t\t\t\tremove this task from the event list again - but as the\n\t\t\t\tscheduler is suspended the task will go onto the pending\n\t\t\t\tready last instead of the actual ready list. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\n\t\t\t\t/* Resuming the scheduler will move tasks from the pending\n\t\t\t\tready list into the ready list - so it is feasible that this\n\t\t\t\ttask is already in a ready list before it yields - in which\n\t\t\t\tcase the yield will not cause a context switch unless there\n\t\t\t\tis also a higher priority task in the pending ready list. */\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Try again. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The timeout has expired. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\ttraceQUEUE_SEND_FAILED( pxQueue );\n\t\t\treturn errQUEUE_FULL;\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t/* Similar to xQueueGenericSend, except without blocking if there is no room\n\tin the queue.  Also don't directly wake a task that was blocked on a queue\n\tread, instead return a flag to say whether a context switch is required or\n\tnot (i.e. has a task with a higher priority than us been woken by this\n\tpost). */\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueue->cTxLock;\n\t\t\tconst UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\n\n\t\t\t/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a\n\t\t\tsemaphore or mutex.  That means prvCopyDataToQueue() cannot result\n\t\t\tin a task disinheriting a priority and prvCopyDataToQueue() can be\n\t\t\tcalled here even though the disinherit function does not check if\n\t\t\tthe scheduler is suspended before accessing the ready lists. */\n\t\t\t( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );\n\n\t\t\t/* The event list is not altered if the queue is locked.  This will\n\t\t\tbe done when the queue is unlocked later. */\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* Do not notify the queue set as an existing item\n\t\t\t\t\t\t\twas overwritten in the queue so the number of items\n\t\t\t\t\t\t\tin the queue has not changed. */\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The queue is a member of a queue set, and posting\n\t\t\t\t\t\t\tto the queue set caused a higher priority task to\n\t\t\t\t\t\t\tunblock.  A context switch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t\t\n\t\t\t\t\t/* Not used in this path. */\n\t\t\t\t\t( void ) uxPreviousMessagesWaiting;\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was posted while it was locked. */\n\t\t\t\tpxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n\t\t\txReturn = errQUEUE_FULL;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Similar to xQueueGenericSendFromISR() but used with semaphores where the\n\titem size is 0.  Don't directly wake a task that was blocked on a queue\n\tread, instead return a flag to say whether a context switch is required or\n\tnot (i.e. has a task with a higher priority than us been woken by this\n\tpost). */\n\n\tconfigASSERT( pxQueue );\n\n\t/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()\n\tif the item size is not 0. */\n\tconfigASSERT( pxQueue->uxItemSize == 0 );\n\n\t/* Normally a mutex would not be given from an interrupt, especially if\n\tthere is a mutex holder, as priority inheritance makes no sense for an\n\tinterrupts, only tasks. */\n\tconfigASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t/* When the queue is used to implement a semaphore no data is ever\n\t\tmoved through the queue but it is still valid to see if the queue 'has\n\t\tspace'. */\n\t\tif( uxMessagesWaiting < pxQueue->uxLength )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueue->cTxLock;\n\n\t\t\ttraceQUEUE_SEND_FROM_ISR( pxQueue );\n\n\t\t\t/* A task can only have an inherited priority if it is a mutex\n\t\t\tholder - and if there is a mutex holder then the mutex cannot be\n\t\t\tgiven from an ISR.  As this is the ISR version of the function it\n\t\t\tcan be assumed there is no mutex holder and no need to determine if\n\t\t\tpriority disinheritance is needed.  Simply increase the count of\n\t\t\tmessages (semaphores) available. */\n\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n\t\t\t/* The event list is not altered if the queue is locked.  This will\n\t\t\tbe done when the queue is unlocked later. */\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The semaphore is a member of a queue set, and\n\t\t\t\t\t\t\tposting\tto the queue set caused a higher priority\n\t\t\t\t\t\t\ttask to\tunblock.  A context switch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t/* The task waiting has a higher priority so\n\t\t\t\t\t\t\t\trecord that a context switch is required. */\n\t\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_QUEUE_SETS */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was posted while it was locked. */\n\t\t\t\tpxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );\n\t\t\txReturn = errQUEUE_FULL;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Check the pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* The buffer into which data is received can only be NULL if the data size\n\tis zero (so no data is copied into the buffer. */\n\tconfigASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904  This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Data available, remove one item. */\n\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\n\t\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n\t\t\t\t/* There is now space in the queue, were any tasks waiting to\n\t\t\t\tpost to the queue?  If so, unblock the highest priority waiting\n\t\t\t\ttask. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* The timeout has not expired.  If the queue is still empty place\n\t\t\tthe task on the list of tasks waiting to receive from the queue. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The queue contains data again.  Loop back to try and read the\n\t\t\t\tdata. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Timed out.  If there is no data in the queue exit, otherwise loop\n\t\t\tback and attempt to read the data. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nQueue_t * const pxQueue = xQueue;\n\n#if( configUSE_MUTEXES == 1 )\n\tBaseType_t xInheritanceOccurred = pdFALSE;\n#endif\n\n\t/* Check the queue pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* Check this really is a semaphore, in which case the item size will be\n\t0. */\n\tconfigASSERT( pxQueue->uxItemSize == 0 );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904 This function relaxes the coding standard somewhat to allow return\n\tstatements within the function itself.  This is done in the interest\n\tof execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Semaphores are queues with an item size of 0, and where the\n\t\t\tnumber of messages in the queue is the semaphore's count value. */\n\t\t\tconst UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxSemaphoreCount > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttraceQUEUE_RECEIVE( pxQueue );\n\n\t\t\t\t/* Semaphores are queues with a data size of zero and where the\n\t\t\t\tmessages waiting is the semaphore's count.  Reduce the count. */\n\t\t\t\tpxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Record the information required to implement\n\t\t\t\t\t\tpriority inheritance should it become necessary. */\n\t\t\t\t\t\tpxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\t/* Check to see if other tasks are blocked waiting to give the\n\t\t\t\tsemaphore, and if so, unblock the highest priority such task. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* For inheritance to have occurred there must have been an\n\t\t\t\t\tinitial timeout, and an adjusted timeout cannot become 0, as\n\t\t\t\t\tif it were 0 the function would have exited. */\n\t\t\t\t\t#if( configUSE_MUTEXES == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\tconfigASSERT( xInheritanceOccurred == pdFALSE );\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\t\t/* The semaphore count was 0 and no block time is specified\n\t\t\t\t\t(or the block time has expired) so exit now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The semaphore count was 0 and a block time was specified\n\t\t\t\t\tso configure the timeout structure ready to block. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can give to and take from the semaphore\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* A block time is specified and not expired.  If the semaphore\n\t\t\tcount is 0 then enter the Blocked state to wait for a semaphore to\n\t\t\tbecome available.  As semaphores are implemented with queues the\n\t\t\tqueue being empty is equivalent to the semaphore count being 0. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );\n\t\t\t\t\t\t}\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* There was no timeout and the semaphore count was not 0, so\n\t\t\t\tattempt to take the semaphore again. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Timed out. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\t/* If the semaphore count is 0 exit now as the timeout has\n\t\t\texpired.  Otherwise return to attempt to take the semaphore that is\n\t\t\tknown to be available.  As semaphores are implemented by queues the\n\t\t\tqueue being empty is equivalent to the semaphore count being 0. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* xInheritanceOccurred could only have be set if\n\t\t\t\t\tpxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to\n\t\t\t\t\ttest the mutex type again to check it is actually a mutex. */\n\t\t\t\t\tif( xInheritanceOccurred != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tUBaseType_t uxHighestWaitingPriority;\n\n\t\t\t\t\t\t\t/* This task blocking on the mutex caused another\n\t\t\t\t\t\t\ttask to inherit this task's priority.  Now this task\n\t\t\t\t\t\t\thas timed out the priority should be disinherited\n\t\t\t\t\t\t\tagain, but only as low as the next highest priority\n\t\t\t\t\t\t\ttask that is waiting for the same mutex. */\n\t\t\t\t\t\t\tuxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );\n\t\t\t\t\t\t\tvTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );\n\t\t\t\t\t\t}\n\t\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_MUTEXES */\n\n\t\t\t\ttraceQUEUE_RECEIVE_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )\n{\nBaseType_t xEntryTimeSet = pdFALSE;\nTimeOut_t xTimeOut;\nint8_t *pcOriginalReadPosition;\nQueue_t * const pxQueue = xQueue;\n\n\t/* Check the pointer is not NULL. */\n\tconfigASSERT( ( pxQueue ) );\n\n\t/* The buffer into which data is received can only be NULL if the data size\n\tis zero (so no data is copied into the buffer. */\n\tconfigASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* Cannot block if the scheduler is suspended. */\n\t#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\t{\n\t\tconfigASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );\n\t}\n\t#endif\n\n\n\t/*lint -save -e904  This function relaxes the coding standard somewhat to\n\tallow return statements within the function itself.  This is done in the\n\tinterest of execution time efficiency. */\n\tfor( ;; )\n\t{\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t\t/* Is there data in the queue now?  To be running the calling task\n\t\t\tmust be the highest priority task wanting to access the queue. */\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Remember the read position so it can be reset after the data\n\t\t\t\tis read from the queue as this function is only peeking the\n\t\t\t\tdata, not removing it. */\n\t\t\t\tpcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n\n\t\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\t\ttraceQUEUE_PEEK( pxQueue );\n\n\t\t\t\t/* The data is not being removed, so reset the read pointer. */\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n\t\t\t\t/* The data is being left in the queue, so see if there are\n\t\t\t\tany other tasks waiting for the data. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority than this task. */\n\t\t\t\t\t\tqueueYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\treturn pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( xTicksToWait == ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and no block time is specified (or\n\t\t\t\t\tthe block time has expired) so leave now. */\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\ttraceQUEUE_PEEK_FAILED( pxQueue );\n\t\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t\t}\n\t\t\t\telse if( xEntryTimeSet == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The queue was empty and a block time was specified so\n\t\t\t\t\tconfigure the timeout structure ready to enter the blocked\n\t\t\t\t\tstate. */\n\t\t\t\t\tvTaskInternalSetTimeOutState( &xTimeOut );\n\t\t\t\t\txEntryTimeSet = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Entry time was already set. */\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Interrupts and other tasks can send to and receive from the queue\n\t\tnow the critical section has been exited. */\n\n\t\tvTaskSuspendAll();\n\t\tprvLockQueue( pxQueue );\n\n\t\t/* Update the timeout state to see if it has expired yet. */\n\t\tif( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )\n\t\t{\n\t\t\t/* Timeout has not expired yet, check to see if there is data in the\n\t\t\tqueue now, and if not enter the Blocked state to wait for data. */\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceBLOCKING_ON_QUEUE_PEEK( pxQueue );\n\t\t\t\tvTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* There is data in the queue now, so don't enter the blocked\n\t\t\t\tstate, instead return to try and obtain the data. */\n\t\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The timeout has expired.  If there is still no data in the queue\n\t\t\texit, otherwise go back and try to read the data again. */\n\t\t\tprvUnlockQueue( pxQueue );\n\t\t\t( void ) xTaskResumeAll();\n\n\t\t\tif( prvIsQueueEmpty( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceQUEUE_PEEK_FAILED( pxQueue );\n\t\t\t\treturn errQUEUE_EMPTY;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t} /*lint -restore */\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tconst UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\t\t/* Cannot block in an ISR, so check there is data available. */\n\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tconst int8_t cRxLock = pxQueue->cRxLock;\n\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR( pxQueue );\n\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\tpxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;\n\n\t\t\t/* If the queue is locked the event list will not be modified.\n\t\t\tInstead update the lock count so the task that unlocks the queue\n\t\t\twill know that an ISR has removed data while the queue was\n\t\t\tlocked. */\n\t\t\tif( cRxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority than us so\n\t\t\t\t\t\tforce a context switch. */\n\t\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Increment the lock count so the task that unlocks the queue\n\t\t\t\tknows that data was removed while it was locked. */\n\t\t\t\tpxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t\ttraceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )\n{\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\nint8_t *pcOriginalReadPosition;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tconfigASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );\n\tconfigASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: http://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\t/* Cannot block in an ISR, so check there is data available. */\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\ttraceQUEUE_PEEK_FROM_ISR( pxQueue );\n\n\t\t\t/* Remember the read position so it can be reset as nothing is\n\t\t\tactually being removed from the queue. */\n\t\t\tpcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;\n\t\t\tprvCopyDataFromQueue( pxQueue, pvBuffer );\n\t\t\tpxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t\ttraceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\n\n\tconfigASSERT( xQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )\n{\nUBaseType_t uxReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tuxReturn = pxQueue->uxMessagesWaiting;\n\n\treturn uxReturn;\n} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */\n/*-----------------------------------------------------------*/\n\nvoid vQueueDelete( QueueHandle_t xQueue )\n{\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\ttraceQUEUE_DELETE( pxQueue );\n\n\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\t{\n\t\tvQueueUnregisterQueue( pxQueue );\n\t}\n\t#endif\n\n\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )\n\t{\n\t\t/* The queue can only have been allocated dynamically - free it\n\t\tagain. */\n\t\tvPortFree( pxQueue );\n\t}\n\t#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\t{\n\t\t/* The queue could have been allocated statically or dynamically, so\n\t\tcheck before attempting to free the memory. */\n\t\tif( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )\n\t\t{\n\t\t\tvPortFree( pxQueue );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#else\n\t{\n\t\t/* The queue must have been statically allocated, so is not going to be\n\t\tdeleted.  Avoid compiler warnings about the unused parameter. */\n\t\t( void ) pxQueue;\n\t}\n\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )\n\t{\n\t\treturn ( ( Queue_t * ) xQueue )->uxQueueNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )\n\t{\n\t\t( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tuint8_t ucQueueGetQueueType( QueueHandle_t xQueue )\n\t{\n\t\treturn ( ( Queue_t * ) xQueue )->ucQueueType;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_MUTEXES == 1 )\n\n\tstatic UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )\n\t{\n\tUBaseType_t uxHighestPriorityOfWaitingTasks;\n\n\t\t/* If a task waiting for a mutex causes the mutex holder to inherit a\n\t\tpriority, but the waiting task times out, then the holder should\n\t\tdisinherit the priority - but only down to the highest priority of any\n\t\tother tasks that are waiting for the same mutex.  For this purpose,\n\t\treturn the priority of the highest priority task that is waiting for the\n\t\tmutex. */\n\t\tif( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )\n\t\t{\n\t\t\tuxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tuxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;\n\t\t}\n\n\t\treturn uxHighestPriorityOfWaitingTasks;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )\n{\nBaseType_t xReturn = pdFALSE;\nUBaseType_t uxMessagesWaiting;\n\n\t/* This function is called from a critical section. */\n\n\tuxMessagesWaiting = pxQueue->uxMessagesWaiting;\n\n\tif( pxQueue->uxItemSize == ( UBaseType_t ) 0 )\n\t{\n\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t{\n\t\t\tif( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )\n\t\t\t{\n\t\t\t\t/* The mutex is no longer being held. */\n\t\t\t\txReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );\n\t\t\t\tpxQueue->u.xSemaphore.xMutexHolder = NULL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_MUTEXES */\n\t}\n\telse if( xPosition == queueSEND_TO_BACK )\n\t{\n\t\t( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n\t\tpxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\t\tif( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n\t\t{\n\t\t\tpxQueue->pcWriteTo = pxQueue->pcHead;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */\n\t\tpxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;\n\t\tif( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */\n\t\t{\n\t\t\tpxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\tif( xPosition == queueOVERWRITE )\n\t\t{\n\t\t\tif( uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* An item is not being added but overwritten, so subtract\n\t\t\t\tone from the recorded number of items in the queue so when\n\t\t\t\tone is added again below the number of recorded items remains\n\t\t\t\tcorrect. */\n\t\t\t\t--uxMessagesWaiting;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\tpxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )\n{\n\tif( pxQueue->uxItemSize != ( UBaseType_t ) 0 )\n\t{\n\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */\n\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */\n\t\t{\n\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvUnlockQueue( Queue_t * const pxQueue )\n{\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */\n\n\t/* The lock counts contains the number of extra data items placed or\n\tremoved from the queue while the queue was locked.  When a queue is\n\tlocked items can be added or removed, but the event lists cannot be\n\tupdated. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tint8_t cTxLock = pxQueue->cTxLock;\n\n\t\t/* See if data was added to the queue while it was locked. */\n\t\twhile( cTxLock > queueLOCKED_UNMODIFIED )\n\t\t{\n\t\t\t/* Data was posted while the queue was locked.  Are any tasks\n\t\t\tblocked waiting for data to become available? */\n\t\t\t#if ( configUSE_QUEUE_SETS == 1 )\n\t\t\t{\n\t\t\t\tif( pxQueue->pxQueueSetContainer != NULL )\n\t\t\t\t{\n\t\t\t\t\tif( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The queue is a member of a queue set, and posting to\n\t\t\t\t\t\tthe queue set caused a higher priority task to unblock.\n\t\t\t\t\t\tA context switch is required. */\n\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Tasks that are removed from the event list will get\n\t\t\t\t\tadded to the pending ready list as the scheduler is still\n\t\t\t\t\tsuspended. */\n\t\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task waiting has a higher priority so record that a\n\t\t\t\t\t\t\tcontext\tswitch is required. */\n\t\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\t#else /* configUSE_QUEUE_SETS */\n\t\t\t{\n\t\t\t\t/* Tasks that are removed from the event list will get added to\n\t\t\t\tthe pending ready list as the scheduler is still suspended. */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority so record that\n\t\t\t\t\t\ta context switch is required. */\n\t\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif /* configUSE_QUEUE_SETS */\n\n\t\t\t--cTxLock;\n\t\t}\n\n\t\tpxQueue->cTxLock = queueUNLOCKED;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\t/* Do the same for the Rx lock. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tint8_t cRxLock = pxQueue->cRxLock;\n\n\t\twhile( cRxLock > queueLOCKED_UNMODIFIED )\n\t\t{\n\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tvTaskMissedYield();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t--cRxLock;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\n\t\tpxQueue->cRxLock = queueUNLOCKED;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )\n{\nBaseType_t xReturn;\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )\n{\nBaseType_t xReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvIsQueueFull( const Queue_t *pxQueue )\n{\nBaseType_t xReturn;\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )\n{\nBaseType_t xReturn;\nQueue_t * const pxQueue = xQueue;\n\n\tconfigASSERT( pxQueue );\n\tif( pxQueue->uxMessagesWaiting == pxQueue->uxLength )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* If the queue is already full we may have to block.  A critical section\n\t\tis required to prevent an interrupt removing something from the queue\n\t\tbetween the check to see if the queue is full and blocking on the queue. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( prvIsQueueFull( pxQueue ) != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The queue is full - do we want to block or just leave without\n\t\t\t\tposting? */\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* As this is called from a coroutine we cannot block directly, but\n\t\t\t\t\treturn indicating that we need to block. */\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_BLOCKED;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n\t\t\t{\n\t\t\t\t/* There is room in the queue, copy the data into the queue. */\n\t\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Were any co-routines waiting for data to become available? */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\n\t\t\t\t\tinto the ready list as we are within a critical section.\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\n\t\t\t\t\tthe event were caused from within an interrupt. */\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The co-routine waiting has a higher priority so record\n\t\t\t\t\t\tthat a yield might be appropriate. */\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = errQUEUE_FULL;\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* If the queue is already empty we may have to block.  A critical section\n\t\tis required to prevent an interrupt adding something to the queue\n\t\tbetween the check to see if the queue is empty and blocking on the queue. */\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* There are no messages in the queue, do we want to block or just\n\t\t\t\tleave with nothing? */\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* As this is a co-routine we cannot block directly, but return\n\t\t\t\t\tindicating that we need to block. */\n\t\t\t\t\tvCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_BLOCKED;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t\treturn errQUEUE_FULL;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\tportDISABLE_INTERRUPTS();\n\t\t{\n\t\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Data is available from the queue. */\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\t\t\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n\t\t\t\t{\n\t\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t\t--( pxQueue->uxMessagesWaiting );\n\t\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Were any co-routines waiting for space to become available? */\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* In this instance the co-routine could be placed directly\n\t\t\t\t\tinto the ready list as we are within a critical section.\n\t\t\t\t\tInstead the same pending ready list mechanism is used as if\n\t\t\t\t\tthe event were caused from within an interrupt. */\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\txReturn = errQUEUE_YIELD;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\tportENABLE_INTERRUPTS();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )\n\t{\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* Cannot block within an ISR so if there is no space on the queue then\n\t\texit without doing anything. */\n\t\tif( pxQueue->uxMessagesWaiting < pxQueue->uxLength )\n\t\t{\n\t\t\tprvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );\n\n\t\t\t/* We only want to wake one co-routine per ISR, so check that a\n\t\t\tco-routine has not already been woken. */\n\t\t\tif( xCoRoutinePreviouslyWoken == pdFALSE )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\treturn pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xCoRoutinePreviouslyWoken;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_CO_ROUTINES == 1 )\n\n\tBaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* We cannot block from an ISR, so check there is data available. If\n\t\tnot then just leave without doing anything. */\n\t\tif( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* Copy the data from the queue. */\n\t\t\tpxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;\n\t\t\tif( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )\n\t\t\t{\n\t\t\t\tpxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t\t--( pxQueue->uxMessagesWaiting );\n\t\t\t( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );\n\n\t\t\tif( ( *pxCoRoutineWoken ) == pdFALSE )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxCoRoutineWoken = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_CO_ROUTINES */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tvoid vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t ux;\n\n\t\t/* See if there is an empty space in the registry.  A NULL name denotes\n\t\ta free slot. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].pcQueueName == NULL )\n\t\t\t{\n\t\t\t\t/* Store the information on this queue. */\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = pcQueueName;\n\t\t\t\txQueueRegistry[ ux ].xHandle = xQueue;\n\n\t\t\t\ttraceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t}\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tconst char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t ux;\n\tconst char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n\t\t/* Note there is nothing here to protect against another task adding or\n\t\tremoving entries from the registry while it is being searched. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].xHandle == xQueue )\n\t\t\t{\n\t\t\t\tpcReturn = xQueueRegistry[ ux ].pcQueueName;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\treturn pcReturn;\n\t} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\n\tvoid vQueueUnregisterQueue( QueueHandle_t xQueue )\n\t{\n\tUBaseType_t ux;\n\n\t\t/* See if the handle of the queue being unregistered in actually in the\n\t\tregistry. */\n\t\tfor( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )\n\t\t{\n\t\t\tif( xQueueRegistry[ ux ].xHandle == xQueue )\n\t\t\t{\n\t\t\t\t/* Set the name to NULL to show that this slot if free again. */\n\t\t\t\txQueueRegistry[ ux ].pcQueueName = NULL;\n\n\t\t\t\t/* Set the handle to NULL to ensure the same queue handle cannot\n\t\t\t\tappear in the registry twice if it is added, removed, then\n\t\t\t\tadded again. */\n\t\t\t\txQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */\n\n#endif /* configQUEUE_REGISTRY_SIZE */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TIMERS == 1 )\n\n\tvoid vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\n\t{\n\tQueue_t * const pxQueue = xQueue;\n\n\t\t/* This function should not be called by application code hence the\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\n\t\tdesigned for use by kernel code, and has special calling requirements.\n\t\tIt can result in vListInsert() being called on a list that can only\n\t\tpossibly ever have one item in it, so the list will be fast, but even\n\t\tso it should be called with the scheduler locked and not from a critical\n\t\tsection. */\n\n\t\t/* Only do anything if there are no messages in the queue.  This function\n\t\twill not actually cause the task to block, just place it on a blocked\n\t\tlist.  It will not block until the scheduler is unlocked - at which\n\t\ttime a yield will be performed.  If an item is added to the queue while\n\t\tthe queue is locked, and the calling task blocks on the queue, then the\n\t\tcalling task will be immediately unblocked when the queue is unlocked. */\n\t\tprvLockQueue( pxQueue );\n\t\tif( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )\n\t\t{\n\t\t\t/* There is nothing in the queue, block for the specified period. */\n\t\t\tvTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t\tprvUnlockQueue( pxQueue );\n\t}\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\n#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tQueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )\n\t{\n\tQueueSetHandle_t pxQueue;\n\n\t\tpxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );\n\n\t\treturn pxQueue;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tBaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )\n\t\t\t{\n\t\t\t\t/* Cannot add a queue/semaphore to more than one queue set. */\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t\telse if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\t/* Cannot add a queue/semaphore to a queue set if there are already\n\t\t\t\titems in the queue/semaphore. */\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tBaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\n\t{\n\tBaseType_t xReturn;\n\tQueue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;\n\n\t\tif( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )\n\t\t{\n\t\t\t/* The queue was not a member of the set. */\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t\telse if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )\n\t\t{\n\t\t\t/* It is dangerous to remove a queue from a set when the queue is\n\t\t\tnot empty because the queue set will still hold pending events for\n\t\t\tthe queue. */\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\t/* The queue is no longer contained in the set. */\n\t\t\t\tpxQueueOrSemaphore->pxQueueSetContainer = NULL;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t\txReturn = pdPASS;\n\t\t}\n\n\t\treturn xReturn;\n\t} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tQueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )\n\t{\n\tQueueSetMemberHandle_t xReturn = NULL;\n\n\t\t( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tQueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )\n\t{\n\tQueueSetMemberHandle_t xReturn = NULL;\n\n\t\t( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_QUEUE_SETS == 1 )\n\n\tstatic BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )\n\t{\n\tQueue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\t/* This function must be called form a critical section. */\n\n\t\tconfigASSERT( pxQueueSetContainer );\n\t\tconfigASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );\n\n\t\tif( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )\n\t\t{\n\t\t\tconst int8_t cTxLock = pxQueueSetContainer->cTxLock;\n\n\t\t\ttraceQUEUE_SEND( pxQueueSetContainer );\n\n\t\t\t/* The data copied is the handle of the queue that contains data. */\n\t\t\txReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );\n\n\t\t\tif( cTxLock == queueUNLOCKED )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The task waiting has a higher priority. */\n\t\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_QUEUE_SETS */\n\n\n\n\n\n\n\n\n\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/stream_buffer.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdint.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"stream_buffer.h\"\n\n#if( configUSE_TASK_NOTIFICATIONS != 1 )\n\t#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c\n#endif\n\n/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* If the user has not provided application specific Rx notification macros,\nor #defined the notification macros away, them provide default implementations\nthat uses task notifications. */\n/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */\n#ifndef sbRECEIVE_COMPLETED\n\t#define sbRECEIVE_COMPLETED( pxStreamBuffer )\t\t\t\t\t\t\t\t\t\t\\\n\t\tvTaskSuspendAll();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,\t\t\t\\\n\t\t\t\t\t\t\t\t\t  ( uint32_t ) 0,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t  eNoAction );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( void ) xTaskResumeAll();\n#endif /* sbRECEIVE_COMPLETED */\n\n#ifndef sbRECEIVE_COMPLETED_FROM_ISR\n\t#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t  pxHigherPriorityTaskWoken )\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxSavedInterruptStatus;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,\t\\\n\t\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t eNoAction,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\t\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\t\t\t\t\t\\\n\t}\n#endif /* sbRECEIVE_COMPLETED_FROM_ISR */\n\n/* If the user has not provided an application specific Tx notification macro,\nor #defined the notification macro away, them provide a default implementation\nthat uses task notifications. */\n#ifndef sbSEND_COMPLETED\n\t#define sbSEND_COMPLETED( pxStreamBuffer )\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tvTaskSuspendAll();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,\t\t\\\n\t\t\t\t\t\t\t\t\t  ( uint32_t ) 0,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t  eNoAction );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t( void ) xTaskResumeAll();\n#endif /* sbSEND_COMPLETED */\n\n#ifndef sbSEND_COMPLETE_FROM_ISR\n\t#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxSavedInterruptStatus;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\t\t\t\t\t\t\\\n\t\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,\t\\\n\t\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t eNoAction,\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\t\t\t\t\\\n\t\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\t\t\t\t\t\t\\\n\t\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\t\t\t\t\t\\\n\t}\n#endif /* sbSEND_COMPLETE_FROM_ISR */\n/*lint -restore (9026) */\n\n/* The number of bytes used to hold the length of a message in the buffer. */\n#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )\n\n/* Bits stored in the ucFlags field of the stream buffer. */\n#define sbFLAGS_IS_MESSAGE_BUFFER\t\t( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */\n#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */\n\n/*-----------------------------------------------------------*/\n\n/* Structure that hold state information on the buffer. */\ntypedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */\n{\n\tvolatile size_t xTail;\t\t\t\t/* Index to the next item to read within the buffer. */\n\tvolatile size_t xHead;\t\t\t\t/* Index to the next item to write within the buffer. */\n\tsize_t xLength;\t\t\t\t\t\t/* The length of the buffer pointed to by pucBuffer. */\n\tsize_t xTriggerLevelBytes;\t\t\t/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */\n\tvolatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */\n\tvolatile TaskHandle_t xTaskWaitingToSend;\t/* Holds the handle of a task waiting to send data to a message buffer that is full. */\n\tuint8_t *pucBuffer;\t\t\t\t\t/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */\n\tuint8_t ucFlags;\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t uxStreamBufferNumber;\t\t/* Used for tracing purposes. */\n\t#endif\n} StreamBuffer_t;\n\n/*\n * The number of bytes available to be read from the buffer.\n */\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;\n\n/*\n * Add xCount bytes from pucData into the pxStreamBuffer message buffer.\n * Returns the number of bytes written, which will either equal xCount in the\n * success case, or 0 if there was not enough space in the buffer (in which case\n * no data is written into the buffer).\n */\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then reads an entire\n * message out of the buffer.  If the stream buffer is being used as a stream\n * buffer then read as many bytes as possible from the buffer.\n * prvReadBytesFromBuffer() is called to actually extract the bytes from the\n * buffer's data storage area.\n */\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesAvailable,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;\n\n/*\n * If the stream buffer is being used as a message buffer, then writes an entire\n * message to the buffer.  If the stream buffer is being used as a stream\n * buffer then write as many bytes as possible to the buffer.\n * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's\n * data storage area.\n */\nstatic size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tconst void * pvTxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xSpace,\n\t\t\t\t\t\t\t\t\t\tsize_t xRequiredSpace ) PRIVILEGED_FUNCTION;\n\n/*\n * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them\n * to pucData.\n */\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t  uint8_t *pucData,\n\t\t\t\t\t\t\t\t\t  size_t xMaxCount,\n\t\t\t\t\t\t\t\t\t  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to\n * initialise the members of the newly created stream buffer structure.\n */\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  uint8_t * const pucBuffer,\n\t\t\t\t\t\t\t\t\t\t  size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  uint8_t ucFlags ) PRIVILEGED_FUNCTION;\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tStreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )\n\t{\n\tuint8_t *pucAllocatedMemory;\n\tuint8_t ucFlags;\n\n\t\t/* In case the stream buffer is going to be used as a message buffer\n\t\t(that is, it will hold discrete messages with a little meta data that\n\t\tsays how big the next message is) check the buffer will be large enough\n\t\tto hold at least one message. */\n\t\tif( xIsMessageBuffer == pdTRUE )\n\t\t{\n\t\t\t/* Is a message buffer but not statically allocated. */\n\t\t\tucFlags = sbFLAGS_IS_MESSAGE_BUFFER;\n\t\t\tconfigASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Not a message buffer and not statically allocated. */\n\t\t\tucFlags = 0;\n\t\t\tconfigASSERT( xBufferSizeBytes > 0 );\n\t\t}\n\t\tconfigASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n\t\t/* A trigger level of 0 would cause a waiting task to unblock even when\n\t\tthe buffer was empty. */\n\t\tif( xTriggerLevelBytes == ( size_t ) 0 )\n\t\t{\n\t\t\txTriggerLevelBytes = ( size_t ) 1;\n\t\t}\n\n\t\t/* A stream buffer requires a StreamBuffer_t structure and a buffer.\n\t\tBoth are allocated in a single call to pvPortMalloc().  The\n\t\tStreamBuffer_t structure is placed at the start of the allocated memory\n\t\tand the buffer follows immediately after.  The requested size is\n\t\tincremented so the free space is returned as the user would expect -\n\t\tthis is a quirk of the implementation that means otherwise the free\n\t\tspace would be reported as one byte smaller than would be logically\n\t\texpected. */\n\t\txBufferSizeBytes++;\n\t\tpucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */\n\n\t\tif( pucAllocatedMemory != NULL )\n\t\t{\n\t\t\tprvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */\n\t\t\t\t\t\t\t\t\t\t   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */\n\t\t\t\t\t\t\t\t\t\t   xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t   xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t   ucFlags );\n\n\t\t\ttraceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttraceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );\n\t\t}\n\n\t\treturn ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tStreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   BaseType_t xIsMessageBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   uint8_t * const pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t   StaticStreamBuffer_t * const pxStaticStreamBuffer )\n\t{\n\tStreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */\n\tStreamBufferHandle_t xReturn;\n\tuint8_t ucFlags;\n\n\t\tconfigASSERT( pucStreamBufferStorageArea );\n\t\tconfigASSERT( pxStaticStreamBuffer );\n\t\tconfigASSERT( xTriggerLevelBytes <= xBufferSizeBytes );\n\n\t\t/* A trigger level of 0 would cause a waiting task to unblock even when\n\t\tthe buffer was empty. */\n\t\tif( xTriggerLevelBytes == ( size_t ) 0 )\n\t\t{\n\t\t\txTriggerLevelBytes = ( size_t ) 1;\n\t\t}\n\n\t\tif( xIsMessageBuffer != pdFALSE )\n\t\t{\n\t\t\t/* Statically allocated message buffer. */\n\t\t\tucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Statically allocated stream buffer. */\n\t\t\tucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;\n\t\t}\n\n\t\t/* In case the stream buffer is going to be used as a message buffer\n\t\t(that is, it will hold discrete messages with a little meta data that\n\t\tsays how big the next message is) check the buffer will be large enough\n\t\tto hold at least one message. */\n\t\tconfigASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticStreamBuffer_t equals the size of the real\n\t\t\tmessage buffer structure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticStreamBuffer_t );\n\t\t\tconfigASSERT( xSize == sizeof( StreamBuffer_t ) );\n\t\t} /*lint !e529 xSize is referenced is configASSERT() is defined. */\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\tif( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )\n\t\t{\n\t\t\tprvInitialiseNewStreamBuffer( pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  pucStreamBufferStorageArea,\n\t\t\t\t\t\t\t\t\t\t  xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  ucFlags );\n\n\t\t\t/* Remember this was statically allocated in case it is ever deleted\n\t\t\tagain. */\n\t\t\tpxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;\n\n\t\t\ttraceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );\n\n\t\t\txReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = NULL;\n\t\t\ttraceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\nvoid vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * pxStreamBuffer = xStreamBuffer;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\ttraceSTREAM_BUFFER_DELETE( xStreamBuffer );\n\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )\n\t{\n\t\t#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t{\n\t\t\t/* Both the structure and the buffer were allocated using a single call\n\t\t\tto pvPortMalloc(), hence only one call to vPortFree() is required. */\n\t\t\tvPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */\n\t\t}\n\t\t#else\n\t\t{\n\t\t\t/* Should not be possible to get here, ucFlags must be corrupt.\n\t\t\tForce an assert. */\n\t\t\tconfigASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );\n\t\t}\n\t\t#endif\n\t}\n\telse\n\t{\n\t\t/* The structure and buffer were not allocated dynamically and cannot be\n\t\tfreed - just scrub the structure so future use will assert. */\n\t\t( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn = pdFAIL;\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\tUBaseType_t uxStreamBufferNumber;\n#endif\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t{\n\t\t/* Store the stream buffer number so it can be restored after the\n\t\treset. */\n\t\tuxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;\n\t}\n\t#endif\n\n\t/* Can only reset a message buffer if there are no tasks blocked on it. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( pxStreamBuffer->xTaskWaitingToReceive == NULL )\n\t\t{\n\t\t\tif( pxStreamBuffer->xTaskWaitingToSend == NULL )\n\t\t\t{\n\t\t\t\tprvInitialiseNewStreamBuffer( pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->pucBuffer,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->xLength,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t\t  pxStreamBuffer->ucFlags );\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\t\t\t{\n\t\t\t\t\tpxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\ttraceSTREAM_BUFFER_RESET( xStreamBuffer );\n\t\t\t}\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* It is not valid for the trigger level to be 0. */\n\tif( xTriggerLevel == ( size_t ) 0 )\n\t{\n\t\txTriggerLevel = ( size_t ) 1;\n\t}\n\n\t/* The trigger level is the number of bytes that must be in the stream\n\tbuffer before a task that is waiting for data is unblocked. */\n\tif( xTriggerLevel <= pxStreamBuffer->xLength )\n\t{\n\t\tpxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;\n\t\txReturn = pdPASS;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xSpace;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\txSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;\n\txSpace -= pxStreamBuffer->xHead;\n\txSpace -= ( size_t ) 1;\n\n\tif( xSpace >= pxStreamBuffer->xLength )\n\t{\n\t\txSpace -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xSpace;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\txReturn = prvBytesInBuffer( pxStreamBuffer );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t  const void *pvTxData,\n\t\t\t\t\t\t  size_t xDataLengthBytes,\n\t\t\t\t\t\t  TickType_t xTicksToWait )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xSpace = 0;\nsize_t xRequiredSpace = xDataLengthBytes;\nTimeOut_t xTimeOut;\n\n\tconfigASSERT( pvTxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This send function is used to write to both message buffers and stream\n\tbuffers.  If this is a message buffer then the space needed must be\n\tincreased by the amount of bytes needed to store the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\n\t\t/* Overflow? */\n\t\tconfigASSERT( xRequiredSpace > xDataLengthBytes );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\tvTaskSetTimeOutState( &xTimeOut );\n\n\t\tdo\n\t\t{\n\t\t\t/* Wait until the required number of bytes are free in the message\n\t\t\tbuffer. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\n\t\t\t\tif( xSpace < xRequiredSpace )\n\t\t\t\t{\n\t\t\t\t\t/* Clear notification state as going to wait for space. */\n\t\t\t\t\t( void ) xTaskNotifyStateClear( NULL );\n\n\t\t\t\t\t/* Should only be one writer. */\n\t\t\t\t\tconfigASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );\n\t\t\t\t\tpxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\ttaskEXIT_CRITICAL();\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\ttraceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );\n\t\t\t( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n\t\t\tpxStreamBuffer->xTaskWaitingToSend = NULL;\n\n\t\t} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tif( xSpace == ( size_t ) 0 )\n\t{\n\t\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n\tif( xReturn > ( size_t ) 0 )\n\t{\n\t\ttraceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );\n\n\t\t/* Was a task waiting for the data? */\n\t\tif( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n\t\t{\n\t\t\tsbSEND_COMPLETED( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t\ttraceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t const void *pvTxData,\n\t\t\t\t\t\t\t\t size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t BaseType_t * const pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xSpace;\nsize_t xRequiredSpace = xDataLengthBytes;\n\n\tconfigASSERT( pvTxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This send function is used to write to both message buffers and stream\n\tbuffers.  If this is a message buffer then the space needed must be\n\tincreased by the amount of bytes needed to store the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );\n\txReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );\n\n\tif( xReturn > ( size_t ) 0 )\n\t{\n\t\t/* Was a task waiting for the data? */\n\t\tif( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )\n\t\t{\n\t\t\tsbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\ttraceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t   const void * pvTxData,\n\t\t\t\t\t\t\t\t\t   size_t xDataLengthBytes,\n\t\t\t\t\t\t\t\t\t   size_t xSpace,\n\t\t\t\t\t\t\t\t\t   size_t xRequiredSpace )\n{\n\tBaseType_t xShouldWrite;\n\tsize_t xReturn;\n\n\tif( xSpace == ( size_t ) 0 )\n\t{\n\t\t/* Doesn't matter if this is a stream buffer or a message buffer, there\n\t\tis no space to write. */\n\t\txShouldWrite = pdFALSE;\n\t}\n\telse if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )\n\t{\n\t\t/* This is a stream buffer, as opposed to a message buffer, so writing a\n\t\tstream of bytes rather than discrete messages.  Write as many bytes as\n\t\tpossible. */\n\t\txShouldWrite = pdTRUE;\n\t\txDataLengthBytes = configMIN( xDataLengthBytes, xSpace );\n\t}\n\telse if( xSpace >= xRequiredSpace )\n\t{\n\t\t/* This is a message buffer, as opposed to a stream buffer, and there\n\t\tis enough space to write both the message length and the message itself\n\t\tinto the buffer.  Start by writing the length of the data, the data\n\t\titself will be written later in this function. */\n\t\txShouldWrite = pdTRUE;\n\t\t( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );\n\t}\n\telse\n\t{\n\t\t/* There is space available, but not enough space. */\n\t\txShouldWrite = pdFALSE;\n\t}\n\n\tif( xShouldWrite != pdFALSE )\n\t{\n\t\t/* Writes the data itself. */\n\t\txReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */\n\t}\n\telse\n\t{\n\t\txReturn = 0;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t void *pvRxData,\n\t\t\t\t\t\t\t size_t xBufferLengthBytes,\n\t\t\t\t\t\t\t TickType_t xTicksToWait )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n\tconfigASSERT( pvRxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This receive function is used by both message buffers, which store\n\tdiscrete messages, and stream buffers, which store a continuous stream of\n\tbytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\tif( xTicksToWait != ( TickType_t ) 0 )\n\t{\n\t\t/* Checking if there is data and clearing the notification state must be\n\t\tperformed atomically. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n\t\t\t/* If this function was invoked by a message buffer read then\n\t\t\txBytesToStoreMessageLength holds the number of bytes used to hold\n\t\t\tthe length of the next discrete message.  If this function was\n\t\t\tinvoked by a stream buffer read then xBytesToStoreMessageLength will\n\t\t\tbe 0. */\n\t\t\tif( xBytesAvailable <= xBytesToStoreMessageLength )\n\t\t\t{\n\t\t\t\t/* Clear notification state as going to wait for data. */\n\t\t\t\t( void ) xTaskNotifyStateClear( NULL );\n\n\t\t\t\t/* Should only be one reader. */\n\t\t\t\tconfigASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );\n\t\t\t\tpxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\tif( xBytesAvailable <= xBytesToStoreMessageLength )\n\t\t{\n\t\t\t/* Wait for data to be available. */\n\t\t\ttraceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );\n\t\t\t( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );\n\t\t\tpxStreamBuffer->xTaskWaitingToReceive = NULL;\n\n\t\t\t/* Recheck the data available after blocking. */\n\t\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t}\n\n\t/* Whether receiving a discrete message (where xBytesToStoreMessageLength\n\tholds the number of bytes used to store the message length) or a stream of\n\tbytes (where xBytesToStoreMessageLength is zero), the number of bytes\n\tavailable must be greater than xBytesToStoreMessageLength to be able to\n\tread bytes from the buffer. */\n\tif( xBytesAvailable > xBytesToStoreMessageLength )\n\t{\n\t\txReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );\n\n\t\t/* Was a task waiting for space in the buffer? */\n\t\tif( xReceivedLength != ( size_t ) 0 )\n\t\t{\n\t\t\ttraceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );\n\t\t\tsbRECEIVE_COMPLETED( pxStreamBuffer );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\ttraceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReturn, xBytesAvailable, xOriginalTail;\nconfigMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* Ensure the stream buffer is being used as a message buffer. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\t\tif( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )\n\t\t{\n\t\t\t/* The number of bytes available is greater than the number of bytes\n\t\t\trequired to hold the length of the next message, so another message\n\t\t\tis available.  Return its length without removing the length bytes\n\t\t\tfrom the buffer.  A copy of the tail is stored so the buffer can be\n\t\t\treturned to its prior state as the message is not actually being\n\t\t\tremoved from the buffer. */\n\t\t\txOriginalTail = pxStreamBuffer->xTail;\n\t\t\t( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );\n\t\t\txReturn = ( size_t ) xTempReturn;\n\t\t\tpxStreamBuffer->xTail = xOriginalTail;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The minimum amount of bytes in a message buffer is\n\t\t\t( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is\n\t\t\tless than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid\n\t\t\tvalue is 0. */\n\t\t\tconfigASSERT( xBytesAvailable == 0 );\n\t\t\txReturn = 0;\n\t\t}\n\t}\n\telse\n\t{\n\t\txReturn = 0;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nsize_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,\n\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\tBaseType_t * const pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nsize_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;\n\n\tconfigASSERT( pvRxData );\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This receive function is used by both message buffers, which store\n\tdiscrete messages, and stream buffers, which store a continuous stream of\n\tbytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the\n\tmessage. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\txBytesAvailable = prvBytesInBuffer( pxStreamBuffer );\n\n\t/* Whether receiving a discrete message (where xBytesToStoreMessageLength\n\tholds the number of bytes used to store the message length) or a stream of\n\tbytes (where xBytesToStoreMessageLength is zero), the number of bytes\n\tavailable must be greater than xBytesToStoreMessageLength to be able to\n\tread bytes from the buffer. */\n\tif( xBytesAvailable > xBytesToStoreMessageLength )\n\t{\n\t\txReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );\n\n\t\t/* Was a task waiting for space in the buffer? */\n\t\tif( xReceivedLength != ( size_t ) 0 )\n\t\t{\n\t\t\tsbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\ttraceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\tvoid *pvRxData,\n\t\t\t\t\t\t\t\t\t\tsize_t xBufferLengthBytes,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesAvailable,\n\t\t\t\t\t\t\t\t\t\tsize_t xBytesToStoreMessageLength )\n{\nsize_t xOriginalTail, xReceivedLength, xNextMessageLength;\nconfigMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;\n\n\tif( xBytesToStoreMessageLength != ( size_t ) 0 )\n\t{\n\t\t/* A discrete message is being received.  First receive the length\n\t\tof the message.  A copy of the tail is stored so the buffer can be\n\t\treturned to its prior state if the length of the message is too\n\t\tlarge for the provided buffer. */\n\t\txOriginalTail = pxStreamBuffer->xTail;\n\t\t( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );\n\t\txNextMessageLength = ( size_t ) xTempNextMessageLength;\n\n\t\t/* Reduce the number of bytes available by the number of bytes just\n\t\tread out. */\n\t\txBytesAvailable -= xBytesToStoreMessageLength;\n\n\t\t/* Check there is enough space in the buffer provided by the\n\t\tuser. */\n\t\tif( xNextMessageLength > xBufferLengthBytes )\n\t\t{\n\t\t\t/* The user has provided insufficient space to read the message\n\t\t\tso return the buffer to its previous state (so the length of\n\t\t\tthe message is in the buffer again). */\n\t\t\tpxStreamBuffer->xTail = xOriginalTail;\n\t\t\txNextMessageLength = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* A stream of bytes is being received (as opposed to a discrete\n\t\tmessage), so read as many bytes as possible. */\n\t\txNextMessageLength = xBufferLengthBytes;\n\t}\n\n\t/* Read the actual data. */\n\txReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */\n\n\treturn xReceivedLength;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )\n{\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nsize_t xTail;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* True if no bytes are available. */\n\txTail = pxStreamBuffer->xTail;\n\tif( pxStreamBuffer->xHead == xTail )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )\n{\nBaseType_t xReturn;\nsize_t xBytesToStoreMessageLength;\nconst StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\t/* This generic version of the receive function is used by both message\n\tbuffers, which store discrete messages, and stream buffers, which store a\n\tcontinuous stream of bytes.  Discrete messages include an additional\n\tsbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */\n\tif( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )\n\t{\n\t\txBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;\n\t}\n\telse\n\t{\n\t\txBytesToStoreMessageLength = 0;\n\t}\n\n\t/* True if the available space equals zero. */\n\tif( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )\n\t{\n\t\txReturn = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )\n\t\t{\n\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,\n\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\n\t\t\t\t\t\t\t\t\t\t eNoAction,\n\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\n\t\t\t( pxStreamBuffer )->xTaskWaitingToReceive = NULL;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )\n{\nStreamBuffer_t * const pxStreamBuffer = xStreamBuffer;\nBaseType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\tconfigASSERT( pxStreamBuffer );\n\n\tuxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\tif( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )\n\t\t{\n\t\t\t( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,\n\t\t\t\t\t\t\t\t\t\t ( uint32_t ) 0,\n\t\t\t\t\t\t\t\t\t\t eNoAction,\n\t\t\t\t\t\t\t\t\t\t pxHigherPriorityTaskWoken );\n\t\t\t( pxStreamBuffer )->xTaskWaitingToSend = NULL;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t}\n\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )\n{\nsize_t xNextHead, xFirstLength;\n\n\tconfigASSERT( xCount > ( size_t ) 0 );\n\n\txNextHead = pxStreamBuffer->xHead;\n\n\t/* Calculate the number of bytes that can be added in the first write -\n\twhich may be less than the total number of bytes that need to be added if\n\tthe buffer will wrap back to the beginning. */\n\txFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );\n\n\t/* Write as many bytes as can be written in the first write. */\n\tconfigASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );\n\t( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n\t/* If the number of bytes written was less than the number that could be\n\twritten in the first write... */\n\tif( xCount > xFirstLength )\n\t{\n\t\t/* ...then write the remaining bytes to the start of the buffer. */\n\t\tconfigASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );\n\t\t( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\txNextHead += xCount;\n\tif( xNextHead >= pxStreamBuffer->xLength )\n\t{\n\t\txNextHead -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxStreamBuffer->xHead = xNextHead;\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )\n{\nsize_t xCount, xFirstLength, xNextTail;\n\n\t/* Use the minimum of the wanted bytes and the available bytes. */\n\txCount = configMIN( xBytesAvailable, xMaxCount );\n\n\tif( xCount > ( size_t ) 0 )\n\t{\n\t\txNextTail = pxStreamBuffer->xTail;\n\n\t\t/* Calculate the number of bytes that can be read - which may be\n\t\tless than the number wanted if the data wraps around to the start of\n\t\tthe buffer. */\n\t\txFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );\n\n\t\t/* Obtain the number of bytes it is possible to obtain in the first\n\t\tread.  Asserts check bounds of read and write. */\n\t\tconfigASSERT( xFirstLength <= xMaxCount );\n\t\tconfigASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );\n\t\t( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\n\t\t/* If the total number of wanted bytes is greater than the number\n\t\tthat could be read in the first read... */\n\t\tif( xCount > xFirstLength )\n\t\t{\n\t\t\t/*...then read the remaining bytes from the start of the buffer. */\n\t\t\tconfigASSERT( xCount <= xMaxCount );\n\t\t\t( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Move the tail pointer to effectively remove the data read from\n\t\tthe buffer. */\n\t\txNextTail += xCount;\n\n\t\tif( xNextTail >= pxStreamBuffer->xLength )\n\t\t{\n\t\t\txNextTail -= pxStreamBuffer->xLength;\n\t\t}\n\n\t\tpxStreamBuffer->xTail = xNextTail;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )\n{\n/* Returns the distance between xTail and xHead. */\nsize_t xCount;\n\n\txCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;\n\txCount -= pxStreamBuffer->xTail;\n\tif ( xCount >= pxStreamBuffer->xLength )\n\t{\n\t\txCount -= pxStreamBuffer->xLength;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xCount;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,\n\t\t\t\t\t\t\t\t\t\t  uint8_t * const pucBuffer,\n\t\t\t\t\t\t\t\t\t\t  size_t xBufferSizeBytes,\n\t\t\t\t\t\t\t\t\t\t  size_t xTriggerLevelBytes,\n\t\t\t\t\t\t\t\t\t\t  uint8_t ucFlags )\n{\n\t/* Assert here is deliberately writing to the entire buffer to ensure it can\n\tbe written to without generating exceptions, and is setting the buffer to a\n\tknown value to assist in development/debugging. */\n\t#if( configASSERT_DEFINED == 1 )\n\t{\n\t\t/* The value written just has to be identifiable when looking at the\n\t\tmemory.  Don't use 0xA5 as that is the stack fill value and could\n\t\tresult in confusion as to what is actually being observed. */\n\t\tconst BaseType_t xWriteValue = 0x55;\n\t\tconfigASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );\n\t} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */\n\t#endif\n\n\t( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */\n\tpxStreamBuffer->pucBuffer = pucBuffer;\n\tpxStreamBuffer->xLength = xBufferSizeBytes;\n\tpxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;\n\tpxStreamBuffer->ucFlags = ucFlags;\n}\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )\n\t{\n\t\treturn xStreamBuffer->uxStreamBufferNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )\n\t{\n\t\txStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tuint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )\n\t{\n\t\treturn ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/tasks.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n#include <string.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n/* FreeRTOS includes. */\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"timers.h\"\n#include \"stack_macros.h\"\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */\n\n/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting\nfunctions but without including stdio.h here. */\n#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )\n\t/* At the bottom of this file are two optional functions that can be used\n\tto generate human readable text from the raw data generated by the\n\tuxTaskGetSystemState() function.  Note the formatting functions are provided\n\tfor convenience only, and are NOT considered part of the kernel. */\n\t#include <stdio.h>\n#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */\n\n#if( configUSE_PREEMPTION == 0 )\n\t/* If the cooperative scheduler is being used then a yield should not be\n\tperformed just because a higher priority task has been woken. */\n\t#define taskYIELD_IF_USING_PREEMPTION()\n#else\n\t#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()\n#endif\n\n/* Values that can be assigned to the ucNotifyState member of the TCB. */\n#define taskNOT_WAITING_NOTIFICATION\t( ( uint8_t ) 0 )\n#define taskWAITING_NOTIFICATION\t\t( ( uint8_t ) 1 )\n#define taskNOTIFICATION_RECEIVED\t\t( ( uint8_t ) 2 )\n\n/*\n * The value used to fill the stack of a task when the task is created.  This\n * is used purely for checking the high water mark for tasks.\n */\n#define tskSTACK_FILL_BYTE\t( 0xa5U )\n\n/* Bits used to recored how a task's stack and TCB were allocated. */\n#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB \t\t( ( uint8_t ) 0 )\n#define tskSTATICALLY_ALLOCATED_STACK_ONLY \t\t\t( ( uint8_t ) 1 )\n#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB\t\t( ( uint8_t ) 2 )\n\n/* If any of the following are set then task stacks are filled with a known\nvalue so the high water mark can be determined.  If none of the following are\nset then don't fill the stack so there is no unnecessary dependency on memset. */\n#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\t#define tskSET_NEW_STACKS_TO_KNOWN_VALUE\t1\n#else\n\t#define tskSET_NEW_STACKS_TO_KNOWN_VALUE\t0\n#endif\n\n/*\n * Macros used by vListTask to indicate which state a task is in.\n */\n#define tskRUNNING_CHAR\t\t( 'X' )\n#define tskBLOCKED_CHAR\t\t( 'B' )\n#define tskREADY_CHAR\t\t( 'R' )\n#define tskDELETED_CHAR\t\t( 'D' )\n#define tskSUSPENDED_CHAR\t( 'S' )\n\n/*\n * Some kernel aware debuggers require the data the debugger needs access to be\n * global, rather than file scope.\n */\n#ifdef portREMOVE_STATIC_QUALIFIER\n\t#define static\n#endif\n\n/* The name allocated to the Idle task.  This can be overridden by defining\nconfigIDLE_TASK_NAME in FreeRTOSConfig.h. */\n#ifndef configIDLE_TASK_NAME\n\t#define configIDLE_TASK_NAME \"IDLE\"\n#endif\n\n#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is\n\tperformed in a generic way that is not optimised to any particular\n\tmicrocontroller architecture. */\n\n\t/* uxTopReadyPriority holds the priority of the highest priority ready\n\tstate task. */\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( ( uxPriority ) > uxTopReadyPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tuxTopReadyPriority = ( uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t} /* taskRECORD_READY_PRIORITY */\n\n\t/*-----------------------------------------------------------*/\n\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxTopPriority = uxTopReadyPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Find the highest priority queue that contains ready tasks. */\t\t\t\t\t\t\t\t\\\n\t\twhile( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )\t\t\t\t\t\t\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tconfigASSERT( uxTopPriority );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t--uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of\t\t\t\t\t\t\\\n\t\tthe\tsame priority get an equal share of the processor time. */\t\t\t\t\t\t\t\t\t\\\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );\t\t\t\\\n\t\tuxTopReadyPriority = uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK */\n\n\t/*-----------------------------------------------------------*/\n\n\t/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as\n\tthey are only required when a port optimised method of task selection is\n\tbeing used. */\n\t#define taskRESET_READY_PRIORITY( uxPriority )\n\t#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )\n\n#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n\t/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is\n\tperformed in a way that is tailored to the particular microcontroller\n\tarchitecture being used. */\n\n\t/* A port optimised version is provided.  Call the port defined macros. */\n\t#define taskRECORD_READY_PRIORITY( uxPriority )\tportRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )\n\n\t/*-----------------------------------------------------------*/\n\n\t#define taskSELECT_HIGHEST_PRIORITY_TASK()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tUBaseType_t uxTopPriority;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t/* Find the highest priority list that contains ready tasks. */\t\t\t\t\t\t\t\t\\\n\t\tportGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );\t\t\t\t\t\t\t\t\\\n\t\tconfigASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );\t\t\\\n\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );\t\t\\\n\t} /* taskSELECT_HIGHEST_PRIORITY_TASK() */\n\n\t/*-----------------------------------------------------------*/\n\n\t/* A port optimised version is provided, call it only if the TCB being reset\n\tis being referenced from a ready list.  If it is referenced from a delayed\n\tor suspended list then it won't be in a ready list. */\n\t#define taskRESET_READY_PRIORITY( uxPriority )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )\t\\\n\t\t{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\tportRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );\t\t\t\t\t\t\t\\\n\t\t}\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t}\n\n#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */\n\n/*-----------------------------------------------------------*/\n\n/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick\ncount overflows. */\n#define taskSWITCH_DELAYED_LISTS()\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n{\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tList_t *pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\t/* The delayed tasks list should be empty when the lists are switched. */\t\t\t\t\t\t\\\n\tconfigASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );\t\t\t\t\t\t\t\t\t\t\\\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxTemp = pxDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxDelayedTaskList = pxOverflowDelayedTaskList;\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tpxOverflowDelayedTaskList = pxTemp;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\txNumOfOverflows++;\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tprvResetNextTaskUnblockTime();\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n}\n\n/*-----------------------------------------------------------*/\n\n/*\n * Place the task represented by pxTCB into the appropriate ready list for\n * the task.  It is inserted at the end of the list.\n */\n#define prvAddTaskToReadyList( pxTCB )\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttraceMOVED_TASK_TO_READY_STATE( pxTCB );\t\t\t\t\t\t\t\t\t\t\t\t\t\t\\\n\ttaskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );\t\t\t\t\t\t\t\t\t\t\t\t\\\n\tvListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \\\n\ttracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )\n/*-----------------------------------------------------------*/\n\n/*\n * Several functions take an TaskHandle_t parameter that can optionally be NULL,\n * where NULL is used to indicate that the handle of the currently executing\n * task should be used in place of the parameter.  This macro simply checks to\n * see if the parameter is NULL and returns a pointer to the appropriate TCB.\n */\n#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )\n\n/* The item value of the event list item is normally used to hold the priority\nof the task to which it belongs (coded to allow it to be held in reverse\npriority order).  However, it is occasionally borrowed for other purposes.  It\nis important its value is not updated due to a task priority change while it is\nbeing used for another purpose.  The following bit definition is used to inform\nthe scheduler that the value should not be changed - in which case it is the\nresponsibility of whichever module is using the value to ensure it gets set back\nto its original value when it is released. */\n#if( configUSE_16_BIT_TICKS == 1 )\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x8000U\n#else\n\t#define taskEVENT_LIST_ITEM_VALUE_IN_USE\t0x80000000UL\n#endif\n\n/*\n * Task control block.  A task control block (TCB) is allocated for each task,\n * and stores task state information, including a pointer to the task's context\n * (the task's run time environment, including register values)\n */\ntypedef struct tskTaskControlBlock \t\t\t/* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tvolatile StackType_t\t*pxTopOfStack;\t/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */\n\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t\txMPU_SETTINGS\txMPUSettings;\t\t/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */\n\t#endif\n\n\tListItem_t\t\t\txStateListItem;\t/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */\n\tListItem_t\t\t\txEventListItem;\t\t/*< Used to reference a task from an event list. */\n\tUBaseType_t\t\t\tuxPriority;\t\t\t/*< The priority of the task.  0 is the lowest priority. */\n\tStackType_t\t\t\t*pxStack;\t\t\t/*< Points to the start of the stack. */\n\tchar\t\t\t\tpcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\n\t#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )\n\t\tStackType_t\t\t*pxEndOfStack;\t\t/*< Points to the highest valid address for the stack. */\n\t#endif\n\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t\tUBaseType_t\t\tuxCriticalNesting;\t/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */\n\t#endif\n\n\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\tuxTCBNumber;\t\t/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */\n\t\tUBaseType_t\t\tuxTaskNumber;\t\t/*< Stores a number specifically for use by third party trace code. */\n\t#endif\n\n\t#if ( configUSE_MUTEXES == 1 )\n\t\tUBaseType_t\t\tuxBasePriority;\t\t/*< The priority last assigned to the task - used by the priority inheritance mechanism. */\n\t\tUBaseType_t\t\tuxMutexesHeld;\n\t#endif\n\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t\tTaskHookFunction_t pxTaskTag;\n\t#endif\n\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )\n\t\tvoid\t\t\t*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];\n\t#endif\n\n\t#if( configGENERATE_RUN_TIME_STATS == 1 )\n\t\tuint32_t\t\tulRunTimeCounter;\t/*< Stores the amount of time the task has spent in the Running state. */\n\t#endif\n\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t/* Allocate a Newlib reent structure that is specific to this task.\n\t\tNote Newlib support has been included by popular demand, but is not\n\t\tused by the FreeRTOS maintainers themselves.  FreeRTOS is not\n\t\tresponsible for resulting newlib operation.  User must be familiar with\n\t\tnewlib and must provide system-wide implementations of the necessary\n\t\tstubs. Be warned that (at the time of writing) the current newlib design\n\t\timplements a system-wide malloc() that must be provided with locks.\n\n\t\tSee the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n\t\tfor additional information. */\n\t\tstruct\t_reent xNewLib_reent;\n\t#endif\n\n\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\tvolatile uint32_t ulNotifiedValue;\n\t\tvolatile uint8_t ucNotifyState;\n\t#endif\n\n\t/* See the comments in FreeRTOS.h with the definition of\n\ttskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */\n\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\tuint8_t\tucStaticallyAllocated; \t\t/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\tuint8_t ucDelayAborted;\n\t#endif\n\n\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\tint iTaskErrno;\n\t#endif\n\n} tskTCB;\n\n/* The old tskTCB name is maintained above then typedefed to the new TCB_t name\nbelow to enable the use of older kernel aware debuggers. */\ntypedef tskTCB TCB_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\nwhich static variables must be declared volatile. */\nPRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;\n\n/* Lists for ready and blocked tasks. --------------------\nxDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but\ndoing so breaks some kernel aware debuggers and debuggers that rely on removing\nthe static qualifier. */\nPRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList1;\t\t\t\t\t\t/*< Delayed tasks. */\nPRIVILEGED_DATA static List_t xDelayedTaskList2;\t\t\t\t\t\t/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;\t\t\t\t/*< Points to the delayed task list currently being used. */\nPRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;\t\t/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */\nPRIVILEGED_DATA static List_t xPendingReadyList;\t\t\t\t\t\t/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */\n\n#if( INCLUDE_vTaskDelete == 1 )\n\n\tPRIVILEGED_DATA static List_t xTasksWaitingTermination;\t\t\t\t/*< Tasks that have been deleted - but their memory not yet freed. */\n\tPRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;\n\n#endif\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tPRIVILEGED_DATA static List_t xSuspendedTaskList;\t\t\t\t\t/*< Tasks that are currently suspended. */\n\n#endif\n\n/* Global POSIX errno. Its value is changed upon context switching to match\nthe errno of the currently running task. */\n#if ( configUSE_POSIX_ERRNO == 1 )\n\tint FreeRTOS_errno = 0;\n#endif\n\n/* Other file private variables. --------------------------------*/\nPRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks \t= ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xTickCount \t\t\t\t= ( TickType_t ) configINITIAL_TICK_COUNT;\nPRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority \t\t= tskIDLE_PRIORITY;\nPRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning \t\t= pdFALSE;\nPRIVILEGED_DATA static volatile TickType_t xPendedTicks \t\t\t= ( TickType_t ) 0U;\nPRIVILEGED_DATA static volatile BaseType_t xYieldPending \t\t\t= pdFALSE;\nPRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows \t\t\t= ( BaseType_t ) 0;\nPRIVILEGED_DATA static UBaseType_t uxTaskNumber \t\t\t\t\t= ( UBaseType_t ) 0U;\nPRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime\t\t= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */\nPRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle\t\t\t\t\t= NULL;\t\t\t/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */\n\n/* Context switches are held pending while the scheduler is suspended.  Also,\ninterrupts must not manipulate the xStateListItem of a TCB, or any of the\nlists the xStateListItem can be referenced from, if the scheduler is suspended.\nIf an interrupt needs to unblock a task while the scheduler is suspended then it\nmoves the task's event list item into the xPendingReadyList, ready for the\nkernel to move the task from the pending ready list into the real ready list\nwhen the scheduler is unsuspended.  The pending ready list itself can only be\naccessed from a critical section. */\nPRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended\t= ( UBaseType_t ) pdFALSE;\n\n#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\n\t/* Do not move these variables to function scope as doing so prevents the\n\tcode working with debuggers that need to remove the static qualifier. */\n\tPRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;\t/*< Holds the value of a timer/counter the last time a task was switched in. */\n\tPRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;\t\t/*< Holds the total amount of execution time as defined by the run time counter clock. */\n\n#endif\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n/* Callback function prototypes. --------------------------*/\n#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )\n\n\textern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );\n\n#endif\n\n#if( configUSE_TICK_HOOK > 0 )\n\n\textern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */\n\n#endif\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\textern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */\n\n#endif\n\n/* File private functions. --------------------------------*/\n\n/**\n * Utility task that simply returns pdTRUE if the task referenced by xTask is\n * currently in the Suspended state, or pdFALSE if the task referenced by xTask\n * is in any other state.\n */\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*\n * Utility to ready all the lists used by the scheduler.  This is called\n * automatically upon the creation of the first task.\n */\nstatic void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The idle task, which as all tasks is implemented as a never ending loop.\n * The idle task is automatically created and added to the ready lists upon\n * creation of the first user task.\n *\n * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );\n\n/*\n * Utility to free all memory allocated by the scheduler to hold a TCB,\n * including the stack pointed to by the TCB.\n *\n * This does not free memory allocated by the task itself (i.e. memory\n * allocated by calls to pvPortMalloc from within the tasks application code).\n */\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tstatic void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Used only by the idle task.  This checks to see if anything has been placed\n * in the list of tasks waiting to be deleted.  If so the task is cleaned up\n * and its TCB deleted.\n */\nstatic void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The currently executing task is entering the Blocked state.  Add the task to\n * either the current or the overflow delayed task list.\n */\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;\n\n/*\n * Fills an TaskStatus_t structure with information on each task that is\n * referenced from the pxList list (which may be a ready list, a delayed list,\n * a suspended list, etc.).\n *\n * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM\n * NORMAL APPLICATION CODE.\n */\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tstatic UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Searches pxList for a task with name pcNameToQuery - returning a handle to\n * the task if it is found, or NULL if the task is not found.\n */\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tstatic TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * When a task is created, the stack of the task is filled with a known value.\n * This function determines the 'high water mark' of the task stack by\n * determining how much of the stack remains at the original preset value.\n */\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n\tstatic configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Return the amount of time, in ticks, that will pass before the kernel will\n * next move a task from the Blocked state to the Running state.\n *\n * This conditional compilation should use inequality to 0, not equality to 1.\n * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user\n * defined low power mode implementations require configUSE_TICKLESS_IDLE to be\n * set to a value other than 1.\n */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tstatic TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Set xNextTaskUnblockTime to the time at which the next Blocked state task\n * will exit the Blocked state.\n */\nstatic void prvResetNextTaskUnblockTime( void );\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\n\n\t/*\n\t * Helper function used to pad task names with spaces when printing out\n\t * human readable tables of task information.\n\t */\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*\n * Called after a Task_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewTask( \tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName, \t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask,\n\t\t\t\t\t\t\t\t\tTCB_t *pxNewTCB,\n\t\t\t\t\t\t\t\t\tconst MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a new task has been created and initialised to place the task\n * under the control of the scheduler.\n */\nstatic void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;\n\n/*\n * freertos_tasks_c_additions_init() should only be called if the user definable\n * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro\n * called by the function.\n */\n#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\n\tstatic void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;\n\n#endif\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tTaskHandle_t xTaskCreateStatic(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tStackType_t * const puxStackBuffer,\n\t\t\t\t\t\t\t\t\tStaticTask_t * const pxTaskBuffer )\n\t{\n\tTCB_t *pxNewTCB;\n\tTaskHandle_t xReturn;\n\n\t\tconfigASSERT( puxStackBuffer != NULL );\n\t\tconfigASSERT( pxTaskBuffer != NULL );\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticTask_t equals the size of the real task\n\t\t\tstructure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticTask_t );\n\t\t\tconfigASSERT( xSize == sizeof( TCB_t ) );\n\t\t\t( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\n\t\tif( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )\n\t\t{\n\t\t\t/* The memory used for the task's TCB and stack are passed into this\n\t\t\tfunction - use them. */\n\t\t\tpxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */\n\t\t\tpxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;\n\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created statically in case the task is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = NULL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* SUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )\n\n\tBaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n\t\tconfigASSERT( pxTaskDefinition->puxStackBuffer != NULL );\n\t\tconfigASSERT( pxTaskDefinition->pxTaskBuffer != NULL );\n\n\t\tif( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends\n\t\t\ton the implementation of the port malloc function and whether or\n\t\t\tnot static allocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;\n\n\t\t\t/* Store the stack location in the TCB. */\n\t\t\tpxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created statically in case the task is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask(\tpxTaskDefinition->pvTaskCode,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->pcName,\n\t\t\t\t\t\t\t\t\t( uint32_t ) pxTaskDefinition->usStackDepth,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->pvParameters,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->uxPriority,\n\t\t\t\t\t\t\t\t\tpxCreatedTask, pxNewTCB,\n\t\t\t\t\t\t\t\t\tpxTaskDefinition->xRegions );\n\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\txReturn = pdPASS;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */\n/*-----------------------------------------------------------*/\n\n#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tBaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\n\t\tconfigASSERT( pxTaskDefinition->puxStackBuffer );\n\n\t\tif( pxTaskDefinition->puxStackBuffer != NULL )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends\n\t\t\ton the implementation of the port malloc function and whether or\n\t\t\tnot static allocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n\t\t\tif( pxNewTCB != NULL )\n\t\t\t{\n\t\t\t\t/* Store the stack location in the TCB. */\n\t\t\t\tpxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;\n\n\t\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )\n\t\t\t\t{\n\t\t\t\t\t/* Tasks can be created statically or dynamically, so note\n\t\t\t\t\tthis task had a statically allocated stack in case it is\n\t\t\t\t\tlater deleted.  The TCB was allocated dynamically. */\n\t\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;\n\t\t\t\t}\n\t\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\t\tprvInitialiseNewTask(\tpxTaskDefinition->pvTaskCode,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->pcName,\n\t\t\t\t\t\t\t\t\t\t( uint32_t ) pxTaskDefinition->usStackDepth,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->pvParameters,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->uxPriority,\n\t\t\t\t\t\t\t\t\t\tpxCreatedTask, pxNewTCB,\n\t\t\t\t\t\t\t\t\t\tpxTaskDefinition->xRegions );\n\n\t\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tBaseType_t xTaskCreate(\tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\tconst configSTACK_DEPTH_TYPE usStackDepth,\n\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask )\n\t{\n\tTCB_t *pxNewTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If the stack grows down then allocate the stack then the TCB so the stack\n\t\tdoes not grow into the TCB.  Likewise if the stack grows up then allocate\n\t\tthe TCB then the stack. */\n\t\t#if( portSTACK_GROWTH > 0 )\n\t\t{\n\t\t\t/* Allocate space for the TCB.  Where the memory comes from depends on\n\t\t\tthe implementation of the port malloc function and whether or not static\n\t\t\tallocation is being used. */\n\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );\n\n\t\t\tif( pxNewTCB != NULL )\n\t\t\t{\n\t\t\t\t/* Allocate space for the stack used by the task being created.\n\t\t\t\tThe base of the stack memory stored in the TCB so the task can\n\t\t\t\tbe deleted later if required. */\n\t\t\t\tpxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t\tif( pxNewTCB->pxStack == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Could not allocate the stack.  Delete the allocated TCB. */\n\t\t\t\t\tvPortFree( pxNewTCB );\n\t\t\t\t\tpxNewTCB = NULL;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\t#else /* portSTACK_GROWTH */\n\t\t{\n\t\tStackType_t *pxStack;\n\n\t\t\t/* Allocate space for the stack used by the task being created. */\n\t\t\tpxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */\n\n\t\t\tif( pxStack != NULL )\n\t\t\t{\n\t\t\t\t/* Allocate space for the TCB. */\n\t\t\t\tpxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */\n\n\t\t\t\tif( pxNewTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Store the stack location in the TCB. */\n\t\t\t\t\tpxNewTCB->pxStack = pxStack;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The stack cannot be used as the TCB was not created.  Free\n\t\t\t\t\tit again. */\n\t\t\t\t\tvPortFree( pxStack );\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxNewTCB = NULL;\n\t\t\t}\n\t\t}\n\t\t#endif /* portSTACK_GROWTH */\n\n\t\tif( pxNewTCB != NULL )\n\t\t{\n\t\t\t#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */\n\t\t\t{\n\t\t\t\t/* Tasks can be created statically or dynamically, so note this\n\t\t\t\ttask was created dynamically in case it is later deleted. */\n\t\t\t\tpxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;\n\t\t\t}\n\t\t\t#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */\n\n\t\t\tprvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );\n\t\t\tprvAddNewTaskToReadyList( pxNewTCB );\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewTask( \tTaskFunction_t pxTaskCode,\n\t\t\t\t\t\t\t\t\tconst char * const pcName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst uint32_t ulStackDepth,\n\t\t\t\t\t\t\t\t\tvoid * const pvParameters,\n\t\t\t\t\t\t\t\t\tUBaseType_t uxPriority,\n\t\t\t\t\t\t\t\t\tTaskHandle_t * const pxCreatedTask,\n\t\t\t\t\t\t\t\t\tTCB_t *pxNewTCB,\n\t\t\t\t\t\t\t\t\tconst MemoryRegion_t * const xRegions )\n{\nStackType_t *pxTopOfStack;\nUBaseType_t x;\n\n\t#if( portUSING_MPU_WRAPPERS == 1 )\n\t\t/* Should the task be created in privileged mode? */\n\t\tBaseType_t xRunPrivileged;\n\t\tif( ( uxPriority & portPRIVILEGE_BIT ) != 0U )\n\t\t{\n\t\t\txRunPrivileged = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txRunPrivileged = pdFALSE;\n\t\t}\n\t\tuxPriority &= ~portPRIVILEGE_BIT;\n\t#endif /* portUSING_MPU_WRAPPERS == 1 */\n\n\t/* Avoid dependency on memset() if it is not required. */\n\t#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )\n\t{\n\t\t/* Fill the stack with a known value to assist debugging. */\n\t\t( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );\n\t}\n\t#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */\n\n\t/* Calculate the top of stack address.  This depends on whether the stack\n\tgrows from high memory to low (as per the 80x86) or vice versa.\n\tportSTACK_GROWTH is used to make the result positive or negative as required\n\tby the port. */\n\t#if( portSTACK_GROWTH < 0 )\n\t{\n\t\tpxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );\n\t\tpxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */\n\n\t\t/* Check the alignment of the calculated top of stack is correct. */\n\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n\t\t#if( configRECORD_STACK_HIGH_ADDRESS == 1 )\n\t\t{\n\t\t\t/* Also record the stack's high address, which may assist\n\t\t\tdebugging. */\n\t\t\tpxNewTCB->pxEndOfStack = pxTopOfStack;\n\t\t}\n\t\t#endif /* configRECORD_STACK_HIGH_ADDRESS */\n\t}\n\t#else /* portSTACK_GROWTH */\n\t{\n\t\tpxTopOfStack = pxNewTCB->pxStack;\n\n\t\t/* Check the alignment of the stack buffer is correct. */\n\t\tconfigASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );\n\n\t\t/* The other extreme of the stack space is required if stack checking is\n\t\tperformed. */\n\t\tpxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );\n\t}\n\t#endif /* portSTACK_GROWTH */\n\n\t/* Store the task name in the TCB. */\n\tif( pcName != NULL )\n\t{\n\t\tfor( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n\t\t{\n\t\t\tpxNewTCB->pcTaskName[ x ] = pcName[ x ];\n\n\t\t\t/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than\n\t\t\tconfigMAX_TASK_NAME_LEN characters just in case the memory after the\n\t\t\tstring is not accessible (extremely unlikely). */\n\t\t\tif( pcName[ x ] == ( char ) 0x00 )\n\t\t\t{\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\t/* Ensure the name string is terminated in the case that the string length\n\t\twas greater or equal to configMAX_TASK_NAME_LEN. */\n\t\tpxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\\0';\n\t}\n\telse\n\t{\n\t\t/* The task has not been given a name, so just ensure there is a NULL\n\t\tterminator when it is read out. */\n\t\tpxNewTCB->pcTaskName[ 0 ] = 0x00;\n\t}\n\n\t/* This is used as an array index so must ensure it's not too large.  First\n\tremove the privilege bit if one is present. */\n\tif( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n\t{\n\t\tuxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tpxNewTCB->uxPriority = uxPriority;\n\t#if ( configUSE_MUTEXES == 1 )\n\t{\n\t\tpxNewTCB->uxBasePriority = uxPriority;\n\t\tpxNewTCB->uxMutexesHeld = 0;\n\t}\n\t#endif /* configUSE_MUTEXES */\n\n\tvListInitialiseItem( &( pxNewTCB->xStateListItem ) );\n\tvListInitialiseItem( &( pxNewTCB->xEventListItem ) );\n\n\t/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get\n\tback to\tthe containing TCB from a generic item in a list. */\n\tlistSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );\n\n\t/* Event lists are always in priority order. */\n\tlistSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\tlistSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );\n\n\t#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\t{\n\t\tpxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;\n\t}\n\t#endif /* portCRITICAL_NESTING_IN_TCB */\n\n\t#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\t{\n\t\tpxNewTCB->pxTaskTag = NULL;\n\t}\n\t#endif /* configUSE_APPLICATION_TASK_TAG */\n\n\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t{\n\t\tpxNewTCB->ulRunTimeCounter = 0UL;\n\t}\n\t#endif /* configGENERATE_RUN_TIME_STATS */\n\n\t#if ( portUSING_MPU_WRAPPERS == 1 )\n\t{\n\t\tvPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );\n\t}\n\t#else\n\t{\n\t\t/* Avoid compiler warning about unreferenced parameter. */\n\t\t( void ) xRegions;\n\t}\n\t#endif\n\n\t#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\t{\n\t\tfor( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )\n\t\t{\n\t\t\tpxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;\n\t\t}\n\t}\n\t#endif\n\n\t#if ( configUSE_TASK_NOTIFICATIONS == 1 )\n\t{\n\t\tpxNewTCB->ulNotifiedValue = 0;\n\t\tpxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t}\n\t#endif\n\n\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t{\n\t\t/* Initialise this task's Newlib reent structure.\n\t\tSee the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n\t\tfor additional information. */\n\t\t_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );\n\t}\n\t#endif\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t{\n\t\tpxNewTCB->ucDelayAborted = pdFALSE;\n\t}\n\t#endif\n\n\t/* Initialize the TCB stack to look as if the task was already running,\n\tbut had been interrupted by the scheduler.  The return address is set\n\tto the start of the task function. Once the stack has been initialised\n\tthe top of stack variable is updated. */\n\t#if( portUSING_MPU_WRAPPERS == 1 )\n\t{\n\t\t/* If the port has capability to detect stack overflow,\n\t\tpass the stack end address to the stack initialization\n\t\tfunction as well. */\n\t\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\t{\n\t\t\t#if( portSTACK_GROWTH < 0 )\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t\t}\n\t\t\t#else /* portSTACK_GROWTH */\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t\t}\n\t\t\t#endif /* portSTACK_GROWTH */\n\t\t}\n\t\t#else /* portHAS_STACK_OVERFLOW_CHECKING */\n\t\t{\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );\n\t\t}\n\t\t#endif /* portHAS_STACK_OVERFLOW_CHECKING */\n\t}\n\t#else /* portUSING_MPU_WRAPPERS */\n\t{\n\t\t/* If the port has capability to detect stack overflow,\n\t\tpass the stack end address to the stack initialization\n\t\tfunction as well. */\n\t\t#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )\n\t\t{\n\t\t\t#if( portSTACK_GROWTH < 0 )\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );\n\t\t\t}\n\t\t\t#else /* portSTACK_GROWTH */\n\t\t\t{\n\t\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );\n\t\t\t}\n\t\t\t#endif /* portSTACK_GROWTH */\n\t\t}\n\t\t#else /* portHAS_STACK_OVERFLOW_CHECKING */\n\t\t{\n\t\t\tpxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );\n\t\t}\n\t\t#endif /* portHAS_STACK_OVERFLOW_CHECKING */\n\t}\n\t#endif /* portUSING_MPU_WRAPPERS */\n\n\tif( pxCreatedTask != NULL )\n\t{\n\t\t/* Pass the handle out in an anonymous way.  The handle can be used to\n\t\tchange the created task's priority, delete the created task, etc.*/\n\t\t*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )\n{\n\t/* Ensure interrupts don't access the task lists while the lists are being\n\tupdated. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tuxCurrentNumberOfTasks++;\n\t\tif( pxCurrentTCB == NULL )\n\t\t{\n\t\t\t/* There are no other tasks, or all the other tasks are in\n\t\t\tthe suspended state - make this the current task. */\n\t\t\tpxCurrentTCB = pxNewTCB;\n\n\t\t\tif( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\t/* This is the first task to be created so do the preliminary\n\t\t\t\tinitialisation required.  We will not recover if this call\n\t\t\t\tfails, but we will report the failure. */\n\t\t\t\tprvInitialiseTaskLists();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* If the scheduler is not already running, make this task the\n\t\t\tcurrent task if it is the highest priority task to be created\n\t\t\tso far. */\n\t\t\tif( xSchedulerRunning == pdFALSE )\n\t\t\t{\n\t\t\t\tif( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB = pxNewTCB;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\tuxTaskNumber++;\n\n\t\t#if ( configUSE_TRACE_FACILITY == 1 )\n\t\t{\n\t\t\t/* Add a counter into the TCB for tracing only. */\n\t\t\tpxNewTCB->uxTCBNumber = uxTaskNumber;\n\t\t}\n\t\t#endif /* configUSE_TRACE_FACILITY */\n\t\ttraceTASK_CREATE( pxNewTCB );\n\n\t\tprvAddTaskToReadyList( pxNewTCB );\n\n\t\tportSETUP_TCB( pxNewTCB );\n\t}\n\ttaskEXIT_CRITICAL();\n\n\tif( xSchedulerRunning != pdFALSE )\n\t{\n\t\t/* If the created task is of a higher priority than the current task\n\t\tthen it should run now. */\n\t\tif( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )\n\t\t{\n\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tvoid vTaskDelete( TaskHandle_t xTaskToDelete )\n\t{\n\tTCB_t *pxTCB;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the calling task that is\n\t\t\tbeing deleted. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToDelete );\n\n\t\t\t/* Remove task from the ready/delayed list. */\n\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Is the task waiting on an event also? */\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Increment the uxTaskNumber also so kernel aware debuggers can\n\t\t\tdetect that the task lists need re-generating.  This is done before\n\t\t\tportPRE_TASK_DELETE_HOOK() as in the Windows port that macro will\n\t\t\tnot return. */\n\t\t\tuxTaskNumber++;\n\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\t/* A task is deleting itself.  This cannot complete within the\n\t\t\t\ttask itself, as a context switch to another task is required.\n\t\t\t\tPlace the task in the termination list.  The idle task will\n\t\t\t\tcheck the termination list and free up any memory allocated by\n\t\t\t\tthe scheduler for the TCB and stack of the deleted task. */\n\t\t\t\tvListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );\n\n\t\t\t\t/* Increment the ucTasksDeleted variable so the idle task knows\n\t\t\t\tthere is a task that has been deleted and that it should therefore\n\t\t\t\tcheck the xTasksWaitingTermination list. */\n\t\t\t\t++uxDeletedTasksWaitingCleanUp;\n\n\t\t\t\t/* Call the delete hook before portPRE_TASK_DELETE_HOOK() as\n\t\t\t\tportPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */\n\t\t\t\ttraceTASK_DELETE( pxTCB );\n\n\t\t\t\t/* The pre-delete hook is primarily for the Windows simulator,\n\t\t\t\tin which Windows specific clean up operations are performed,\n\t\t\t\tafter which it is not possible to yield away from this task -\n\t\t\t\thence xYieldPending is used to latch that a context switch is\n\t\t\t\trequired. */\n\t\t\t\tportPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t--uxCurrentNumberOfTasks;\n\t\t\t\ttraceTASK_DELETE( pxTCB );\n\t\t\t\tprvDeleteTCB( pxTCB );\n\n\t\t\t\t/* Reset the next expected unblock time in case it referred to\n\t\t\t\tthe task that has just been deleted. */\n\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\t/* Force a reschedule if it is the currently running task that has just\n\t\tbeen deleted. */\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelayUntil == 1 )\n\n\tvoid vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )\n\t{\n\tTickType_t xTimeToWake;\n\tBaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;\n\n\t\tconfigASSERT( pxPreviousWakeTime );\n\t\tconfigASSERT( ( xTimeIncrement > 0U ) );\n\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Minor optimisation.  The tick count cannot change in this\n\t\t\tblock. */\n\t\t\tconst TickType_t xConstTickCount = xTickCount;\n\n\t\t\t/* Generate the tick time at which the task wants to wake. */\n\t\t\txTimeToWake = *pxPreviousWakeTime + xTimeIncrement;\n\n\t\t\tif( xConstTickCount < *pxPreviousWakeTime )\n\t\t\t{\n\t\t\t\t/* The tick count has overflowed since this function was\n\t\t\t\tlasted called.  In this case the only time we should ever\n\t\t\t\tactually delay is if the wake time has also\toverflowed,\n\t\t\t\tand the wake time is greater than the tick time.  When this\n\t\t\t\tis the case it is as if neither time had overflowed. */\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )\n\t\t\t\t{\n\t\t\t\t\txShouldDelay = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The tick time has not overflowed.  In this case we will\n\t\t\t\tdelay if either the wake time has overflowed, and/or the\n\t\t\t\ttick time is less than the wake time. */\n\t\t\t\tif( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )\n\t\t\t\t{\n\t\t\t\t\txShouldDelay = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\n\t\t\t/* Update the wake time ready for the next call. */\n\t\t\t*pxPreviousWakeTime = xTimeToWake;\n\n\t\t\tif( xShouldDelay != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceTASK_DELAY_UNTIL( xTimeToWake );\n\n\t\t\t\t/* prvAddCurrentTaskToDelayedList() needs the block time, not\n\t\t\t\tthe time to wake, so subtract the current tick count. */\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\txAlreadyYielded = xTaskResumeAll();\n\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\n\t\thave put ourselves to sleep. */\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelayUntil */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelay == 1 )\n\n\tvoid vTaskDelay( const TickType_t xTicksToDelay )\n\t{\n\tBaseType_t xAlreadyYielded = pdFALSE;\n\n\t\t/* A delay time of zero just forces a reschedule. */\n\t\tif( xTicksToDelay > ( TickType_t ) 0U )\n\t\t{\n\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\tvTaskSuspendAll();\n\t\t\t{\n\t\t\t\ttraceTASK_DELAY();\n\n\t\t\t\t/* A task that is removed from the event list while the\n\t\t\t\tscheduler is suspended will not get placed in the ready\n\t\t\t\tlist or removed from the blocked list until the scheduler\n\t\t\t\tis resumed.\n\n\t\t\t\tThis task cannot be in an event list as it is the currently\n\t\t\t\texecuting task. */\n\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );\n\t\t\t}\n\t\t\txAlreadyYielded = xTaskResumeAll();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* Force a reschedule if xTaskResumeAll has not already done so, we may\n\t\thave put ourselves to sleep. */\n\t\tif( xAlreadyYielded == pdFALSE )\n\t\t{\n\t\t\tportYIELD_WITHIN_API();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskDelay */\n/*-----------------------------------------------------------*/\n\n#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )\n\n\teTaskState eTaskGetState( TaskHandle_t xTask )\n\t{\n\teTaskState eReturn;\n\tList_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;\n\tconst TCB_t * const pxTCB = xTask;\n\n\t\tconfigASSERT( pxTCB );\n\n\t\tif( pxTCB == pxCurrentTCB )\n\t\t{\n\t\t\t/* The task calling this function is querying its own state. */\n\t\t\teReturn = eRunning;\n\t\t}\n\t\telse\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tpxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );\n\t\t\t\tpxDelayedList = pxDelayedTaskList;\n\t\t\t\tpxOverflowedDelayedList = pxOverflowDelayedTaskList;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\tif( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )\n\t\t\t{\n\t\t\t\t/* The task being queried is referenced from one of the Blocked\n\t\t\t\tlists. */\n\t\t\t\teReturn = eBlocked;\n\t\t\t}\n\n\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\telse if( pxStateList == &xSuspendedTaskList )\n\t\t\t\t{\n\t\t\t\t\t/* The task being queried is referenced from the suspended\n\t\t\t\t\tlist.  Is it genuinely suspended or is it blocked\n\t\t\t\t\tindefinitely? */\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* The task does not appear on the event list item of\n\t\t\t\t\t\t\tand of the RTOS objects, but could still be in the\n\t\t\t\t\t\t\tblocked state if it is waiting on its notification\n\t\t\t\t\t\t\trather than waiting on an object. */\n\t\t\t\t\t\t\tif( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\teReturn = eBlocked;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\teReturn = eSuspended;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\teReturn = eSuspended;\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\teReturn = eBlocked;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if ( INCLUDE_vTaskDelete == 1 )\n\t\t\t\telse if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )\n\t\t\t\t{\n\t\t\t\t\t/* The task being queried is referenced from the deleted\n\t\t\t\t\ttasks list, or it is not referenced from any lists at\n\t\t\t\t\tall. */\n\t\t\t\t\teReturn = eDeleted;\n\t\t\t\t}\n\t\t\t#endif\n\n\t\t\telse /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */\n\t\t\t{\n\t\t\t\t/* If the task is not in any other state, it must be in the\n\t\t\t\tReady (including pending ready) state. */\n\t\t\t\teReturn = eReady;\n\t\t\t}\n\t\t}\n\n\t\treturn eReturn;\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_eTaskGetState */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n\tUBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )\n\t{\n\tTCB_t const *pxTCB;\n\tUBaseType_t uxReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the task\n\t\t\tthat called uxTaskPriorityGet() that is being queried. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\t\t\tuxReturn = pxTCB->uxPriority;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskPriorityGet == 1 )\n\n\tUBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )\n\t{\n\tTCB_t const *pxTCB;\n\tUBaseType_t uxReturn, uxSavedInterruptState;\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttps://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tuxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the calling\n\t\t\ttask that is being queried. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\t\t\tuxReturn = pxTCB->uxPriority;\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskPriorityGet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskPrioritySet == 1 )\n\n\tvoid vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )\n\t{\n\tTCB_t *pxTCB;\n\tUBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;\n\tBaseType_t xYieldRequired = pdFALSE;\n\n\t\tconfigASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );\n\n\t\t/* Ensure the new priority is valid. */\n\t\tif( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )\n\t\t{\n\t\t\tuxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the priority of the calling\n\t\t\ttask that is being changed. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t\ttraceTASK_PRIORITY_SET( pxTCB, uxNewPriority );\n\n\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t{\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxBasePriority;\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\tuxCurrentBasePriority = pxTCB->uxPriority;\n\t\t\t}\n\t\t\t#endif\n\n\t\t\tif( uxCurrentBasePriority != uxNewPriority )\n\t\t\t{\n\t\t\t\t/* The priority change may have readied a task of higher\n\t\t\t\tpriority than the calling task. */\n\t\t\t\tif( uxNewPriority > uxCurrentBasePriority )\n\t\t\t\t{\n\t\t\t\t\tif( pxTCB != pxCurrentTCB )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The priority of a task other than the currently\n\t\t\t\t\t\trunning task is being raised.  Is the priority being\n\t\t\t\t\t\traised above that of the running task? */\n\t\t\t\t\t\tif( uxNewPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The priority of the running task is being raised,\n\t\t\t\t\t\tbut the running task must already be the highest\n\t\t\t\t\t\tpriority task able to run so no yield is required. */\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse if( pxTCB == pxCurrentTCB )\n\t\t\t\t{\n\t\t\t\t\t/* Setting the priority of the running task down means\n\t\t\t\t\tthere may now be another task of higher priority that\n\t\t\t\t\tis ready to execute. */\n\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Setting the priority of any other task down does not\n\t\t\t\t\trequire a yield as the running task must be above the\n\t\t\t\t\tnew priority of the task being modified. */\n\t\t\t\t}\n\n\t\t\t\t/* Remember the ready list the task might be referenced from\n\t\t\t\tbefore its uxPriority member is changed so the\n\t\t\t\ttaskRESET_READY_PRIORITY() macro can function correctly. */\n\t\t\t\tuxPriorityUsedOnEntry = pxTCB->uxPriority;\n\n\t\t\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Only change the priority being used if the task is not\n\t\t\t\t\tcurrently using an inherited priority. */\n\t\t\t\t\tif( pxTCB->uxBasePriority == pxTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* The base priority gets set whatever. */\n\t\t\t\t\tpxTCB->uxBasePriority = uxNewPriority;\n\t\t\t\t}\n\t\t\t\t#else\n\t\t\t\t{\n\t\t\t\t\tpxTCB->uxPriority = uxNewPriority;\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t/* Only reset the event list item value if the value is not\n\t\t\t\tbeing used for anything else. */\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t{\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* If the task is in the blocked or suspended list we need do\n\t\t\t\tnothing more than change its priority variable. However, if\n\t\t\t\tthe task is in a ready list it needs to be removed and placed\n\t\t\t\tin the list appropriate to its new priority. */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The task is currently in its ready list - remove before\n\t\t\t\t\tadding it to it's new ready list.  As we are in a critical\n\t\t\t\t\tsection we can do this even if the scheduler is suspended. */\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* It is known that the task is in its ready list so\n\t\t\t\t\t\tthere is no need to check again and the port level\n\t\t\t\t\t\treset macro can be called directly. */\n\t\t\t\t\t\tportRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\tif( xYieldRequired != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* Remove compiler warning about unused variables when the port\n\t\t\t\toptimised task selection is not being used. */\n\t\t\t\t( void ) uxPriorityUsedOnEntry;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\t}\n\n#endif /* INCLUDE_vTaskPrioritySet */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tvoid vTaskSuspend( TaskHandle_t xTaskToSuspend )\n\t{\n\tTCB_t *pxTCB;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* If null is passed in here then it is the running task that is\n\t\t\tbeing suspended. */\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSuspend );\n\n\t\t\ttraceTASK_SUSPEND( pxTCB );\n\n\t\t\t/* Remove task from the ready/delayed list and place in the\n\t\t\tsuspended list. */\n\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t{\n\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Is the task waiting on an event also? */\n\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );\n\n\t\t\t#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t\t{\n\t\t\t\t\t/* The task was blocked to wait for a notification, but is\n\t\t\t\t\tnow suspended, so no notification was received. */\n\t\t\t\t\tpxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\t/* Reset the next expected unblock time in case it referred to the\n\t\t\ttask that is now in the Suspended state. */\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\tif( pxTCB == pxCurrentTCB )\n\t\t{\n\t\t\tif( xSchedulerRunning != pdFALSE )\n\t\t\t{\n\t\t\t\t/* The current task has just been suspended. */\n\t\t\t\tconfigASSERT( uxSchedulerSuspended == 0 );\n\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The scheduler is not running, but the task that was pointed\n\t\t\t\tto by pxCurrentTCB has just been suspended and pxCurrentTCB\n\t\t\t\tmust be adjusted to point to a different task. */\n\t\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */\n\t\t\t\t{\n\t\t\t\t\t/* No other tasks are ready, so set pxCurrentTCB back to\n\t\t\t\t\tNULL so when the next task is created pxCurrentTCB will\n\t\t\t\t\tbe set to point to it no matter what its relative priority\n\t\t\t\t\tis. */\n\t\t\t\t\tpxCurrentTCB = NULL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tvTaskSwitchContext();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tstatic BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )\n\t{\n\tBaseType_t xReturn = pdFALSE;\n\tconst TCB_t * const pxTCB = xTask;\n\n\t\t/* Accesses xPendingReadyList so must be called from a critical\n\t\tsection. */\n\n\t\t/* It does not make sense to check if the calling task is suspended. */\n\t\tconfigASSERT( xTask );\n\n\t\t/* Is the task being resumed actually in the suspended list? */\n\t\tif( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t{\n\t\t\t/* Has the task already been resumed from within an ISR? */\n\t\t\tif( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )\n\t\t\t{\n\t\t\t\t/* Is it in the suspended list because it is in the\tSuspended\n\t\t\t\tstate, or because is is blocked with no timeout? */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */\n\t\t\t\t{\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */\n\n#endif /* INCLUDE_vTaskSuspend */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskSuspend == 1 )\n\n\tvoid vTaskResume( TaskHandle_t xTaskToResume )\n\t{\n\tTCB_t * const pxTCB = xTaskToResume;\n\n\t\t/* It does not make sense to resume the calling task. */\n\t\tconfigASSERT( xTaskToResume );\n\n\t\t/* The parameter cannot be NULL as it is impossible to resume the\n\t\tcurrently executing task. */\n\t\tif( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\ttraceTASK_RESUME( pxTCB );\n\n\t\t\t\t\t/* The ready list can be accessed even if the scheduler is\n\t\t\t\t\tsuspended because this is inside a critical section. */\n\t\t\t\t\t( void ) uxListRemove(  &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* A higher priority task may have just been resumed. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* This yield may not cause the task just resumed to run,\n\t\t\t\t\t\tbut will leave the lists in the correct state for the\n\t\t\t\t\t\tnext yield. */\n\t\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* INCLUDE_vTaskSuspend */\n\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )\n\n\tBaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )\n\t{\n\tBaseType_t xYieldRequired = pdFALSE;\n\tTCB_t * const pxTCB = xTaskToResume;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToResume );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttps://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tif( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )\n\t\t\t{\n\t\t\t\ttraceTASK_RESUME_FROM_ISR( pxTCB );\n\n\t\t\t\t/* Check the ready lists can be accessed. */\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* Ready lists can be accessed so move the task from the\n\t\t\t\t\tsuspended list to the ready list directly. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\txYieldRequired = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed or ready lists cannot be accessed so the task\n\t\t\t\t\tis held in the pending ready list until the scheduler is\n\t\t\t\t\tunsuspended. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xYieldRequired;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nvoid vTaskStartScheduler( void )\n{\nBaseType_t xReturn;\n\n\t/* Add the idle task at the lowest priority. */\n\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t{\n\t\tStaticTask_t *pxIdleTaskTCBBuffer = NULL;\n\t\tStackType_t *pxIdleTaskStackBuffer = NULL;\n\t\tuint32_t ulIdleTaskStackSize;\n\n\t\t/* The Idle task is created using user provided RAM - obtain the\n\t\taddress of the RAM then create the idle task. */\n\t\tvApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );\n\t\txIdleTaskHandle = xTaskCreateStatic(\tprvIdleTask,\n\t\t\t\t\t\t\t\t\t\t\t\tconfigIDLE_TASK_NAME,\n\t\t\t\t\t\t\t\t\t\t\t\tulIdleTaskStackSize,\n\t\t\t\t\t\t\t\t\t\t\t\t( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */\n\t\t\t\t\t\t\t\t\t\t\t\tportPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n\t\t\t\t\t\t\t\t\t\t\t\tpxIdleTaskStackBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\tpxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n\n\t\tif( xIdleTaskHandle != NULL )\n\t\t{\n\t\t\txReturn = pdPASS;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\t}\n\t#else\n\t{\n\t\t/* The Idle task is being created using dynamically allocated RAM. */\n\t\txReturn = xTaskCreate(\tprvIdleTask,\n\t\t\t\t\t\t\t\tconfigIDLE_TASK_NAME,\n\t\t\t\t\t\t\t\tconfigMINIMAL_STACK_SIZE,\n\t\t\t\t\t\t\t\t( void * ) NULL,\n\t\t\t\t\t\t\t\tportPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */\n\t\t\t\t\t\t\t\t&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */\n\t}\n\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\n\t#if ( configUSE_TIMERS == 1 )\n\t{\n\t\tif( xReturn == pdPASS )\n\t\t{\n\t\t\txReturn = xTimerCreateTimerTask();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\t#endif /* configUSE_TIMERS */\n\n\tif( xReturn == pdPASS )\n\t{\n\t\t/* freertos_tasks_c_additions_init() should only be called if the user\n\t\tdefinable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is\n\t\tthe only macro called by the function. */\n\t\t#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\t\t{\n\t\t\tfreertos_tasks_c_additions_init();\n\t\t}\n\t\t#endif\n\n\t\t/* Interrupts are turned off here, to ensure a tick does not occur\n\t\tbefore or during the call to xPortStartScheduler().  The stacks of\n\t\tthe created tasks contain a status word with interrupts switched on\n\t\tso interrupts will automatically get re-enabled when the first task\n\t\tstarts to run. */\n\t\tportDISABLE_INTERRUPTS();\n\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\n\t\t\tstructure specific to the task that will run first.\n\t\t\tSee the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n\t\t\tfor additional information. */\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\n\t\txNextTaskUnblockTime = portMAX_DELAY;\n\t\txSchedulerRunning = pdTRUE;\n\t\txTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;\n\n\t\t/* If configGENERATE_RUN_TIME_STATS is defined then the following\n\t\tmacro must be defined to configure the timer/counter used to generate\n\t\tthe run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS\n\t\tis set to 0 and the following line fails to build then ensure you do not\n\t\thave portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your\n\t\tFreeRTOSConfig.h file. */\n\t\tportCONFIGURE_TIMER_FOR_RUN_TIME_STATS();\n\n\t\ttraceTASK_SWITCHED_IN();\n\n\t\t/* Setting up the timer tick is hardware specific and thus in the\n\t\tportable interface. */\n\t\tif( xPortStartScheduler() != pdFALSE )\n\t\t{\n\t\t\t/* Should not reach here as if the scheduler is running the\n\t\t\tfunction will not return. */\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Should only reach here if a task calls xTaskEndScheduler(). */\n\t\t}\n\t}\n\telse\n\t{\n\t\t/* This line will only be reached if the kernel could not be started,\n\t\tbecause there was not enough FreeRTOS heap to create the idle task\n\t\tor the timer task. */\n\t\tconfigASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );\n\t}\n\n\t/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,\n\tmeaning xIdleTaskHandle is not used anywhere else. */\n\t( void ) xIdleTaskHandle;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskEndScheduler( void )\n{\n\t/* Stop the scheduler interrupts and call the portable scheduler end\n\troutine so the original ISRs can be restored if necessary.  The port\n\tlayer must ensure interrupts enable\tbit is left in the correct state. */\n\tportDISABLE_INTERRUPTS();\n\txSchedulerRunning = pdFALSE;\n\tvPortEndScheduler();\n}\n/*----------------------------------------------------------*/\n\nvoid vTaskSuspendAll( void )\n{\n\t/* A critical section is not required as the variable is of type\n\tBaseType_t.  Please read Richard Barry's reply in the following link to a\n\tpost in the FreeRTOS support forum before reporting this as a bug! -\n\thttp://goo.gl/wu4acr */\n\n\t/* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that\n\tdo not otherwise exhibit real time behaviour. */\n\tportSOFTWARE_BARRIER();\n\n\t/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment\n\tis used to allow calls to vTaskSuspendAll() to nest. */\n\t++uxSchedulerSuspended;\n\n\t/* Enforces ordering for ports and optimised compilers that may otherwise place\n\tthe above increment elsewhere. */\n\tportMEMORY_BARRIER();\n}\n/*----------------------------------------------------------*/\n\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tstatic TickType_t prvGetExpectedIdleTime( void )\n\t{\n\tTickType_t xReturn;\n\tUBaseType_t uxHigherPriorityReadyTasks = pdFALSE;\n\n\t\t/* uxHigherPriorityReadyTasks takes care of the case where\n\t\tconfigUSE_PREEMPTION is 0, so there may be tasks above the idle priority\n\t\ttask that are in the Ready state, even though the idle task is\n\t\trunning. */\n\t\t#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )\n\t\t{\n\t\t\tif( uxTopReadyPriority > tskIDLE_PRIORITY )\n\t\t\t{\n\t\t\t\tuxHigherPriorityReadyTasks = pdTRUE;\n\t\t\t}\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tconst UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;\n\n\t\t\t/* When port optimised task selection is used the uxTopReadyPriority\n\t\t\tvariable is used as a bit map.  If bits other than the least\n\t\t\tsignificant bit are set then there are tasks that have a priority\n\t\t\tabove the idle priority that are in the Ready state.  This takes\n\t\t\tcare of the case where the co-operative scheduler is in use. */\n\t\t\tif( uxTopReadyPriority > uxLeastSignificantBit )\n\t\t\t{\n\t\t\t\tuxHigherPriorityReadyTasks = pdTRUE;\n\t\t\t}\n\t\t}\n\t\t#endif\n\n\t\tif( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )\n\t\t{\n\t\t\txReturn = 0;\n\t\t}\n\t\telse if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )\n\t\t{\n\t\t\t/* There are other idle priority tasks in the ready state.  If\n\t\t\ttime slicing is used then the very next tick interrupt must be\n\t\t\tprocessed. */\n\t\t\txReturn = 0;\n\t\t}\n\t\telse if( uxHigherPriorityReadyTasks != pdFALSE )\n\t\t{\n\t\t\t/* There are tasks in the Ready state that have a priority above the\n\t\t\tidle priority.  This path can only be reached if\n\t\t\tconfigUSE_PREEMPTION is 0. */\n\t\t\txReturn = 0;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xNextTaskUnblockTime - xTickCount;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskResumeAll( void )\n{\nTCB_t *pxTCB = NULL;\nBaseType_t xAlreadyYielded = pdFALSE;\n\n\t/* If uxSchedulerSuspended is zero then this function does not match a\n\tprevious call to vTaskSuspendAll(). */\n\tconfigASSERT( uxSchedulerSuspended );\n\n\t/* It is possible that an ISR caused a task to be removed from an event\n\tlist while the scheduler was suspended.  If this was the case then the\n\tremoved task will have been added to the xPendingReadyList.  Once the\n\tscheduler has been resumed it is safe to move all the pending ready\n\ttasks from this list into their appropriate ready list. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\t--uxSchedulerSuspended;\n\n\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t{\n\t\t\tif( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )\n\t\t\t{\n\t\t\t\t/* Move any readied tasks from the pending list into the\n\t\t\t\tappropriate ready list. */\n\t\t\t\twhile( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* If the moved task has a priority higher than the current\n\t\t\t\t\ttask then a yield must be performed. */\n\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* A task was unblocked while the scheduler was suspended,\n\t\t\t\t\twhich may have prevented the next unblock time from being\n\t\t\t\t\tre-calculated, in which case re-calculate it now.  Mainly\n\t\t\t\t\timportant for low power tickless implementations, where\n\t\t\t\t\tthis can prevent an unnecessary exit from low power\n\t\t\t\t\tstate. */\n\t\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t\t}\n\n\t\t\t\t/* If any ticks occurred while the scheduler was suspended then\n\t\t\t\tthey should be processed now.  This ensures the tick count does\n\t\t\t\tnot\tslip, and that any delayed tasks are resumed at the correct\n\t\t\t\ttime. */\n\t\t\t\t{\n\t\t\t\t\tTickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */\n\n\t\t\t\t\tif( xPendedCounts > ( TickType_t ) 0U )\n\t\t\t\t\t{\n\t\t\t\t\t\tdo\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( xTaskIncrementTick() != pdFALSE )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\telse\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t\t--xPendedCounts;\n\t\t\t\t\t\t} while( xPendedCounts > ( TickType_t ) 0U );\n\n\t\t\t\t\t\txPendedTicks = 0;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( xYieldPending != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t#if( configUSE_PREEMPTION != 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\txAlreadyYielded = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\t#endif\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xAlreadyYielded;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCount( void )\n{\nTickType_t xTicks;\n\n\t/* Critical section required if running on a 16 bit processor. */\n\tportTICK_TYPE_ENTER_CRITICAL();\n\t{\n\t\txTicks = xTickCount;\n\t}\n\tportTICK_TYPE_EXIT_CRITICAL();\n\n\treturn xTicks;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTaskGetTickCountFromISR( void )\n{\nTickType_t xReturn;\nUBaseType_t uxSavedInterruptStatus;\n\n\t/* RTOS ports that support interrupt nesting have the concept of a maximum\n\tsystem call (or maximum API call) interrupt priority.  Interrupts that are\n\tabove the maximum system call priority are kept permanently enabled, even\n\twhen the RTOS kernel is in a critical section, but cannot make any calls to\n\tFreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h\n\tthen portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\tfailure if a FreeRTOS API function is called from an interrupt that has been\n\tassigned a priority above the configured maximum system call priority.\n\tOnly FreeRTOS functions that end in FromISR can be called from interrupts\n\tthat have been assigned a priority at or (logically) below the maximum\n\tsystem call\tinterrupt priority.  FreeRTOS maintains a separate interrupt\n\tsafe API to ensure interrupt entry is as fast and as simple as possible.\n\tMore information (albeit Cortex-M specific) is provided on the following\n\tlink: https://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\tuxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();\n\t{\n\t\txReturn = xTickCount;\n\t}\n\tportTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxTaskGetNumberOfTasks( void )\n{\n\t/* A critical section is not required because the variables are of type\n\tBaseType_t. */\n\treturn uxCurrentNumberOfTasks;\n}\n/*-----------------------------------------------------------*/\n\nchar *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n{\nTCB_t *pxTCB;\n\n\t/* If null is passed in here then the name of the calling task is being\n\tqueried. */\n\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\n\tconfigASSERT( pxTCB );\n\treturn &( pxTCB->pcTaskName[ 0 ] );\n}\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tstatic TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )\n\t{\n\tTCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;\n\tUBaseType_t x;\n\tchar cNextChar;\n\tBaseType_t xBreakLoop;\n\n\t\t/* This function is called with the scheduler suspended. */\n\n\t\tif( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\tdo\n\t\t\t{\n\t\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\t\t/* Check each character in the name looking for a match or\n\t\t\t\tmismatch. */\n\t\t\t\txBreakLoop = pdFALSE;\n\t\t\t\tfor( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )\n\t\t\t\t{\n\t\t\t\t\tcNextChar = pxNextTCB->pcTaskName[ x ];\n\n\t\t\t\t\tif( cNextChar != pcNameToQuery[ x ] )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Characters didn't match. */\n\t\t\t\t\t\txBreakLoop = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse if( cNextChar == ( char ) 0x00 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Both strings terminated, a match must have been\n\t\t\t\t\t\tfound. */\n\t\t\t\t\t\tpxReturn = pxNextTCB;\n\t\t\t\t\t\txBreakLoop = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\tif( xBreakLoop != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tbreak;\n\t\t\t\t\t}\n\t\t\t\t}\n\n\t\t\t\tif( pxReturn != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* The handle has been found. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t} while( pxNextTCB != pxFirstTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn pxReturn;\n\t}\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetHandle == 1 )\n\n\tTaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t{\n\tUBaseType_t uxQueue = configMAX_PRIORITIES;\n\tTCB_t* pxTCB;\n\n\t\t/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */\n\t\tconfigASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Search the ready lists. */\n\t\t\tdo\n\t\t\t{\n\t\t\t\tuxQueue--;\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );\n\n\t\t\t\tif( pxTCB != NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Found the handle. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t/* Search the delayed lists. */\n\t\t\tif( pxTCB == NULL )\n\t\t\t{\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );\n\t\t\t}\n\n\t\t\tif( pxTCB == NULL )\n\t\t\t{\n\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );\n\t\t\t}\n\n\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Search the suspended list. */\n\t\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if( INCLUDE_vTaskDelete == 1 )\n\t\t\t{\n\t\t\t\tif( pxTCB == NULL )\n\t\t\t\t{\n\t\t\t\t\t/* Search the deleted list. */\n\t\t\t\t\tpxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn pxTCB;\n\t}\n\n#endif /* INCLUDE_xTaskGetHandle */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )\n\t{\n\tUBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* Is there a space in the array for each task in the system? */\n\t\t\tif( uxArraySize >= uxCurrentNumberOfTasks )\n\t\t\t{\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\n\t\t\t\ttask in the Ready state. */\n\t\t\t\tdo\n\t\t\t\t{\n\t\t\t\t\tuxQueue--;\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );\n\n\t\t\t\t} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\t\t\t\t/* Fill in an TaskStatus_t structure with information on each\n\t\t\t\ttask in the Blocked state. */\n\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );\n\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );\n\n\t\t\t\t#if( INCLUDE_vTaskDelete == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\n\t\t\t\t\teach task that has been deleted but not yet cleaned up. */\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Fill in an TaskStatus_t structure with information on\n\t\t\t\t\teach task in the Suspended state. */\n\t\t\t\t\tuxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\t#if ( configGENERATE_RUN_TIME_STATS == 1)\n\t\t\t\t{\n\t\t\t\t\tif( pulTotalRunTime != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t\t*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#else\n\t\t\t\t{\n\t\t\t\t\tif( pulTotalRunTime != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pulTotalRunTime = 0;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn uxTask;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\n\n\tTaskHandle_t xTaskGetIdleTaskHandle( void )\n\t{\n\t\t/* If xTaskGetIdleTaskHandle() is called before the scheduler has been\n\t\tstarted, then xIdleTaskHandle will be NULL. */\n\t\tconfigASSERT( ( xIdleTaskHandle != NULL ) );\n\t\treturn xIdleTaskHandle;\n\t}\n\n#endif /* INCLUDE_xTaskGetIdleTaskHandle */\n/*----------------------------------------------------------*/\n\n/* This conditional compilation should use inequality to 0, not equality to 1.\nThis is to ensure vTaskStepTick() is available when user defined low power mode\nimplementations require configUSE_TICKLESS_IDLE to be set to a value other than\n1. */\n#if ( configUSE_TICKLESS_IDLE != 0 )\n\n\tvoid vTaskStepTick( const TickType_t xTicksToJump )\n\t{\n\t\t/* Correct the tick count value after a period during which the tick\n\t\twas suppressed.  Note this does *not* call the tick hook function for\n\t\teach stepped tick. */\n\t\tconfigASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );\n\t\txTickCount += xTicksToJump;\n\t\ttraceINCREASE_TICK_COUNT( xTicksToJump );\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )\n{\nBaseType_t xYieldRequired = pdFALSE;\n\n\t/* Must not be called with the scheduler suspended as the implementation\n\trelies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */\n\tconfigASSERT( uxSchedulerSuspended == 0 );\n\n\t/* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when\n\tthe scheduler is suspended so the ticks are executed in xTaskResumeAll(). */\n\tvTaskSuspendAll();\n\txPendedTicks += xTicksToCatchUp;\n\txYieldRequired = xTaskResumeAll();\n\n\treturn xYieldRequired;\n}\n/*----------------------------------------------------------*/\n\n#if ( INCLUDE_xTaskAbortDelay == 1 )\n\n\tBaseType_t xTaskAbortDelay( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB = xTask;\n\tBaseType_t xReturn;\n\n\t\tconfigASSERT( pxTCB );\n\n\t\tvTaskSuspendAll();\n\t\t{\n\t\t\t/* A task can only be prematurely removed from the Blocked state if\n\t\t\tit is actually in the Blocked state. */\n\t\t\tif( eTaskGetState( xTask ) == eBlocked )\n\t\t\t{\n\t\t\t\txReturn = pdPASS;\n\n\t\t\t\t/* Remove the reference to the task from the blocked list.  An\n\t\t\t\tinterrupt won't touch the xStateListItem because the\n\t\t\t\tscheduler is suspended. */\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t/* Is the task waiting on an event also?  If so remove it from\n\t\t\t\tthe event list too.  Interrupts can touch the event list item,\n\t\t\t\teven though the scheduler is suspended, so a critical section\n\t\t\t\tis used. */\n\t\t\t\ttaskENTER_CRITICAL();\n\t\t\t\t{\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\n\t\t\t\t\t\t/* This lets the task know it was forcibly removed from the\n\t\t\t\t\t\tblocked state so it should not re-evaluate its block time and\n\t\t\t\t\t\tthen block again. */\n\t\t\t\t\t\tpxTCB->ucDelayAborted = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\t\t/* Place the unblocked task into the appropriate ready list. */\n\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t/* A task being unblocked cannot cause an immediate context\n\t\t\t\tswitch if preemption is turned off. */\n\t\t\t\t#if (  configUSE_PREEMPTION == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* Preemption is on, but a context switch should only be\n\t\t\t\t\tperformed if the unblocked task has a priority that is\n\t\t\t\t\tequal to or higher than the currently executing task. */\n\t\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Pend the yield to be performed when the scheduler\n\t\t\t\t\t\tis unsuspended. */\n\t\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* configUSE_PREEMPTION */\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\t( void ) xTaskResumeAll();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTaskAbortDelay */\n/*----------------------------------------------------------*/\n\nBaseType_t xTaskIncrementTick( void )\n{\nTCB_t * pxTCB;\nTickType_t xItemValue;\nBaseType_t xSwitchRequired = pdFALSE;\n\n\t/* Called by the portable layer each time a tick interrupt occurs.\n\tIncrements the tick then checks to see if the new tick value will cause any\n\ttasks to be unblocked. */\n\ttraceTASK_INCREMENT_TICK( xTickCount );\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t{\n\t\t/* Minor optimisation.  The tick count cannot change in this\n\t\tblock. */\n\t\tconst TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;\n\n\t\t/* Increment the RTOS tick, switching the delayed and overflowed\n\t\tdelayed lists if it wraps to 0. */\n\t\txTickCount = xConstTickCount;\n\n\t\tif( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */\n\t\t{\n\t\t\ttaskSWITCH_DELAYED_LISTS();\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\t/* See if this tick has made a timeout expire.  Tasks are stored in\n\t\tthe\tqueue in the order of their wake time - meaning once one task\n\t\thas been found whose block time has not expired there is no need to\n\t\tlook any further down the list. */\n\t\tif( xConstTickCount >= xNextTaskUnblockTime )\n\t\t{\n\t\t\tfor( ;; )\n\t\t\t{\n\t\t\t\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The delayed list is empty.  Set xNextTaskUnblockTime\n\t\t\t\t\tto the maximum possible value so it is extremely\n\t\t\t\t\tunlikely that the\n\t\t\t\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass\n\t\t\t\t\tnext time through. */\n\t\t\t\t\txNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed list is not empty, get the value of the\n\t\t\t\t\titem at the head of the delayed list.  This is the time\n\t\t\t\t\tat which the task at the head of the delayed list must\n\t\t\t\t\tbe removed from the Blocked state. */\n\t\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t\txItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t\tif( xConstTickCount < xItemValue )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* It is not time to unblock this item yet, but the\n\t\t\t\t\t\titem value is the time at which the task at the head\n\t\t\t\t\t\tof the blocked list must be removed from the Blocked\n\t\t\t\t\t\tstate -\tso record the item value in\n\t\t\t\t\t\txNextTaskUnblockTime. */\n\t\t\t\t\t\txNextTaskUnblockTime = xItemValue;\n\t\t\t\t\t\tbreak; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* It is time to remove the item from the Blocked state. */\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\n\t\t\t\t\t/* Is the task waiting on an event also?  If so remove\n\t\t\t\t\tit from the event list. */\n\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xEventListItem ) );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Place the unblocked task into the appropriate ready\n\t\t\t\t\tlist. */\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* A task being unblocked cannot cause an immediate\n\t\t\t\t\tcontext switch if preemption is turned off. */\n\t\t\t\t\t#if (  configUSE_PREEMPTION == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* Preemption is on, but a context switch should\n\t\t\t\t\t\tonly be performed if the unblocked task has a\n\t\t\t\t\t\tpriority that is equal to or higher than the\n\t\t\t\t\t\tcurrently executing task. */\n\t\t\t\t\t\tif( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txSwitchRequired = pdTRUE;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configUSE_PREEMPTION */\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\n\t\t/* Tasks of equal priority to the currently running task will share\n\t\tprocessing time (time slice) if preemption is on, and the application\n\t\twriter has not explicitly turned time slicing off. */\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )\n\t\t{\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\txSwitchRequired = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */\n\n\t\t#if ( configUSE_TICK_HOOK == 1 )\n\t\t{\n\t\t\t/* Guard against the tick hook being called when the pended tick\n\t\t\tcount is being unwound (when the scheduler is being unlocked). */\n\t\t\tif( xPendedTicks == ( TickType_t ) 0 )\n\t\t\t{\n\t\t\t\tvApplicationTickHook();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_TICK_HOOK */\n\n\t\t#if ( configUSE_PREEMPTION == 1 )\n\t\t{\n\t\t\tif( xYieldPending != pdFALSE )\n\t\t\t{\n\t\t\t\txSwitchRequired = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_PREEMPTION */\n\t}\n\telse\n\t{\n\t\t++xPendedTicks;\n\n\t\t/* The tick hook gets called at regular intervals, even if the\n\t\tscheduler is locked. */\n\t\t#if ( configUSE_TICK_HOOK == 1 )\n\t\t{\n\t\t\tvApplicationTickHook();\n\t\t}\n\t\t#endif\n\t}\n\n\treturn xSwitchRequired;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tvoid vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )\n\t{\n\tTCB_t *xTCB;\n\n\t\t/* If xTask is NULL then it is the task hook of the calling task that is\n\t\tgetting set. */\n\t\tif( xTask == NULL )\n\t\t{\n\t\t\txTCB = ( TCB_t * ) pxCurrentTCB;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txTCB = xTask;\n\t\t}\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txTCB->pxTaskTag = pxHookFunction;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tTaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tTaskHookFunction_t xReturn;\n\n\t\t/* If xTask is NULL then set the calling task's hook. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\txReturn = pxTCB->pxTaskTag;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tTaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tTaskHookFunction_t xReturn;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\t/* If xTask is NULL then set the calling task's hook. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t/* Save the hook function in the TCB.  A critical section is required as\n\t\tthe value can be accessed from an interrupt. */\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\txReturn = pxTCB->pxTaskTag;\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_APPLICATION_TASK_TAG == 1 )\n\n\tBaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\n\t{\n\tTCB_t *xTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If xTask is NULL then we are calling our own task hook. */\n\t\tif( xTask == NULL )\n\t\t{\n\t\t\txTCB = pxCurrentTCB;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txTCB = xTask;\n\t\t}\n\n\t\tif( xTCB->pxTaskTag != NULL )\n\t\t{\n\t\t\txReturn = xTCB->pxTaskTag( pvParameter );\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdFAIL;\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_APPLICATION_TASK_TAG */\n/*-----------------------------------------------------------*/\n\nvoid vTaskSwitchContext( void )\n{\n\tif( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )\n\t{\n\t\t/* The scheduler is currently suspended - do not allow a context\n\t\tswitch. */\n\t\txYieldPending = pdTRUE;\n\t}\n\telse\n\t{\n\t\txYieldPending = pdFALSE;\n\t\ttraceTASK_SWITCHED_OUT();\n\n\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\t{\n\t\t\t#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE\n\t\t\t\tportALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );\n\t\t\t#else\n\t\t\t\tulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();\n\t\t\t#endif\n\n\t\t\t/* Add the amount of time the task has been running to the\n\t\t\taccumulated time so far.  The time the task started running was\n\t\t\tstored in ulTaskSwitchedInTime.  Note that there is no overflow\n\t\t\tprotection here so count values are only valid until the timer\n\t\t\toverflows.  The guard against negative values is to protect\n\t\t\tagainst suspect run time stat counter implementations - which\n\t\t\tare provided by the application, not the kernel. */\n\t\t\tif( ulTotalRunTime > ulTaskSwitchedInTime )\n\t\t\t{\n\t\t\t\tpxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t\tulTaskSwitchedInTime = ulTotalRunTime;\n\t\t}\n\t\t#endif /* configGENERATE_RUN_TIME_STATS */\n\n\t\t/* Check for stack overflow, if configured. */\n\t\ttaskCHECK_FOR_STACK_OVERFLOW();\n\n\t\t/* Before the currently running task is switched out, save its errno. */\n\t\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\t{\n\t\t\tpxCurrentTCB->iTaskErrno = FreeRTOS_errno;\n\t\t}\n\t\t#endif\n\n\t\t/* Select a new task to run using either the generic C or port\n\t\toptimised asm code. */\n\t\ttaskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\ttraceTASK_SWITCHED_IN();\n\n\t\t/* After the new task is switched in, update the global errno. */\n\t\t#if( configUSE_POSIX_ERRNO == 1 )\n\t\t{\n\t\t\tFreeRTOS_errno = pxCurrentTCB->iTaskErrno;\n\t\t}\n\t\t#endif\n\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t/* Switch Newlib's _impure_ptr variable to point to the _reent\n\t\t\tstructure specific to this task.\n\t\t\tSee the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n\t\t\tfor additional information. */\n\t\t\t_impure_ptr = &( pxCurrentTCB->xNewLib_reent );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )\n{\n\tconfigASSERT( pxEventList );\n\n\t/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE\n\tSCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */\n\n\t/* Place the event list item of the TCB in the appropriate event list.\n\tThis is placed in the list in priority order so the highest priority task\n\tis the first to be woken by the event.  The queue that contains the event\n\tlist is locked, preventing simultaneous access from interrupts. */\n\tvListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )\n{\n\tconfigASSERT( pxEventList );\n\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n\tthe event groups implementation. */\n\tconfigASSERT( uxSchedulerSuspended != 0 );\n\n\t/* Store the item value in the event list item.  It is safe to access the\n\tevent list item here as interrupts won't access the event list item of a\n\ttask that is not in the Blocked state. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n\t/* Place the event list item of the TCB at the end of the appropriate event\n\tlist.  It is safe to access the event list here because it is part of an\n\tevent group implementation - and interrupts don't access event groups\n\tdirectly (instead they access them indirectly by pending function calls to\n\tthe task level). */\n\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TIMERS == 1 )\n\n\tvoid vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )\n\t{\n\t\tconfigASSERT( pxEventList );\n\n\t\t/* This function should not be called by application code hence the\n\t\t'Restricted' in its name.  It is not part of the public API.  It is\n\t\tdesigned for use by kernel code, and has special calling requirements -\n\t\tit should be called with the scheduler suspended. */\n\n\n\t\t/* Place the event list item of the TCB in the appropriate event list.\n\t\tIn this case it is assume that this is the only task that is going to\n\t\tbe waiting on this event list, so the faster vListInsertEnd() function\n\t\tcan be used in place of vListInsert. */\n\t\tvListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );\n\n\t\t/* If the task should block indefinitely then set the block time to a\n\t\tvalue that will be recognised as an indefinite delay inside the\n\t\tprvAddCurrentTaskToDelayedList() function. */\n\t\tif( xWaitIndefinitely != pdFALSE )\n\t\t{\n\t\t\txTicksToWait = portMAX_DELAY;\n\t\t}\n\n\t\ttraceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );\n\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );\n\t}\n\n#endif /* configUSE_TIMERS */\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )\n{\nTCB_t *pxUnblockedTCB;\nBaseType_t xReturn;\n\n\t/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be\n\tcalled from a critical section within an ISR. */\n\n\t/* The event list is sorted in priority order, so the first in the list can\n\tbe removed as it is known to be the highest priority.  Remove the TCB from\n\tthe delayed list, and add it to the ready list.\n\n\tIf an event is for a queue that is locked then this function will never\n\tget called - the lock count on the queue will get modified instead.  This\n\tmeans exclusive access to the event list is guaranteed here.\n\n\tThis function assumes that a check has already been made to ensure that\n\tpxEventList is not empty. */\n\tpxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\tconfigASSERT( pxUnblockedTCB );\n\t( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );\n\n\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t{\n\t\t( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );\n\t\tprvAddTaskToReadyList( pxUnblockedTCB );\n\n\t\t#if( configUSE_TICKLESS_IDLE != 0 )\n\t\t{\n\t\t\t/* If a task is blocked on a kernel object then xNextTaskUnblockTime\n\t\t\tmight be set to the blocked task's time out time.  If the task is\n\t\t\tunblocked for a reason other than a timeout xNextTaskUnblockTime is\n\t\t\tnormally left unchanged, because it is automatically reset to a new\n\t\t\tvalue when the tick count equals xNextTaskUnblockTime.  However if\n\t\t\ttickless idling is used it might be more important to enter sleep mode\n\t\t\tat the earliest possible time - so reset xNextTaskUnblockTime here to\n\t\t\tensure it is updated at the earliest possible time. */\n\t\t\tprvResetNextTaskUnblockTime();\n\t\t}\n\t\t#endif\n\t}\n\telse\n\t{\n\t\t/* The delayed and ready lists cannot be accessed, so hold this task\n\t\tpending until the scheduler is resumed. */\n\t\tvListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );\n\t}\n\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t{\n\t\t/* Return true if the task removed from the event list has a higher\n\t\tpriority than the calling task.  This allows the calling task to know if\n\t\tit should force a context switch now. */\n\t\txReturn = pdTRUE;\n\n\t\t/* Mark that a yield is pending in case the user is not using the\n\t\t\"xHigherPriorityTaskWoken\" parameter to an ISR safe FreeRTOS function. */\n\t\txYieldPending = pdTRUE;\n\t}\n\telse\n\t{\n\t\txReturn = pdFALSE;\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )\n{\nTCB_t *pxUnblockedTCB;\n\n\t/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by\n\tthe event flags implementation. */\n\tconfigASSERT( uxSchedulerSuspended != pdFALSE );\n\n\t/* Store the new item value in the event list. */\n\tlistSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );\n\n\t/* Remove the event list form the event flag.  Interrupts do not access\n\tevent flags. */\n\tpxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\tconfigASSERT( pxUnblockedTCB );\n\t( void ) uxListRemove( pxEventListItem );\n\n\t#if( configUSE_TICKLESS_IDLE != 0 )\n\t{\n\t\t/* If a task is blocked on a kernel object then xNextTaskUnblockTime\n\t\tmight be set to the blocked task's time out time.  If the task is\n\t\tunblocked for a reason other than a timeout xNextTaskUnblockTime is\n\t\tnormally left unchanged, because it is automatically reset to a new\n\t\tvalue when the tick count equals xNextTaskUnblockTime.  However if\n\t\ttickless idling is used it might be more important to enter sleep mode\n\t\tat the earliest possible time - so reset xNextTaskUnblockTime here to\n\t\tensure it is updated at the earliest possible time. */\n\t\tprvResetNextTaskUnblockTime();\n\t}\n\t#endif\n\n\t/* Remove the task from the delayed list and add it to the ready list.  The\n\tscheduler is suspended so interrupts will not be accessing the ready\n\tlists. */\n\t( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );\n\tprvAddTaskToReadyList( pxUnblockedTCB );\n\n\tif( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t{\n\t\t/* The unblocked task has a priority above that of the calling task, so\n\t\ta context switch is required.  This function is called with the\n\t\tscheduler suspended so xYieldPending is set so the context switch\n\t\toccurs immediately that the scheduler is resumed (unsuspended). */\n\t\txYieldPending = pdTRUE;\n\t}\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n\tconfigASSERT( pxTimeOut );\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxTimeOut->xOverflowCount = xNumOfOverflows;\n\t\tpxTimeOut->xTimeOnEntering = xTickCount;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )\n{\n\t/* For internal use only as it does not use a critical section. */\n\tpxTimeOut->xOverflowCount = xNumOfOverflows;\n\tpxTimeOut->xTimeOnEntering = xTickCount;\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )\n{\nBaseType_t xReturn;\n\n\tconfigASSERT( pxTimeOut );\n\tconfigASSERT( pxTicksToWait );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\t/* Minor optimisation.  The tick count cannot change in this block. */\n\t\tconst TickType_t xConstTickCount = xTickCount;\n\t\tconst TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;\n\n\t\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t\t\tif( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )\n\t\t\t{\n\t\t\t\t/* The delay was aborted, which is not the same as a time out,\n\t\t\t\tbut has the same result. */\n\t\t\t\tpxCurrentTCB->ucDelayAborted = pdFALSE;\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t#endif\n\n\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\tif( *pxTicksToWait == portMAX_DELAY )\n\t\t\t{\n\t\t\t\t/* If INCLUDE_vTaskSuspend is set to 1 and the block time\n\t\t\t\tspecified is the maximum block time then the task should block\n\t\t\t\tindefinitely, and therefore never time out. */\n\t\t\t\txReturn = pdFALSE;\n\t\t\t}\n\t\t\telse\n\t\t#endif\n\n\t\tif( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */\n\t\t{\n\t\t\t/* The tick count is greater than the time at which\n\t\t\tvTaskSetTimeout() was called, but has also overflowed since\n\t\t\tvTaskSetTimeOut() was called.  It must have wrapped all the way\n\t\t\taround and gone past again. This passed since vTaskSetTimeout()\n\t\t\twas called. */\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t\telse if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */\n\t\t{\n\t\t\t/* Not a genuine timeout. Adjust parameters for time remaining. */\n\t\t\t*pxTicksToWait -= xElapsedTime;\n\t\t\tvTaskInternalSetTimeOutState( pxTimeOut );\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t*pxTicksToWait = 0;\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTaskMissedYield( void )\n{\n\txYieldPending = pdTRUE;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )\n\t{\n\tUBaseType_t uxReturn;\n\tTCB_t const *pxTCB;\n\n\t\tif( xTask != NULL )\n\t\t{\n\t\t\tpxTCB = xTask;\n\t\t\tuxReturn = pxTCB->uxTaskNumber;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tuxReturn = 0U;\n\t\t}\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )\n\t{\n\tTCB_t * pxTCB;\n\n\t\tif( xTask != NULL )\n\t\t{\n\t\t\tpxTCB = xTask;\n\t\t\tpxTCB->uxTaskNumber = uxHandle;\n\t\t}\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n\n/*\n * -----------------------------------------------------------\n * The Idle task.\n * ----------------------------------------------------------\n *\n * The portTASK_FUNCTION() macro is used to allow port/compiler specific\n * language extensions.  The equivalent prototype for this function is:\n *\n * void prvIdleTask( void *pvParameters );\n *\n */\nstatic portTASK_FUNCTION( prvIdleTask, pvParameters )\n{\n\t/* Stop warnings. */\n\t( void ) pvParameters;\n\n\t/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE\n\tSCHEDULER IS STARTED. **/\n\n\t/* In case a task that has a secure context deletes itself, in which case\n\tthe idle task is responsible for deleting the task's secure context, if\n\tany. */\n\tportALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );\n\n\tfor( ;; )\n\t{\n\t\t/* See if any tasks have deleted themselves - if so then the idle task\n\t\tis responsible for freeing the deleted task's TCB and stack. */\n\t\tprvCheckTasksWaitingTermination();\n\n\t\t#if ( configUSE_PREEMPTION == 0 )\n\t\t{\n\t\t\t/* If we are not using preemption we keep forcing a task switch to\n\t\t\tsee if any other task has become available.  If we are using\n\t\t\tpreemption we don't need to do this as any task becoming available\n\t\t\twill automatically get the processor anyway. */\n\t\t\ttaskYIELD();\n\t\t}\n\t\t#endif /* configUSE_PREEMPTION */\n\n\t\t#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )\n\t\t{\n\t\t\t/* When using preemption tasks of equal priority will be\n\t\t\ttimesliced.  If a task that is sharing the idle priority is ready\n\t\t\tto run then the idle task should yield before the end of the\n\t\t\ttimeslice.\n\n\t\t\tA critical region is not required here as we are just reading from\n\t\t\tthe list, and an occasional incorrect value will not matter.  If\n\t\t\tthe ready list at the idle priority contains more than one task\n\t\t\tthen a task other than the idle task is ready to execute. */\n\t\t\tif( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )\n\t\t\t{\n\t\t\t\ttaskYIELD();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */\n\n\t\t#if ( configUSE_IDLE_HOOK == 1 )\n\t\t{\n\t\t\textern void vApplicationIdleHook( void );\n\n\t\t\t/* Call the user defined function from within the idle task.  This\n\t\t\tallows the application designer to add background functionality\n\t\t\twithout the overhead of a separate task.\n\t\t\tNOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,\n\t\t\tCALL A FUNCTION THAT MIGHT BLOCK. */\n\t\t\tvApplicationIdleHook();\n\t\t}\n\t\t#endif /* configUSE_IDLE_HOOK */\n\n\t\t/* This conditional compilation should use inequality to 0, not equality\n\t\tto 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when\n\t\tuser defined low power mode\timplementations require\n\t\tconfigUSE_TICKLESS_IDLE to be set to a value other than 1. */\n\t\t#if ( configUSE_TICKLESS_IDLE != 0 )\n\t\t{\n\t\tTickType_t xExpectedIdleTime;\n\n\t\t\t/* It is not desirable to suspend then resume the scheduler on\n\t\t\teach iteration of the idle task.  Therefore, a preliminary\n\t\t\ttest of the expected idle time is performed without the\n\t\t\tscheduler suspended.  The result here is not necessarily\n\t\t\tvalid. */\n\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\n\n\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n\t\t\t{\n\t\t\t\tvTaskSuspendAll();\n\t\t\t\t{\n\t\t\t\t\t/* Now the scheduler is suspended, the expected idle\n\t\t\t\t\ttime can be sampled again, and this time its value can\n\t\t\t\t\tbe used. */\n\t\t\t\t\tconfigASSERT( xNextTaskUnblockTime >= xTickCount );\n\t\t\t\t\txExpectedIdleTime = prvGetExpectedIdleTime();\n\n\t\t\t\t\t/* Define the following macro to set xExpectedIdleTime to 0\n\t\t\t\t\tif the application does not want\n\t\t\t\t\tportSUPPRESS_TICKS_AND_SLEEP() to be called. */\n\t\t\t\t\tconfigPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );\n\n\t\t\t\t\tif( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )\n\t\t\t\t\t{\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_BEGIN();\n\t\t\t\t\t\tportSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );\n\t\t\t\t\t\ttraceLOW_POWER_IDLE_END();\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configUSE_TICKLESS_IDLE */\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TICKLESS_IDLE != 0 )\n\n\teSleepModeStatus eTaskConfirmSleepModeStatus( void )\n\t{\n\t/* The idle task exists in addition to the application tasks. */\n\tconst UBaseType_t uxNonApplicationTasks = 1;\n\teSleepModeStatus eReturn = eStandardSleep;\n\n\t\t/* This function must be called from a critical section. */\n\n\t\tif( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )\n\t\t{\n\t\t\t/* A task was made ready while the scheduler was suspended. */\n\t\t\teReturn = eAbortSleep;\n\t\t}\n\t\telse if( xYieldPending != pdFALSE )\n\t\t{\n\t\t\t/* A yield was pended while the scheduler was suspended. */\n\t\t\teReturn = eAbortSleep;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* If all the tasks are in the suspended list (which might mean they\n\t\t\thave an infinite block time rather than actually being suspended)\n\t\t\tthen it is safe to turn all clocks off and just wait for external\n\t\t\tinterrupts. */\n\t\t\tif( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )\n\t\t\t{\n\t\t\t\teReturn = eNoTasksWaitingTimeout;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\treturn eReturn;\n\t}\n\n#endif /* configUSE_TICKLESS_IDLE */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n\tvoid vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )\n\t{\n\tTCB_t *pxTCB;\n\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\n\t\t{\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToSet );\n\t\t\tconfigASSERT( pxTCB != NULL );\n\t\t\tpxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;\n\t\t}\n\t}\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )\n\n\tvoid *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )\n\t{\n\tvoid *pvReturn = NULL;\n\tTCB_t *pxTCB;\n\n\t\tif( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )\n\t\t{\n\t\t\tpxTCB = prvGetTCBFromHandle( xTaskToQuery );\n\t\t\tpvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpvReturn = NULL;\n\t\t}\n\n\t\treturn pvReturn;\n\t}\n\n#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */\n/*-----------------------------------------------------------*/\n\n#if ( portUSING_MPU_WRAPPERS == 1 )\n\n\tvoid vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )\n\t{\n\tTCB_t *pxTCB;\n\n\t\t/* If null is passed in here then we are modifying the MPU settings of\n\t\tthe calling task. */\n\t\tpxTCB = prvGetTCBFromHandle( xTaskToModify );\n\n\t\tvPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );\n\t}\n\n#endif /* portUSING_MPU_WRAPPERS */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseTaskLists( void )\n{\nUBaseType_t uxPriority;\n\n\tfor( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )\n\t{\n\t\tvListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );\n\t}\n\n\tvListInitialise( &xDelayedTaskList1 );\n\tvListInitialise( &xDelayedTaskList2 );\n\tvListInitialise( &xPendingReadyList );\n\n\t#if ( INCLUDE_vTaskDelete == 1 )\n\t{\n\t\tvListInitialise( &xTasksWaitingTermination );\n\t}\n\t#endif /* INCLUDE_vTaskDelete */\n\n\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t{\n\t\tvListInitialise( &xSuspendedTaskList );\n\t}\n\t#endif /* INCLUDE_vTaskSuspend */\n\n\t/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList\n\tusing list2. */\n\tpxDelayedTaskList = &xDelayedTaskList1;\n\tpxOverflowDelayedTaskList = &xDelayedTaskList2;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckTasksWaitingTermination( void )\n{\n\n\t/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/\n\n\t#if ( INCLUDE_vTaskDelete == 1 )\n\t{\n\t\tTCB_t *pxTCB;\n\n\t\t/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()\n\t\tbeing called too often in the idle task. */\n\t\twhile( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )\n\t\t{\n\t\t\ttaskENTER_CRITICAL();\n\t\t\t{\n\t\t\t\tpxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t--uxCurrentNumberOfTasks;\n\t\t\t\t--uxDeletedTasksWaitingCleanUp;\n\t\t\t}\n\t\t\ttaskEXIT_CRITICAL();\n\n\t\t\tprvDeleteTCB( pxTCB );\n\t\t}\n\t}\n\t#endif /* INCLUDE_vTaskDelete */\n}\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )\n\t{\n\tTCB_t *pxTCB;\n\n\t\t/* xTask is NULL then get the state of the calling task. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\tpxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;\n\t\tpxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );\n\t\tpxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;\n\t\tpxTaskStatus->pxStackBase = pxTCB->pxStack;\n\t\tpxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;\n\n\t\t#if ( configUSE_MUTEXES == 1 )\n\t\t{\n\t\t\tpxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpxTaskStatus->uxBasePriority = 0;\n\t\t}\n\t\t#endif\n\n\t\t#if ( configGENERATE_RUN_TIME_STATS == 1 )\n\t\t{\n\t\t\tpxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpxTaskStatus->ulRunTimeCounter = 0;\n\t\t}\n\t\t#endif\n\n\t\t/* Obtaining the task state is a little fiddly, so is only done if the\n\t\tvalue of eState passed into this function is eInvalid - otherwise the\n\t\tstate is just set to whatever is passed in. */\n\t\tif( eState != eInvalid )\n\t\t{\n\t\t\tif( pxTCB == pxCurrentTCB )\n\t\t\t{\n\t\t\t\tpxTaskStatus->eCurrentState = eRunning;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tpxTaskStatus->eCurrentState = eState;\n\n\t\t\t\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t\t\t\t{\n\t\t\t\t\t/* If the task is in the suspended list then there is a\n\t\t\t\t\tchance it is actually just blocked indefinitely - so really\n\t\t\t\t\tit should be reported as being in the Blocked state. */\n\t\t\t\t\tif( eState == eSuspended )\n\t\t\t\t\t{\n\t\t\t\t\t\tvTaskSuspendAll();\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tif( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )\n\t\t\t\t\t\t\t{\n\t\t\t\t\t\t\t\tpxTaskStatus->eCurrentState = eBlocked;\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\t#endif /* INCLUDE_vTaskSuspend */\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTaskStatus->eCurrentState = eTaskGetState( pxTCB );\n\t\t}\n\n\t\t/* Obtaining the stack space takes some time, so the xGetFreeStackSpace\n\t\tparameter is provided to allow it to be skipped. */\n\t\tif( xGetFreeStackSpace != pdFALSE )\n\t\t{\n\t\t\t#if ( portSTACK_GROWTH > 0 )\n\t\t\t{\n\t\t\t\tpxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\tpxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );\n\t\t\t}\n\t\t\t#endif\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTaskStatus->usStackHighWaterMark = 0;\n\t\t}\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tstatic UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )\n\t{\n\tconfigLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;\n\tUBaseType_t uxTask = 0;\n\n\t\tif( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )\n\t\t{\n\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t\t\t/* Populate an TaskStatus_t structure within the\n\t\t\tpxTaskStatusArray array for each task that is referenced from\n\t\t\tpxList.  See the definition of TaskStatus_t in task.h for the\n\t\t\tmeaning of each TaskStatus_t structure member. */\n\t\t\tdo\n\t\t\t{\n\t\t\t\tlistGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t\t\tvTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );\n\t\t\t\tuxTask++;\n\t\t\t} while( pxNextTCB != pxFirstTCB );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn uxTask;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )\n\n\tstatic configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )\n\t{\n\tuint32_t ulCount = 0U;\n\n\t\twhile( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )\n\t\t{\n\t\t\tpucStackByte -= portSTACK_GROWTH;\n\t\t\tulCount++;\n\t\t}\n\n\t\tulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */\n\n\t\treturn ( configSTACK_DEPTH_TYPE ) ulCount;\n\t}\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )\n\n\t/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the\n\tsame except for their return type.  Using configSTACK_DEPTH_TYPE allows the\n\tuser to determine the return type.  It gets around the problem of the value\n\toverflowing on 8-bit types without breaking backward compatibility for\n\tapplications that expect an 8-bit return type. */\n\tconfigSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tuint8_t *pucEndOfStack;\n\tconfigSTACK_DEPTH_TYPE uxReturn;\n\n\t\t/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are\n\t\tthe same except for their return type.  Using configSTACK_DEPTH_TYPE\n\t\tallows the user to determine the return type.  It gets around the\n\t\tproblem of the value overflowing on 8-bit types without breaking\n\t\tbackward compatibility for applications that expect an 8-bit return\n\t\ttype. */\n\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t#if portSTACK_GROWTH < 0\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n\t\t}\n\t\t#endif\n\n\t\tuxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\n\n\tUBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tuint8_t *pucEndOfStack;\n\tUBaseType_t uxReturn;\n\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\t#if portSTACK_GROWTH < 0\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxStack;\n\t\t}\n\t\t#else\n\t\t{\n\t\t\tpucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;\n\t\t}\n\t\t#endif\n\n\t\tuxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );\n\n\t\treturn uxReturn;\n\t}\n\n#endif /* INCLUDE_uxTaskGetStackHighWaterMark */\n/*-----------------------------------------------------------*/\n\n#if ( INCLUDE_vTaskDelete == 1 )\n\n\tstatic void prvDeleteTCB( TCB_t *pxTCB )\n\t{\n\t\t/* This call is required specifically for the TriCore port.  It must be\n\t\tabove the vPortFree() calls.  The call is also used by ports/demos that\n\t\twant to allocate and clean RAM statically. */\n\t\tportCLEAN_UP_TCB( pxTCB );\n\n\t\t/* Free up the memory allocated by the scheduler for the task.  It is up\n\t\tto the task to free any memory allocated at the application level.\n\t\tSee the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html\n\t\tfor additional information. */\n\t\t#if ( configUSE_NEWLIB_REENTRANT == 1 )\n\t\t{\n\t\t\t_reclaim_reent( &( pxTCB->xNewLib_reent ) );\n\t\t}\n\t\t#endif /* configUSE_NEWLIB_REENTRANT */\n\n\t\t#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )\n\t\t{\n\t\t\t/* The task can only have been allocated dynamically - free both\n\t\t\tthe stack and TCB. */\n\t\t\tvPortFree( pxTCB->pxStack );\n\t\t\tvPortFree( pxTCB );\n\t\t}\n\t\t#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */\n\t\t{\n\t\t\t/* The task could have been allocated statically or dynamically, so\n\t\t\tcheck what was statically allocated before trying to free the\n\t\t\tmemory. */\n\t\t\tif( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )\n\t\t\t{\n\t\t\t\t/* Both the stack and TCB were allocated dynamically, so both\n\t\t\t\tmust be freed. */\n\t\t\t\tvPortFree( pxTCB->pxStack );\n\t\t\t\tvPortFree( pxTCB );\n\t\t\t}\n\t\t\telse if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )\n\t\t\t{\n\t\t\t\t/* Only the stack was statically allocated, so the TCB is the\n\t\t\t\tonly memory that must be freed. */\n\t\t\t\tvPortFree( pxTCB );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* Neither the stack nor the TCB were allocated dynamically, so\n\t\t\t\tnothing needs to be freed. */\n\t\t\t\tconfigASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB\t);\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t}\n\n#endif /* INCLUDE_vTaskDelete */\n/*-----------------------------------------------------------*/\n\nstatic void prvResetNextTaskUnblockTime( void )\n{\nTCB_t *pxTCB;\n\n\tif( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )\n\t{\n\t\t/* The new current delayed list is empty.  Set xNextTaskUnblockTime to\n\t\tthe maximum possible value so it is\textremely unlikely that the\n\t\tif( xTickCount >= xNextTaskUnblockTime ) test will pass until\n\t\tthere is an item in the delayed list. */\n\t\txNextTaskUnblockTime = portMAX_DELAY;\n\t}\n\telse\n\t{\n\t\t/* The new current delayed list is not empty, get the value of\n\t\tthe item at the head of the delayed list.  This is the time at\n\t\twhich the task at the head of the delayed list should be removed\n\t\tfrom the Blocked state. */\n\t\t( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\txNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );\n\t}\n}\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )\n\n\tTaskHandle_t xTaskGetCurrentTaskHandle( void )\n\t{\n\tTaskHandle_t xReturn;\n\n\t\t/* A critical section is not required as this is not called from\n\t\tan interrupt and the current TCB will always be the same for any\n\t\tindividual execution thread. */\n\t\txReturn = pxCurrentTCB;\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )\n\n\tBaseType_t xTaskGetSchedulerState( void )\n\t{\n\tBaseType_t xReturn;\n\n\t\tif( xSchedulerRunning == pdFALSE )\n\t\t{\n\t\t\txReturn = taskSCHEDULER_NOT_STARTED;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t{\n\t\t\t\txReturn = taskSCHEDULER_RUNNING;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = taskSCHEDULER_SUSPENDED;\n\t\t\t}\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tBaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )\n\t{\n\tTCB_t * const pxMutexHolderTCB = pxMutexHolder;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\t/* If the mutex was given back by an interrupt while the queue was\n\t\tlocked then the mutex holder might now be NULL.  _RB_ Is this still\n\t\tneeded as interrupts can no longer use mutexes? */\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* If the holder of the mutex has a priority below the priority of\n\t\t\tthe task attempting to obtain the mutex then it will temporarily\n\t\t\tinherit the priority of the task attempting to obtain the mutex. */\n\t\t\tif( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )\n\t\t\t{\n\t\t\t\t/* Adjust the mutex holder state to account for its new\n\t\t\t\tpriority.  Only reset the event list item value if the value is\n\t\t\t\tnot being used for anything else. */\n\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t{\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\n\t\t\t\t/* If the task being modified is in the ready state it will need\n\t\t\t\tto be moved into a new list. */\n\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tif( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* It is known that the task is in its ready list so\n\t\t\t\t\t\tthere is no need to check again and the port level\n\t\t\t\t\t\treset macro can be called directly. */\n\t\t\t\t\t\tportRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Inherit the priority before being moved into the new list. */\n\t\t\t\t\tpxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n\t\t\t\t\tprvAddTaskToReadyList( pxMutexHolderTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* Just inherit the priority. */\n\t\t\t\t\tpxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;\n\t\t\t\t}\n\n\t\t\t\ttraceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );\n\n\t\t\t\t/* Inheritance occurred. */\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tif( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The base priority of the mutex holder is lower than the\n\t\t\t\t\tpriority of the task attempting to take the mutex, but the\n\t\t\t\t\tcurrent priority of the mutex holder is not lower than the\n\t\t\t\t\tpriority of the task attempting to take the mutex.\n\t\t\t\t\tTherefore the mutex holder must have already inherited a\n\t\t\t\t\tpriority, but inheritance would have occurred if that had\n\t\t\t\t\tnot been the case. */\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tBaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )\n\t{\n\tTCB_t * const pxTCB = pxMutexHolder;\n\tBaseType_t xReturn = pdFALSE;\n\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* A task can only have an inherited priority if it holds the mutex.\n\t\t\tIf the mutex is held by a task then it cannot be given from an\n\t\t\tinterrupt, and if a mutex is given by the holding task then it must\n\t\t\tbe the running state task. */\n\t\t\tconfigASSERT( pxTCB == pxCurrentTCB );\n\t\t\tconfigASSERT( pxTCB->uxMutexesHeld );\n\t\t\t( pxTCB->uxMutexesHeld )--;\n\n\t\t\t/* Has the holder of the mutex inherited the priority of another\n\t\t\ttask? */\n\t\t\tif( pxTCB->uxPriority != pxTCB->uxBasePriority )\n\t\t\t{\n\t\t\t\t/* Only disinherit if no other mutexes are held. */\n\t\t\t\tif( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\t/* A task can only have an inherited priority if it holds\n\t\t\t\t\tthe mutex.  If the mutex is held by a task then it cannot be\n\t\t\t\t\tgiven from an interrupt, and if a mutex is given by the\n\t\t\t\t\tholding task then it must be the running state task.  Remove\n\t\t\t\t\tthe holding task from the ready/delayed list. */\n\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t{\n\t\t\t\t\t\ttaskRESET_READY_PRIORITY( pxTCB->uxPriority );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Disinherit the priority before adding the task into the\n\t\t\t\t\tnew\tready list. */\n\t\t\t\t\ttraceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\n\t\t\t\t\tpxTCB->uxPriority = pxTCB->uxBasePriority;\n\n\t\t\t\t\t/* Reset the event list item value.  It cannot be in use for\n\t\t\t\t\tany other purpose if this task is running, and it must be\n\t\t\t\t\trunning to give back the mutex. */\n\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t\t/* Return true to indicate that a context switch is required.\n\t\t\t\t\tThis is only actually required in the corner case whereby\n\t\t\t\t\tmultiple mutexes were held and the mutexes were given back\n\t\t\t\t\tin an order different to that in which they were taken.\n\t\t\t\t\tIf a context switch did not occur when the first mutex was\n\t\t\t\t\treturned, even if a task was waiting on it, then a context\n\t\t\t\t\tswitch should occur when the last mutex is returned whether\n\t\t\t\t\ta task is waiting on it or not. */\n\t\t\t\t\txReturn = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tvoid vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )\n\t{\n\tTCB_t * const pxTCB = pxMutexHolder;\n\tUBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;\n\tconst UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;\n\n\t\tif( pxMutexHolder != NULL )\n\t\t{\n\t\t\t/* If pxMutexHolder is not NULL then the holder must hold at least\n\t\t\tone mutex. */\n\t\t\tconfigASSERT( pxTCB->uxMutexesHeld );\n\n\t\t\t/* Determine the priority to which the priority of the task that\n\t\t\tholds the mutex should be set.  This will be the greater of the\n\t\t\tholding task's base priority and the priority of the highest\n\t\t\tpriority task that is waiting to obtain the mutex. */\n\t\t\tif( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )\n\t\t\t{\n\t\t\t\tuxPriorityToUse = uxHighestPriorityWaitingTask;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tuxPriorityToUse = pxTCB->uxBasePriority;\n\t\t\t}\n\n\t\t\t/* Does the priority need to change? */\n\t\t\tif( pxTCB->uxPriority != uxPriorityToUse )\n\t\t\t{\n\t\t\t\t/* Only disinherit if no other mutexes are held.  This is a\n\t\t\t\tsimplification in the priority inheritance implementation.  If\n\t\t\t\tthe task that holds the mutex is also holding other mutexes then\n\t\t\t\tthe other mutexes may have caused the priority inheritance. */\n\t\t\t\tif( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )\n\t\t\t\t{\n\t\t\t\t\t/* If a task has timed out because it already holds the\n\t\t\t\t\tmutex it was trying to obtain then it cannot of inherited\n\t\t\t\t\tits own priority. */\n\t\t\t\t\tconfigASSERT( pxTCB != pxCurrentTCB );\n\n\t\t\t\t\t/* Disinherit the priority, remembering the previous\n\t\t\t\t\tpriority to facilitate determining the subject task's\n\t\t\t\t\tstate. */\n\t\t\t\t\ttraceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );\n\t\t\t\t\tuxPriorityUsedOnEntry = pxTCB->uxPriority;\n\t\t\t\t\tpxTCB->uxPriority = uxPriorityToUse;\n\n\t\t\t\t\t/* Only reset the event list item value if the value is not\n\t\t\t\t\tbeing used for anything else. */\n\t\t\t\t\tif( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\n\t\t\t\t\t/* If the running task is not the task that holds the mutex\n\t\t\t\t\tthen the task that holds the mutex could be in either the\n\t\t\t\t\tReady, Blocked or Suspended states.  Only remove the task\n\t\t\t\t\tfrom its current state list if it is in the Ready state as\n\t\t\t\t\tthe task's priority is going to change and there is one\n\t\t\t\t\tReady list per priority. */\n\t\t\t\t\tif( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\tif( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* It is known that the task is in its ready list so\n\t\t\t\t\t\t\tthere is no need to check again and the port level\n\t\t\t\t\t\t\treset macro can be called directly. */\n\t\t\t\t\t\t\tportRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\n\t\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n\tvoid vTaskEnterCritical( void )\n\t{\n\t\tportDISABLE_INTERRUPTS();\n\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\t( pxCurrentTCB->uxCriticalNesting )++;\n\n\t\t\t/* This is not the interrupt safe version of the enter critical\n\t\t\tfunction so\tassert() if it is being called from an interrupt\n\t\t\tcontext.  Only API functions that end in \"FromISR\" can be used in an\n\t\t\tinterrupt.  Only assert if the critical nesting count is 1 to\n\t\t\tprotect against recursive calls if the assert function also uses a\n\t\t\tcritical section. */\n\t\t\tif( pxCurrentTCB->uxCriticalNesting == 1 )\n\t\t\t{\n\t\t\t\tportASSERT_IF_IN_ISR();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( portCRITICAL_NESTING_IN_TCB == 1 )\n\n\tvoid vTaskExitCritical( void )\n\t{\n\t\tif( xSchedulerRunning != pdFALSE )\n\t\t{\n\t\t\tif( pxCurrentTCB->uxCriticalNesting > 0U )\n\t\t\t{\n\t\t\t\t( pxCurrentTCB->uxCriticalNesting )--;\n\n\t\t\t\tif( pxCurrentTCB->uxCriticalNesting == 0U )\n\t\t\t\t{\n\t\t\t\t\tportENABLE_INTERRUPTS();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* portCRITICAL_NESTING_IN_TCB */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )\n\n\tstatic char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )\n\t{\n\tsize_t x;\n\n\t\t/* Start by copying the entire string. */\n\t\tstrcpy( pcBuffer, pcTaskName );\n\n\t\t/* Pad the end of the string with spaces to ensure columns line up when\n\t\tprinted out. */\n\t\tfor( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )\n\t\t{\n\t\t\tpcBuffer[ x ] = ' ';\n\t\t}\n\n\t\t/* Terminate. */\n\t\tpcBuffer[ x ] = ( char ) 0x00;\n\n\t\t/* Return the new end of string. */\n\t\treturn &( pcBuffer[ x ] );\n\t}\n\n#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */\n/*-----------------------------------------------------------*/\n\n#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tvoid vTaskList( char * pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tUBaseType_t uxArraySize, x;\n\tchar cStatus;\n\n\t\t/*\n\t\t * PLEASE NOTE:\n\t\t *\n\t\t * This function is provided for convenience only, and is used by many\n\t\t * of the demo applications.  Do not consider it to be part of the\n\t\t * scheduler.\n\t\t *\n\t\t * vTaskList() calls uxTaskGetSystemState(), then formats part of the\n\t\t * uxTaskGetSystemState() output into a human readable table that\n\t\t * displays task names, states and stack usage.\n\t\t *\n\t\t * vTaskList() has a dependency on the sprintf() C library function that\n\t\t * might bloat the code size, use a lot of stack, and provide different\n\t\t * results on different platforms.  An alternative, tiny, third party,\n\t\t * and limited functionality implementation of sprintf() is provided in\n\t\t * many of the FreeRTOS/Demo sub-directories in a file called\n\t\t * printf-stdarg.c (note printf-stdarg.c does not provide a full\n\t\t * snprintf() implementation!).\n\t\t *\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\n\t\t * directly to get access to raw stats data, rather than indirectly\n\t\t * through a call to vTaskList().\n\t\t */\n\n\n\t\t/* Make sure the write buffer does not contain a string. */\n\t\t*pcWriteBuffer = ( char ) 0x00;\n\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\n\t\tfunction is executing. */\n\t\tuxArraySize = uxCurrentNumberOfTasks;\n\n\t\t/* Allocate an array index for each task.  NOTE!  if\n\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n\t\tequate to NULL. */\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t/* Generate the (binary) data. */\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );\n\n\t\t\t/* Create a human readable table from the binary data. */\n\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t{\n\t\t\t\tswitch( pxTaskStatusArray[ x ].eCurrentState )\n\t\t\t\t{\n\t\t\t\t\tcase eRunning:\t\tcStatus = tskRUNNING_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eReady:\t\tcStatus = tskREADY_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eBlocked:\t\tcStatus = tskBLOCKED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eSuspended:\tcStatus = tskSUSPENDED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eDeleted:\t\tcStatus = tskDELETED_CHAR;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\n\t\t\t\t\tcase eInvalid:\t\t/* Fall through. */\n\t\t\t\t\tdefault:\t\t\t/* Should not get here, but it is included\n\t\t\t\t\t\t\t\t\t\tto prevent static checking errors. */\n\t\t\t\t\t\t\t\t\t\tcStatus = ( char ) 0x00;\n\t\t\t\t\t\t\t\t\t\tbreak;\n\t\t\t\t}\n\n\t\t\t\t/* Write the task name to the string, padding with spaces so it\n\t\t\t\tcan be printed in tabular form more easily. */\n\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n\t\t\t\t/* Write the rest of the string. */\n\t\t\t\tsprintf( pcWriteBuffer, \"\\t%c\\t%u\\t%u\\t%u\\r\\n\", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n\t\t\t}\n\n\t\t\t/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n\t\t\tis 0 then vPortFree() will be #defined to nothing. */\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */\n/*----------------------------------------------------------*/\n\n#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )\n\n\tvoid vTaskGetRunTimeStats( char *pcWriteBuffer )\n\t{\n\tTaskStatus_t *pxTaskStatusArray;\n\tUBaseType_t uxArraySize, x;\n\tuint32_t ulTotalTime, ulStatsAsPercentage;\n\n\t\t#if( configUSE_TRACE_FACILITY != 1 )\n\t\t{\n\t\t\t#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().\n\t\t}\n\t\t#endif\n\n\t\t/*\n\t\t * PLEASE NOTE:\n\t\t *\n\t\t * This function is provided for convenience only, and is used by many\n\t\t * of the demo applications.  Do not consider it to be part of the\n\t\t * scheduler.\n\t\t *\n\t\t * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part\n\t\t * of the uxTaskGetSystemState() output into a human readable table that\n\t\t * displays the amount of time each task has spent in the Running state\n\t\t * in both absolute and percentage terms.\n\t\t *\n\t\t * vTaskGetRunTimeStats() has a dependency on the sprintf() C library\n\t\t * function that might bloat the code size, use a lot of stack, and\n\t\t * provide different results on different platforms.  An alternative,\n\t\t * tiny, third party, and limited functionality implementation of\n\t\t * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in\n\t\t * a file called printf-stdarg.c (note printf-stdarg.c does not provide\n\t\t * a full snprintf() implementation!).\n\t\t *\n\t\t * It is recommended that production systems call uxTaskGetSystemState()\n\t\t * directly to get access to raw stats data, rather than indirectly\n\t\t * through a call to vTaskGetRunTimeStats().\n\t\t */\n\n\t\t/* Make sure the write buffer does not contain a string. */\n\t\t*pcWriteBuffer = ( char ) 0x00;\n\n\t\t/* Take a snapshot of the number of tasks in case it changes while this\n\t\tfunction is executing. */\n\t\tuxArraySize = uxCurrentNumberOfTasks;\n\n\t\t/* Allocate an array index for each task.  NOTE!  If\n\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will\n\t\tequate to NULL. */\n\t\tpxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */\n\n\t\tif( pxTaskStatusArray != NULL )\n\t\t{\n\t\t\t/* Generate the (binary) data. */\n\t\t\tuxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );\n\n\t\t\t/* For percentage calculations. */\n\t\t\tulTotalTime /= 100UL;\n\n\t\t\t/* Avoid divide by zero errors. */\n\t\t\tif( ulTotalTime > 0UL )\n\t\t\t{\n\t\t\t\t/* Create a human readable table from the binary data. */\n\t\t\t\tfor( x = 0; x < uxArraySize; x++ )\n\t\t\t\t{\n\t\t\t\t\t/* What percentage of the total run time has the task used?\n\t\t\t\t\tThis will always be rounded down to the nearest integer.\n\t\t\t\t\tulTotalRunTimeDiv100 has already been divided by 100. */\n\t\t\t\t\tulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;\n\n\t\t\t\t\t/* Write the task name to the string, padding with\n\t\t\t\t\tspaces so it can be printed in tabular form more\n\t\t\t\t\teasily. */\n\t\t\t\t\tpcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );\n\n\t\t\t\t\tif( ulStatsAsPercentage > 0UL )\n\t\t\t\t\t{\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t%lu%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\n\t\t\t\t\t\t\tprintf() library can be used. */\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t%u%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If the percentage is zero here then the task has\n\t\t\t\t\t\tconsumed less than 1% of the total run time. */\n\t\t\t\t\t\t#ifdef portLU_PRINTF_SPECIFIER_REQUIRED\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%lu\\t\\t<1%%\\r\\n\", pxTaskStatusArray[ x ].ulRunTimeCounter );\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#else\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\t/* sizeof( int ) == sizeof( long ) so a smaller\n\t\t\t\t\t\t\tprintf() library can be used. */\n\t\t\t\t\t\t\tsprintf( pcWriteBuffer, \"\\t%u\\t\\t<1%%\\r\\n\", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */\n\t\t\t\t\t\t}\n\t\t\t\t\t\t#endif\n\t\t\t\t\t}\n\n\t\t\t\t\tpcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\t/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION\n\t\t\tis 0 then vPortFree() will be #defined to nothing. */\n\t\t\tvPortFree( pxTaskStatusArray );\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */\n/*-----------------------------------------------------------*/\n\nTickType_t uxTaskResetEventItemValue( void )\n{\nTickType_t uxReturn;\n\n\tuxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );\n\n\t/* Reset the event list item to its normal value - so it can be used with\n\tqueues and semaphores. */\n\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_MUTEXES == 1 )\n\n\tTaskHandle_t pvTaskIncrementMutexHeldCount( void )\n\t{\n\t\t/* If xSemaphoreCreateMutex() is called before any tasks have been created\n\t\tthen pxCurrentTCB will be NULL. */\n\t\tif( pxCurrentTCB != NULL )\n\t\t{\n\t\t\t( pxCurrentTCB->uxMutexesHeld )++;\n\t\t}\n\n\t\treturn pxCurrentTCB;\n\t}\n\n#endif /* configUSE_MUTEXES */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tuint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )\n\t{\n\tuint32_t ulReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Only block if the notification count is not already non-zero. */\n\t\t\tif( pxCurrentTCB->ulNotifiedValue == 0UL )\n\t\t\t{\n\t\t\t\t/* Mark this task as waiting for a notification. */\n\t\t\t\tpxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;\n\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n\t\t\t\t\ttraceTASK_NOTIFY_TAKE_BLOCK();\n\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\n\t\t\t\t\tsection (some will yield immediately, others wait until the\n\t\t\t\t\tcritical section exits) - but it is not something that\n\t\t\t\t\tapplication code should ever do. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\ttraceTASK_NOTIFY_TAKE();\n\t\t\tulReturn = pxCurrentTCB->ulNotifiedValue;\n\n\t\t\tif( ulReturn != 0UL )\n\t\t\t{\n\t\t\t\tif( xClearCountOnExit != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB->ulNotifiedValue = 0UL;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tpxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\tpxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn ulReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )\n\t{\n\tBaseType_t xReturn;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Only block if a notification is not already pending. */\n\t\t\tif( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\t/* Clear bits in the task's notification value as bits may get\n\t\t\t\tset\tby the notifying task or interrupt.  This can be used to\n\t\t\t\tclear the value to zero. */\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;\n\n\t\t\t\t/* Mark this task as waiting for a notification. */\n\t\t\t\tpxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;\n\n\t\t\t\tif( xTicksToWait > ( TickType_t ) 0 )\n\t\t\t\t{\n\t\t\t\t\tprvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );\n\t\t\t\t\ttraceTASK_NOTIFY_WAIT_BLOCK();\n\n\t\t\t\t\t/* All ports are written to allow a yield in a critical\n\t\t\t\t\tsection (some will yield immediately, others wait until the\n\t\t\t\t\tcritical section exits) - but it is not something that\n\t\t\t\t\tapplication code should ever do. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\ttraceTASK_NOTIFY_WAIT();\n\n\t\t\tif( pulNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t/* Output the current notification value, which may or may not\n\t\t\t\thave changed. */\n\t\t\t\t*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\t/* If ucNotifyValue is set then either the task never entered the\n\t\t\tblocked state (because a notification was already pending) or the\n\t\t\ttask unblocked because of a notification.  Otherwise the task\n\t\t\tunblocked because of a timeout. */\n\t\t\tif( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\t/* A notification was not received. */\n\t\t\t\txReturn = pdFALSE;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* A notification was already pending or a notification was\n\t\t\t\treceived while the task was waiting. */\n\t\t\t\tpxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;\n\t\t\t\txReturn = pdTRUE;\n\t\t\t}\n\n\t\t\tpxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )\n\t{\n\tTCB_t * pxTCB;\n\tBaseType_t xReturn = pdPASS;\n\tuint8_t ucOriginalNotifyState;\n\n\t\tconfigASSERT( xTaskToNotify );\n\t\tpxTCB = xTaskToNotify;\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pulPreviousNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\tswitch( eAction )\n\t\t\t{\n\t\t\t\tcase eSetBits\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eIncrement\t:\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithOverwrite\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithoutOverwrite :\n\t\t\t\t\tif( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The value could not be written to the task. */\n\t\t\t\t\t\txReturn = pdFAIL;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eNoAction:\n\t\t\t\t\t/* The task is being notified without its notify value being\n\t\t\t\t\tupdated. */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\t/* Should not get here if all enums are handled.\n\t\t\t\t\tArtificially force an assert by testing a value the\n\t\t\t\t\tcompiler can't assume is const. */\n\t\t\t\t\tconfigASSERT( pxTCB->ulNotifiedValue == ~0UL );\n\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ttraceTASK_NOTIFY();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\t#if( configUSE_TICKLESS_IDLE != 0 )\n\t\t\t\t{\n\t\t\t\t\t/* If a task is blocked waiting for a notification then\n\t\t\t\t\txNextTaskUnblockTime might be set to the blocked task's time\n\t\t\t\t\tout time.  If the task is unblocked for a reason other than\n\t\t\t\t\ta timeout xNextTaskUnblockTime is normally left unchanged,\n\t\t\t\t\tbecause it will automatically get reset to a new value when\n\t\t\t\t\tthe tick count equals xNextTaskUnblockTime.  However if\n\t\t\t\t\ttickless idling is used it might be more important to enter\n\t\t\t\t\tsleep mode at the earliest possible time - so reset\n\t\t\t\t\txNextTaskUnblockTime here to ensure it is updated at the\n\t\t\t\t\tearliest possible time. */\n\t\t\t\t\tprvResetNextTaskUnblockTime();\n\t\t\t\t}\n\t\t\t\t#endif\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\ttaskYIELD_IF_USING_PREEMPTION();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tTCB_t * pxTCB;\n\tuint8_t ucOriginalNotifyState;\n\tBaseType_t xReturn = pdPASS;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToNotify );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tpxTCB = xTaskToNotify;\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tif( pulPreviousNotificationValue != NULL )\n\t\t\t{\n\t\t\t\t*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;\n\t\t\t}\n\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\tswitch( eAction )\n\t\t\t{\n\t\t\t\tcase eSetBits\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue |= ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eIncrement\t:\n\t\t\t\t\t( pxTCB->ulNotifiedValue )++;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithOverwrite\t:\n\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eSetValueWithoutOverwrite :\n\t\t\t\t\tif( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )\n\t\t\t\t\t{\n\t\t\t\t\t\tpxTCB->ulNotifiedValue = ulValue;\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The value could not be written to the task. */\n\t\t\t\t\t\txReturn = pdFAIL;\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase eNoAction :\n\t\t\t\t\t/* The task is being notified without its notify value being\n\t\t\t\t\tupdated. */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault:\n\t\t\t\t\t/* Should not get here if all enums are handled.\n\t\t\t\t\tArtificially force an assert by testing a value the\n\t\t\t\t\tcompiler can't assume is const. */\n\t\t\t\t\tconfigASSERT( pxTCB->ulNotifiedValue == ~0UL );\n\t\t\t\t\tbreak;\n\t\t\t}\n\n\t\t\ttraceTASK_NOTIFY_FROM_ISR();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Mark that a yield is pending in case the user is not\n\t\t\t\t\tusing the \"xHigherPriorityTaskWoken\" parameter to an ISR\n\t\t\t\t\tsafe FreeRTOS function. */\n\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tvoid vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tTCB_t * pxTCB;\n\tuint8_t ucOriginalNotifyState;\n\tUBaseType_t uxSavedInterruptStatus;\n\n\t\tconfigASSERT( xTaskToNotify );\n\n\t\t/* RTOS ports that support interrupt nesting have the concept of a\n\t\tmaximum\tsystem call (or maximum API call) interrupt priority.\n\t\tInterrupts that are\tabove the maximum system call priority are keep\n\t\tpermanently enabled, even when the RTOS kernel is in a critical section,\n\t\tbut cannot make any calls to FreeRTOS API functions.  If configASSERT()\n\t\tis defined in FreeRTOSConfig.h then\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion\n\t\tfailure if a FreeRTOS API function is called from an interrupt that has\n\t\tbeen assigned a priority above the configured maximum system call\n\t\tpriority.  Only FreeRTOS functions that end in FromISR can be called\n\t\tfrom interrupts\tthat have been assigned a priority at or (logically)\n\t\tbelow the maximum system call interrupt priority.  FreeRTOS maintains a\n\t\tseparate interrupt safe API to ensure interrupt entry is as fast and as\n\t\tsimple as possible.  More information (albeit Cortex-M specific) is\n\t\tprovided on the following link:\n\t\thttp://www.freertos.org/RTOS-Cortex-M3-M4.html */\n\t\tportASSERT_IF_INTERRUPT_PRIORITY_INVALID();\n\n\t\tpxTCB = xTaskToNotify;\n\n\t\tuxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();\n\t\t{\n\t\t\tucOriginalNotifyState = pxTCB->ucNotifyState;\n\t\t\tpxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;\n\n\t\t\t/* 'Giving' is equivalent to incrementing a count in a counting\n\t\t\tsemaphore. */\n\t\t\t( pxTCB->ulNotifiedValue )++;\n\n\t\t\ttraceTASK_NOTIFY_GIVE_FROM_ISR();\n\n\t\t\t/* If the task is in the blocked state specifically to wait for a\n\t\t\tnotification then unblock it now. */\n\t\t\tif( ucOriginalNotifyState == taskWAITING_NOTIFICATION )\n\t\t\t{\n\t\t\t\t/* The task should not have been on an event list. */\n\t\t\t\tconfigASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );\n\n\t\t\t\tif( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t( void ) uxListRemove( &( pxTCB->xStateListItem ) );\n\t\t\t\t\tprvAddTaskToReadyList( pxTCB );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\t/* The delayed and ready lists cannot be accessed, so hold\n\t\t\t\t\tthis task pending until the scheduler is resumed. */\n\t\t\t\t\tvListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );\n\t\t\t\t}\n\n\t\t\t\tif( pxTCB->uxPriority > pxCurrentTCB->uxPriority )\n\t\t\t\t{\n\t\t\t\t\t/* The notified task has a priority above the currently\n\t\t\t\t\texecuting task so a yield is required. */\n\t\t\t\t\tif( pxHigherPriorityTaskWoken != NULL )\n\t\t\t\t\t{\n\t\t\t\t\t\t*pxHigherPriorityTaskWoken = pdTRUE;\n\t\t\t\t\t}\n\n\t\t\t\t\t/* Mark that a yield is pending in case the user is not\n\t\t\t\t\tusing the \"xHigherPriorityTaskWoken\" parameter in an ISR\n\t\t\t\t\tsafe FreeRTOS function. */\n\t\t\t\t\txYieldPending = pdTRUE;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tportCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tBaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )\n\t{\n\tTCB_t *pxTCB;\n\tBaseType_t xReturn;\n\n\t\t/* If null is passed in here then it is the calling task that is having\n\t\tits notification state cleared. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\tif( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )\n\t\t\t{\n\t\t\t\tpxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = pdFAIL;\n\t\t\t}\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn xReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( configUSE_TASK_NOTIFICATIONS == 1 )\n\n\tuint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear )\n\t{\n\tTCB_t *pxTCB;\n\tuint32_t ulReturn;\n\n\t\t/* If null is passed in here then it is the calling task that is having\n\t\tits notification state cleared. */\n\t\tpxTCB = prvGetTCBFromHandle( xTask );\n\n\t\ttaskENTER_CRITICAL();\n\t\t{\n\t\t\t/* Return the notification as it was before the bits were cleared,\n\t\t\tthen clear the bit mask. */\n\t\t\tulReturn = pxCurrentTCB->ulNotifiedValue;\n\t\t\tpxTCB->ulNotifiedValue &= ~ulBitsToClear;\n\t\t}\n\t\ttaskEXIT_CRITICAL();\n\n\t\treturn ulReturn;\n\t}\n\n#endif /* configUSE_TASK_NOTIFICATIONS */\n/*-----------------------------------------------------------*/\n\n#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )\n\n\tuint32_t ulTaskGetIdleRunTimeCounter( void )\n\t{\n\t\treturn xIdleTaskHandle->ulRunTimeCounter;\n\t}\n\n#endif\n/*-----------------------------------------------------------*/\n\nstatic void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )\n{\nTickType_t xTimeToWake;\nconst TickType_t xConstTickCount = xTickCount;\n\n\t#if( INCLUDE_xTaskAbortDelay == 1 )\n\t{\n\t\t/* About to enter a delayed list, so ensure the ucDelayAborted flag is\n\t\treset to pdFALSE so it can be detected as having been set to pdTRUE\n\t\twhen the task leaves the Blocked state. */\n\t\tpxCurrentTCB->ucDelayAborted = pdFALSE;\n\t}\n\t#endif\n\n\t/* Remove the task from the ready list before adding it to the blocked list\n\tas the same list item is used for both lists. */\n\tif( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )\n\t{\n\t\t/* The current task must be in a ready list, so there is no need to\n\t\tcheck, and the port reset macro can be called directly. */\n\t\tportRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t#if ( INCLUDE_vTaskSuspend == 1 )\n\t{\n\t\tif( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )\n\t\t{\n\t\t\t/* Add the task to the suspended task list instead of a delayed task\n\t\t\tlist to ensure it is not woken by a timing event.  It will block\n\t\t\tindefinitely. */\n\t\t\tvListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Calculate the time at which the task should be woken if the event\n\t\t\tdoes not occur.  This may overflow but this doesn't matter, the\n\t\t\tkernel will manage it correctly. */\n\t\t\txTimeToWake = xConstTickCount + xTicksToWait;\n\n\t\t\t/* The list item will be inserted in wake time order. */\n\t\t\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n\t\t\tif( xTimeToWake < xConstTickCount )\n\t\t\t{\n\t\t\t\t/* Wake time has overflowed.  Place this item in the overflow\n\t\t\t\tlist. */\n\t\t\t\tvListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The wake time has not overflowed, so the current block list\n\t\t\t\tis used. */\n\t\t\t\tvListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n\t\t\t\t/* If the task entering the blocked state was placed at the\n\t\t\t\thead of the list of blocked tasks then xNextTaskUnblockTime\n\t\t\t\tneeds to be updated too. */\n\t\t\t\tif( xTimeToWake < xNextTaskUnblockTime )\n\t\t\t\t{\n\t\t\t\t\txNextTaskUnblockTime = xTimeToWake;\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t}\n\t#else /* INCLUDE_vTaskSuspend */\n\t{\n\t\t/* Calculate the time at which the task should be woken if the event\n\t\tdoes not occur.  This may overflow but this doesn't matter, the kernel\n\t\twill manage it correctly. */\n\t\txTimeToWake = xConstTickCount + xTicksToWait;\n\n\t\t/* The list item will be inserted in wake time order. */\n\t\tlistSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );\n\n\t\tif( xTimeToWake < xConstTickCount )\n\t\t{\n\t\t\t/* Wake time has overflowed.  Place this item in the overflow list. */\n\t\t\tvListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* The wake time has not overflowed, so the current block list is used. */\n\t\t\tvListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );\n\n\t\t\t/* If the task entering the blocked state was placed at the head of the\n\t\t\tlist of blocked tasks then xNextTaskUnblockTime needs to be updated\n\t\t\ttoo. */\n\t\t\tif( xTimeToWake < xNextTaskUnblockTime )\n\t\t\t{\n\t\t\t\txNextTaskUnblockTime = xTimeToWake;\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\n\t\t/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */\n\t\t( void ) xCanBlockIndefinitely;\n\t}\n\t#endif /* INCLUDE_vTaskSuspend */\n}\n\n/* Code below here allows additional code to be inserted into this source file,\nespecially where access to file scope functions and data is needed (for example\nwhen performing module tests). */\n\n#ifdef FREERTOS_MODULE_TEST\n\t#include \"tasks_test_access_functions.h\"\n#endif\n\n\n#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )\n\n\t#include \"freertos_tasks_c_additions.h\"\n\n\t#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT\n\t\tstatic void freertos_tasks_c_additions_init( void )\n\t\t{\n\t\t\tFREERTOS_TASKS_C_ADDITIONS_INIT();\n\t\t}\n\t#endif\n\n#endif\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Middlewares/Third_Party/FreeRTOS/Source/timers.c",
    "content": "/*\n * FreeRTOS Kernel V10.3.1\n * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy of\n * this software and associated documentation files (the \"Software\"), to deal in\n * the Software without restriction, including without limitation the rights to\n * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\n * the Software, and to permit persons to whom the Software is furnished to do so,\n * subject to the following conditions:\n *\n * The above copyright notice and this permission notice shall be included in all\n * copies or substantial portions of the Software.\n *\n * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\n * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\n * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\n * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\n * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\n *\n * http://www.FreeRTOS.org\n * http://aws.amazon.com/freertos\n *\n * 1 tab == 4 spaces!\n */\n\n/* Standard includes. */\n#include <stdlib.h>\n\n/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\nall the API functions to use the MPU wrappers.  That should only be done when\ntask.h is included from an application file. */\n#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"queue.h\"\n#include \"timers.h\"\n\n#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )\n\t#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.\n#endif\n\n/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified\nbecause the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined\nfor the header files above, but not in this file, in order to generate the\ncorrect privileged Vs unprivileged linkage and placement. */\n#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */\n\n\n/* This entire source file will be skipped if the application is not configured\nto include software timer functionality.  This #if is closed at the very bottom\nof this file.  If you want to include software timer functionality then ensure\nconfigUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#if ( configUSE_TIMERS == 1 )\n\n/* Misc definitions. */\n#define tmrNO_DELAY\t\t( TickType_t ) 0U\n\n/* The name assigned to the timer service task.  This can be overridden by\ndefining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */\n#ifndef configTIMER_SERVICE_TASK_NAME\n\t#define configTIMER_SERVICE_TASK_NAME \"Tmr Svc\"\n#endif\n\n/* Bit definitions used in the ucStatus member of a timer structure. */\n#define tmrSTATUS_IS_ACTIVE\t\t\t\t\t( ( uint8_t ) 0x01 )\n#define tmrSTATUS_IS_STATICALLY_ALLOCATED\t( ( uint8_t ) 0x02 )\n#define tmrSTATUS_IS_AUTORELOAD\t\t\t\t( ( uint8_t ) 0x04 )\n\n/* The definition of the timers themselves. */\ntypedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */\n{\n\tconst char\t\t\t\t*pcTimerName;\t\t/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\tListItem_t\t\t\t\txTimerListItem;\t\t/*<< Standard linked list item as used by all kernel features for event management. */\n\tTickType_t\t\t\t\txTimerPeriodInTicks;/*<< How quickly and often the timer expires. */\n\tvoid \t\t\t\t\t*pvTimerID;\t\t\t/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */\n\tTimerCallbackFunction_t\tpxCallbackFunction;\t/*<< The function that will be called when the timer expires. */\n\t#if( configUSE_TRACE_FACILITY == 1 )\n\t\tUBaseType_t\t\t\tuxTimerNumber;\t\t/*<< An ID assigned by trace tools such as FreeRTOS+Trace */\n\t#endif\n\tuint8_t \t\t\t\tucStatus;\t\t\t/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */\n} xTIMER;\n\n/* The old xTIMER name is maintained above then typedefed to the new Timer_t\nname below to enable the use of older kernel aware debuggers. */\ntypedef xTIMER Timer_t;\n\n/* The definition of messages that can be sent and received on the timer queue.\nTwo types of message can be queued - messages that manipulate a software timer,\nand messages that request the execution of a non-timer related callback.  The\ntwo message types are defined in two separate structures, xTimerParametersType\nand xCallbackParametersType respectively. */\ntypedef struct tmrTimerParameters\n{\n\tTickType_t\t\t\txMessageValue;\t\t/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */\n\tTimer_t *\t\t\tpxTimer;\t\t\t/*<< The timer to which the command will be applied. */\n} TimerParameter_t;\n\n\ntypedef struct tmrCallbackParameters\n{\n\tPendedFunction_t\tpxCallbackFunction;\t/* << The callback function to execute. */\n\tvoid *pvParameter1;\t\t\t\t\t\t/* << The value that will be used as the callback functions first parameter. */\n\tuint32_t ulParameter2;\t\t\t\t\t/* << The value that will be used as the callback functions second parameter. */\n} CallbackParameters_t;\n\n/* The structure that contains the two message types, along with an identifier\nthat is used to determine which message type is valid. */\ntypedef struct tmrTimerQueueMessage\n{\n\tBaseType_t\t\t\txMessageID;\t\t\t/*<< The command being sent to the timer service task. */\n\tunion\n\t{\n\t\tTimerParameter_t xTimerParameters;\n\n\t\t/* Don't include xCallbackParameters if it is not going to be used as\n\t\tit makes the structure (and therefore the timer queue) larger. */\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\t\t\tCallbackParameters_t xCallbackParameters;\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\n\t} u;\n} DaemonTaskMessage_t;\n\n/*lint -save -e956 A manual analysis and inspection has been used to determine\nwhich static variables must be declared volatile. */\n\n/* The list in which active timers are stored.  Timers are referenced in expire\ntime order, with the nearest expiry time at the front of the list.  Only the\ntimer service task is allowed to access these lists.\nxActiveTimerList1 and xActiveTimerList2 could be at function scope but that\nbreaks some kernel aware debuggers, and debuggers that reply on removing the\nstatic qualifier. */\nPRIVILEGED_DATA static List_t xActiveTimerList1;\nPRIVILEGED_DATA static List_t xActiveTimerList2;\nPRIVILEGED_DATA static List_t *pxCurrentTimerList;\nPRIVILEGED_DATA static List_t *pxOverflowTimerList;\n\n/* A queue that is used to send commands to the timer service task. */\nPRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;\nPRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;\n\n/*lint -restore */\n\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\t/* If static allocation is supported then the application must provide the\n\tfollowing callback function - which enables the application to optionally\n\tprovide the memory that will be used by the timer task as the task's stack\n\tand TCB. */\n\textern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );\n\n#endif\n\n/*\n * Initialise the infrastructure used by the timer service task if it has not\n * been initialised already.\n */\nstatic void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;\n\n/*\n * The timer service task (daemon).  Timer functionality is controlled by this\n * task.  Other tasks communicate with the timer service task using the\n * xTimerQueue queue.\n */\nstatic portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;\n\n/*\n * Called by the timer service task to interpret and process a command it\n * received on the timer queue.\n */\nstatic void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,\n * depending on if the expire time causes a timer counter overflow.\n */\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;\n\n/*\n * An active timer has reached its expire time.  Reload the timer if it is an\n * auto-reload timer, then call its callback.\n */\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;\n\n/*\n * The tick count has overflowed.  Switch the timer lists after ensuring the\n * current timer list does not still reference some timers.\n */\nstatic void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;\n\n/*\n * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE\n * if a tick count overflow occurred since prvSampleTimeNow() was last called.\n */\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;\n\n/*\n * If the timer list contains any active timers then return the expire time of\n * the timer that will expire first and set *pxListWasEmpty to false.  If the\n * timer list does not contain any timers then return 0 and set *pxListWasEmpty\n * to pdTRUE.\n */\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * If a timer has expired, process it.  Otherwise, block the timer service task\n * until either a timer does expire or a command is received.\n */\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;\n\n/*\n * Called after a Timer_t structure has been allocated either statically or\n * dynamically to fill in the structure's members.\n */\nstatic void prvInitialiseNewTimer(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\tTimer_t *pxNewTimer ) PRIVILEGED_FUNCTION;\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerCreateTimerTask( void )\n{\nBaseType_t xReturn = pdFAIL;\n\n\t/* This function is called when the scheduler is started if\n\tconfigUSE_TIMERS is set to 1.  Check that the infrastructure used by the\n\ttimer service task has been created/initialised.  If timers have already\n\tbeen created then the initialisation will already have been performed. */\n\tprvCheckForValidListAndQueue();\n\n\tif( xTimerQueue != NULL )\n\t{\n\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t{\n\t\t\tStaticTask_t *pxTimerTaskTCBBuffer = NULL;\n\t\t\tStackType_t *pxTimerTaskStackBuffer = NULL;\n\t\t\tuint32_t ulTimerTaskStackSize;\n\n\t\t\tvApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );\n\t\t\txTimerTaskHandle = xTaskCreateStatic(\tprvTimerTask,\n\t\t\t\t\t\t\t\t\t\t\t\t\tconfigTIMER_SERVICE_TASK_NAME,\n\t\t\t\t\t\t\t\t\t\t\t\t\tulTimerTaskStackSize,\n\t\t\t\t\t\t\t\t\t\t\t\t\tNULL,\n\t\t\t\t\t\t\t\t\t\t\t\t\t( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n\t\t\t\t\t\t\t\t\t\t\t\t\tpxTimerTaskStackBuffer,\n\t\t\t\t\t\t\t\t\t\t\t\t\tpxTimerTaskTCBBuffer );\n\n\t\t\tif( xTimerTaskHandle != NULL )\n\t\t\t{\n\t\t\t\txReturn = pdPASS;\n\t\t\t}\n\t\t}\n\t\t#else\n\t\t{\n\t\t\txReturn = xTaskCreate(\tprvTimerTask,\n\t\t\t\t\t\t\t\t\tconfigTIMER_SERVICE_TASK_NAME,\n\t\t\t\t\t\t\t\t\tconfigTIMER_TASK_STACK_DEPTH,\n\t\t\t\t\t\t\t\t\tNULL,\n\t\t\t\t\t\t\t\t\t( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,\n\t\t\t\t\t\t\t\t\t&xTimerTaskHandle );\n\t\t}\n\t\t#endif /* configSUPPORT_STATIC_ALLOCATION */\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\tconfigASSERT( xReturn );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\n\tTimerHandle_t xTimerCreate(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction )\n\t{\n\tTimer_t *pxNewTimer;\n\n\t\tpxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */\n\n\t\tif( pxNewTimer != NULL )\n\t\t{\n\t\t\t/* Status is thus far zero as the timer is not created statically\n\t\t\tand has not been started.  The auto-reload bit may get set in\n\t\t\tprvInitialiseNewTimer. */\n\t\t\tpxNewTimer->ucStatus = 0x00;\n\t\t\tprvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n\t\t}\n\n\t\treturn pxNewTimer;\n\t}\n\n#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\n#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\n\tTimerHandle_t xTimerCreateStatic(\tconst char * const pcTimerName,\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\t\tStaticTimer_t *pxTimerBuffer )\n\t{\n\tTimer_t *pxNewTimer;\n\n\t\t#if( configASSERT_DEFINED == 1 )\n\t\t{\n\t\t\t/* Sanity check that the size of the structure used to declare a\n\t\t\tvariable of type StaticTimer_t equals the size of the real timer\n\t\t\tstructure. */\n\t\t\tvolatile size_t xSize = sizeof( StaticTimer_t );\n\t\t\tconfigASSERT( xSize == sizeof( Timer_t ) );\n\t\t\t( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */\n\t\t}\n\t\t#endif /* configASSERT_DEFINED */\n\n\t\t/* A pointer to a StaticTimer_t structure MUST be provided, use it. */\n\t\tconfigASSERT( pxTimerBuffer );\n\t\tpxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */\n\n\t\tif( pxNewTimer != NULL )\n\t\t{\n\t\t\t/* Timers can be created statically or dynamically so note this\n\t\t\ttimer was created statically in case it is later deleted.  The\n\t\t\tauto-reload bit may get set in prvInitialiseNewTimer(). */\n\t\t\tpxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;\n\n\t\t\tprvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );\n\t\t}\n\n\t\treturn pxNewTimer;\n\t}\n\n#endif /* configSUPPORT_STATIC_ALLOCATION */\n/*-----------------------------------------------------------*/\n\nstatic void prvInitialiseNewTimer(\tconst char * const pcTimerName,\t\t\t/*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n\t\t\t\t\t\t\t\t\tconst TickType_t xTimerPeriodInTicks,\n\t\t\t\t\t\t\t\t\tconst UBaseType_t uxAutoReload,\n\t\t\t\t\t\t\t\t\tvoid * const pvTimerID,\n\t\t\t\t\t\t\t\t\tTimerCallbackFunction_t pxCallbackFunction,\n\t\t\t\t\t\t\t\t\tTimer_t *pxNewTimer )\n{\n\t/* 0 is not a valid value for xTimerPeriodInTicks. */\n\tconfigASSERT( ( xTimerPeriodInTicks > 0 ) );\n\n\tif( pxNewTimer != NULL )\n\t{\n\t\t/* Ensure the infrastructure used by the timer service task has been\n\t\tcreated/initialised. */\n\t\tprvCheckForValidListAndQueue();\n\n\t\t/* Initialise the timer structure members using the function\n\t\tparameters. */\n\t\tpxNewTimer->pcTimerName = pcTimerName;\n\t\tpxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;\n\t\tpxNewTimer->pvTimerID = pvTimerID;\n\t\tpxNewTimer->pxCallbackFunction = pxCallbackFunction;\n\t\tvListInitialiseItem( &( pxNewTimer->xTimerListItem ) );\n\t\tif( uxAutoReload != pdFALSE )\n\t\t{\n\t\t\tpxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t\ttraceTIMER_CREATE( pxNewTimer );\n\t}\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )\n{\nBaseType_t xReturn = pdFAIL;\nDaemonTaskMessage_t xMessage;\n\n\tconfigASSERT( xTimer );\n\n\t/* Send a message to the timer service task to perform a particular action\n\ton a particular timer definition. */\n\tif( xTimerQueue != NULL )\n\t{\n\t\t/* Send a command to the timer service task to start the xTimer timer. */\n\t\txMessage.xMessageID = xCommandID;\n\t\txMessage.u.xTimerParameters.xMessageValue = xOptionalValue;\n\t\txMessage.u.xTimerParameters.pxTimer = xTimer;\n\n\t\tif( xCommandID < tmrFIRST_FROM_ISR_COMMAND )\n\t\t{\n\t\t\tif( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )\n\t\t\t{\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n\t\t}\n\n\t\ttraceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );\n\t}\n\telse\n\t{\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nTaskHandle_t xTimerGetTimerDaemonTaskHandle( void )\n{\n\t/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been\n\tstarted, then xTimerTaskHandle will be NULL. */\n\tconfigASSERT( ( xTimerTaskHandle != NULL ) );\n\treturn xTimerTaskHandle;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTimerGetPeriod( TimerHandle_t xTimer )\n{\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\treturn pxTimer->xTimerPeriodInTicks;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )\n{\nTimer_t * pxTimer =  xTimer;\n\n\tconfigASSERT( xTimer );\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( uxAutoReload != pdFALSE )\n\t\t{\n\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nUBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )\n{\nTimer_t * pxTimer =  xTimer;\nUBaseType_t uxReturn;\n\n\tconfigASSERT( xTimer );\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )\n\t\t{\n\t\t\t/* Not an auto-reload timer. */\n\t\t\tuxReturn = ( UBaseType_t ) pdFALSE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\t/* Is an auto-reload timer. */\n\t\t\tuxReturn = ( UBaseType_t ) pdTRUE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn uxReturn;\n}\n/*-----------------------------------------------------------*/\n\nTickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )\n{\nTimer_t * pxTimer =  xTimer;\nTickType_t xReturn;\n\n\tconfigASSERT( xTimer );\n\txReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );\n\treturn xReturn;\n}\n/*-----------------------------------------------------------*/\n\nconst char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */\n{\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\treturn pxTimer->pcTimerName;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )\n{\nBaseType_t xResult;\nTimer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\n\t/* Remove the timer from the list of active timers.  A check has already\n\tbeen performed to ensure the list is not empty. */\n\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\ttraceTIMER_EXPIRED( pxTimer );\n\n\t/* If the timer is an auto-reload timer then calculate the next\n\texpiry time and re-insert the timer in the list of active timers. */\n\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t{\n\t\t/* The timer is inserted into a list using a time relative to anything\n\t\tother than the current time.  It will therefore be inserted into the\n\t\tcorrect list relative to the time this task thinks it is now. */\n\t\tif( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )\n\t\t{\n\t\t\t/* The timer expired before it was added to the active timer\n\t\t\tlist.  Reload it now.  */\n\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\n\t\t\tconfigASSERT( xResult );\n\t\t\t( void ) xResult;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\telse\n\t{\n\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\tmtCOVERAGE_TEST_MARKER();\n\t}\n\n\t/* Call the timer callback. */\n\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n}\n/*-----------------------------------------------------------*/\n\nstatic portTASK_FUNCTION( prvTimerTask, pvParameters )\n{\nTickType_t xNextExpireTime;\nBaseType_t xListWasEmpty;\n\n\t/* Just to avoid compiler warnings. */\n\t( void ) pvParameters;\n\n\t#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )\n\t{\n\t\textern void vApplicationDaemonTaskStartupHook( void );\n\n\t\t/* Allow the application writer to execute some code in the context of\n\t\tthis task at the point the task starts executing.  This is useful if the\n\t\tapplication includes initialisation code that would benefit from\n\t\texecuting after the scheduler has been started. */\n\t\tvApplicationDaemonTaskStartupHook();\n\t}\n\t#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */\n\n\tfor( ;; )\n\t{\n\t\t/* Query the timers list to see if it contains any timers, and if so,\n\t\tobtain the time at which the next timer will expire. */\n\t\txNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );\n\n\t\t/* If a timer has expired, process it.  Otherwise, block this task\n\t\tuntil either a timer does expire, or a command is received. */\n\t\tprvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );\n\n\t\t/* Empty the command queue. */\n\t\tprvProcessReceivedCommands();\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )\n{\nTickType_t xTimeNow;\nBaseType_t xTimerListsWereSwitched;\n\n\tvTaskSuspendAll();\n\t{\n\t\t/* Obtain the time now to make an assessment as to whether the timer\n\t\thas expired or not.  If obtaining the time causes the lists to switch\n\t\tthen don't process this timer as any timers that remained in the list\n\t\twhen the lists were switched will have been processed within the\n\t\tprvSampleTimeNow() function. */\n\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\t\tif( xTimerListsWereSwitched == pdFALSE )\n\t\t{\n\t\t\t/* The tick count has not overflowed, has the timer expired? */\n\t\t\tif( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )\n\t\t\t{\n\t\t\t\t( void ) xTaskResumeAll();\n\t\t\t\tprvProcessExpiredTimer( xNextExpireTime, xTimeNow );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\t/* The tick count has not overflowed, and the next expire\n\t\t\t\ttime has not been reached yet.  This task should therefore\n\t\t\t\tblock to wait for the next expire time or a command to be\n\t\t\t\treceived - whichever comes first.  The following line cannot\n\t\t\t\tbe reached unless xNextExpireTime > xTimeNow, except in the\n\t\t\t\tcase when the current timer list is empty. */\n\t\t\t\tif( xListWasEmpty != pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* The current timer list is empty - is the overflow list\n\t\t\t\t\talso empty? */\n\t\t\t\t\txListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );\n\t\t\t\t}\n\n\t\t\t\tvQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );\n\n\t\t\t\tif( xTaskResumeAll() == pdFALSE )\n\t\t\t\t{\n\t\t\t\t\t/* Yield to wait for either a command to arrive, or the\n\t\t\t\t\tblock time to expire.  If a command arrived between the\n\t\t\t\t\tcritical section being exited and this yield then the yield\n\t\t\t\t\twill not cause the task to block. */\n\t\t\t\t\tportYIELD_WITHIN_API();\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\t( void ) xTaskResumeAll();\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )\n{\nTickType_t xNextExpireTime;\n\n\t/* Timers are listed in expiry time order, with the head of the list\n\treferencing the task that will expire first.  Obtain the time at which\n\tthe timer with the nearest expiry time will expire.  If there are no\n\tactive timers then just set the next expire time to 0.  That will cause\n\tthis task to unblock when the tick count overflows, at which point the\n\ttimer lists will be switched and the next expiry time can be\n\tre-assessed.  */\n\t*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );\n\tif( *pxListWasEmpty == pdFALSE )\n\t{\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n\t}\n\telse\n\t{\n\t\t/* Ensure the task unblocks when the tick count rolls over. */\n\t\txNextExpireTime = ( TickType_t ) 0U;\n\t}\n\n\treturn xNextExpireTime;\n}\n/*-----------------------------------------------------------*/\n\nstatic TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )\n{\nTickType_t xTimeNow;\nPRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */\n\n\txTimeNow = xTaskGetTickCount();\n\n\tif( xTimeNow < xLastTime )\n\t{\n\t\tprvSwitchTimerLists();\n\t\t*pxTimerListsWereSwitched = pdTRUE;\n\t}\n\telse\n\t{\n\t\t*pxTimerListsWereSwitched = pdFALSE;\n\t}\n\n\txLastTime = xTimeNow;\n\n\treturn xTimeNow;\n}\n/*-----------------------------------------------------------*/\n\nstatic BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )\n{\nBaseType_t xProcessTimerNow = pdFALSE;\n\n\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );\n\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\n\n\tif( xNextExpiryTime <= xTimeNow )\n\t{\n\t\t/* Has the expiry time elapsed between the command to start/reset a\n\t\ttimer was issued, and the time the command was processed? */\n\t\tif( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */\n\t\t{\n\t\t\t/* The time between a command being issued and the command being\n\t\t\tprocessed actually exceeds the timers period.  */\n\t\t\txProcessTimerNow = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tvListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );\n\t\t}\n\t}\n\telse\n\t{\n\t\tif( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )\n\t\t{\n\t\t\t/* If, since the command was issued, the tick count has overflowed\n\t\t\tbut the expiry time has not, then the timer must have already passed\n\t\t\tits expiry time and should be processed immediately. */\n\t\t\txProcessTimerNow = pdTRUE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\n\t\t}\n\t}\n\n\treturn xProcessTimerNow;\n}\n/*-----------------------------------------------------------*/\n\nstatic void\tprvProcessReceivedCommands( void )\n{\nDaemonTaskMessage_t xMessage;\nTimer_t *pxTimer;\nBaseType_t xTimerListsWereSwitched, xResult;\nTickType_t xTimeNow;\n\n\twhile( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */\n\t{\n\t\t#if ( INCLUDE_xTimerPendFunctionCall == 1 )\n\t\t{\n\t\t\t/* Negative commands are pended function calls rather than timer\n\t\t\tcommands. */\n\t\t\tif( xMessage.xMessageID < ( BaseType_t ) 0 )\n\t\t\t{\n\t\t\t\tconst CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );\n\n\t\t\t\t/* The timer uses the xCallbackParameters member to request a\n\t\t\t\tcallback be executed.  Check the callback is not NULL. */\n\t\t\t\tconfigASSERT( pxCallback );\n\n\t\t\t\t/* Call the function. */\n\t\t\t\tpxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\t\t}\n\t\t#endif /* INCLUDE_xTimerPendFunctionCall */\n\n\t\t/* Commands that are positive are timer commands rather than pended\n\t\tfunction calls. */\n\t\tif( xMessage.xMessageID >= ( BaseType_t ) 0 )\n\t\t{\n\t\t\t/* The messages uses the xTimerParameters member to work on a\n\t\t\tsoftware timer. */\n\t\t\tpxTimer = xMessage.u.xTimerParameters.pxTimer;\n\n\t\t\tif( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */\n\t\t\t{\n\t\t\t\t/* The timer is in a list, remove it. */\n\t\t\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t}\n\n\t\t\ttraceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );\n\n\t\t\t/* In this case the xTimerListsWereSwitched parameter is not used, but\n\t\t\tit must be present in the function call.  prvSampleTimeNow() must be\n\t\t\tcalled after the message is received from xTimerQueue so there is no\n\t\t\tpossibility of a higher priority task adding a message to the message\n\t\t\tqueue with a time that is ahead of the timer daemon task (because it\n\t\t\tpre-empted the timer daemon task after the xTimeNow value was set). */\n\t\t\txTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );\n\n\t\t\tswitch( xMessage.xMessageID )\n\t\t\t{\n\t\t\t\tcase tmrCOMMAND_START :\n\t\t\t\tcase tmrCOMMAND_START_FROM_ISR :\n\t\t\t\tcase tmrCOMMAND_RESET :\n\t\t\t\tcase tmrCOMMAND_RESET_FROM_ISR :\n\t\t\t\tcase tmrCOMMAND_START_DONT_TRACE :\n\t\t\t\t\t/* Start or restart a timer. */\n\t\t\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tif( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The timer expired before it was added to the active\n\t\t\t\t\t\ttimer list.  Process it now. */\n\t\t\t\t\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n\t\t\t\t\t\ttraceTIMER_EXPIRED( pxTimer );\n\n\t\t\t\t\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );\n\t\t\t\t\t\t\tconfigASSERT( xResult );\n\t\t\t\t\t\t\t( void ) xResult;\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\telse\n\t\t\t\t\t{\n\t\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t\t}\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_STOP :\n\t\t\t\tcase tmrCOMMAND_STOP_FROM_ISR :\n\t\t\t\t\t/* The timer has already been removed from the active list. */\n\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD :\n\t\t\t\tcase tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :\n\t\t\t\t\tpxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\tpxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;\n\t\t\t\t\tconfigASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );\n\n\t\t\t\t\t/* The new period does not really have a reference, and can\n\t\t\t\t\tbe longer or shorter than the old one.  The command time is\n\t\t\t\t\ttherefore set to the current time, and as the period cannot\n\t\t\t\t\tbe zero the next expiry time can only be in the future,\n\t\t\t\t\tmeaning (unlike for the xTimerStart() case above) there is\n\t\t\t\t\tno fail case that needs to be handled here. */\n\t\t\t\t\t( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );\n\t\t\t\t\tbreak;\n\n\t\t\t\tcase tmrCOMMAND_DELETE :\n\t\t\t\t\t#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\n\t\t\t\t\t{\n\t\t\t\t\t\t/* The timer has already been removed from the active list,\n\t\t\t\t\t\tjust free up the memory if the memory was dynamically\n\t\t\t\t\t\tallocated. */\n\t\t\t\t\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tvPortFree( pxTimer );\n\t\t\t\t\t\t}\n\t\t\t\t\t\telse\n\t\t\t\t\t\t{\n\t\t\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\t\t}\n\t\t\t\t\t}\n\t\t\t\t\t#else\n\t\t\t\t\t{\n\t\t\t\t\t\t/* If dynamic allocation is not enabled, the memory\n\t\t\t\t\t\tcould not have been dynamically allocated. So there is\n\t\t\t\t\t\tno need to free the memory - just mark the timer as\n\t\t\t\t\t\t\"not active\". */\n\t\t\t\t\t\tpxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;\n\t\t\t\t\t}\n\t\t\t\t\t#endif /* configSUPPORT_DYNAMIC_ALLOCATION */\n\t\t\t\t\tbreak;\n\n\t\t\t\tdefault\t:\n\t\t\t\t\t/* Don't expect to get here. */\n\t\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t}\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvSwitchTimerLists( void )\n{\nTickType_t xNextExpireTime, xReloadTime;\nList_t *pxTemp;\nTimer_t *pxTimer;\nBaseType_t xResult;\n\n\t/* The tick count has overflowed.  The timer lists must be switched.\n\tIf there are any timers still referenced from the current timer list\n\tthen they must have expired and should be processed before the lists\n\tare switched. */\n\twhile( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )\n\t{\n\t\txNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );\n\n\t\t/* Remove the timer from the list. */\n\t\tpxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */\n\t\t( void ) uxListRemove( &( pxTimer->xTimerListItem ) );\n\t\ttraceTIMER_EXPIRED( pxTimer );\n\n\t\t/* Execute its callback, then send a command to restart the timer if\n\t\tit is an auto-reload timer.  It cannot be restarted here as the lists\n\t\thave not yet been switched. */\n\t\tpxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );\n\n\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )\n\t\t{\n\t\t\t/* Calculate the reload value, and if the reload value results in\n\t\t\tthe timer going into the same timer list then it has already expired\n\t\t\tand the timer should be re-inserted into the current list so it is\n\t\t\tprocessed again within this loop.  Otherwise a command should be sent\n\t\t\tto restart the timer to ensure it is only inserted into a list after\n\t\t\tthe lists have been swapped. */\n\t\t\txReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );\n\t\t\tif( xReloadTime > xNextExpireTime )\n\t\t\t{\n\t\t\t\tlistSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );\n\t\t\t\tlistSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );\n\t\t\t\tvListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );\n\t\t\t}\n\t\t\telse\n\t\t\t{\n\t\t\t\txResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );\n\t\t\t\tconfigASSERT( xResult );\n\t\t\t\t( void ) xResult;\n\t\t\t}\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\n\tpxTemp = pxCurrentTimerList;\n\tpxCurrentTimerList = pxOverflowTimerList;\n\tpxOverflowTimerList = pxTemp;\n}\n/*-----------------------------------------------------------*/\n\nstatic void prvCheckForValidListAndQueue( void )\n{\n\t/* Check that the list from which active timers are referenced, and the\n\tqueue used to communicate with the timer service, have been\n\tinitialised. */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( xTimerQueue == NULL )\n\t\t{\n\t\t\tvListInitialise( &xActiveTimerList1 );\n\t\t\tvListInitialise( &xActiveTimerList2 );\n\t\t\tpxCurrentTimerList = &xActiveTimerList1;\n\t\t\tpxOverflowTimerList = &xActiveTimerList2;\n\n\t\t\t#if( configSUPPORT_STATIC_ALLOCATION == 1 )\n\t\t\t{\n\t\t\t\t/* The timer queue is allocated statically in case\n\t\t\t\tconfigSUPPORT_DYNAMIC_ALLOCATION is 0. */\n\t\t\t\tstatic StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n\t\t\t\tstatic uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */\n\n\t\t\t\txTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );\n\t\t\t}\n\t\t\t#else\n\t\t\t{\n\t\t\t\txTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );\n\t\t\t}\n\t\t\t#endif\n\n\t\t\t#if ( configQUEUE_REGISTRY_SIZE > 0 )\n\t\t\t{\n\t\t\t\tif( xTimerQueue != NULL )\n\t\t\t\t{\n\t\t\t\t\tvQueueAddToRegistry( xTimerQueue, \"TmrQ\" );\n\t\t\t\t}\n\t\t\t\telse\n\t\t\t\t{\n\t\t\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t\t\t}\n\t\t\t}\n\t\t\t#endif /* configQUEUE_REGISTRY_SIZE */\n\t\t}\n\t\telse\n\t\t{\n\t\t\tmtCOVERAGE_TEST_MARKER();\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\nBaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )\n{\nBaseType_t xReturn;\nTimer_t *pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\n\t/* Is the timer in the list of active timers? */\n\ttaskENTER_CRITICAL();\n\t{\n\t\tif( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )\n\t\t{\n\t\t\txReturn = pdFALSE;\n\t\t}\n\t\telse\n\t\t{\n\t\t\txReturn = pdTRUE;\n\t\t}\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn xReturn;\n} /*lint !e818 Can't be pointer to const due to the typedef. */\n/*-----------------------------------------------------------*/\n\nvoid *pvTimerGetTimerID( const TimerHandle_t xTimer )\n{\nTimer_t * const pxTimer = xTimer;\nvoid *pvReturn;\n\n\tconfigASSERT( xTimer );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpvReturn = pxTimer->pvTimerID;\n\t}\n\ttaskEXIT_CRITICAL();\n\n\treturn pvReturn;\n}\n/*-----------------------------------------------------------*/\n\nvoid vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )\n{\nTimer_t * const pxTimer = xTimer;\n\n\tconfigASSERT( xTimer );\n\n\ttaskENTER_CRITICAL();\n\t{\n\t\tpxTimer->pvTimerID = pvNewID;\n\t}\n\ttaskEXIT_CRITICAL();\n}\n/*-----------------------------------------------------------*/\n\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\n\n\tBaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )\n\t{\n\tDaemonTaskMessage_t xMessage;\n\tBaseType_t xReturn;\n\n\t\t/* Complete the message with the function parameters and post it to the\n\t\tdaemon task. */\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n\t\txReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );\n\n\t\ttracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n#if( INCLUDE_xTimerPendFunctionCall == 1 )\n\n\tBaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )\n\t{\n\tDaemonTaskMessage_t xMessage;\n\tBaseType_t xReturn;\n\n\t\t/* This function can only be called after a timer has been created or\n\t\tafter the scheduler has been started because, until then, the timer\n\t\tqueue does not exist. */\n\t\tconfigASSERT( xTimerQueue );\n\n\t\t/* Complete the message with the function parameters and post it to the\n\t\tdaemon task. */\n\t\txMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;\n\t\txMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;\n\t\txMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;\n\t\txMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;\n\n\t\txReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );\n\n\t\ttracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );\n\n\t\treturn xReturn;\n\t}\n\n#endif /* INCLUDE_xTimerPendFunctionCall */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tUBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )\n\t{\n\t\treturn ( ( Timer_t * ) xTimer )->uxTimerNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n#if ( configUSE_TRACE_FACILITY == 1 )\n\n\tvoid vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )\n\t{\n\t\t( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;\n\t}\n\n#endif /* configUSE_TRACE_FACILITY */\n/*-----------------------------------------------------------*/\n\n/* This entire source file will be skipped if the application is not configured\nto include software timer functionality.  If you want to include software timer\nfunctionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */\n#endif /* configUSE_TIMERS == 1 */\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/REF-STM32F4-fw.ioc",
    "content": "#MicroXplorer Configuration settings - do not modify\nADC1.Channel-3\\#ChannelRegularConversion=ADC_CHANNEL_12\nADC1.Channel-4\\#ChannelRegularConversion=ADC_CHANNEL_13\nADC1.Channel-5\\#ChannelRegularConversion=ADC_CHANNEL_14\nADC1.Channel-6\\#ChannelRegularConversion=ADC_CHANNEL_15\nADC1.Channel-7\\#ChannelRegularConversion=ADC_CHANNEL_TEMPSENSOR\nADC1.Channel-9\\#ChannelRegularConversion=ADC_CHANNEL_VREFINT\nADC1.ContinuousConvMode=ENABLE\nADC1.DMAContinuousRequests=ENABLE\nADC1.IPParameters=Rank-3\\#ChannelRegularConversion,master,Channel-3\\#ChannelRegularConversion,SamplingTime-3\\#ChannelRegularConversion,NbrOfConversionFlag,ScanConvMode,ContinuousConvMode,DMAContinuousRequests,InjNumberOfConversion,Rank-4\\#ChannelRegularConversion,Channel-4\\#ChannelRegularConversion,SamplingTime-4\\#ChannelRegularConversion,Rank-5\\#ChannelRegularConversion,Channel-5\\#ChannelRegularConversion,SamplingTime-5\\#ChannelRegularConversion,Rank-6\\#ChannelRegularConversion,Channel-6\\#ChannelRegularConversion,SamplingTime-6\\#ChannelRegularConversion,NbrOfConversion,Rank-7\\#ChannelRegularConversion,Channel-7\\#ChannelRegularConversion,SamplingTime-7\\#ChannelRegularConversion,Rank-9\\#ChannelRegularConversion,Channel-9\\#ChannelRegularConversion,SamplingTime-9\\#ChannelRegularConversion\nADC1.InjNumberOfConversion=0\nADC1.NbrOfConversion=6\nADC1.NbrOfConversionFlag=1\nADC1.Rank-3\\#ChannelRegularConversion=1\nADC1.Rank-4\\#ChannelRegularConversion=2\nADC1.Rank-5\\#ChannelRegularConversion=3\nADC1.Rank-6\\#ChannelRegularConversion=4\nADC1.Rank-7\\#ChannelRegularConversion=5\nADC1.Rank-9\\#ChannelRegularConversion=6\nADC1.SamplingTime-3\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.SamplingTime-4\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.SamplingTime-5\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.SamplingTime-6\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.SamplingTime-7\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.SamplingTime-9\\#ChannelRegularConversion=ADC_SAMPLETIME_28CYCLES\nADC1.ScanConvMode=ENABLE\nADC1.master=1\nCAN1.AWUM=ENABLE\nCAN1.BS1=CAN_BS1_3TQ\nCAN1.BS2=CAN_BS2_2TQ\nCAN1.CalculateBaudRate=1000000\nCAN1.CalculateTimeBit=999.99\nCAN1.CalculateTimeQuantum=166.66666666666669\nCAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,Prescaler,BS2,AWUM,TXFP\nCAN1.Prescaler=7\nCAN1.TXFP=ENABLE\nCAN2.AWUM=ENABLE\nCAN2.BS1=CAN_BS1_3TQ\nCAN2.BS2=CAN_BS2_2TQ\nCAN2.CalculateBaudRate=1000000\nCAN2.CalculateTimeBit=999.99\nCAN2.CalculateTimeQuantum=166.66666666666669\nCAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,Prescaler,BS2,AWUM\nCAN2.Prescaler=7\nDma.ADC1.2.Direction=DMA_PERIPH_TO_MEMORY\nDma.ADC1.2.FIFOMode=DMA_FIFOMODE_DISABLE\nDma.ADC1.2.Instance=DMA2_Stream0\nDma.ADC1.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD\nDma.ADC1.2.MemInc=DMA_MINC_ENABLE\nDma.ADC1.2.Mode=DMA_CIRCULAR\nDma.ADC1.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD\nDma.ADC1.2.PeriphInc=DMA_PINC_DISABLE\nDma.ADC1.2.Priority=DMA_PRIORITY_LOW\nDma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode\nDma.Request0=UART4_RX\nDma.Request1=UART4_TX\nDma.Request2=ADC1\nDma.Request3=UART5_RX\nDma.Request4=UART5_TX\nDma.RequestsNb=5\nDma.UART4_RX.0.Direction=DMA_PERIPH_TO_MEMORY\nDma.UART4_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE\nDma.UART4_RX.0.Instance=DMA1_Stream2\nDma.UART4_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE\nDma.UART4_RX.0.MemInc=DMA_MINC_ENABLE\nDma.UART4_RX.0.Mode=DMA_CIRCULAR\nDma.UART4_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE\nDma.UART4_RX.0.PeriphInc=DMA_PINC_DISABLE\nDma.UART4_RX.0.Priority=DMA_PRIORITY_LOW\nDma.UART4_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode\nDma.UART4_TX.1.Direction=DMA_MEMORY_TO_PERIPH\nDma.UART4_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE\nDma.UART4_TX.1.Instance=DMA1_Stream4\nDma.UART4_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE\nDma.UART4_TX.1.MemInc=DMA_MINC_ENABLE\nDma.UART4_TX.1.Mode=DMA_NORMAL\nDma.UART4_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE\nDma.UART4_TX.1.PeriphInc=DMA_PINC_DISABLE\nDma.UART4_TX.1.Priority=DMA_PRIORITY_LOW\nDma.UART4_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode\nDma.UART5_RX.3.Direction=DMA_PERIPH_TO_MEMORY\nDma.UART5_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE\nDma.UART5_RX.3.Instance=DMA1_Stream0\nDma.UART5_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE\nDma.UART5_RX.3.MemInc=DMA_MINC_ENABLE\nDma.UART5_RX.3.Mode=DMA_CIRCULAR\nDma.UART5_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE\nDma.UART5_RX.3.PeriphInc=DMA_PINC_DISABLE\nDma.UART5_RX.3.Priority=DMA_PRIORITY_LOW\nDma.UART5_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode\nDma.UART5_TX.4.Direction=DMA_MEMORY_TO_PERIPH\nDma.UART5_TX.4.FIFOMode=DMA_FIFOMODE_DISABLE\nDma.UART5_TX.4.Instance=DMA1_Stream7\nDma.UART5_TX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE\nDma.UART5_TX.4.MemInc=DMA_MINC_ENABLE\nDma.UART5_TX.4.Mode=DMA_NORMAL\nDma.UART5_TX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE\nDma.UART5_TX.4.PeriphInc=DMA_PINC_DISABLE\nDma.UART5_TX.4.Priority=DMA_PRIORITY_LOW\nDma.UART5_TX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode\nFREERTOS.FootprintOK=true\nFREERTOS.IPParameters=Tasks01,configENABLE_FPU,FootprintOK,configUSE_PREEMPTION,configTOTAL_HEAP_SIZE,configUSE_TRACE_FACILITY,configUSE_APPLICATION_TASK_TAG\nFREERTOS.Tasks01=defaultTask,24,500,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL\nFREERTOS.configENABLE_FPU=1\nFREERTOS.configTOTAL_HEAP_SIZE=65536\nFREERTOS.configUSE_APPLICATION_TASK_TAG=0\nFREERTOS.configUSE_PREEMPTION=1\nFREERTOS.configUSE_TRACE_FACILITY=1\nFile.Version=6\nGPIO.groupedBy=Group By Peripherals\nI2C1.I2C_Mode=I2C_Fast\nI2C1.IPParameters=I2C_Mode\nI2C2.I2C_Mode=I2C_Fast\nI2C2.IPParameters=I2C_Mode\nI2C3.I2C_Mode=I2C_Fast\nI2C3.IPParameters=I2C_Mode\nKeepUserPlacement=false\nMcu.Family=STM32F4\nMcu.IP0=ADC1\nMcu.IP1=CAN1\nMcu.IP10=SPI1\nMcu.IP11=SPI3\nMcu.IP12=SYS\nMcu.IP13=TIM2\nMcu.IP14=TIM3\nMcu.IP15=TIM7\nMcu.IP16=TIM9\nMcu.IP17=TIM10\nMcu.IP18=TIM11\nMcu.IP19=TIM12\nMcu.IP2=CAN2\nMcu.IP20=TIM13\nMcu.IP21=TIM14\nMcu.IP22=UART4\nMcu.IP23=UART5\nMcu.IP24=USART1\nMcu.IP25=USB_DEVICE\nMcu.IP26=USB_OTG_FS\nMcu.IP3=DMA\nMcu.IP4=FREERTOS\nMcu.IP5=I2C1\nMcu.IP6=I2C2\nMcu.IP7=I2C3\nMcu.IP8=NVIC\nMcu.IP9=RCC\nMcu.IPNb=27\nMcu.Name=STM32F405RGTx\nMcu.Package=LQFP64\nMcu.Pin0=PC13-ANTI_TAMP\nMcu.Pin1=PH0-OSC_IN\nMcu.Pin10=PA7\nMcu.Pin11=PC4\nMcu.Pin12=PC5\nMcu.Pin13=PB10\nMcu.Pin14=PB11\nMcu.Pin15=PB12\nMcu.Pin16=PB13\nMcu.Pin17=PB14\nMcu.Pin18=PB15\nMcu.Pin19=PC6\nMcu.Pin2=PH1-OSC_OUT\nMcu.Pin20=PC7\nMcu.Pin21=PC8\nMcu.Pin22=PC9\nMcu.Pin23=PA8\nMcu.Pin24=PA9\nMcu.Pin25=PA10\nMcu.Pin26=PA11\nMcu.Pin27=PA12\nMcu.Pin28=PA13\nMcu.Pin29=PA14\nMcu.Pin3=PC2\nMcu.Pin30=PA15\nMcu.Pin31=PC10\nMcu.Pin32=PC11\nMcu.Pin33=PC12\nMcu.Pin34=PD2\nMcu.Pin35=PB3\nMcu.Pin36=PB4\nMcu.Pin37=PB5\nMcu.Pin38=PB6\nMcu.Pin39=PB7\nMcu.Pin4=PC3\nMcu.Pin40=PB8\nMcu.Pin41=PB9\nMcu.Pin42=VP_ADC1_TempSens_Input\nMcu.Pin43=VP_ADC1_Vref_Input\nMcu.Pin44=VP_FREERTOS_VS_CMSIS_V2\nMcu.Pin45=VP_SYS_VS_tim6\nMcu.Pin46=VP_TIM7_VS_ClockSourceINT\nMcu.Pin47=VP_TIM10_VS_ClockSourceINT\nMcu.Pin48=VP_TIM11_VS_ClockSourceINT\nMcu.Pin49=VP_TIM13_VS_ClockSourceINT\nMcu.Pin5=PA0-WKUP\nMcu.Pin50=VP_TIM14_VS_ClockSourceINT\nMcu.Pin51=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS\nMcu.Pin6=PA1\nMcu.Pin7=PA2\nMcu.Pin8=PA3\nMcu.Pin9=PA5\nMcu.PinsNb=52\nMcu.ThirdPartyNb=0\nMcu.UserConstants=\nMcu.UserName=STM32F405RGTx\nMxCube.Version=6.2.1\nMxDb.Version=DB.6.0.21\nNVIC.ADC_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.BusFault_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nNVIC.CAN1_RX0_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN1_RX1_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN1_SCE_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN1_TX_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN2_RX0_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN2_RX1_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN2_SCE_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.CAN2_TX_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.DMA1_Stream0_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:false\\:true\nNVIC.DMA1_Stream2_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:false\\:true\nNVIC.DMA1_Stream4_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:false\\:true\nNVIC.DMA1_Stream7_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:false\\:true\nNVIC.DMA2_Stream0_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:false\\:true\nNVIC.DebugMonitor_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nNVIC.ForceEnableDMAVector=true\nNVIC.HardFault_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nNVIC.MemoryManagement_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nNVIC.NonMaskableInt_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nNVIC.OTG_FS_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:false\\:true\nNVIC.PendSV_IRQn=true\\:15\\:0\\:false\\:false\\:false\\:true\\:false\\:false\nNVIC.PriorityGroup=NVIC_PRIORITYGROUP_4\nNVIC.SPI3_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.SVCall_IRQn=true\\:0\\:0\\:false\\:false\\:false\\:false\\:false\\:false\nNVIC.SavedPendsvIrqHandlerGenerated=true\nNVIC.SavedSvcallIrqHandlerGenerated=true\nNVIC.SavedSystickIrqHandlerGenerated=true\nNVIC.SysTick_IRQn=true\\:15\\:0\\:false\\:false\\:false\\:true\\:false\\:true\nNVIC.TIM1_TRG_COM_TIM11_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM1_UP_TIM10_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM2_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM3_IRQn=true\\:5\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM6_DAC_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:true\nNVIC.TIM7_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM8_TRG_COM_TIM14_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.TIM8_UP_TIM13_IRQn=true\\:5\\:0\\:false\\:false\\:true\\:true\\:true\\:true\nNVIC.TimeBase=TIM6_DAC_IRQn\nNVIC.TimeBaseIP=TIM6\nNVIC.UART4_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.UART5_IRQn=true\\:6\\:0\\:true\\:false\\:true\\:true\\:true\\:true\nNVIC.UsageFault_IRQn=true\\:0\\:0\\:false\\:false\\:true\\:false\\:false\\:false\nPA0-WKUP.Locked=true\nPA0-WKUP.Mode=Asynchronous\nPA0-WKUP.Signal=UART4_TX\nPA1.Locked=true\nPA1.Mode=Asynchronous\nPA1.Signal=UART4_RX\nPA10.Mode=Asynchronous\nPA10.Signal=USART1_RX\nPA11.Mode=Device_Only\nPA11.Signal=USB_OTG_FS_DM\nPA12.Mode=Device_Only\nPA12.Signal=USB_OTG_FS_DP\nPA13.Mode=Serial_Wire\nPA13.Signal=SYS_JTMS-SWDIO\nPA14.Mode=Serial_Wire\nPA14.Signal=SYS_JTCK-SWCLK\nPA15.Signal=S_TIM2_CH1_ETR\nPA2.Signal=S_TIM9_CH1\nPA3.Signal=S_TIM9_CH2\nPA5.Mode=Full_Duplex_Master\nPA5.Signal=SPI1_SCK\nPA7.Mode=Full_Duplex_Master\nPA7.Signal=SPI1_MOSI\nPA8.Mode=I2C\nPA8.Signal=I2C3_SCL\nPA9.Mode=Asynchronous\nPA9.Signal=USART1_TX\nPB10.GPIOParameters=GPIO_Label\nPB10.GPIO_Label=OLED_I2C2_SCL\nPB10.Mode=I2C\nPB10.Signal=I2C2_SCL\nPB11.GPIOParameters=GPIO_Label\nPB11.GPIO_Label=OLED_I2C2_SDA\nPB11.Mode=I2C\nPB11.Signal=I2C2_SDA\nPB12.GPIOParameters=GPIO_PuPd\nPB12.GPIO_PuPd=GPIO_PULLUP\nPB12.Mode=CAN_Activate\nPB12.Signal=CAN2_RX\nPB13.Mode=CAN_Activate\nPB13.Signal=CAN2_TX\nPB14.Signal=S_TIM12_CH1\nPB15.Signal=S_TIM12_CH2\nPB3.Signal=S_TIM2_CH2\nPB4.Mode=Full_Duplex_Master\nPB4.Signal=SPI1_MISO\nPB5.Mode=Full_Duplex_Master\nPB5.Signal=SPI3_MOSI\nPB6.GPIOParameters=GPIO_Label\nPB6.GPIO_Label=IMU_I2C1_SCL\nPB6.Mode=I2C\nPB6.Signal=I2C1_SCL\nPB7.GPIOParameters=GPIO_Label\nPB7.GPIO_Label=IMU_I2C1_SDA\nPB7.Mode=I2C\nPB7.Signal=I2C1_SDA\nPB8.GPIOParameters=GPIO_PuPd\nPB8.GPIO_PuPd=GPIO_PULLUP\nPB8.Mode=CAN_Activate\nPB8.Signal=CAN1_RX\nPB9.Mode=CAN_Activate\nPB9.Signal=CAN1_TX\nPC10.Mode=Full_Duplex_Master\nPC10.Signal=SPI3_SCK\nPC11.Mode=Full_Duplex_Master\nPC11.Signal=SPI3_MISO\nPC12.Mode=Asynchronous\nPC12.Signal=UART5_TX\nPC13-ANTI_TAMP.GPIOParameters=GPIO_PuPd,GPIO_Label\nPC13-ANTI_TAMP.GPIO_Label=KEY\nPC13-ANTI_TAMP.GPIO_PuPd=GPIO_PULLUP\nPC13-ANTI_TAMP.Locked=true\nPC13-ANTI_TAMP.Signal=GPIO_Input\nPC2.Signal=ADCx_IN12\nPC3.Signal=ADCx_IN13\nPC4.Signal=ADCx_IN14\nPC5.Signal=ADCx_IN15\nPC6.Signal=S_TIM3_CH1\nPC7.Signal=S_TIM3_CH2\nPC8.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd,GPIO_Label\nPC8.GPIO_Label=LED\nPC8.GPIO_PuPd=GPIO_NOPULL\nPC8.GPIO_Speed=GPIO_SPEED_FREQ_HIGH\nPC8.Locked=true\nPC8.PinState=GPIO_PIN_SET\nPC8.Signal=GPIO_Output\nPC9.Mode=I2C\nPC9.Signal=I2C3_SDA\nPD2.Mode=Asynchronous\nPD2.Signal=UART5_RX\nPH0-OSC_IN.Mode=HSE-External-Oscillator\nPH0-OSC_IN.Signal=RCC_OSC_IN\nPH1-OSC_OUT.Mode=HSE-External-Oscillator\nPH1-OSC_OUT.Signal=RCC_OSC_OUT\nPinOutPanel.RotationAngle=0\nProjectManager.AskForMigrate=true\nProjectManager.BackupPrevious=false\nProjectManager.CompilerOptimize=6\nProjectManager.ComputerToolchain=false\nProjectManager.CoupleFile=true\nProjectManager.CustomerFirmwarePackage=\nProjectManager.DefaultFWLocation=true\nProjectManager.DeletePrevious=true\nProjectManager.DeviceId=STM32F405RGTx\nProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.26.1\nProjectManager.FreePins=false\nProjectManager.HalAssertFull=false\nProjectManager.HeapSize=0x3C00\nProjectManager.KeepUserCode=true\nProjectManager.LastFirmware=false\nProjectManager.LibraryCopy=1\nProjectManager.MainLocation=Core/Src\nProjectManager.NoMain=false\nProjectManager.PreviousToolchain=SW4STM32\nProjectManager.ProjectBuild=false\nProjectManager.ProjectFileName=REF-STM32F4-fw.ioc\nProjectManager.ProjectName=REF-STM32F4-fw\nProjectManager.RegisterCallBack=\nProjectManager.StackSize=0x800\nProjectManager.TargetToolchain=SW4STM32\nProjectManager.ToolChainLocation=\nProjectManager.UnderRoot=true\nProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-false,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_CAN1_Init-CAN1-false-HAL-true,7-MX_CAN2_Init-CAN2-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,9-MX_I2C3_Init-I2C3-false-HAL-true,10-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,11-MX_SPI1_Init-SPI1-false-HAL-true,12-MX_SPI3_Init-SPI3-false-HAL-true,13-MX_UART4_Init-UART4-false-HAL-true,14-MX_ADC1_Init-ADC1-false-HAL-true,15-MX_UART5_Init-UART5-false-HAL-true,16-MX_TIM2_Init-TIM2-false-HAL-true,17-MX_TIM3_Init-TIM3-false-HAL-true,18-MX_TIM12_Init-TIM12-true-HAL-true,19-MX_TIM9_Init-TIM9-true-HAL-true,20-MX_TIM7_Init-TIM7-true-HAL-true,21-MX_TIM10_Init-TIM10-true-HAL-true,22-MX_TIM11_Init-TIM11-true-HAL-true,23-MX_TIM13_Init-TIM13-true-HAL-true,24-MX_TIM14_Init-TIM14-true-HAL-true\nRCC.48MHZClocksFreq_Value=48000000\nRCC.AHBFreq_Value=168000000\nRCC.APB1CLKDivider=RCC_HCLK_DIV4\nRCC.APB1Freq_Value=42000000\nRCC.APB1TimFreq_Value=84000000\nRCC.APB2CLKDivider=RCC_HCLK_DIV2\nRCC.APB2Freq_Value=84000000\nRCC.APB2TimFreq_Value=168000000\nRCC.CortexFreq_Value=168000000\nRCC.EthernetFreq_Value=168000000\nRCC.FCLKCortexFreq_Value=168000000\nRCC.FamilyName=M\nRCC.HCLKFreq_Value=168000000\nRCC.HSE_VALUE=8000000\nRCC.HSI_VALUE=16000000\nRCC.I2SClocksFreq_Value=192000000\nRCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S\nRCC.LSE_VALUE=32768\nRCC.LSI_VALUE=32000\nRCC.MCO2PinFreq_Value=168000000\nRCC.PLLCLKFreq_Value=168000000\nRCC.PLLM=4\nRCC.PLLN=168\nRCC.PLLQ=7\nRCC.PLLQCLKFreq_Value=48000000\nRCC.RTCFreq_Value=32000\nRCC.RTCHSEDivFreq_Value=4000000\nRCC.SYSCLKFreq_VALUE=168000000\nRCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK\nRCC.VCOI2SOutputFreq_Value=384000000\nRCC.VCOInputFreq_Value=2000000\nRCC.VCOOutputFreq_Value=336000000\nRCC.VcooutputI2S=192000000\nSH.ADCx_IN12.0=ADC1_IN12,IN12\nSH.ADCx_IN12.ConfNb=1\nSH.ADCx_IN13.0=ADC1_IN13,IN13\nSH.ADCx_IN13.ConfNb=1\nSH.ADCx_IN14.0=ADC1_IN14,IN14\nSH.ADCx_IN14.ConfNb=1\nSH.ADCx_IN15.0=ADC1_IN15,IN15\nSH.ADCx_IN15.ConfNb=1\nSH.S_TIM12_CH1.0=TIM12_CH1,PWM Generation1 CH1\nSH.S_TIM12_CH1.ConfNb=1\nSH.S_TIM12_CH2.0=TIM12_CH2,PWM Generation2 CH2\nSH.S_TIM12_CH2.ConfNb=1\nSH.S_TIM2_CH1_ETR.0=TIM2_CH1,Encoder_Interface\nSH.S_TIM2_CH1_ETR.ConfNb=1\nSH.S_TIM2_CH2.0=TIM2_CH2,Encoder_Interface\nSH.S_TIM2_CH2.ConfNb=1\nSH.S_TIM3_CH1.0=TIM3_CH1,Encoder_Interface\nSH.S_TIM3_CH1.ConfNb=1\nSH.S_TIM3_CH2.0=TIM3_CH2,Encoder_Interface\nSH.S_TIM3_CH2.ConfNb=1\nSH.S_TIM9_CH1.0=TIM9_CH1,PWM Generation1 CH1\nSH.S_TIM9_CH1.ConfNb=1\nSH.S_TIM9_CH2.0=TIM9_CH2,PWM Generation2 CH2\nSH.S_TIM9_CH2.ConfNb=1\nSPI1.CalculateBaudRate=42.0 MBits/s\nSPI1.Direction=SPI_DIRECTION_2LINES\nSPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate\nSPI1.Mode=SPI_MODE_MASTER\nSPI1.VirtualType=VM_MASTER\nSPI3.CalculateBaudRate=21.0 MBits/s\nSPI3.Direction=SPI_DIRECTION_2LINES\nSPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate\nSPI3.Mode=SPI_MODE_MASTER\nSPI3.VirtualType=VM_MASTER\nTIM10.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE\nTIM10.ClockDivision=TIM_CLOCKDIVISION_DIV1\nTIM10.IPParameters=Prescaler,Period,AutoReloadPreload,ClockDivision\nTIM10.Period=9999\nTIM10.Prescaler=167\nTIM11.IPParameters=Prescaler,Period\nTIM11.Period=9999\nTIM11.Prescaler=167\nTIM12.Channel-PWM\\ Generation1\\ CH1=TIM_CHANNEL_1\nTIM12.Channel-PWM\\ Generation2\\ CH2=TIM_CHANNEL_2\nTIM12.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Prescaler,Period\nTIM12.Period=999\nTIM12.Prescaler=3\nTIM13.IPParameters=Prescaler,Period\nTIM13.Period=9999\nTIM13.Prescaler=83\nTIM14.IPParameters=Prescaler,Period\nTIM14.Period=9999\nTIM14.Prescaler=83\nTIM2.CounterMode=TIM_COUNTERMODE_UP\nTIM2.EncoderMode=TIM_ENCODERMODE_TI12\nTIM2.IC1Filter=4\nTIM2.IC2Filter=4\nTIM2.IPParameters=EncoderMode,Period,IC1Filter,IC2Filter,CounterMode\nTIM2.Period=65535\nTIM3.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_DISABLE\nTIM3.EncoderMode=TIM_ENCODERMODE_TI12\nTIM3.IC1Filter=4\nTIM3.IC2Filter=4\nTIM3.IPParameters=EncoderMode,IC1Filter,IC2Filter,AutoReloadPreload\nTIM7.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE\nTIM7.IPParameters=AutoReloadPreload,Prescaler,Period\nTIM7.Period=9999\nTIM7.Prescaler=83\nTIM9.Channel-PWM\\ Generation1\\ CH1=TIM_CHANNEL_1\nTIM9.Channel-PWM\\ Generation2\\ CH2=TIM_CHANNEL_2\nTIM9.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Prescaler,Period\nTIM9.Period=999\nTIM9.Prescaler=7\nUART4.IPParameters=VirtualMode\nUART4.VirtualMode=Asynchronous\nUART5.IPParameters=VirtualMode\nUART5.VirtualMode=Asynchronous\nUSART1.IPParameters=VirtualMode\nUSART1.VirtualMode=VM_ASYNC\nUSB_DEVICE.CLASS_NAME_FS=CDC\nUSB_DEVICE.IPParameters=VirtualMode-CDC_FS,VirtualModeFS,CLASS_NAME_FS\nUSB_DEVICE.VirtualMode-CDC_FS=Cdc\nUSB_DEVICE.VirtualModeFS=Cdc_FS\nUSB_OTG_FS.IPParameters=VirtualMode\nUSB_OTG_FS.VirtualMode=Device_Only\nVP_ADC1_TempSens_Input.Mode=IN-TempSens\nVP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input\nVP_ADC1_Vref_Input.Mode=IN-Vrefint\nVP_ADC1_Vref_Input.Signal=ADC1_Vref_Input\nVP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2\nVP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2\nVP_SYS_VS_tim6.Mode=TIM6\nVP_SYS_VS_tim6.Signal=SYS_VS_tim6\nVP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer\nVP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT\nVP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer\nVP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT\nVP_TIM13_VS_ClockSourceINT.Mode=Enable_Timer\nVP_TIM13_VS_ClockSourceINT.Signal=TIM13_VS_ClockSourceINT\nVP_TIM14_VS_ClockSourceINT.Mode=Enable_Timer\nVP_TIM14_VS_ClockSourceINT.Signal=TIM14_VS_ClockSourceINT\nVP_TIM7_VS_ClockSourceINT.Mode=Enable_Timer\nVP_TIM7_VS_ClockSourceINT.Signal=TIM7_VS_ClockSourceINT\nVP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS\nVP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS\nboard=custom\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/ctrl_step/ctrl_step.cpp",
    "content": "#include \"ctrl_step.hpp\"\r\n#include \"communication.hpp\"\r\n\r\n\r\nCtrlStepMotor::CtrlStepMotor(CAN_HandleTypeDef* _hcan, uint8_t _id, bool _inverse,\r\n                             uint8_t _reduction, float _angleLimitMin, float _angleLimitMax) :\r\n    nodeID(_id), hcan(_hcan), inverseDirection(_inverse), reduction(_reduction),\r\n    angleLimitMin(_angleLimitMin), angleLimitMax(_angleLimitMax)\r\n{\r\n    txHeader =\r\n        {\r\n            .StdId = 0,\r\n            .ExtId = 0,\r\n            .IDE = CAN_ID_STD,\r\n            .RTR = CAN_RTR_DATA,\r\n            .DLC = 8,\r\n            .TransmitGlobalTime = DISABLE\r\n        };\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetEnable(bool _enable)\r\n{\r\n    state = _enable ? FINISH : STOP;\r\n\r\n    uint8_t mode = 0x01;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Int to Bytes\r\n    uint32_t val = _enable ? 1 : 0;\r\n    auto* b = (unsigned char*) &val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::DoCalibration()\r\n{\r\n    uint8_t mode = 0x02;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetCurrentSetPoint(float _val)\r\n{\r\n    state = RUNNING;\r\n\r\n    uint8_t mode = 0x03;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetVelocitySetPoint(float _val)\r\n{\r\n    state = RUNNING;\r\n\r\n    uint8_t mode = 0x04;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetPositionSetPoint(float _val)\r\n{\r\n    uint8_t mode = 0x05;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need ACK\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetPositionWithVelocityLimit(float _pos, float _vel)\r\n{\r\n    uint8_t mode = 0x07;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_pos;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    b = (unsigned char*) &_vel;\r\n    for (int i = 4; i < 8; i++)\r\n        canBuf[i] = *(b + i - 4);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetNodeID(uint32_t _id)\r\n{\r\n    uint8_t mode = 0x11;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Int to Bytes\r\n    auto* b = (unsigned char*) &_id;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetCurrentLimit(float _val)\r\n{\r\n    uint8_t mode = 0x12;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetVelocityLimit(float _val)\r\n{\r\n    uint8_t mode = 0x13;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetAcceleration(float _val)\r\n{\r\n    uint8_t mode = 0x14;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 0; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::ApplyPositionAsHome()\r\n{\r\n    uint8_t mode = 0x15;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetEnableOnBoot(bool _enable)\r\n{\r\n    uint8_t mode = 0x16;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    // Int to Bytes\r\n    uint32_t val = _enable ? 1 : 0;\r\n    auto* b = (unsigned char*) &val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetEnableStallProtect(bool _enable)\r\n{\r\n    uint8_t mode = 0x1B;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    uint32_t val = _enable ? 1 : 0;\r\n    auto* b = (unsigned char*) &val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::Reboot()\r\n{\r\n    uint8_t mode = 0x7f;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::EraseConfigs()\r\n{\r\n    uint8_t mode = 0x7e;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetAngle(float _angle)\r\n{\r\n    _angle = inverseDirection ? -_angle : _angle;\r\n    float stepMotorCnt = _angle / 360.0f * (float) reduction;\r\n    SetPositionSetPoint(stepMotorCnt);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetAngleWithVelocityLimit(float _angle, float _vel)\r\n{\r\n    _angle = inverseDirection ? -_angle : _angle;\r\n    float stepMotorCnt = _angle / 360.0f * (float) reduction;\r\n    SetPositionWithVelocityLimit(stepMotorCnt, _vel);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::UpdateAngle()\r\n{\r\n    uint8_t mode = 0x23;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::UpdateAngleCallback(float _pos, bool _isFinished)\r\n{\r\n    state = _isFinished ? FINISH : RUNNING;\r\n\r\n    float tmp = _pos / (float) reduction * 360;\r\n    angle = inverseDirection ? -tmp : tmp;\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetDceKp(int32_t _val)\r\n{\r\n    uint8_t mode = 0x17;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetDceKv(int32_t _val)\r\n{\r\n    uint8_t mode = 0x18;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetDceKi(int32_t _val)\r\n{\r\n    uint8_t mode = 0x19;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid CtrlStepMotor::SetDceKd(int32_t _val)\r\n{\r\n    uint8_t mode = 0x1A;\r\n    txHeader.StdId = nodeID << 7 | mode;\r\n\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n    canBuf[4] = 1; // Need save to EEPROM or not\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/ctrl_step/ctrl_step.hpp",
    "content": "#ifndef DUMMY_CORE_FW_CTRL_STEP_HPP\r\n#define DUMMY_CORE_FW_CTRL_STEP_HPP\r\n\r\n#include \"fibre/protocol.hpp\"\r\n#include \"can.h\"\r\n\r\nclass CtrlStepMotor\r\n{\r\npublic:\r\n    enum State\r\n    {\r\n        RUNNING,\r\n        FINISH,\r\n        STOP\r\n    };\r\n\r\n\r\n    const uint32_t CTRL_CIRCLE_COUNT = 200 * 256;\r\n\r\n    CtrlStepMotor(CAN_HandleTypeDef* _hcan, uint8_t _id, bool _inverse = false, uint8_t _reduction = 1,\r\n                  float _angleLimitMin = -180, float _angleLimitMax = 180);\r\n\r\n    uint8_t nodeID;\r\n    float angle = 0;\r\n    float angleLimitMax;\r\n    float angleLimitMin;\r\n    bool inverseDirection;\r\n    uint8_t reduction;\r\n    State state = STOP;\r\n\r\n    void SetAngle(float _angle);\r\n    void SetAngleWithVelocityLimit(float _angle, float _vel);\r\n    // CAN Command\r\n    void SetEnable(bool _enable);\r\n    void DoCalibration();\r\n    void SetCurrentSetPoint(float _val);\r\n    void SetVelocitySetPoint(float _val);\r\n    void SetPositionSetPoint(float _val);\r\n    void SetPositionWithVelocityLimit(float _pos, float _vel);\r\n    void SetNodeID(uint32_t _id);\r\n    void SetCurrentLimit(float _val);\r\n    void SetVelocityLimit(float _val);\r\n    void SetAcceleration(float _val);\r\n    void SetDceKp(int32_t _val);\r\n    void SetDceKv(int32_t _val);\r\n    void SetDceKi(int32_t _val);\r\n    void SetDceKd(int32_t _val);\r\n    void ApplyPositionAsHome();\r\n    void SetEnableOnBoot(bool _enable);\r\n    void SetEnableStallProtect(bool _enable);\r\n    void Reboot();\r\n    void EraseConfigs();\r\n\r\n    void UpdateAngle();\r\n    void UpdateAngleCallback(float _pos, bool _isFinished);\r\n\r\n\r\n    // Communication protocol definitions\r\n    auto MakeProtocolDefinitions()\r\n    {\r\n        return make_protocol_member_list(\r\n            make_protocol_ro_property(\"angle\", &angle),\r\n            make_protocol_function(\"reboot\", *this, &CtrlStepMotor::Reboot),\r\n            make_protocol_function(\"erase_configs\", *this, &CtrlStepMotor::EraseConfigs),\r\n            make_protocol_function(\"set_enable\", *this, &CtrlStepMotor::SetEnable, \"enable\"),\r\n            make_protocol_function(\"set_position_with_time\", *this,\r\n                                   &CtrlStepMotor::SetPositionWithVelocityLimit, \"pos\", \"time\"),\r\n            make_protocol_function(\"set_position\", *this, &CtrlStepMotor::SetPositionSetPoint, \"pos\"),\r\n            make_protocol_function(\"set_velocity\", *this, &CtrlStepMotor::SetVelocitySetPoint, \"vel\"),\r\n            make_protocol_function(\"set_velocity_limit\", *this, &CtrlStepMotor::SetVelocityLimit, \"vel\"),\r\n            make_protocol_function(\"set_current\", *this, &CtrlStepMotor::SetCurrentSetPoint, \"current\"),\r\n            make_protocol_function(\"set_current_limit\", *this, &CtrlStepMotor::SetCurrentLimit, \"current\"),\r\n            make_protocol_function(\"set_node_id\", *this, &CtrlStepMotor::SetNodeID, \"id\"),\r\n            make_protocol_function(\"set_acceleration\", *this, &CtrlStepMotor::SetAcceleration, \"acc\"),\r\n            make_protocol_function(\"apply_home_offset\", *this, &CtrlStepMotor::ApplyPositionAsHome),\r\n            make_protocol_function(\"do_calibration\", *this, &CtrlStepMotor::DoCalibration),\r\n            make_protocol_function(\"set_enable_on_boot\", *this, &CtrlStepMotor::SetEnableOnBoot, \"enable\"),\r\n            make_protocol_function(\"set_dce_kp\", *this, &CtrlStepMotor::SetDceKp, \"vel\"),\r\n            make_protocol_function(\"set_dce_kv\", *this, &CtrlStepMotor::SetDceKv, \"vel\"),\r\n            make_protocol_function(\"set_dce_ki\", *this, &CtrlStepMotor::SetDceKi, \"vel\"),\r\n            make_protocol_function(\"set_dce_kd\", *this, &CtrlStepMotor::SetDceKd, \"vel\"),\r\n            make_protocol_function(\"set_enable_stall_protect\", *this, &CtrlStepMotor::SetEnableStallProtect,\r\n                                   \"enable\"),\r\n            make_protocol_function(\"update_angle\", *this, &CtrlStepMotor::UpdateAngle)\r\n        );\r\n    }\r\n\r\n\r\nprivate:\r\n    CAN_HandleTypeDef* hcan;\r\n    uint8_t canBuf[8] = {};\r\n    CAN_TxHeaderTypeDef txHeader = {};\r\n};\r\n\r\n#endif //DUMMY_CORE_FW_CTRL_STEP_HPP\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca.cpp",
    "content": "#include \"sca.hpp\"\n\n/*----- NEED TO MODIFY THESE FUNCTIONS TO ADAPT DIFFERENT PLATFORMS  -----*/\n// As well should modify Defines in sca_api.h\n\nuint8_t SCA::Can1SendMsg(uint8_t _id, uint8_t *_msg, uint8_t _len)\n{\n    SCA::txHeader[0].StdId = _id;\n    SCA::txHeader[0].ExtId = _id;\n    SCA::txHeader[0].IDE = 0;\n    SCA::txHeader[0].RTR = 0;\n    SCA::txHeader[0].DLC = _len;\n    for (int i = 0; i < _len; i++)\n        SCA::data[0][i] = _msg[i];\n\n    HAL_StatusTypeDef re;\n    int i = 0xFFF;\n    do\n        re = HAL_CAN_AddTxMessage(&hcan1, &SCA::txHeader[0], SCA::data[0], nullptr);\n    while (re == HAL_ERROR && (i--));\n\n    return 0;\n}\n\nuint8_t SCA::Can2SendMsg(uint8_t _id, uint8_t *_msg, uint8_t _len)\n{\n    SCA::txHeader[1].StdId = _id;\n    SCA::txHeader[1].ExtId = _id;\n    SCA::txHeader[1].IDE = 0;\n    SCA::txHeader[1].RTR = 0;\n    SCA::txHeader[1].DLC = _len;\n    for (int i = 0; i < _len; i++)\n        SCA::data[1][i] = _msg[i];\n\n    HAL_StatusTypeDef re;\n    int i = 0xFFF;\n    do\n        re = HAL_CAN_AddTxMessage(&hcan2, &SCA::txHeader[1], SCA::data[1], nullptr);\n    while (re == HAL_ERROR && (i--));\n\n    return 0;\n}\n\nvoid SCA::OnCanReceiveMsg(CAN_RxHeaderTypeDef *_rxHeader, uint8_t *_data)\n{\n    SCA::RxMsg.DLC = _rxHeader->DLC;\n    SCA::RxMsg.StdId = _rxHeader->StdId;\n    SCA::RxMsg.ExtId = _rxHeader->ExtId;\n    SCA::RxMsg.FMI = _rxHeader->FilterMatchIndex;\n    SCA::RxMsg.IDE = _rxHeader->IDE;\n    SCA::RxMsg.RTR = _rxHeader->RTR;\n    for (int i = 0; i < 8; i++)\n        SCA::RxMsg.Data[i] = _data[i];\n\n    // Should be invoked when got CAN responds.\n    canDispatch(&SCA::RxMsg);\n}\n\n/*------------------------------------------------------------------------------*/\n\n// Static class fields.\nuint8_t SCA::data[2][8];\nCAN_TxHeaderTypeDef SCA::txHeader[2];\nCanRxMsg SCA::RxMsg;\n\nSCA::SCA(CAN_HandleTypeDef *_hcan, uint8_t _id, float _reductionRatio) :\n    hcan(_hcan), id(_id), reductionRatio(_reductionRatio)\n{\n    hcan1.Instance = CAN1;\n    hcan2.Instance = CAN2;\n\n    if (hcan->Instance == CAN1)\n    {\n        canHandler.CanPort = 1;\n        canHandler.Send = SCA::Can1SendMsg;\n    } else if (hcan->Instance == CAN2)\n    {\n        canHandler.CanPort = 2;\n        canHandler.Send = SCA::Can2SendMsg;\n    }\n\n    canHandler.Retry = 2;\n}\n\n\nbool SCA::Init(bool _enableActuator)\n{\n    SetupActuators();\n    scaHandler = getInstance(id);\n\n    if (_enableActuator)\n        return EnableActuator() == SCA_NoError;\n    else\n        return true;\n}\n\nvoid SCA::Homing()\n{\n    if (scaHandler->Power_State == Actr_Disable)\n        return;\n\n    SetMode(SCA_Profile_Position_Mode);\n    SetPosition(0);\n\n    do\n    {\n        GetPosition();\n        HAL_Delay(100);\n    } while ((scaHandler->Position_Real > 0.1f) || (scaHandler->Position_Real < -0.1f));\n}\n\n\nvoid SCA::LookupActuators()\n{\n    lookupActuators(&canHandler);\n}\n\nvoid SCA::SetupActuators()\n{\n    setupActuators(id, &canHandler);\n}\n\nvoid SCA::ResetController()\n{\n    resetController(id);\n}\n\nvoid SCA::RegainAttributes()\n{\n    regainAttrbute(id, Block);\n}\n\nbool SCA::IsOnline()\n{\n    isOnline(id, runCmdBlock);\n    return scaHandler->Online_State == Actr_Enable;\n}\n\nbool SCA::IsEnable()\n{\n    isEnable(id, runCmdBlock);\n    return scaHandler->Power_State == Actr_Enable;\n}\n\nbool SCA::IsUpdate()\n{\n    return isUpdate(id);\n}\n\nbool SCA::EnableActuator()\n{\n    return enableActuator(id) == SCA_NoError;\n}\n\nbool SCA::DisableActuator()\n{\n    return disableActuator(id) == SCA_NoError;\n}\n\nbool SCA::SetMode(uint8_t _actuatorMode)\n{\n    return activateActuatorMode(id, _actuatorMode, Block) == SCA_NoError;\n}\n\nuint8_t SCA::GetMode()\n{\n    getActuatorMode(id, runCmdBlock);\n    return scaHandler->Mode;\n}\n\nuint16_t SCA::GetErrorCode()\n{\n    getErrorCode(id, Block);\n    return scaHandler->SCA_Warn.Error_Code;\n}\n\nbool SCA::ClearError()\n{\n    return clearError(id, runCmdBlock) == SCA_NoError;\n}\n\nbool SCA::SaveAllParams()\n{\n    return saveAllParams(id, Block) == SCA_NoError;\n}\n\nvoid SCA::SetPosition(float _pos)\n{\n    setPositionFast(scaHandler, _pos * reductionRatio);\n}\n\nfloat SCA::GetPosition()\n{\n    getPositionFast(scaHandler, Block);\n    return scaHandler->Position_Real / reductionRatio;\n}\n\nvoid SCA::SetPositionKp(float _kp)\n{\n    setPositionKp(id, _kp, runCmdBlock);\n}\n\nfloat SCA::GetPositionKp()\n{\n    getPositionKp(id, Block);\n    return scaHandler->Position_Filter_P;\n}\n\nvoid SCA::SetPositionKi(float _ki)\n{\n    setPositionKi(id, _ki, runCmdBlock);\n}\n\nfloat SCA::GetPositionKi()\n{\n    getPositionKi(id, Block);\n    return scaHandler->Position_Filter_I;\n}\n\nvoid SCA::SetPositionUmax(float _max)\n{\n    setPositionUmax(id, _max, runCmdBlock);\n}\n\nfloat SCA::GetPositionUmax()\n{\n    getPositionUmax(id, Block);\n    return scaHandler->Position_Filter_Limit_H;\n}\n\nvoid SCA::SetPositionUmin(float _min)\n{\n    setPositionUmax(id, _min, runCmdBlock);\n}\n\nfloat SCA::GetPositionUmin()\n{\n    getPositionUmin(id, Block);\n    return scaHandler->Position_Filter_Limit_L;\n}\n\nvoid SCA::SetPositionOffSet(float _offSet)\n{\n    setPositionOffset(id, _offSet, runCmdBlock);\n}\n\nfloat SCA::GetPositionOffSet()\n{\n    getPositionOffset(id, Block);\n    return scaHandler->Position_Offset;\n}\n\nvoid SCA::SetMaximumPosition(float _maxPos)\n{\n    setMaximumPosition(id, _maxPos, runCmdBlock);\n}\n\nfloat SCA::GetMaximumPosition()\n{\n    getMaximumPosition(id, Block);\n    return scaHandler->Position_Limit_H;\n}\n\nvoid SCA::SetMinimumPosition(float _minPos)\n{\n    setMinimumPosition(id, _minPos, runCmdBlock);\n}\n\nfloat SCA::GetMinimumPosition()\n{\n    getMinimumPosition(id, Block);\n    return scaHandler->Position_Limit_L;\n}\n\nuint8_t SCA::EnablePositionLimit(uint8_t _enable)\n{\n    return enablePositionLimit(id, _enable, runCmdBlock);\n}\n\nuint8_t SCA::IsPositionLimitEnable()\n{\n    return isPositionLimitEnable(id, runCmdBlock);\n}\n\nuint8_t SCA::SetHomingPosition(float _homingPos)\n{\n    return setHomingPosition(id, _homingPos, runCmdBlock);\n}\n\nuint8_t SCA::EnablePositionFilter(uint8_t _enable)\n{\n    return enablePositionFilter(id, _enable, runCmdBlock);\n}\n\nuint8_t SCA::IsPositionFilterEnable()\n{\n    return isPositionFilterEnable(id, runCmdBlock);\n}\n\nvoid SCA::SetPositionCutoffFrequency(float _frequency)\n{\n    setPositionCutoffFrequency(id, _frequency, runCmdBlock);\n}\n\nfloat SCA::GetPositionCutoffFrequency()\n{\n    getPositionCutoffFrequency(id, Block);\n    return scaHandler->Position_Filter_Value;\n}\n\nuint8_t SCA::ClearHomingInfo()\n{\n    return clearHomingInfo(id, runCmdBlock);\n}\n\nuint8_t SCA::SetProfilePositionAcceleration(float _acceleration)\n{\n    return setProfilePositionAcceleration(id, _acceleration, runCmdBlock);\n}\n\nfloat SCA::GetProfilePositionAcceleration()\n{\n    getProfilePositionAcceleration(id, Block);\n    return scaHandler->PP_Max_Acceleration;\n}\n\nuint8_t SCA::SetProfilePositionDeceleration(float _deceleration)\n{\n    return setProfilePositionDeceleration(id, _deceleration, runCmdBlock);\n}\n\nfloat SCA::GetProfilePositionDeceleration()\n{\n    getProfilePositionDeceleration(id, Block);\n    return scaHandler->PP_Max_Deceleration;\n}\n\nuint8_t SCA::SetProfilePositionMaxVelocity(float _maxVelocity)\n{\n    return setProfilePositionMaxVelocity(id, _maxVelocity, runCmdBlock);\n}\n\nfloat SCA::GetProfilePositionMaxVelocity()\n{\n    getProfilePositionMaxVelocity(id, Block);\n    return scaHandler->PP_Max_Velocity;\n}\n\nvoid SCA::SetVelocity(float _vel)\n{\n    setVelocityFast(scaHandler, _vel * reductionRatio);\n}\n\nfloat SCA::GetVelocity()\n{\n    getVelocityFast(scaHandler, Block);\n    return scaHandler->Velocity_Real / reductionRatio;\n}\n\nuint8_t SCA::GetVelocityKp()\n{\n    return getVelocityKp(id, Block);\n}\n\nuint8_t SCA::SetVelocityKp(float _kp)\n{\n    return setVelocityKp(id, _kp, runCmdBlock);\n}\n\nuint8_t SCA::GetVelocityKi()\n{\n    return getVelocityKi(id, Block);\n}\n\nuint8_t SCA::SetVelocityKi(float _ki)\n{\n    return setVelocityKi(id, _ki, runCmdBlock);\n}\n\nuint8_t SCA::GetVelocityUmax()\n{\n    return getVelocityUmax(id, Block);\n}\n\nuint8_t SCA::SetVelocityUmax(float _max)\n{\n    return setVelocityUmax(id, _max, runCmdBlock);\n}\n\nuint8_t SCA::GetVelocityUmin()\n{\n    return getVelocityUmin(id, Block);\n}\n\nuint8_t SCA::SetVelocityUmin(float _min)\n{\n    return setVelocityUmin(id, _min, runCmdBlock);\n}\n\nuint8_t SCA::EnableVelocityFilter(uint8_t _enable)\n{\n    return enableVelocityFilter(id, _enable, runCmdBlock);\n}\n\nuint8_t SCA::IsVelocityFilterEnable()\n{\n    return isVelocityFilterEnable(id, runCmdBlock);\n}\n\nuint8_t SCA::GetVelocityCutoffFrequency()\n{\n    return getVelocityCutoffFrequency(id, Block);\n}\n\nuint8_t SCA::SetVelocityCutoffFrequency(float _frequency)\n{\n    return setVelocityCutoffFrequency(id, _frequency, runCmdBlock);\n}\n\nuint8_t SCA::SetVelocityLimit(float _limit)\n{\n    return setVelocityLimit(id, _limit, runCmdBlock);\n}\n\nuint8_t SCA::GetVelocityLimit()\n{\n    return getVelocityLimit(id, Block);\n}\n\nuint8_t SCA::SetProfileVelocityAcceleration(float _acceleration)\n{\n    return setProfileVelocityAcceleration(id, _acceleration, runCmdBlock);\n}\n\nuint8_t SCA::GetProfileVelocityAcceleration()\n{\n    return getProfileVelocityAcceleration(id, Block);\n}\n\nuint8_t SCA::SetProfileVelocityDeceleration(float _deceleration)\n{\n    return setProfileVelocityDeceleration(id, _deceleration, runCmdBlock);\n}\n\nuint8_t SCA::GetProfileVelocityDeceleration()\n{\n    return getProfileVelocityDeceleration(id, Block);\n}\n\nuint8_t SCA::SetProfileVelocityMaxVelocity(float _maxVelocity)\n{\n    return setProfileVelocityMaxVelocity(id, _maxVelocity, runCmdBlock);\n}\n\nuint8_t SCA::GetProfileVelocityMaxVelocity()\n{\n    return getProfileVelocityMaxVelocity(id, Block);\n}\n\nfloat SCA::GetVelocityRange()\n{\n    return getVelocityRange(id);\n}\n\nuint8_t SCA::SetCurrent(float _current)\n{\n    return setCurrentFast(scaHandler, _current);\n}\n\nuint8_t SCA::GetCurrent()\n{\n    return getCurrentFast(scaHandler, Block);\n}\n\nuint8_t SCA::GetCurrentKp()\n{\n    return getCurrentKp(id, Block);\n}\n\nuint8_t SCA::GetCurrentKi()\n{\n    return getCurrentKi(id, Block);\n}\n\nuint8_t SCA::GetCurrentRange()\n{\n    return getCurrentRange(id, Block);\n}\n\nuint8_t SCA::EnableCurrentFilter(uint8_t _enable)\n{\n    return enableCurrentFilter(id, _enable, runCmdBlock);\n}\n\nuint8_t SCA::IsCurrentFilterEnable()\n{\n    return isCurrentFilterEnable(id, runCmdBlock);\n}\n\nuint8_t SCA::GetCurrentCutoffFrequency()\n{\n    return getCurrentCutoffFrequency(id, Block);\n}\n\nuint8_t SCA::SetCurrentCutoffFrequency(float _frequency)\n{\n    return setCurrentCutoffFrequency(id, _frequency, runCmdBlock);\n}\n\nuint8_t SCA::SetCurrentLimit(float _limit)\n{\n    return setCurrentLimit(id, _limit, runCmdBlock);\n}\n\nuint8_t SCA::GetCurrentLimit()\n{\n    return getCurrentLimit(id, Block);\n}\n\nuint8_t SCA::GetVoltage()\n{\n    return getVoltage(id, Block);\n}\n\nuint8_t SCA::GetLockEnergy()\n{\n    return getLockEnergy(id, Block);\n}\n\nuint8_t SCA::SetLockEnergy(float _energy)\n{\n    return setLockEnergy(id, _energy, runCmdBlock);\n}\n\nuint8_t SCA::GetActuatorSerialNumber()\n{\n    return getActuatorSerialNumber(id, Block);\n}\n\nuint8_t SCA::GetMotorTemperature()\n{\n    return getMotorTemperature(id, Block);\n}\n\nuint8_t SCA::GetInverterTemperature()\n{\n    return getInverterTemperature(id, Block);\n}\n\nuint8_t SCA::GetMotorProtectedTemperature()\n{\n    return getMotorProtectedTemperature(id, Block);\n}\n\nuint8_t SCA::SetMotorProtectedTemperature(float _temp)\n{\n    return setMotorProtectedTemperature(id, _temp, runCmdBlock);\n}\n\nuint8_t SCA::GetMotorRecoveryTemperature()\n{\n    return getMotorRecoveryTemperature(id, Block);\n}\n\nuint8_t SCA::SetMotorRecoveryTemperature(float _temp)\n{\n    return setMotorRecoveryTemperature(id, _temp, runCmdBlock);\n}\n\nuint8_t SCA::GetInverterProtectedTemperature()\n{\n    return getInverterProtectedTemperature(id, Block);\n}\n\nuint8_t SCA::SetInverterProtectedTemperature(float _temp)\n{\n    return setInverterProtectedTemperature(id, _temp, runCmdBlock);\n}\n\nuint8_t SCA::GetInverterRecoveryTemperature()\n{\n    return getInverterRecoveryTemperature(id, Block);\n}\n\nuint8_t SCA::SetInverterRecoveryTemperature(float _temp)\n{\n    return setInverterRecoveryTemperature(id, _temp, runCmdBlock);\n}\n\nuint8_t SCA::SetActuatorID(uint8_t currentID, uint8_t _newId)\n{\n    return setActuatorID(id, _newId, runCmdBlock);\n}\n\nuint8_t SCA::GetActuatorLastState()\n{\n    return getActuatorLastState(id, Block);\n}\n\nuint8_t SCA::RequestCVPValue()\n{\n    return requestCVPValueFast(scaHandler, runCmdBlock);\n}\n\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca.hpp",
    "content": "#ifndef REF_STM32F4_SCA_HPP\n#define REF_STM32F4_SCA_HPP\n\n#include \"sca_api.h\"\n#include \"fibre/protocol.hpp\"\n#include <can.h>\n\nclass SCA\n{\nprivate:\n    uint8_t id;\n    float reductionRatio;\n\n    CAN_Handler_t canHandler;\n    bool runCmdBlock = false;\n    CAN_HandleTypeDef *hcan;\n\npublic:\n    static uint8_t data[2][8];\n    static CAN_TxHeaderTypeDef txHeader[2];\n    static uint8_t Can1SendMsg(uint8_t _id, uint8_t *_msg, uint8_t _len);\n    static uint8_t Can2SendMsg(uint8_t _id, uint8_t *_msg, uint8_t _len);\n    static CanRxMsg RxMsg;\n    static void OnCanReceiveMsg(CAN_RxHeaderTypeDef *_rxHeader, uint8_t *_data);\n\n    SCA(CAN_HandleTypeDef *_hcan, uint8_t _id, float _reductionRatio = 36);\n\n    SCA_Handler_t *scaHandler;\n\n    bool Init(bool _enableActuator = true);\n    void LookupActuators();\n    void SetupActuators();\n\n    /*********************************/\n    void Homing();\n    void ResetController();\n    void RegainAttributes();\n    bool IsOnline();\n    bool IsEnable();\n    bool IsUpdate();\n    bool EnableActuator();\n    bool DisableActuator();\n    bool SetMode(uint8_t _actuatorMode);\n    uint8_t GetMode();\n    uint16_t GetErrorCode();\n    bool ClearError();\n    bool SaveAllParams();\n\n    /***************λ******************/\n    void SetPosition(float _pos);\n    float GetPosition();\n    void SetPositionKp(float _kp);\n    float GetPositionKp();\n    void SetPositionKi(float _ki);\n    float GetPositionKi();\n    void SetPositionUmax(float _max);\n    float GetPositionUmax();\n    void SetPositionUmin(float _min);\n    float GetPositionUmin();\n    void SetPositionOffSet(float _offSet);\n    float GetPositionOffSet();\n    void SetMaximumPosition(float _maxPos);\n    float GetMaximumPosition();\n    void SetMinimumPosition(float _minPos);\n    float GetMinimumPosition();\n    uint8_t EnablePositionLimit(uint8_t _enable);\n    uint8_t IsPositionLimitEnable();\n    uint8_t SetHomingPosition(float _homingPos);\n    uint8_t EnablePositionFilter(uint8_t _enable);\n    uint8_t IsPositionFilterEnable();\n    void SetPositionCutoffFrequency(float _frequency);\n    float GetPositionCutoffFrequency();\n    uint8_t ClearHomingInfo();\n    uint8_t SetProfilePositionAcceleration(float _acceleration);\n    float GetProfilePositionAcceleration();\n    uint8_t SetProfilePositionDeceleration(float _deceleration);\n    float GetProfilePositionDeceleration();\n    uint8_t SetProfilePositionMaxVelocity(float _maxVelocity);\n    float GetProfilePositionMaxVelocity();\n\n    /***************ٶ******************/\n    void SetVelocity(float _vel);\n    float GetVelocity();\n    uint8_t GetVelocityKp();\n    uint8_t SetVelocityKp(float _kp);\n    uint8_t GetVelocityKi();\n    uint8_t SetVelocityKi(float _ki);\n    uint8_t GetVelocityUmax();\n    uint8_t SetVelocityUmax(float _max);\n    uint8_t GetVelocityUmin();\n    uint8_t SetVelocityUmin(float _min);\n    uint8_t EnableVelocityFilter(uint8_t _enable);\n    uint8_t IsVelocityFilterEnable();\n    uint8_t GetVelocityCutoffFrequency();\n    uint8_t SetVelocityCutoffFrequency(float _frequency);\n    uint8_t SetVelocityLimit(float _limit);\n    uint8_t GetVelocityLimit();\n    uint8_t SetProfileVelocityAcceleration(float _acceleration);\n    uint8_t GetProfileVelocityAcceleration();\n    uint8_t SetProfileVelocityDeceleration(float _deceleration);\n    uint8_t GetProfileVelocityDeceleration();\n    uint8_t SetProfileVelocityMaxVelocity(float _maxVelocity);\n    uint8_t GetProfileVelocityMaxVelocity();\n    float GetVelocityRange();\n\n    /*********************************/\n    uint8_t SetCurrent(float _current);\n    uint8_t GetCurrent();\n    uint8_t GetCurrentKp();\n    uint8_t GetCurrentKi();\n    uint8_t GetCurrentRange();\n    uint8_t EnableCurrentFilter(uint8_t _enable);\n    uint8_t IsCurrentFilterEnable();\n    uint8_t GetCurrentCutoffFrequency();\n    uint8_t SetCurrentCutoffFrequency(float _frequency);\n    uint8_t SetCurrentLimit(float _limit);\n    uint8_t GetCurrentLimit();\n\n    /*********************************/\n    uint8_t GetVoltage();\n    uint8_t GetLockEnergy();\n    uint8_t SetLockEnergy(float _energy);\n    uint8_t GetActuatorSerialNumber();\n    uint8_t GetMotorTemperature();\n    uint8_t GetInverterTemperature();\n    uint8_t GetMotorProtectedTemperature();\n    uint8_t SetMotorProtectedTemperature(float _temp);\n    uint8_t GetMotorRecoveryTemperature();\n    uint8_t SetMotorRecoveryTemperature(float _temp);\n    uint8_t GetInverterProtectedTemperature();\n    uint8_t SetInverterProtectedTemperature(float _temp);\n    uint8_t GetInverterRecoveryTemperature();\n    uint8_t SetInverterRecoveryTemperature(float _temp);\n    uint8_t SetActuatorID(uint8_t currEntID, uint8_t _newId);\n    uint8_t GetActuatorLastState();\n    uint8_t RequestCVPValue();\n\n    // Communication protocol definitions\n    auto MakeProtocolDefinitions()\n    {\n        return make_protocol_member_list(\n            make_protocol_function(\"enable\", *this, &SCA::EnableActuator),\n            make_protocol_function(\"disable\", *this, &SCA::DisableActuator),\n            make_protocol_function(\"homing\", *this, &SCA::Homing),\n            make_protocol_function(\"get_error_code\", *this, &SCA::GetErrorCode),\n            make_protocol_function(\"clear_error\", *this, &SCA::ClearError),\n            make_protocol_function(\"is_online\", *this, &SCA::IsOnline),\n            make_protocol_function(\"is_enable\", *this, &SCA::IsEnable),\n            make_protocol_function(\"set_mode\", *this, &SCA::SetMode, \"mode\"),\n            make_protocol_function(\"get_mode\", *this, &SCA::GetMode),\n            make_protocol_function(\"set_position\", *this, &SCA::SetPosition, \"pos\"),\n            make_protocol_function(\"get_position\", *this, &SCA::GetPosition),\n            make_protocol_function(\"set_velocity\", *this, &SCA::SetVelocity, \"vel\"),\n            make_protocol_function(\"get_velocity\", *this, &SCA::GetVelocity),\n            make_protocol_function(\"set_current\", *this, &SCA::SetCurrent, \"current\"),\n            make_protocol_function(\"get_current\", *this, &SCA::GetCurrent)\n        );\n    }\n};\n\n#endif //REF_STM32F4_SCA_HPP\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca_api.c",
    "content": "/**\n  ******************************************************************************\n  * @\t  SCA_API.c\n  * @\t  INNFOS Software Team\n  * @\t  V1.5.3\n  * @\t  2019.09.10\n  * @ժ\tҪ  SCA ƽӿڲ\n  ******************************************************************************/\n/* Update log --------------------------------------------------------------------*/\n//V1.1.0 2019.08.05 APIýӿڸΪIDPC SDKһ£вĶдAPI\n//V1.5.0 2019.08.16 ݽշʽжϽգͨŹܣӦݷ\n//\t\t\t\t\tȡϴιػ״̬APIŻ̡\n//V1.5.1 2019.09.10 ѯ\n//V1.5.3 2019.11.15 Żػ\n\n/* Includes ----------------------------------------------------------------------*/\n#include \"sca_api.h\"\n/* Variable defines --------------------------------------------------------------*/\n\n/* ÿSCAҪһӦϢʵʹж SCA_NUM_USE */\nSCA_Handler_t SCA_Handler_List[SCA_NUM_USE];\n\n/* Funcation declaration ---------------------------------------------------------*/\nextern void warnBitAnaly(SCA_Handler_t* pSCA);\n\n/* Funcation defines -------------------------------------------------------------*/\n\n/***********************************************************/\n\n/**\n  * @\t\tCANϲҴڵSCAӡҵID\n  * @\t\tcanPortҪѯ\n  * @\t\t\n  * @ע\t\tÿִ̨ԼIDʹò֪\n  *\t\t\tӦIDô˺\n  */\nvoid lookupActuators(CAN_Handler_t* canPort)\n{\n    uint16_t ID;\n    uint8_t Found = 0;\n    SCA_Handler_t temp;\n\n    /* бԭʼ */\n    temp = SCA_Handler_List[0];\n\n    /* ʹһбвѯ */\n    SCA_Handler_List[0].Can = canPort;\n\n    for(ID = 1; ID <= 0xFF; ID++)\n    {\n        /* װµID */\n        SCA_Handler_List[0].ID = ID;\n\n        /* յIDID */\n        if(isOnline(ID,Block) == SCA_NoError)\n        {\n            /* ¼ҵĸӡҵID */\n            Found++;\n            SCA_Debug(\"Found ID %d in canPort %d\\r\\n\",ID,canPort->CanPort);\n        }\n    }\n    /* ָĵ */\n    SCA_Handler_List[0] = temp;\n\n    /* ʾϢ */\n    SCA_Debug(\"canPort %d polling done ! Found %d Actuators altogether!\\r\\n\\r\\n\",canPort->CanPort,Found);\n}\n\n/**\n  * @\t\tʼIDCAN˿Ϣ\n  * @\t\tidʼִID\n  *\t\t\tpCanʹõCAN˿ڵַ\n  * @\t\t\n  * @ע\t\tҪSCA_NUM_USE\n  */\nvoid setupActuators(uint8_t id, CAN_Handler_t* pCan)\n{\n    static uint32_t i = 0;\n\n    /* ʹ */\n    if(i >= SCA_NUM_USE)\treturn;\n\n    /* Ϣ */\n    SCA_Handler_List[i].ID = id;\n    SCA_Handler_List[i].Can = pCan;\n\n    /* б */\n    i++;\n}\n\n/**\n  * @\t\tλSCAµ\n  * @\t\tid0ʾȫλΪ0ʱλָIDĿ\n  * @\t\t\n  * @ע\t\tֺƻ״̬SCAȽ\n  *\t\t\tSCAϵ磬ָƵ״̬Ȼִд˺\n  *\t\t\t,ִп\n  */\nvoid resetController(uint8_t id)\n{\n    uint8_t i,id_temp;\n    CAN_Handler_t* pCan_temp = NULL;\n\n    if(id == 0)\n    {\n        /* Ϣ */\n        for(i = 0; i < SCA_NUM_USE; i++)\n        {\n            /* IDCAN˿ڵַ */\n            id_temp = SCA_Handler_List[i].ID;\n            pCan_temp = SCA_Handler_List[i].Can;\n\n            /* ṹ */\n            memset(&SCA_Handler_List[i], 0, sizeof(SCA_Handler_List[i]));\n\n            /* ָIDCAN˿ڵַ */\n            SCA_Handler_List[i].ID = id_temp;\n            SCA_Handler_List[i].Can = pCan_temp;\n        }\n    }else\n    {\n        /* ȡIDϢ */\n        SCA_Handler_t* pSCA = getInstance(id);\n        if(pSCA == NULL)\treturn;\n\n        /* CAN˿ڵַ */\n        pCan_temp = pSCA->Can;\n\n        /* ṹ */\n        memset(pSCA, 0, sizeof(SCA_Handler_List[0]));\n\n        /* ָIDCAN˿ڵַ */\n        pSCA->ID = id;\n        pSCA->Can = pCan_temp;\n    }\n}\n\n/**\n  * @\t\tȡָIDSCAϢ\n  * @\t\tid ҪȡϢִID\n  * @\t\tNULLδҵIDϢ\n  *\t\t\tҵϢ\n  */\nSCA_Handler_t* getInstance(uint8_t id)\n{\n    uint8_t i;\n\n    for(i = 0; i < SCA_NUM_USE; i++)\n        if(SCA_Handler_List[i].ID == id)\n            return &SCA_Handler_List[i];\n\n    return NULL;\n}\n\n/**\n  * @\t\tִߣ״̬\n  * @\t\tid Ҫִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorִ\n  *\t\t\tSCA_OverTimeִ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t isOnline(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = getInstance(id);\n\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬ */\n    pSCA->Online_State = Actr_Disable;\n\n    /* öȡSCAͨţӦSCA */\n    Error = SCA_Read(pSCA, R1_Heartbeat);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ʽͨ */\n    while((pSCA->Online_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִʹ״̬\n  * @\t\tid Ҫִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tActr_Enableִʹ\n  *\t\t\tActr_Disableִδʹ\n  *\n  */\nuint8_t isEnable(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* նȡ־λ */\n    pSCA->paraCache.R_Power_State = Actr_Disable;\n\n    /* öȡSCAͨţӦSCA */\n    Error = SCA_Read(pSCA, R1_PowerState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ʽͨ */\n    while((pSCA->paraCache.R_Power_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִIJ״̬\n  * @\t\tid Ҫִid\n  * @\t\tActr_Enableв\n  *\t\t\tActr_Disableûв\n  */\nuint8_t isUpdate(uint8_t id)\n{\n    uint8_t State;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    State = pSCA->Update_State;\n    pSCA->Update_State = Actr_Disable;\n\n    return State;\n}\n\n/**\n  * @\t\tʹִʽ\n  * @\t\t\n  * @\t\t\n  */\nvoid enableAllActuators()\n{\n    uint8_t i;\n\n    for(i = 0; i < SCA_NUM_USE; i++)\n        enableActuator(SCA_Handler_List[i].ID);\n}\n\n/**\n  * @\t\tʧִʽ\n  * @\t\t\n  * @\t\t\n  */\nvoid disableAllActuators()\n{\n    uint8_t i;\n\n    for(i = 0; i < SCA_NUM_USE; i++)\n        disableActuator(SCA_Handler_List[i].ID);\n}\n\n/**\n  * @\t\tִʹ,ʽ\n  * @\t\tidҪʹִܵID\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t enableActuator(uint8_t id)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ѯһεǰʹ״̬ */\n    Error = isEnable(id, Block);\n    if(Error)\treturn Error;\n\n    /* ǰѾĿ״ֱ̬ӷسɹ */\n    if(pSCA->Power_State == Actr_Enable)\tgoto PowerOn;\n\n    /* Ŀд뻺 */\n    pSCA->paraCache.Power_State = Actr_Enable;\n\n    /* ִп */\n    Error = SCA_Write_1(pSCA, W1_PowerState, Actr_Enable);\n    if(Error)\treturn Error;\n\n    /* ȴɹ¾Ϣ */\n    while((pSCA->Power_State != Actr_Enable) && (waitime++ < CanPowertime));\n    if(waitime >= CanPowertime)\treturn SCA_OperationFailed;\n\n    PowerOn:\n    /* ״̬ */\n    pSCA->Online_State = Actr_Enable;\n\n    /* 豸кţID */\n    getActuatorSerialNumber(id,Block);\n\n    /* һϴιػ쳣״̬ */\n    getActuatorLastState(id,Block);\n    if(pSCA->Last_State == 0)\t\t//ʾϴιػ״̬쳣\n        SCA_Debug(\"ID:%d Last_State Error\\r\\n\",pSCA->ID);\n\n    /*  ̵ִֵڶдʱʹã\n        ͬͺŵSCAֵͬҲֶµϢ\n        òֵDZȡġ*/\n    getCurrentRange(id,Block);\n    if(pSCA->Current_Max == 0)\t//δȡֵ޷дֵ\n        SCA_Debug(\"ID:%d Current_Max Error\\r\\n\",pSCA->ID);\n\n    /* һвУΪ̿ʱ÷ */\n    regainAttrbute(id,Unblock);\n\n    return Error;\n}\n\n/**\n  * @\t\tִʧ,\n  * @\t\tidҪʧִܵID\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t disableActuator(uint8_t id)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ѯһεǰʹ״̬ */\n    Error = isEnable(id, Block);\n    if(Error)\treturn Error;\n\n    /* ǰѾĿ״ֱ̬ӷسɹ */\n    if(pSCA->Power_State == Actr_Disable)\treturn SCA_NoError;\n\n    /* Ŀд뻺 */\n    pSCA->paraCache.Power_State = Actr_Disable;\n\n    /* ִйػ */\n    Error = SCA_Write_1(pSCA, W1_PowerState, Actr_Disable);\n    if(Error)\treturn Error;\n\n    /* ȴػɹ */\n    while((pSCA->Power_State != Actr_Disable) && (waitime++ < CanPowertime));\n    if(waitime >= CanPowertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִлģʽ\n  * @\t\tidҪִid\n  *\t\t\tmodeģʽ SCA_Protocol.h\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t activateActuatorMode(uint8_t id, uint8_t ActuatorMode, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ǰѾĿ״ֱ̬ӷسɹ */\n    if(pSCA->Mode == ActuatorMode)\treturn SCA_NoError;\n\n    /* Ŀд뻺 */\n    pSCA->paraCache.Mode = ActuatorMode;\n\n    /* ִģʽл */\n    Error = SCA_Write_1(pSCA, W1_Mode, ActuatorMode);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Mode != ActuatorMode) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִȡǰģʽ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getActuatorMode(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* նȡȴ־λ */\n    pSCA->paraCache.R_Mode = Actr_Disable;\n\n    /* װȡֱֵӱ浽 */\n    Error = SCA_Read(pSCA, R1_Mode);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Mode != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִȡϢ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getErrorCode(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* նȡȴ־λ */\n    pSCA->paraCache.R_Error_Code = Actr_Disable;\n\n    /* ִжȡϢ */\n    Error = SCA_Read(pSCA, R2_Error);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Error_Code != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִϢ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t clearError(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ǰ޴[ */\n    if(pSCA->SCA_Warn.Error_Code == 0)\treturn SCA_NoError;\n\n    /* ִМ[ */\n    Error = SCA_Write_4(pSCA, W4_ClearError);\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->SCA_Warn.Error_Code != 0) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִȡǰв\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\t\n  */\nvoid regainAttrbute(uint8_t id,uint8_t isBlock)\n{\n    getErrorCode(id,isBlock);\n    requestCVPValue(id,isBlock);\n    getActuatorMode(id,isBlock);\n    getPositionKp(id,isBlock);\n    getPositionKi(id,isBlock);\n    getPositionUmax(id,isBlock);\n    getPositionUmin(id,isBlock);\n    getPositionOffset(id,isBlock);\n    getMaximumPosition(id,isBlock);\n    getMinimumPosition(id,isBlock);\n    isPositionLimitEnable(id,isBlock);\n    isPositionFilterEnable(id,isBlock);\n    getPositionCutoffFrequency(id,isBlock);\n    getProfilePositionAcceleration(id,isBlock);\n    getProfilePositionDeceleration(id,isBlock);\n    getProfilePositionMaxVelocity(id,isBlock);\n    getVelocityKp(id,isBlock);\n    getVelocityKi(id,isBlock);\n    getVelocityUmax(id,isBlock);\n    getVelocityUmin(id,isBlock);\n    isVelocityFilterEnable(id,isBlock);\n    getVelocityCutoffFrequency(id,isBlock);\n    getVelocityLimit(id,isBlock);\n    getProfileVelocityAcceleration(id,isBlock);\n    getProfileVelocityDeceleration(id,isBlock);\n    getProfileVelocityMaxVelocity(id,isBlock);\n    getCurrentKp(id,isBlock);\n    getCurrentKi(id,isBlock);\n    isCurrentFilterEnable(id,isBlock);\n    getCurrentCutoffFrequency(id,isBlock);\n    getCurrentLimit(id,isBlock);\n    getVoltage(id,isBlock);\n    getLockEnergy(id,isBlock);\n    getMotorTemperature(id,isBlock);\n    getInverterTemperature(id,isBlock);\n    getMotorProtectedTemperature(id,isBlock);\n    getMotorRecoveryTemperature(id,isBlock);\n    getInverterProtectedTemperature(id,isBlock);\n    getInverterRecoveryTemperature(id,isBlock);\n}\n/**\n  * @\t\tִ浱ǰв\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t saveAllParams(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* մ洢״̬λ */\n    pSCA->Save_State = Actr_Disable;\n\n    Error = SCA_Write_4(pSCA, W4_Save);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִгɹ */\n    while((pSCA->Save_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanPowertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n\n/****************************λ*******************************/\n\n/**\n  * @\t\tִõǰλֵ\n  * @\t\tidҪִid\n  *\t\t\tposĿλֵʵֵΧ -127.0R ~ +127.0R\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPosition(uint8_t id, float pos)\n{\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    return SCA_Write_3(pSCA, W3_Position, pos);\n}\n\n/**\n  * @\t\tִõǰλֵ\n  * @\t\tpSCAҪִַָ\n  *\t\t\tposĿλֵʵֵΧ -127.0R ~ +127.0R\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionFast(SCA_Handler_t* pSCA, float pos)\n{\n    return SCA_Write_3(pSCA, W3_Position, pos);\n}\n\n/**\n  * @\t\tִȡǰλֵ,\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPosition(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Position);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִгɹ */\n    while((pSCA->paraCache.R_Position_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanPowertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִȡǰλֵ,У\n  * @\t\tpSCAҪִַָ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionFast(SCA_Handler_t* pSCA, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Position);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִгɹ */\n    while((pSCA->paraCache.R_Position_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanPowertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλû Kpֵ\n  * @\t\tidҪִid\n  *\t\t\tKpĿλû Kpֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionKp(uint8_t id,float Kp, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_P = Kp;\n\n    Error = SCA_Write_3(pSCA, W3_PositionFilterP, Kp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_P != Kp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλû Kpֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionKp(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_P = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionFilterP);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_P != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλû Kiֵ\n  * @\t\tidҪִid\n  *\t\t\tKiĿλû Kiֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionKi(uint8_t id,float Ki, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_I = Ki;\n\n    Error = SCA_Write_3(pSCA, W3_PositionFilterI, Ki);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_I != Ki) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλû Kiֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionKi(uint8_t id, uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_I = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionFilterI);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_I != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλûֵ\n  * @\t\tidҪִid\n  *\t\t\tmaxĿλûֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionUmax(uint8_t id,float max,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_Limit_H = max;\n\n    Error = SCA_Write_3(pSCA, W3_PositionFilterLimitH, max);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_Limit_H != max) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλûֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionUmax(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_Limit_H = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionFilterLimitH);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_Limit_H != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλûֵ\n  * @\t\tidҪִid\n  *\t\t\tminĿλûֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionUmin(uint8_t id,float min,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_Limit_L = min;\n\n    Error = SCA_Write_3(pSCA, W3_PositionFilterLimitL, min);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_Limit_L != min) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλûֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionUmin(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_Limit_L = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionFilterLimitL);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_Limit_L != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλƫֵ\n  * @\t\tidҪִid\n  *\t\t\toffsetĿλƫֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionOffset(uint8_t id, float offset,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Offset = offset;\n\n    Error = SCA_Write_3(pSCA, W3_PositionOffset, offset);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Offset != offset) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλƫֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionOffset(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Offset = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionOffset);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Offset != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλֵ\n  * @\t\tidҪִid\n  *\t\t\tmaxPosĿλֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setMaximumPosition(uint8_t id,float maxPos,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Limit_H = maxPos;\n\n    Error = SCA_Write_3(pSCA, W3_PositionLimitH, maxPos);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Limit_H != maxPos) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getMaximumPosition(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Limit_H = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionLimitH);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Limit_H != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλСֵ\n  * @\t\tidҪִid\n  *\t\t\tminPosĿλСֵʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setMinimumPosition(uint8_t id,float minPos,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Limit_L = minPos;\n\n    Error = SCA_Write_3(pSCA, W3_PositionLimitL, minPos);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Limit_L != minPos) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλСֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getMinimumPosition(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Limit_L = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PositionLimitL);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Limit_L != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tʹܻʧִλλ\n  * @\t\tidҪִid\n  *\t\t\tenableʹ״̬Actr_EnableʹܣActr_Disableʧ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t enablePositionLimit(uint8_t id, uint8_t enable,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Limit_State = enable;\n\n    Error = SCA_Write_1(pSCA, W1_PositionLimitState, enable);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Limit_State != enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλλʹ״̬\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t isPositionLimitEnable(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Limit_State = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R1_PositionLimitState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Limit_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλã¼λ\n  * @\t\tidҪִid\n  *\t\t\thomingPosλãʵֵλ R\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setHomingPosition(uint8_t id,float homingPos,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Homing_Value = homingPos;\n\n    Error = SCA_Write_3(pSCA, W3_HomingValue, homingPos);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Homing_Value != homingPos) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tʹִλû˲\n  * @\t\tidҪִid\n  *\t\t\tenableʹ״̬Actr_EnableʹܣActr_Disableʧ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t enablePositionFilter(uint8_t id,uint8_t enable,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_State = enable;\n\n    Error = SCA_Write_1(pSCA, W1_PositionFilterState, enable);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_State != enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλû˲ʹ״̬\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t isPositionFilterEnable(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_State = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R1_PositionFilterState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλû˲\n  * @\t\tidҪִid\n  *\t\t\tfrequency˲ʵֵλ hz\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setPositionCutoffFrequency(uint8_t id, float frequency,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Position_Filter_Value = frequency;\n\n    Error = SCA_Write_2(pSCA, W2_PositionFilterValue, frequency);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Position_Filter_Value != frequency) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλû˲\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getPositionCutoffFrequency(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Position_Filter_Value = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_PositionFilterValue);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Position_Filter_Value != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\thomingϢҼ޺0λ\n  * @\t\tidִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t clearHomingInfo(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.W_ClearHome = Actr_Disable;\n\n    Error = SCA_Write_4(pSCA, W4_ClearHome);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.W_ClearHome != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλûٶ\n  * @\t\tidҪִid\n  *\t\t\taccelerationٶȣʵֵλ RPM/S^2\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfilePositionAcceleration(uint8_t id, float acceleration,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PP_Max_Acceleration = acceleration;\n\n    /*  μٶȴֵʵֵIQ20дӿ\n        IQ24ʽģҪIQ4ı⣬ֵ\n        λRPM轫ֵ60RPMλ\n        ֵ = 2^4 * 60 = 960\n    */\n    acceleration /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PPMaxAcceleration, acceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PP_Max_Acceleration != acceleration) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλûٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfilePositionAcceleration(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PP_Max_Acceleration = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PPMaxAcceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PP_Max_Acceleration != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλûٶ\n  * @\t\tidҪִid\n  *\t\t\tdecelerationٶȣʵֵλ RPM/S^2\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfilePositionDeceleration(uint8_t id, float deceleration,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PP_Max_Deceleration = deceleration;\n\n    deceleration /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PPMaxDeceleration, deceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PP_Max_Deceleration != deceleration) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλûٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfilePositionDeceleration(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PP_Max_Deceleration = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PPMaxDeceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PP_Max_Deceleration != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִλûٶ\n  * @\t\tidҪִid\n  *\t\t\tmaxVelocityٶȣʵֵλ RPM\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfilePositionMaxVelocity(uint8_t id, float maxVelocity,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PP_Max_Velocity = maxVelocity;\n\n    maxVelocity /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PPMaxVelocity, maxVelocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PP_Max_Velocity != maxVelocity) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִλûٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfilePositionMaxVelocity(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PP_Max_Velocity = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PPMaxVelocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PP_Max_Velocity != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n\n/****************************ٶ*******************************/\n\n/**\n  * @\t\tִǰٶֵ\n  * @\t\tidҪִid\n  *\t\t\tvelĿٶȣʵֵλ RPM\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocity(uint8_t id,float vel)\n{\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    return SCA_Write_3(pSCA, W3_Velocity, vel);\n}\n\n/**\n  * @\t\tִǰٶֵ,\n  * @\t\tpSCAҪִַָ\n  *\t\t\tvelĿٶȣʵֵλ RPM\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityFast(SCA_Handler_t* pSCA,float vel)\n{\n    return SCA_Write_3(pSCA, W3_Velocity, vel);\n}\n\n\n/**\n  * @\t\tȡִǰٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocity(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Velocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִǰٶȣ,\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityFast(SCA_Handler_t* pSCA,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Velocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityKp(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_P = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_VelocityFilterP);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_P != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻ\n  * @\t\tidҪִid\n  *\t\t\tKpٶȻʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityKp(uint8_t id,float Kp,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_P = Kp;\n\n    Error = SCA_Write_3(pSCA, W3_VelocityFilterP, Kp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_P != Kp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ֣\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityKi(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_I = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_VelocityFilterI);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_I != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻ\n  * @\t\tidҪִid\n  *\t\t\tKiٶȻ֣ʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityKi(uint8_t id, float Ki,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_I = Ki;\n\n    Error = SCA_Write_3(pSCA, W3_VelocityFilterI, Ki);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_I != Ki) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ޷\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityUmax(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_Limit_H = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_VelocityFilterLimitH);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_Limit_H != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻ޷\n  * @\t\tidҪִid\n  *\t\t\tmax޷ʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityUmax(uint8_t id, float max,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_Limit_H = max;\n\n    Error = SCA_Write_3(pSCA, W3_VelocityFilterLimitH, max);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_Limit_H != max) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻС޷\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityUmin(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_Limit_L = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_VelocityFilterLimitL);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_Limit_L != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻС޷\n  * @\t\tidҪִid\n  *\t\t\tminС޷ʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityUmin(uint8_t id, float min,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_Limit_L = min;\n\n    Error = SCA_Write_3(pSCA, W3_VelocityFilterLimitL, min);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_Limit_L != min) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻٶ\n  * @\t\tidҪִid\n  * @\t\tٶȻٶ̣ʵֵ\n  */\nfloat getVelocityRange(uint8_t id)\n{\n    return Velocity_Max;\n}\n\n/**\n  * @\t\tʹִٶȻ˲\n  * @\t\tidҪִid\n  *\t\t\tenableʹ״̬Actr_EnableʹܣActr_Disableʧ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t enableVelocityFilter(uint8_t id,uint8_t enable,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_State = enable;\n\n    Error = SCA_Write_1(pSCA, W1_VelocityFilterState, enable);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_State != enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ˲ʹ״̬\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t isVelocityFilterEnable(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_State = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R1_VelocityFilterState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ˲\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityCutoffFrequency(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Filter_Value = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_VelocityFilterValue);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Filter_Value != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻ˲\n  * @\t\tidҪִid\n  *\t\t\tfrequency˲ʵֵλ hz\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityCutoffFrequency(uint8_t id, float frequency,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Filter_Value = frequency;\n\n    Error = SCA_Write_2(pSCA, W2_VelocityFilterValue, frequency);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Filter_Value != frequency) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻ޷\n  * @\t\tidҪִid\n  *\t\t\tlimit޷\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setVelocityLimit(uint8_t id,float limit,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Velocity_Limit = limit;\n\n    Error = SCA_Write_3(pSCA, W3_VelocityLimit, limit);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Velocity_Limit != limit) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻ޷\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVelocityLimit(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Velocity_Limit = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_VelocityLimit);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Velocity_Limit != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻٶ\n  * @\t\tidҪִid\n  *\t\t\taccelerationٶȣʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfileVelocityAcceleration(uint8_t id,float acceleration,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PV_Max_Acceleration = acceleration;\n\n    acceleration /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PVMaxAcceleration, acceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PV_Max_Acceleration != acceleration) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfileVelocityAcceleration(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PV_Max_Acceleration = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PVMaxAcceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PV_Max_Acceleration != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻٶ\n  * @\t\tidҪִid\n  *\t\t\tdecelerationٶȣʵֵ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfileVelocityDeceleration(uint8_t id,float deceleration,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PV_Max_Deceleration = deceleration;\n\n    deceleration /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PVMaxDeceleration, deceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PV_Max_Deceleration != deceleration) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfileVelocityDeceleration(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PV_Max_Deceleration = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PVMaxDeceleration);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PV_Max_Deceleration != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִٶȻٶ\n  * @\t\tidҪִid\n  *\t\t\tmaxVelocityٶȣʵֵλ RPM\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setProfileVelocityMaxVelocity(uint8_t id, float maxVelocity,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.PV_Max_Velocity = maxVelocity;\n\n    maxVelocity /= Profile_Scal;\n\n    Error = SCA_Write_3(pSCA, W3_PVMaxVelocity, maxVelocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->PV_Max_Velocity != maxVelocity) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִٶȻٶȣ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getProfileVelocityMaxVelocity(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_PV_Max_Velocity = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_PVMaxVelocity);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_PV_Max_Velocity != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n\n/***********************************************************/\n\n/**\n  * @\t\tִǰֵ\n  * @\t\tidҪִid\n  *\t\t\tcurrentǰֵʵֵλ A\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setCurrent(uint8_t id,float current)\n{\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    return SCA_Write_3(pSCA, W3_Current, current);\n}\n\n/**\n  * @\t\tִǰֵ\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcurrentǰֵʵֵλ A\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setCurrentFast(SCA_Handler_t* pSCA,float current)\n{\n    return SCA_Write_3(pSCA, W3_Current, current);\n}\n\n/**\n  * @\t\tȡִǰֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrent(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Current);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִǰֵ,\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentFast(SCA_Handler_t* pSCA,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Real = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_Current);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Real != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentKp(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Filter_P = Actr_Disable;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    Error = SCA_Read(pSCA, R3_CurrentFilterP);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Filter_P != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִ֣\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentKi(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Filter_I = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_CurrentFilterI);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Filter_I != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tȡִ̣\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentRange(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Max = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_Current_Max);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Max != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tʹִ˲\n  * @\t\tidҪִid\n  *\t\t\tenableʹ״̬Actr_EnableʹܣActr_Disableʧ\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t enableCurrentFilter(uint8_t id,uint8_t enable,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Current_Filter_State = enable;\n\n    Error = SCA_Write_1(pSCA, W1_CurrentFilterState, enable);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Current_Filter_State != enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִ˲ʹ״̬\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t isCurrentFilterEnable(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Filter_State = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R1_CurrentFilterState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Filter_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tȡִ˲\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentCutoffFrequency(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Filter_Value = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_CurrentFilterValue);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Filter_Value != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tִ˲\n  * @\t\tidҪִid\n  *\t\t\tfrequencyĿֹƵʣλ hz\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setCurrentCutoffFrequency(uint8_t id, float frequency,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Current_Filter_Value = frequency;\n\n    Error = SCA_Write_2(pSCA, W2_CurrentFilterValue, frequency);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Current_Filter_Value != frequency) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִ޷\n  * @\t\tidҪִid\n  *\t\t\tlimit޷\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setCurrentLimit(uint8_t id,float limit,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Current_Limit = limit;\n\n    Error = SCA_Write_3(pSCA, W3_CurrentLimit, limit);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Current_Limit != limit) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִ޷\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getCurrentLimit(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Current_Limit = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_CurrentLimit);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Current_Limit != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/***********************************************************/\n\n/**\n  * @\t\tȡִѹ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getVoltage(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Voltage = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_Voltage);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Voltage != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִת\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getLockEnergy(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Blocked_Energy = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R3_BlockEngy);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Blocked_Energy != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tִתֵ\n  * @\t\tidҪִid\n  *\t\t\tenergyתֵʵֵλ J\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setLockEnergy(uint8_t id,float energy,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Blocked_Energy = energy;\n\n    Error = SCA_Write_3(pSCA, W3_BlockEngy, energy);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Blocked_Energy != energy) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getMotorTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Motor_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_MotorTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Motor_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tȡִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getInverterTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Inverter_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_InverterTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Inverter_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tȡִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getMotorProtectedTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Inverter_Protect_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_MotorProtectTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Inverter_Protect_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\ttemp¶ֵʵֵλ ϶\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setMotorProtectedTemperature(uint8_t id,float temp,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Motor_Protect_Temp = temp;\n\n    Error = SCA_Write_2(pSCA, W2_MotorProtectTemp, temp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Motor_Protect_Temp != temp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִָ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getMotorRecoveryTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Motor_Recover_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_MotorRecoverTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Motor_Recover_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִָ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\ttempָ¶ֵʵֵλ ϶\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setMotorRecoveryTemperature(uint8_t id,float temp,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Motor_Recover_Temp = temp;\n\n    Error = SCA_Write_2(pSCA, W2_MotorRecoverTemp, temp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Motor_Recover_Temp != temp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getInverterProtectedTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Inverter_Protect_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_InverterProtectTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Inverter_Protect_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tִ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\ttemp¶ֵʵֵλ ϶\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setInverterProtectedTemperature(uint8_t id,float temp,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Inverter_Protect_Temp = temp;\n\n    Error = SCA_Write_2(pSCA, W2_InverterProtectTemp, temp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Inverter_Protect_Temp != temp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִָ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getInverterRecoveryTemperature(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Inverter_Recover_Temp = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R2_InverterRecoverTemp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Inverter_Recover_Temp != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tִָ¶ֵ\n  * @\t\tidҪִid\n  *\t\t\ttempָ¶ֵʵֵλ ϶\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setInverterRecoveryTemperature(uint8_t id,float temp,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.Inverter_Recover_Temp = temp;\n\n    Error = SCA_Write_2(pSCA, W2_InverterRecoverTemp, temp);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->Inverter_Recover_Temp != temp) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tִid\n  * @\t\tnewIDid\n  *\t\t\tcurrentIDǰid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t setActuatorID(uint8_t currentID, uint8_t newID,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ĿIDǷѴ */\n    pSCA = getInstance(newID);\n    if(pSCA != NULL)\treturn SCA_OperationFailed;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(currentID);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* Ŀд뻺棬ȴ */\n    pSCA->paraCache.ID = newID;\n\n    Error = SCA_Write_5(pSCA, W5_ChangeID, newID);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->ID != newID) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n  * @\t\tȡִкţ浽\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getActuatorSerialNumber(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Serial_Num = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R5_ShakeHands);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Serial_Num != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n  * @\t\tȡִϴεĹػ״̬浽\n  * @\t\tidҪִid\n  *\t\t\tisBlockBlockΪʽUnblockΪʽ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t getActuatorLastState(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_Last_State = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R1_LastState);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_Last_State != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n\n}\n\n/**\n * @\t\tȡٶλõֵУЧʸ\n * @\t\tidҪִid\n *\t\t\tisBlockBlockΪʽUnblockΪʽ\n * @\t\tSCA_NoErrorɹ\n *\t\t\tͨŴμ SCA_Error б\n */\nuint8_t requestCVPValue(uint8_t id,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n    SCA_Handler_t* pSCA = NULL;\n\n    /* ȡIDϢ */\n    pSCA = getInstance(id);\n    if(pSCA == NULL)\treturn SCA_UnknownID;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_CVP = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R4_CVP);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_CVP != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n\n/**\n * @\t\tȡٶλõֵУЧʸߣ\n * @\t\tpSCAҪִַָ\n *\t\t\tisBlockBlockΪʽUnblockΪʽ\n * @\t\tSCA_NoErrorɹ\n *\t\t\tͨŴμ SCA_Error б\n */\nuint8_t requestCVPValueFast(SCA_Handler_t* pSCA,uint8_t isBlock)\n{\n    uint8_t Error;\n    uint32_t waitime = 0;\n\n    /* ״̬λ */\n    pSCA->paraCache.R_CVP = Actr_Disable;\n\n    Error = SCA_Read(pSCA, R4_CVP);\n    if(Error)\treturn Error;\n\n    /*  */\n    if(isBlock == Unblock)\n    {\n        /* ͺʱֹ߹ */\n        SCA_Delay(SendInterval);\n        return Error;\n    }\n\n    /* ȴִн */\n    while((pSCA->paraCache.R_CVP != Actr_Enable) && (waitime++ < CanOvertime));\n    if(waitime >= CanOvertime)\treturn SCA_OperationFailed;\n\n    return Error;\n}\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca_api.h",
    "content": "/**\n  ******************************************************************************\n  * @\t  SCA_API.h\n  * @\t  INNFOS Software Team\n  * @\t  V1.5.3\n  * @\t  2019.09.10\n  * @ժ\tҪ  SCA ƽӿڲ\n  ******************************************************************************/\n\n#ifndef __SCA_API_H\n#define __SCA_API_H\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"sca_protocol.h\"\n#include <string.h>\n#include <stdio.h>\n#include <malloc.h>\n#include \"time_utils.h\"\n\n/*  */\n#define SCA_NUM_USE        2            //ǰʹSCA,1-255\n#define SCA_DEBUGER        0            //ʹܵԽӿ\n#define CanOvertime        0xFFFF        //ʱ180MHZ\n#define CanPowertime    0xFFFFFF    //ػʱ180MHZ\n#define SendInterval    200            //ʱָͼ\n#define SCA_Delay(x)    delayMicroseconds(x)    //ʱӿڣʱʱ\n\n\n#if SCA_DEBUGER\n#define SCA_Debug printf\n#else\n#define SCA_Debug(s,...)\n#endif\n\n/* º궨Ϣ޸ģ */\n\n//SCA״̬\n#define Actr_Enable        0x01\n#define Actr_Disable    0x00\n\n//ͨŷʽ\n#define Block            0x01\n#define Unblock            0x00\n\n//SCAģʽ\n#define SCA_Current_Mode            0x01\n#define SCA_Velocity_Mode            0x02\n#define SCA_Position_Mode            0x03\n#define SCA_Profile_Position_Mode    0X06\n#define SCA_Profile_Velocity_Mode    0X07\n#define SCA_Homing_Mode                0X08\n\n/* \nFASTຯʹ˵\n\tIDAPIʱڲIDӦϢֱ۵SCAʹ\n\t϶ʱִЧʵֱ͡ӶָָӦĽṹ壬ʡ\n\tȥҾḶָֹ́ʹʱԾڲݵ޸ġ\n\tָڴFast͵APIʹõSCA϶Ƶдʱ\n\tߺִЧʡ͵ĺҲɰմַʽ޸ġ\n\t\n\tExample:\n\n\t\t//ִID 0x03ԸIDпдλ\n\t\tSCA_Handler_t* pSCA_ID3 = NULL;\n\t\tpSCA_ID3 = getInstance(0x03);\n\t\tif(pSCA_ID3 == NULL)\treturn;//δҵIDϢ\n\n\t\t//öõֱָӴFastдλú\n\t\tsetPositionFast(pSCA_ID3,100);\n\t\nʽʹ˵\n\tвisBlockĺ֧ʽִзʽɸʵ\n\tʹѡȴʱڲпɸCPUʸĸ\n\tƿȺΪʽͨţȴִнأݴҡ\n\t⣬ʹ߹أSCAڷ\n\tִʱڲбʱͨøʱʱ䡣\n*/\n\n/*********************************/\nvoid lookupActuators(CAN_Handler_t *canPort);\nvoid setupActuators(uint8_t id, CAN_Handler_t *can);\nvoid resetController(uint8_t id);\nvoid enableAllActuators(void);\nvoid disableAllActuators(void);\nvoid regainAttrbute(uint8_t id, uint8_t isBlock);\nuint8_t isOnline(uint8_t id, uint8_t isBlock);\nuint8_t isEnable(uint8_t id, uint8_t isBlock);\nuint8_t isUpdate(uint8_t id);\nuint8_t enableActuator(uint8_t id);\nuint8_t disableActuator(uint8_t id);\nuint8_t activateActuatorMode(uint8_t id, uint8_t ActuatorMode, uint8_t isBlock);\nuint8_t getActuatorMode(uint8_t id, uint8_t isBlock);\nuint8_t getErrorCode(uint8_t id, uint8_t isBlock);\nuint8_t clearError(uint8_t id, uint8_t isBlock);\nuint8_t saveAllParams(uint8_t id, uint8_t isBlock);\nSCA_Handler_t *getInstance(uint8_t id);\n\n/***************λ******************/\nuint8_t setPosition(uint8_t id, float pos);\nuint8_t setPositionFast(SCA_Handler_t *pSCA, float pos);\nuint8_t getPosition(uint8_t id, uint8_t isBlock);\nuint8_t getPositionFast(SCA_Handler_t *pSCA, uint8_t isBlock);\nuint8_t setPositionKp(uint8_t id, float Kp, uint8_t isBlock);\nuint8_t getPositionKp(uint8_t id, uint8_t isBlock);\nuint8_t setPositionKi(uint8_t id, float Ki, uint8_t isBlock);\nuint8_t getPositionKi(uint8_t id, uint8_t isBlock);\nuint8_t setPositionUmax(uint8_t id, float max, uint8_t isBlock);\nuint8_t getPositionUmax(uint8_t id, uint8_t isBlock);\nuint8_t setPositionUmin(uint8_t id, float min, uint8_t isBlock);\nuint8_t getPositionUmin(uint8_t id, uint8_t isBlock);\nuint8_t setPositionOffset(uint8_t id, float offset, uint8_t isBlock);\nuint8_t getPositionOffset(uint8_t id, uint8_t isBlock);\nuint8_t setMaximumPosition(uint8_t id, float maxPos, uint8_t isBlock);\nuint8_t getMaximumPosition(uint8_t id, uint8_t isBlock);\nuint8_t setMinimumPosition(uint8_t id, float minPos, uint8_t isBlock);\nuint8_t getMinimumPosition(uint8_t id, uint8_t isBlock);\nuint8_t enablePositionLimit(uint8_t id, uint8_t enable, uint8_t isBlock);\nuint8_t isPositionLimitEnable(uint8_t id, uint8_t isBlock);\nuint8_t setHomingPosition(uint8_t id, float homingPos, uint8_t isBlock);\nuint8_t enablePositionFilter(uint8_t id, uint8_t enable, uint8_t isBlock);\nuint8_t isPositionFilterEnable(uint8_t id, uint8_t isBlock);\nuint8_t setPositionCutoffFrequency(uint8_t id, float frequency, uint8_t isBlock);\nuint8_t getPositionCutoffFrequency(uint8_t id, uint8_t isBlock);\nuint8_t clearHomingInfo(uint8_t id, uint8_t isBlock);\nuint8_t setProfilePositionAcceleration(uint8_t id, float acceleration, uint8_t isBlock);\nuint8_t getProfilePositionAcceleration(uint8_t id, uint8_t isBlock);\nuint8_t setProfilePositionDeceleration(uint8_t id, float deceleration, uint8_t isBlock);\nuint8_t getProfilePositionDeceleration(uint8_t id, uint8_t isBlock);\nuint8_t setProfilePositionMaxVelocity(uint8_t id, float maxVelocity, uint8_t isBlock);\nuint8_t getProfilePositionMaxVelocity(uint8_t id, uint8_t isBlock);\n\n/***************ٶ******************/\nuint8_t setVelocity(uint8_t id, float vel);\nuint8_t setVelocityFast(SCA_Handler_t *pSCA, float vel);\nuint8_t getVelocity(uint8_t id, uint8_t isBlock);\nuint8_t getVelocityFast(SCA_Handler_t *pSCA, uint8_t isBlock);\nuint8_t getVelocityKp(uint8_t id, uint8_t isBlock);\nuint8_t setVelocityKp(uint8_t id, float Kp, uint8_t isBlock);\nuint8_t getVelocityKi(uint8_t id, uint8_t isBlock);\nuint8_t setVelocityKi(uint8_t id, float Ki, uint8_t isBlock);\nuint8_t getVelocityUmax(uint8_t id, uint8_t isBlock);\nuint8_t setVelocityUmax(uint8_t id, float max, uint8_t isBlock);\nuint8_t getVelocityUmin(uint8_t id, uint8_t isBlock);\nuint8_t setVelocityUmin(uint8_t id, float min, uint8_t isBlock);\nuint8_t enableVelocityFilter(uint8_t id, uint8_t enable, uint8_t isBlock);\nuint8_t isVelocityFilterEnable(uint8_t id, uint8_t isBlock);\nuint8_t getVelocityCutoffFrequency(uint8_t id, uint8_t isBlock);\nuint8_t setVelocityCutoffFrequency(uint8_t id, float frequency, uint8_t isBlock);\nuint8_t setVelocityLimit(uint8_t id, float limit, uint8_t isBlock);\nuint8_t getVelocityLimit(uint8_t id, uint8_t isBlock);\nuint8_t setProfileVelocityAcceleration(uint8_t id, float acceleration, uint8_t isBlock);\nuint8_t getProfileVelocityAcceleration(uint8_t id, uint8_t isBlock);\nuint8_t setProfileVelocityDeceleration(uint8_t id, float deceleration, uint8_t isBlock);\nuint8_t getProfileVelocityDeceleration(uint8_t id, uint8_t isBlock);\nuint8_t setProfileVelocityMaxVelocity(uint8_t id, float maxVelocity, uint8_t isBlock);\nuint8_t getProfileVelocityMaxVelocity(uint8_t id, uint8_t isBlock);\nfloat getVelocityRange(uint8_t id);\n\n/*********************************/\nuint8_t setCurrent(uint8_t id, float current);\nuint8_t setCurrentFast(SCA_Handler_t *pSCA, float current);\nuint8_t getCurrent(uint8_t id, uint8_t isBlock);\nuint8_t getCurrentFast(SCA_Handler_t *pSCA, uint8_t isBlock);\nuint8_t getCurrentKp(uint8_t id, uint8_t isBlock);\nuint8_t getCurrentKi(uint8_t id, uint8_t isBlock);\nuint8_t getCurrentRange(uint8_t id, uint8_t isBlock);\nuint8_t enableCurrentFilter(uint8_t id, uint8_t enable, uint8_t isBlock);\nuint8_t isCurrentFilterEnable(uint8_t id, uint8_t isBlock);\nuint8_t getCurrentCutoffFrequency(uint8_t id, uint8_t isBlock);\nuint8_t setCurrentCutoffFrequency(uint8_t id, float frequency, uint8_t isBlock);\nuint8_t setCurrentLimit(uint8_t id, float limit, uint8_t isBlock);\nuint8_t getCurrentLimit(uint8_t id, uint8_t isBlock);\n\n/*********************************/\nuint8_t getVoltage(uint8_t id, uint8_t isBlock);\nuint8_t getLockEnergy(uint8_t id, uint8_t isBlock);\nuint8_t setLockEnergy(uint8_t id, float energy, uint8_t isBlock);\nuint8_t getActuatorSerialNumber(uint8_t id, uint8_t isBlock);\nuint8_t getMotorTemperature(uint8_t id, uint8_t isBlock);\nuint8_t getInverterTemperature(uint8_t id, uint8_t isBlock);\nuint8_t getMotorProtectedTemperature(uint8_t id, uint8_t isBlock);\nuint8_t setMotorProtectedTemperature(uint8_t id, float temp, uint8_t isBlock);\nuint8_t getMotorRecoveryTemperature(uint8_t id, uint8_t isBlock);\nuint8_t setMotorRecoveryTemperature(uint8_t id, float temp, uint8_t isBlock);\nuint8_t getInverterProtectedTemperature(uint8_t id, uint8_t isBlock);\nuint8_t setInverterProtectedTemperature(uint8_t id, float temp, uint8_t isBlock);\nuint8_t getInverterRecoveryTemperature(uint8_t id, uint8_t isBlock);\nuint8_t setInverterRecoveryTemperature(uint8_t id, float temp, uint8_t isBlock);\nuint8_t setActuatorID(uint8_t currentID, uint8_t newID, uint8_t isBlock);\nuint8_t getActuatorLastState(uint8_t id, uint8_t isBlock);\nuint8_t requestCVPValue(uint8_t id, uint8_t isBlock);\nuint8_t requestCVPValueFast(SCA_Handler_t *pSCA, uint8_t isBlock);\n\n\n#ifdef __cplusplus\n}\n\n#endif\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca_protocol.c",
    "content": "/**\n  ******************************************************************************\n  * @\t  SCA_Protocol.c\n  * @\t  INNFOS Software Team\n  * @\t  V1.5.2\n  * @\t  2019.06.24\n  * @ժ\tҪ  INNFOS CAN ͨЭ\n  ******************************************************************************/\n/* Update log --------------------------------------------------------------------*/\n//V1.1.0 2019.08.05 дӿ,CANߵݵȴʱ\n//V1.5.0 2019.08.16 ݽսӿڣͳһӿڡݷӿڣ\n//V1.5.2 2019.11.04\t޸Ծɰļԡ\n\n/* Includes ----------------------------------------------------------------------*/\n#include \"sca_api.h\"\n\n/* Forward Declaration -----------------------------------------------------------*/\nstatic uint8_t canTransmit(SCA_Handler_t *pSCA, uint8_t *TxBuf, uint8_t TxLen);\nstatic void R1dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg);\nstatic void R2dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg);\nstatic void R3dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg);\nstatic void R4dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg);\nstatic void WriteDataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg);\nvoid warnBitAnaly(SCA_Handler_t *pSCA);\n\n/* Funcation defines -------------------------------------------------------------*/\n\n/**\n  * @\t\t1д2byte2byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  *\t\t\tTxDataҪ͵ݣ\n  *\t\t\t\t\t1.ִģʽѡ 2.ʹܣ0x01ʧܣ0x00\n  * @\t\tSCA_NoErrorͳɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Write_1(SCA_Handler_t *pSCA, uint8_t cmd, uint8_t TxData)\n{\n    uint8_t TxBuf[2];\n\n    /* ݴʽ\n        TxBuf[0]- \tTxBuf[1]-ݣλ TxBuf[7]-ݣλ */\n    TxBuf[0] = cmd;\n    TxBuf[1] = TxData;\n\n    /* õײͨźݣͨŴ򷵻شֵ */\n    return canTransmit(pSCA, TxBuf, 2);\n}\n\n/**\n  * @\t\t2д3byte2byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  *\t\t\tTxDataҪ͵ݣʵֵ\n  * @\t\tSCA_NoErrorͳɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Write_2(SCA_Handler_t *pSCA, uint8_t cmd, float TxData)\n{\n    uint8_t TxBuf[3];\n    int16_t temp;\n\n    /* ڶдIQ8ʽд */\n    temp = TxData * IQ8;\n\n    /* ݴ */\n    TxBuf[0] = cmd;\n    TxBuf[1] = (uint8_t) (temp >> 8);\n    TxBuf[2] = (uint8_t) (temp >> 0);\n\n    return canTransmit(pSCA, TxBuf, 3);\n}\n\n/**\n  * @\t\t3д5byte2byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  *\t\t\tTxData͵ݣʵֵ\n  * @\t\tSCA_NoErrorͳɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Write_3(SCA_Handler_t *pSCA, uint8_t cmd, float TxData)\n{\n    uint8_t TxBuf[5];\n    int32_t temp;\n\n    /*\tٶ趨ʱҪñֵ\n        趨ֵԸòֵתΪIQ24ʽ\t*/\n    if ((cmd == W3_Velocity) || (cmd == W3_VelocityLimit))\n        temp = TxData / Velocity_Max * IQ24;\n    else if ((cmd == W3_Current) || (cmd == W3_CurrentLimit))\n        temp = TxData / pSCA->Current_Max * IQ24;\n    else if (cmd == W3_BlockEngy)\n        temp = TxData * BlkEngy_Scal;    //תΪʵֵ75.225\n    else\n        temp = TxData * IQ24;\n\n    TxBuf[0] = cmd;\n    TxBuf[1] = (uint8_t) (temp >> 24);\n    TxBuf[2] = (uint8_t) (temp >> 16);\n    TxBuf[3] = (uint8_t) (temp >> 8);\n    TxBuf[4] = (uint8_t) (temp >> 0);\n\n    return canTransmit(pSCA, TxBuf, 5);\n}\n\n/**\n  * @\t\t4д1byte2byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  * @\t\tSCA_NoErrorͳɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Write_4(SCA_Handler_t *pSCA, uint8_t cmd)\n{\n    uint8_t TxBuf[1];\n    TxBuf[0] = cmd;\n    return canTransmit(pSCA, TxBuf, 1);\n}\n\n/**\n  * @\t\t5д6byte2byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  *\t\t\tTxData\n  * @\t\tSCA_NoErrorͳɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Write_5(SCA_Handler_t *pSCA, uint8_t cmd, uint8_t TxData)\n{\n    uint8_t TxBuf[6];\n\n    /*\n        дݸʽ\n        1ֽ+4ֽڵַSCAкţ+1ֽڲĿݣ\n    */\n    TxBuf[0] = cmd;\n    TxBuf[1] = pSCA->Serial_Num[0];\n    TxBuf[2] = pSCA->Serial_Num[1];\n    TxBuf[3] = pSCA->Serial_Num[2];\n    TxBuf[4] = pSCA->Serial_Num[3];\n    TxBuf[5] = TxData;\n\n    return canTransmit(pSCA, TxBuf, 6);\n}\n\n/**\n  * @\t\tȡӿڣ1byte\n  * @\t\tpSCAҪִַָ\n  *\t\t\tcmdָ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tͨŴμ SCA_Error б\n  */\nuint8_t SCA_Read(SCA_Handler_t *pSCA, uint8_t cmd)\n{\n    uint8_t TxBuf[1];\n    TxBuf[0] = cmd;\n    return canTransmit(pSCA, TxBuf, 1);\n}\n\n/**\n  * @\t\tCANײͨź\n  * @\t\tIDҪִID\n  *\t\t\tTxBufҪ͵ݵַ\n  *\t\t\tTxLenҪ͵ݳ\n  * @\t\tSCA_NoErrorɹ\n  *\t\t\tSCA_SendErrorʧ\n  */\nstatic uint8_t canTransmit(SCA_Handler_t *pSCA, uint8_t *TxBuf, uint8_t TxLen)\n{\n    uint32_t waitime = 0;\n\n    /* CAN1ָݣʧططRetry */\n    while (pSCA->Can->Send(pSCA->ID, TxBuf, TxLen) && (waitime < pSCA->Can->Retry)) waitime++;\n\n    /* ʹ趨ֵطʧ */\n    if (waitime >= pSCA->Can->Retry)\n        return SCA_SendError;\n\n    /* ݷͳɹûд */\n    return SCA_NoError;\n}\n\n/**\n  * @\t\t1ȡݽ1byte2byte\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void R1dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    /* ȡװصյַ */\n    switch (RxMsg->Data[0])\n    {\n        case R1_Heartbeat:\n            pSCA->Online_State = RxMsg->Data[1];\n            break;\n\n        case R1_Mode:\n            pSCA->Mode = RxMsg->Data[1];\n            pSCA->paraCache.R_Mode = Actr_Enable;\n            break;\n\n        case R1_LastState:\n            pSCA->Last_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Last_State = Actr_Enable;\n            break;\n\n        case R1_CurrentFilterState:\n            pSCA->Current_Filter_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Current_Filter_State = Actr_Enable;\n            break;\n\n        case R1_VelocityFilterState:\n            pSCA->Velocity_Filter_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Velocity_Filter_State = Actr_Enable;\n            break;\n\n        case R1_PositionFilterState:\n            pSCA->Position_Filter_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Position_Filter_State = Actr_Enable;\n            break;\n\n        case R1_PositionLimitState:\n            pSCA->Position_Limit_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Position_Limit_State = Actr_Enable;\n            break;\n\n        case R1_PowerState:\n            pSCA->Power_State = RxMsg->Data[1];\n            pSCA->paraCache.R_Power_State = Actr_Enable;\n            break;\n\n        default:\n            break;\n    }\n}\n\n/**\n  * @\t\t2ȡݽ1byte3byte\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void R2dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    int16_t temp;\n    float RxData;\n\n    /* ڶдΪIQ8ʽ */\n    temp = ((int16_t) RxMsg->Data[1]) << 8;\n    temp |= ((int16_t) RxMsg->Data[2]) << 0;\n\n    /* ڵڶдУѹΪIQ10ʽ */\n    if (RxMsg->Data[0] == R2_Voltage)\n        RxData = (float) temp / IQ10;\n    else\n        RxData = (float) temp / IQ8;\n\n    switch (RxMsg->Data[0])\n    {\n        case R2_Voltage:\n            pSCA->Voltage = RxData;\n            pSCA->paraCache.R_Voltage = Actr_Enable;\n            break;\n\n        case R2_Current_Max:\n            pSCA->Current_Max = RxData;\n            pSCA->paraCache.R_Current_Max = Actr_Enable;\n            break;\n\n        case R2_CurrentFilterValue:\n            pSCA->Current_Filter_Value = RxData;\n            pSCA->paraCache.R_Current_Filter_Value = Actr_Enable;\n            break;\n\n        case R2_VelocityFilterValue:\n            pSCA->Velocity_Filter_Value = RxData;\n            pSCA->paraCache.R_Velocity_Filter_Value = Actr_Enable;\n            break;\n\n        case R2_PositionFilterValue:\n            pSCA->Position_Filter_Value = RxData;\n            pSCA->paraCache.R_Position_Filter_Value = Actr_Enable;\n            break;\n\n        case R2_MotorTemp:\n            pSCA->Motor_Temp = RxData;\n            pSCA->paraCache.R_Motor_Temp = Actr_Enable;\n            break;\n\n        case R2_InverterTemp:\n            pSCA->Inverter_Temp = RxData;\n            pSCA->paraCache.R_Inverter_Temp = Actr_Enable;\n            break;\n\n        case R2_InverterProtectTemp:\n            pSCA->Inverter_Protect_Temp = RxData;\n            pSCA->paraCache.R_Inverter_Protect_Temp = Actr_Enable;\n            break;\n\n        case R2_InverterRecoverTemp:\n            pSCA->Inverter_Recover_Temp = RxData;\n            pSCA->paraCache.R_Inverter_Recover_Temp = Actr_Enable;\n            break;\n\n        case R2_MotorProtectTemp:\n            pSCA->Motor_Protect_Temp = RxData;\n            pSCA->paraCache.R_Motor_Protect_Temp = Actr_Enable;\n            break;\n\n        case R2_MotorRecoverTemp:\n            pSCA->Motor_Recover_Temp = RxData;\n            pSCA->paraCache.R_Motor_Recover_Temp = Actr_Enable;\n            break;\n\n        case R2_Error:\n            pSCA->SCA_Warn.Error_Code = temp;\n            warnBitAnaly(pSCA);\n            pSCA->paraCache.R_Error_Code = Actr_Enable;\n            break;\n\n        default:\n            break;\n    }\n}\n\n/**\n  * @\t\t3ȡݽ1byte5byte\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void R3dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    int32_t temp;\n    float RxData;\n\n    /* дIQ24ʽ */\n    temp = ((int32_t) RxMsg->Data[1]) << 24;\n    temp |= ((int32_t) RxMsg->Data[2]) << 16;\n    temp |= ((int32_t) RxMsg->Data[3]) << 8;\n    temp |= ((int32_t) RxMsg->Data[4]) << 0;\n\n    /* ٶȺ͵ʹñֵҪתֵԸòֵõʵֵ */\n    if ((RxMsg->Data[0] == R3_Velocity) || (RxMsg->Data[0] == R3_VelocityLimit))\n        RxData = (float) temp / IQ24 * Velocity_Max;\n\n    else if ((RxMsg->Data[0] == R3_Current) || (RxMsg->Data[0] == R3_CurrentLimit))\n        RxData = (float) temp / IQ24 * pSCA->Current_Max;\n\n    else if (RxMsg->Data[0] == R3_BlockEngy)\n        RxData = (float) temp / BlkEngy_Scal;    //תΪʵ75.225\n\n    else\n        RxData = (float) temp / IQ24;\n\n    switch (RxMsg->Data[0])\n    {\n        case R3_Current:\n            pSCA->Current_Real = RxData;\n            pSCA->paraCache.R_Current_Real = Actr_Enable;\n            break;\n\n        case R3_Velocity:\n            pSCA->Velocity_Real = RxData;\n            pSCA->paraCache.R_Velocity_Real = Actr_Enable;\n            break;\n\n        case R3_Position:\n            pSCA->Position_Real = RxData;\n            pSCA->paraCache.R_Position_Real = Actr_Enable;\n            break;\n\n        case R3_CurrentFilterP:\n            pSCA->Current_Filter_P = RxData;\n            pSCA->paraCache.R_Current_Filter_P = Actr_Enable;\n            break;\n\n        case R3_CurrentFilterI:\n            pSCA->Current_Filter_I = RxData;\n            pSCA->paraCache.R_Current_Filter_I = Actr_Enable;\n            break;\n\n        case R3_VelocityFilterP:\n            pSCA->Velocity_Filter_P = RxData;\n            pSCA->paraCache.R_Velocity_Filter_P = Actr_Enable;\n            break;\n\n        case R3_VelocityFilterI:\n            pSCA->Velocity_Filter_I = RxData;\n            pSCA->paraCache.R_Velocity_Filter_I = Actr_Enable;\n            break;\n\n        case R3_PositionFilterP:\n            pSCA->Position_Filter_P = RxData;\n            pSCA->paraCache.R_Position_Filter_P = Actr_Enable;\n            break;\n\n        case R3_PositionFilterI:\n            pSCA->Position_Filter_I = RxData;\n            pSCA->paraCache.R_Position_Filter_I = Actr_Enable;\n            break;\n\n        case R3_PositionFilterD:\n            break;\n\n        case R3_PPMaxVelocity:\n            pSCA->PP_Max_Velocity = RxData * Profile_Scal;\n            pSCA->paraCache.R_PP_Max_Velocity = Actr_Enable;\n            break;\n\n        case R3_PPMaxAcceleration:\n            pSCA->PP_Max_Acceleration = RxData * Profile_Scal;\n            pSCA->paraCache.R_PP_Max_Acceleration = Actr_Enable;\n            break;\n\n        case R3_PPMaxDeceleration:\n            pSCA->PP_Max_Deceleration = RxData * Profile_Scal;\n            pSCA->paraCache.R_PP_Max_Deceleration = Actr_Enable;\n            break;\n\n        case R3_PVMaxVelocity:\n            pSCA->PV_Max_Velocity = RxData * Profile_Scal;\n            pSCA->paraCache.R_PV_Max_Velocity = Actr_Enable;\n            break;\n\n        case R3_PVMaxAcceleration:\n            pSCA->PV_Max_Acceleration = RxData * Profile_Scal;\n            pSCA->paraCache.R_PV_Max_Acceleration = Actr_Enable;\n            break;\n\n        case R3_PVMaxDeceleration:\n            pSCA->PV_Max_Deceleration = RxData * Profile_Scal;\n            pSCA->paraCache.R_PV_Max_Deceleration = Actr_Enable;\n            break;\n\n        case R3_CurrentFilterLimitL:\n            break;\n\n        case R3_CurrentFilterLimitH:\n            break;\n\n        case R3_VelocityFilterLimitL:\n            pSCA->Velocity_Filter_Limit_L = RxData;\n            pSCA->paraCache.R_Velocity_Filter_Limit_L = Actr_Enable;\n            break;\n\n        case R3_VelocityFilterLimitH:\n            pSCA->Velocity_Filter_Limit_H = RxData;\n            pSCA->paraCache.R_Velocity_Filter_Limit_H = Actr_Enable;\n            break;\n\n        case R3_PositionFilterLimitL:\n            pSCA->Position_Filter_Limit_L = RxData;\n            pSCA->paraCache.R_Position_Filter_Limit_L = Actr_Enable;\n            break;\n\n        case R3_PositionFilterLimitH:\n            pSCA->Position_Filter_Limit_H = RxData;\n            pSCA->paraCache.R_Position_Filter_Limit_H = Actr_Enable;\n            break;\n\n        case R3_CurrentLimit:\n            pSCA->Current_Limit = RxData;\n            pSCA->paraCache.R_Current_Limit = Actr_Enable;\n            break;\n\n        case R3_VelocityLimit:\n            pSCA->Velocity_Limit = RxData;\n            pSCA->paraCache.R_Velocity_Limit = Actr_Enable;\n            break;\n\n        case R3_Inertia:\n            break;\n\n        case R3_PositionLimitH:\n            pSCA->Position_Limit_H = RxData;\n            pSCA->paraCache.R_Position_Limit_H = Actr_Enable;\n            break;\n\n        case R3_PositionLimitL:\n            pSCA->Position_Limit_L = RxData;\n            pSCA->paraCache.R_Position_Limit_L = Actr_Enable;\n            break;\n\n        case R3_PositionOffset:\n            pSCA->Position_Offset = RxData;\n            pSCA->paraCache.R_Position_Offset = Actr_Enable;\n            break;\n\n        case R3_HomingCurrentLimitL:\n            pSCA->Homing_Current_Limit_L = RxData;\n            pSCA->paraCache.R_Homing_Current_Limit_L = Actr_Enable;\n            break;\n\n        case R3_HomingCurrentLimitH:\n            pSCA->Homing_Current_Limit_H = RxData;\n            pSCA->paraCache.R_Homing_Current_Limit_H = Actr_Enable;\n            break;\n\n        case R3_BlockEngy:\n            pSCA->Blocked_Energy = RxData;\n            pSCA->paraCache.R_Blocked_Energy = Actr_Enable;\n            break;\n\n        default:\n            break;\n    }\n}\n\n/**\n  * @\t\t4ȡݽ1byte8byte\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void R4dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    int32_t temp;\n\n    /*\tȡЭУΪʹٶȡλͬһ֡бʾ\n        ٶֵIQ14ʽ䣬λֵIQ16ʽ䡣Ϊ˷\n        λļ㣬λֵ8λλתIQ24õʵֵ\n        ͬٶֵ16λλתIQ30õʵֵ\t\t*/\n\n    temp = ((int32_t) RxMsg->Data[1]) << 24;\n    temp |= ((int32_t) RxMsg->Data[2]) << 16;\n    temp |= ((int32_t) RxMsg->Data[3]) << 8;\n    pSCA->Position_Real = (float) temp / IQ24;\n\n    temp = ((int32_t) RxMsg->Data[4]) << 24;\n    temp |= ((int32_t) RxMsg->Data[5]) << 16;\n    pSCA->Velocity_Real = (float) temp / IQ30 * Velocity_Max;\n\n    temp = ((int32_t) RxMsg->Data[6]) << 24;\n    temp |= ((int32_t) RxMsg->Data[7]) << 16;\n    pSCA->Current_Real = (float) temp / IQ30 * pSCA->Current_Max;\n\n    /* յ */\n    pSCA->paraCache.R_CVP = Actr_Enable;\n}\n\n/**\n  * @\t\t5ȡݽ1byte5byte\n  *\t\t\tڲѯִָк\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void R5dataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    /* װк */\n    pSCA->Serial_Num[0] = RxMsg->Data[1];\n    pSCA->Serial_Num[1] = RxMsg->Data[2];\n    pSCA->Serial_Num[2] = RxMsg->Data[3];\n    pSCA->Serial_Num[3] = RxMsg->Data[4];\n\n    /* յ */\n    pSCA->paraCache.R_Serial_Num = Actr_Enable;\n}\n\n/**\n  * @\t\tдݽед\n  *\t\t\tڲѯִָк\n  * @\t\tpSCAĿִַָ\n  *\t\t\tRxMsgյݰ\n  * @\t\t\n  */\nstatic void WriteDataProcess(SCA_Handler_t *pSCA, CanRxMsg *RxMsg)\n{\n    /* дɹеIJµ */\n    if (RxMsg->Data[1] == Actr_Enable)\n    {\n        /* дɹλ洢־λ */\n        pSCA->Save_State = Actr_Disable;\n\n        switch (RxMsg->Data[0])\n        {\n            case W1_Mode:\n                pSCA->Mode = pSCA->paraCache.Mode;\n                break;\n\n            case W1_CurrentFilterState:\n                pSCA->Current_Filter_State = pSCA->paraCache.Current_Filter_State;\n                break;\n\n            case W1_VelocityFilterState:\n                pSCA->Velocity_Filter_State = pSCA->paraCache.Velocity_Filter_State;\n                break;\n\n            case W1_PositionFilterState:\n                pSCA->Position_Filter_State = pSCA->paraCache.Position_Filter_State;\n                break;\n\n            case W1_PositionLimitState:\n                pSCA->Position_Limit_State = pSCA->paraCache.Position_Limit_State;\n                break;\n\n            case W1_PowerState:\n                pSCA->Power_State = pSCA->paraCache.Power_State;\n                break;\n\n            case W2_CurrentFilterValue:\n                pSCA->Current_Filter_Value = pSCA->paraCache.Current_Filter_Value;\n                break;\n\n            case W2_VelocityFilterValue:\n                pSCA->Velocity_Filter_Value = pSCA->paraCache.Velocity_Filter_Value;\n                break;\n\n            case W2_PositionFilterValue:\n                pSCA->Position_Filter_Value = pSCA->paraCache.Position_Filter_Value;\n                break;\n\n            case W2_InverterProtectTemp:\n                pSCA->Inverter_Protect_Temp = pSCA->paraCache.Inverter_Protect_Temp;\n                break;\n\n            case W2_InverterRecoverTemp:\n                pSCA->Inverter_Recover_Temp = pSCA->paraCache.Inverter_Recover_Temp;\n                break;\n\n            case W2_MotorProtectTemp:\n                pSCA->Motor_Protect_Temp = pSCA->paraCache.Motor_Protect_Temp;\n                break;\n\n            case W2_MotorRecoverTemp:\n                pSCA->Motor_Recover_Temp = pSCA->paraCache.Motor_Recover_Temp;\n                break;\n\n            case W3_Current:\n                pSCA->Current_Real = pSCA->paraCache.Current_Real;\n                break;\n\n            case W3_Velocity:\n                pSCA->Velocity_Real = pSCA->paraCache.Velocity_Real;\n                break;\n\n            case W3_Position:\n                pSCA->Position_Real = pSCA->paraCache.Position_Real;\n                break;\n\n            case W3_CurrentFilterP:\n                pSCA->Current_Filter_P = pSCA->paraCache.Current_Filter_P;\n                break;\n\n            case W3_CurrentFilterI:\n                pSCA->Current_Filter_I = pSCA->paraCache.Current_Filter_I;\n                break;\n\n            case W3_VelocityFilterP:\n                pSCA->Velocity_Filter_P = pSCA->paraCache.Velocity_Filter_P;\n                break;\n\n            case W3_VelocityFilterI:\n                pSCA->Velocity_Filter_I = pSCA->paraCache.Velocity_Filter_I;\n                break;\n\n            case W3_PositionFilterP:\n                pSCA->Position_Filter_P = pSCA->paraCache.Position_Filter_P;\n                break;\n\n            case W3_PositionFilterI:\n                pSCA->Position_Filter_I = pSCA->paraCache.Position_Filter_I;\n                break;\n\n            case W3_PositionFilterD:\n                break;\n\n            case W3_PPMaxVelocity:\n                pSCA->PP_Max_Velocity = pSCA->paraCache.PP_Max_Velocity;\n                break;\n\n            case W3_PPMaxAcceleration:\n                pSCA->PP_Max_Acceleration = pSCA->paraCache.PP_Max_Acceleration;\n                break;\n\n            case W3_PPMaxDeceleration:\n                pSCA->PP_Max_Deceleration = pSCA->paraCache.PP_Max_Deceleration;\n                break;\n\n            case W3_PVMaxVelocity:\n                pSCA->PV_Max_Velocity = pSCA->paraCache.PV_Max_Velocity;\n                break;\n\n            case W3_PVMaxAcceleration:\n                pSCA->PV_Max_Acceleration = pSCA->paraCache.PV_Max_Acceleration;\n                break;\n\n            case W3_PVMaxDeceleration:\n                pSCA->PV_Max_Deceleration = pSCA->paraCache.PV_Max_Deceleration;\n                break;\n\n            case W3_CurrentFilterLimitL:\n                break;\n\n            case W3_CurrentFilterLimitH:\n                break;\n\n            case W3_VelocityFilterLimitL:\n                pSCA->Velocity_Filter_Limit_L = pSCA->paraCache.Velocity_Filter_Limit_L;\n                break;\n\n            case W3_VelocityFilterLimitH:\n                pSCA->Velocity_Filter_Limit_H = pSCA->paraCache.Velocity_Filter_Limit_H;\n                break;\n\n            case W3_PositionFilterLimitL:\n                pSCA->Position_Filter_Limit_L = pSCA->paraCache.Position_Filter_Limit_L;\n                break;\n\n            case W3_PositionFilterLimitH:\n                pSCA->Position_Filter_Limit_H = pSCA->paraCache.Position_Filter_Limit_H;\n                break;\n\n            case W3_CurrentLimit:\n                pSCA->Current_Limit = pSCA->paraCache.Current_Limit;\n                break;\n\n            case W3_VelocityLimit:\n                pSCA->Velocity_Limit = pSCA->paraCache.Velocity_Limit;\n                break;\n\n            case W3_PositionLimitH:\n                pSCA->Position_Limit_H = pSCA->paraCache.Position_Limit_H;\n                break;\n\n            case W3_PositionLimitL:\n                pSCA->Position_Limit_L = pSCA->paraCache.Position_Limit_L;\n                break;\n\n            case W3_HomingValue:\n                pSCA->Homing_Value = pSCA->paraCache.Homing_Value;\n                break;\n\n            case W3_PositionOffset:\n                pSCA->Position_Offset = pSCA->paraCache.Position_Offset;\n                break;\n\n            case W3_HomingCurrentLimitL:\n                pSCA->Homing_Current_Limit_L = pSCA->paraCache.Homing_Current_Limit_L;\n                break;\n\n            case W3_HomingCurrentLimitH:\n                pSCA->Homing_Current_Limit_H = pSCA->paraCache.Homing_Current_Limit_H;\n                break;\n\n            case W3_BlockEngy:\n                pSCA->Blocked_Energy = pSCA->paraCache.Blocked_Energy;\n                break;\n\n            case W4_ClearError:\n                pSCA->SCA_Warn.Error_Code = 0;\n                warnBitAnaly(pSCA);\n                break;\n\n            case W4_ClearHome:\n                pSCA->Position_Real = 0;\n                pSCA->Position_Limit_H = 127.0f;\n                pSCA->Position_Limit_L = -127.0f;\n                pSCA->paraCache.W_ClearHome = Actr_Enable;\n                break;\n\n            case W4_Save:\n                pSCA->Save_State = Actr_Enable;\n                break;\n\n            case W5_ChangeID:\n                pSCA->ID = pSCA->paraCache.ID;\n\n            default:\n                break;\n        }\n    }\n}\n\n/**\n  * @\t\tCANݽ\n  * @\t\tRxMessageյݰ\n  * @\t\t\n  */\nvoid canDispatch(CanRxMsg *RxMsg)\n{\n    SCA_Handler_t *pSCA = getInstance((uint8_t) RxMsg->StdId);\n\n    /* ڸIDϢ */\n    if (pSCA == NULL) return;\n\n    /* ݸ */\n    pSCA->Update_State = Actr_Enable;\n\n    /*  */\n    switch (RxMsg->Data[0])\n    {\n        case R1_Heartbeat:\n        case R1_Mode:\n        case R1_LastState:\n        case R1_CurrentFilterState:\n        case R1_VelocityFilterState:\n        case R1_PositionFilterState:\n        case R1_PositionLimitState:\n        case R1_PowerState:\n            R1dataProcess(pSCA, RxMsg);\n            break;\n\n        case R2_Voltage:\n        case R2_Current_Max:\n        case R2_CurrentFilterValue:\n        case R2_VelocityFilterValue:\n        case R2_PositionFilterValue:\n        case R2_MotorTemp:\n        case R2_InverterTemp:\n        case R2_InverterProtectTemp:\n        case R2_InverterRecoverTemp:\n        case R2_MotorProtectTemp:\n        case R2_MotorRecoverTemp:\n        case R2_Error:\n            R2dataProcess(pSCA, RxMsg);\n            break;\n\n        case R3_Current:\n        case R3_Velocity:\n        case R3_Position:\n        case R3_CurrentFilterP:\n        case R3_CurrentFilterI:\n        case R3_VelocityFilterP:\n        case R3_VelocityFilterI:\n        case R3_PositionFilterP:\n        case R3_PositionFilterI:\n        case R3_PositionFilterD:\n        case R3_PPMaxVelocity:\n        case R3_PPMaxAcceleration:\n        case R3_PPMaxDeceleration:\n        case R3_PVMaxVelocity:\n        case R3_PVMaxAcceleration:\n        case R3_PVMaxDeceleration:\n        case R3_CurrentFilterLimitL:\n        case R3_CurrentFilterLimitH:\n        case R3_VelocityFilterLimitL:\n        case R3_VelocityFilterLimitH:\n        case R3_PositionFilterLimitL:\n        case R3_PositionFilterLimitH:\n        case R3_CurrentLimit:\n        case R3_VelocityLimit:\n        case R3_Inertia:\n        case R3_PositionLimitH:\n        case R3_PositionLimitL:\n        case R3_PositionOffset:\n        case R3_HomingCurrentLimitL:\n        case R3_HomingCurrentLimitH:\n        case R3_BlockEngy:\n            R3dataProcess(pSCA, RxMsg);\n            break;\n\n        case R4_CVP:\n            R4dataProcess(pSCA, RxMsg);\n            break;\n\n        case R5_ShakeHands:\n            R5dataProcess(pSCA, RxMsg);\n            break;\n\n            /* ΪдָждǷɹ¾ */\n        default:\n            WriteDataProcess(pSCA, RxMsg);\n            break;\n    }\n}\n\n/**\n  * @\t\tʶеľϢ\n  * @\t\tpSCAҪִַָ\n  * @\t\t\n  */\nvoid warnBitAnaly(SCA_Handler_t *pSCA)\n{\n    if (pSCA->SCA_Warn.Error_Code & 0x0001)\n        pSCA->SCA_Warn.WARN_OVER_VOLT = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_OVER_VOLT = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0002)\n        pSCA->SCA_Warn.WARN_UNDER_VOLT = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_UNDER_VOLT = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0004)\n        pSCA->SCA_Warn.WARN_LOCK_ROTOR = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_LOCK_ROTOR = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0008)\n        pSCA->SCA_Warn.WARN_OVER_TEMP = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_OVER_TEMP = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0010)\n        pSCA->SCA_Warn.WARN_RW_PARA = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_RW_PARA = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0020)\n        pSCA->SCA_Warn.WARN_MUL_CIRCLE = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_MUL_CIRCLE = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0040)\n        pSCA->SCA_Warn.WARN_TEMP_SENSOR_INV = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_TEMP_SENSOR_INV = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0080)\n        pSCA->SCA_Warn.WARN_CAN_BUS = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_CAN_BUS = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0100)\n        pSCA->SCA_Warn.WARN_TEMP_SENSOR_MTR = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_TEMP_SENSOR_MTR = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0200)\n        pSCA->SCA_Warn.WARN_OVER_STEP = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_OVER_STEP = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0x0400)\n        pSCA->SCA_Warn.WARN_DRV_PROTEC = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_DRV_PROTEC = Actr_Disable;\n\n    if (pSCA->SCA_Warn.Error_Code & 0xF800)\n        pSCA->SCA_Warn.WARN_DVICE = Actr_Enable;\n    else\n        pSCA->SCA_Warn.WARN_DVICE = Actr_Disable;\n\n}\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/actuators/mintasca/sca_protocol.h",
    "content": "/**\n  ******************************************************************************\n  * @\t  SCA_Protocol.h\n  * @\t  INNFOS Software Team\n  * @\t  V1.5.2\n  * @\t  2019.08.20\n  * @ժ\tҪ  INNFOS CAN ͨЭ\n  ******************************************************************************/\n\n#ifndef __SCA_PROTOCOL_H\n#define __SCA_PROTOCOL_H\n\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include \"main.h\"\n\n/* º궨Ϣ޸ģ */\n\n//INNFOS CAN ͨЭָ\n//һȡָ\n#define R1_Heartbeat            0x00\n#define R1_Mode                    0x55\n#define R1_LastState            0xB0\n#define R1_CurrentFilterState    0X71\n#define R1_VelocityFilterState    0x75\n#define R1_PositionFilterState    0x79\n#define R1_PositionLimitState    0x8B\n#define R1_PowerState            0x2B\n\n//ڶȡָ\n#define R2_Voltage                0x45\n#define R2_Current_Max            0x53\n#define R2_CurrentFilterValue    0x73\n#define R2_VelocityFilterValue    0x77\n#define R2_PositionFilterValue    0x7B\n#define R2_MotorTemp            0x5F\n#define R2_InverterTemp            0x60\n#define R2_InverterProtectTemp    0x62\n#define R2_InverterRecoverTemp    0x64\n#define R2_MotorProtectTemp        0x6C\n#define R2_MotorRecoverTemp        0x6E\n#define R2_Error                0xFF\n\n//ȡָ\n#define R3_Current                0x04\n#define R3_Velocity                0x05\n#define R3_Position                0x06\n#define R3_CurrentFilterP        0x15\n#define R3_CurrentFilterI        0x16\n#define R3_VelocityFilterP        0x17\n#define R3_VelocityFilterI        0x18\n#define R3_PositionFilterP        0x19\n#define R3_PositionFilterI        0x1A\n#define R3_PositionFilterD        0X1B\n#define R3_PPMaxVelocity        0x1C\n#define R3_PPMaxAcceleration    0x1D\n#define R3_PPMaxDeceleration    0x1E\n#define R3_PVMaxVelocity        0x22\n#define R3_PVMaxAcceleration    0x23\n#define R3_PVMaxDeceleration    0x24\n#define R3_CurrentFilterLimitL    0x34\n#define R3_CurrentFilterLimitH    0x35\n#define R3_VelocityFilterLimitL    0x36\n#define R3_VelocityFilterLimitH    0x37\n#define R3_PositionFilterLimitL    0x38\n#define R3_PositionFilterLimitH    0x39\n#define R3_CurrentLimit            0x59\n#define R3_VelocityLimit        0x5B\n#define R3_Inertia                0x7D\n#define R3_PositionLimitH        0x85\n#define R3_PositionLimitL        0x86\n#define R3_PositionOffset        0x8A\n#define R3_HomingCurrentLimitL    0x92\n#define R3_HomingCurrentLimitH    0x93\n#define R3_BlockEngy            0x7F\n\n//ȡָ\n#define R4_CVP                    0x94\n\n//ȡָ\n#define R5_ShakeHands            0x02\n\n//һд\n#define W1_Mode                    0x07\n#define W1_CurrentFilterState    0X70\n#define W1_VelocityFilterState    0x74\n#define W1_PositionFilterState    0x78\n#define W1_PositionLimitState    0x8C\n#define W1_PowerState            0x2A\n\n//ڶд\n#define W2_CurrentFilterValue    0x72\n#define W2_VelocityFilterValue    0x76\n#define W2_PositionFilterValue    0x7A\n#define W2_InverterProtectTemp    0x61\n#define W2_InverterRecoverTemp    0x63\n#define W2_MotorProtectTemp        0x6B\n#define W2_MotorRecoverTemp        0x6D\n\n//д\n#define W3_Current                0x08\n#define W3_Velocity                0x09\n#define W3_Position                0x0A\n#define W3_CurrentFilterP        0x0E\n#define W3_CurrentFilterI        0x0F\n#define W3_VelocityFilterP        0x10\n#define W3_VelocityFilterI        0x11\n#define W3_PositionFilterP        0x12\n#define W3_PositionFilterI        0x13\n#define W3_PositionFilterD        0X14\n#define W3_PPMaxVelocity        0x1F\n#define W3_PPMaxAcceleration    0x20\n#define W3_PPMaxDeceleration    0x21\n#define W3_PVMaxVelocity        0x25\n#define W3_PVMaxAcceleration    0x26\n#define W3_PVMaxDeceleration    0x27\n#define W3_CurrentFilterLimitL    0x2E\n#define W3_CurrentFilterLimitH    0x2F\n#define W3_VelocityFilterLimitL    0x30\n#define W3_VelocityFilterLimitH    0x31\n#define W3_PositionFilterLimitL    0x32\n#define W3_PositionFilterLimitH    0x33\n#define W3_CurrentLimit            0x58\n#define W3_VelocityLimit        0x5A\n#define W3_PositionLimitH        0x83\n#define W3_PositionLimitL        0x84\n#define W3_HomingValue            0x87\n#define W3_PositionOffset        0x89\n#define W3_HomingCurrentLimitL    0x90\n#define W3_HomingCurrentLimitH    0x91\n#define W3_BlockEngy            0x7E\n\n//д\n#define W4_ClearError            0xFE\n#define W4_ClearHome            0x88\n#define W4_Save                    0x0D\n\n//д\n#define W5_ChangeID                0x3D\n\n//ֵ\n#define Velocity_Max    6000.0f            //ٶ̶ֵΪ6000RPMΪã\n#define BlkEngy_Scal    75.225f            //תֵ\n#define Profile_Scal    960.0f            //βֵ\n#define IQ8                256.0f            //2^8\n#define IQ10            1024.0f            //2^10\n#define IQ24            16777216.0f        //2^24\n#define IQ30            1073741824.0f    //2^30\n\n/* IDΪCAN֡IDmsgΪҪ͵ݣַ\n   lenΪݵijȣ0ɹʧ */\ntypedef uint8_t (*Send_t)(uint8_t ID, uint8_t *msg, uint8_t len);\n\ntypedef struct                //CAN˿ھ\n{\n    //SCA ״̬Ϣ\n    uint8_t CanPort;        //ʹõCAN˿ں\n    uint8_t Retry;            //ʧʱط\n    Send_t Send;            //ͺʽμSend_t\n} CAN_Handler_t;\n\ntypedef struct                        //SCAϢ\n{\n    uint16_t Error_Code;            //\n\n    /* 屨Ϣ01 */\n    uint8_t WARN_OVER_VOLT;        //ѹ쳣\n    uint8_t WARN_UNDER_VOLT;        //Ƿѹ쳣\n    uint8_t WARN_LOCK_ROTOR;        //ת쳣\n    uint8_t WARN_OVER_TEMP;        //쳣\n    uint8_t WARN_RW_PARA;            //д쳣\n    uint8_t WARN_MUL_CIRCLE;        //Ȧ쳣\n    uint8_t WARN_TEMP_SENSOR_INV;    //¶ȴ쳣\n    uint8_t WARN_CAN_BUS;            //CANͨѶ쳣\n    uint8_t WARN_TEMP_SENSOR_MTR;    //¶ȴ쳣\n    uint8_t WARN_OVER_STEP;            //λģʽԾ1\n    uint8_t WARN_DRV_PROTEC;        //DRV\n    uint8_t WARN_DVICE;            //豸쳣\n\n} SCA_Warn_t;\n\n/* \n\tSCA棬дʱĿɹд\n\tȡ־λʱʹãݿɸĿҪвü\n */\ntypedef struct\n{\n    /* Ϣ */\n    uint8_t ID;                        //SCA ID\n\n    /* һݱ */\n    uint8_t Mode;                    //ǰģʽ\n    uint8_t Current_Filter_State;    //˲״̬\n    uint8_t Velocity_Filter_State;    //ٶȻ˲״̬\n    uint8_t Position_Filter_State;    //ٶȻ˲״̬\n    uint8_t Position_Limit_State;    //λλ״̬\n    uint8_t Power_State;            //ػ״̬\n    /* ȡ־λ */\n    uint8_t R_Mode;                    //ȡݷر־λ 1Ϊݷ\n    uint8_t R_Last_State;\n    uint8_t R_Current_Filter_State;\n    uint8_t R_Velocity_Filter_State;\n    uint8_t R_Position_Filter_State;\n    uint8_t R_Position_Limit_State;\n    uint8_t R_Power_State;\n\n    /* ڶݱ */\n    float Current_Filter_Value;        //˲\n    float Velocity_Filter_Value;    //ٶȻ˲\n    float Position_Filter_Value;    //λû˲\n    float Inverter_Protect_Temp;    //¶\n    float Inverter_Recover_Temp;    //ָ¶\n    float Motor_Protect_Temp;        //¶\n    float Motor_Recover_Temp;        //ָ¶\n    /* ȡ־λ */\n    uint8_t R_Current_Filter_Value;\n    uint8_t R_Velocity_Filter_Value;\n    uint8_t R_Position_Filter_Value;\n    uint8_t R_Inverter_Protect_Temp;\n    uint8_t R_Inverter_Recover_Temp;\n    uint8_t R_Motor_Protect_Temp;\n    uint8_t R_Motor_Recover_Temp;\n    uint8_t R_Voltage;\n    uint8_t R_Current_Max;\n    uint8_t R_Motor_Temp;\n    uint8_t R_Inverter_Temp;\n    uint8_t R_Error_Code;\n\n    /* ݱ */\n    float Current_Real;                //ǰλA\n    float Velocity_Real;            //ǰٶȣλRPM\n    float Position_Real;            //ǰλãʵֵλR\n    float Current_Filter_P;            //Pֵ\n    float Current_Filter_I;            //Iֵ\n    float Velocity_Filter_P;        //ٶȻPֵ\n    float Velocity_Filter_I;        //ٶȻIֵ\n    float Position_Filter_P;        //λûPֵ\n    float Position_Filter_I;        //λûIֵ\n    //float Position_Filter_D;\t\t//λûDֵ\n    float PP_Max_Velocity;            //λٶֵ\n    float PP_Max_Acceleration;        //λμٶֵ\n    float PP_Max_Deceleration;        //λμٶֵ\n    float PV_Max_Velocity;            //ٶٶֵ\n    float PV_Max_Acceleration;        //ٶμٶֵ\n    float PV_Max_Deceleration;        //ٶμٶֵ\n    //float Current_Filter_Limit_L;\t//\n    //float Current_Filter_Limit_H;\t//\n    float Velocity_Filter_Limit_L;    //ٶȻ\n    float Velocity_Filter_Limit_H;    //ٶȻ\n    float Position_Filter_Limit_L;    //λû\n    float Position_Filter_Limit_H;    //λû\n    float Position_Limit_H;            //ִλ\n    float Position_Limit_L;            //ִλ\n    float Current_Limit;            //޷\n    float Velocity_Limit;            //ٶ޷\n    float Homing_Value;                //ִHomingֵ\n    float Position_Offset;            //ִλƫ\n    float Homing_Current_Limit_L;    //Զ\n    float Homing_Current_Limit_H;    //Զ\n    float Blocked_Energy;            //ת\n    /* ȡ־λ */\n    uint8_t R_Current_Real;\n    uint8_t R_Velocity_Real;\n    uint8_t R_Position_Real;\n    uint8_t R_Current_Filter_P;\n    uint8_t R_Current_Filter_I;\n    uint8_t R_Velocity_Filter_P;\n    uint8_t R_Velocity_Filter_I;\n    uint8_t R_Position_Filter_P;\n    uint8_t R_Position_Filter_I;\n    //uint8_t R_Position_Filter_D;\n    uint8_t R_PP_Max_Velocity;\n    uint8_t R_PP_Max_Acceleration;\n    uint8_t R_PP_Max_Deceleration;\n    uint8_t R_PV_Max_Velocity;\n    uint8_t R_PV_Max_Acceleration;\n    uint8_t R_PV_Max_Deceleration;\n    //uint8_t R_Current_Filter_Limit_L;\n    //uint8_t R_Current_Filter_Limit_H;\n    uint8_t R_Velocity_Filter_Limit_L;\n    uint8_t R_Velocity_Filter_Limit_H;\n    uint8_t R_Position_Filter_Limit_L;\n    uint8_t R_Position_Filter_Limit_H;\n    uint8_t R_Position_Limit_H;\n    uint8_t R_Position_Limit_L;\n    uint8_t R_Current_Limit;\n    uint8_t R_Velocity_Limit;\n    uint8_t R_Homing_Value;\n    uint8_t R_Position_Offset;\n    uint8_t R_Homing_Current_Limit_L;\n    uint8_t R_Homing_Current_Limit_H;\n    uint8_t R_Blocked_Energy;\n    uint8_t R_CVP;\n    uint8_t R_Serial_Num;\n    uint8_t W_ClearHome;\n\n} Para_Cache_t;\n\n/* \n\tSCAϢֵ\n\tݿɸĿҪвü\n */\ntypedef struct\n{\n    /* Эݱ */\n    uint8_t ID;                        //SCAID\n    uint8_t Serial_Num[4];            //к\n    uint8_t Save_State;                //״̬1Ϊѱ\n    uint8_t Online_State;            //ǰ״̬1Ϊ\n    uint8_t Update_State;            //Ƿвˢ£1Ϊвˢ\n    CAN_Handler_t *Can;                //ʹõCAN˿\n    Para_Cache_t paraCache;            //\n\n    /* ûݱ */\n\n    /* һݱ */\n    uint8_t Mode;                    //ǰģʽ\n    uint8_t Last_State;                //ϴιػ쳣״̬1Ϊ\n    uint8_t Current_Filter_State;    //˲״̬\n    uint8_t Velocity_Filter_State;    //ٶȻ˲״̬\n    uint8_t Position_Filter_State;    //ٶȻ˲״̬\n    uint8_t Position_Limit_State;    //λλ״̬\n    uint8_t Power_State;            //ػ״̬\n\n    /* ڶݱ */\n    float Voltage;                    //ǰѹλV\n    float Current_Max;                //\n    float Current_Filter_Value;        //˲\n    float Velocity_Filter_Value;    //ٶȻ˲\n    float Position_Filter_Value;    //λû˲\n    float Motor_Temp;                //¶\n    float Inverter_Temp;            //¶\n    float Inverter_Protect_Temp;    //¶\n    float Inverter_Recover_Temp;    //ָ¶\n    float Motor_Protect_Temp;        //¶\n    float Motor_Recover_Temp;        //ָ¶\n    SCA_Warn_t SCA_Warn;            //Ϣ\n\n    /* ݱ */\n    float Current_Real;                //ǰλA\n    float Velocity_Real;            //ǰٶȣλRPM\n    float Position_Real;            //ǰλãʵֵλR\n    float Current_Filter_P;            //Pֵ\n    float Current_Filter_I;            //Iֵ\n    float Velocity_Filter_P;        //ٶȻPֵ\n    float Velocity_Filter_I;        //ٶȻIֵ\n    float Position_Filter_P;        //λûPֵ\n    float Position_Filter_I;        //λûIֵ\n    //float Position_Filter_D;\t\t//λûDֵ\n    float PP_Max_Velocity;            //λٶֵ\n    float PP_Max_Acceleration;        //λμٶֵ\n    float PP_Max_Deceleration;        //λμٶֵ\n    float PV_Max_Velocity;            //ٶٶֵ\n    float PV_Max_Acceleration;        //ٶμٶֵ\n    float PV_Max_Deceleration;        //ٶμٶֵ\n    //float Current_Filter_Limit_L;\t//\n    //float Current_Filter_Limit_H;\t//\n    float Velocity_Filter_Limit_L;    //ٶȻ\n    float Velocity_Filter_Limit_H;    //ٶȻ\n    float Position_Filter_Limit_L;    //λû\n    float Position_Filter_Limit_H;    //λû\n    float Position_Limit_H;            //ִλ\n    float Position_Limit_L;            //ִλ\n    float Current_Limit;            //޷\n    float Velocity_Limit;            //ٶ޷\n    float Homing_Value;                //ִHomingֵ\n    float Position_Offset;            //ִλƫ\n    float Homing_Current_Limit_L;    //Զ\n    float Homing_Current_Limit_H;    //Զ\n    float Blocked_Energy;            //ת\n\n} SCA_Handler_t;\n\nenum SCA_Error                //SCAͨŴö\n{\n    SCA_NoError = 0,        //޴\n    SCA_OverTime,            //ͨŵȴʱ\n    SCA_SendError,            //ݷʧ\n    SCA_OperationFailed,    //ʧ\n    SCA_UnknownID,            //δҵIDִ\n};\n\n/* ݽսӿڣµCANݰʱ\n  CanRxMsg ΪCANݰĽͽṹֲʱ\n  ƽ̨CanRxMsgṹͣ˴ĬʹSTM32\n  ׼⺯еĽսṹ\t*/\ntypedef struct\n{\n    uint32_t StdId;  /*!< Specifies the standard identifier.\n                        This parameter can be a value between 0 to 0x7FF. */\n\n    uint32_t ExtId;  /*!< Specifies the extended identifier.\n                        This parameter can be a value between 0 to 0x1FFFFFFF. */\n\n    uint8_t IDE;     /*!< Specifies the type of identifier for the message that\n                        will be received. This parameter can be a value of\n                        @ref CAN_identifier_type */\n\n    uint8_t RTR;     /*!< Specifies the type of frame for the received message.\n                        This parameter can be a value of\n                        @ref CAN_remote_transmission_request */\n\n    uint8_t DLC;     /*!< Specifies the length of the frame that will be received.\n                        This parameter can be a value between 0 to 8 */\n\n    uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to\n                        0xFF. */\n\n    uint8_t FMI;     /*!< Specifies the index of the filter the message stored in\n                        the mailbox passes through. This parameter can be a\n                        value between 0 to 0xFF */\n} CanRxMsg;\n\nvoid canDispatch(CanRxMsg *RxMsg);\n\n/* ºΪAPI */\n\n/* ȡӿ */\nuint8_t SCA_Read(SCA_Handler_t *pSCA, uint8_t cmd);\n\n/* д */\nuint8_t SCA_Write_1(SCA_Handler_t *pSCA, uint8_t cmd, uint8_t TxData);\nuint8_t SCA_Write_2(SCA_Handler_t *pSCA, uint8_t cmd, float TxData);\nuint8_t SCA_Write_3(SCA_Handler_t *pSCA, uint8_t cmd, float TxData);\nuint8_t SCA_Write_4(SCA_Handler_t *pSCA, uint8_t cmd);\nuint8_t SCA_Write_5(SCA_Handler_t *pSCA, uint8_t cmd, uint8_t TxData);\n\n\n#ifdef __cplusplus\n}\n\n#endif\n#endif\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/algorithms/kinematic/6dof_kinematic.cpp",
    "content": "#include \"6dof_kinematic.h\"\r\n\r\ninline float cosf(float x)\r\n{\r\n    return arm_cos_f32(x);\r\n}\r\n\r\ninline float sinf(float x)\r\n{\r\n    return arm_sin_f32(x);\r\n}\r\n\r\nstatic void MatMultiply(const float* _matrix1, const float* _matrix2, float* _matrixOut,\r\n                        const int _m, const int _l, const int _n)\r\n{\r\n    float tmp;\r\n    int i, j, k;\r\n    for (i = 0; i < _m; i++)\r\n    {\r\n        for (j = 0; j < _n; j++)\r\n        {\r\n            tmp = 0.0f;\r\n            for (k = 0; k < _l; k++)\r\n            {\r\n                tmp += _matrix1[_l * i + k] * _matrix2[_n * k + j];\r\n            }\r\n            _matrixOut[_n * i + j] = tmp;\r\n        }\r\n    }\r\n}\r\n\r\nstatic void RotMatToEulerAngle(const float* _rotationM, float* _eulerAngles)\r\n{\r\n    float A, B, C, cb;\r\n\r\n    if (fabs(_rotationM[6]) >= 1.0 - 0.0001)\r\n    {\r\n        if (_rotationM[6] < 0)\r\n        {\r\n            A = 0.0f;\r\n            B = (float) M_PI_2;\r\n            C = atan2f(_rotationM[1], _rotationM[4]);\r\n        } else\r\n        {\r\n            A = 0.0f;\r\n            B = -(float) M_PI_2;\r\n            C = -atan2f(_rotationM[1], _rotationM[4]);\r\n        }\r\n    } else\r\n    {\r\n        B = atan2f(-_rotationM[6], sqrtf(_rotationM[0] * _rotationM[0] + _rotationM[3] * _rotationM[3]));\r\n        cb = cosf(B);\r\n        A = atan2f(_rotationM[3] / cb, _rotationM[0] / cb);\r\n        C = atan2f(_rotationM[7] / cb, _rotationM[8] / cb);\r\n    }\r\n\r\n    _eulerAngles[0] = C;\r\n    _eulerAngles[1] = B;\r\n    _eulerAngles[2] = A;\r\n}\r\n\r\nstatic void EulerAngleToRotMat(const float* _eulerAngles, float* _rotationM)\r\n{\r\n    float ca, cb, cc, sa, sb, sc;\r\n\r\n    cc = cosf(_eulerAngles[0]);\r\n    cb = cosf(_eulerAngles[1]);\r\n    ca = cosf(_eulerAngles[2]);\r\n    sc = sinf(_eulerAngles[0]);\r\n    sb = sinf(_eulerAngles[1]);\r\n    sa = sinf(_eulerAngles[2]);\r\n\r\n    _rotationM[0] = ca * cb;\r\n    _rotationM[1] = ca * sb * sc - sa * cc;\r\n    _rotationM[2] = ca * sb * cc + sa * sc;\r\n    _rotationM[3] = sa * cb;\r\n    _rotationM[4] = sa * sb * sc + ca * cc;\r\n    _rotationM[5] = sa * sb * cc - ca * sc;\r\n    _rotationM[6] = -sb;\r\n    _rotationM[7] = cb * sc;\r\n    _rotationM[8] = cb * cc;\r\n}\r\n\r\n\r\nDOF6Kinematic::DOF6Kinematic(float L_BS, float D_BS, float L_AM, float L_FA, float D_EW, float L_WT)\r\n    : armConfig(ArmConfig_t{L_BS, D_BS, L_AM, L_FA, D_EW, L_WT})\r\n{\r\n    float tmp_DH_matrix[6][4] = {\r\n        {0.0f,            armConfig.L_BASE,    armConfig.D_BASE, -(float) M_PI_2},\r\n        {-(float) M_PI_2, 0.0f,                armConfig.L_ARM,  0.0f},\r\n        {(float) M_PI_2,  armConfig.D_ELBOW,   0.0f,             (float) M_PI_2},\r\n        {0.0f,            armConfig.L_FOREARM, 0.0f,             -(float) M_PI_2},\r\n        {0.0f,            0.0f,                0.0f,             (float) M_PI_2},\r\n        {0.0f,            armConfig.L_WRIST, 0.0f, 0.0f}\r\n    };\r\n    memcpy(DH_matrix, tmp_DH_matrix, sizeof(tmp_DH_matrix));\r\n\r\n    float tmp_L1_bs[3] = {armConfig.D_BASE, -armConfig.L_BASE, 0.0f};\r\n    memcpy(L1_base, tmp_L1_bs, sizeof(tmp_L1_bs));\r\n    float tmp_L2_se[3] = {armConfig.L_ARM, 0.0f, 0.0f};\r\n    memcpy(L2_arm, tmp_L2_se, sizeof(tmp_L2_se));\r\n    float tmp_L3_ew[3] = {-armConfig.D_ELBOW, 0.0f, armConfig.L_FOREARM};\r\n    memcpy(L3_elbow, tmp_L3_ew, sizeof(tmp_L3_ew));\r\n    float tmp_L6_wt[3] = {0.0f, 0.0f, armConfig.L_WRIST};\r\n    memcpy(L6_wrist, tmp_L6_wt, sizeof(tmp_L6_wt));\r\n\r\n    l_se_2 = armConfig.L_ARM * armConfig.L_ARM;\r\n    l_se = armConfig.L_ARM;\r\n    l_ew_2 = armConfig.L_FOREARM * armConfig.L_FOREARM + armConfig.D_ELBOW * armConfig.D_ELBOW;\r\n    l_ew = 0;\r\n    atan_e = 0;\r\n}\r\n\r\nbool\r\nDOF6Kinematic::SolveFK(const DOF6Kinematic::Joint6D_t &_inputJoint6D, DOF6Kinematic::Pose6D_t &_outputPose6D)\r\n{\r\n    float q_in[6];\r\n    float q[6];\r\n    float cosq, sinq;\r\n    float cosa, sina;\r\n    float P06[6];\r\n    float R06[9];\r\n    float R[6][9];\r\n    float R02[9];\r\n    float R03[9];\r\n    float R04[9];\r\n    float R05[9];\r\n    float L0_bs[3];\r\n    float L0_se[3];\r\n    float L0_ew[3];\r\n    float L0_wt[3];\r\n\r\n    for (int i = 0; i < 6; i++)\r\n        q_in[i] = _inputJoint6D.a[i] / RAD_TO_DEG;\r\n\r\n    for (int i = 0; i < 6; i++)\r\n    {\r\n        q[i] = q_in[i] + DH_matrix[i][0];\r\n        cosq = cosf(q[i]);\r\n        sinq = sinf(q[i]);\r\n        cosa = cosf(DH_matrix[i][3]);\r\n        sina = sinf(DH_matrix[i][3]);\r\n\r\n        R[i][0] = cosq;\r\n        R[i][1] = -cosa * sinq;\r\n        R[i][2] = sina * sinq;\r\n        R[i][3] = sinq;\r\n        R[i][4] = cosa * cosq;\r\n        R[i][5] = -sina * cosq;\r\n        R[i][6] = 0.0f;\r\n        R[i][7] = sina;\r\n        R[i][8] = cosa;\r\n    }\r\n\r\n    MatMultiply(R[0], R[1], R02, 3, 3, 3);\r\n    MatMultiply(R02, R[2], R03, 3, 3, 3);\r\n    MatMultiply(R03, R[3], R04, 3, 3, 3);\r\n    MatMultiply(R04, R[4], R05, 3, 3, 3);\r\n    MatMultiply(R05, R[5], R06, 3, 3, 3);\r\n\r\n    MatMultiply(R[0], L1_base, L0_bs, 3, 3, 1);\r\n    MatMultiply(R02, L2_arm, L0_se, 3, 3, 1);\r\n    MatMultiply(R03, L3_elbow, L0_ew, 3, 3, 1);\r\n    MatMultiply(R06, L6_wrist, L0_wt, 3, 3, 1);\r\n\r\n    for (int i = 0; i < 3; i++)\r\n        P06[i] = L0_bs[i] + L0_se[i] + L0_ew[i] + L0_wt[i];\r\n\r\n    RotMatToEulerAngle(R06, &(P06[3]));\r\n\r\n    _outputPose6D.X = P06[0];\r\n    _outputPose6D.Y = P06[1];\r\n    _outputPose6D.Z = P06[2];\r\n    _outputPose6D.A = P06[3] * RAD_TO_DEG;\r\n    _outputPose6D.B = P06[4] * RAD_TO_DEG;\r\n    _outputPose6D.C = P06[5] * RAD_TO_DEG;\r\n    memcpy(_outputPose6D.R, R06, 9 * sizeof(float));\r\n\r\n    return true;\r\n}\r\n\r\nbool DOF6Kinematic::SolveIK(const DOF6Kinematic::Pose6D_t &_inputPose6D, const Joint6D_t &_lastJoint6D,\r\n                            DOF6Kinematic::IKSolves_t &_outputSolves)\r\n{\r\n    float qs[2];\r\n    float qa[2][2];\r\n    float qw[2][3];\r\n    float cosqs, sinqs;\r\n    float cosqa[2], sinqa[2];\r\n    float cosqw, sinqw;\r\n    float P06[6];\r\n    float R06[9];\r\n    float P0_w[3];\r\n    float P1_w[3];\r\n    float L0_wt[3];\r\n    float L1_sw[3];\r\n    float R10[9];\r\n    float R31[9];\r\n    float R30[9];\r\n    float R36[9];\r\n    float l_sw_2, l_sw, atan_a, acos_a, acos_e;\r\n\r\n    int ind_arm, ind_elbow, ind_wrist;\r\n    int i;\r\n\r\n    if (0 == l_ew)\r\n    {\r\n        l_ew = sqrtf(l_ew_2);\r\n        atan_e = atanf(armConfig.D_ELBOW / armConfig.L_FOREARM);\r\n    }\r\n\r\n    P06[0] = _inputPose6D.X / 1000.0f;\r\n    P06[1] = _inputPose6D.Y / 1000.0f;\r\n    P06[2] = _inputPose6D.Z / 1000.0f;\r\n    if (!_inputPose6D.hasR)\r\n    {\r\n        P06[3] = _inputPose6D.A / RAD_TO_DEG;\r\n        P06[4] = _inputPose6D.B / RAD_TO_DEG;\r\n        P06[5] = _inputPose6D.C / RAD_TO_DEG;\r\n        EulerAngleToRotMat(&(P06[3]), R06);\r\n    } else\r\n    {\r\n        memcpy(R06, _inputPose6D.R, 9 * sizeof(float));\r\n    }\r\n    for (i = 0; i < 2; i++)\r\n    {\r\n        qs[i] = _lastJoint6D.a[0];\r\n        qa[i][0] = _lastJoint6D.a[1];\r\n        qa[i][1] = _lastJoint6D.a[2];\r\n        qw[i][0] = _lastJoint6D.a[3];\r\n        qw[i][1] = _lastJoint6D.a[4];\r\n        qw[i][2] = _lastJoint6D.a[5];\r\n    }\r\n    MatMultiply(R06, L6_wrist, L0_wt, 3, 3, 1);\r\n    for (i = 0; i < 3; i++)\r\n    {\r\n        P0_w[i] = P06[i] - L0_wt[i];\r\n    }\r\n    if (sqrt(P0_w[0] * P0_w[0] + P0_w[1] * P0_w[1]) <= 0.000001)\r\n    {\r\n        qs[0] = _lastJoint6D.a[0];\r\n        qs[1] = _lastJoint6D.a[0];\r\n        for (i = 0; i < 4; i++)\r\n        {\r\n            _outputSolves.solFlag[0 + i][0] = -1;\r\n            _outputSolves.solFlag[4 + i][0] = -1;\r\n        }\r\n    } else\r\n    {\r\n        qs[0] = atan2f(P0_w[1], P0_w[0]);\r\n        qs[1] = atan2f(-P0_w[1], -P0_w[0]);\r\n        for (i = 0; i < 4; i++)\r\n        {\r\n            _outputSolves.solFlag[0 + i][0] = 1;\r\n            _outputSolves.solFlag[4 + i][0] = 1;\r\n        }\r\n    }\r\n    for (ind_arm = 0; ind_arm < 2; ind_arm++)\r\n    {\r\n        cosqs = cosf(qs[ind_arm] + DH_matrix[0][0]);\r\n        sinqs = sinf(qs[ind_arm] + DH_matrix[0][0]);\r\n\r\n        R10[0] = cosqs;\r\n        R10[1] = sinqs;\r\n        R10[2] = 0.0f;\r\n        R10[3] = 0.0f;\r\n        R10[4] = 0.0f;\r\n        R10[5] = -1.0f;\r\n        R10[6] = -sinqs;\r\n        R10[7] = cosqs;\r\n        R10[8] = 0.0f;\r\n\r\n        MatMultiply(R10, P0_w, P1_w, 3, 3, 1);\r\n        for (i = 0; i < 3; i++)\r\n        {\r\n            L1_sw[i] = P1_w[i] - L1_base[i];\r\n        }\r\n        l_sw_2 = L1_sw[0] * L1_sw[0] + L1_sw[1] * L1_sw[1];\r\n        l_sw = sqrtf(l_sw_2);\r\n\r\n        if (fabs(l_se + l_ew - l_sw) <= 0.000001)\r\n        {\r\n            qa[0][0] = atan2f(L1_sw[1], L1_sw[0]);\r\n            qa[1][0] = qa[0][0];\r\n            qa[0][1] = 0.0f;\r\n            qa[1][1] = 0.0f;\r\n            if (l_sw > l_se + l_ew)\r\n            {\r\n                for (i = 0; i < 2; i++)\r\n                {\r\n                    _outputSolves.solFlag[4 * ind_arm + 0 + i][1] = 0;\r\n                    _outputSolves.solFlag[4 * ind_arm + 2 + i][1] = 0;\r\n                }\r\n            } else\r\n            {\r\n                for (i = 0; i < 2; i++)\r\n                {\r\n                    _outputSolves.solFlag[4 * ind_arm + 0 + i][1] = 1;\r\n                    _outputSolves.solFlag[4 * ind_arm + 2 + i][1] = 1;\r\n                }\r\n            }\r\n        } else if (fabs(l_sw - fabs(l_se - l_ew)) <= 0.000001)\r\n        {\r\n            qa[0][0] = atan2f(L1_sw[1], L1_sw[0]);\r\n            qa[1][0] = qa[0][0];\r\n            if (0 == ind_arm)\r\n            {\r\n                qa[0][1] = (float) M_PI;\r\n                qa[1][1] = -(float) M_PI;\r\n            } else\r\n            {\r\n                qa[0][1] = -(float) M_PI;\r\n                qa[1][1] = (float) M_PI;\r\n            }\r\n            if (l_sw < fabs(l_se - l_ew))\r\n            {\r\n                for (i = 0; i < 2; i++)\r\n                {\r\n                    _outputSolves.solFlag[4 * ind_arm + 0 + i][1] = 0;\r\n                    _outputSolves.solFlag[4 * ind_arm + 2 + i][1] = 0;\r\n                }\r\n            } else\r\n            {\r\n                for (i = 0; i < 2; i++)\r\n                {\r\n                    _outputSolves.solFlag[4 * ind_arm + 0 + i][1] = 1;\r\n                    _outputSolves.solFlag[4 * ind_arm + 2 + i][1] = 1;\r\n                }\r\n            }\r\n        } else\r\n        {\r\n            atan_a = atan2f(L1_sw[1], L1_sw[0]);\r\n            acos_a = 0.5f * (l_se_2 + l_sw_2 - l_ew_2) / (l_se * l_sw);\r\n            if (acos_a >= 1.0f) acos_a = 0.0f;\r\n            else if (acos_a <= -1.0f) acos_a = (float) M_PI;\r\n            else acos_a = acosf(acos_a);\r\n            acos_e = 0.5f * (l_se_2 + l_ew_2 - l_sw_2) / (l_se * l_ew);\r\n            if (acos_e >= 1.0f) acos_e = 0.0f;\r\n            else if (acos_e <= -1.0f) acos_e = (float) M_PI;\r\n            else acos_e = acosf(acos_e);\r\n            if (0 == ind_arm)\r\n            {\r\n                qa[0][0] = atan_a - acos_a + (float) M_PI_2;\r\n                qa[0][1] = atan_e - acos_e + (float) M_PI;\r\n                qa[1][0] = atan_a + acos_a + (float) M_PI_2;\r\n                qa[1][1] = atan_e + acos_e - (float) M_PI;\r\n\r\n            } else\r\n            {\r\n                qa[0][0] = atan_a + acos_a + (float) M_PI_2;\r\n                qa[0][1] = atan_e + acos_e - (float) M_PI;\r\n                qa[1][0] = atan_a - acos_a + (float) M_PI_2;\r\n                qa[1][1] = atan_e - acos_e + (float) M_PI;\r\n            }\r\n            for (i = 0; i < 2; i++)\r\n            {\r\n                _outputSolves.solFlag[4 * ind_arm + 0 + i][1] = 1;\r\n                _outputSolves.solFlag[4 * ind_arm + 2 + i][1] = 1;\r\n            }\r\n        }\r\n        for (ind_elbow = 0; ind_elbow < 2; ind_elbow++)\r\n        {\r\n            cosqa[0] = cosf(qa[ind_elbow][0] + DH_matrix[1][0]);\r\n            sinqa[0] = sinf(qa[ind_elbow][0] + DH_matrix[1][0]);\r\n            cosqa[1] = cosf(qa[ind_elbow][1] + DH_matrix[2][0]);\r\n            sinqa[1] = sinf(qa[ind_elbow][1] + DH_matrix[2][0]);\r\n\r\n            R31[0] = cosqa[0] * cosqa[1] - sinqa[0] * sinqa[1];\r\n            R31[1] = cosqa[0] * sinqa[1] + sinqa[0] * cosqa[1];\r\n            R31[2] = 0.0f;\r\n            R31[3] = 0.0f;\r\n            R31[4] = 0.0f;\r\n            R31[5] = 1.0f;\r\n            R31[6] = cosqa[0] * sinqa[1] + sinqa[0] * cosqa[1];\r\n            R31[7] = -cosqa[0] * cosqa[1] + sinqa[0] * sinqa[1];\r\n            R31[8] = 0.0f;\r\n\r\n            MatMultiply(R31, R10, R30, 3, 3, 3);\r\n            MatMultiply(R30, R06, R36, 3, 3, 3);\r\n\r\n            if (R36[8] >= 1.0 - 0.000001)\r\n            {\r\n                cosqw = 1.0f;\r\n                qw[0][1] = 0.0f;\r\n                qw[1][1] = 0.0f;\r\n            } else if (R36[8] <= -1.0 + 0.000001)\r\n            {\r\n                cosqw = -1.0f;\r\n                if (0 == ind_arm)\r\n                {\r\n                    qw[0][1] = (float) M_PI;\r\n                    qw[1][1] = -(float) M_PI;\r\n                } else\r\n                {\r\n                    qw[0][1] = -(float) M_PI;\r\n                    qw[1][1] = (float) M_PI;\r\n                }\r\n            } else\r\n            {\r\n                cosqw = R36[8];\r\n                if (0 == ind_arm)\r\n                {\r\n                    qw[0][1] = acosf(cosqw);\r\n                    qw[1][1] = -acosf(cosqw);\r\n                } else\r\n                {\r\n                    qw[0][1] = -acosf(cosqw);\r\n                    qw[1][1] = acosf(cosqw);\r\n                }\r\n            }\r\n            if (1.0f == cosqw || -1.0f == cosqw)\r\n            {\r\n                if (0 == ind_arm)\r\n                {\r\n                    qw[0][0] = _lastJoint6D.a[3];\r\n                    cosqw = cosf(_lastJoint6D.a[3] + DH_matrix[3][0]);\r\n                    sinqw = sinf(_lastJoint6D.a[3] + DH_matrix[3][0]);\r\n                    qw[0][2] = atan2f(cosqw * R36[3] - sinqw * R36[0], cosqw * R36[0] + sinqw * R36[3]);\r\n                    qw[1][2] = _lastJoint6D.a[5];\r\n                    cosqw = cosf(_lastJoint6D.a[5] + DH_matrix[5][0]);\r\n                    sinqw = sinf(_lastJoint6D.a[5] + DH_matrix[5][0]);\r\n                    qw[1][0] = atan2f(cosqw * R36[3] - sinqw * R36[0], cosqw * R36[0] + sinqw * R36[3]);\r\n                } else\r\n                {\r\n                    qw[0][2] = _lastJoint6D.a[5];\r\n                    cosqw = cosf(_lastJoint6D.a[5] + DH_matrix[5][0]);\r\n                    sinqw = sinf(_lastJoint6D.a[5] + DH_matrix[5][0]);\r\n                    qw[0][0] = atan2f(cosqw * R36[3] - sinqw * R36[0], cosqw * R36[0] + sinqw * R36[3]);\r\n                    qw[1][0] = _lastJoint6D.a[3];\r\n                    cosqw = cosf(_lastJoint6D.a[3] + DH_matrix[3][0]);\r\n                    sinqw = sinf(_lastJoint6D.a[3] + DH_matrix[3][0]);\r\n                    qw[1][2] = atan2f(cosqw * R36[3] - sinqw * R36[0], cosqw * R36[0] + sinqw * R36[3]);\r\n                }\r\n                _outputSolves.solFlag[4 * ind_arm + 2 * ind_elbow + 0][2] = -1;\r\n                _outputSolves.solFlag[4 * ind_arm + 2 * ind_elbow + 1][2] = -1;\r\n            } else\r\n            {\r\n                if (0 == ind_arm)\r\n                {\r\n                    qw[0][0] = atan2f(R36[5], R36[2]);\r\n                    qw[1][0] = atan2f(-R36[5], -R36[2]);\r\n                    qw[0][2] = atan2f(R36[7], -R36[6]);\r\n                    qw[1][2] = atan2f(-R36[7], R36[6]);\r\n                } else\r\n                {\r\n                    qw[0][0] = atan2f(-R36[5], -R36[2]);\r\n                    qw[1][0] = atan2f(R36[5], R36[2]);\r\n                    qw[0][2] = atan2f(-R36[7], R36[6]);\r\n                    qw[1][2] = atan2f(R36[7], -R36[6]);\r\n                }\r\n                _outputSolves.solFlag[4 * ind_arm + 2 * ind_elbow + 0][2] = 1;\r\n                _outputSolves.solFlag[4 * ind_arm + 2 * ind_elbow + 1][2] = 1;\r\n            }\r\n            for (ind_wrist = 0; ind_wrist < 2; ind_wrist++)\r\n            {\r\n                if (qs[ind_arm] > (float) M_PI)\r\n                    _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[0] =\r\n                        qs[ind_arm] - (float) M_PI;\r\n                else if (qs[ind_arm] < -(float) M_PI)\r\n                    _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[0] =\r\n                        qs[ind_arm] + (float) M_PI;\r\n                else\r\n                    _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[0] = qs[ind_arm];\r\n\r\n                for (i = 0; i < 2; i++)\r\n                {\r\n                    if (qa[ind_elbow][i] > (float) M_PI)\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[1 + i] =\r\n                            qa[ind_elbow][i] - (float) M_PI;\r\n                    else if (qa[ind_elbow][i] < -(float) M_PI)\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[1 + i] =\r\n                            qa[ind_elbow][i] + (float) M_PI;\r\n                    else\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[1 + i] =\r\n                            qa[ind_elbow][i];\r\n                }\r\n\r\n                for (i = 0; i < 3; i++)\r\n                {\r\n                    if (qw[ind_wrist][i] > (float) M_PI)\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[3 + i] =\r\n                            qw[ind_wrist][i] - (float) M_PI;\r\n                    else if (qw[ind_wrist][i] < -(float) M_PI)\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[3 + i] =\r\n                            qw[ind_wrist][i] + (float) M_PI;\r\n                    else\r\n                        _outputSolves.config[4 * ind_arm + 2 * ind_elbow + ind_wrist].a[3 + i] =\r\n                            qw[ind_wrist][i];\r\n                }\r\n            }\r\n        }\r\n    }\r\n\r\n    for (i = 0; i < 8; i++)\r\n        for (float &j: _outputSolves.config[i].a)\r\n            j *= RAD_TO_DEG;\r\n\r\n    return true;\r\n}\r\n\r\nDOF6Kinematic::Joint6D_t\r\noperator-(const DOF6Kinematic::Joint6D_t &_joints1, const DOF6Kinematic::Joint6D_t &_joints2)\r\n{\r\n    DOF6Kinematic::Joint6D_t tmp{};\r\n    for (int i = 0; i < 6; i++)\r\n        tmp.a[i] = _joints1.a[i] - _joints2.a[i];\r\n\r\n    return tmp;\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/algorithms/kinematic/6dof_kinematic.h",
    "content": "#ifndef DOF6_KINEMATIC_SOLVER_H\r\n#define DOF6_KINEMATIC_SOLVER_H\r\n\r\n#include \"stm32f405xx.h\"\r\n#include \"arm_math.h\"\r\n#include \"memory.h\"\r\n\r\nclass DOF6Kinematic\r\n{\r\nprivate:\r\n    const float RAD_TO_DEG = 57.295777754771045f;\r\n\r\n    // DH parameters\r\n    struct ArmConfig_t\r\n    {\r\n        float L_BASE;\r\n        float D_BASE;\r\n        float L_ARM;\r\n        float L_FOREARM;\r\n        float D_ELBOW;\r\n        float L_WRIST;\r\n    };\r\n    ArmConfig_t armConfig;\r\n\r\n    float DH_matrix[6][4] = {0}; // home,d,a,alpha\r\n    float L1_base[3] = {0};\r\n    float L2_arm[3] = {0};\r\n    float L3_elbow[3] = {0};\r\n    float L6_wrist[3] = {0};\r\n\r\n    float l_se_2;\r\n    float l_se;\r\n    float l_ew_2;\r\n    float l_ew;\r\n    float atan_e;\r\n\r\npublic:\r\n    struct Joint6D_t\r\n    {\r\n        Joint6D_t()\r\n        = default;\r\n\r\n        Joint6D_t(float a1, float a2, float a3, float a4, float a5, float a6)\r\n            : a{a1, a2, a3, a4, a5, a6}\r\n        {}\r\n\r\n        float a[6];\r\n\r\n        friend Joint6D_t operator-(const Joint6D_t &_joints1, const Joint6D_t &_joints2);\r\n    };\r\n\r\n    struct Pose6D_t\r\n    {\r\n        Pose6D_t()\r\n        = default;\r\n\r\n        Pose6D_t(float x, float y, float z, float a, float b, float c)\r\n            : X(x), Y(y), Z(z), A(a), B(b), C(c), hasR(false)\r\n        {}\r\n\r\n        float X{}, Y{}, Z{};\r\n        float A{}, B{}, C{};\r\n        float R[9]{};\r\n\r\n        // if Pose was calculated by FK then it's true automatically (so that no need to do extra calc),\r\n        // otherwise if manually set params then it should be set to false.\r\n        bool hasR{};\r\n    };\r\n\r\n    struct IKSolves_t\r\n    {\r\n        Joint6D_t config[8];\r\n        char solFlag[8][3];\r\n    };\r\n\r\n    DOF6Kinematic(float L_BS, float D_BS, float L_AM, float L_FA, float D_EW, float L_WT);\r\n\r\n    bool SolveFK(const Joint6D_t &_inputJoint6D, Pose6D_t &_outputPose6D);\r\n\r\n    bool SolveIK(const Pose6D_t &_inputPose6D, const Joint6D_t &_lastJoint6D, IKSolves_t &_outputSolves);\r\n};\r\n\r\n#endif //DOF6_KINEMATIC_SOLVER_H\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/instances/dummy_robot.cpp",
    "content": "#include \"communication.hpp\"\r\n#include \"dummy_robot.h\"\r\n\r\ninline float AbsMaxOf6(DOF6Kinematic::Joint6D_t _joints, uint8_t &_index)\r\n{\r\n    float max = -1;\r\n    for (uint8_t i = 0; i < 6; i++)\r\n    {\r\n        if (abs(_joints.a[i]) > max)\r\n        {\r\n            max = abs(_joints.a[i]);\r\n            _index = i;\r\n        }\r\n    }\r\n\r\n    return max;\r\n}\r\n\r\n\r\nDummyRobot::DummyRobot(CAN_HandleTypeDef* _hcan) :\r\n    hcan(_hcan)\r\n{\r\n    motorJ[ALL] = new CtrlStepMotor(_hcan, 0, false, 1, -180, 180);\r\n    motorJ[1] = new CtrlStepMotor(_hcan, 1, true, 50, -170, 170);\r\n    motorJ[2] = new CtrlStepMotor(_hcan, 2, false, 30, -73, 90);\r\n    motorJ[3] = new CtrlStepMotor(_hcan, 3, true, 30, 35, 180);\r\n    motorJ[4] = new CtrlStepMotor(_hcan, 4, false, 24, -180, 180);\r\n    motorJ[5] = new CtrlStepMotor(_hcan, 5, true, 30, -120, 120);\r\n    motorJ[6] = new CtrlStepMotor(_hcan, 6, true, 50, -720, 720);\r\n    hand = new DummyHand(_hcan, 7);\r\n\r\n    dof6Solver = new DOF6Kinematic(0.109f, 0.035f, 0.146f, 0.115f, 0.052f, 0.072f);\r\n}\r\n\r\n\r\nDummyRobot::~DummyRobot()\r\n{\r\n    for (int j = 0; j <= 6; j++)\r\n        delete motorJ[j];\r\n\r\n    delete hand;\r\n    delete dof6Solver;\r\n}\r\n\r\n\r\nvoid DummyRobot::Init()\r\n{\r\n    SetCommandMode(DEFAULT_COMMAND_MODE);\r\n    SetJointSpeed(DEFAULT_JOINT_SPEED);\r\n}\r\n\r\n\r\nvoid DummyRobot::Reboot()\r\n{\r\n    motorJ[ALL]->Reboot();\r\n    osDelay(500); // waiting for all joints done\r\n    HAL_NVIC_SystemReset();\r\n}\r\n\r\n\r\nvoid DummyRobot::MoveJoints(DOF6Kinematic::Joint6D_t _joints)\r\n{\r\n    for (int j = 1; j <= 6; j++)\r\n    {\r\n        motorJ[j]->SetAngleWithVelocityLimit(_joints.a[j - 1] - initPose.a[j - 1],\r\n                                             dynamicJointSpeeds.a[j - 1]);\r\n    }\r\n}\r\n\r\n\r\nbool DummyRobot::MoveJ(float _j1, float _j2, float _j3, float _j4, float _j5, float _j6)\r\n{\r\n    DOF6Kinematic::Joint6D_t targetJointsTmp(_j1, _j2, _j3, _j4, _j5, _j6);\r\n    bool valid = true;\r\n\r\n    for (int j = 1; j <= 6; j++)\r\n    {\r\n        if (targetJointsTmp.a[j - 1] > motorJ[j]->angleLimitMax ||\r\n            targetJointsTmp.a[j - 1] < motorJ[j]->angleLimitMin)\r\n            valid = false;\r\n    }\r\n\r\n    if (valid)\r\n    {\r\n        DOF6Kinematic::Joint6D_t deltaJoints = targetJointsTmp - currentJoints;\r\n        uint8_t index;\r\n        float maxAngle = AbsMaxOf6(deltaJoints, index);\r\n        float time = maxAngle * (float) (motorJ[index + 1]->reduction) / jointSpeed;\r\n        for (int j = 1; j <= 6; j++)\r\n        {\r\n            dynamicJointSpeeds.a[j - 1] =\r\n                abs(deltaJoints.a[j - 1] * (float) (motorJ[j]->reduction) / time * 0.1f); //0~10r/s\r\n        }\r\n\r\n        jointsStateFlag = 0;\r\n        targetJoints = targetJointsTmp;\r\n\r\n        return true;\r\n    }\r\n\r\n    return false;\r\n}\r\n\r\n\r\nbool DummyRobot::MoveL(float _x, float _y, float _z, float _a, float _b, float _c)\r\n{\r\n    DOF6Kinematic::Pose6D_t pose6D(_x, _y, _z, _a, _b, _c);\r\n    DOF6Kinematic::IKSolves_t ikSolves{};\r\n    DOF6Kinematic::Joint6D_t lastJoint6D{};\r\n\r\n    dof6Solver->SolveIK(pose6D, lastJoint6D, ikSolves);\r\n\r\n    bool valid[8];\r\n    int validCnt = 0;\r\n\r\n    for (int i = 0; i < 8; i++)\r\n    {\r\n        valid[i] = true;\r\n\r\n        for (int j = 1; j <= 6; j++)\r\n        {\r\n            if (ikSolves.config[i].a[j - 1] > motorJ[j]->angleLimitMax ||\r\n                ikSolves.config[i].a[j - 1] < motorJ[j]->angleLimitMin)\r\n            {\r\n                valid[i] = false;\r\n                continue;\r\n            }\r\n        }\r\n\r\n        if (valid[i]) validCnt++;\r\n    }\r\n\r\n    if (validCnt)\r\n    {\r\n        float min = 1000;\r\n        uint8_t indexConfig = 0, indexJoint = 0;\r\n        for (int i = 0; i < 8; i++)\r\n        {\r\n            if (valid[i])\r\n            {\r\n                for (int j = 0; j < 6; j++)\r\n                    lastJoint6D.a[j] = ikSolves.config[i].a[j];\r\n                DOF6Kinematic::Joint6D_t tmp = currentJoints - lastJoint6D;\r\n                float maxAngle = AbsMaxOf6(tmp, indexJoint);\r\n                if (maxAngle < min)\r\n                {\r\n                    min = maxAngle;\r\n                    indexConfig = i;\r\n                }\r\n            }\r\n        }\r\n\r\n        return MoveJ(ikSolves.config[indexConfig].a[0], ikSolves.config[indexConfig].a[1],\r\n                     ikSolves.config[indexConfig].a[2], ikSolves.config[indexConfig].a[3],\r\n                     ikSolves.config[indexConfig].a[4], ikSolves.config[indexConfig].a[5]);\r\n    }\r\n\r\n    return false;\r\n}\r\n\r\nvoid DummyRobot::UpdateJointAngles()\r\n{\r\n    motorJ[ALL]->UpdateAngle();\r\n}\r\n\r\n\r\nvoid DummyRobot::UpdateJointAnglesCallback()\r\n{\r\n    for (int i = 1; i <= 6; i++)\r\n    {\r\n        currentJoints.a[i - 1] = motorJ[i]->angle + initPose.a[i - 1];\r\n\r\n        if (motorJ[i]->state == CtrlStepMotor::FINISH)\r\n            jointsStateFlag |= (1 << i);\r\n        else\r\n            jointsStateFlag &= ~(1 << i);\r\n    }\r\n}\r\n\r\n\r\nvoid DummyRobot::SetJointSpeed(float _speed)\r\n{\r\n    if (_speed < 0)_speed = 0;\r\n    else if (_speed > 100) _speed = 100;\r\n\r\n    jointSpeed = _speed * jointSpeedRatio;\r\n}\r\n\r\n\r\nvoid DummyRobot::SetJointAcceleration(float _acc)\r\n{\r\n    if (_acc < 0)_acc = 0;\r\n    else if (_acc > 100) _acc = 100;\r\n\r\n    for (int i = 1; i <= 6; i++)\r\n        motorJ[i]->SetAcceleration(_acc / 100 * DEFAULT_JOINT_ACCELERATION_BASES.a[i - 1]);\r\n}\r\n\r\n\r\nvoid DummyRobot::CalibrateHomeOffset()\r\n{\r\n    // Disable FixUpdate, but not disable motors\r\n    isEnabled = false;\r\n    motorJ[ALL]->SetEnable(true);\r\n\r\n    // 1.Manually move joints to L-Pose [precisely]\r\n    // ...\r\n    motorJ[2]->SetCurrentLimit(0.5);\r\n    motorJ[3]->SetCurrentLimit(0.5);\r\n    osDelay(500);\r\n\r\n    // 2.Apply Home-Offset the first time\r\n    motorJ[ALL]->ApplyPositionAsHome();\r\n    osDelay(500);\r\n\r\n    // 3.Go to Resting-Pose\r\n    initPose = DOF6Kinematic::Joint6D_t(0, 0, 90, 0, 0, 0);\r\n    currentJoints = DOF6Kinematic::Joint6D_t(0, 0, 90, 0, 0, 0);\r\n    Resting();\r\n    osDelay(500);\r\n\r\n    // 4.Apply Home-Offset the second time\r\n    motorJ[ALL]->ApplyPositionAsHome();\r\n    osDelay(500);\r\n    motorJ[2]->SetCurrentLimit(1);\r\n    motorJ[3]->SetCurrentLimit(1);\r\n    osDelay(500);\r\n\r\n    Reboot();\r\n}\r\n\r\n\r\nvoid DummyRobot::Homing()\r\n{\r\n    float lastSpeed = jointSpeed;\r\n    SetJointSpeed(10);\r\n\r\n    MoveJ(0, 0, 90, 0, 0, 0);\r\n    MoveJoints(targetJoints);\r\n    while (IsMoving())\r\n        osDelay(10);\r\n\r\n    SetJointSpeed(lastSpeed);\r\n}\r\n\r\n\r\nvoid DummyRobot::Resting()\r\n{\r\n    float lastSpeed = jointSpeed;\r\n    SetJointSpeed(10);\r\n\r\n    MoveJ(REST_POSE.a[0], REST_POSE.a[1], REST_POSE.a[2],\r\n          REST_POSE.a[3], REST_POSE.a[4], REST_POSE.a[5]);\r\n    MoveJoints(targetJoints);\r\n    while (IsMoving())\r\n        osDelay(10);\r\n\r\n    SetJointSpeed(lastSpeed);\r\n}\r\n\r\n\r\nvoid DummyRobot::SetEnable(bool _enable)\r\n{\r\n    motorJ[ALL]->SetEnable(_enable);\r\n    isEnabled = _enable;\r\n}\r\n\r\n\r\nvoid DummyRobot::UpdateJointPose6D()\r\n{\r\n    dof6Solver->SolveFK(currentJoints, currentPose6D);\r\n    currentPose6D.X *= 1000; // m -> mm\r\n    currentPose6D.Y *= 1000; // m -> mm\r\n    currentPose6D.Z *= 1000; // m -> mm\r\n}\r\n\r\n\r\nbool DummyRobot::IsMoving()\r\n{\r\n    return jointsStateFlag != 0b1111110;\r\n}\r\n\r\n\r\nbool DummyRobot::IsEnabled()\r\n{\r\n    return isEnabled;\r\n}\r\n\r\n\r\nvoid DummyRobot::SetCommandMode(uint32_t _mode)\r\n{\r\n    if (_mode < COMMAND_TARGET_POINT_SEQUENTIAL ||\r\n        _mode > COMMAND_MOTOR_TUNING)\r\n        return;\r\n\r\n    commandMode = static_cast<CommandMode>(_mode);\r\n\r\n    switch (commandMode)\r\n    {\r\n        case COMMAND_TARGET_POINT_SEQUENTIAL:\r\n        case COMMAND_TARGET_POINT_INTERRUPTABLE:\r\n            jointSpeedRatio = 1;\r\n            SetJointAcceleration(DEFAULT_JOINT_ACCELERATION_LOW);\r\n            break;\r\n        case COMMAND_CONTINUES_TRAJECTORY:\r\n            SetJointAcceleration(DEFAULT_JOINT_ACCELERATION_HIGH);\r\n            jointSpeedRatio = 0.3;\r\n            break;\r\n        case COMMAND_MOTOR_TUNING:\r\n            break;\r\n    }\r\n}\r\n\r\n\r\nDummyHand::DummyHand(CAN_HandleTypeDef* _hcan, uint8_t\r\n_id) :\r\n    nodeID(_id), hcan(_hcan)\r\n{\r\n    txHeader =\r\n        {\r\n            .StdId = 0,\r\n            .ExtId = 0,\r\n            .IDE = CAN_ID_STD,\r\n            .RTR = CAN_RTR_DATA,\r\n            .DLC = 8,\r\n            .TransmitGlobalTime = DISABLE\r\n        };\r\n}\r\n\r\n\r\nvoid DummyHand::SetAngle(float _angle)\r\n{\r\n    if (_angle > 30)_angle = 30;\r\n    if (_angle < 0)_angle = 0;\r\n\r\n    uint8_t mode = 0x02;\r\n    txHeader.StdId = 7 << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_angle;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid DummyHand::SetMaxCurrent(float _val)\r\n{\r\n    if (_val > 1)_val = 1;\r\n    if (_val < 0)_val = 0;\r\n\r\n    uint8_t mode = 0x01;\r\n    txHeader.StdId = 7 << 7 | mode;\r\n\r\n    // Float to Bytes\r\n    auto* b = (unsigned char*) &_val;\r\n    for (int i = 0; i < 4; i++)\r\n        canBuf[i] = *(b + i);\r\n\r\n    CanSendMessage(get_can_ctx(hcan), canBuf, &txHeader);\r\n}\r\n\r\n\r\nvoid DummyHand::SetEnable(bool _enable)\r\n{\r\n    if (_enable)\r\n        SetMaxCurrent(maxCurrent);\r\n    else\r\n        SetMaxCurrent(0);\r\n}\r\n\r\n\r\nuint32_t DummyRobot::CommandHandler::Push(const std::string &_cmd)\r\n{\r\n    osStatus_t status = osMessageQueuePut(commandFifo, _cmd.c_str(), 0U, 0U);\r\n    if (status == osOK)\r\n        return osMessageQueueGetSpace(commandFifo);\r\n\r\n    return 0xFF; // failed\r\n}\r\n\r\n\r\nvoid DummyRobot::CommandHandler::EmergencyStop()\r\n{\r\n    context->MoveJ(context->currentJoints.a[0], context->currentJoints.a[1], context->currentJoints.a[2],\r\n                   context->currentJoints.a[3], context->currentJoints.a[4], context->currentJoints.a[5]);\r\n    context->MoveJoints(context->targetJoints);\r\n    context->isEnabled = false;\r\n    ClearFifo();\r\n}\r\n\r\n\r\nstd::string DummyRobot::CommandHandler::Pop(uint32_t timeout)\r\n{\r\n    osStatus_t status = osMessageQueueGet(commandFifo, strBuffer, nullptr, timeout);\r\n\r\n    return std::string{strBuffer};\r\n}\r\n\r\n\r\nuint32_t DummyRobot::CommandHandler::GetSpace()\r\n{\r\n    return osMessageQueueGetSpace(commandFifo);\r\n}\r\n\r\n\r\nuint32_t DummyRobot::CommandHandler::ParseCommand(const std::string &_cmd)\r\n{\r\n    uint8_t argNum;\r\n\r\n    switch (context->commandMode)\r\n    {\r\n        case COMMAND_TARGET_POINT_SEQUENTIAL:\r\n        case COMMAND_CONTINUES_TRAJECTORY:\r\n            if (_cmd[0] == '>')\r\n            {\r\n                float joints[6];\r\n                float speed;\r\n\r\n                argNum = sscanf(_cmd.c_str(), \">%f,%f,%f,%f,%f,%f,%f\", joints, joints + 1, joints + 2,\r\n                                joints + 3, joints + 4, joints + 5, &speed);\r\n                if (argNum == 6)\r\n                {\r\n                    context->MoveJ(joints[0], joints[1], joints[2],\r\n                                   joints[3], joints[4], joints[5]);\r\n                } else if (argNum == 7)\r\n                {\r\n                    context->SetJointSpeed(speed);\r\n                    context->MoveJ(joints[0], joints[1], joints[2],\r\n                                   joints[3], joints[4], joints[5]);\r\n                }\r\n                // Trigger a transmission immediately, in case IsMoving() returns false\r\n                context->MoveJoints(context->targetJoints);\r\n\r\n                while (context->IsMoving() && context->IsEnabled())\r\n                    osDelay(5);\r\n                Respond(*usbStreamOutputPtr, \"ok\");\r\n                Respond(*uart4StreamOutputPtr, \"ok\");\r\n            } else if (_cmd[0] == '@')\r\n            {\r\n                float pose[6];\r\n                float speed;\r\n\r\n                argNum = sscanf(_cmd.c_str(), \"@%f,%f,%f,%f,%f,%f,%f\", pose, pose + 1, pose + 2,\r\n                                pose + 3, pose + 4, pose + 5, &speed);\r\n                if (argNum == 6)\r\n                {\r\n                    context->MoveL(pose[0], pose[1], pose[2], pose[3], pose[4], pose[5]);\r\n                } else if (argNum == 7)\r\n                {\r\n                    context->SetJointSpeed(speed);\r\n                    context->MoveL(pose[0], pose[1], pose[2], pose[3], pose[4], pose[5]);\r\n                }\r\n                // Trigger a transmission immediately, in case IsMoving() returns false\r\n                context->MoveJoints(context->targetJoints);\r\n\r\n                while (context->IsMoving())\r\n                    osDelay(5);\r\n                Respond(*usbStreamOutputPtr, \"ok\");\r\n                Respond(*uart4StreamOutputPtr, \"ok\");\r\n            }\r\n\r\n            break;\r\n\r\n        case COMMAND_TARGET_POINT_INTERRUPTABLE:\r\n            if (_cmd[0] == '>')\r\n            {\r\n                float joints[6];\r\n                float speed;\r\n\r\n                argNum = sscanf(_cmd.c_str(), \">%f,%f,%f,%f,%f,%f,%f\", joints, joints + 1, joints + 2,\r\n                                joints + 3, joints + 4, joints + 5, &speed);\r\n                if (argNum == 6)\r\n                {\r\n                    context->MoveJ(joints[0], joints[1], joints[2],\r\n                                   joints[3], joints[4], joints[5]);\r\n                } else if (argNum == 7)\r\n                {\r\n                    context->SetJointSpeed(speed);\r\n                    context->MoveJ(joints[0], joints[1], joints[2],\r\n                                   joints[3], joints[4], joints[5]);\r\n                }\r\n                Respond(*usbStreamOutputPtr, \"ok\");\r\n                Respond(*uart4StreamOutputPtr, \"ok\");\r\n            } else if (_cmd[0] == '@')\r\n            {\r\n                float pose[6];\r\n                float speed;\r\n\r\n                argNum = sscanf(_cmd.c_str(), \"@%f,%f,%f,%f,%f,%f,%f\", pose, pose + 1, pose + 2,\r\n                                pose + 3, pose + 4, pose + 5, &speed);\r\n                if (argNum == 6)\r\n                {\r\n                    context->MoveL(pose[0], pose[1], pose[2], pose[3], pose[4], pose[5]);\r\n                } else if (argNum == 7)\r\n                {\r\n                    context->SetJointSpeed(speed);\r\n                    context->MoveL(pose[0], pose[1], pose[2], pose[3], pose[4], pose[5]);\r\n                }\r\n                Respond(*usbStreamOutputPtr, \"ok\");\r\n                Respond(*uart4StreamOutputPtr, \"ok\");\r\n            }\r\n            break;\r\n\r\n        case COMMAND_MOTOR_TUNING:\r\n            break;\r\n    }\r\n\r\n    return osMessageQueueGetSpace(commandFifo);\r\n}\r\n\r\n\r\nvoid DummyRobot::CommandHandler::ClearFifo()\r\n{\r\n    osMessageQueueReset(commandFifo);\r\n}\r\n\r\n\r\nvoid DummyRobot::TuningHelper::SetTuningFlag(uint8_t _flag)\r\n{\r\n    tuningFlag = _flag;\r\n}\r\n\r\n\r\nvoid DummyRobot::TuningHelper::Tick(uint32_t _timeMillis)\r\n{\r\n    time += PI * 2 * frequency * (float) _timeMillis / 1000.0f;\r\n    float delta = amplitude * sinf(time);\r\n\r\n    for (int i = 1; i <= 6; i++)\r\n        if (tuningFlag & (1 << (i - 1)))\r\n            context->motorJ[i]->SetAngle(delta);\r\n}\r\n\r\n\r\nvoid DummyRobot::TuningHelper::SetFreqAndAmp(float _freq, float _amp)\r\n{\r\n    if (_freq > 5)_freq = 5;\r\n    else if (_freq < 0.1) _freq = 0.1;\r\n    if (_amp > 50)_amp = 50;\r\n    else if (_amp < 1) _amp = 1;\r\n\r\n    frequency = _freq;\r\n    amplitude = _amp;\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/Robot/instances/dummy_robot.h",
    "content": "#ifndef REF_STM32F4_FW_DUMMY_ROBOT_H\r\n#define REF_STM32F4_FW_DUMMY_ROBOT_H\r\n\r\n#include \"algorithms/kinematic/6dof_kinematic.h\"\r\n#include \"actuators/ctrl_step/ctrl_step.hpp\"\r\n\r\n#define ALL 0\r\n\r\n/*\r\n  |   PARAMS   | `current_limit` | `acceleration` | `dce_kp` | `dce_kv` | `dce_ki` | `dce_kd` |\r\n  | ---------- | --------------- | -------------- | -------- | -------- | -------- | -------- |\r\n  | **Joint1** | 2               | 30             | 1000     | 80       | 200      | 250      |\r\n  | **Joint2** | 2               | 30             | 1000     | 80       | 200      | 200      |\r\n  | **Joint3** | 2               | 30             | 1500     | 80       | 200      | 250      |\r\n  | **Joint4** | 2               | 30             | 1000     | 80       | 200      | 250      |\r\n  | **Joint5** | 2               | 30             | 1000     | 80       | 200      | 250      |\r\n  | **Joint6** | 2               | 30             | 1000     | 80       | 200      | 250      |\r\n */\r\n\r\n\r\nclass DummyHand\r\n{\r\npublic:\r\n    uint8_t nodeID = 7;\r\n    float maxCurrent = 0.7;\r\n\r\n\r\n    DummyHand(CAN_HandleTypeDef* _hcan, uint8_t _id);\r\n\r\n\r\n    void SetAngle(float _angle);\r\n    void SetMaxCurrent(float _val);\r\n    void SetEnable(bool _enable);\r\n\r\n\r\n    // Communication protocol definitions\r\n    auto MakeProtocolDefinitions()\r\n    {\r\n        return make_protocol_member_list(\r\n            make_protocol_function(\"set_angle\", *this, &DummyHand::SetAngle, \"angle\"),\r\n            make_protocol_function(\"set_enable\", *this, &DummyHand::SetEnable, \"enable\"),\r\n            make_protocol_function(\"set_current_limit\", *this, &DummyHand::SetMaxCurrent, \"current\")\r\n        );\r\n    }\r\n\r\n\r\nprivate:\r\n    CAN_HandleTypeDef* hcan;\r\n    uint8_t canBuf[8];\r\n    CAN_TxHeaderTypeDef txHeader;\r\n    float minAngle = 0;\r\n    float maxAngle = 45;\r\n};\r\n\r\n\r\nclass DummyRobot\r\n{\r\npublic:\r\n    explicit DummyRobot(CAN_HandleTypeDef* _hcan);\r\n    ~DummyRobot();\r\n\r\n\r\n    enum CommandMode\r\n    {\r\n        COMMAND_TARGET_POINT_SEQUENTIAL = 1,\r\n        COMMAND_TARGET_POINT_INTERRUPTABLE,\r\n        COMMAND_CONTINUES_TRAJECTORY,\r\n        COMMAND_MOTOR_TUNING\r\n    };\r\n\r\n\r\n    class TuningHelper\r\n    {\r\n    public:\r\n        explicit TuningHelper(DummyRobot* _context) : context(_context)\r\n        {\r\n        }\r\n\r\n        void SetTuningFlag(uint8_t _flag);\r\n        void Tick(uint32_t _timeMillis);\r\n        void SetFreqAndAmp(float _freq, float _amp);\r\n\r\n\r\n        // Communication protocol definitions\r\n        auto MakeProtocolDefinitions()\r\n        {\r\n            return make_protocol_member_list(\r\n                make_protocol_function(\"set_tuning_freq_amp\", *this,\r\n                                       &TuningHelper::SetFreqAndAmp, \"freq\", \"amp\"),\r\n                make_protocol_function(\"set_tuning_flag\", *this,\r\n                                       &TuningHelper::SetTuningFlag, \"flag\")\r\n            );\r\n        }\r\n\r\n\r\n    private:\r\n        DummyRobot* context;\r\n        float time = 0;\r\n        uint8_t tuningFlag = 0;\r\n        float frequency = 1;\r\n        float amplitude = 1;\r\n    };\r\n    TuningHelper tuningHelper = TuningHelper(this);\r\n\r\n\r\n    // This is the pose when power on.\r\n    const DOF6Kinematic::Joint6D_t REST_POSE = {0, -73, 180, 0, 0, 0};\r\n    const float DEFAULT_JOINT_SPEED = 30;  // degree/s\r\n    const DOF6Kinematic::Joint6D_t DEFAULT_JOINT_ACCELERATION_BASES = {150, 100, 200, 200, 200, 200};\r\n    const float DEFAULT_JOINT_ACCELERATION_LOW = 30;    // 0~100\r\n    const float DEFAULT_JOINT_ACCELERATION_HIGH = 100;  // 0~100\r\n    const CommandMode DEFAULT_COMMAND_MODE = COMMAND_TARGET_POINT_INTERRUPTABLE;\r\n\r\n\r\n    DOF6Kinematic::Joint6D_t currentJoints = REST_POSE;\r\n    DOF6Kinematic::Joint6D_t targetJoints = REST_POSE;\r\n    DOF6Kinematic::Joint6D_t initPose = REST_POSE;\r\n    DOF6Kinematic::Pose6D_t currentPose6D = {};\r\n    volatile uint8_t jointsStateFlag = 0b00000000;\r\n    CommandMode commandMode = DEFAULT_COMMAND_MODE;\r\n    CtrlStepMotor* motorJ[7] = {nullptr};\r\n    DummyHand* hand = {nullptr};\r\n\r\n\r\n    void Init();\r\n    bool MoveJ(float _j1, float _j2, float _j3, float _j4, float _j5, float _j6);\r\n    bool MoveL(float _x, float _y, float _z, float _a, float _b, float _c);\r\n    void MoveJoints(DOF6Kinematic::Joint6D_t _joints);\r\n    void SetJointSpeed(float _speed);\r\n    void SetJointAcceleration(float _acc);\r\n    void UpdateJointAngles();\r\n    void UpdateJointAnglesCallback();\r\n    void UpdateJointPose6D();\r\n    void Reboot();\r\n    void SetEnable(bool _enable);\r\n    void CalibrateHomeOffset();\r\n    void Homing();\r\n    void Resting();\r\n    bool IsMoving();\r\n    bool IsEnabled();\r\n    void SetCommandMode(uint32_t _mode);\r\n\r\n\r\n    // Communication protocol definitions\r\n    auto MakeProtocolDefinitions()\r\n    {\r\n        return make_protocol_member_list(\r\n            make_protocol_function(\"calibrate_home_offset\", *this, &DummyRobot::CalibrateHomeOffset),\r\n            make_protocol_function(\"homing\", *this, &DummyRobot::Homing),\r\n            make_protocol_function(\"resting\", *this, &DummyRobot::Resting),\r\n            make_protocol_object(\"joint_1\", motorJ[1]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_2\", motorJ[2]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_3\", motorJ[3]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_4\", motorJ[4]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_5\", motorJ[5]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_6\", motorJ[6]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"joint_all\", motorJ[ALL]->MakeProtocolDefinitions()),\r\n            make_protocol_object(\"hand\", hand->MakeProtocolDefinitions()),\r\n            make_protocol_function(\"reboot\", *this, &DummyRobot::Reboot),\r\n            make_protocol_function(\"set_enable\", *this, &DummyRobot::SetEnable, \"enable\"),\r\n            make_protocol_function(\"move_j\", *this, &DummyRobot::MoveJ, \"j1\", \"j2\", \"j3\", \"j4\", \"j5\", \"j6\"),\r\n            make_protocol_function(\"move_l\", *this, &DummyRobot::MoveL, \"x\", \"y\", \"z\", \"a\", \"b\", \"c\"),\r\n            make_protocol_function(\"set_joint_speed\", *this, &DummyRobot::SetJointSpeed, \"speed\"),\r\n            make_protocol_function(\"set_joint_acc\", *this, &DummyRobot::SetJointAcceleration, \"acc\"),\r\n            make_protocol_function(\"set_command_mode\", *this, &DummyRobot::SetCommandMode, \"mode\"),\r\n            make_protocol_object(\"tuning\", tuningHelper.MakeProtocolDefinitions())\r\n        );\r\n    }\r\n\r\n\r\n    class CommandHandler\r\n    {\r\n    public:\r\n        explicit CommandHandler(DummyRobot* _context) : context(_context)\r\n        {\r\n            commandFifo = osMessageQueueNew(16, 64, nullptr);\r\n        }\r\n\r\n        uint32_t Push(const std::string &_cmd);\r\n        std::string Pop(uint32_t timeout);\r\n        uint32_t ParseCommand(const std::string &_cmd);\r\n        uint32_t GetSpace();\r\n        void ClearFifo();\r\n        void EmergencyStop();\r\n\r\n\r\n    private:\r\n        DummyRobot* context;\r\n        osMessageQueueId_t commandFifo;\r\n        char strBuffer[64]{};\r\n    };\r\n    CommandHandler commandHandler = CommandHandler(this);\r\n\r\n\r\nprivate:\r\n    CAN_HandleTypeDef* hcan;\r\n    float jointSpeed = DEFAULT_JOINT_SPEED;\r\n    float jointSpeedRatio = 1;\r\n    DOF6Kinematic::Joint6D_t dynamicJointSpeeds = {1, 1, 1, 1, 1, 1};\r\n    DOF6Kinematic* dof6Solver;\r\n    bool isEnabled = false;\r\n};\r\n\r\n\r\n#endif //REF_STM32F4_FW_DUMMY_ROBOT_H\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/STM32F405RGTx_FLASH.ld",
    "content": "/*\n******************************************************************************\n**\n\n**  File        : LinkerScript.ld\n**\n**  Author\t\t: Auto-generated by System Workbench for STM32\n**\n**  Abstract    : Linker script for STM32F405RGTx series\n**                1024Kbytes FLASH and 192Kbytes RAM\n**\n**                Set heap size, stack size and stack location according\n**                to application requirements.\n**\n**                Set memory bank area and size if external memory is used.\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Distribution: The file is distributed “as is,” without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and/or other materials provided with the distribution.\n**   3. Neither the name of STMicroelectronics nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*/\n\n/* Entry Point */\nENTRY(Reset_Handler)\n\n/* Highest address of the user mode stack */\n_estack = 0x20020000;    /* end of RAM */\n/* Generate a link error if heap and stack don't fit into RAM */\n_Min_Heap_Size = 0x3C00;      /* required amount of heap  */\n_Min_Stack_Size = 0x800; /* required amount of stack */\n\n/* Specify the memory areas */\nMEMORY\n{\nRAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K\nCCMRAM (xrw)      : ORIGIN = 0x10000000, LENGTH = 64K\nFLASH (rx)      : ORIGIN = 0x8000000, LENGTH = 1024K\n}\n\n/* Define output sections */\nSECTIONS\n{\n  /* The startup code goes first into FLASH */\n  .isr_vector :\n  {\n    . = ALIGN(4);\n    KEEP(*(.isr_vector)) /* Startup code */\n    . = ALIGN(4);\n  } >FLASH\n\n  /* The program code and other data goes into FLASH */\n  .text :\n  {\n    . = ALIGN(4);\n    *(.text)           /* .text sections (code) */\n    *(.text*)          /* .text* sections (code) */\n    *(.glue_7)         /* glue arm to thumb code */\n    *(.glue_7t)        /* glue thumb to arm code */\n    *(.eh_frame)\n\n    KEEP (*(.init))\n    KEEP (*(.fini))\n\n    . = ALIGN(4);\n    _etext = .;        /* define a global symbols at end of code */\n  } >FLASH\n\n  /* Constant data goes into FLASH */\n  .rodata :\n  {\n    . = ALIGN(4);\n    *(.rodata)         /* .rodata sections (constants, strings, etc.) */\n    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */\n    . = ALIGN(4);\n  } >FLASH\n\n  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH\n  .ARM : {\n    __exidx_start = .;\n    *(.ARM.exidx*)\n    __exidx_end = .;\n  } >FLASH\n\n  .preinit_array     :\n  {\n    PROVIDE_HIDDEN (__preinit_array_start = .);\n    KEEP (*(.preinit_array*))\n    PROVIDE_HIDDEN (__preinit_array_end = .);\n  } >FLASH\n  .init_array :\n  {\n    PROVIDE_HIDDEN (__init_array_start = .);\n    KEEP (*(SORT(.init_array.*)))\n    KEEP (*(.init_array*))\n    PROVIDE_HIDDEN (__init_array_end = .);\n  } >FLASH\n  .fini_array :\n  {\n    PROVIDE_HIDDEN (__fini_array_start = .);\n    KEEP (*(SORT(.fini_array.*)))\n    KEEP (*(.fini_array*))\n    PROVIDE_HIDDEN (__fini_array_end = .);\n  } >FLASH\n\n  /* used by the startup to initialize data */\n  _sidata = LOADADDR(.data);\n\n  /* Initialized data sections goes into RAM, load LMA copy after code */\n  .data : \n  {\n    . = ALIGN(4);\n    _sdata = .;        /* create a global symbol at data start */\n    *(.data)           /* .data sections */\n    *(.data*)          /* .data* sections */\n\n    . = ALIGN(4);\n    _edata = .;        /* define a global symbol at data end */\n  } >RAM AT> FLASH\n\n  _siccmram = LOADADDR(.ccmram);\n\n  /* CCM-RAM section \n  * \n  * IMPORTANT NOTE! \n  * If initialized variables will be placed in this section,\n  * the startup code needs to be modified to copy the init-values.  \n  */\n  .ccmram :\n  {\n    . = ALIGN(4);\n    _sccmram = .;       /* create a global symbol at ccmram start */\n    *(.ccmram)\n    *(.ccmram*)\n    \n    . = ALIGN(4);\n    _eccmram = .;       /* create a global symbol at ccmram end */\n  } >CCMRAM AT> FLASH\n\n  \n  /* Uninitialized data section */\n  . = ALIGN(4);\n  .bss :\n  {\n    /* This is used by the startup in order to initialize the .bss secion */\n    _sbss = .;         /* define a global symbol at bss start */\n    __bss_start__ = _sbss;\n    *(.bss)\n    *(.bss*)\n    *(COMMON)\n\n    . = ALIGN(4);\n    _ebss = .;         /* define a global symbol at bss end */\n    __bss_end__ = _ebss;\n  } >RAM\n\n  /* User_heap_stack section, used to check that there is enough RAM left */\n  ._user_heap_stack :\n  {\n    . = ALIGN(8);\n    PROVIDE ( end = . );\n    PROVIDE ( _end = . );\n    . = . + _Min_Heap_Size;\n    . = . + _Min_Stack_Size;\n    . = ALIGN(8);\n  } >RAM\n\n  \n\n  /* Remove information from the standard libraries */\n  /DISCARD/ :\n  {\n    libc.a ( * )\n    libm.a ( * )\n    libgcc.a ( * )\n  }\n\n  .ARM.attributes 0 : { *(.ARM.attributes) }\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usb_device.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : usb_device.c\n  * @version        : v1.0_Cube\n  * @brief          : This file implements the USB Device\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Includes ------------------------------------------------------------------*/\n\n#include \"usb_device.h\"\n#include \"usbd_core.h\"\n#include \"usbd_desc.h\"\n#include \"usbd_cdc.h\"\n#include \"usbd_cdc_if.h\"\n\n/* USER CODE BEGIN Includes */\n#include <main.h>\n\n/* USER CODE END Includes */\n\n/* USER CODE BEGIN PV */\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE END PV */\n\n/* USER CODE BEGIN PFP */\n/* Private function prototypes -----------------------------------------------*/\n\n/* USER CODE END PFP */\n\n/* USB Device Core handle declaration. */\nUSBD_HandleTypeDef hUsbDeviceFS;\n\n/*\n * -- Insert your variables declaration here --\n */\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/*\n * -- Insert your external function declaration here --\n */\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/**\n  * Init USB device Library, add supported class and start the library\n  * @retval None\n  */\nvoid MX_USB_DEVICE_Init(void)\n{\n  /* USER CODE BEGIN USB_DEVICE_Init_PreTreatment */\n\n  /* USER CODE END USB_DEVICE_Init_PreTreatment */\n\n  /* Init Device Library, add supported class and start the library. */\n  if (USBD_Init(&hUsbDeviceFS, &FS_Desc, DEVICE_FS) != USBD_OK)\n  {\n    Error_Handler();\n  }\n  if (USBD_RegisterClass(&hUsbDeviceFS, &USBD_CDC) != USBD_OK)\n  {\n    Error_Handler();\n  }\n  if (USBD_CDC_RegisterInterface(&hUsbDeviceFS, &USBD_Interface_fops_FS) != USBD_OK)\n  {\n    Error_Handler();\n  }\n  if (USBD_Start(&hUsbDeviceFS) != USBD_OK)\n  {\n    Error_Handler();\n  }\n\n  /* USER CODE BEGIN USB_DEVICE_Init_PostTreatment */\n\n  /* USER CODE END USB_DEVICE_Init_PostTreatment */\n}\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usb_device.h",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : usb_device.h\n  * @version        : v1.0_Cube\n  * @brief          : Header for usb_device.c file.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under Ultimate Liberty license\n  * SLA0044, the \"License\"; You may not use this file except in compliance with\n  * the License. You may obtain a copy of the License at:\n  *                             www.st.com/SLA0044\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USB_DEVICE__H__\n#define __USB_DEVICE__H__\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n#include \"stm32f4xx_hal.h\"\n#include \"usbd_def.h\"\n\n/* USER CODE BEGIN INCLUDE */\n\n/* USER CODE END INCLUDE */\n\n/** @addtogroup USBD_OTG_DRIVER\n  * @{\n  */\n\n/** @defgroup USBD_DEVICE USBD_DEVICE\n  * @brief Device file for Usb otg low level driver.\n  * @{\n  */\n\n/** @defgroup USBD_DEVICE_Exported_Variables USBD_DEVICE_Exported_Variables\n  * @brief Public variables.\n  * @{\n  */\n\n/* Private variables ---------------------------------------------------------*/\n/* USER CODE BEGIN PV */\nextern USBD_HandleTypeDef hUsbDeviceFS;\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\n/* USER CODE BEGIN PFP */\n\n/* USER CODE END PFP */\n\n/*\n * -- Insert your variables declaration here --\n */\n/* USER CODE BEGIN VARIABLES */\n\n/* USER CODE END VARIABLES */\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DEVICE_Exported_FunctionsPrototype USBD_DEVICE_Exported_FunctionsPrototype\n  * @brief Declaration of public functions for Usb device.\n  * @{\n  */\n\n/** USB Device initialization function. */\nvoid MX_USB_DEVICE_Init(void);\n\n/*\n * -- Insert functions declaration here --\n */\n/* USER CODE BEGIN FD */\n\n/* USER CODE END FD */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USB_DEVICE__H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usbd_cdc_if.c",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_cdc_if.c\n  * @version        : v1.0_Cube\n  * @brief          : Usb device for Virtual Com Port.\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_cdc_if.h\"\n\n/* USER CODE BEGIN INCLUDE */\n#include \"cmsis_os.h\"\n#include <freertos_inc.h>\n#include \"interface_usb.hpp\"\n/* USER CODE END INCLUDE */\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n\n/* USER CODE BEGIN PV */\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE END PV */\n\n/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY\n  * @brief Usb device library.\n  * @{\n  */\n\n/** @addtogroup USBD_CDC_IF\n  * @{\n  */\n\n/** @defgroup USBD_CDC_IF_Private_TypesDefinitions USBD_CDC_IF_Private_TypesDefinitions\n  * @brief Private types.\n  * @{\n  */\n\n/* USER CODE BEGIN PRIVATE_TYPES */\n/* USER CODE END PRIVATE_TYPES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Private_Defines USBD_CDC_IF_Private_Defines\n  * @brief Private defines.\n  * @{\n  */\n\n/* USER CODE BEGIN PRIVATE_DEFINES */\n/* USER CODE END PRIVATE_DEFINES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Private_Macros USBD_CDC_IF_Private_Macros\n  * @brief Private macros.\n  * @{\n  */\n\n/* USER CODE BEGIN PRIVATE_MACRO */\n/* USER CODE END PRIVATE_MACRO */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Private_Variables USBD_CDC_IF_Private_Variables\n  * @brief Private variables.\n  * @{\n  */\n/* Create buffer for reception and transmission           */\n/* It's up to user to redefine and/or remove those define */\n/** Received data over USB are stored in this buffer      */\nuint8_t CDCRxBufferFS[APP_RX_DATA_SIZE];\nuint8_t REFRxBufferFS[APP_RX_DATA_SIZE];\n\n/** Data to send over USB CDC are stored in this buffer   */\nuint8_t CDCTxBufferFS[APP_TX_DATA_SIZE];\nuint8_t REFTxBufferFS[APP_TX_DATA_SIZE];\n\n/* USER CODE BEGIN PRIVATE_VARIABLES */\n/* USER CODE END PRIVATE_VARIABLES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables\n  * @brief Public variables.\n  * @{\n  */\n\nextern USBD_HandleTypeDef hUsbDeviceFS;\n\n/* USER CODE BEGIN EXPORTED_VARIABLES */\n/* USER CODE END EXPORTED_VARIABLES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Private_FunctionPrototypes USBD_CDC_IF_Private_FunctionPrototypes\n  * @brief Private functions declaration.\n  * @{\n  */\n\nstatic int8_t CDC_Init_FS(void);\nstatic int8_t CDC_DeInit_FS(void);\nstatic int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length);\nstatic int8_t CDC_Receive_FS(uint8_t* pbuf, uint32_t *Len, uint8_t endpoint_pair);\n\n/* USER CODE BEGIN PRIVATE_FUNCTIONS_DECLARATION */\n/* USER CODE END PRIVATE_FUNCTIONS_DECLARATION */\n\n/**\n  * @}\n  */\n\nUSBD_CDC_ItfTypeDef USBD_Interface_fops_FS =\n    {\n        CDC_Init_FS,\n        CDC_DeInit_FS,\n        CDC_Control_FS,\n        CDC_Receive_FS\n    };\n\n/* Private functions ---------------------------------------------------------*/\n/**\n  * @brief  Initializes the CDC media low layer over the FS USB IP\n  * @retval USBD_OK if all operations are OK else USBD_FAIL\n  */\nstatic int8_t CDC_Init_FS(void)\n{\n    /* USER CODE BEGIN 3 */\n    /* Set Application Buffers */\n    USBD_CDC_SetTxBuffer(&hUsbDeviceFS, CDCTxBufferFS, 0, CDC_OUT_EP);\n    USBD_CDC_SetRxBuffer(&hUsbDeviceFS, CDCRxBufferFS, CDC_OUT_EP);\n    USBD_CDC_SetTxBuffer(&hUsbDeviceFS, REFTxBufferFS, 0, ODRIVE_OUT_EP);\n    USBD_CDC_SetRxBuffer(&hUsbDeviceFS, REFRxBufferFS, ODRIVE_OUT_EP);\n    return (USBD_OK);\n    /* USER CODE END 3 */\n}\n\n/**\n  * @brief  DeInitializes the CDC media low layer\n  * @retval USBD_OK if all operations are OK else USBD_FAIL\n  */\nstatic int8_t CDC_DeInit_FS(void)\n{\n    /* USER CODE BEGIN 4 */\n    return (USBD_OK);\n    /* USER CODE END 4 */\n}\n\n/**\n  * @brief  Manage the CDC class requests\n  * @param  cmd: Command code\n  * @param  pbuf: Buffer containing command data (request parameters)\n  * @param  length: Number of data to be sent (in bytes)\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\n  */\nstatic int8_t CDC_Control_FS(uint8_t cmd, uint8_t* pbuf, uint16_t length)\n{\n    /* USER CODE BEGIN 5 */\n    switch (cmd)\n    {\n        case CDC_SEND_ENCAPSULATED_COMMAND:\n\n            break;\n\n        case CDC_GET_ENCAPSULATED_RESPONSE:\n\n            break;\n\n        case CDC_SET_COMM_FEATURE:\n\n            break;\n\n        case CDC_GET_COMM_FEATURE:\n\n            break;\n\n        case CDC_CLEAR_COMM_FEATURE:\n\n            break;\n\n            /*******************************************************************************/\n            /* Line Coding Structure                                                       */\n            /*-----------------------------------------------------------------------------*/\n            /* Offset | Field       | Size | Value  | Description                          */\n            /* 0      | dwDTERate   |   4  | Number |Data terminal rate, in bits per second*/\n            /* 4      | bCharFormat |   1  | Number | Stop bits                            */\n            /*                                        0 - 1 Stop bit                       */\n            /*                                        1 - 1.5 Stop bits                    */\n            /*                                        2 - 2 Stop bits                      */\n            /* 5      | bParityType |  1   | Number | Parity                               */\n            /*                                        0 - None                             */\n            /*                                        1 - Odd                              */\n            /*                                        2 - Even                             */\n            /*                                        3 - Mark                             */\n            /*                                        4 - Space                            */\n            /* 6      | bDataBits  |   1   | Number Data bits (5, 6, 7, 8 or 16).          */\n            /*******************************************************************************/\n        case CDC_SET_LINE_CODING:\n\n            break;\n\n        case CDC_GET_LINE_CODING:\n            pbuf[0] = (uint8_t)(115200);\n            pbuf[1] = (uint8_t)(115200 >> 8);\n            pbuf[2] = (uint8_t)(115200 >> 16);\n            pbuf[3] = (uint8_t)(115200 >> 24);\n            pbuf[4] = 0;  // stop bits (1)\n            pbuf[5] = 0;  // parity (none)\n            pbuf[6] = 8;  // number of bits (8)\n            break;\n\n        case CDC_SET_CONTROL_LINE_STATE:\n\n            break;\n\n        case CDC_SEND_BREAK:\n\n            break;\n\n        default:\n            break;\n    }\n\n    return (USBD_OK);\n    /* USER CODE END 5 */\n}\n\n/**\n  * @brief  Data received over USB OUT endpoint are sent over CDC interface\n  *         through this function.\n  *\n  *         @note\n  *         This function will block any OUT packet reception on USB endpoint\n  *         untill exiting this function. If you exit this function before transfer\n  *         is complete on CDC interface (ie. using DMA controller) it will result\n  *         in receiving more data while previous ones are still not sent.\n  *\n  * @param  Buf: Buffer of data to be received\n  * @param  Len: Number of data received (in bytes)\n  * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL\n  */\nstatic int8_t CDC_Receive_FS(uint8_t* Buf, uint32_t *Len, uint8_t endpoint_pair)\n{\n    /* USER CODE BEGIN 6 */\n    usb_rx_process_packet(Buf, *Len, endpoint_pair);\n\n    return (USBD_OK);\n    /* USER CODE END 6 */\n}\n\n/**\n  * @brief  CDC_Transmit_FS\n  *         Data to send over USB IN endpoint are sent over CDC interface\n  *         through this function.\n  *         @note\n  *\n  *\n  * @param  Buf: Buffer of data to be sent\n  * @param  Len: Number of data to be sent (in bytes)\n  * @retval USBD_OK if all operations are OK else USBD_FAIL or USBD_BUSY\n  */\nuint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair)\n{\n    uint8_t result = USBD_OK;\n    /* USER CODE BEGIN 7 */\n\n    //Check length\n    if (Len > USB_TX_DATA_SIZE)\n        return USBD_FAIL;\n\n    USBD_CDC_HandleTypeDef* hcdc = (USBD_CDC_HandleTypeDef*) hUsbDeviceFS.pClassData;\n\n    // Select EP\n    USBD_CDC_EP_HandleTypeDef* hEP_Tx;\n    uint8_t* TxBuff;\n    if (endpoint_pair == CDC_OUT_EP) {\n        hEP_Tx = &hcdc->CDC_Tx;\n        TxBuff = CDCTxBufferFS;\n    } else if (endpoint_pair == ODRIVE_OUT_EP) {\n        hEP_Tx = &hcdc->REF_Tx;\n        TxBuff = REFTxBufferFS;\n    } else {\n        return USBD_FAIL;\n    }\n\n    // Check for ongoing transmission\n    if (hEP_Tx->State != 0)\n        return USBD_BUSY;\n    // memcpy Buf into UserTxBufferFS\n    memcpy(TxBuff, Buf, Len);\n    // Update Len\n    USBD_CDC_SetTxBuffer(&hUsbDeviceFS, TxBuff, Len, endpoint_pair);\n    result = USBD_CDC_TransmitPacket(&hUsbDeviceFS, endpoint_pair);\n    /* USER CODE END 7 */\n    return result;\n}\n\n/* USER CODE BEGIN PRIVATE_FUNCTIONS_IMPLEMENTATION */\n/* USER CODE END PRIVATE_FUNCTIONS_IMPLEMENTATION */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usbd_cdc_if.h",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_cdc_if.h\n  * @version        : v1.0_Cube\n  * @brief          : Header for usbd_cdc_if.c file.\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_CDC_IF_H__\n#define __USBD_CDC_IF_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_cdc.h\"\n\n/* USER CODE BEGIN INCLUDE */\n/* USER CODE END INCLUDE */\n\n/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY\n  * @brief For Usb device.\n  * @{\n  */\n\n/** @defgroup USBD_CDC_IF USBD_CDC_IF\n  * @brief Usb VCP device module\n  * @{\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_Defines USBD_CDC_IF_Exported_Defines\n  * @brief Defines.\n  * @{\n  */\n/* USER CODE BEGIN EXPORTED_DEFINES */\n/* Define size for the receive and transmit buffer over CDC */\n/* It's up to user to redefine and/or remove those define */\n#define USB_RX_DATA_SIZE  64\n#define USB_TX_DATA_SIZE  64\n#define APP_RX_DATA_SIZE  USB_RX_DATA_SIZE\n#define APP_TX_DATA_SIZE  USB_TX_DATA_SIZE\n/* USER CODE END EXPORTED_DEFINES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_Types USBD_CDC_IF_Exported_Types\n  * @brief Types.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_TYPES */\n/* USER CODE END EXPORTED_TYPES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_Macros USBD_CDC_IF_Exported_Macros\n  * @brief Aliases.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_MACRO */\n/* USER CODE END EXPORTED_MACRO */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_Variables USBD_CDC_IF_Exported_Variables\n  * @brief Public variables.\n  * @{\n  */\n\n/** CDC Interface callback. */\nextern USBD_CDC_ItfTypeDef USBD_Interface_fops_FS;\n\n/* USER CODE BEGIN EXPORTED_VARIABLES */\n/* USER CODE END EXPORTED_VARIABLES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CDC_IF_Exported_FunctionsPrototype USBD_CDC_IF_Exported_FunctionsPrototype\n  * @brief Public functions declaration.\n  * @{\n  */\n\nuint8_t CDC_Transmit_FS(uint8_t* Buf, uint16_t Len, uint8_t endpoint_pair);\n\n/* USER CODE BEGIN EXPORTED_FUNCTIONS */\n/* USER CODE END EXPORTED_FUNCTIONS */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_CDC_IF_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usbd_desc.c",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_desc.c\n  * @version        : v1.0_Cube\n  * @brief          : This file implements the USB device descriptors.\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_core.h\"\n#include \"usbd_desc.h\"\n#include \"usbd_conf.h\"\n\n/* USER CODE BEGIN INCLUDE */\n#include \"common_inc.h\"\n/* USER CODE END INCLUDE */\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n\n/* USER CODE BEGIN PV */\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE END PV */\n\n/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY\n  * @{\n  */\n\n/** @addtogroup USBD_DESC\n  * @{\n  */\n\n/** @defgroup USBD_DESC_Private_TypesDefinitions USBD_DESC_Private_TypesDefinitions\n  * @brief Private types.\n  * @{\n  */\n\n/* USER CODE BEGIN PRIVATE_TYPES */\n\n/* USER CODE END PRIVATE_TYPES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Private_Defines USBD_DESC_Private_Defines\n  * @brief Private defines.\n  * @{\n  */\n\n#define USBD_VID     0x1209\n#define USBD_LANGID_STRING     1033\n#define USBD_MANUFACTURER_STRING     \"Robot Embedded Framework\"\n#define USBD_PID_FS     0x0D32\n#define USBD_PRODUCT_XSTR(s) USBD_PRODUCT_STR(s)\n#define USBD_PRODUCT_STR(s) #s\n#define USBD_PRODUCT_STRING_FS REF CONFIG_FW_VERSION CDC Interface\n#define NATIVE_STRING REF CONFIG_FW_VERSION Native Interface\n#define USBD_SERIALNUMBER_STRING_FS     \"000000000001\"\n#define USBD_CONFIGURATION_STRING_FS     \"CDC Config\"\n#define USBD_INTERFACE_STRING_FS     \"CDC Interface\"\n\n#define USB_SIZ_BOS_DESC            0x0C\n\n/* USER CODE BEGIN PRIVATE_DEFINES */\n\n/* USER CODE END PRIVATE_DEFINES */\n\n/**\n  * @}\n  */\n\n/* USER CODE BEGIN 0 */\n\n// MS OS String descriptor to tell Windows that it may query for other descriptors\n// It's a standard string descriptor.\n// Windows will only query for OS descriptors once!\n// Delete the information about already queried devices in registry by deleting:\n// HKEY_LOCAL_MACHINE\\SYSTEM\\CurrentControlSet\\Control\\usbflags\\VVVVPPPPRRRR\n__ALIGN_BEGIN uint8_t USBD_MS_OS_StringDescriptor[]  __ALIGN_END =\n    {\n        0x12,           //  bLength           1 0x12  Length of the descriptor\n        0x03,           //  bDescriptorType   1 0x03  Descriptor type\n        //  qwSignature      14 ‘MSFT100’ Signature field\n        0x4D, 0x00,     //  'M'\n        0x53, 0x00,     //  'S'\n        0x46, 0x00,     //  'F'\n        0x54, 0x00,     //  'T'\n        0x31, 0x00,     //  '1'\n        0x30, 0x00,     //  '0'\n        0x30, 0x00,     //  '0'\n        MS_VendorCode,  //  bMS_VendorCode    1 Vendor-specific Vendor code\n        0x00            //  bPad              1 0x00  Pad field\n    };\n\n// redefined further down\n__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;\n\n/**\n* @brief  UsrStrDescriptor\n*         return non standard string descriptor\n* @param  pdev: device instance\n* @param  index : descriptor index (0xEE for MS OS String Descriptor)\n* @param  length : pointer data length\n* @retval pointer to descriptor buffer\n*/\nuint8_t *USBD_UsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index, uint16_t *length)\n{\n    *length = 0;\n    if (USBD_IDX_MICROSOFT_DESC_STR == index)\n    {\n        *length = sizeof(USBD_MS_OS_StringDescriptor);\n        return USBD_MS_OS_StringDescriptor;\n    } else if (USBD_IDX_REF_INTF_STR == index)\n    {\n        USBD_GetString((uint8_t *) USBD_PRODUCT_XSTR(NATIVE_STRING), USBD_StrDesc, length);\n        return USBD_StrDesc;\n    }\n    return NULL;\n}\n\n/* USER CODE END 0 */\n\n/** @defgroup USBD_DESC_Private_Macros USBD_DESC_Private_Macros\n  * @brief Private macros.\n  * @{\n  */\n\n/* USER CODE BEGIN PRIVATE_MACRO */\n\n/* USER CODE END PRIVATE_MACRO */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Private_FunctionPrototypes USBD_DESC_Private_FunctionPrototypes\n  * @brief Private functions declaration.\n  * @{\n  */\n\nuint8_t *USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\nuint8_t *USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n\n#ifdef USB_SUPPORT_USER_STRING_DESC\nuint8_t * USBD_FS_USRStringDesc(USBD_SpeedTypeDef speed, uint8_t idx, uint16_t *length);\n#endif /* USB_SUPPORT_USER_STRING_DESC */\n\n#if (USBD_LPM_ENABLED == 1)\nuint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length);\n#endif /* (USBD_LPM_ENABLED == 1) */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables\n  * @brief Private variables.\n  * @{\n  */\n\nUSBD_DescriptorsTypeDef FS_Desc =\n    {\n        USBD_FS_DeviceDescriptor, USBD_FS_LangIDStrDescriptor, USBD_FS_ManufacturerStrDescriptor,\n        USBD_FS_ProductStrDescriptor, USBD_FS_SerialStrDescriptor, USBD_FS_ConfigStrDescriptor,\n        USBD_FS_InterfaceStrDescriptor\n#if (USBD_LPM_ENABLED == 1)\n        , USBD_FS_USR_BOSDescriptor\n#endif /* (USBD_LPM_ENABLED == 1) */\n    };\n\n#if defined ( __ICCARM__ ) /* IAR Compiler */\n#pragma data_alignment=4\n#endif /* defined ( __ICCARM__ ) */\n/** USB standard device descriptor. */\n__ALIGN_BEGIN uint8_t USBD_FS_DeviceDesc[USB_LEN_DEV_DESC] __ALIGN_END =\n    {\n        0x12,                       /*bLength */\n        USB_DESC_TYPE_DEVICE,       /*bDescriptorType*/\n#if (USBD_LPM_ENABLED == 1)\n        0x01,                       /*bcdUSB */ /* changed to USB version 2.01\n                                             in order to support LPM L1 suspend\n                                             resume test of USBCV3.0*/\n#else\n        0x00,                       /*bcdUSB */\n#endif /* (USBD_LPM_ENABLED == 1) */\n        0x02,\n        // Notify OS that this is a composite device\n        0xEF,                       /*bDeviceClass*/\n        0x02,                       /*bDeviceSubClass*/\n        0x01,                       /*bDeviceProtocol*/\n        USB_MAX_EP0_SIZE,           /*bMaxPacketSize*/\n        LOBYTE(USBD_VID),           /*idVendor*/\n        HIBYTE(USBD_VID),           /*idVendor*/\n        LOBYTE(USBD_PID_FS),        /*idProduct*/\n        HIBYTE(USBD_PID_FS),        /*idProduct*/\n        0x00,                       /*bcdDevice rel. 2.00*/\n        0x03,                       /* bNumInterfaces */\n        USBD_IDX_MFC_STR,           /*Index of manufacturer  string*/\n        USBD_IDX_PRODUCT_STR,       /*Index of product string*/\n        USBD_IDX_SERIAL_STR,        /*Index of serial number string*/\n        USBD_MAX_NUM_CONFIGURATION  /*bNumConfigurations*/\n    };\n\n/* USB_DeviceDescriptor */\n/** BOS descriptor. */\n#if (USBD_LPM_ENABLED == 1)\n#if defined ( __ICCARM__ ) /* IAR Compiler */\n#pragma data_alignment=4\n#endif /* defined ( __ICCARM__ ) */\n__ALIGN_BEGIN uint8_t USBD_FS_BOSDesc[USB_SIZ_BOS_DESC] __ALIGN_END =\n{\n  0x5,\n  USB_DESC_TYPE_BOS,\n  0xC,\n  0x0,\n  0x1,  /* 1 device capability*/\n        /* device capability*/\n  0x7,\n  USB_DEVICE_CAPABITY_TYPE,\n  0x2,\n  0x2,  /* LPM capability bit set*/\n  0x0,\n  0x0,\n  0x0\n};\n#endif /* (USBD_LPM_ENABLED == 1) */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Private_Variables USBD_DESC_Private_Variables\n  * @brief Private variables.\n  * @{\n  */\n\n#if defined ( __ICCARM__ ) /* IAR Compiler */\n#pragma data_alignment=4\n#endif /* defined ( __ICCARM__ ) */\n\n/** USB lang indentifier descriptor. */\n__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_LEN_LANGID_STR_DESC] __ALIGN_END =\n    {\n        USB_LEN_LANGID_STR_DESC,\n        USB_DESC_TYPE_STRING,\n        LOBYTE(USBD_LANGID_STRING),\n        HIBYTE(USBD_LANGID_STRING)\n    };\n\n#if defined ( __ICCARM__ ) /* IAR Compiler */\n#pragma data_alignment=4\n#endif /* defined ( __ICCARM__ ) */\n/* Internal string descriptor. */\n__ALIGN_BEGIN uint8_t USBD_StrDesc[USBD_MAX_STR_DESC_SIZ] __ALIGN_END;\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Private_Functions USBD_DESC_Private_Functions\n  * @brief Private functions.\n  * @{\n  */\n\n/**\n  * @brief  Return the device descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_DeviceDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    *length = sizeof(USBD_FS_DeviceDesc);\n    return USBD_FS_DeviceDesc;\n}\n\n/**\n  * @brief  Return the LangID string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_LangIDStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    *length = sizeof(USBD_LangIDDesc);\n    return USBD_LangIDDesc;\n}\n\n/**\n  * @brief  Return the product string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_ProductStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    if (speed == 0)\n    {\n        USBD_GetString((uint8_t *) USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length);\n    } else\n    {\n        USBD_GetString((uint8_t *) USBD_PRODUCT_XSTR(USBD_PRODUCT_STRING_FS), USBD_StrDesc, length);\n    }\n    return USBD_StrDesc;\n}\n\n/**\n  * @brief  Return the manufacturer string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_ManufacturerStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    USBD_GetString((uint8_t *) USBD_MANUFACTURER_STRING, USBD_StrDesc, length);\n    return USBD_StrDesc;\n}\n\n/**\n  * @brief  Return the serial number string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_SerialStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    USBD_GetString((uint8_t *) (serialNumberStr), USBD_StrDesc, length);\n    return USBD_StrDesc;\n}\n\n/**\n  * @brief  Return the configuration string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_ConfigStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    if (speed == USBD_SPEED_HIGH)\n    {\n        USBD_GetString((uint8_t *) USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);\n    } else\n    {\n        USBD_GetString((uint8_t *) USBD_CONFIGURATION_STRING_FS, USBD_StrDesc, length);\n    }\n    return USBD_StrDesc;\n}\n\n/**\n  * @brief  Return the interface string descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t *USBD_FS_InterfaceStrDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n    if (speed == 0)\n    {\n        USBD_GetString((uint8_t *) USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);\n    } else\n    {\n        USBD_GetString((uint8_t *) USBD_INTERFACE_STRING_FS, USBD_StrDesc, length);\n    }\n    return USBD_StrDesc;\n}\n\n#if (USBD_LPM_ENABLED == 1)\n/**\n  * @brief  Return the BOS descriptor\n  * @param  speed : Current device speed\n  * @param  length : Pointer to data length variable\n  * @retval Pointer to descriptor buffer\n  */\nuint8_t * USBD_FS_USR_BOSDescriptor(USBD_SpeedTypeDef speed, uint16_t *length)\n{\n  *length = sizeof(USBD_FS_BOSDesc);\n  return (uint8_t*)USBD_FS_BOSDesc;\n}\n#endif /* (USBD_LPM_ENABLED == 1) */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/App/usbd_desc.h",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_desc.h\n  * @version        : v1.0_Cube\n  * @brief          : Header for usbd_desc.c file.\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_DESC__H__\n#define __USBD_DESC__H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usbd_def.h\"\n\n/* USER CODE BEGIN INCLUDE */\n\n/* USER CODE END INCLUDE */\n\n/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY\n  * @{\n  */\n\n/** @defgroup USBD_DESC USBD_DESC\n  * @brief Usb device descriptors module.\n  * @{\n  */\n\n/** @defgroup USBD_DESC_Exported_Defines USBD_DESC_Exported_Defines\n  * @brief Defines.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_DEFINES */\n\n/* USER CODE END EXPORTED_DEFINES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Exported_TypesDefinitions USBD_DESC_Exported_TypesDefinitions\n  * @brief Types.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_TYPES */\n\n/* USER CODE END EXPORTED_TYPES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Exported_Macros USBD_DESC_Exported_Macros\n  * @brief Aliases.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_MACRO */\n\n/* USER CODE END EXPORTED_MACRO */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Exported_Variables USBD_DESC_Exported_Variables\n  * @brief Public variables.\n  * @{\n  */\n\n/** Descriptor for the Usb device. */\nextern USBD_DescriptorsTypeDef FS_Desc;\n\n/* USER CODE BEGIN EXPORTED_VARIABLES */\n\n/* USER CODE END EXPORTED_VARIABLES */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_DESC_Exported_FunctionsPrototype USBD_DESC_Exported_FunctionsPrototype\n  * @brief Public functions declaration.\n  * @{\n  */\n\n/* USER CODE BEGIN EXPORTED_FUNCTIONS */\n\nuint8_t * USBD_UsrStrDescriptor(struct _USBD_HandleTypeDef *pdev, uint8_t index,  uint16_t *length);\n\n/* USER CODE END EXPORTED_FUNCTIONS */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_DESC__H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/Target/usbd_conf.c",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_conf.c\n  * @version        : v1.0_Cube\n  * @brief          : This file implements the board support package for the USB device library\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f4xx.h\"\n#include \"stm32f4xx_hal.h\"\n#include \"usbd_def.h\"\n#include \"usbd_core.h\"\n\n/* USER CODE BEGIN Includes */\n#include \"main.h\"\n\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* Private define ------------------------------------------------------------*/\n/* Private macro -------------------------------------------------------------*/\n\n/* USER CODE BEGIN PV */\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE END PV */\n\nPCD_HandleTypeDef hpcd_USB_OTG_FS;\n\n\n/* External functions --------------------------------------------------------*/\nvoid SystemClock_Config(void);\n\n/* USER CODE BEGIN 0 */\n/* USER CODE END 0 */\n\n/* USER CODE BEGIN PFP */\n/* Private function prototypes -----------------------------------------------*/\n\n/* USER CODE END PFP */\n\n/* Private functions ---------------------------------------------------------*/\n\n/* USER CODE BEGIN 1 */\n/* USER CODE END 1 */\n\n/*******************************************************************************\n                       LL Driver Callbacks (PCD -> USB Device Library)\n*******************************************************************************/\n/* MSP Init */\n\nvoid HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)\n{\n    GPIO_InitTypeDef GPIO_InitStruct;\n    if(pcdHandle->Instance==USB_OTG_FS)\n    {\n        /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */\n\n        /* USER CODE END USB_OTG_FS_MspInit 0 */\n\n        /**USB_OTG_FS GPIO Configuration\n        PA11     ------> USB_OTG_FS_DM\n        PA12     ------> USB_OTG_FS_DP\n        */\n        GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;\n        GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n        GPIO_InitStruct.Pull = GPIO_NOPULL;\n        GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;\n        GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS;\n        HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n        /* Peripheral clock enable */\n        __HAL_RCC_USB_OTG_FS_CLK_ENABLE();\n\n        /* Peripheral interrupt init */\n        HAL_NVIC_SetPriority(OTG_FS_IRQn, 5, 0);\n        HAL_NVIC_EnableIRQ(OTG_FS_IRQn);\n        /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */\n\n        /* USER CODE END USB_OTG_FS_MspInit 1 */\n    }\n}\n\nvoid HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle)\n{\n    if(pcdHandle->Instance==USB_OTG_FS)\n    {\n        /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */\n\n        /* USER CODE END USB_OTG_FS_MspDeInit 0 */\n        /* Peripheral clock disable */\n        __HAL_RCC_USB_OTG_FS_CLK_DISABLE();\n\n        /**USB_OTG_FS GPIO Configuration\n        PA11     ------> USB_OTG_FS_DM\n        PA12     ------> USB_OTG_FS_DP\n        */\n        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);\n\n        /* Peripheral interrupt Deinit*/\n        HAL_NVIC_DisableIRQ(OTG_FS_IRQn);\n\n        /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */\n\n        /* USER CODE END USB_OTG_FS_MspDeInit 1 */\n    }\n}\n\n/**\n  * @brief  Setup stage callback\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)\n{\n    USBD_StatusTypeDef ret = USBD_OK;\n    USBD_HandleTypeDef *pdev = hpcd->pData;\n    USBD_SetupReqTypedef    *req = &pdev->request;\n    USBD_ParseSetupRequest(req, (uint8_t *)hpcd->Setup);\n    if ( ( USB_REQ_TYPE_VENDOR == (req->bmRequest & USB_REQ_TYPE_MASK) ) && ( MS_VendorCode == req->bRequest ) )\n    {\n        pdev->ep0_state = USBD_EP0_SETUP;\n        pdev->ep0_data_len = pdev->request.wLength;\n\n        ret = pdev->pClass->Setup(pdev, req);\n\n        if( (req->wLength == 0) && (ret == USBD_OK) )\n        {\n            USBD_CtlSendStatus(pdev);\n        }\n        return;\n    }\n    USBD_LL_SetupStage((USBD_HandleTypeDef*)hpcd->pData, (uint8_t *)hpcd->Setup);\n}\n\n/**\n  * @brief  Data Out stage callback.\n  * @param  hpcd: PCD handle\n  * @param  epnum: Endpoint number\n  * @retval None\n  */\nvoid HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n    USBD_LL_DataOutStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->OUT_ep[epnum].xfer_buff);\n}\n\n/**\n  * @brief  Data In stage callback.\n  * @param  hpcd: PCD handle\n  * @param  epnum: Endpoint number\n  * @retval None\n  */\nvoid HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n    USBD_LL_DataInStage((USBD_HandleTypeDef*)hpcd->pData, epnum, hpcd->IN_ep[epnum].xfer_buff);\n}\n\n/**\n  * @brief  SOF callback.\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)\n{\n    USBD_LL_SOF((USBD_HandleTypeDef*)hpcd->pData);\n}\n\n/**\n  * @brief  Reset callback.\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)\n{\n    USBD_SpeedTypeDef speed = USBD_SPEED_FULL;\n\n    /* Set USB current speed. */\n    switch (hpcd->Init.speed)\n    {\n        case PCD_SPEED_HIGH:\n            speed = USBD_SPEED_HIGH;\n            break;\n        case PCD_SPEED_FULL:\n            speed = USBD_SPEED_FULL;\n            break;\n\n        default:\n            speed = USBD_SPEED_FULL;\n            break;\n    }\n    USBD_LL_SetSpeed((USBD_HandleTypeDef*)hpcd->pData, speed);\n\n    /* Reset Device. */\n    USBD_LL_Reset((USBD_HandleTypeDef*)hpcd->pData);\n}\n\n/**\n  * @brief  Suspend callback.\n  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)\n{\n    /* Inform USB library that core enters in suspend Mode. */\n    USBD_LL_Suspend((USBD_HandleTypeDef*)hpcd->pData);\n    __HAL_PCD_GATE_PHYCLOCK(hpcd);\n    /* Enter in STOP mode. */\n    /* USER CODE BEGIN 2 */\n    if (hpcd->Init.low_power_enable)\n    {\n        /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register */\n        SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));\n    }\n    /* USER CODE END 2 */\n}\n\n/**\n  * @brief  Resume callback.\n  * When Low power mode is enabled the debug cannot be used (IAR, Keil doesn't support it)\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)\n{\n    /* USER CODE BEGIN 3 */\n    /* USER CODE END 3 */\n    USBD_LL_Resume((USBD_HandleTypeDef*)hpcd->pData);\n}\n\n/**\n  * @brief  ISOOUTIncomplete callback.\n  * @param  hpcd: PCD handle\n  * @param  epnum: Endpoint number\n  * @retval None\n  */\nvoid HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n    USBD_LL_IsoOUTIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);\n}\n\n/**\n  * @brief  ISOINIncomplete callback.\n  * @param  hpcd: PCD handle\n  * @param  epnum: Endpoint number\n  * @retval None\n  */\nvoid HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)\n{\n    USBD_LL_IsoINIncomplete((USBD_HandleTypeDef*)hpcd->pData, epnum);\n}\n\n/**\n  * @brief  Connect callback.\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)\n{\n    USBD_LL_DevConnected((USBD_HandleTypeDef*)hpcd->pData);\n}\n\n/**\n  * @brief  Disconnect callback.\n  * @param  hpcd: PCD handle\n  * @retval None\n  */\nvoid HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)\n{\n    USBD_LL_DevDisconnected((USBD_HandleTypeDef*)hpcd->pData);\n}\n\n/*******************************************************************************\n                       LL Driver Interface (USB Device Library --> PCD)\n*******************************************************************************/\n\n/**\n  * @brief  Initializes the low level portion of the device driver.\n  * @param  pdev: Device handle\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)\n{\n    /* Init USB Ip. */\n    if (pdev->id == DEVICE_FS) {\n        /* Link the driver to the stack. */\n        hpcd_USB_OTG_FS.pData = pdev;\n        pdev->pData = &hpcd_USB_OTG_FS;\n\n        hpcd_USB_OTG_FS.Instance = USB_OTG_FS;\n        hpcd_USB_OTG_FS.Init.dev_endpoints = 6;\n        hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL;\n        hpcd_USB_OTG_FS.Init.dma_enable = DISABLE;\n        hpcd_USB_OTG_FS.Init.ep0_mps = EP_MPS_64;\n        hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED;\n        hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE;\n        hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE;\n        hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE;\n        hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE;\n        hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE;\n        if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK)\n        {\n            Error_Handler();\n        }\n\n        HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);\n        HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);\n        HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40); // CDC IN endpoint\n        HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 3, 0x40); // REF IN endpoint\n    }\n    return USBD_OK;\n}\n\n/**\n  * @brief  De-Initializes the low level portion of the device driver.\n  * @param  pdev: Device handle\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_DeInit(USBD_HandleTypeDef *pdev)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_DeInit(pdev->pData);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Starts the low level portion of the device driver.\n  * @param  pdev: Device handle\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_Start(USBD_HandleTypeDef *pdev)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_Start(pdev->pData);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Stops the low level portion of the device driver.\n  * @param  pdev: Device handle\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_Stop(USBD_HandleTypeDef *pdev)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_Stop(pdev->pData);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Opens an endpoint of the low level driver.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @param  ep_type: Endpoint type\n  * @param  ep_mps: Endpoint max packet size\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_OpenEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_Open(pdev->pData, ep_addr, ep_mps, ep_type);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Closes an endpoint of the low level driver.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_CloseEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_Close(pdev->pData, ep_addr);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Flushes an endpoint of the Low Level Driver.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_FlushEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_Flush(pdev->pData, ep_addr);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Sets a Stall condition on an endpoint of the Low Level Driver.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_StallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_SetStall(pdev->pData, ep_addr);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Clears a Stall condition on an endpoint of the Low Level Driver.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_ClearStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_ClrStall(pdev->pData, ep_addr);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Returns Stall condition.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval Stall (1: Yes, 0: No)\n  */\nuint8_t USBD_LL_IsStallEP(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    PCD_HandleTypeDef *hpcd = (PCD_HandleTypeDef*) pdev->pData;\n\n    if((ep_addr & 0x80) == 0x80)\n    {\n        return hpcd->IN_ep[ep_addr & 0x7F].is_stall;\n    }\n    else\n    {\n        return hpcd->OUT_ep[ep_addr & 0x7F].is_stall;\n    }\n}\n\n/**\n  * @brief  Assigns a USB address to the device.\n  * @param  pdev: Device handle\n  * @param  dev_addr: Device address\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_SetUSBAddress(USBD_HandleTypeDef *pdev, uint8_t dev_addr)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_SetAddress(pdev->pData, dev_addr);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Transmits data over an endpoint.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @param  pbuf: Pointer to data to be sent\n  * @param  size: Data size\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_Transmit(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_Transmit(pdev->pData, ep_addr, pbuf, size);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Prepares an endpoint for reception.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @param  pbuf: Pointer to data to be received\n  * @param  size: Data size\n  * @retval USBD status\n  */\nUSBD_StatusTypeDef USBD_LL_PrepareReceive(USBD_HandleTypeDef *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t size)\n{\n    HAL_StatusTypeDef hal_status = HAL_OK;\n    USBD_StatusTypeDef usb_status = USBD_OK;\n\n    hal_status = HAL_PCD_EP_Receive(pdev->pData, ep_addr, pbuf, size);\n\n    switch (hal_status) {\n        case HAL_OK :\n            usb_status = USBD_OK;\n            break;\n        case HAL_ERROR :\n            usb_status = USBD_FAIL;\n            break;\n        case HAL_BUSY :\n            usb_status = USBD_BUSY;\n            break;\n        case HAL_TIMEOUT :\n            usb_status = USBD_FAIL;\n            break;\n        default :\n            usb_status = USBD_FAIL;\n            break;\n    }\n    return usb_status;\n}\n\n/**\n  * @brief  Returns the last transfered packet size.\n  * @param  pdev: Device handle\n  * @param  ep_addr: Endpoint number\n  * @retval Recived Data Size\n  */\nuint32_t USBD_LL_GetRxDataSize(USBD_HandleTypeDef *pdev, uint8_t ep_addr)\n{\n    return HAL_PCD_EP_GetRxCount((PCD_HandleTypeDef*) pdev->pData, ep_addr);\n}\n\n#if (USBD_LPM_ENABLED == 1)\n/**\n  * @brief  Send LPM message to user layer\n  * @param  hpcd: PCD handle\n  * @param  msg: LPM message\n  * @retval None\n  */\nvoid HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)\n{\n  switch (msg)\n  {\n  case PCD_LPM_L0_ACTIVE:\n    if (hpcd->Init.low_power_enable)\n    {\n      SystemClock_Config();\n\n      /* Reset SLEEPDEEP bit of Cortex System Control Register. */\n      SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));\n    }\n    __HAL_PCD_UNGATE_PHYCLOCK(hpcd);\n    USBD_LL_Resume(hpcd->pData);\n    break;\n\n  case PCD_LPM_L1_ACTIVE:\n    __HAL_PCD_GATE_PHYCLOCK(hpcd);\n    USBD_LL_Suspend(hpcd->pData);\n\n    /* Enter in STOP mode. */\n    if (hpcd->Init.low_power_enable)\n    {\n      /* Set SLEEPDEEP bit and SleepOnExit of Cortex System Control Register. */\n      SCB->SCR |= (uint32_t)((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk));\n    }\n    break;\n  }\n}\n#endif /* (USBD_LPM_ENABLED == 1) */\n\n/**\n  * @brief  Delays routine for the USB Device Library.\n  * @param  Delay: Delay in ms\n  * @retval None\n  */\nvoid USBD_LL_Delay(uint32_t Delay)\n{\n    HAL_Delay(Delay);\n}\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/USB_DEVICE/Target/usbd_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file           : usbd_conf.h\n  * @version        : v1.0_Cube\n  * @brief          : Header for usbd_conf.c file.\n  ******************************************************************************\n  * This notice applies to any and all portions of this file\n  * that are not between comment pairs USER CODE BEGIN and\n  * USER CODE END. Other portions of this file, whether\n  * inserted by the user or by software development tools\n  * are owned by their respective copyright owners.\n  *\n  * Copyright (c) 2018 STMicroelectronics International N.V.\n  * All rights reserved.\n  *\n  * Redistribution and use in source and binary forms, with or without\n  * modification, are permitted, provided that the following conditions are met:\n  *\n  * 1. Redistribution of source code must retain the above copyright notice,\n  *    this list of conditions and the following disclaimer.\n  * 2. Redistributions in binary form must reproduce the above copyright notice,\n  *    this list of conditions and the following disclaimer in the documentation\n  *    and/or other materials provided with the distribution.\n  * 3. Neither the name of STMicroelectronics nor the names of other\n  *    contributors to this software may be used to endorse or promote products\n  *    derived from this software without specific written permission.\n  * 4. This software, including modifications and/or derivative works of this\n  *    software, must execute solely and exclusively on microcontroller or\n  *    microprocessor devices manufactured by or for STMicroelectronics.\n  * 5. Redistribution and use of this software other than as permitted under\n  *    this license is void and will automatically terminate your rights under\n  *    this license.\n  *\n  * THIS SOFTWARE IS PROVIDED BY STMICROELECTRONICS AND CONTRIBUTORS \"AS IS\"\n  * AND ANY EXPRESS, IMPLIED OR STATUTORY WARRANTIES, INCLUDING, BUT NOT\n  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A\n  * PARTICULAR PURPOSE AND NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY\n  * RIGHTS ARE DISCLAIMED TO THE FULLEST EXTENT PERMITTED BY LAW. IN NO EVENT\n  * SHALL STMICROELECTRONICS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,\n  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\n  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,\n  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\n  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\n  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USBD_CONF__H__\n#define __USBD_CONF__H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include <stdio.h>\n#include <stdlib.h>\n#include <string.h>\n#include \"stm32f4xx.h\"\n#include \"stm32f4xx_hal.h\"\n\n/* USER CODE BEGIN INCLUDE */\n\n/* USER CODE END INCLUDE */\n\n/** @addtogroup USBD_OTG_DRIVER\n  * @brief Driver for Usb device.\n  * @{\n  */\n\n/** @defgroup USBD_CONF USBD_CONF\n  * @brief Configuration file for Usb otg low level driver.\n  * @{\n  */\n\n/** @defgroup USBD_CONF_Exported_Variables USBD_CONF_Exported_Variables\n  * @brief Public variables.\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CONF_Exported_Defines USBD_CONF_Exported_Defines\n  * @brief Defines for configuration of the Usb device.\n  * @{\n  */\n#define MS_VendorCode 'P'\n\n/*---------- -----------*/\n#define USBD_MAX_NUM_INTERFACES     1\n/*---------- -----------*/\n#define USBD_MAX_NUM_CONFIGURATION     1\n/*---------- -----------*/\n#define USBD_MAX_STR_DESC_SIZ     512\n/*---------- -----------*/\n#define USBD_SUPPORT_USER_STRING     1\n/*---------- -----------*/\n#define USBD_DEBUG_LEVEL     0\n/*---------- -----------*/\n#define USBD_LPM_ENABLED     0\n/*---------- -----------*/\n#define USBD_SELF_POWERED     1\n\n/****************************************/\n/* #define for FS and HS identification */\n#define DEVICE_FS \t\t0\n#define DEVICE_HS \t\t1\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CONF_Exported_Macros USBD_CONF_Exported_Macros\n  * @brief Aliases.\n  * @{\n  */\n\n/* Memory management macros */\n\n/** Alias for memory allocation. */\n#define USBD_malloc         malloc\n\n/** Alias for memory release. */\n#define USBD_free           free\n\n/** Alias for memory set. */\n#define USBD_memset         memset\n\n/** Alias for memory copy. */\n#define USBD_memcpy         memcpy\n\n/** Alias for delay. */\n#define USBD_Delay          HAL_Delay\n\n/* DEBUG macros */\n\n#if (USBD_DEBUG_LEVEL > 0)\n#define USBD_UsrLog(...)    printf(__VA_ARGS__);\\\n                            printf(\"\\n\");\n#else\n#define USBD_UsrLog(...)\n#endif\n\n#if (USBD_DEBUG_LEVEL > 1)\n\n#define USBD_ErrLog(...)    printf(\"ERROR: \") ;\\\n                            printf(__VA_ARGS__);\\\n                            printf(\"\\n\");\n#else\n#define USBD_ErrLog(...)\n#endif\n\n#if (USBD_DEBUG_LEVEL > 2)\n#define USBD_DbgLog(...)    printf(\"DEBUG : \") ;\\\n                            printf(__VA_ARGS__);\\\n                            printf(\"\\n\");\n#else\n#define USBD_DbgLog(...)\n#endif\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CONF_Exported_Types USBD_CONF_Exported_Types\n  * @brief Types.\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @defgroup USBD_CONF_Exported_FunctionsPrototype USBD_CONF_Exported_FunctionsPrototype\n  * @brief Declaration of public functions for Usb device.\n  * @{\n  */\n\n/* Exported functions -------------------------------------------------------*/\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USBD_CONF__H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/common_inc.h",
    "content": "#ifndef REF_STM32F4_COMMON_INC_H\n#define REF_STM32F4_COMMON_INC_H\n\n#define CONFIG_FW_VERSION 1.0\n\n/*---------------------------- C Scope ---------------------------*/\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n\n#include \"FreeRTOS.h\"\n#include \"task.h\"\n#include \"main.h\"\n#include \"cmsis_os.h\"\n#include \"freertos_inc.h\"\n#include \"adc.h\"\n#include \"tim.h\"\n#include \"time_utils.h\"\n\nvoid Main(void);\n\nextern uint64_t serialNumber;\nextern char serialNumberStr[13];\n\n\n#ifdef __cplusplus\n}\n\n/*---------------------------- C++ Scope ---------------------------*/\n#include \"communication.hpp\"\n#include \"eeprom_interface.h\"\n#include \"U8g2lib.hpp\"\n#include \"MPU6050.hpp\"\n#include \"encoder.hpp\"\n#include \"analog.hpp\"\n#include \"pwm.hpp\"\n#include \"timer.hpp\"\n#include \"actuators/mintasca/sca.hpp\"\n#include \"actuators/ctrl_step/ctrl_step.hpp\"\n#include \"instances/dummy_robot.h\"\n\n\n#endif\n#endif //REF_STM32F4_COMMON_INC_H\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/freertos_inc.h",
    "content": "#ifndef __FREERTOS_H\n#define __FREERTOS_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n// List of semaphores\nextern osSemaphoreId sem_usb_irq;\nextern osSemaphoreId sem_uart4_dma;\nextern osSemaphoreId sem_uart5_dma;\nextern osSemaphoreId sem_usb_rx;\nextern osSemaphoreId sem_usb_tx;\nextern osSemaphoreId sem_can1_tx;\nextern osSemaphoreId sem_can2_tx;\n\n// List of Tasks\n/*--------------------------------- System Tasks -------------------------------------*/\nextern osThreadId_t defaultTaskHandle;      // Usage: 2000 Bytes stack\nextern osThreadId_t commTaskHandle;         // Usage: 48000 Bytes stack\nextern osThreadId_t usbIrqTaskHandle;       // Usage: 512  Bytes stack\nextern osThreadId_t usbServerTaskHandle;    // Usage: 2048 Bytes stack\nextern osThreadId_t uartServerTaskHandle;   // Usage: 2048 Bytes stack\n\n/*---------------------------------- User Tasks --------------------------------------*/\nextern osThreadId_t oledTaskHandle;         // Usage: 4000 Bytes stack\nextern osThreadId_t controlLoopFixUpdateHandle;  // Usage: 4000 Bytes stack\n\n/*---------------- 60K (used) / 64K (for FreeRTOS on ccram) ------------------*/\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/main.cpp",
    "content": "#include \"common_inc.h\"\r\n\r\n\r\n// On-board Screen, can choose from hi2c2 or hi2c0(soft i2c)\r\nSSD1306 oled(&hi2c0);\r\n// On-board Sensor, used hi2c1\r\nMPU6050 mpu6050(&hi2c1);\r\n// 5 User-Timers, can choose from htim7/htim10/htim11/htim13/htim14\r\nTimer timerCtrlLoop(&htim7, 200);\r\n// 2x2-channel PWMs, used htim9 & htim12, each has 2-channel outputs\r\nPWM pwm(21000, 21000);\r\n// Robot instance\r\nDummyRobot dummy(&hcan1);\r\n\r\n\r\n/* Thread Definitions -----------------------------------------------------*/\r\nosThreadId_t controlLoopFixUpdateHandle;\r\nvoid ThreadControlLoopFixUpdate(void* argument)\r\n{\r\n    for (;;)\r\n    {\r\n        // Suspended here until got Notification.\r\n        ulTaskNotifyTake(pdTRUE, portMAX_DELAY);\r\n\r\n        if (dummy.IsEnabled())\r\n        {\r\n            // Send control command to Motors & update Joint states\r\n            switch (dummy.commandMode)\r\n            {\r\n                case DummyRobot::COMMAND_TARGET_POINT_SEQUENTIAL:\r\n                case DummyRobot::COMMAND_TARGET_POINT_INTERRUPTABLE:\r\n                case DummyRobot::COMMAND_CONTINUES_TRAJECTORY:\r\n                    dummy.MoveJoints(dummy.targetJoints);\r\n                    dummy.UpdateJointPose6D();\r\n                    break;\r\n                case DummyRobot::COMMAND_MOTOR_TUNING:\r\n                    dummy.tuningHelper.Tick(10);\r\n                    dummy.UpdateJointPose6D();\r\n                    break;\r\n            }\r\n        } else\r\n        {\r\n            // Just update Joint states\r\n            dummy.UpdateJointAngles();\r\n            dummy.UpdateJointPose6D();\r\n        }\r\n    }\r\n}\r\n\r\n\r\nosThreadId_t ControlLoopUpdateHandle;\r\nvoid ThreadControlLoopUpdate(void* argument)\r\n{\r\n    for (;;)\r\n    {\r\n        dummy.commandHandler.ParseCommand(dummy.commandHandler.Pop(osWaitForever));\r\n    }\r\n}\r\n\r\n\r\nosThreadId_t oledTaskHandle;\r\nvoid ThreadOledUpdate(void* argument)\r\n{\r\n    uint32_t t = micros();\r\n    char buf[16];\r\n    char cmdModeNames[4][4] = {\"SEQ\", \"INT\", \"TRJ\", \"TUN\"};\r\n\r\n    for (;;)\r\n    {\r\n        mpu6050.Update(true);\r\n\r\n        oled.clearBuffer();\r\n        oled.setFont(u8g2_font_5x8_tr);\r\n        oled.setCursor(0, 10);\r\n        oled.printf(\"IMU:%.3f/%.3f\", mpu6050.data.ax, mpu6050.data.ay);\r\n        oled.setCursor(85, 10);\r\n        oled.printf(\"| FPS:%lu\", 1000000 / (micros() - t));\r\n        t = micros();\r\n\r\n        oled.drawBox(0, 15, 128, 3);\r\n        oled.setCursor(0, 30);\r\n        oled.printf(\">%3d|%3d|%3d|%3d|%3d|%3d\",\r\n                    (int) roundf(dummy.currentJoints.a[0]), (int) roundf(dummy.currentJoints.a[1]),\r\n                    (int) roundf(dummy.currentJoints.a[2]), (int) roundf(dummy.currentJoints.a[3]),\r\n                    (int) roundf(dummy.currentJoints.a[4]), (int) roundf(dummy.currentJoints.a[5]));\r\n\r\n        oled.drawBox(40, 35, 128, 24);\r\n        oled.setFont(u8g2_font_6x12_tr);\r\n        oled.setDrawColor(0);\r\n        oled.setCursor(42, 45);\r\n        oled.printf(\"%4d|%4d|%4d\", (int) roundf(dummy.currentPose6D.X),\r\n                    (int) roundf(dummy.currentPose6D.Y), (int) roundf(dummy.currentPose6D.Z));\r\n        oled.setCursor(42, 56);\r\n        oled.printf(\"%4d|%4d|%4d\", (int) roundf(dummy.currentPose6D.A),\r\n                    (int) roundf(dummy.currentPose6D.B), (int) roundf(dummy.currentPose6D.C));\r\n        oled.setDrawColor(1);\r\n        oled.setCursor(0, 45);\r\n        oled.printf(\"[XYZ]:\");\r\n        oled.setCursor(0, 56);\r\n        oled.printf(\"[ABC]:\");\r\n\r\n        oled.setFont(u8g2_font_10x20_tr);\r\n        oled.setCursor(0, 78);\r\n        if (dummy.IsEnabled())\r\n        {\r\n            for (int i = 1; i <= 6; i++)\r\n                buf[i - 1] = (dummy.jointsStateFlag & (1 << i) ? '*' : '_');\r\n            buf[6] = 0;\r\n            oled.printf(\"[%s] %s\", cmdModeNames[dummy.commandMode - 1], buf);\r\n        } else\r\n        {\r\n            oled.printf(\"[%s] %s\", cmdModeNames[dummy.commandMode - 1], \"======\");\r\n        }\r\n\r\n        oled.sendBuffer();\r\n    }\r\n}\r\n\r\n\r\n/* Timer Callbacks -------------------------------------------------------*/\r\nvoid OnTimer7Callback()\r\n{\r\n    BaseType_t xHigherPriorityTaskWoken = pdFALSE;\r\n\r\n    // Wake & invoke thread IMMEDIATELY.\r\n    vTaskNotifyGiveFromISR(TaskHandle_t(controlLoopFixUpdateHandle), &xHigherPriorityTaskWoken);\r\n    portYIELD_FROM_ISR(xHigherPriorityTaskWoken);\r\n}\r\n\r\n\r\n/* Default Entry -------------------------------------------------------*/\r\nvoid Main(void)\r\n{\r\n    // Init all communication staff, including USB-CDC/VCP/UART/CAN etc.\r\n    InitCommunication();\r\n\r\n    // Init Robot.\r\n    dummy.Init();\r\n\r\n    // Init IMU.\r\n    do\r\n    {\r\n        mpu6050.Init();\r\n        osDelay(100);\r\n    } while (!mpu6050.testConnection());\r\n    mpu6050.InitFilter(200, 100, 50);\r\n\r\n    // Init OLED 128x80.\r\n    oled.Init();\r\n    pwm.Start();\r\n\r\n    // Init & Run User Threads.\r\n    const osThreadAttr_t controlLoopTask_attributes = {\r\n        .name = \"ControlLoopFixUpdateTask\",\r\n        .stack_size = 2000,\r\n        .priority = (osPriority_t) osPriorityRealtime,\r\n    };\r\n    controlLoopFixUpdateHandle = osThreadNew(ThreadControlLoopFixUpdate, nullptr,\r\n                                             &controlLoopTask_attributes);\r\n\r\n    const osThreadAttr_t ControlLoopUpdateTask_attributes = {\r\n        .name = \"ControlLoopUpdateTask\",\r\n        .stack_size = 2000,\r\n        .priority = (osPriority_t) osPriorityNormal,\r\n    };\r\n    ControlLoopUpdateHandle = osThreadNew(ThreadControlLoopUpdate, nullptr,\r\n                                          &ControlLoopUpdateTask_attributes);\r\n\r\n    const osThreadAttr_t oledTask_attributes = {\r\n        .name = \"OledTask\",\r\n        .stack_size = 2000,\r\n        .priority = (osPriority_t) osPriorityNormal,   // should >= Normal\r\n    };\r\n    oledTaskHandle = osThreadNew(ThreadOledUpdate, nullptr, &oledTask_attributes);\r\n\r\n    // Start Timer Callbacks.\r\n    timerCtrlLoop.SetCallback(OnTimer7Callback);\r\n    timerCtrlLoop.Start();\r\n\r\n    // System started, light switch-led up.\r\n    Respond(*uart4StreamOutputPtr, \"[sys] Heap remain: %d Bytes\\n\", xPortGetMinimumEverFreeHeapSize());\r\n    pwm.SetDuty(PWM::CH_A1, 0.5);\r\n}\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/protocols/ascii_protocol.cpp",
    "content": "#include \"common_inc.h\"\r\n\r\nextern DummyRobot dummy;\r\n\r\n\r\nvoid OnUsbAsciiCmd(const char* _cmd, size_t _len, StreamSink &_responseChannel)\r\n{\r\n    /*---------------------------- ↓ Add Your CMDs Here ↓ -----------------------------*/\r\n    if (_cmd[0] == '!' || !dummy.IsEnabled())\r\n    {\r\n        std::string s(_cmd);\r\n        if (s.find(\"STOP\") != std::string::npos)\r\n        {\r\n            dummy.commandHandler.EmergencyStop();\r\n            Respond(_responseChannel, \"Stopped ok\");\r\n        } else if (s.find(\"START\") != std::string::npos)\r\n        {\r\n            dummy.SetEnable(true);\r\n            Respond(_responseChannel, \"Started ok\");\r\n        } else if (s.find(\"DISABLE\") != std::string::npos)\r\n        {\r\n            dummy.SetEnable(false);\r\n            Respond(_responseChannel, \"Disabled ok\");\r\n        }\r\n    } else if (_cmd[0] == '#')\r\n    {\r\n        std::string s(_cmd);\r\n        if (s.find(\"GETJPOS\") != std::string::npos)\r\n        {\r\n            Respond(_responseChannel, \"ok %.2f %.2f %.2f %.2f %.2f %.2f\",\r\n                    dummy.currentJoints.a[0], dummy.currentJoints.a[1],\r\n                    dummy.currentJoints.a[2], dummy.currentJoints.a[3],\r\n                    dummy.currentJoints.a[4], dummy.currentJoints.a[5]);\r\n        } else if (s.find(\"GETLPOS\") != std::string::npos)\r\n        {\r\n            dummy.UpdateJointPose6D();\r\n            Respond(_responseChannel, \"ok %.2f %.2f %.2f %.2f %.2f %.2f\",\r\n                    dummy.currentPose6D.X, dummy.currentPose6D.Y,\r\n                    dummy.currentPose6D.Z, dummy.currentPose6D.A,\r\n                    dummy.currentPose6D.B, dummy.currentPose6D.C);\r\n        } else if (s.find(\"CMDMODE\") != std::string::npos)\r\n        {\r\n            uint32_t mode;\r\n            sscanf(_cmd, \"#CMDMODE %lu\", &mode);\r\n            dummy.SetCommandMode(mode);\r\n            Respond(_responseChannel, \"Set command mode to [%lu]\", mode);\r\n        } else\r\n            Respond(_responseChannel, \"ok\");\r\n    } else if (_cmd[0] == '>' || _cmd[0] == '@')\r\n    {\r\n        uint32_t freeSize = dummy.commandHandler.Push(_cmd);\r\n        Respond(_responseChannel, \"%d\", freeSize);\r\n    }\r\n\r\n/*---------------------------- ↑ Add Your CMDs Here ↑ -----------------------------*/\r\n}\r\n\r\n\r\nvoid OnUart4AsciiCmd(const char* _cmd, size_t _len, StreamSink &_responseChannel)\r\n{\r\n    /*---------------------------- ↓ Add Your CMDs Here ↓ -----------------------------*/\r\n    if (_cmd[0] == '!' || !dummy.IsEnabled())\r\n    {\r\n        std::string s(_cmd);\r\n        if (s.find(\"STOP\") != std::string::npos)\r\n        {\r\n            dummy.commandHandler.EmergencyStop();\r\n            Respond(_responseChannel, \"Stopped ok\");\r\n        } else if (s.find(\"START\") != std::string::npos)\r\n        {\r\n            dummy.SetEnable(true);\r\n            Respond(_responseChannel, \"Started ok\");\r\n        } else if (s.find(\"DISABLE\") != std::string::npos)\r\n        {\r\n            dummy.SetEnable(false);\r\n            Respond(_responseChannel, \"Disabled ok\");\r\n        }\r\n    } else if (_cmd[0] == '#')\r\n    {\r\n        std::string s(_cmd);\r\n        if (s.find(\"GETJPOS\") != std::string::npos)\r\n        {\r\n            Respond(_responseChannel, \"ok %.2f %.2f %.2f %.2f %.2f %.2f\",\r\n                    dummy.currentJoints.a[0], dummy.currentJoints.a[1],\r\n                    dummy.currentJoints.a[2], dummy.currentJoints.a[3],\r\n                    dummy.currentJoints.a[4], dummy.currentJoints.a[5]);\r\n        } else if (s.find(\"GETLPOS\") != std::string::npos)\r\n        {\r\n            dummy.UpdateJointPose6D();\r\n            Respond(_responseChannel, \"ok %.2f %.2f %.2f %.2f %.2f %.2f\",\r\n                    dummy.currentPose6D.X, dummy.currentPose6D.Y,\r\n                    dummy.currentPose6D.Z, dummy.currentPose6D.A,\r\n                    dummy.currentPose6D.B, dummy.currentPose6D.C);\r\n        } else if (s.find(\"CMDMODE\") != std::string::npos)\r\n        {\r\n            uint32_t mode;\r\n            sscanf(_cmd, \"#CMDMODE %lu\", &mode);\r\n            dummy.SetCommandMode(mode);\r\n            Respond(_responseChannel, \"Set command mode to [%lu]\", mode);\r\n        } else\r\n            Respond(_responseChannel, \"ok\");\r\n    } else if (_cmd[0] == '>' || _cmd[0] == '@')\r\n    {\r\n        uint32_t freeSize = dummy.commandHandler.Push(_cmd);\r\n        Respond(_responseChannel, \"%d\", freeSize);\r\n    }\r\n/*---------------------------- ↑ Add Your CMDs Here ↑ -----------------------------*/\r\n}\r\n\r\n\r\nvoid OnUart5AsciiCmd(const char* _cmd, size_t _len, StreamSink &_responseChannel)\r\n{\r\n    /*---------------------------- ↓ Add Your CMDs Here ↓ -----------------------------*/\r\n\r\n/*---------------------------- ↑ Add Your CMDs Here ↑ -----------------------------*/\r\n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/protocols/can_protocol.cpp",
    "content": "#include \"common_inc.h\"\n\n\n// Used for response CAN message.\nstatic CAN_TxHeaderTypeDef txHeader =\n    {\n        .StdId = 0,\n        .ExtId = 0,\n        .IDE = CAN_ID_STD,\n        .RTR = CAN_RTR_DATA,\n        .DLC = 8,\n        .TransmitGlobalTime = DISABLE\n    };\n\nextern DummyRobot dummy;\n\nvoid OnCanMessage(CAN_context* canCtx, CAN_RxHeaderTypeDef* rxHeader, uint8_t* data)\n{\n    // Common CAN message callback, uses ID 32~0x7FF.\n    if (canCtx->handle->Instance == CAN1)\n    {\n        uint8_t id = rxHeader->StdId >> 7; // 4Bits ID & 7Bits Msg\n        uint8_t cmd = rxHeader->StdId & 0x7F; // 4Bits ID & 7Bits Msg\n\n        /*----------------------- ↓ Add Your CAN1 Packet Protocol Here ↓ ------------------------*/\n        switch (cmd)\n        {\n            case 0x23:\n                dummy.motorJ[id]->UpdateAngleCallback(*(float*) (data), data[4]);\n                break;\n            default:\n                break;\n        }\n\n        dummy.UpdateJointAnglesCallback();\n\n    } else if (canCtx->handle->Instance == CAN2)\n    {\n        /*----------------------- ↓ Add Your CAN2 Packet Protocol Here ↓ ------------------------*/\n    }\n    /*----------------------- ↑ Add Your Packet Protocol Here ↑ ------------------------*/\n}"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/UserApp/protocols/cmd_protocol.cpp",
    "content": "\r\n#include \"common_inc.h\"\r\n\r\n/*----------------- 1.Add Your Extern Variables Here (Optional) ------------------*/\r\nextern DummyRobot dummy;\r\n\r\nclass HelperFunctions\r\n{\r\npublic:\r\n    /*--------------- 2.Add Your Helper Functions Helper Here (optional) ----------------*/\r\n    float GetTemperatureHelper()\r\n    { return AdcGetChipTemperature(); }\r\n\r\n} staticFunctions;\r\n\r\n\r\n// Define options that intractable with \"reftool\".\r\nstatic inline auto MakeObjTree()\r\n{\r\n    /*--------------- 3.Add Your Protocol Variables & Functions Here ----------------*/\r\n    return make_protocol_member_list(\r\n        // Add Read-Only Variables\r\n        make_protocol_ro_property(\"serial_number\", &serialNumber),\r\n        make_protocol_function(\"get_temperature\", staticFunctions, &HelperFunctions::GetTemperatureHelper),\r\n        make_protocol_object(\"robot\", dummy.MakeProtocolDefinitions())\r\n    );\r\n}\r\n\r\n\r\nCOMMIT_PROTOCOL\r\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/startup/startup_stm32f405xx.s",
    "content": "/**\n  ******************************************************************************\n  * @file      startup_stm32f405xx.s\n  * @author    MCD Application Team\n  * @brief     STM32F405xx Devices vector table for GCC based toolchains. \n  *            This module performs:\n  *                - Set the initial SP\n  *                - Set the initial PC == Reset_Handler,\n  *                - Set the vector table entries with the exceptions ISR address\n  *                - Branches to main in the C library (which eventually\n  *                  calls main()).\n  *            After Reset the Cortex-M4 processor is in Thread mode,\n  *            priority is Privileged, and the Stack is set to Main.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n    \n  .syntax unified\n  .cpu cortex-m4\n  .fpu softvfp\n  .thumb\n\n.global  g_pfnVectors\n.global  Default_Handler\n\n/* start address for the initialization values of the .data section. \ndefined in linker script */\n.word  _sidata\n/* start address for the .data section. defined in linker script */  \n.word  _sdata\n/* end address for the .data section. defined in linker script */\n.word  _edata\n/* start address for the .bss section. defined in linker script */\n.word  _sbss\n/* end address for the .bss section. defined in linker script */\n.word  _ebss\n/* stack used for SystemInit_ExtMemCtl; always internal RAM used */\n\n/**\n * @brief  This is the code that gets called when the processor first\n *          starts execution following a reset event. Only the absolutely\n *          necessary set is performed, after which the application\n *          supplied main() routine is called. \n * @param  None\n * @retval : None\n*/\n\n    .section  .text.Reset_Handler\n  .weak  Reset_Handler\n  .type  Reset_Handler, %function\nReset_Handler:  \n  ldr   sp, =_estack     /* set stack pointer */\n\n/* Copy the data segment initializers from flash to SRAM */  \n  ldr r0, =_sdata\n  ldr r1, =_edata\n  ldr r2, =_sidata\n  movs r3, #0\n  b LoopCopyDataInit\n\nCopyDataInit:\n  ldr r4, [r2, r3]\n  str r4, [r0, r3]\n  adds r3, r3, #4\n\nLoopCopyDataInit:\n  adds r4, r0, r3\n  cmp r4, r1\n  bcc CopyDataInit\n  \n/* Zero fill the bss segment. */\n  ldr r2, =_sbss\n  ldr r4, =_ebss\n  movs r3, #0\n  b LoopFillZerobss\n\nFillZerobss:\n  str  r3, [r2]\n  adds r2, r2, #4\n\nLoopFillZerobss:\n  cmp r2, r4\n  bcc FillZerobss\n\n/* Call the clock system intitialization function.*/\n  bl  SystemInit   \n/* Call static constructors */\n    bl __libc_init_array\n/* Call the application's entry point.*/\n  bl  main\n  bx  lr    \n.size  Reset_Handler, .-Reset_Handler\n\n/**\n * @brief  This is the code that gets called when the processor receives an \n *         unexpected interrupt.  This simply enters an infinite loop, preserving\n *         the system state for examination by a debugger.\n * @param  None     \n * @retval None       \n*/\n    .section  .text.Default_Handler,\"ax\",%progbits\nDefault_Handler:\nInfinite_Loop:\n  b  Infinite_Loop\n  .size  Default_Handler, .-Default_Handler\n/******************************************************************************\n*\n* The minimal vector table for a Cortex M3. Note that the proper constructs\n* must be placed on this to ensure that it ends up at physical address\n* 0x0000.0000.\n* \n*******************************************************************************/\n   .section  .isr_vector,\"a\",%progbits\n  .type  g_pfnVectors, %object\n  .size  g_pfnVectors, .-g_pfnVectors\n    \n\n\t\ng_pfnVectors:\n  .word  _estack\n  .word  Reset_Handler\n\n  .word  NMI_Handler\n  .word  HardFault_Handler\n  .word  MemManage_Handler\n  .word  BusFault_Handler\n  .word  UsageFault_Handler\n  .word  0\n  .word  0\n  .word  0\n  .word  0\n  .word  SVC_Handler\n  .word  DebugMon_Handler\n  .word  0\n  .word  PendSV_Handler\n  .word  SysTick_Handler\n  \n  /* External Interrupts */\n  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        \n  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        \n  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            \n  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      \n  .word     FLASH_IRQHandler                  /* FLASH                        */                                          \n  .word     RCC_IRQHandler                    /* RCC                          */                                            \n  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        \n  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          \n  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          \n  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          \n  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          \n  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  \n  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   \n  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   \n  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   \n  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   \n  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   \n  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   \n  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   \n  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         \n  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          \n  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          \n  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          \n  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          \n  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         \n  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         \n  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */\n  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          \n  .word     TIM2_IRQHandler                   /* TIM2                         */                   \n  .word     TIM3_IRQHandler                   /* TIM3                         */                   \n  .word     TIM4_IRQHandler                   /* TIM4                         */                   \n  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          \n  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          \n  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          \n  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            \n  .word     SPI1_IRQHandler                   /* SPI1                         */                   \n  .word     SPI2_IRQHandler                   /* SPI2                         */                   \n  .word     USART1_IRQHandler                 /* USART1                       */                   \n  .word     USART2_IRQHandler                 /* USART2                       */                   \n  .word     USART3_IRQHandler                 /* USART3                       */                   \n  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          \n  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 \n  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       \n  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         \n  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         \n  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */\n  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          \n  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          \n  .word     FSMC_IRQHandler                   /* FSMC                         */                   \n  .word     SDIO_IRQHandler                   /* SDIO                         */                   \n  .word     TIM5_IRQHandler                   /* TIM5                         */                   \n  .word     SPI3_IRQHandler                   /* SPI3                         */                   \n  .word     UART4_IRQHandler                  /* UART4                        */                   \n  .word     UART5_IRQHandler                  /* UART5                        */                   \n  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   \n  .word     TIM7_IRQHandler                   /* TIM7                         */\n  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   \n  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   \n  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   \n  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   \n  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   \n  .word     0                                 /* Reserved                     */                   \n  .word     0                                 /* Reserved                     */                     \n  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          \n  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          \n  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          \n  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          \n  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   \n  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   \n  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   \n  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   \n  .word     USART6_IRQHandler                 /* USART6                       */                    \n  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          \n  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          \n  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   \n  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   \n  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         \n  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   \n  .word     0                                 /* Reserved                         */                   \n  .word     0                                 /* Reserved                  */                   \n  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */\n  .word     FPU_IRQHandler                    /* FPU                          */\n\n                      \n/*******************************************************************************\n*\n* Provide weak aliases for each Exception handler to the Default_Handler. \n* As they are weak aliases, any function with the same name will override \n* this definition.\n* \n*******************************************************************************/\n   .weak      NMI_Handler\n   .thumb_set NMI_Handler,Default_Handler\n  \n   .weak      HardFault_Handler\n   .thumb_set HardFault_Handler,Default_Handler\n  \n   .weak      MemManage_Handler\n   .thumb_set MemManage_Handler,Default_Handler\n  \n   .weak      BusFault_Handler\n   .thumb_set BusFault_Handler,Default_Handler\n\n   .weak      UsageFault_Handler\n   .thumb_set UsageFault_Handler,Default_Handler\n\n   .weak      SVC_Handler\n   .thumb_set SVC_Handler,Default_Handler\n\n   .weak      DebugMon_Handler\n   .thumb_set DebugMon_Handler,Default_Handler\n\n   .weak      PendSV_Handler\n   .thumb_set PendSV_Handler,Default_Handler\n\n   .weak      SysTick_Handler\n   .thumb_set SysTick_Handler,Default_Handler              \n  \n   .weak      WWDG_IRQHandler                   \n   .thumb_set WWDG_IRQHandler,Default_Handler      \n                  \n   .weak      PVD_IRQHandler      \n   .thumb_set PVD_IRQHandler,Default_Handler\n               \n   .weak      TAMP_STAMP_IRQHandler            \n   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler\n            \n   .weak      RTC_WKUP_IRQHandler                  \n   .thumb_set RTC_WKUP_IRQHandler,Default_Handler\n            \n   .weak      FLASH_IRQHandler         \n   .thumb_set FLASH_IRQHandler,Default_Handler\n                  \n   .weak      RCC_IRQHandler      \n   .thumb_set RCC_IRQHandler,Default_Handler\n                  \n   .weak      EXTI0_IRQHandler         \n   .thumb_set EXTI0_IRQHandler,Default_Handler\n                  \n   .weak      EXTI1_IRQHandler         \n   .thumb_set EXTI1_IRQHandler,Default_Handler\n                     \n   .weak      EXTI2_IRQHandler         \n   .thumb_set EXTI2_IRQHandler,Default_Handler \n                 \n   .weak      EXTI3_IRQHandler         \n   .thumb_set EXTI3_IRQHandler,Default_Handler\n                        \n   .weak      EXTI4_IRQHandler         \n   .thumb_set EXTI4_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream0_IRQHandler               \n   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler\n         \n   .weak      DMA1_Stream1_IRQHandler               \n   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream2_IRQHandler               \n   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream3_IRQHandler               \n   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler \n                 \n   .weak      DMA1_Stream4_IRQHandler              \n   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream5_IRQHandler               \n   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream6_IRQHandler               \n   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler\n                  \n   .weak      ADC_IRQHandler      \n   .thumb_set ADC_IRQHandler,Default_Handler\n               \n   .weak      CAN1_TX_IRQHandler   \n   .thumb_set CAN1_TX_IRQHandler,Default_Handler\n            \n   .weak      CAN1_RX0_IRQHandler                  \n   .thumb_set CAN1_RX0_IRQHandler,Default_Handler\n                           \n   .weak      CAN1_RX1_IRQHandler                  \n   .thumb_set CAN1_RX1_IRQHandler,Default_Handler\n            \n   .weak      CAN1_SCE_IRQHandler                  \n   .thumb_set CAN1_SCE_IRQHandler,Default_Handler\n            \n   .weak      EXTI9_5_IRQHandler   \n   .thumb_set EXTI9_5_IRQHandler,Default_Handler\n            \n   .weak      TIM1_BRK_TIM9_IRQHandler            \n   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler\n            \n   .weak      TIM1_UP_TIM10_IRQHandler            \n   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler\n      \n   .weak      TIM1_TRG_COM_TIM11_IRQHandler      \n   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler\n      \n   .weak      TIM1_CC_IRQHandler   \n   .thumb_set TIM1_CC_IRQHandler,Default_Handler\n                  \n   .weak      TIM2_IRQHandler            \n   .thumb_set TIM2_IRQHandler,Default_Handler\n                  \n   .weak      TIM3_IRQHandler            \n   .thumb_set TIM3_IRQHandler,Default_Handler\n                  \n   .weak      TIM4_IRQHandler            \n   .thumb_set TIM4_IRQHandler,Default_Handler\n                  \n   .weak      I2C1_EV_IRQHandler   \n   .thumb_set I2C1_EV_IRQHandler,Default_Handler\n                     \n   .weak      I2C1_ER_IRQHandler   \n   .thumb_set I2C1_ER_IRQHandler,Default_Handler\n                     \n   .weak      I2C2_EV_IRQHandler   \n   .thumb_set I2C2_EV_IRQHandler,Default_Handler\n                  \n   .weak      I2C2_ER_IRQHandler   \n   .thumb_set I2C2_ER_IRQHandler,Default_Handler\n                           \n   .weak      SPI1_IRQHandler            \n   .thumb_set SPI1_IRQHandler,Default_Handler\n                        \n   .weak      SPI2_IRQHandler            \n   .thumb_set SPI2_IRQHandler,Default_Handler\n                  \n   .weak      USART1_IRQHandler      \n   .thumb_set USART1_IRQHandler,Default_Handler\n                     \n   .weak      USART2_IRQHandler      \n   .thumb_set USART2_IRQHandler,Default_Handler\n                     \n   .weak      USART3_IRQHandler      \n   .thumb_set USART3_IRQHandler,Default_Handler\n                  \n   .weak      EXTI15_10_IRQHandler               \n   .thumb_set EXTI15_10_IRQHandler,Default_Handler\n               \n   .weak      RTC_Alarm_IRQHandler               \n   .thumb_set RTC_Alarm_IRQHandler,Default_Handler\n            \n   .weak      OTG_FS_WKUP_IRQHandler         \n   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler\n            \n   .weak      TIM8_BRK_TIM12_IRQHandler         \n   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler\n         \n   .weak      TIM8_UP_TIM13_IRQHandler            \n   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler\n         \n   .weak      TIM8_TRG_COM_TIM14_IRQHandler      \n   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler\n      \n   .weak      TIM8_CC_IRQHandler   \n   .thumb_set TIM8_CC_IRQHandler,Default_Handler\n                  \n   .weak      DMA1_Stream7_IRQHandler               \n   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler\n                     \n   .weak      FSMC_IRQHandler            \n   .thumb_set FSMC_IRQHandler,Default_Handler\n                     \n   .weak      SDIO_IRQHandler            \n   .thumb_set SDIO_IRQHandler,Default_Handler\n                     \n   .weak      TIM5_IRQHandler            \n   .thumb_set TIM5_IRQHandler,Default_Handler\n                     \n   .weak      SPI3_IRQHandler            \n   .thumb_set SPI3_IRQHandler,Default_Handler\n                     \n   .weak      UART4_IRQHandler         \n   .thumb_set UART4_IRQHandler,Default_Handler\n                  \n   .weak      UART5_IRQHandler         \n   .thumb_set UART5_IRQHandler,Default_Handler\n                  \n   .weak      TIM6_DAC_IRQHandler                  \n   .thumb_set TIM6_DAC_IRQHandler,Default_Handler\n               \n   .weak      TIM7_IRQHandler            \n   .thumb_set TIM7_IRQHandler,Default_Handler\n         \n   .weak      DMA2_Stream0_IRQHandler               \n   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler\n               \n   .weak      DMA2_Stream1_IRQHandler               \n   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream2_IRQHandler               \n   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler\n            \n   .weak      DMA2_Stream3_IRQHandler               \n   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler\n            \n   .weak      DMA2_Stream4_IRQHandler               \n   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler\n            \n   .weak      CAN2_TX_IRQHandler   \n   .thumb_set CAN2_TX_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_RX0_IRQHandler                  \n   .thumb_set CAN2_RX0_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_RX1_IRQHandler                  \n   .thumb_set CAN2_RX1_IRQHandler,Default_Handler\n                           \n   .weak      CAN2_SCE_IRQHandler                  \n   .thumb_set CAN2_SCE_IRQHandler,Default_Handler\n                           \n   .weak      OTG_FS_IRQHandler      \n   .thumb_set OTG_FS_IRQHandler,Default_Handler\n                     \n   .weak      DMA2_Stream5_IRQHandler               \n   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream6_IRQHandler               \n   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler\n                  \n   .weak      DMA2_Stream7_IRQHandler               \n   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler\n                  \n   .weak      USART6_IRQHandler      \n   .thumb_set USART6_IRQHandler,Default_Handler\n                        \n   .weak      I2C3_EV_IRQHandler   \n   .thumb_set I2C3_EV_IRQHandler,Default_Handler\n                        \n   .weak      I2C3_ER_IRQHandler   \n   .thumb_set I2C3_ER_IRQHandler,Default_Handler\n                        \n   .weak      OTG_HS_EP1_OUT_IRQHandler         \n   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler\n               \n   .weak      OTG_HS_EP1_IN_IRQHandler            \n   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler\n               \n   .weak      OTG_HS_WKUP_IRQHandler         \n   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler\n            \n   .weak      OTG_HS_IRQHandler      \n   .thumb_set OTG_HS_IRQHandler,Default_Handler\n                                                     \n   .weak      HASH_RNG_IRQHandler                  \n   .thumb_set HASH_RNG_IRQHandler,Default_Handler   \n\n   .weak      FPU_IRQHandler                  \n   .thumb_set FPU_IRQHandler,Default_Handler  \n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n  \n\n"
  },
  {
    "path": "2.Firmware/Core-STM32F4-fw/stlink.cfg",
    "content": "# choose st-link/j-link/dap-link etc.\n#adapter driver cmsis-dap\n#transport select swd\nsource [find interface/stlink.cfg]\ntransport select hla_swd\n\n# 0x10000 = 64K Flash Size\n# set FLASH_SIZE 0x100000\n\nsource [find target/stm32f4x.cfg]\n\n# download speed = 1MHz\nadapter speed 10000"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/.cproject",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<?fileVersion 4.0.0?><cproject storage_type_id=\"org.eclipse.cdt.core.XmlProjectDescriptionStorage\">\n\t<storageModule moduleId=\"org.eclipse.cdt.core.settings\">\n\t\t<cconfiguration id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.2131378430\">\n\t\t\t<storageModule buildSystemId=\"org.eclipse.cdt.managedbuilder.core.configurationDataProvider\" id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.2131378430\" moduleId=\"org.eclipse.cdt.core.settings\" name=\"Debug\">\n\t\t\t\t<externalSettings />\n\t\t\t\t<extensions>\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.ELF\" point=\"org.eclipse.cdt.core.BinaryParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GASErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GmakeErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GLDErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.CWDLocator\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t\t<extension id=\"org.eclipse.cdt.core.GCCErrorParser\" point=\"org.eclipse.cdt.core.ErrorParser\" />\n\t\t\t\t</extensions>\n\t\t\t</storageModule>\n\t\t\t<storageModule moduleId=\"cdtBuildSystem\" version=\"4.0.0\">\n\t\t\t\t<configuration artifactExtension=\"elf\" artifactName=\"${ProjName}\" buildArtefactType=\"org.eclipse.cdt.build.core.buildArtefactType.exe\" buildProperties=\"org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug\" cleanCommand=\"rm -rf\" description=\"\" id=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug.2131378430\" name=\"Debug\" parent=\"fr.ac6.managedbuild.config.gnu.cross.exe.debug\" postannouncebuildStep=\"Generating hex and Printing size information:\" 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    "content": "#THIS FILE IS AUTO GENERATED FROM THE TEMPLATE! DO NOT CHANGE!\nset(CMAKE_SYSTEM_NAME Generic)\nset(CMAKE_SYSTEM_VERSION 1)\ncmake_minimum_required(VERSION 3.20)\n\n# specify cross compilers and tools\nset(CMAKE_C_COMPILER arm-none-eabi-gcc)\nset(CMAKE_CXX_COMPILER arm-none-eabi-g++)\nset(CMAKE_ASM_COMPILER arm-none-eabi-gcc)\nset(CMAKE_AR arm-none-eabi-ar)\nset(CMAKE_OBJCOPY arm-none-eabi-objcopy)\nset(CMAKE_OBJDUMP arm-none-eabi-objdump)\nset(SIZE arm-none-eabi-size)\nset(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)\n\n# project settings\nproject(Ctrl-Step-STM32-fw C CXX ASM)\nset(CMAKE_CXX_STANDARD 17)\nset(CMAKE_C_STANDARD 11)\n\n#Uncomment for hardware floating point\n#add_compile_definitions(ARM_MATH_CM4;ARM_MATH_MATRIX_CHECK;ARM_MATH_ROUNDING)\n#add_compile_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\n#add_link_options(-mfloat-abi=hard -mfpu=fpv4-sp-d16)\n\n#Uncomment for software floating point\n#add_compile_options(-mfloat-abi=soft)\n\nadd_compile_options(-mcpu=cortex-m3 -mthumb -mthumb-interwork)\nadd_compile_options(-ffunction-sections -fdata-sections -fno-common -fmessage-length=0)\n\n# uncomment to mitigate c++17 absolute addresses warnings\n#set(CMAKE_CXX_FLAGS \"${CMAKE_CXX_FLAGS} -Wno-register\")\n\nif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"Release\")\n    message(STATUS \"Maximum optimization for speed\")\n    add_compile_options(-Ofast)\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"RelWithDebInfo\")\n    message(STATUS \"Maximum optimization for speed, debug info included\")\n    add_compile_options(-Ofast -g)\nelseif (\"${CMAKE_BUILD_TYPE}\" STREQUAL \"MinSizeRel\")\n    message(STATUS \"Maximum optimization for size\")\n    add_compile_options(-Os)\nelse ()\n    message(STATUS \"Minimal optimization, debug info included\")\n    add_compile_options(-Og -g)\nendif ()\n\ninclude_directories(\n        Core/Inc\n        Drivers/STM32F1xx_HAL_Driver/Inc\n        Drivers/STM32F1xx_HAL_Driver/Inc/Legacy\n        Drivers/CMSIS/Device/ST/STM32F1xx/Include\n        Drivers/CMSIS/Include\n        Ctrl\n        Ctrl/Sensor\n        Ctrl/Signal\n        Ctrl/LowLevel\n        Ctrl/MotorControl\n        UserApp\n        Port\n)\n\nadd_definitions(-DUSE_HAL_DRIVER -D__MICROLIB -DSTM32F1 -DSTM32F1xx -DSTM32F103xB)\n\nfile(GLOB_RECURSE SOURCES\n        \"startup/*.*\"\n        \"Drivers/*.*\"\n        \"Core/*.*\"\n        \"Ctrl/*.*\"\n        \"UserApp/*.*\"\n        \"Port/*.*\"\n        )\n\nset(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/STM32F103CBTx_FLASH.ld)\n\nadd_link_options(-Wl,-gc-sections,--print-memory-usage,-Map=${PROJECT_BINARY_DIR}/${PROJECT_NAME}.map)\nadd_link_options(-mcpu=cortex-m3 -mthumb -mthumb-interwork)\nadd_link_options(-T ${LINKER_SCRIPT})\n\nadd_executable(${PROJECT_NAME}.elf ${SOURCES} ${LINKER_SCRIPT})\n\nset(HEX_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.hex)\nset(BIN_FILE ${PROJECT_BINARY_DIR}/${PROJECT_NAME}.bin)\n\nadd_custom_command(TARGET ${PROJECT_NAME}.elf POST_BUILD\n        COMMAND ${CMAKE_OBJCOPY} -Oihex $<TARGET_FILE:${PROJECT_NAME}.elf> ${HEX_FILE}\n        COMMAND ${CMAKE_OBJCOPY} -Obinary $<TARGET_FILE:${PROJECT_NAME}.elf> ${BIN_FILE}\n        COMMENT \"Building ${HEX_FILE}\nBuilding ${BIN_FILE}\")\n"
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    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/adc.h",
    "content": "/**\n  ******************************************************************************\n  * @file    adc.h\n  * @brief   This file contains all the function prototypes for\n  *          the adc.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __ADC_H__\n#define __ADC_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern ADC_HandleTypeDef hadc1;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_ADC1_Init(void);\n\n/* USER CODE BEGIN Prototypes */\nextern uint16_t whole_adc_data[2][12];\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __ADC_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
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  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/can.h",
    "content": "/**\n  ******************************************************************************\n  * @file    can.h\n  * @brief   This file contains all the function prototypes for\n  *          the can.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __CAN_H__\n#define __CAN_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\nextern CAN_HandleTypeDef hcan;\nextern CAN_TxHeaderTypeDef TxHeader;\nextern CAN_RxHeaderTypeDef RxHeader;\nextern uint8_t TxData[8];\nextern uint8_t RxData[8];\nextern uint32_t TxMailbox;\n/* USER CODE END Includes */\n\nextern CAN_HandleTypeDef hcan;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_CAN_Init(void);\n\n/* USER CODE BEGIN Prototypes */\nvoid CAN_Send(CAN_TxHeaderTypeDef* pHeader, uint8_t* data);\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CAN_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/dma.h",
    "content": "/**\n  ******************************************************************************\n  * @file    dma.h\n  * @brief   This file contains all the function prototypes for\n  *          the dma.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __DMA_H__\n#define __DMA_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* DMA memory to memory transfer handles -------------------------------------*/\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_DMA_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __DMA_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/gpio.h",
    "content": "/**\n  ******************************************************************************\n  * @file    gpio.h\n  * @brief   This file contains all the function prototypes for\n  *          the gpio.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __GPIO_H__\n#define __GPIO_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_GPIO_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/********** Button **********/\n/********** Button **********/\n/********** Button **********/\nvoid REIN_GPIO_Button_Init(void);  \t //GPIO初始??(Button)\n\n/********** HwElec **********/\n/********** HwElec **********/\n/********** HwElec **********/\nvoid REIN_GPIO_HwElec_Init(void);   \t//GPIO初始??(HwElec)\n\n/********** MT6816Base **********/\n/********** MT6816Base **********/\n/********** MT6816Base **********/\nvoid REIN_GPIO_MT6816_ABZ_Init(void);  //GPIO初始??(MT6816_ABZ)\nvoid REIN_GPIO_MT6816_SPI_Init(void);  //GPIO初始??(MT6916_SPI)\n\n/********** Modbus **********/\n/********** Modbus **********/\n/********** Modbus **********/\nvoid REIN_GPIO_Modbus_Init(void);\t\t\t//GPIO初始??(Modbus)\n\n/********** OLED **********/\n/********** OLED **********/\n/********** OLED **********/\nvoid REIN_GPIO_OLED_Init(void);\t\t\t //GPIO初始??(OLED)\n\n/********** SIGNAL **********/\n/********** SIGNAL **********/\n/********** SIGNAL **********/\nvoid REIN_GPIO_SIGNAL_COUNT_Init(void);\t\t//GPIO初始??(SIGNAL_COUNT)\nvoid REIN_GPIO_SIGNAL_COUNT_DeInit(void);\t//GPIO清理(SIGNAL_COUNT)\nvoid REIN_GPIO_SIGNAL_PWM_Init(void);\t\t\t//GPIO初始??(SIGNAL_PWM)\nvoid REIN_GPIO_SIGNAL_PWM_DeInit(void);\t\t//GPIO清理(SIGNAL_PWM)\n\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n#endif /*__ GPIO_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/main.h",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : main.h\n  * @brief          : Header for main.c file.\n  *                   This file contains the common defines of the application.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __MAIN_H\n#define __MAIN_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"stm32f1xx_hal.h\"\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Exported types ------------------------------------------------------------*/\n/* USER CODE BEGIN ET */\n\n/* USER CODE END ET */\n\n/* Exported constants --------------------------------------------------------*/\n/* USER CODE BEGIN EC */\n\n/* USER CODE END EC */\n\n/* Exported macro ------------------------------------------------------------*/\n/* USER CODE BEGIN EM */\n\n/* USER CODE END EM */\n\n/* Exported functions prototypes ---------------------------------------------*/\nvoid Error_Handler(void);\n\n/* USER CODE BEGIN EFP */\n\n/* USER CODE END EFP */\n\n/* Private defines -----------------------------------------------------------*/\n#define LED1_Pin GPIO_PIN_13\n#define LED1_GPIO_Port GPIOC\n#define LED2_Pin GPIO_PIN_14\n#define LED2_GPIO_Port GPIOC\n#define POWER_U_Pin GPIO_PIN_0\n#define POWER_U_GPIO_Port GPIOA\n#define DRV_TEMP_Pin GPIO_PIN_1\n#define DRV_TEMP_GPIO_Port GPIOA\n#define HW_ELEC_BM_Pin GPIO_PIN_2\n#define HW_ELEC_BM_GPIO_Port GPIOA\n#define HW_ELEC_BP_Pin GPIO_PIN_3\n#define HW_ELEC_BP_GPIO_Port GPIOA\n#define HW_ELEC_AM_Pin GPIO_PIN_4\n#define HW_ELEC_AM_GPIO_Port GPIOA\n#define HW_ELEC_AP_Pin GPIO_PIN_5\n#define HW_ELEC_AP_GPIO_Port GPIOA\n#define SIGNAL_COUNT_DIR_Pin GPIO_PIN_7\n#define SIGNAL_COUNT_DIR_GPIO_Port GPIOA\n#define SIGNAL_COUNT_DIR_EXTI_IRQn EXTI9_5_IRQn\n#define SIGNAL_COUNT_EN_Pin GPIO_PIN_0\n#define SIGNAL_COUNT_EN_GPIO_Port GPIOB\n#define SIGNAL_ALERT_Pin GPIO_PIN_1\n#define SIGNAL_ALERT_GPIO_Port GPIOB\n#define BUTTON2_Pin GPIO_PIN_2\n#define BUTTON2_GPIO_Port GPIOB\n#define HW_ELEC_BPWM_Pin GPIO_PIN_10\n#define HW_ELEC_BPWM_GPIO_Port GPIOB\n#define HW_ELEC_APWM_Pin GPIO_PIN_11\n#define HW_ELEC_APWM_GPIO_Port GPIOB\n#define BUTTON1_Pin GPIO_PIN_12\n#define BUTTON1_GPIO_Port GPIOB\n#define SPI1_CS_Pin GPIO_PIN_15\n#define SPI1_CS_GPIO_Port GPIOA\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __MAIN_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/spi.h",
    "content": "/**\n  ******************************************************************************\n  * @file    spi.h\n  * @brief   This file contains all the function prototypes for\n  *          the spi.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __SPI_H__\n#define __SPI_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern SPI_HandleTypeDef hspi1;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_SPI1_Init(void);\n\n/* USER CODE BEGIN Prototypes */\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __SPI_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/stm32f1xx_hal_conf.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f1xx_hal_conf.h\n  * @brief   HAL configuration file.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F1xx_HAL_CONF_H\n#define __STM32F1xx_HAL_CONF_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Exported types ------------------------------------------------------------*/\n/* Exported constants --------------------------------------------------------*/\n\n/* ########################## Module Selection ############################## */\n/**\n  * @brief This is the list of modules to be used in the HAL driver\n  */\n\n#define HAL_MODULE_ENABLED\n  #define HAL_ADC_MODULE_ENABLED\n/*#define HAL_CRYP_MODULE_ENABLED   */\n#define HAL_CAN_MODULE_ENABLED\n/*#define HAL_CAN_LEGACY_MODULE_ENABLED   */\n/*#define HAL_CEC_MODULE_ENABLED   */\n/*#define HAL_CORTEX_MODULE_ENABLED   */\n/*#define HAL_CRC_MODULE_ENABLED   */\n/*#define HAL_DAC_MODULE_ENABLED   */\n#define HAL_DMA_MODULE_ENABLED\n/*#define HAL_ETH_MODULE_ENABLED   */\n/*#define HAL_FLASH_MODULE_ENABLED   */\n#define HAL_GPIO_MODULE_ENABLED\n/*#define HAL_I2C_MODULE_ENABLED   */\n/*#define HAL_I2S_MODULE_ENABLED   */\n/*#define HAL_IRDA_MODULE_ENABLED   */\n/*#define HAL_IWDG_MODULE_ENABLED   */\n/*#define HAL_NOR_MODULE_ENABLED   */\n/*#define HAL_NAND_MODULE_ENABLED   */\n/*#define HAL_PCCARD_MODULE_ENABLED   */\n/*#define HAL_PCD_MODULE_ENABLED   */\n/*#define HAL_HCD_MODULE_ENABLED   */\n/*#define HAL_PWR_MODULE_ENABLED   */\n/*#define HAL_RCC_MODULE_ENABLED   */\n/*#define HAL_RTC_MODULE_ENABLED   */\n/*#define HAL_SD_MODULE_ENABLED   */\n/*#define HAL_MMC_MODULE_ENABLED   */\n/*#define HAL_SDRAM_MODULE_ENABLED   */\n/*#define HAL_SMARTCARD_MODULE_ENABLED   */\n#define HAL_SPI_MODULE_ENABLED\n/*#define HAL_SRAM_MODULE_ENABLED   */\n#define HAL_TIM_MODULE_ENABLED\n#define HAL_UART_MODULE_ENABLED\n/*#define HAL_USART_MODULE_ENABLED   */\n/*#define HAL_WWDG_MODULE_ENABLED   */\n\n#define HAL_CORTEX_MODULE_ENABLED\n#define HAL_DMA_MODULE_ENABLED\n#define HAL_FLASH_MODULE_ENABLED\n#define HAL_EXTI_MODULE_ENABLED\n#define HAL_GPIO_MODULE_ENABLED\n#define HAL_PWR_MODULE_ENABLED\n#define HAL_RCC_MODULE_ENABLED\n\n/* ########################## Oscillator Values adaptation ####################*/\n/**\n  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSE is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSE_VALUE)\n  #define HSE_VALUE    12000000U /*!< Value of the External oscillator in Hz */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSE_STARTUP_TIMEOUT)\n  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */\n#endif /* HSE_STARTUP_TIMEOUT */\n\n/**\n  * @brief Internal High Speed oscillator (HSI) value.\n  *        This value is used by the RCC HAL module to compute the system frequency\n  *        (when HSI is used as system clock source, directly or through the PLL).\n  */\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE    8000000U /*!< Value of the Internal oscillator in Hz*/\n#endif /* HSI_VALUE */\n\n/**\n  * @brief Internal Low Speed oscillator (LSI) value.\n  */\n#if !defined  (LSI_VALUE)\n #define LSI_VALUE               40000U    /*!< LSI Typical Value in Hz */\n#endif /* LSI_VALUE */                     /*!< Value of the Internal Low Speed oscillator in Hz\n                                                The real value may vary depending on the variations\n                                                in voltage and temperature. */\n\n/**\n  * @brief External Low Speed oscillator (LSE) value.\n  *        This value is used by the UART, RTC HAL module to compute the system frequency\n  */\n#if !defined  (LSE_VALUE)\n  #define LSE_VALUE    32768U /*!< Value of the External oscillator in Hz*/\n#endif /* LSE_VALUE */\n\n#if !defined  (LSE_STARTUP_TIMEOUT)\n  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */\n#endif /* LSE_STARTUP_TIMEOUT */\n\n/* Tip: To avoid modifying this file each time you need to use different HSE,\n   ===  you can define the HSE value in your toolchain compiler preprocessor. */\n\n/* ########################### System Configuration ######################### */\n/**\n  * @brief This is the HAL system configuration section\n  */\n#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */\n#define  TICK_INT_PRIORITY            3U    /*!< tick interrupt priority (lowest by default)  */\n#define  USE_RTOS                     0U\n#define  PREFETCH_ENABLE              1U\n\n#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */\n#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */\n#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */\n#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */\n#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */\n#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */\n#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */\n#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */\n#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */\n#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */\n#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */\n#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */\n#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */\n#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */\n#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */\n#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */\n#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */\n#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */\n#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */\n#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */\n#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */\n#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */\n#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */\n\n/* ########################## Assert Selection ############################## */\n/**\n  * @brief Uncomment the line below to expanse the \"assert_param\" macro in the\n  *        HAL drivers code\n  */\n/* #define USE_FULL_ASSERT    1U */\n\n/* ################## Ethernet peripheral configuration ##################### */\n\n/* Section 1 : Ethernet peripheral configuration */\n\n/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */\n#define MAC_ADDR0   2U\n#define MAC_ADDR1   0U\n#define MAC_ADDR2   0U\n#define MAC_ADDR3   0U\n#define MAC_ADDR4   0U\n#define MAC_ADDR5   0U\n\n/* Definition of the Ethernet driver buffers size and count */\n#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */\n#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */\n#define ETH_RXBUFNB                    8U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */\n#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */\n\n/* Section 2: PHY configuration section */\n\n/* DP83848_PHY_ADDRESS Address*/\n#define DP83848_PHY_ADDRESS           0x01U\n/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/\n#define PHY_RESET_DELAY                 0x000000FFU\n/* PHY Configuration delay */\n#define PHY_CONFIG_DELAY                0x00000FFFU\n\n#define PHY_READ_TO                     0x0000FFFFU\n#define PHY_WRITE_TO                    0x0000FFFFU\n\n/* Section 3: Common PHY Registers */\n\n#define PHY_BCR                         ((uint16_t)0x00)    /*!< Transceiver Basic Control Register   */\n#define PHY_BSR                         ((uint16_t)0x01)    /*!< Transceiver Basic Status Register    */\n\n#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */\n#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */\n#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */\n#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */\n#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */\n#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */\n#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */\n#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */\n#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */\n#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */\n\n#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */\n#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */\n#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */\n\n/* Section 4: Extended PHY Registers */\n#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */\n\n#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */\n#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */\n\n/* ################## SPI peripheral configuration ########################## */\n\n/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver\n* Activated: CRC code is present inside driver\n* Deactivated: CRC code cleaned from driver\n*/\n\n#define USE_SPI_CRC                     0U\n\n/* Includes ------------------------------------------------------------------*/\n/**\n  * @brief Include module's header file\n  */\n\n#ifdef HAL_RCC_MODULE_ENABLED\n#include \"stm32f1xx_hal_rcc.h\"\n#endif /* HAL_RCC_MODULE_ENABLED */\n\n#ifdef HAL_GPIO_MODULE_ENABLED\n#include \"stm32f1xx_hal_gpio.h\"\n#endif /* HAL_GPIO_MODULE_ENABLED */\n\n#ifdef HAL_EXTI_MODULE_ENABLED\n#include \"stm32f1xx_hal_exti.h\"\n#endif /* HAL_EXTI_MODULE_ENABLED */\n\n#ifdef HAL_DMA_MODULE_ENABLED\n#include \"stm32f1xx_hal_dma.h\"\n#endif /* HAL_DMA_MODULE_ENABLED */\n\n#ifdef HAL_ETH_MODULE_ENABLED\n#include \"stm32f1xx_hal_eth.h\"\n#endif /* HAL_ETH_MODULE_ENABLED */\n\n#ifdef HAL_CAN_MODULE_ENABLED\n#include \"stm32f1xx_hal_can.h\"\n#endif /* HAL_CAN_MODULE_ENABLED */\n\n#ifdef HAL_CAN_LEGACY_MODULE_ENABLED\n  #include \"Legacy/stm32f1xx_hal_can_legacy.h\"\n#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */\n\n#ifdef HAL_CEC_MODULE_ENABLED\n#include \"stm32f1xx_hal_cec.h\"\n#endif /* HAL_CEC_MODULE_ENABLED */\n\n#ifdef HAL_CORTEX_MODULE_ENABLED\n#include \"stm32f1xx_hal_cortex.h\"\n#endif /* HAL_CORTEX_MODULE_ENABLED */\n\n#ifdef HAL_ADC_MODULE_ENABLED\n#include \"stm32f1xx_hal_adc.h\"\n#endif /* HAL_ADC_MODULE_ENABLED */\n\n#ifdef HAL_CRC_MODULE_ENABLED\n#include \"stm32f1xx_hal_crc.h\"\n#endif /* HAL_CRC_MODULE_ENABLED */\n\n#ifdef HAL_DAC_MODULE_ENABLED\n#include \"stm32f1xx_hal_dac.h\"\n#endif /* HAL_DAC_MODULE_ENABLED */\n\n#ifdef HAL_FLASH_MODULE_ENABLED\n#include \"stm32f1xx_hal_flash.h\"\n#endif /* HAL_FLASH_MODULE_ENABLED */\n\n#ifdef HAL_SRAM_MODULE_ENABLED\n#include \"stm32f1xx_hal_sram.h\"\n#endif /* HAL_SRAM_MODULE_ENABLED */\n\n#ifdef HAL_NOR_MODULE_ENABLED\n#include \"stm32f1xx_hal_nor.h\"\n#endif /* HAL_NOR_MODULE_ENABLED */\n\n#ifdef HAL_I2C_MODULE_ENABLED\n#include \"stm32f1xx_hal_i2c.h\"\n#endif /* HAL_I2C_MODULE_ENABLED */\n\n#ifdef HAL_I2S_MODULE_ENABLED\n#include \"stm32f1xx_hal_i2s.h\"\n#endif /* HAL_I2S_MODULE_ENABLED */\n\n#ifdef HAL_IWDG_MODULE_ENABLED\n#include \"stm32f1xx_hal_iwdg.h\"\n#endif /* HAL_IWDG_MODULE_ENABLED */\n\n#ifdef HAL_PWR_MODULE_ENABLED\n#include \"stm32f1xx_hal_pwr.h\"\n#endif /* HAL_PWR_MODULE_ENABLED */\n\n#ifdef HAL_RTC_MODULE_ENABLED\n#include \"stm32f1xx_hal_rtc.h\"\n#endif /* HAL_RTC_MODULE_ENABLED */\n\n#ifdef HAL_PCCARD_MODULE_ENABLED\n#include \"stm32f1xx_hal_pccard.h\"\n#endif /* HAL_PCCARD_MODULE_ENABLED */\n\n#ifdef HAL_SD_MODULE_ENABLED\n#include \"stm32f1xx_hal_sd.h\"\n#endif /* HAL_SD_MODULE_ENABLED */\n\n#ifdef HAL_NAND_MODULE_ENABLED\n#include \"stm32f1xx_hal_nand.h\"\n#endif /* HAL_NAND_MODULE_ENABLED */\n\n#ifdef HAL_SPI_MODULE_ENABLED\n#include \"stm32f1xx_hal_spi.h\"\n#endif /* HAL_SPI_MODULE_ENABLED */\n\n#ifdef HAL_TIM_MODULE_ENABLED\n#include \"stm32f1xx_hal_tim.h\"\n#endif /* HAL_TIM_MODULE_ENABLED */\n\n#ifdef HAL_UART_MODULE_ENABLED\n#include \"stm32f1xx_hal_uart.h\"\n#endif /* HAL_UART_MODULE_ENABLED */\n\n#ifdef HAL_USART_MODULE_ENABLED\n#include \"stm32f1xx_hal_usart.h\"\n#endif /* HAL_USART_MODULE_ENABLED */\n\n#ifdef HAL_IRDA_MODULE_ENABLED\n#include \"stm32f1xx_hal_irda.h\"\n#endif /* HAL_IRDA_MODULE_ENABLED */\n\n#ifdef HAL_SMARTCARD_MODULE_ENABLED\n#include \"stm32f1xx_hal_smartcard.h\"\n#endif /* HAL_SMARTCARD_MODULE_ENABLED */\n\n#ifdef HAL_WWDG_MODULE_ENABLED\n#include \"stm32f1xx_hal_wwdg.h\"\n#endif /* HAL_WWDG_MODULE_ENABLED */\n\n#ifdef HAL_PCD_MODULE_ENABLED\n#include \"stm32f1xx_hal_pcd.h\"\n#endif /* HAL_PCD_MODULE_ENABLED */\n\n#ifdef HAL_HCD_MODULE_ENABLED\n#include \"stm32f1xx_hal_hcd.h\"\n#endif /* HAL_HCD_MODULE_ENABLED */\n\n#ifdef HAL_MMC_MODULE_ENABLED\n#include \"stm32f1xx_hal_mmc.h\"\n#endif /* HAL_MMC_MODULE_ENABLED */\n\n/* Exported macro ------------------------------------------------------------*/\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  The assert_param macro is used for function's parameters check.\n  * @param  expr If expr is false, it calls assert_failed function\n  *         which reports the name of the source file and the source\n  *         line number of the call that failed.\n  *         If expr is true, it returns no value.\n  * @retval None\n  */\n#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))\n/* Exported functions ------------------------------------------------------- */\nvoid assert_failed(uint8_t* file, uint32_t line);\n#else\n#define assert_param(expr) ((void)0U)\n#endif /* USE_FULL_ASSERT */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F1xx_HAL_CONF_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/stm32f1xx_it.h",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file    stm32f1xx_it.h\n  * @brief   This file contains the headers of the interrupt handlers.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __STM32F1xx_IT_H\n#define __STM32F1xx_IT_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Exported types ------------------------------------------------------------*/\n/* USER CODE BEGIN ET */\n\n/* USER CODE END ET */\n\n/* Exported constants --------------------------------------------------------*/\n/* USER CODE BEGIN EC */\n\n/* USER CODE END EC */\n\n/* Exported macro ------------------------------------------------------------*/\n/* USER CODE BEGIN EM */\n\n/* USER CODE END EM */\n\n/* Exported functions prototypes ---------------------------------------------*/\nvoid NMI_Handler(void);\nvoid HardFault_Handler(void);\nvoid MemManage_Handler(void);\nvoid BusFault_Handler(void);\nvoid UsageFault_Handler(void);\nvoid SVC_Handler(void);\nvoid DebugMon_Handler(void);\nvoid PendSV_Handler(void);\nvoid SysTick_Handler(void);\nvoid DMA1_Channel1_IRQHandler(void);\nvoid DMA1_Channel4_IRQHandler(void);\nvoid DMA1_Channel5_IRQHandler(void);\nvoid USB_HP_CAN1_TX_IRQHandler(void);\nvoid USB_LP_CAN1_RX0_IRQHandler(void);\nvoid CAN1_RX1_IRQHandler(void);\nvoid CAN1_SCE_IRQHandler(void);\nvoid EXTI9_5_IRQHandler(void);\nvoid TIM1_UP_IRQHandler(void);\nvoid TIM3_IRQHandler(void);\nvoid TIM4_IRQHandler(void);\nvoid USART1_IRQHandler(void);\n/* USER CODE BEGIN EFP */\n\n/* USER CODE END EFP */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __STM32F1xx_IT_H */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/tim.h",
    "content": "/**\n  ******************************************************************************\n  * @file    tim.h\n  * @brief   This file contains all the function prototypes for\n  *          the tim.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __TIM_H__\n#define __TIM_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern TIM_HandleTypeDef htim1;\nextern TIM_HandleTypeDef htim2;\nextern TIM_HandleTypeDef htim3;\nextern TIM_HandleTypeDef htim4;\n\n/* USER CODE BEGIN Private defines */\n\n/* USER CODE END Private defines */\n\nvoid MX_TIM1_Init(void);\nvoid MX_TIM2_Init(void);\nvoid MX_TIM3_Init(void);\nvoid MX_TIM4_Init(void);\n\nvoid HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);\n\n/* USER CODE BEGIN Prototypes */\n/********** HwElec **********/\n/********** HwElec **********/\n/********** HwElec **********/\nvoid REIN_TIM_HwElec_Init(void);       //TIM初始??(HwElec)\n\n/********** MT6816Base **********/\n/********** MT6816Base **********/\n/********** MT6816Base **********/\nvoid REIN_TIM_MT6816_ABZ_Init(void);\t\t//TIM初始??(MT6816_ABZ)\nvoid REIN_TIM_MT6816_PWM_Init(void);\t\t//TIM初始??(MT6816_PWM)\n\n/********** SIGNAL **********/\n/********** SIGNAL **********/\n/********** SIGNAL **********/\nvoid REIN_TIM_SIGNAL_COUNT_Init(void);\t\t//TIM初始??(SIGNAL_COUNT)\nvoid REIN_TIM_SIGNAL_COUNT_DeInit(void);\t//TIM清理(SIGNAL_COUNT)\nvoid REIN_TIM_SIGNAL_PWM_Init(void);\t\t\t//TIM初始??(SIGNAL_PWM)\nvoid REIN_TIM_SIGNAL_PWM_DeInit(void);\t\t//TIM清理(SIGNAL_PWM)\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __TIM_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Inc/usart.h",
    "content": "/**\n  ******************************************************************************\n  * @file    usart.h\n  * @brief   This file contains all the function prototypes for\n  *          the usart.c file\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* Define to prevent recursive inclusion -------------------------------------*/\n#ifndef __USART_H__\n#define __USART_H__\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\nextern UART_HandleTypeDef huart1;\n\n/* USER CODE BEGIN Private defines */\n#define BUFFER_SIZE  128\n\nextern DMA_HandleTypeDef hdma_usart1_rx;\nextern DMA_HandleTypeDef hdma_usart1_tx;\nextern volatile uint8_t rxLen;\nextern volatile uint8_t recv_end_flag;\nextern uint8_t rx_buffer[BUFFER_SIZE];\n\n\n/* USER CODE END Private defines */\n\nvoid MX_USART1_UART_Init(void);\n\n/* USER CODE BEGIN Prototypes */\nextern void (*OnRecvEnd)(uint8_t *data, uint16_t len);\nvoid Uart_SetRxCpltCallBack(void(*xerc)(uint8_t *, uint16_t));\n\n/* USER CODE END Prototypes */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __USART_H__ */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/adc.c",
    "content": "/**\n  ******************************************************************************\n  * @file    adc.c\n  * @brief   This file provides code for the configuration\n  *          of the ADC instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"adc.h\"\n\n/* USER CODE BEGIN 0 */\nuint16_t whole_adc_data[2][12];\n\n/* USER CODE END 0 */\n\nADC_HandleTypeDef hadc1;\nDMA_HandleTypeDef hdma_adc1;\n\n/* ADC1 init function */\nvoid MX_ADC1_Init(void)\n{\n\n  /* USER CODE BEGIN ADC1_Init 0 */\n\n  /* USER CODE END ADC1_Init 0 */\n\n  ADC_ChannelConfTypeDef sConfig = {0};\n\n  /* USER CODE BEGIN ADC1_Init 1 */\n\n  /* USER CODE END ADC1_Init 1 */\n  /** Common config\n  */\n  hadc1.Instance = ADC1;\n  hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE;\n  hadc1.Init.ContinuousConvMode = ENABLE;\n  hadc1.Init.DiscontinuousConvMode = DISABLE;\n  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;\n  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;\n  hadc1.Init.NbrOfConversion = 2;\n  if (HAL_ADC_Init(&hadc1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure Regular Channel\n  */\n  sConfig.Channel = ADC_CHANNEL_0;\n  sConfig.Rank = ADC_REGULAR_RANK_1;\n  sConfig.SamplingTime = ADC_SAMPLETIME_239CYCLES_5;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Configure Regular Channel\n  */\n  sConfig.Channel = ADC_CHANNEL_1;\n  sConfig.Rank = ADC_REGULAR_RANK_2;\n  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN ADC1_Init 2 */\n  HAL_ADCEx_Calibration_Start(&hadc1);\n  HAL_ADC_Start_DMA(&hadc1, (uint32_t*)&whole_adc_data[0][0], 2);\n\n  /* USER CODE END ADC1_Init 2 */\n\n}\n\nvoid HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(adcHandle->Instance==ADC1)\n  {\n  /* USER CODE BEGIN ADC1_MspInit 0 */\n\n  /* USER CODE END ADC1_MspInit 0 */\n    /* ADC1 clock enable */\n    __HAL_RCC_ADC1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**ADC1 GPIO Configuration\n    PA0-WKUP     ------> ADC1_IN0\n    PA1     ------> ADC1_IN1\n    */\n    GPIO_InitStruct.Pin = POWER_U_Pin|DRV_TEMP_Pin;\n    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* ADC1 DMA Init */\n    /* ADC1 Init */\n    hdma_adc1.Instance = DMA1_Channel1;\n    hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY;\n    hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_adc1.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;\n    hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;\n    hdma_adc1.Init.Mode = DMA_CIRCULAR;\n    hdma_adc1.Init.Priority = DMA_PRIORITY_VERY_HIGH;\n    if (HAL_DMA_Init(&hdma_adc1) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1);\n\n  /* USER CODE BEGIN ADC1_MspInit 1 */\n\n  /* USER CODE END ADC1_MspInit 1 */\n  }\n}\n\nvoid HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle)\n{\n\n  if(adcHandle->Instance==ADC1)\n  {\n  /* USER CODE BEGIN ADC1_MspDeInit 0 */\n\n  /* USER CODE END ADC1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_ADC1_CLK_DISABLE();\n\n    /**ADC1 GPIO Configuration\n    PA0-WKUP     ------> ADC1_IN0\n    PA1     ------> ADC1_IN1\n    */\n    HAL_GPIO_DeInit(GPIOA, POWER_U_Pin|DRV_TEMP_Pin);\n\n    /* ADC1 DMA DeInit */\n    HAL_DMA_DeInit(adcHandle->DMA_Handle);\n  /* USER CODE BEGIN ADC1_MspDeInit 1 */\n\n  /* USER CODE END ADC1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/can.c",
    "content": "/**\n  ******************************************************************************\n  * @file    can.c\n  * @brief   This file provides code for the configuration\n  *          of the CAN instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"can.h\"\n\n/* USER CODE BEGIN 0 */\n#include \"common_inc.h\"\n#include \"configurations.h\"\n\nCAN_TxHeaderTypeDef TxHeader;\nCAN_RxHeaderTypeDef RxHeader;\nuint8_t TxData[8];\nuint8_t RxData[8];\nuint32_t TxMailbox;\n\n/* USER CODE END 0 */\n\nCAN_HandleTypeDef hcan;\n\n/* CAN init function */\nvoid MX_CAN_Init(void)\n{\n\n  /* USER CODE BEGIN CAN_Init 0 */\n\n  /* USER CODE END CAN_Init 0 */\n\n  /* USER CODE BEGIN CAN_Init 1 */\n\n  /* USER CODE END CAN_Init 1 */\n  hcan.Instance = CAN1;\n  hcan.Init.Prescaler = 4;\n  hcan.Init.Mode = CAN_MODE_NORMAL;\n  hcan.Init.SyncJumpWidth = CAN_SJW_1TQ;\n  hcan.Init.TimeSeg1 = CAN_BS1_5TQ;\n  hcan.Init.TimeSeg2 = CAN_BS2_3TQ;\n  hcan.Init.TimeTriggeredMode = DISABLE;\n  hcan.Init.AutoBusOff = DISABLE;\n  hcan.Init.AutoWakeUp = ENABLE;\n  hcan.Init.AutoRetransmission = DISABLE;\n  hcan.Init.ReceiveFifoLocked = DISABLE;\n  hcan.Init.TransmitFifoPriority = DISABLE;\n  if (HAL_CAN_Init(&hcan) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN CAN_Init 2 */\n    CAN_FilterTypeDef sFilterConfig;\n    //filter one (stack light blink)\n    sFilterConfig.FilterBank = 0;\n    sFilterConfig.FilterMode = CAN_FILTERMODE_IDMASK;\n    sFilterConfig.FilterScale = CAN_FILTERSCALE_32BIT;\n    sFilterConfig.FilterIdHigh = 0x0000;\n    sFilterConfig.FilterIdLow = 0x0000;\n    sFilterConfig.FilterMaskIdHigh = 0x0000;\n    sFilterConfig.FilterMaskIdLow = 0x0000;\n    sFilterConfig.FilterFIFOAssignment = CAN_RX_FIFO0;\n    sFilterConfig.FilterActivation = ENABLE;\n    sFilterConfig.SlaveStartFilterBank = 14;\n    if (HAL_CAN_ConfigFilter(&hcan, &sFilterConfig) != HAL_OK)\n    {\n        /* Filter configuration Error */\n        Error_Handler();\n    }\n\n    HAL_CAN_Start(&hcan); //start CAN\n\n    HAL_CAN_ActivateNotification(&hcan,\n                                 CAN_IT_TX_MAILBOX_EMPTY |\n                                 CAN_IT_RX_FIFO0_MSG_PENDING | CAN_IT_RX_FIFO1_MSG_PENDING |\n                                 /* we probably only want this */\n                                 CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO1_FULL |\n                                 CAN_IT_RX_FIFO0_OVERRUN | CAN_IT_RX_FIFO1_OVERRUN |\n                                 CAN_IT_WAKEUP | CAN_IT_SLEEP_ACK |\n                                 CAN_IT_ERROR_WARNING | CAN_IT_ERROR_PASSIVE |\n                                 CAN_IT_BUSOFF | CAN_IT_LAST_ERROR_CODE |\n                                 CAN_IT_ERROR);\n\n/* Configure Transmission process */\n    TxHeader.StdId = boardConfig.canNodeId;\n    TxHeader.ExtId = 0x00;\n    TxHeader.RTR = CAN_RTR_DATA;\n    TxHeader.IDE = CAN_ID_STD;\n    TxHeader.DLC = 8;\n    TxHeader.TransmitGlobalTime = DISABLE;\n\n  /* USER CODE END CAN_Init 2 */\n\n}\n\nvoid HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(canHandle->Instance==CAN1)\n  {\n  /* USER CODE BEGIN CAN1_MspInit 0 */\n\n  /* USER CODE END CAN1_MspInit 0 */\n    /* CAN1 clock enable */\n    __HAL_RCC_CAN1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**CAN GPIO Configuration\n    PB8     ------> CAN_RX\n    PB9     ------> CAN_TX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_8;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_9;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    __HAL_AFIO_REMAP_CAN1_2();\n\n    /* CAN1 interrupt Init */\n    HAL_NVIC_SetPriority(USB_HP_CAN1_TX_IRQn, 3, 0);\n    HAL_NVIC_EnableIRQ(USB_HP_CAN1_TX_IRQn);\n    HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 3, 0);\n    HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);\n    HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 3, 0);\n    HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn);\n    HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 3, 0);\n    HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn);\n  /* USER CODE BEGIN CAN1_MspInit 1 */\n\n  /* USER CODE END CAN1_MspInit 1 */\n  }\n}\n\nvoid HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle)\n{\n\n  if(canHandle->Instance==CAN1)\n  {\n  /* USER CODE BEGIN CAN1_MspDeInit 0 */\n\n  /* USER CODE END CAN1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_CAN1_CLK_DISABLE();\n\n    /**CAN GPIO Configuration\n    PB8     ------> CAN_RX\n    PB9     ------> CAN_TX\n    */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8|GPIO_PIN_9);\n\n    /* CAN1 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(USB_HP_CAN1_TX_IRQn);\n    HAL_NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn);\n    HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn);\n    HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn);\n  /* USER CODE BEGIN CAN1_MspDeInit 1 */\n\n  /* USER CODE END CAN1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\nvoid CAN_Send(CAN_TxHeaderTypeDef* pHeader, uint8_t* data)\n{\n    if (HAL_CAN_AddTxMessage(&hcan, pHeader, data, &TxMailbox) != HAL_OK)\n    {\n        Error_Handler();\n    }\n}\n\nvoid HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef* CanHandle)\n{\n    /* Get RX message */\n    if (HAL_CAN_GetRxMessage(CanHandle, CAN_RX_FIFO0, &RxHeader, RxData) != HAL_OK)\n    {\n        /* Reception Error */\n        Error_Handler();\n    }\n\n    uint8_t id = (RxHeader.StdId >> 7); // 4Bits ID & 7Bits Msg\n    uint8_t cmd = RxHeader.StdId & 0x7F; // 4Bits ID & 7Bits Msg\n    if (id == 0 || id == boardConfig.canNodeId)\n    {\n        OnCanCmd(cmd, RxData, RxHeader.DLC);\n    }\n}\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/dma.c",
    "content": "/**\n  ******************************************************************************\n  * @file    dma.c\n  * @brief   This file provides code for the configuration\n  *          of all the requested memory to memory DMA transfers.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"dma.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/*----------------------------------------------------------------------------*/\n/* Configure DMA                                                              */\n/*----------------------------------------------------------------------------*/\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/**\n  * Enable DMA controller clock\n  */\nvoid MX_DMA_Init(void)\n{\n\n  /* DMA controller clock enable */\n  __HAL_RCC_DMA1_CLK_ENABLE();\n\n  /* DMA interrupt init */\n  /* DMA1_Channel1_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);\n  /* DMA1_Channel4_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 3, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);\n  /* DMA1_Channel5_IRQn interrupt configuration */\n  HAL_NVIC_SetPriority(DMA1_Channel5_IRQn, 3, 0);\n  HAL_NVIC_EnableIRQ(DMA1_Channel5_IRQn);\n\n}\n\n/* USER CODE BEGIN 2 */\n\n/* USER CODE END 2 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/gpio.c",
    "content": "/**\n  ******************************************************************************\n  * @file    gpio.c\n  * @brief   This file provides code for the configuration\n  *          of all used GPIO pins.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"gpio.h\"\n\n/* USER CODE BEGIN 0 */\n#include \"common_inc.h\"\n/* USER CODE END 0 */\n\n/*----------------------------------------------------------------------------*/\n/* Configure GPIO                                                             */\n/*----------------------------------------------------------------------------*/\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/** Configure pins as\n        * Analog\n        * Input\n        * Output\n        * EVENT_OUT\n        * EXTI\n*/\nvoid MX_GPIO_Init(void)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n\n  /* GPIO Ports Clock Enable */\n  __HAL_RCC_GPIOC_CLK_ENABLE();\n  __HAL_RCC_GPIOD_CLK_ENABLE();\n  __HAL_RCC_GPIOA_CLK_ENABLE();\n  __HAL_RCC_GPIOB_CLK_ENABLE();\n\n  /*Configure GPIO pin Output Level */\n  HAL_GPIO_WritePin(GPIOC, LED1_Pin|LED2_Pin, GPIO_PIN_RESET);\n\n  /*Configure GPIO pin Output Level */\n  HAL_GPIO_WritePin(GPIOA, HW_ELEC_BM_Pin|HW_ELEC_BP_Pin|HW_ELEC_AM_Pin|HW_ELEC_AP_Pin, GPIO_PIN_RESET);\n\n  /*Configure GPIO pin Output Level */\n  HAL_GPIO_WritePin(SIGNAL_ALERT_GPIO_Port, SIGNAL_ALERT_Pin, GPIO_PIN_RESET);\n\n  /*Configure GPIO pin Output Level */\n  HAL_GPIO_WritePin(SPI1_CS_GPIO_Port, SPI1_CS_Pin, GPIO_PIN_SET);\n\n  /*Configure GPIO pins : PCPin PCPin */\n  GPIO_InitStruct.Pin = LED1_Pin|LED2_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);\n\n  /*Configure GPIO pins : PAPin PAPin PAPin PAPin */\n  GPIO_InitStruct.Pin = HW_ELEC_BM_Pin|HW_ELEC_BP_Pin|HW_ELEC_AM_Pin|HW_ELEC_AP_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = SIGNAL_COUNT_DIR_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  HAL_GPIO_Init(SIGNAL_COUNT_DIR_GPIO_Port, &GPIO_InitStruct);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = SIGNAL_COUNT_EN_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  HAL_GPIO_Init(SIGNAL_COUNT_EN_GPIO_Port, &GPIO_InitStruct);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = SIGNAL_ALERT_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n  HAL_GPIO_Init(SIGNAL_ALERT_GPIO_Port, &GPIO_InitStruct);\n\n  /*Configure GPIO pins : PBPin PBPin */\n  GPIO_InitStruct.Pin = BUTTON2_Pin|BUTTON1_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n  GPIO_InitStruct.Pull = GPIO_PULLUP;\n  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n  /*Configure GPIO pin : PtPin */\n  GPIO_InitStruct.Pin = SPI1_CS_Pin;\n  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;\n  GPIO_InitStruct.Pull = GPIO_NOPULL;\n  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;\n  HAL_GPIO_Init(SPI1_CS_GPIO_Port, &GPIO_InitStruct);\n\n  /* EXTI interrupt init*/\n  HAL_NVIC_SetPriority(EXTI9_5_IRQn, 0, 0);\n  HAL_NVIC_EnableIRQ(EXTI9_5_IRQn);\n\n}\n\n/* USER CODE BEGIN 2 */\n\n/* USER CODE END 2 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/main.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file           : main.c\n  * @brief          : Main program body\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n#include \"adc.h\"\n#include \"can.h\"\n#include \"dma.h\"\n#include \"spi.h\"\n#include \"tim.h\"\n#include \"usart.h\"\n#include \"gpio.h\"\n\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n#include \"common_inc.h\"\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* USER CODE BEGIN PTD */\n\n/* USER CODE END PTD */\n\n/* Private define ------------------------------------------------------------*/\n/* USER CODE BEGIN PD */\n/* USER CODE END PD */\n\n/* Private macro -------------------------------------------------------------*/\n/* USER CODE BEGIN PM */\n\n/* USER CODE END PM */\n\n/* Private variables ---------------------------------------------------------*/\n\n/* USER CODE BEGIN PV */\n\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\nvoid SystemClock_Config(void);\n/* USER CODE BEGIN PFP */\n\n/* USER CODE END PFP */\n\n/* Private user code ---------------------------------------------------------*/\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/**\n  * @brief  The application entry point.\n  * @retval int\n  */\nint main(void)\n{\n  /* USER CODE BEGIN 1 */\n\n  /* USER CODE END 1 */\n\n  /* MCU Configuration--------------------------------------------------------*/\n\n  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */\n  HAL_Init();\n\n  /* USER CODE BEGIN Init */\n\n  /* USER CODE END Init */\n\n  /* Configure the system clock */\n  SystemClock_Config();\n\n  /* USER CODE BEGIN SysInit */\n\n  /* USER CODE END SysInit */\n\n  /* Initialize all configured peripherals */\n  MX_GPIO_Init();\n  MX_DMA_Init();\n  MX_ADC1_Init();\n  MX_USART1_UART_Init();\n  MX_CAN_Init();\n  MX_SPI1_Init();\n  MX_TIM2_Init();\n  MX_TIM3_Init();\n  MX_TIM4_Init();\n  MX_TIM1_Init();\n  /* USER CODE BEGIN 2 */\n    Main();\n  /* USER CODE END 2 */\n\n  /* Infinite loop */\n  /* USER CODE BEGIN WHILE */\n    while (1)\n    {\n    /* USER CODE END WHILE */\n\n    /* USER CODE BEGIN 3 */\n    }\n  /* USER CODE END 3 */\n}\n\n/**\n  * @brief System Clock Configuration\n  * @retval None\n  */\nvoid SystemClock_Config(void)\n{\n  RCC_OscInitTypeDef RCC_OscInitStruct = {0};\n  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};\n  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};\n\n  /** Initializes the RCC Oscillators according to the specified parameters\n  * in the RCC_OscInitTypeDef structure.\n  */\n  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;\n  RCC_OscInitStruct.HSEState = RCC_HSE_ON;\n  RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;\n  RCC_OscInitStruct.HSIState = RCC_HSI_ON;\n  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;\n  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;\n  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;\n  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /** Initializes the CPU, AHB and APB buses clocks\n  */\n  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK\n                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;\n  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;\n  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;\n  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;\n  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;\n\n  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;\n  PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;\n  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)\n  {\n    Error_Handler();\n  }\n}\n\n/* USER CODE BEGIN 4 */\n\n/* USER CODE END 4 */\n\n/**\n  * @brief  This function is executed in case of error occurrence.\n  * @retval None\n  */\nvoid Error_Handler(void)\n{\n  /* USER CODE BEGIN Error_Handler_Debug */\n    /* User can add his own implementation to report the HAL error return state */\n    __disable_irq();\n    while (1)\n    {\n    }\n  /* USER CODE END Error_Handler_Debug */\n}\n\n#ifdef  USE_FULL_ASSERT\n/**\n  * @brief  Reports the name of the source file and the source line number\n  *         where the assert_param error has occurred.\n  * @param  file: pointer to the source file name\n  * @param  line: assert_param error line source number\n  * @retval None\n  */\nvoid assert_failed(uint8_t *file, uint32_t line)\n{\n  /* USER CODE BEGIN 6 */\n  /* User can add his own implementation to report the file name and line number,\n     ex: printf(\"Wrong parameters value: file %s on line %d\\r\\n\", file, line) */\n  /* USER CODE END 6 */\n}\n#endif /* USE_FULL_ASSERT */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/spi.c",
    "content": "/**\n  ******************************************************************************\n  * @file    spi.c\n  * @brief   This file provides code for the configuration\n  *          of the SPI instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"spi.h\"\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\nSPI_HandleTypeDef hspi1;\n\n/* SPI1 init function */\nvoid MX_SPI1_Init(void)\n{\n\n  /* USER CODE BEGIN SPI1_Init 0 */\n\n  /* USER CODE END SPI1_Init 0 */\n\n  /* USER CODE BEGIN SPI1_Init 1 */\n\n  /* USER CODE END SPI1_Init 1 */\n  hspi1.Instance = SPI1;\n  hspi1.Init.Mode = SPI_MODE_MASTER;\n  hspi1.Init.Direction = SPI_DIRECTION_2LINES;\n  hspi1.Init.DataSize = SPI_DATASIZE_16BIT;\n  hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;\n  hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;\n  hspi1.Init.NSS = SPI_NSS_SOFT;\n  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_8;\n  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;\n  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;\n  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;\n  hspi1.Init.CRCPolynomial = 10;\n  if (HAL_SPI_Init(&hspi1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN SPI1_Init 2 */\n\n  /* USER CODE END SPI1_Init 2 */\n\n}\n\nvoid HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(spiHandle->Instance==SPI1)\n  {\n  /* USER CODE BEGIN SPI1_MspInit 0 */\n\n  /* USER CODE END SPI1_MspInit 0 */\n    /* SPI1 clock enable */\n    __HAL_RCC_SPI1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**SPI1 GPIO Configuration\n    PB3     ------> SPI1_SCK\n    PB4     ------> SPI1_MISO\n    PB5     ------> SPI1_MOSI\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_5;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_4;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    __HAL_AFIO_REMAP_SPI1_ENABLE();\n\n  /* USER CODE BEGIN SPI1_MspInit 1 */\n\n  /* USER CODE END SPI1_MspInit 1 */\n  }\n}\n\nvoid HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)\n{\n\n  if(spiHandle->Instance==SPI1)\n  {\n  /* USER CODE BEGIN SPI1_MspDeInit 0 */\n\n  /* USER CODE END SPI1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_SPI1_CLK_DISABLE();\n\n    /**SPI1 GPIO Configuration\n    PB3     ------> SPI1_SCK\n    PB4     ------> SPI1_MISO\n    PB5     ------> SPI1_MOSI\n    */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5);\n\n  /* USER CODE BEGIN SPI1_MspDeInit 1 */\n\n  /* USER CODE END SPI1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/stm32f1xx_hal_msp.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file         stm32f1xx_hal_msp.c\n  * @brief        This file provides code for the MSP Initialization\n  *               and de-Initialization codes.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n/* USER CODE BEGIN Includes */\n\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* USER CODE BEGIN TD */\n\n/* USER CODE END TD */\n\n/* Private define ------------------------------------------------------------*/\n/* USER CODE BEGIN Define */\n\n/* USER CODE END Define */\n\n/* Private macro -------------------------------------------------------------*/\n/* USER CODE BEGIN Macro */\n\n/* USER CODE END Macro */\n\n/* Private variables ---------------------------------------------------------*/\n/* USER CODE BEGIN PV */\n\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\n/* USER CODE BEGIN PFP */\n\n/* USER CODE END PFP */\n\n/* External functions --------------------------------------------------------*/\n/* USER CODE BEGIN ExternalFunctions */\n\n/* USER CODE END ExternalFunctions */\n\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n/**\n  * Initializes the Global MSP.\n  */\nvoid HAL_MspInit(void)\n{\n  /* USER CODE BEGIN MspInit 0 */\n\n  /* USER CODE END MspInit 0 */\n\n  __HAL_RCC_AFIO_CLK_ENABLE();\n  __HAL_RCC_PWR_CLK_ENABLE();\n\n  /* System interrupt init*/\n\n  /** NOJTAG: JTAG-DP Disabled and SW-DP Enabled\n  */\n  __HAL_AFIO_REMAP_SWJ_NOJTAG();\n\n  /* USER CODE BEGIN MspInit 1 */\n\n  /* USER CODE END MspInit 1 */\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/stm32f1xx_it.c",
    "content": "/* USER CODE BEGIN Header */\n/**\n  ******************************************************************************\n  * @file    stm32f1xx_it.c\n  * @brief   Interrupt Service Routines.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n/* USER CODE END Header */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"main.h\"\n#include \"stm32f1xx_it.h\"\n/* Private includes ----------------------------------------------------------*/\n/* USER CODE BEGIN Includes */\n#include <memory.h>\n#include \"common_inc.h\"\n#include \"usart.h\"\n/* USER CODE END Includes */\n\n/* Private typedef -----------------------------------------------------------*/\n/* USER CODE BEGIN TD */\n\n\n/* USER CODE END TD */\n\n/* Private define ------------------------------------------------------------*/\n/* USER CODE BEGIN PD */\n\n/* USER CODE END PD */\n\n/* Private macro -------------------------------------------------------------*/\n/* USER CODE BEGIN PM */\n\n/* USER CODE END PM */\n\n/* Private variables ---------------------------------------------------------*/\n/* USER CODE BEGIN PV */\n\n/* USER CODE END PV */\n\n/* Private function prototypes -----------------------------------------------*/\n/* USER CODE BEGIN PFP */\nextern void GpioPin7InterruptCallback();\nextern void Tim1Callback100Hz();\nextern void Tim3CaptureCallback();\nextern void Tim4Callback20kHz();\n\n/* USER CODE END PFP */\n\n/* Private user code ---------------------------------------------------------*/\n/* USER CODE BEGIN 0 */\n\n/* USER CODE END 0 */\n\n/* External variables --------------------------------------------------------*/\nextern DMA_HandleTypeDef hdma_adc1;\nextern CAN_HandleTypeDef hcan;\nextern TIM_HandleTypeDef htim1;\nextern TIM_HandleTypeDef htim3;\nextern TIM_HandleTypeDef htim4;\nextern DMA_HandleTypeDef hdma_usart1_rx;\nextern DMA_HandleTypeDef hdma_usart1_tx;\nextern UART_HandleTypeDef huart1;\n/* USER CODE BEGIN EV */\n\n/* USER CODE END EV */\n\n/******************************************************************************/\n/*           Cortex-M3 Processor Interruption and Exception Handlers          */\n/******************************************************************************/\n/**\n  * @brief This function handles Non maskable interrupt.\n  */\nvoid NMI_Handler(void)\n{\n  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */\n\n  /* USER CODE END NonMaskableInt_IRQn 0 */\n  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */\n    while (1)\n    {\n    }\n  /* USER CODE END NonMaskableInt_IRQn 1 */\n}\n\n/**\n  * @brief This function handles Hard fault interrupt.\n  */\nvoid HardFault_Handler(void)\n{\n  /* USER CODE BEGIN HardFault_IRQn 0 */\n\n  /* USER CODE END HardFault_IRQn 0 */\n  while (1)\n  {\n    /* USER CODE BEGIN W1_HardFault_IRQn 0 */\n    /* USER CODE END W1_HardFault_IRQn 0 */\n  }\n}\n\n/**\n  * @brief This function handles Memory management fault.\n  */\nvoid MemManage_Handler(void)\n{\n  /* USER CODE BEGIN MemoryManagement_IRQn 0 */\n\n  /* USER CODE END MemoryManagement_IRQn 0 */\n  while (1)\n  {\n    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */\n    /* USER CODE END W1_MemoryManagement_IRQn 0 */\n  }\n}\n\n/**\n  * @brief This function handles Prefetch fault, memory access fault.\n  */\nvoid BusFault_Handler(void)\n{\n  /* USER CODE BEGIN BusFault_IRQn 0 */\n\n  /* USER CODE END BusFault_IRQn 0 */\n  while (1)\n  {\n    /* USER CODE BEGIN W1_BusFault_IRQn 0 */\n    /* USER CODE END W1_BusFault_IRQn 0 */\n  }\n}\n\n/**\n  * @brief This function handles Undefined instruction or illegal state.\n  */\nvoid UsageFault_Handler(void)\n{\n  /* USER CODE BEGIN UsageFault_IRQn 0 */\n\n  /* USER CODE END UsageFault_IRQn 0 */\n  while (1)\n  {\n    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */\n    /* USER CODE END W1_UsageFault_IRQn 0 */\n  }\n}\n\n/**\n  * @brief This function handles System service call via SWI instruction.\n  */\nvoid SVC_Handler(void)\n{\n  /* USER CODE BEGIN SVCall_IRQn 0 */\n\n  /* USER CODE END SVCall_IRQn 0 */\n  /* USER CODE BEGIN SVCall_IRQn 1 */\n\n  /* USER CODE END SVCall_IRQn 1 */\n}\n\n/**\n  * @brief This function handles Debug monitor.\n  */\nvoid DebugMon_Handler(void)\n{\n  /* USER CODE BEGIN DebugMonitor_IRQn 0 */\n\n  /* USER CODE END DebugMonitor_IRQn 0 */\n  /* USER CODE BEGIN DebugMonitor_IRQn 1 */\n\n  /* USER CODE END DebugMonitor_IRQn 1 */\n}\n\n/**\n  * @brief This function handles Pendable request for system service.\n  */\nvoid PendSV_Handler(void)\n{\n  /* USER CODE BEGIN PendSV_IRQn 0 */\n\n  /* USER CODE END PendSV_IRQn 0 */\n  /* USER CODE BEGIN PendSV_IRQn 1 */\n\n  /* USER CODE END PendSV_IRQn 1 */\n}\n\n/**\n  * @brief This function handles System tick timer.\n  */\nvoid SysTick_Handler(void)\n{\n  /* USER CODE BEGIN SysTick_IRQn 0 */\n\n  /* USER CODE END SysTick_IRQn 0 */\n  HAL_IncTick();\n  /* USER CODE BEGIN SysTick_IRQn 1 */\n  /* USER CODE END SysTick_IRQn 1 */\n}\n\n/******************************************************************************/\n/* STM32F1xx Peripheral Interrupt Handlers                                    */\n/* Add here the Interrupt Handlers for the used peripherals.                  */\n/* For the available peripheral interrupt handler names,                      */\n/* please refer to the startup file (startup_stm32f1xx.s).                    */\n/******************************************************************************/\n\n/**\n  * @brief This function handles DMA1 channel1 global interrupt.\n  */\nvoid DMA1_Channel1_IRQHandler(void)\n{\n  /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */\n\n  /* USER CODE END DMA1_Channel1_IRQn 0 */\n  HAL_DMA_IRQHandler(&hdma_adc1);\n  /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */\n\n  /* USER CODE END DMA1_Channel1_IRQn 1 */\n}\n\n/**\n  * @brief This function handles DMA1 channel4 global interrupt.\n  */\nvoid DMA1_Channel4_IRQHandler(void)\n{\n  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */\n\n  /* USER CODE END DMA1_Channel4_IRQn 0 */\n  HAL_DMA_IRQHandler(&hdma_usart1_tx);\n  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */\n\n  /* USER CODE END DMA1_Channel4_IRQn 1 */\n}\n\n/**\n  * @brief This function handles DMA1 channel5 global interrupt.\n  */\nvoid DMA1_Channel5_IRQHandler(void)\n{\n  /* USER CODE BEGIN DMA1_Channel5_IRQn 0 */\n\n  /* USER CODE END DMA1_Channel5_IRQn 0 */\n  HAL_DMA_IRQHandler(&hdma_usart1_rx);\n  /* USER CODE BEGIN DMA1_Channel5_IRQn 1 */\n\n  /* USER CODE END DMA1_Channel5_IRQn 1 */\n}\n\n/**\n  * @brief This function handles USB high priority or CAN TX interrupts.\n  */\nvoid USB_HP_CAN1_TX_IRQHandler(void)\n{\n  /* USER CODE BEGIN USB_HP_CAN1_TX_IRQn 0 */\n\n  /* USER CODE END USB_HP_CAN1_TX_IRQn 0 */\n  HAL_CAN_IRQHandler(&hcan);\n  /* USER CODE BEGIN USB_HP_CAN1_TX_IRQn 1 */\n\n  /* USER CODE END USB_HP_CAN1_TX_IRQn 1 */\n}\n\n/**\n  * @brief This function handles USB low priority or CAN RX0 interrupts.\n  */\nvoid USB_LP_CAN1_RX0_IRQHandler(void)\n{\n  /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 0 */\n\n  /* USER CODE END USB_LP_CAN1_RX0_IRQn 0 */\n  HAL_CAN_IRQHandler(&hcan);\n  /* USER CODE BEGIN USB_LP_CAN1_RX0_IRQn 1 */\n\n  /* USER CODE END USB_LP_CAN1_RX0_IRQn 1 */\n}\n\n/**\n  * @brief This function handles CAN RX1 interrupt.\n  */\nvoid CAN1_RX1_IRQHandler(void)\n{\n  /* USER CODE BEGIN CAN1_RX1_IRQn 0 */\n  /* USER CODE END CAN1_RX1_IRQn 0 */\n  HAL_CAN_IRQHandler(&hcan);\n  /* USER CODE BEGIN CAN1_RX1_IRQn 1 */\n\n  /* USER CODE END CAN1_RX1_IRQn 1 */\n}\n\n/**\n  * @brief This function handles CAN SCE interrupt.\n  */\nvoid CAN1_SCE_IRQHandler(void)\n{\n  /* USER CODE BEGIN CAN1_SCE_IRQn 0 */\n\n  /* USER CODE END CAN1_SCE_IRQn 0 */\n  HAL_CAN_IRQHandler(&hcan);\n  /* USER CODE BEGIN CAN1_SCE_IRQn 1 */\n\n  /* USER CODE END CAN1_SCE_IRQn 1 */\n}\n\n/**\n  * @brief This function handles EXTI line[9:5] interrupts.\n  */\nvoid EXTI9_5_IRQHandler(void)\n{\n  /* USER CODE BEGIN EXTI9_5_IRQn 0 */\n    return;\n  /* USER CODE END EXTI9_5_IRQn 0 */\n  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7);\n  /* USER CODE BEGIN EXTI9_5_IRQn 1 */\n\n  /* USER CODE END EXTI9_5_IRQn 1 */\n}\n\n/**\n  * @brief This function handles TIM1 update interrupt.\n  */\nvoid TIM1_UP_IRQHandler(void)\n{\n  /* USER CODE BEGIN TIM1_UP_IRQn 0 */\n    Tim1Callback100Hz();\n    return;\n  /* USER CODE END TIM1_UP_IRQn 0 */\n  HAL_TIM_IRQHandler(&htim1);\n  /* USER CODE BEGIN TIM1_UP_IRQn 1 */\n\n  /* USER CODE END TIM1_UP_IRQn 1 */\n}\n\n/**\n  * @brief This function handles TIM3 global interrupt.\n  */\nvoid TIM3_IRQHandler(void)\n{\n  /* USER CODE BEGIN TIM3_IRQn 0 */\n    return;\n  /* USER CODE END TIM3_IRQn 0 */\n  HAL_TIM_IRQHandler(&htim3);\n  /* USER CODE BEGIN TIM3_IRQn 1 */\n\n  /* USER CODE END TIM3_IRQn 1 */\n}\n\n/**\n  * @brief This function handles TIM4 global interrupt.\n  */\nvoid TIM4_IRQHandler(void)\n{\n  /* USER CODE BEGIN TIM4_IRQn 0 */\n    Tim4Callback20kHz();\n    return;\n  /* USER CODE END TIM4_IRQn 0 */\n  HAL_TIM_IRQHandler(&htim4);\n  /* USER CODE BEGIN TIM4_IRQn 1 */\n\n  /* USER CODE END TIM4_IRQn 1 */\n}\n\n/**\n  * @brief This function handles USART1 global interrupt.\n  */\nvoid USART1_IRQHandler(void)\n{\n  /* USER CODE BEGIN USART1_IRQn 0 */\n    if ((__HAL_UART_GET_FLAG(&huart1, UART_FLAG_IDLE) != RESET))\n    {\n        __HAL_UART_CLEAR_IDLEFLAG(&huart1);\n        HAL_UART_DMAStop(&huart1);\n        uint32_t temp = __HAL_DMA_GET_COUNTER(&hdma_usart1_rx);\n        rxLen = BUFFER_SIZE - temp;\n\n        OnRecvEnd(rx_buffer, rxLen);\n\n        memset(rx_buffer, 0, rxLen);\n        rxLen = 0;\n\n        HAL_UART_Receive_DMA(&huart1, rx_buffer, BUFFER_SIZE);\n    }\n\n  /* USER CODE END USART1_IRQn 0 */\n  HAL_UART_IRQHandler(&huart1);\n  /* USER CODE BEGIN USART1_IRQn 1 */\n\n  /* USER CODE END USART1_IRQn 1 */\n}\n\n/* USER CODE BEGIN 1 */\n\n/* USER CODE END 1 */\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/syscalls.c",
    "content": "/**\n*****************************************************************************\n**\n**  File        : syscalls.c\n**\n**  Author\t\t: Auto-generated by System workbench for STM32\n**\n**  Abstract    : System Workbench Minimal System calls file\n**\n** \t\t          For more information about which c-functions\n**                need which of these lowlevel functions\n**                please consult the Newlib libc-manual\n**\n**  Target      : STMicroelectronics STM32\n**\n**  Distribution: The file is distributed ??as is,?? without any warranty\n**                of any kind.\n**\n*****************************************************************************\n** @attention\n**\n** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>\n**\n** Redistribution and use in source and binary forms, with or without modification,\n** are permitted provided that the following conditions are met:\n**   1. Redistributions of source code must retain the above copyright notice,\n**      this list of conditions and the following disclaimer.\n**   2. Redistributions in binary form must reproduce the above copyright notice,\n**      this list of conditions and the following disclaimer in the documentation\n**      and/or other materials provided with the distribution.\n**   3. Neither the name of STMicroelectronics nor the names of its contributors\n**      may be used to endorse or promote products derived from this software\n**      without specific prior written permission.\n**\n** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\n** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE\n** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL\n** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR\n** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER\n** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,\n** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\n** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\n**\n*****************************************************************************\n*/\n\n/* Includes */\n#include <sys/stat.h>\n#include <stdlib.h>\n#include <errno.h>\n#include <stdio.h>\n#include <signal.h>\n#include <time.h>\n#include <sys/time.h>\n#include <sys/times.h>\n\n\n/* Variables */\n//#undef errno\nextern int errno;\nextern int __io_putchar(int ch) __attribute__((weak));\nextern int __io_getchar(void) __attribute__((weak));\n\nregister char * stack_ptr asm(\"sp\");\n\nchar *__env[1] = { 0 };\nchar **environ = __env;\n\n\n/* Functions */\nvoid initialise_monitor_handles()\n{\n}\n\nint _getpid(void)\n{\n    return 1;\n}\n\nint _kill(int pid, int sig)\n{\n    errno = EINVAL;\n    return -1;\n}\n\nvoid _exit (int status)\n{\n    _kill(status, -1);\n    while (1) {}\t\t/* Make sure we hang here */\n}\n\n__attribute__((weak)) int _read(int file, char *ptr, int len)\n{\n    int DataIdx;\n\n    for (DataIdx = 0; DataIdx < len; DataIdx++)\n    {\n        *ptr++ = __io_getchar();\n    }\n\n    return len;\n}\n\n__attribute__((weak)) int _write(int file, char *ptr, int len)\n{\n    int DataIdx;\n\n    for (DataIdx = 0; DataIdx < len; DataIdx++)\n    {\n        __io_putchar(*ptr++);\n    }\n    return len;\n}\n\ncaddr_t _sbrk(int incr)\n{\n    extern char end asm(\"end\");\n    static char *heap_end;\n    char *prev_heap_end;\n\n    if (heap_end == 0)\n        heap_end = &end;\n\n    prev_heap_end = heap_end;\n    if (heap_end + incr > stack_ptr)\n    {\n//\t\twrite(1, \"Heap and stack collision\\n\", 25);\n//\t\tabort();\n        errno = ENOMEM;\n        return (caddr_t) -1;\n    }\n\n    heap_end += incr;\n\n    return (caddr_t) prev_heap_end;\n}\n\n\n\nint _open(char *path, int flags, ...)\n{\n    /* Pretend like we always fail */\n    return -1;\n}\n\nint _wait(int *status)\n{\n    errno = ECHILD;\n    return -1;\n}\n\nint _unlink(char *name)\n{\n    errno = ENOENT;\n    return -1;\n}\n\nint _times(struct tms *buf)\n{\n    return -1;\n}\n\nint _stat(char *file, struct stat *st)\n{\n    st->st_mode = S_IFCHR;\n    return 0;\n}\n\nint _link(char *old, char *new)\n{\n    errno = EMLINK;\n    return -1;\n}\n\nint _fork(void)\n{\n    errno = EAGAIN;\n    return -1;\n}\n\nint _execve(char *name, char **argv, char **env)\n{\n    errno = ENOMEM;\n    return -1;\n}\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/system_stm32f1xx.c",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f1xx.c\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.\n  * \n  * 1.  This file provides two functions and one global variable to be called from \n  *     user application:\n  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier\n  *                      factors, AHB/APBx prescalers and Flash settings). \n  *                      This function is called at startup just after reset and \n  *                      before branch to main program. This call is made inside\n  *                      the \"startup_stm32f1xx_xx.s\" file.\n  *\n  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used\n  *                                  by the user application to setup the SysTick \n  *                                  timer or configure other parameters.\n  *                                     \n  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must\n  *                                 be called whenever the core clock is changed\n  *                                 during program execution.\n  *\n  * 2. After each device reset the HSI (8 MHz) is used as system clock source.\n  *    Then SystemInit() function is called, in \"startup_stm32f1xx_xx.s\" file, to\n  *    configure the system clock before to branch to main program.\n  *\n  * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depending on\n  *    the product used), refer to \"HSE_VALUE\". \n  *    When HSE is used as system clock source, directly or through PLL, and you\n  *    are using different crystal you have to adapt the HSE value to your own\n  *    configuration.\n  *        \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f1xx_system\n  * @{\n  */  \n  \n/** @addtogroup STM32F1xx_System_Private_Includes\n  * @{\n  */\n\n#include \"stm32f1xx.h\"\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_TypesDefinitions\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_Defines\n  * @{\n  */\n\n#if !defined  (HSE_VALUE) \n  #define HSE_VALUE               8000000U /*!< Default value of the External oscillator in Hz.\n                                                This value can be provided and adapted by the user application. */\n#endif /* HSE_VALUE */\n\n#if !defined  (HSI_VALUE)\n  #define HSI_VALUE               8000000U /*!< Default value of the Internal oscillator in Hz.\n                                                This value can be provided and adapted by the user application. */\n#endif /* HSI_VALUE */\n\n/*!< Uncomment the following line if you need to use external SRAM  */ \n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n/* #define DATA_IN_ExtSRAM */\n#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\n\n/* Note: Following vector table addresses must be defined in line with linker\n         configuration. */\n/*!< Uncomment the following line if you need to relocate the vector table\n     anywhere in Flash or Sram, else the vector table is kept at the automatic\n     remap of boot address selected */\n/* #define USER_VECT_TAB_ADDRESS */\n\n#if defined(USER_VECT_TAB_ADDRESS)\n/*!< Uncomment the following line if you need to relocate your vector Table\n     in Sram else user remap will be done in Flash. */\n/* #define VECT_TAB_SRAM */\n#if defined(VECT_TAB_SRAM)\n#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.\n                                                     This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.\n                                                     This value must be a multiple of 0x200. */\n#else\n#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.\n                                                     This value must be a multiple of 0x200. */\n#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.\n                                                     This value must be a multiple of 0x200. */\n#endif /* VECT_TAB_SRAM */\n#endif /* USER_VECT_TAB_ADDRESS */\n\n/******************************************************************************/\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_Variables\n  * @{\n  */\n\n  /* This variable is updated in three ways:\n      1) by calling CMSIS function SystemCoreClockUpdate()\n      2) by calling HAL API function HAL_RCC_GetHCLKFreq()\n      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \n         Note: If you use this function to configure the system clock; then there\n               is no need to call the 2 first functions listed above, since SystemCoreClock\n               variable is updated automatically.\n  */\nuint32_t SystemCoreClock = 16000000;\nconst uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};\nconst uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_FunctionPrototypes\n  * @{\n  */\n\n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n#ifdef DATA_IN_ExtSRAM\n  static void SystemInit_ExtMemCtl(void); \n#endif /* DATA_IN_ExtSRAM */\n#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F1xx_System_Private_Functions\n  * @{\n  */\n\n/**\n  * @brief  Setup the microcontroller system\n  *         Initialize the Embedded Flash Interface, the PLL and update the \n  *         SystemCoreClock variable.\n  * @note   This function should be used only after reset.\n  * @param  None\n  * @retval None\n  */\nvoid SystemInit (void)\n{\n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n  #ifdef DATA_IN_ExtSRAM\n    SystemInit_ExtMemCtl(); \n  #endif /* DATA_IN_ExtSRAM */\n#endif \n\n  /* Configure the Vector Table location -------------------------------------*/\n#if defined(USER_VECT_TAB_ADDRESS)\n  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */\n#endif /* USER_VECT_TAB_ADDRESS */\n}\n\n/**\n  * @brief  Update SystemCoreClock variable according to Clock Register Values.\n  *         The SystemCoreClock variable contains the core clock (HCLK), it can\n  *         be used by the user application to setup the SysTick timer or configure\n  *         other parameters.\n  *           \n  * @note   Each time the core clock (HCLK) changes, this function must be called\n  *         to update SystemCoreClock variable value. Otherwise, any configuration\n  *         based on this variable will be incorrect.         \n  *     \n  * @note   - The system frequency computed by this function is not the real \n  *           frequency in the chip. It is calculated based on the predefined \n  *           constant and the selected clock source:\n  *             \n  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)\n  *                                              \n  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)\n  *                          \n  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) \n  *             or HSI_VALUE(*) multiplied by the PLL factors.\n  *         \n  *         (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value\n  *             8 MHz) but the real value may vary depending on the variations\n  *             in voltage and temperature.   \n  *    \n  *         (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value\n  *              8 MHz or 25 MHz, depending on the product used), user has to ensure\n  *              that HSE_VALUE is same as the real frequency of the crystal used.\n  *              Otherwise, this function may have wrong result.\n  *                \n  *         - The result of this function could be not correct when using fractional\n  *           value for HSE crystal.\n  * @param  None\n  * @retval None\n  */\nvoid SystemCoreClockUpdate (void)\n{\n  uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;\n\n#if defined(STM32F105xC) || defined(STM32F107xC)\n  uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;\n#endif /* STM32F105xC */\n\n#if defined(STM32F100xB) || defined(STM32F100xE)\n  uint32_t prediv1factor = 0U;\n#endif /* STM32F100xB or STM32F100xE */\n    \n  /* Get SYSCLK source -------------------------------------------------------*/\n  tmp = RCC->CFGR & RCC_CFGR_SWS;\n  \n  switch (tmp)\n  {\n    case 0x00U:  /* HSI used as system clock */\n      SystemCoreClock = HSI_VALUE;\n      break;\n    case 0x04U:  /* HSE used as system clock */\n      SystemCoreClock = HSE_VALUE;\n      break;\n    case 0x08U:  /* PLL used as system clock */\n\n      /* Get PLL clock source and multiplication factor ----------------------*/\n      pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;\n      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;\n      \n#if !defined(STM32F105xC) && !defined(STM32F107xC)      \n      pllmull = ( pllmull >> 18U) + 2U;\n      \n      if (pllsource == 0x00U)\n      {\n        /* HSI oscillator clock divided by 2 selected as PLL clock entry */\n        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;\n      }\n      else\n      {\n #if defined(STM32F100xB) || defined(STM32F100xE)\n       prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;\n       /* HSE oscillator clock selected as PREDIV1 clock entry */\n       SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; \n #else\n        /* HSE selected as PLL clock entry */\n        if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)\n        {/* HSE oscillator clock divided by 2 */\n          SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;\n        }\n        else\n        {\n          SystemCoreClock = HSE_VALUE * pllmull;\n        }\n #endif\n      }\n#else\n      pllmull = pllmull >> 18U;\n      \n      if (pllmull != 0x0DU)\n      {\n         pllmull += 2U;\n      }\n      else\n      { /* PLL multiplication factor = PLL input clock * 6.5 */\n        pllmull = 13U / 2U; \n      }\n            \n      if (pllsource == 0x00U)\n      {\n        /* HSI oscillator clock divided by 2 selected as PLL clock entry */\n        SystemCoreClock = (HSI_VALUE >> 1U) * pllmull;\n      }\n      else\n      {/* PREDIV1 selected as PLL clock entry */\n        \n        /* Get PREDIV1 clock source and division factor */\n        prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;\n        prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1U;\n        \n        if (prediv1source == 0U)\n        { \n          /* HSE oscillator clock selected as PREDIV1 clock entry */\n          SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;          \n        }\n        else\n        {/* PLL2 clock selected as PREDIV1 clock entry */\n          \n          /* Get PREDIV2 division factor and PLL2 multiplication factor */\n          prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4U) + 1U;\n          pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8U) + 2U; \n          SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         \n        }\n      }\n#endif /* STM32F105xC */ \n      break;\n\n    default:\n      SystemCoreClock = HSI_VALUE;\n      break;\n  }\n  \n  /* Compute HCLK clock frequency ----------------*/\n  /* Get HCLK prescaler */\n  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];\n  /* HCLK clock frequency */\n  SystemCoreClock >>= tmp;  \n}\n\n#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)\n/**\n  * @brief  Setup the external memory controller. Called in startup_stm32f1xx.s \n  *          before jump to __main\n  * @param  None\n  * @retval None\n  */ \n#ifdef DATA_IN_ExtSRAM\n/**\n  * @brief  Setup the external memory controller. \n  *         Called in startup_stm32f1xx_xx.s/.c before jump to main.\n  *         This function configures the external SRAM mounted on STM3210E-EVAL\n  *         board (STM32 High density devices). This SRAM will be used as program\n  *         data memory (including heap and stack).\n  * @param  None\n  * @retval None\n  */ \nvoid SystemInit_ExtMemCtl(void) \n{\n  __IO uint32_t tmpreg;\n  /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is \n    required, then adjust the Register Addresses */\n\n  /* Enable FSMC clock */\n  RCC->AHBENR = 0x00000114U;\n\n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\n  \n  /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */\n  RCC->APB2ENR = 0x000001E0U;\n  \n  /* Delay after an RCC peripheral clock enabling */\n  tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\n\n  (void)(tmpreg);\n  \n/* ---------------  SRAM Data lines, NOE and NWE configuration ---------------*/\n/*----------------  SRAM Address lines configuration -------------------------*/\n/*----------------  NOE and NWE configuration --------------------------------*/  \n/*----------------  NE3 configuration ----------------------------------------*/\n/*----------------  NBL0, NBL1 configuration ---------------------------------*/\n  \n  GPIOD->CRL = 0x44BB44BBU;  \n  GPIOD->CRH = 0xBBBBBBBBU;\n\n  GPIOE->CRL = 0xB44444BBU;  \n  GPIOE->CRH = 0xBBBBBBBBU;\n\n  GPIOF->CRL = 0x44BBBBBBU;  \n  GPIOF->CRH = 0xBBBB4444U;\n\n  GPIOG->CRL = 0x44BBBBBBU;  \n  GPIOG->CRH = 0x444B4B44U;\n   \n/*----------------  FSMC Configuration ---------------------------------------*/  \n/*----------------  Enable FSMC Bank1_SRAM Bank ------------------------------*/\n  \n  FSMC_Bank1->BTCR[4U] = 0x00001091U;\n  FSMC_Bank1->BTCR[5U] = 0x00110212U;\n}\n#endif /* DATA_IN_ExtSRAM */\n#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */    \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/tim.c",
    "content": "/**\n  ******************************************************************************\n  * @file    tim.c\n  * @brief   This file provides code for the configuration\n  *          of the TIM instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"tim.h\"\n\n/* USER CODE BEGIN 0 */\n#include \"common_inc.h\"\n\n/* USER CODE END 0 */\n\nTIM_HandleTypeDef htim1;\nTIM_HandleTypeDef htim2;\nTIM_HandleTypeDef htim3;\nTIM_HandleTypeDef htim4;\n\n/* TIM1 init function */\nvoid MX_TIM1_Init(void)\n{\n\n  /* USER CODE BEGIN TIM1_Init 0 */\n\n  /* USER CODE END TIM1_Init 0 */\n\n  TIM_ClockConfigTypeDef sClockSourceConfig = {0};\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n  /* USER CODE BEGIN TIM1_Init 1 */\n\n  /* USER CODE END TIM1_Init 1 */\n  htim1.Instance = TIM1;\n  htim1.Init.Prescaler = 71;\n  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim1.Init.Period = 9999;\n  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim1.Init.RepetitionCounter = 0;\n  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;\n  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;\n  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM1_Init 2 */\n\n  /* USER CODE END TIM1_Init 2 */\n\n}\n/* TIM2 init function */\nvoid MX_TIM2_Init(void)\n{\n\n  /* USER CODE BEGIN TIM2_Init 0 */\n\n  /* USER CODE END TIM2_Init 0 */\n\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n  TIM_OC_InitTypeDef sConfigOC = {0};\n\n  /* USER CODE BEGIN TIM2_Init 1 */\n\n  /* USER CODE END TIM2_Init 1 */\n  htim2.Instance = TIM2;\n  htim2.Init.Prescaler = 0;\n  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim2.Init.Period = 1023;\n  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sConfigOC.OCMode = TIM_OCMODE_PWM1;\n  sConfigOC.Pulse = 0;\n  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;\n  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;\n  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM2_Init 2 */\n    HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_3);\n    HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_4);\n\n  /* USER CODE END TIM2_Init 2 */\n  HAL_TIM_MspPostInit(&htim2);\n\n}\n/* TIM3 init function */\nvoid MX_TIM3_Init(void)\n{\n\n  /* USER CODE BEGIN TIM3_Init 0 */\n\n  /* USER CODE END TIM3_Init 0 */\n\n  TIM_SlaveConfigTypeDef sSlaveConfig = {0};\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n  TIM_IC_InitTypeDef sConfigIC = {0};\n\n  /* USER CODE BEGIN TIM3_Init 1 */\n\n  /* USER CODE END TIM3_Init 1 */\n  htim3.Instance = TIM3;\n  htim3.Init.Prescaler = 71;\n  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim3.Init.Period = 65535;\n  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;\n  if (HAL_TIM_Base_Init(&htim3) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  if (HAL_TIM_IC_Init(&htim3) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET;\n  sSlaveConfig.InputTrigger = TIM_TS_TI1FP1;\n  sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING;\n  sSlaveConfig.TriggerFilter = 0;\n  if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;\n  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;\n  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;\n  sConfigIC.ICFilter = 0;\n  if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM3_Init 2 */\n\n  /* USER CODE END TIM3_Init 2 */\n\n}\n/* TIM4 init function */\nvoid MX_TIM4_Init(void)\n{\n\n  /* USER CODE BEGIN TIM4_Init 0 */\n\n  /* USER CODE END TIM4_Init 0 */\n\n  TIM_ClockConfigTypeDef sClockSourceConfig = {0};\n  TIM_MasterConfigTypeDef sMasterConfig = {0};\n\n  /* USER CODE BEGIN TIM4_Init 1 */\n\n  /* USER CODE END TIM4_Init 1 */\n  htim4.Instance = TIM4;\n  htim4.Init.Prescaler = 71;\n  htim4.Init.CounterMode = TIM_COUNTERMODE_UP;\n  htim4.Init.Period = 49;\n  htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;\n  htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;\n  if (HAL_TIM_Base_Init(&htim4) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;\n  if (HAL_TIM_ConfigClockSource(&htim4, &sClockSourceConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;\n  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;\n  if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN TIM4_Init 2 */\n\n  /* USER CODE END TIM4_Init 2 */\n\n}\n\nvoid HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(tim_baseHandle->Instance==TIM1)\n  {\n  /* USER CODE BEGIN TIM1_MspInit 0 */\n\n  /* USER CODE END TIM1_MspInit 0 */\n    /* TIM1 clock enable */\n    __HAL_RCC_TIM1_CLK_ENABLE();\n\n    /* TIM1 interrupt Init */\n    HAL_NVIC_SetPriority(TIM1_UP_IRQn, 5, 0);\n    HAL_NVIC_EnableIRQ(TIM1_UP_IRQn);\n  /* USER CODE BEGIN TIM1_MspInit 1 */\n\n  /* USER CODE END TIM1_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM3)\n  {\n  /* USER CODE BEGIN TIM3_MspInit 0 */\n\n  /* USER CODE END TIM3_MspInit 0 */\n    /* TIM3 clock enable */\n    __HAL_RCC_TIM3_CLK_ENABLE();\n\n    __HAL_RCC_GPIOA_CLK_ENABLE();\n    /**TIM3 GPIO Configuration\n    PA6     ------> TIM3_CH1\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_6;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);\n\n    /* TIM3 interrupt Init */\n    HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);\n    HAL_NVIC_EnableIRQ(TIM3_IRQn);\n  /* USER CODE BEGIN TIM3_MspInit 1 */\n\n  /* USER CODE END TIM3_MspInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM4)\n  {\n  /* USER CODE BEGIN TIM4_MspInit 0 */\n\n  /* USER CODE END TIM4_MspInit 0 */\n    /* TIM4 clock enable */\n    __HAL_RCC_TIM4_CLK_ENABLE();\n\n    /* TIM4 interrupt Init */\n    HAL_NVIC_SetPriority(TIM4_IRQn, 0, 0);\n    HAL_NVIC_EnableIRQ(TIM4_IRQn);\n  /* USER CODE BEGIN TIM4_MspInit 1 */\n\n  /* USER CODE END TIM4_MspInit 1 */\n  }\n}\n\nvoid HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle)\n{\n\n  if(tim_pwmHandle->Instance==TIM2)\n  {\n  /* USER CODE BEGIN TIM2_MspInit 0 */\n\n  /* USER CODE END TIM2_MspInit 0 */\n    /* TIM2 clock enable */\n    __HAL_RCC_TIM2_CLK_ENABLE();\n  /* USER CODE BEGIN TIM2_MspInit 1 */\n\n  /* USER CODE END TIM2_MspInit 1 */\n  }\n}\nvoid HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(timHandle->Instance==TIM2)\n  {\n  /* USER CODE BEGIN TIM2_MspPostInit 0 */\n\n  /* USER CODE END TIM2_MspPostInit 0 */\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**TIM2 GPIO Configuration\n    PB10     ------> TIM2_CH3\n    PB11     ------> TIM2_CH4\n    */\n    GPIO_InitStruct.Pin = HW_ELEC_BPWM_Pin|HW_ELEC_APWM_Pin;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    __HAL_AFIO_REMAP_TIM2_PARTIAL_2();\n\n  /* USER CODE BEGIN TIM2_MspPostInit 1 */\n\n  /* USER CODE END TIM2_MspPostInit 1 */\n  }\n\n}\n\nvoid HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)\n{\n\n  if(tim_baseHandle->Instance==TIM1)\n  {\n  /* USER CODE BEGIN TIM1_MspDeInit 0 */\n\n  /* USER CODE END TIM1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM1_CLK_DISABLE();\n\n    /* TIM1 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM1_UP_IRQn);\n  /* USER CODE BEGIN TIM1_MspDeInit 1 */\n\n  /* USER CODE END TIM1_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM3)\n  {\n  /* USER CODE BEGIN TIM3_MspDeInit 0 */\n\n  /* USER CODE END TIM3_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM3_CLK_DISABLE();\n\n    /**TIM3 GPIO Configuration\n    PA6     ------> TIM3_CH1\n    */\n    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6);\n\n    /* TIM3 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM3_IRQn);\n  /* USER CODE BEGIN TIM3_MspDeInit 1 */\n\n  /* USER CODE END TIM3_MspDeInit 1 */\n  }\n  else if(tim_baseHandle->Instance==TIM4)\n  {\n  /* USER CODE BEGIN TIM4_MspDeInit 0 */\n\n  /* USER CODE END TIM4_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM4_CLK_DISABLE();\n\n    /* TIM4 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(TIM4_IRQn);\n  /* USER CODE BEGIN TIM4_MspDeInit 1 */\n\n  /* USER CODE END TIM4_MspDeInit 1 */\n  }\n}\n\nvoid HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle)\n{\n\n  if(tim_pwmHandle->Instance==TIM2)\n  {\n  /* USER CODE BEGIN TIM2_MspDeInit 0 */\n\n  /* USER CODE END TIM2_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_TIM2_CLK_DISABLE();\n  /* USER CODE BEGIN TIM2_MspDeInit 1 */\n\n  /* USER CODE END TIM2_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Core/Src/usart.c",
    "content": "/**\n  ******************************************************************************\n  * @file    usart.c\n  * @brief   This file provides code for the configuration\n  *          of the USART instances.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/* Includes ------------------------------------------------------------------*/\n#include \"usart.h\"\n\n/* USER CODE BEGIN 0 */\n#include \"common_inc.h\"\n#include \"Platform/retarget.h\"\n\nvolatile uint8_t rxLen = 0;\nuint8_t rx_buffer[BUFFER_SIZE] = {0};\nvoid (* OnRecvEnd)(uint8_t* data, uint16_t len);\n/* USER CODE END 0 */\n\nUART_HandleTypeDef huart1;\nDMA_HandleTypeDef hdma_usart1_rx;\nDMA_HandleTypeDef hdma_usart1_tx;\n\n/* USART1 init function */\n\nvoid MX_USART1_UART_Init(void)\n{\n\n  /* USER CODE BEGIN USART1_Init 0 */\n\n  /* USER CODE END USART1_Init 0 */\n\n  /* USER CODE BEGIN USART1_Init 1 */\n\n  /* USER CODE END USART1_Init 1 */\n  huart1.Instance = USART1;\n  huart1.Init.BaudRate = 115200;\n  huart1.Init.WordLength = UART_WORDLENGTH_8B;\n  huart1.Init.StopBits = UART_STOPBITS_1;\n  huart1.Init.Parity = UART_PARITY_NONE;\n  huart1.Init.Mode = UART_MODE_TX_RX;\n  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;\n  huart1.Init.OverSampling = UART_OVERSAMPLING_16;\n  if (HAL_UART_Init(&huart1) != HAL_OK)\n  {\n    Error_Handler();\n  }\n  /* USER CODE BEGIN USART1_Init 2 */\n  __HAL_UART_ENABLE_IT(&huart1, UART_IT_IDLE);\n  RetargetInit(&huart1);\n  Uart_SetRxCpltCallBack(OnUartCmd);\n\n  HAL_UART_Receive_DMA(&huart1, rx_buffer, BUFFER_SIZE);\n\n  /* USER CODE END USART1_Init 2 */\n\n}\n\nvoid HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)\n{\n\n  GPIO_InitTypeDef GPIO_InitStruct = {0};\n  if(uartHandle->Instance==USART1)\n  {\n  /* USER CODE BEGIN USART1_MspInit 0 */\n\n  /* USER CODE END USART1_MspInit 0 */\n    /* USART1 clock enable */\n    __HAL_RCC_USART1_CLK_ENABLE();\n\n    __HAL_RCC_GPIOB_CLK_ENABLE();\n    /**USART1 GPIO Configuration\n    PB6     ------> USART1_TX\n    PB7     ------> USART1_RX\n    */\n    GPIO_InitStruct.Pin = GPIO_PIN_6;\n    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;\n    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    GPIO_InitStruct.Pin = GPIO_PIN_7;\n    GPIO_InitStruct.Mode = GPIO_MODE_INPUT;\n    GPIO_InitStruct.Pull = GPIO_NOPULL;\n    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);\n\n    __HAL_AFIO_REMAP_USART1_ENABLE();\n\n    /* USART1 DMA Init */\n    /* USART1_RX Init */\n    hdma_usart1_rx.Instance = DMA1_Channel5;\n    hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;\n    hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_usart1_rx.Init.Mode = DMA_NORMAL;\n    hdma_usart1_rx.Init.Priority = DMA_PRIORITY_MEDIUM;\n    if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmarx,hdma_usart1_rx);\n\n    /* USART1_TX Init */\n    hdma_usart1_tx.Instance = DMA1_Channel4;\n    hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;\n    hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE;\n    hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE;\n    hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;\n    hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;\n    hdma_usart1_tx.Init.Mode = DMA_NORMAL;\n    hdma_usart1_tx.Init.Priority = DMA_PRIORITY_MEDIUM;\n    if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK)\n    {\n      Error_Handler();\n    }\n\n    __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx);\n\n    /* USART1 interrupt Init */\n    HAL_NVIC_SetPriority(USART1_IRQn, 3, 0);\n    HAL_NVIC_EnableIRQ(USART1_IRQn);\n  /* USER CODE BEGIN USART1_MspInit 1 */\n\n  /* USER CODE END USART1_MspInit 1 */\n  }\n}\n\nvoid HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)\n{\n\n  if(uartHandle->Instance==USART1)\n  {\n  /* USER CODE BEGIN USART1_MspDeInit 0 */\n\n  /* USER CODE END USART1_MspDeInit 0 */\n    /* Peripheral clock disable */\n    __HAL_RCC_USART1_CLK_DISABLE();\n\n    /**USART1 GPIO Configuration\n    PB6     ------> USART1_TX\n    PB7     ------> USART1_RX\n    */\n    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);\n\n    /* USART1 DMA DeInit */\n    HAL_DMA_DeInit(uartHandle->hdmarx);\n    HAL_DMA_DeInit(uartHandle->hdmatx);\n\n    /* USART1 interrupt Deinit */\n    HAL_NVIC_DisableIRQ(USART1_IRQn);\n  /* USER CODE BEGIN USART1_MspDeInit 1 */\n\n  /* USER CODE END USART1_MspDeInit 1 */\n  }\n}\n\n/* USER CODE BEGIN 1 */\nvoid Uart_SetRxCpltCallBack(void(* xerc)(uint8_t*, uint16_t))\n{\n  OnRecvEnd = xerc;\n}\n/* USER CODE END 1 */\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Driver/driver_base.h",
    "content": "#ifndef CTRL_STEP_FW_DRIVER_BASE_H\n#define CTRL_STEP_FW_DRIVER_BASE_H\n\n#include <cstdint>\n\n\nclass DriverBase\n{\npublic:\n    virtual void Init() = 0;\n\n    /*\n     * FOC current vector direction is described as counts, that means\n     * we divide a 360° circle into N counts, and _directionInCount is\n     * between (0 ~ N-1), and after calculation the current range is (0 ~ 3300mA)\n     */\n    virtual void SetFocCurrentVector(uint32_t _directionInCount, int32_t _current_mA) = 0;\n\n    virtual void Sleep() = 0;\n\n    virtual void Brake() = 0;\n\n\nprotected:\n    // Used to composite the FOC current vector\n    virtual void SetTwoCoilsCurrent(uint16_t _currentA_mA, uint16_t _currentB_mA) = 0;\n\n    typedef struct\n    {\n        uint16_t sinMapPtr;\n        int16_t sinMapData;\n        uint16_t dacValue12Bits;\n    } FastSinToDac_t;\n\n    FastSinToDac_t phaseB{};\n    FastSinToDac_t phaseA{};\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Driver/sin_map.h",
    "content": "#ifndef SIN_FORM_H\n#define SIN_FORM_H\n\n#ifdef __cplusplus\nextern \"C\" {\n#endif\n\n#include <cstdint>\n#include <cmath>\n\n#define sin_pi_m2_dpix\t\t\t1024\n#define sin_pi_m2_dpiybit\t\t12\n\nconst int16_t sin_pi_m2[sin_pi_m2_dpix + 1] = {\n    0, 25, 50, 75, 101, 126, 151, 176, 201, 226, 251, 276, 301, 326, 351, 376, 401, 426, 451, 476, 501, 526,\n    551, 576, 601, 626, 651, 675, 700, 725, 750, 774,\n    799, 824, 848, 873, 897, 922, 946, 971, 995, 1020, 1044, 1068, 1092, 1117, 1141, 1165, 1189, 1213, 1237,\n    1261, 1285, 1309, 1332, 1356, 1380, 1404, 1427, 1451, 1474, 1498, 1521, 1544,\n    1567, 1591, 1614, 1637, 1660, 1683, 1706, 1729, 1751, 1774, 1797, 1819, 1842, 1864, 1886, 1909, 1931,\n    1953, 1975, 1997, 2019, 2041, 2062, 2084, 2106, 2127, 2149, 2170, 2191, 2213, 2234, 2255,\n    2276, 2296, 2317, 2338, 2359, 2379, 2399, 2420, 2440, 2460, 2480, 2500, 2520, 2540, 2559, 2579, 2598,\n    2618, 2637, 2656, 2675, 2694, 2713, 2732, 2751, 2769, 2788, 2806, 2824, 2843, 2861, 2878,\n    2896, 2914, 2932, 2949, 2967, 2984, 3001, 3018, 3035, 3052, 3068, 3085, 3102, 3118, 3134, 3150, 3166,\n    3182, 3198, 3214, 3229, 3244, 3260, 3275, 3290, 3305, 3320, 3334, 3349, 3363, 3378, 3392,\n    3406, 3420, 3433, 3447, 3461, 3474, 3487, 3500, 3513, 3526, 3539, 3551, 3564, 3576, 3588, 3600, 3612,\n    3624, 3636, 3647, 3659, 3670, 3681, 3692, 3703, 3713, 3724, 3734, 3745, 3755, 3765, 3775,\n    3784, 3794, 3803, 3812, 3822, 3831, 3839, 3848, 3857, 3865, 3873, 3881, 3889, 3897, 3905, 3912, 3920,\n    3927, 3934, 3941, 3948, 3954, 3961, 3967, 3973, 3979, 3985, 3991, 3996, 4002, 4007, 4012,\n    4017, 4022, 4027, 4031, 4036, 4040, 4044, 4048, 4052, 4055, 4059, 4062, 4065, 4068, 4071, 4074, 4076,\n    4079, 4081, 4083, 4085, 4087, 4088, 4090, 4091, 4092, 4093, 4094, 4095, 4095, 4096, 4096,\n    4096, 4096, 4096, 4095, 4095, 4094, 4093, 4092, 4091, 4090, 4088, 4087, 4085, 4083, 4081, 4079, 4076,\n    4074, 4071, 4068, 4065, 4062, 4059, 4055, 4052, 4048, 4044, 4040, 4036, 4031, 4027, 4022,\n    4017, 4012, 4007, 4002, 3996, 3991, 3985, 3979, 3973, 3967, 3961, 3954, 3948, 3941, 3934, 3927, 3920,\n    3912, 3905, 3897, 3889, 3881, 3873, 3865, 3857, 3848, 3839, 3831, 3822, 3812, 3803, 3794,\n    3784, 3775, 3765, 3755, 3745, 3734, 3724, 3713, 3703, 3692, 3681, 3670, 3659, 3647, 3636, 3624, 3612,\n    3600, 3588, 3576, 3564, 3551, 3539, 3526, 3513, 3500, 3487, 3474, 3461, 3447, 3433, 3420,\n    3406, 3392, 3378, 3363, 3349, 3334, 3320, 3305, 3290, 3275, 3260, 3244, 3229, 3214, 3198, 3182, 3166,\n    3150, 3134, 3118, 3102, 3085, 3068, 3052, 3035, 3018, 3001, 2984, 2967, 2949, 2932, 2914,\n    2896, 2878, 2861, 2843, 2824, 2806, 2788, 2769, 2751, 2732, 2713, 2694, 2675, 2656, 2637, 2618, 2598,\n    2579, 2559, 2540, 2520, 2500, 2480, 2460, 2440, 2420, 2399, 2379, 2359, 2338, 2317, 2296,\n    2276, 2255, 2234, 2213, 2191, 2170, 2149, 2127, 2106, 2084, 2062, 2041, 2019, 1997, 1975, 1953, 1931,\n    1909, 1886, 1864, 1842, 1819, 1797, 1774, 1751, 1729, 1706, 1683, 1660, 1637, 1614, 1591,\n    1567, 1544, 1521, 1498, 1474, 1451, 1427, 1404, 1380, 1356, 1332, 1309, 1285, 1261, 1237, 1213, 1189,\n    1165, 1141, 1117, 1092, 1068, 1044, 1020, 995, 971, 946, 922, 897, 873, 848, 824,\n    799, 774, 750, 725, 700, 675, 651, 626, 601, 576, 551, 526, 501, 476, 451, 426, 401, 376, 351, 326, 301,\n    276, 251, 226, 201, 176, 151, 126, 101, 75, 50, 25,\n    0, -25, -50, -75, -101, -126, -151, -176, -201, -226, -251, -276, -301, -326, -351, -376, -401, -426,\n    -451, -476, -501, -526, -551, -576, -601, -626, -651, -675, -700, -725, -750, -774,\n    -799, -824, -848, -873, -897, -922, -946, -971, -995, -1020, -1044, -1068, -1092, -1117, -1141, -1165,\n    -1189, -1213, -1237, -1261, -1285, -1309, -1332, -1356, -1380, -1404, -1427, -1451, -1474, -1498, -1521,\n    -1544,\n    -1567, -1591, -1614, -1637, -1660, -1683, -1706, -1729, -1751, -1774, -1797, -1819, -1842, -1864, -1886,\n    -1909, -1931, -1953, -1975, -1997, -2019, -2041, -2062, -2084, -2106, -2127, -2149, -2170, -2191, -2213,\n    -2234, -2255,\n    -2276, -2296, -2317, -2338, -2359, -2379, -2399, -2420, -2440, -2460, -2480, -2500, -2520, -2540, -2559,\n    -2579, -2598, -2618, -2637, -2656, -2675, -2694, -2713, -2732, -2751, -2769, -2788, -2806, -2824, -2843,\n    -2861, -2878,\n    -2896, -2914, -2932, -2949, -2967, -2984, -3001, -3018, -3035, -3052, -3068, -3085, -3102, -3118, -3134,\n    -3150, -3166, -3182, -3198, -3214, -3229, -3244, -3260, -3275, -3290, -3305, -3320, -3334, -3349, -3363,\n    -3378, -3392,\n    -3406, -3420, -3433, -3447, -3461, -3474, -3487, -3500, -3513, -3526, -3539, -3551, -3564, -3576, -3588,\n    -3600, -3612, -3624, -3636, -3647, -3659, -3670, -3681, -3692, -3703, -3713, -3724, -3734, -3745, -3755,\n    -3765, -3775,\n    -3784, -3794, -3803, -3812, -3822, -3831, -3839, -3848, -3857, -3865, -3873, -3881, -3889, -3897, -3905,\n    -3912, -3920, -3927, -3934, -3941, -3948, -3954, -3961, -3967, -3973, -3979, -3985, -3991, -3996, -4002,\n    -4007, -4012,\n    -4017, -4022, -4027, -4031, -4036, -4040, -4044, -4048, -4052, -4055, -4059, -4062, -4065, -4068, -4071,\n    -4074, -4076, -4079, -4081, -4083, -4085, -4087, -4088, -4090, -4091, -4092, -4093, -4094, -4095, -4095,\n    -4096, -4096,\n    -4096, -4096, -4096, -4095, -4095, -4094, -4093, -4092, -4091, -4090, -4088, -4087, -4085, -4083, -4081,\n    -4079, -4076, -4074, -4071, -4068, -4065, -4062, -4059, -4055, -4052, -4048, -4044, -4040, -4036, -4031,\n    -4027, -4022,\n    -4017, -4012, -4007, -4002, -3996, -3991, -3985, -3979, -3973, -3967, -3961, -3954, -3948, -3941, -3934,\n    -3927, -3920, -3912, -3905, -3897, -3889, -3881, -3873, -3865, -3857, -3848, -3839, -3831, -3822, -3812,\n    -3803, -3794,\n    -3784, -3775, -3765, -3755, -3745, -3734, -3724, -3713, -3703, -3692, -3681, -3670, -3659, -3647, -3636,\n    -3624, -3612, -3600, -3588, -3576, -3564, -3551, -3539, -3526, -3513, -3500, -3487, -3474, -3461, -3447,\n    -3433, -3420,\n    -3406, -3392, -3378, -3363, -3349, -3334, -3320, -3305, -3290, -3275, -3260, -3244, -3229, -3214, -3198,\n    -3182, -3166, -3150, -3134, -3118, -3102, -3085, -3068, -3052, -3035, -3018, -3001, -2984, -2967, -2949,\n    -2932, -2914,\n    -2896, -2878, -2861, -2843, -2824, -2806, -2788, -2769, -2751, -2732, -2713, -2694, -2675, -2656, -2637,\n    -2618, -2598, -2579, -2559, -2540, -2520, -2500, -2480, -2460, -2440, -2420, -2399, -2379, -2359, -2338,\n    -2317, -2296,\n    -2276, -2255, -2234, -2213, -2191, -2170, -2149, -2127, -2106, -2084, -2062, -2041, -2019, -1997, -1975,\n    -1953, -1931, -1909, -1886, -1864, -1842, -1819, -1797, -1774, -1751, -1729, -1706, -1683, -1660, -1637,\n    -1614, -1591,\n    -1567, -1544, -1521, -1498, -1474, -1451, -1427, -1404, -1380, -1356, -1332, -1309, -1285, -1261, -1237,\n    -1213, -1189, -1165, -1141, -1117, -1092, -1068, -1044, -1020, -995, -971, -946, -922, -897, -873, -848,\n    -824,\n    -799, -774, -750, -725, -700, -675, -651, -626, -601, -576, -551, -526, -501, -476, -451, -426, -401,\n    -376, -351, -326, -301, -276, -251, -226, -201, -176, -151, -126, -101, -75, -50, -25,\n    0,\n};\n\n#ifdef __cplusplus\n}\n#endif\n\t \n#endif\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Driver/tb67h450_base.cpp",
    "content": "#include \"tb67h450_base.h\"\n#include \"sin_map.h\"\n\nvoid TB67H450Base::Init()\n{\n    InitGpio();\n    InitPwm();\n}\n\nvoid TB67H450Base::SetFocCurrentVector(uint32_t _directionInCount, int32_t _current_mA)\n{\n    phaseB.sinMapPtr = (_directionInCount) & (0x000003FF);\n    phaseA.sinMapPtr = (phaseB.sinMapPtr + (256)) & (0x000003FF);\n\n    phaseA.sinMapData = sin_pi_m2[phaseA.sinMapPtr];\n    phaseB.sinMapData = sin_pi_m2[phaseB.sinMapPtr];\n\n    uint32_t dac_reg = abs(_current_mA);\n    dac_reg = (uint32_t) (dac_reg * 5083) >> 12;\n    dac_reg = dac_reg & (0x00000FFF);\n    phaseA.dacValue12Bits =\n        (uint32_t) (dac_reg * abs(phaseA.sinMapData)) >> sin_pi_m2_dpiybit;\n    phaseB.dacValue12Bits =\n        (uint32_t) (dac_reg * abs(phaseB.sinMapData)) >> sin_pi_m2_dpiybit;\n\n    SetTwoCoilsCurrent(phaseA.dacValue12Bits, phaseB.dacValue12Bits);\n\n    if (phaseA.sinMapData > 0)\n        SetInputA(true, false);\n    else if (phaseA.sinMapData < 0)\n        SetInputA(false, true);\n    else\n        SetInputA(true, true);\n\n    if (phaseB.sinMapData > 0)\n        SetInputB(true, false);\n    else if (phaseB.sinMapData < 0)\n        SetInputB(false, true);\n    else\n        SetInputB(true, true);\n}\n\n\nvoid TB67H450Base::SetTwoCoilsCurrent(uint16_t _currentA_3300mAIn12Bits, uint16_t _currentB_3300mAIn12Bits)\n{\n    /*\n     * After SetFocCurrentVector calculation a 12bits value was mapped to 0~3300mA.\n     * And due to used 0.1Ohm shank resistor, 0~3300mV V-ref means 0~3300mA CurrentSetPoint,\n     * For more details, see TB67H450 Datasheet page.10 .\n     */\n\n    DacOutputVoltage(_currentA_3300mAIn12Bits, _currentB_3300mAIn12Bits);\n}\n\n\nvoid TB67H450Base::Sleep()\n{\n    phaseA.dacValue12Bits = 0;\n    phaseB.dacValue12Bits = 0;\n\n    SetTwoCoilsCurrent(phaseA.dacValue12Bits, phaseB.dacValue12Bits);\n\n    SetInputA(false, false);\n    SetInputB(false, false);\n}\n\n\nvoid TB67H450Base::Brake()\n{\n    phaseA.dacValue12Bits = 0;\n    phaseB.dacValue12Bits = 0;\n\n    SetTwoCoilsCurrent(phaseA.dacValue12Bits, phaseB.dacValue12Bits);\n\n    SetInputA(true, true);\n    SetInputB(true, true);\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Driver/tb67h450_base.h",
    "content": "#ifndef CTRL_STEP_FW_TB67H450_BASE_H\n#define CTRL_STEP_FW_TB67H450_BASE_H\n\n#include \"driver_base.h\"\n\nclass TB67H450Base : public DriverBase\n{\npublic:\n    explicit TB67H450Base()\n    = default;\n\n    void Init() override;\n\n    void SetFocCurrentVector(uint32_t _directionInCount, int32_t _current_mA) override;\n\n    void Sleep() override;\n\n    void Brake() override;\n\n\nprotected:\n    void SetTwoCoilsCurrent(uint16_t _currentA_3300mAIn12Bits, uint16_t _currentB_3300mAIn12Bits) override;\n\n\n    /***** Port Specified Implements *****/\n    virtual void InitGpio();\n\n    virtual void InitPwm();\n\n    virtual void DacOutputVoltage(uint16_t _voltageA_3300mVIn12bits, uint16_t _voltageB_3300mVIn12bits);\n\n    virtual void SetInputA(bool _statusAp, bool _statusAm);\n\n    virtual void SetInputB(bool _statusBp, bool _statusBm);\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Motor/motion_planner.cpp",
    "content": "#include \"motion_planner.h\"\n#include \"math.h\"\n\n\nvoid MotionPlanner::CurrentTracker::Init()\n{\n    SetCurrentAcc(context->config->ratedCurrentAcc);\n}\n\n\nvoid MotionPlanner::CurrentTracker::NewTask(int32_t _realCurrent)\n{\n    currentIntegral = 0;\n    trackCurrent = _realCurrent;\n}\n\n\nvoid MotionPlanner::CurrentTracker::CalcSoftGoal(int32_t _goalCurrent)\n{\n    int32_t deltaCurrent = _goalCurrent - trackCurrent;\n\n    if (deltaCurrent == 0)\n    {\n        trackCurrent = _goalCurrent;\n    } else if (deltaCurrent > 0)\n    {\n        if (trackCurrent >= 0)\n        {\n            CalcCurrentIntegral(currentAcc);\n            if (trackCurrent >= _goalCurrent)\n            {\n                currentIntegral = 0;\n                trackCurrent = _goalCurrent;\n            }\n        } else\n        {\n            CalcCurrentIntegral(currentAcc);\n            if ((int32_t) trackCurrent >= 0)\n            {\n                currentIntegral = 0;\n                trackCurrent = 0;\n            }\n        }\n    } else if (deltaCurrent < 0)\n    {\n        if (trackCurrent <= 0)\n        {\n            CalcCurrentIntegral(-currentAcc);\n            if ((int32_t) trackCurrent <= (int32_t) _goalCurrent)\n            {\n                currentIntegral = 0;\n                trackCurrent = _goalCurrent;\n            }\n        } else\n        {\n            CalcCurrentIntegral(-currentAcc);\n            if ((int32_t) trackCurrent <= 0)\n            {\n                currentIntegral = 0;\n                trackCurrent = 0;\n            }\n        }\n    }\n\n    goCurrent = (int32_t) trackCurrent;\n}\n\n\nvoid MotionPlanner::CurrentTracker::CalcCurrentIntegral(int32_t _current)\n{\n    currentIntegral += _current;\n    trackCurrent += currentIntegral / context->CONTROL_FREQUENCY;\n    currentIntegral = currentIntegral % context->CONTROL_FREQUENCY;\n}\n\n\nvoid MotionPlanner::CurrentTracker::SetCurrentAcc(int32_t _currentAcc)\n{\n    currentAcc = _currentAcc;\n}\n\n\nvoid MotionPlanner::VelocityTracker::Init()\n{\n    SetVelocityAcc(context->config->ratedVelocityAcc);\n}\n\n\nvoid MotionPlanner::VelocityTracker::SetVelocityAcc(int32_t _velocityAcc)\n{\n    velocityAcc = _velocityAcc;\n}\n\n\nvoid MotionPlanner::VelocityTracker::NewTask(int32_t _realVelocity)\n{\n    velocityIntegral = 0;\n    trackVelocity = _realVelocity;\n}\n\n\nvoid MotionPlanner::VelocityTracker::CalcSoftGoal(int32_t _goalVelocity)\n{\n    int32_t deltaVelocity = _goalVelocity - trackVelocity;\n\n    if (deltaVelocity == 0)\n    {\n        trackVelocity = _goalVelocity;\n    } else if (deltaVelocity > 0)\n    {\n        if (trackVelocity >= 0)\n        {\n            CalcVelocityIntegral(velocityAcc);\n            if (trackVelocity >= _goalVelocity)\n            {\n                velocityIntegral = 0;\n                trackVelocity = _goalVelocity;\n            }\n        } else\n        {\n            CalcVelocityIntegral(velocityAcc);\n            if (trackVelocity >= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        }\n    } else if (deltaVelocity < 0)\n    {\n        if (trackVelocity <= 0)\n        {\n            CalcVelocityIntegral(-velocityAcc);\n            if (trackVelocity <= _goalVelocity)\n            {\n                velocityIntegral = 0;\n                trackVelocity = _goalVelocity;\n            }\n        } else\n        {\n            CalcVelocityIntegral(-velocityAcc);\n            if (trackVelocity <= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        }\n    }\n\n    goVelocity = (int32_t) trackVelocity;\n}\n\n\nvoid MotionPlanner::VelocityTracker::CalcVelocityIntegral(int32_t _velocity)\n{\n    velocityIntegral += _velocity;\n    trackVelocity += velocityIntegral / context->CONTROL_FREQUENCY;\n    velocityIntegral = velocityIntegral % context->CONTROL_FREQUENCY;\n}\n\n\nvoid MotionPlanner::PositionTracker::Init()\n{\n    SetVelocityAcc(context->config->ratedVelocityAcc);\n\n    /*\n     *  Allow to locking-brake when velocity is lower than (speedLockingBrake).\n     *  The best value should be (ratedMoveAcc/1000)\n     */\n    speedLockingBrake = context->config->ratedVelocityAcc / 1000;\n}\n\n\nvoid MotionPlanner::PositionTracker::SetVelocityAcc(int32_t value)\n{\n    velocityUpAcc = value;\n    velocityDownAcc = value;\n    quickVelocityDownAcc = 0.5f / (float) velocityDownAcc;\n}\n\n\nvoid MotionPlanner::PositionTracker::NewTask(int32_t real_location, int32_t real_speed)\n{\n    velocityIntegral = 0;\n    trackVelocity = real_speed;\n    positionIntegral = 0;\n    trackPosition = real_location;\n}\n\n\nvoid MotionPlanner::PositionTracker::CalcSoftGoal(int32_t _goalPosition)\n{\n    int32_t deltaPosition = _goalPosition - trackPosition;\n\n    if (deltaPosition == 0)\n    {\n        if ((trackVelocity >= -speedLockingBrake) && (trackVelocity <= speedLockingBrake))\n        {\n            velocityIntegral = 0;\n            trackVelocity = 0;\n            positionIntegral = 0;\n        } else if (trackVelocity > 0)\n        {\n            CalcVelocityIntegral(-velocityDownAcc);\n            if (trackVelocity <= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        } else if (trackVelocity < 0)\n        {\n            CalcVelocityIntegral(velocityDownAcc);\n            if (trackVelocity >= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        }\n    } else\n    {\n        if (trackVelocity == 0)\n        {\n            if (deltaPosition > 0)\n            {\n                CalcVelocityIntegral(velocityUpAcc);\n            } else\n            {\n                CalcVelocityIntegral(-velocityUpAcc);\n            }\n        } else if ((deltaPosition > 0) && (trackVelocity > 0))\n        {\n            if (trackVelocity <= context->config->ratedVelocity)\n            {\n                auto need_down_location = (int32_t) ((float) trackVelocity *\n                                                     (float) trackVelocity *\n                                                     (float) quickVelocityDownAcc);\n                if (abs(deltaPosition) > need_down_location)\n                {\n                    if (trackVelocity < context->config->ratedVelocity)\n                    {\n                        CalcVelocityIntegral(velocityUpAcc);\n                        if (trackVelocity >= context->config->ratedVelocity)\n                        {\n                            velocityIntegral = 0;\n                            trackVelocity = context->config->ratedVelocity;\n                        }\n                    } else if (trackVelocity > context->config->ratedVelocity)\n                    {\n                        CalcVelocityIntegral(-velocityDownAcc);\n                    }\n                } else\n                {\n                    CalcVelocityIntegral(-velocityDownAcc);\n                    if (trackVelocity <= 0)\n                    {\n                        velocityIntegral = 0;\n                        trackVelocity = 0;\n                    }\n                }\n            } else\n            {\n                CalcVelocityIntegral(-velocityDownAcc);\n                if (trackVelocity <= 0)\n                {\n                    velocityIntegral = 0;\n                    trackVelocity = 0;\n                }\n            }\n        } else if ((deltaPosition < 0) && (trackVelocity < 0))\n        {\n            if (trackVelocity >= -context->config->ratedVelocity)\n            {\n                auto need_down_location = (int32_t) ((float) trackVelocity *\n                                                     (float) trackVelocity *\n                                                     (float) quickVelocityDownAcc);\n                if (abs(deltaPosition) > need_down_location)\n                {\n                    if (trackVelocity > -context->config->ratedVelocity)\n                    {\n                        CalcVelocityIntegral(-velocityUpAcc);\n                        if (trackVelocity <= -context->config->ratedVelocity)\n                        {\n                            velocityIntegral = 0;\n                            trackVelocity = -context->config->ratedVelocity;\n                        }\n                    } else if (trackVelocity < -context->config->ratedVelocity)\n                    {\n                        CalcVelocityIntegral(velocityDownAcc);\n                    }\n                } else\n                {\n                    CalcVelocityIntegral(velocityDownAcc);\n                    if (trackVelocity >= 0)\n                    {\n                        velocityIntegral = 0;\n                        trackVelocity = 0;\n                    }\n                }\n            } else\n            {\n                CalcVelocityIntegral(velocityDownAcc);\n                if (trackVelocity >= 0)\n                {\n                    velocityIntegral = 0;\n                    trackVelocity = 0;\n                }\n            }\n        } else if ((deltaPosition < 0) && (trackVelocity > 0))\n        {\n            CalcVelocityIntegral(-velocityDownAcc);\n            if (trackVelocity <= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        } else if (((deltaPosition > 0) && (trackVelocity < 0)))\n        {\n            CalcVelocityIntegral(velocityDownAcc);\n            if (trackVelocity >= 0)\n            {\n                velocityIntegral = 0;\n                trackVelocity = 0;\n            }\n        }\n    }\n\n    CalcPositionIntegral(trackVelocity);\n\n    go_location = (int32_t) trackPosition;\n    go_velocity = (int32_t) trackVelocity;\n}\n\n\nvoid MotionPlanner::PositionTracker::CalcPositionIntegral(int32_t value)\n{\n    positionIntegral += value;\n    trackPosition += positionIntegral / context->CONTROL_FREQUENCY;\n    positionIntegral = positionIntegral % context->CONTROL_FREQUENCY;\n}\n\n\nvoid MotionPlanner::PositionTracker::CalcVelocityIntegral(int32_t value)\n{\n    velocityIntegral += value;\n    trackVelocity += velocityIntegral / context->CONTROL_FREQUENCY;\n    velocityIntegral = velocityIntegral % context->CONTROL_FREQUENCY;\n}\n\n\nvoid MotionPlanner::PositionInterpolator::Init()\n{\n\n}\n\n\nvoid MotionPlanner::PositionInterpolator::NewTask(int32_t _realPosition, int32_t _realVelocity)\n{\n    recordPosition = _realPosition;\n    recordPositionLast = _realPosition;\n    estPosition = _realPosition;\n    estVelocity = _realVelocity;\n}\n\n\nvoid MotionPlanner::PositionInterpolator::CalcSoftGoal(int32_t _goalPosition)\n{\n    recordPositionLast = recordPosition;\n    recordPosition = _goalPosition;\n\n    estPositionIntegral += (((recordPosition - recordPositionLast) * context->CONTROL_FREQUENCY)\n                            + ((estVelocity << 6) - estVelocity));\n    estVelocity = estPositionIntegral >> 6;\n    estPositionIntegral -= (estVelocity << 6);\n\n    estPosition = recordPosition;\n\n    goPosition = estPosition;\n    goVelocity = estVelocity;\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::SetSlowDownVelocityAcc(int32_t value)\n{\n    velocityDownAcc = value;\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::NewTask(int32_t real_location, int32_t real_speed)\n{\n    updateTime = 0;\n    overtimeFlag = false;\n    dynamicVelocityAccRemainder = 0;\n    velocityNow = real_speed;\n    velovityNowRemainder = 0;\n    positionNow = real_location;\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::CalcSoftGoal(int32_t _goalPosition, int32_t _goalVelocity)\n{\n    if (_goalVelocity != recordVelocity || _goalPosition != recordPosition)\n    {\n        updateTime = 0;\n        recordVelocity = _goalVelocity;\n        recordPosition = _goalPosition;\n\n        dynamicVelocityAcc = (int32_t) ((float) (_goalVelocity + velocityNow) *\n                                        (float) (_goalVelocity - velocityNow) /\n                                        (float) (2 * (_goalPosition - positionNow)));\n\n        overtimeFlag = false;\n    } else\n    {\n        if (updateTime >= (updateTimeout * 1000))\n            overtimeFlag = true;\n        else\n            updateTime += context->CONTROL_PERIOD;\n    }\n\n    if (overtimeFlag)\n    {\n        if (velocityNow == 0)\n        {\n            dynamicVelocityAccRemainder = 0;\n        } else if (velocityNow > 0)\n        {\n            CalcVelocityIntegral(-velocityDownAcc);\n            if (velocityNow <= 0)\n            {\n                dynamicVelocityAccRemainder = 0;\n                velocityNow = 0;\n            }\n        } else\n        {\n            CalcVelocityIntegral(velocityDownAcc);\n            if (velocityNow >= 0)\n            {\n                dynamicVelocityAccRemainder = 0;\n                velocityNow = 0;\n            }\n        }\n    } else\n    {\n        CalcVelocityIntegral(dynamicVelocityAcc);\n    }\n\n    CalcPositionIntegral(velocityNow);\n\n    goPosition = positionNow;\n    goVelocity = velocityNow;\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::CalcVelocityIntegral(int32_t value)\n{\n    dynamicVelocityAccRemainder += value; // sum up last remainder\n    velocityNow += dynamicVelocityAccRemainder / context->CONTROL_FREQUENCY;\n    dynamicVelocityAccRemainder = dynamicVelocityAccRemainder % context->CONTROL_FREQUENCY; // calc remainder\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::CalcPositionIntegral(int32_t value)\n{\n    velovityNowRemainder += value;\n    positionNow += velovityNowRemainder / context->CONTROL_FREQUENCY;\n    velovityNowRemainder = velovityNowRemainder % context->CONTROL_FREQUENCY;\n}\n\n\nvoid MotionPlanner::TrajectoryTracker::Init(int32_t _updateTimeout)\n{\n    //SetSlowDownVelocityAcc(context->config->ratedVelocityAcc / 10);\n    SetSlowDownVelocityAcc(context->config->ratedVelocityAcc);\n    updateTimeout = _updateTimeout;\n}\n\n\nvoid MotionPlanner::AttachConfig(MotionPlanner::Config_t* _config)\n{\n    config = _config;\n\n    currentTracker.Init();\n    velocityTracker.Init();\n    positionTracker.Init();\n    positionInterpolator.Init();\n    trajectoryTracker.Init(200);\n}\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Motor/motion_planner.h",
    "content": "#ifndef CTRL_STEP_FW_MOTION_PLANNER_H\n#define CTRL_STEP_FW_MOTION_PLANNER_H\n\n#include <cstdint>\n\nclass MotionPlanner\n{\npublic:\n    MotionPlanner() = default;\n\n\n    const int32_t CONTROL_FREQUENCY = 20000;                    // Hz\n    const int32_t  CONTROL_PERIOD = 1000000 / CONTROL_FREQUENCY; // uS\n\n    struct Config_t\n    {\n        int32_t encoderHomeOffset;\n        int32_t caliCurrent;\n        int32_t ratedCurrent;\n        int32_t ratedVelocity;\n        int32_t ratedVelocityAcc;\n        int32_t ratedCurrentAcc;\n    };\n\n    class CurrentTracker\n    {\n    public:\n        explicit CurrentTracker(MotionPlanner* _context) :\n            context(_context)\n        {\n        }\n\n\n        int32_t goCurrent = 0;\n\n\n        void Init();\n        void SetCurrentAcc(int32_t _currentAcc);\n        void NewTask(int32_t _realCurrent);\n        void CalcSoftGoal(int32_t _goalCurrent);\n\n\n    private:\n        MotionPlanner* context;\n        int32_t currentAcc = 0;\n        int32_t currentIntegral = 0;\n        int32_t trackCurrent = 0;\n\n\n        void CalcCurrentIntegral(int32_t _current);\n    };\n    CurrentTracker currentTracker = CurrentTracker(this);\n\n    class VelocityTracker\n    {\n    public:\n        explicit VelocityTracker(MotionPlanner* _context) :\n            context(_context)\n        {\n        }\n\n\n        int32_t goVelocity = 0;\n\n\n        void Init();\n        void SetVelocityAcc(int32_t _velocityAcc);\n        void NewTask(int32_t _realVelocity);\n        void CalcSoftGoal(int32_t _goalVelocity);\n\n\n    private:\n        MotionPlanner* context;\n        int32_t velocityAcc = 0;\n        int32_t velocityIntegral = 0;\n        int32_t trackVelocity = 0;\n\n\n        void CalcVelocityIntegral(int32_t _velocity);\n    };\n    VelocityTracker velocityTracker = VelocityTracker(this);\n\n    class PositionTracker\n    {\n    public:\n        explicit PositionTracker(MotionPlanner* _context) :\n            context(_context)\n        {\n        }\n\n\n        int32_t go_location = 0;\n        int32_t go_velocity = 0;\n\n\n        void Init();\n        void SetVelocityAcc(int32_t value);\n        void NewTask(int32_t real_location, int32_t real_speed);\n        void CalcSoftGoal(int32_t _goalPosition);\n\n\n    private:\n        MotionPlanner* context;\n        int32_t velocityUpAcc = 0;\n        int32_t velocityDownAcc = 0;\n        float quickVelocityDownAcc = 0;\n        int32_t speedLockingBrake = 0;\n        int32_t velocityIntegral = 0;\n        int32_t trackVelocity = 0;\n        int32_t positionIntegral = 0;\n        int32_t trackPosition = 0;\n\n\n        void CalcVelocityIntegral(int32_t value);\n        void CalcPositionIntegral(int32_t value);\n    };\n    PositionTracker positionTracker = PositionTracker(this);\n\n    class PositionInterpolator\n    {\n    public:\n        explicit PositionInterpolator(MotionPlanner* _context) :\n            context(_context)\n        {\n        }\n\n\n        int32_t goPosition = 0;\n        int32_t goVelocity = 0;\n\n\n        void Init();\n        void NewTask(int32_t _realPosition, int32_t _realVelocity);\n        void CalcSoftGoal(int32_t _goalPosition);\n\n\n    private:\n        MotionPlanner* context;\n        int32_t recordPosition = 0;\n        int32_t recordPositionLast = 0;\n        int32_t estPosition = 0;\n        int32_t estPositionIntegral = 0;\n        int32_t estVelocity = 0;\n    };\n    PositionInterpolator positionInterpolator = PositionInterpolator(this);\n\n    class TrajectoryTracker\n    {\n    public:\n        explicit TrajectoryTracker(MotionPlanner* _context) :\n            context(_context)\n        {\n        }\n\n\n        int32_t goPosition = 0;\n        int32_t goVelocity = 0;\n\n\n        void Init(int32_t _updateTimeout);\n        void SetSlowDownVelocityAcc(int32_t value);\n        void NewTask(int32_t real_location, int32_t real_speed);\n        void CalcSoftGoal(int32_t _goalPosition, int32_t _goalVelocity);\n\n\n    private:\n        MotionPlanner* context;\n        int32_t velocityDownAcc = 0;\n        int32_t dynamicVelocityAcc = 0;\n        int32_t updateTime = 0;\n        int32_t updateTimeout = 200; // (ms) motion set-points cmd max interval\n        bool overtimeFlag = false;\n        int32_t recordVelocity = 0;\n        int32_t recordPosition = 0;\n        int32_t dynamicVelocityAccRemainder = 0;\n        int32_t velocityNow = 0;\n        int32_t velovityNowRemainder = 0;\n        int32_t positionNow = 0;\n\n\n        void CalcVelocityIntegral(int32_t value);\n        void CalcPositionIntegral(int32_t value);\n    };\n    TrajectoryTracker trajectoryTracker = TrajectoryTracker(this);\n\n\n    void AttachConfig(Config_t* _config);\n\nprivate:\n    Config_t* config = nullptr;\n};\n\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Motor/motor.cpp",
    "content": "#include \"configurations.h\"\n#include \"motor.h\"\n\n#include <cmath>\n\n\nvoid Motor::Tick20kHz()\n{\n    // 1.Encoder data Update\n    encoder->UpdateAngle();\n\n    // 2.Motor Control Update\n    CloseLoopControlTick();\n}\n\n\nvoid Motor::AttachEncoder(EncoderBase* _encoder)\n{\n    encoder = _encoder;\n}\n\n\nvoid Motor::AttachDriver(DriverBase* _driver)\n{\n    driver = _driver;\n}\n\n\nvoid Motor::CloseLoopControlTick()\n{\n    /************************************ First Called ************************************/\n    static bool isFirstCalled = true;\n    if (isFirstCalled)\n    {\n        int32_t angle;\n        if (config.motionParams.encoderHomeOffset < MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS / 2)\n        {\n            angle =\n                encoder->angleData.rectifiedAngle >\n                config.motionParams.encoderHomeOffset + MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS / 2 ?\n                encoder->angleData.rectifiedAngle - MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS :\n                encoder->angleData.rectifiedAngle;\n        } else\n        {\n            angle =\n                encoder->angleData.rectifiedAngle <\n                config.motionParams.encoderHomeOffset - MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS / 2 ?\n                encoder->angleData.rectifiedAngle + MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS :\n                encoder->angleData.rectifiedAngle;\n        }\n\n        controller->realLapPosition = angle;\n        controller->realLapPositionLast = angle;\n        controller->realPosition = angle;\n        controller->realPositionLast = angle;\n\n        isFirstCalled = false;\n        return;\n    }\n\n    /********************************* Update Data *********************************/\n    int32_t deltaLapPosition;\n\n    // Read Encoder data\n    controller->realLapPositionLast = controller->realLapPosition;\n    controller->realLapPosition = encoder->angleData.rectifiedAngle;\n\n    // Lap-Position calculate\n    deltaLapPosition = controller->realLapPosition - controller->realLapPositionLast;\n    if (deltaLapPosition > MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS >> 1)\n        deltaLapPosition -= MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n    else if (deltaLapPosition < -MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS >> 1)\n        deltaLapPosition += MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n\n    // Naive-Position calculate\n    controller->realPositionLast = controller->realPosition;\n    controller->realPosition += deltaLapPosition;\n\n    /********************************* Estimate Data *********************************/\n    // Estimate Velocity\n    controller->estVelocityIntegral += (\n        (controller->realPosition - controller->realPositionLast) * motionPlanner.CONTROL_FREQUENCY\n        + ((controller->estVelocity << 5) - controller->estVelocity)\n    );\n    controller->estVelocity = controller->estVelocityIntegral >> 5;\n    controller->estVelocityIntegral -= (controller->estVelocity << 5);\n\n    // Estimate Position\n    controller->estLeadPosition = Controller::CompensateAdvancedAngle(controller->estVelocity);\n    controller->estPosition = controller->realPosition + controller->estLeadPosition;\n\n    // Estimate Error\n    controller->estError = controller->softPosition - controller->estPosition;\n\n    /************************************ Ctrl Loop ************************************/\n    if (controller->isStalled ||\n        controller->softDisable ||\n        !encoder->IsCalibrated())\n    {\n        controller->ClearIntegral();    // clear integrals\n        controller->focPosition = 0;    // clear outputs\n        controller->focCurrent = 0;\n        driver->Sleep();\n    } else if (controller->softBrake)\n    {\n        controller->ClearIntegral();\n        controller->focPosition = 0;\n        controller->focCurrent = 0;\n        driver->Brake();\n    } else\n    {\n        switch (controller->modeRunning)\n        {\n            case MODE_STEP_DIR:\n                controller->CalcDceToOutput(controller->softPosition, controller->softVelocity);\n                break;\n            case MODE_STOP:\n                driver->Sleep();\n                break;\n            case MODE_COMMAND_Trajectory:\n                controller->CalcDceToOutput(controller->softPosition, controller->softVelocity);\n                break;\n            case MODE_COMMAND_CURRENT:\n                controller->CalcCurrentToOutput(controller->softCurrent);\n                break;\n            case MODE_COMMAND_VELOCITY:\n                controller->CalcPidToOutput(controller->softVelocity);\n                break;\n            case MODE_COMMAND_POSITION:\n                controller->CalcDceToOutput(controller->softPosition, controller->softVelocity);\n                break;\n            case MODE_PWM_CURRENT:\n                controller->CalcCurrentToOutput(controller->softCurrent);\n                break;\n            case MODE_PWM_VELOCITY:\n                controller->CalcPidToOutput(controller->softVelocity);\n                break;\n            case MODE_PWM_POSITION:\n                controller->CalcDceToOutput(controller->softPosition, controller->softVelocity);\n                break;\n            default:\n                break;\n        }\n    }\n\n    /******************************* Mode Change Handle *******************************/\n    if (controller->modeRunning != controller->requestMode)\n    {\n        controller->modeRunning = controller->requestMode;\n        controller->softNewCurve = true;\n    }\n\n    /******************************* Update Hard-Goal *******************************/\n    if (controller->goalVelocity > config.motionParams.ratedVelocity)\n        controller->goalVelocity = config.motionParams.ratedVelocity;\n    else if (controller->goalVelocity < -config.motionParams.ratedVelocity)\n        controller->goalVelocity = -config.motionParams.ratedVelocity;\n    if (controller->goalCurrent > config.motionParams.ratedCurrent)\n        controller->goalCurrent = config.motionParams.ratedCurrent;\n    else if (controller->goalCurrent < -config.motionParams.ratedCurrent)\n        controller->goalCurrent = -config.motionParams.ratedCurrent;\n\n    /******************************** Motion Plan *********************************/\n    if ((controller->softDisable && !controller->goalDisable) ||\n        (controller->softBrake && !controller->goalBrake))\n    {\n        controller->softNewCurve = true;\n    }\n\n    if (controller->softNewCurve)\n    {\n        controller->softNewCurve = false;\n        controller->ClearIntegral();\n        controller->ClearStallFlag();\n\n        switch (controller->modeRunning)\n        {\n            case MODE_STOP:\n                break;\n            case MODE_COMMAND_POSITION:\n                motionPlanner.positionTracker.NewTask(controller->estPosition, controller->estVelocity);\n                break;\n            case MODE_COMMAND_VELOCITY:\n                motionPlanner.velocityTracker.NewTask(controller->estVelocity);\n                break;\n            case MODE_COMMAND_CURRENT:\n                motionPlanner.currentTracker.NewTask(controller->focCurrent);\n                break;\n            case MODE_COMMAND_Trajectory:\n                motionPlanner.trajectoryTracker.NewTask(controller->estPosition, controller->estVelocity);\n                break;\n            case MODE_PWM_POSITION:\n                motionPlanner.positionTracker.NewTask(controller->estPosition, controller->estVelocity);\n                break;\n            case MODE_PWM_VELOCITY:\n                motionPlanner.velocityTracker.NewTask(controller->estVelocity);\n                break;\n            case MODE_PWM_CURRENT:\n                motionPlanner.currentTracker.NewTask(controller->focCurrent);\n                break;\n            case MODE_STEP_DIR:\n                motionPlanner.positionInterpolator.NewTask(controller->estPosition, controller->estVelocity);\n                // step/dir mode uses delta-position, so stay where we are\n                controller->goalPosition = controller->estPosition;\n                break;\n            default:\n                break;\n        }\n    }\n\n    /******************************* Update Soft Goal *******************************/\n    switch (controller->modeRunning)\n    {\n        case MODE_STOP:\n            break;\n        case MODE_COMMAND_POSITION:\n            motionPlanner.positionTracker.CalcSoftGoal(controller->goalPosition);\n            controller->softPosition = motionPlanner.positionTracker.go_location;\n            controller->softVelocity = motionPlanner.positionTracker.go_velocity;\n            break;\n        case MODE_COMMAND_VELOCITY:\n            motionPlanner.velocityTracker.CalcSoftGoal(controller->goalVelocity);\n            controller->softVelocity = motionPlanner.velocityTracker.goVelocity;\n            break;\n        case MODE_COMMAND_CURRENT:\n            motionPlanner.currentTracker.CalcSoftGoal(controller->goalCurrent);\n            controller->softCurrent = motionPlanner.currentTracker.goCurrent;\n            break;\n        case MODE_COMMAND_Trajectory:\n            motionPlanner.trajectoryTracker.CalcSoftGoal(controller->goalPosition, controller->goalVelocity);\n            controller->softPosition = motionPlanner.trajectoryTracker.goPosition;\n            controller->softVelocity = motionPlanner.trajectoryTracker.goVelocity;\n            break;\n        case MODE_PWM_POSITION:\n            motionPlanner.positionTracker.CalcSoftGoal(controller->goalPosition);\n            controller->softPosition = motionPlanner.positionTracker.go_location;\n            controller->softVelocity = motionPlanner.positionTracker.go_velocity;\n            break;\n        case MODE_PWM_VELOCITY:\n            motionPlanner.velocityTracker.CalcSoftGoal(controller->goalVelocity);\n            controller->softVelocity = motionPlanner.velocityTracker.goVelocity;\n            break;\n        case MODE_PWM_CURRENT:\n            motionPlanner.currentTracker.CalcSoftGoal(controller->goalCurrent);\n            controller->softCurrent = motionPlanner.currentTracker.goCurrent;\n            break;\n        case MODE_STEP_DIR:\n            motionPlanner.positionInterpolator.CalcSoftGoal(controller->goalPosition);\n            controller->softPosition = motionPlanner.positionInterpolator.goPosition;\n            controller->softVelocity = motionPlanner.positionInterpolator.goVelocity;\n            break;\n        default:\n            break;\n    }\n\n    controller->softDisable = controller->goalDisable;\n    controller->softBrake = controller->goalBrake;\n\n    /******************************** State Check ********************************/\n    int32_t current = abs(controller->focCurrent);\n\n    // Stall detect\n    if (controller->config->stallProtectSwitch)\n    {\n        if (// Current Mode\n            ((controller->modeRunning == MODE_COMMAND_CURRENT ||\n              controller->modeRunning == MODE_PWM_CURRENT) &&\n             (current != 0))\n            || // Other Mode\n            current == config.motionParams.ratedCurrent)\n        {\n            if (abs(controller->estVelocity) < MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS / 5)\n            {\n                if (controller->stalledTime >= 1000 * 1000)\n                    controller->isStalled = true;\n                else\n                    controller->stalledTime += motionPlanner.CONTROL_PERIOD;\n            }\n        } else // can ONLY clear stall flag  MANUALLY\n        {\n            controller->stalledTime = 0;\n        }\n    }\n\n    // Overload detect\n    if ((controller->modeRunning != MODE_COMMAND_CURRENT) &&\n        (controller->modeRunning != MODE_PWM_CURRENT) &&\n        (current == config.motionParams.ratedCurrent))\n    {\n        if (controller->overloadTime >= 1000 * 1000)\n            controller->overloadFlag = true;\n        else\n            controller->overloadTime += motionPlanner.CONTROL_PERIOD;\n    } else // auto clear overload flag when released\n    {\n        controller->overloadTime = 0;\n        controller->overloadFlag = false;\n    }\n\n    /******************************** Update State ********************************/\n    if (!encoder->IsCalibrated())\n        controller->state = STATE_NO_CALIB;\n    else if (controller->modeRunning == MODE_STOP)\n        controller->state = STATE_STOP;\n    else if (controller->isStalled)\n        controller->state = STATE_STALL;\n    else if (controller->overloadFlag)\n        controller->state = STATE_OVERLOAD;\n    else\n    {\n        if (controller->modeRunning == MODE_COMMAND_POSITION)\n        {\n            if ((controller->softPosition == controller->goalPosition)\n                && (controller->softVelocity == 0))\n                controller->state = STATE_FINISH;\n            else\n                controller->state = STATE_RUNNING;\n        } else if (controller->modeRunning == MODE_COMMAND_VELOCITY)\n        {\n            if (controller->softVelocity == controller->goalVelocity)\n                controller->state = STATE_FINISH;\n            else\n                controller->state = STATE_RUNNING;\n        } else if (controller->modeRunning == MODE_COMMAND_CURRENT)\n        {\n            if (controller->softCurrent == controller->goalCurrent)\n                controller->state = STATE_FINISH;\n            else\n                controller->state = STATE_RUNNING;\n        } else\n        {\n            controller->state = STATE_FINISH;\n        }\n    }\n}\n\n\nvoid Motor::Controller::CalcCurrentToOutput(int32_t current)\n{\n    focCurrent = current;\n\n    if (focCurrent > 0)\n        focPosition = estPosition + context->SOFT_DIVIDE_NUM; // ahead phase of 90°\n    else if (focCurrent < 0)\n        focPosition = estPosition - context->SOFT_DIVIDE_NUM; // behind phase of 90°\n    else focPosition = estPosition;\n\n    context->driver->SetFocCurrentVector(focPosition, focCurrent);\n}\n\n\nvoid Motor::Controller::CalcPidToOutput(int32_t _speed)\n{\n    config->pid.vErrorLast = config->pid.vError;\n    config->pid.vError = _speed - estVelocity;\n    if (config->pid.vError > (1024 * 1024)) config->pid.vError = (1024 * 1024);\n    if (config->pid.vError < (-1024 * 1024)) config->pid.vError = (-1024 * 1024);\n    config->pid.outputKp = ((config->pid.kp) * (config->pid.vError));\n\n    config->pid.integralRound += (config->pid.ki * config->pid.vError);\n    config->pid.integralRemainder = config->pid.integralRound >> 10;\n    config->pid.integralRound -= (config->pid.integralRemainder << 10);\n    config->pid.outputKi += config->pid.integralRemainder;\n    // integralRound limitation is  ratedCurrent*1024\n    if (config->pid.outputKi > context->config.motionParams.ratedCurrent << 10)\n        config->pid.outputKi = context->config.motionParams.ratedCurrent << 10;\n    else if (config->pid.outputKi < -(context->config.motionParams.ratedCurrent << 10))\n        config->pid.outputKi = -(context->config.motionParams.ratedCurrent << 10);\n\n    config->pid.outputKd = config->pid.kd * (config->pid.vError - config->pid.vErrorLast);\n\n    config->pid.output = (config->pid.outputKp + config->pid.outputKi + config->pid.outputKd) >> 10;\n    if (config->pid.output > context->config.motionParams.ratedCurrent)\n        config->pid.output = context->config.motionParams.ratedCurrent;\n    else if (config->pid.output < -context->config.motionParams.ratedCurrent)\n        config->pid.output = -context->config.motionParams.ratedCurrent;\n\n    CalcCurrentToOutput(config->pid.output);\n}\n\n\nvoid Motor::Controller::CalcDceToOutput(int32_t _location, int32_t _speed)\n{\n    config->dce.pError = _location - estPosition;\n    if (config->dce.pError > (3200)) config->dce.pError = (3200);   // limited pError to 1/16r (51200/16)\n    if (config->dce.pError < (-3200)) config->dce.pError = (-3200);\n    config->dce.vError = (_speed - estVelocity) >> 7;\n    if (config->dce.vError > (4000)) config->dce.vError = (4000);   // limited vError\n    if (config->dce.vError < (-4000)) config->dce.vError = (-4000);\n\n    config->dce.outputKp = config->dce.kp * config->dce.pError;\n\n    config->dce.integralRound += (config->dce.ki * config->dce.pError + config->dce.kv * config->dce.vError);\n    config->dce.integralRemainder = config->dce.integralRound >> 7;\n    config->dce.integralRound -= (config->dce.integralRemainder << 7);\n    config->dce.outputKi += config->dce.integralRemainder;\n    // limited to ratedCurrent * 1024, should be TUNED when use different scene\n    if (config->dce.outputKi > context->config.motionParams.ratedCurrent << 10)\n        config->dce.outputKi = context->config.motionParams.ratedCurrent << 10;\n    else if (config->dce.outputKi < -(context->config.motionParams.ratedCurrent << 10))\n        config->dce.outputKi = -(context->config.motionParams.ratedCurrent << 10);\n\n    config->dce.outputKd = ((config->dce.kd) * (config->dce.vError));\n\n    config->dce.output = (config->dce.outputKp + config->dce.outputKi + config->dce.outputKd) >> 10;\n    if (config->dce.output > context->config.motionParams.ratedCurrent)\n        config->dce.output = context->config.motionParams.ratedCurrent;\n    else if (config->dce.output < -context->config.motionParams.ratedCurrent)\n        config->dce.output = -context->config.motionParams.ratedCurrent;\n\n    CalcCurrentToOutput(config->dce.output);\n}\n\n\nvoid Motor::Controller::SetCtrlMode(Motor::Mode_t _mode)\n{\n    requestMode = _mode;\n}\n\n\nvoid Motor::Controller::AddTrajectorySetPoint(int32_t _pos, int32_t _vel)\n{\n    SetPositionSetPoint(_pos);\n    SetVelocitySetPoint(_vel);\n}\n\n\nvoid Motor::Controller::SetPositionSetPoint(int32_t _pos)\n{\n    goalPosition = _pos + context->config.motionParams.encoderHomeOffset;\n}\n\n\nbool Motor::Controller::SetPositionSetPointWithTime(int32_t _pos, float _time)\n{\n    int32_t deltaPos = abs(_pos - realPosition + context->config.motionParams.encoderHomeOffset);\n\n    float pMax = (float) context->config.motionParams.ratedVelocityAcc * _time * _time / 4;\n    if ((float) deltaPos > pMax)\n    {\n        context->config.motionParams.ratedVelocity = boardConfig.velocityLimit;\n        SetPositionSetPoint(_pos);\n\n        return false;\n    } else\n    {\n        float vMax = _time * (float) context->config.motionParams.ratedVelocityAcc;\n        vMax -= (float) context->config.motionParams.ratedVelocityAcc *\n                (sqrtf(_time * _time - 4 * (float) deltaPos /\n                                       (float) context->config.motionParams.ratedVelocityAcc));\n        vMax /= 2;\n\n        context->config.motionParams.ratedVelocity = (int32_t) vMax;\n        SetPositionSetPoint(_pos);\n\n        return true;\n    }\n}\n\n\nvoid Motor::Controller::SetVelocitySetPoint(int32_t _vel)\n{\n    if ((_vel >= -context->config.motionParams.ratedVelocity) &&\n        (_vel <= context->config.motionParams.ratedVelocity))\n    {\n        goalVelocity = _vel;\n    }\n}\n\n\nfloat Motor::Controller::GetPosition(bool _isLap)\n{\n    return _isLap ?\n           (float) (realLapPosition - context->config.motionParams.encoderHomeOffset) /\n           (float) (context->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS)\n                  :\n           (float) (realPosition - context->config.motionParams.encoderHomeOffset) /\n           (float) (context->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n}\n\n\nfloat Motor::Controller::GetVelocity()\n{\n    return (float) estVelocity / (float) context->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n}\n\n\nfloat Motor::Controller::GetFocCurrent()\n{\n    return (float) focCurrent / 1000.f;\n}\n\n\nvoid Motor::Controller::SetCurrentSetPoint(int32_t _cur)\n{\n    if (_cur > context->config.motionParams.ratedCurrent)\n        goalCurrent = context->config.motionParams.ratedCurrent;\n    else if (_cur < -context->config.motionParams.ratedCurrent)\n        goalCurrent = -context->config.motionParams.ratedCurrent;\n    else\n        goalCurrent = _cur;\n}\n\n\nvoid Motor::Controller::SetDisable(bool _disable)\n{\n    goalDisable = _disable;\n}\n\n\nvoid Motor::Controller::SetBrake(bool _brake)\n{\n    goalBrake = _brake;\n\n}\n\n\nvoid Motor::Controller::ClearStallFlag()\n{\n    stalledTime = 0;\n    isStalled = false;\n}\n\n\nint32_t Motor::Controller::CompensateAdvancedAngle(int32_t _vel)\n{\n    /*\n     * The code is for DPS series sensors, need to measured and renew for TLE5012/MT6816.\n     */\n\n    int32_t compensate;\n\n    if (_vel < 0)\n    {\n        if (_vel > -100000) compensate = 0;\n        else if (_vel > -1300000) compensate = (((_vel + 100000) * 262) >> 20) - 0;\n        else if (_vel > -2200000) compensate = (((_vel + 1300000) * 105) >> 20) - 300;\n        else compensate = (((_vel + 2200000) * 52) >> 20) - 390;\n\n        if (compensate < -430) compensate = -430;\n    } else\n    {\n        if (_vel < 100000) compensate = 0;\n        else if (_vel < 1300000) compensate = (((_vel - 100000) * 262) >> 20) + 0;\n        else if (_vel < 2200000) compensate = (((_vel - 1300000) * 105) >> 20) + 300;\n        else compensate = (((_vel - 2200000) * 52) >> 20) + 390;\n\n        if (compensate > 430) compensate = 430;\n    }\n\n    return compensate;\n}\n\n\nvoid Motor::Controller::Init()\n{\n    requestMode = boardConfig.enableMotorOnBoot ? static_cast<Mode_t>(boardConfig.defaultMode) : MODE_STOP;\n\n    modeRunning = MODE_STOP;\n    state = STATE_STOP;\n\n    realLapPosition = 0;\n    realLapPositionLast = 0;\n    realPosition = 0;\n    realPositionLast = 0;\n\n    estVelocityIntegral = 0;\n    estVelocity = 0;\n    estLeadPosition = 0;\n    estPosition = 0;\n    estError = 0;\n\n    goalPosition = context->config.motionParams.encoderHomeOffset;\n    goalVelocity = 0;\n    goalCurrent = 0;\n    goalDisable = false;\n    goalBrake = false;\n\n    softPosition = 0;\n    softVelocity = 0;\n    softCurrent = 0;\n    softDisable = false;\n    softBrake = false;\n    softNewCurve = false;\n\n    focPosition = 0;\n    focCurrent = 0;\n\n    stalledTime = 0;\n    isStalled = false;\n\n    overloadTime = 0;\n    overloadFlag = false;\n\n    config->pid.vError = 0;\n    config->pid.vErrorLast = 0;\n    config->pid.outputKp = 0;\n    config->pid.outputKi = 0;\n    config->pid.outputKd = 0;\n    config->pid.integralRound = 0;\n    config->pid.integralRemainder = 0;\n    config->pid.output = 0;\n\n    config->dce.pError = 0;\n    config->dce.vError = 0;\n    config->dce.outputKp = 0;\n    config->dce.outputKi = 0;\n    config->dce.outputKd = 0;\n    config->dce.integralRound = 0;\n    config->dce.integralRemainder = 0;\n    config->dce.output = 0;\n}\n\n\nvoid Motor::Controller::ApplyPosAsHomeOffset()\n{\n    context->config.motionParams.encoderHomeOffset = realPosition %\n                                                     context->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n}\n\n\nvoid Motor::Controller::AttachConfig(Motor::Controller::Config_t* _config)\n{\n    config = _config;\n}\n\n\nvoid Motor::Controller::ClearIntegral() const\n{\n    config->pid.integralRound = 0;\n    config->pid.integralRemainder = 0;\n    config->pid.outputKi = 0;\n\n    config->dce.integralRound = 0;\n    config->dce.integralRemainder = 0;\n    config->dce.outputKi = 0;\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Motor/motor.h",
    "content": "#ifndef CTRL_STEP_FW_MOTOR_H\n#define CTRL_STEP_FW_MOTOR_H\n\n#include \"Motor/motion_planner.h\"\n#include \"Sensor/Encoder/encoder_base.h\"\n#include \"Driver/driver_base.h\"\n\nclass Motor\n{\npublic:\n    Motor() :\n        controller(&controllerInstance)\n    {\n        /****************** Default Configs *******************/\n        config.motionParams.encoderHomeOffset = 0;\n        config.motionParams.caliCurrent = 2000;             // (mA)\n        config.motionParams.ratedCurrent = 1000;            // (mA)\n        config.motionParams.ratedCurrentAcc = 2 * 1000;     // (mA/s)\n        config.motionParams.ratedVelocity = 30 * MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n        config.motionParams.ratedVelocityAcc = 1000 * MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n\n        config.ctrlParams.stallProtectSwitch = false;\n        config.ctrlParams.pid =\n            Controller::PID_t{\n                .kp = 5,\n                .ki = 30,\n                .kd = 0\n            };\n        config.ctrlParams.dce =\n            Controller::DCE_t{\n                .kp = 200,\n                .kv = 80,\n                .ki = 300,\n                .kd = 250\n            };\n\n        /*****************************************************/\n\n\n        motionPlanner.AttachConfig(&config.motionParams);\n        controller->AttachConfig(&config.ctrlParams);\n    }\n\n\n    const int32_t MOTOR_ONE_CIRCLE_HARD_STEPS = 200; // for 1.8° step-motors\n    const int32_t SOFT_DIVIDE_NUM = 256;\n    const int32_t MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS = MOTOR_ONE_CIRCLE_HARD_STEPS * SOFT_DIVIDE_NUM;\n\n    typedef enum\n    {\n        MODE_STOP,\n        MODE_COMMAND_POSITION,\n        MODE_COMMAND_VELOCITY,\n        MODE_COMMAND_CURRENT,\n        MODE_COMMAND_Trajectory,\n        MODE_PWM_POSITION,\n        MODE_PWM_VELOCITY,\n        MODE_PWM_CURRENT,\n        MODE_STEP_DIR,\n    } Mode_t;\n\n    typedef enum\n    {\n        STATE_STOP,\n        STATE_FINISH,\n        STATE_RUNNING,\n        STATE_OVERLOAD,\n        STATE_STALL,\n        STATE_NO_CALIB\n    } State_t;\n\n\n    class Controller\n    {\n    public:\n        friend Motor;\n\n        typedef struct\n        {\n            bool kpValid, kiValid, kdValid;\n            int32_t kp, ki, kd;\n            int32_t vError, vErrorLast;\n            int32_t outputKp, outputKi, outputKd;\n            int32_t integralRound;\n            int32_t integralRemainder;\n            int32_t output;\n        } PID_t;\n\n        typedef struct\n        {\n            int32_t kp, kv, ki, kd;\n            int32_t pError, vError;\n            int32_t outputKp, outputKi, outputKd;\n            int32_t integralRound;\n            int32_t integralRemainder;\n            int32_t output;\n        } DCE_t;\n\n        typedef struct\n        {\n            PID_t pid;\n            DCE_t dce;\n\n            bool stallProtectSwitch;\n        } Config_t;\n\n\n        explicit Controller(Motor* _context)\n        {\n            context = _context;\n\n            requestMode = MODE_STOP;\n            modeRunning = MODE_STOP;\n        }\n\n\n        Config_t* config = nullptr;\n        Mode_t requestMode;\n        Mode_t modeRunning;\n        State_t state = STATE_STOP;\n        bool isStalled = false;\n\n\n        void Init();\n        void SetCtrlMode(Mode_t _mode);\n        void SetCurrentSetPoint(int32_t _cur);\n        void SetVelocitySetPoint(int32_t _vel);\n        void SetPositionSetPoint(int32_t _pos);\n        bool SetPositionSetPointWithTime(int32_t _pos, float _time);\n        float GetPosition(bool _isLap = false);\n        float GetVelocity();\n        float GetFocCurrent();\n        void AddTrajectorySetPoint(int32_t _pos, int32_t _vel);\n        void SetDisable(bool _disable);\n        void SetBrake(bool _brake);\n        void ApplyPosAsHomeOffset();\n        void ClearStallFlag();\n\n\n    private:\n        Motor* context;\n        int32_t realLapPosition{};\n        int32_t realLapPositionLast{};\n        int32_t realPosition{};\n        int32_t realPositionLast{};\n        int32_t estVelocity{};\n        int32_t estVelocityIntegral{};\n        int32_t estLeadPosition{};\n        int32_t estPosition{};\n        int32_t estError{};\n        int32_t focCurrent{};\n        int32_t goalPosition{};\n        int32_t goalVelocity{};\n        int32_t goalCurrent{};\n        bool goalDisable{};\n        bool goalBrake{};\n        int32_t softPosition{};\n        int32_t softVelocity{};\n        int32_t softCurrent{};\n        bool softDisable{};\n        bool softBrake{};\n        bool softNewCurve{};\n        int32_t focPosition{};\n        uint32_t stalledTime{};\n        uint32_t overloadTime{};\n        bool overloadFlag{};\n\n\n        void AttachConfig(Config_t* _config);\n        void CalcCurrentToOutput(int32_t current);\n        void CalcPidToOutput(int32_t _speed);\n        void CalcDceToOutput(int32_t _location, int32_t _speed);\n        void ClearIntegral() const;\n\n        static int32_t CompensateAdvancedAngle(int32_t _vel);\n    };\n\n\n    struct Config_t\n    {\n        MotionPlanner::Config_t motionParams{};\n        Controller::Config_t ctrlParams{};\n    };\n    Config_t config;\n\n    MotionPlanner motionPlanner;\n    Controller* controller = nullptr;\n    EncoderBase* encoder = nullptr;\n    DriverBase* driver = nullptr;\n\n\n    void Tick20kHz();\n    void AttachEncoder(EncoderBase* _encoder);\n    void AttachDriver(DriverBase* _driver);\n\n\nprivate:\n    Controller controllerInstance = Controller(this);\n\n\n    void CloseLoopControlTick();\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Sensor/Encoder/encoder_base.h",
    "content": "#ifndef CTRL_STEP_FW_ENCODER_H\n#define CTRL_STEP_FW_ENCODER_H\n\n#include <cstdint>\n\n\nclass EncoderBase\n{\npublic:\n    typedef struct\n    {\n        uint16_t rawAngle;          // raw data\n        uint16_t rectifiedAngle;    // calibrated rawAngle data\n        bool rectifyValid;\n    } AngleData_t;\n    AngleData_t angleData{0};\n\n\n    /*\n     * Resolution is (2^14 = 16384), each state will use an uint16 data\n     * as map, thus total need 32K-flash for calibration.\n    */\n    const int32_t RESOLUTION = ((int32_t) ((0x00000001U) << 14));\n\n    virtual bool Init() = 0;\n\n    // Get current rawAngle\n    virtual uint16_t UpdateAngle() = 0;\n\n    virtual bool IsCalibrated() = 0;\n\n\nprivate:\n\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Sensor/Encoder/encoder_calibrator_base.cpp",
    "content": "#include <Platform/Memory/stockpile_f103cb.h>\n#include <valarray>\n#include \"encoder_calibrator_base.h\"\n\nint32_t EncoderCalibratorBase::CycleDataAverage(const uint16_t* _data, uint16_t _length, int32_t _cyc)\n{\n    int32_t sumData = 0;\n    int32_t subData;\n    int32_t diffData;\n\n    sumData += (int32_t) _data[0];\n    for (uint16_t i = 1; i < _length; i++)\n    {\n        diffData = (int32_t) _data[i];\n        subData = (int32_t) _data[i] - (int32_t) _data[0];\n        if (subData > (_cyc >> 1)) diffData = (int32_t) _data[i] - _cyc;\n        if (subData < (-_cyc >> 1)) diffData = (int32_t) _data[i] + _cyc;\n        sumData += diffData;\n    }\n\n    sumData = sumData / _length;\n\n    if (sumData < 0) sumData += _cyc;\n    if (sumData > _cyc) sumData -= _cyc;\n\n    return sumData;\n}\n\n\nvoid EncoderCalibratorBase::CalibrationDataCheck()\n{\n    uint32_t count;\n    int32_t subData;\n\n    int32_t calibSampleResolution = motor->encoder->RESOLUTION / MOTOR_ONE_CIRCLE_HARD_STEPS;\n    for (count = 0; count < MOTOR_ONE_CIRCLE_HARD_STEPS + 1; count++)\n    {\n        sampleDataAverageForward[count] = (uint16_t) CycleAverage((int32_t) sampleDataAverageForward[count],\n                                                                  (int32_t) sampleDataAverageBackward[count],\n                                                                  motor->encoder->RESOLUTION);\n    }\n    subData = CycleSubtract((int32_t) sampleDataAverageForward[0],\n                            (int32_t) sampleDataAverageForward[MOTOR_ONE_CIRCLE_HARD_STEPS - 1],\n                            motor->encoder->RESOLUTION);\n    if (subData == 0)\n    {\n        errorCode = CALI_ERROR_AVERAGE_DIR;\n        return;\n    } else\n    {\n        goDirection = subData > 0;\n    }\n\n    for (count = 1; count < MOTOR_ONE_CIRCLE_HARD_STEPS; count++)\n    {\n        subData = CycleSubtract((int32_t) sampleDataAverageForward[count],\n                                (int32_t) sampleDataAverageForward[count - 1],\n                                motor->encoder->RESOLUTION);\n        if (abs(subData) > (calibSampleResolution * 3 / 2)) // delta-data too large\n        {\n            errorCode = CALI_ERROR_AVERAGE_CONTINUTY;\n            return;\n        }\n        if (abs(subData) < (calibSampleResolution * 1 / 2)) // delta-data too small\n        {\n            errorCode = CALI_ERROR_AVERAGE_CONTINUTY;\n            return;\n        }\n        if (subData == 0)\n        {\n            errorCode = CALI_ERROR_AVERAGE_DIR;\n            return;\n        }\n        if ((subData > 0) && (!goDirection))\n        {\n            errorCode = CALI_ERROR_AVERAGE_DIR;\n            return;\n        }\n        if ((subData < 0) && (goDirection))\n        {\n            errorCode = CALI_ERROR_AVERAGE_DIR;\n            return;\n        }\n    }\n\n\n    uint32_t step_num = 0;\n    if (goDirection)\n    {\n        for (count = 0; count < MOTOR_ONE_CIRCLE_HARD_STEPS; count++)\n        {\n            subData = (int32_t) sampleDataAverageForward[CycleMod(count + 1, MOTOR_ONE_CIRCLE_HARD_STEPS)] -\n                      (int32_t) sampleDataAverageForward[CycleMod(count, MOTOR_ONE_CIRCLE_HARD_STEPS)];\n            if (subData < 0)\n            {\n                step_num++;\n                rcdX = (int32_t) count;\n                rcdY = (motor->encoder->RESOLUTION - 1) -\n                       sampleDataAverageForward[CycleMod(rcdX, MOTOR_ONE_CIRCLE_HARD_STEPS)];\n            }\n        }\n        if (step_num != 1)\n        {\n            errorCode = CALI_ERROR_PHASE_STEP;\n            return;\n        }\n    } else\n    {\n        for (count = 0; count < MOTOR_ONE_CIRCLE_HARD_STEPS; count++)\n        {\n            subData = (int32_t) sampleDataAverageForward[CycleMod(count + 1, MOTOR_ONE_CIRCLE_HARD_STEPS)] -\n                      (int32_t) sampleDataAverageForward[CycleMod(count, MOTOR_ONE_CIRCLE_HARD_STEPS)];\n            if (subData > 0)\n            {\n                step_num++;\n                rcdX = (int32_t) count;\n                rcdY = (motor->encoder->RESOLUTION - 1) -\n                       sampleDataAverageForward[CycleMod(rcdX + 1, MOTOR_ONE_CIRCLE_HARD_STEPS)];\n            }\n        }\n        if (step_num != 1)\n        {\n            errorCode = CALI_ERROR_PHASE_STEP;\n            return;\n        }\n    }\n\n    errorCode = CALI_NO_ERROR;\n}\n\n\nvoid EncoderCalibratorBase::Tick20kHz()\n{\n    motor->encoder->UpdateAngle();\n\n    switch (state)\n    {\n        case CALI_DISABLE:\n            if (isTriggered)\n            {\n                motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n                goPosition = motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n                sampleCount = 0;\n                state = CALI_FORWARD_PREPARE;\n                errorCode = CALI_NO_ERROR;\n            }\n            break;\n        case CALI_FORWARD_PREPARE:\n            goPosition += AUTO_CALIB_SPEED;\n            motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n            if (goPosition == 2 * motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS)\n            {\n                goPosition = motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS;\n                state = CALI_FORWARD_MEASURE;\n            }\n            break;\n        case CALI_FORWARD_MEASURE:\n            if ((goPosition % motor->SOFT_DIVIDE_NUM) == 0)\n            {\n                sampleDataRaw[sampleCount++] = motor->encoder->angleData.rawAngle;\n                if (sampleCount == EncoderCalibratorBase::SAMPLE_COUNTS_PER_STEP)\n                {\n                    sampleDataAverageForward[(goPosition - motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS) /\n                                             motor->SOFT_DIVIDE_NUM]\n                        = CycleDataAverage(sampleDataRaw, EncoderCalibratorBase::SAMPLE_COUNTS_PER_STEP,\n                                           motor->encoder->RESOLUTION);\n\n                    sampleCount = 0;\n                    goPosition += FINE_TUNE_CALIB_SPEED;\n                }\n            } else\n            {\n                goPosition += FINE_TUNE_CALIB_SPEED;\n            }\n\n            motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n\n            if (goPosition > (2 * motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS))\n            {\n                state = CALI_BACKWARD_RETURN;\n            }\n            break;\n        case CALI_BACKWARD_RETURN:\n            goPosition += FINE_TUNE_CALIB_SPEED;\n            motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n\n            if (goPosition ==\n                (2 * motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS + motor->SOFT_DIVIDE_NUM * 20))\n            {\n                state = CALI_BACKWARD_GAP_DISMISS;\n            }\n            break;\n        case CALI_BACKWARD_GAP_DISMISS:\n            goPosition -= FINE_TUNE_CALIB_SPEED;\n            motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n            if (goPosition == (2 * motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS))\n            {\n                state = CALI_BACKWARD_MEASURE;\n            }\n            break;\n        case CALI_BACKWARD_MEASURE:\n            if ((goPosition % motor->SOFT_DIVIDE_NUM) == 0)\n            {\n                sampleDataRaw[sampleCount++] = motor->encoder->angleData.rawAngle;\n                if (sampleCount == EncoderCalibratorBase::SAMPLE_COUNTS_PER_STEP)\n                {\n                    sampleDataAverageBackward[(goPosition - motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS) /\n                                              motor->SOFT_DIVIDE_NUM]\n                        = CycleDataAverage(sampleDataRaw, EncoderCalibratorBase::SAMPLE_COUNTS_PER_STEP,\n                                           motor->encoder->RESOLUTION);\n\n                    sampleCount = 0;\n                    goPosition -= FINE_TUNE_CALIB_SPEED;\n                }\n            } else\n            {\n                goPosition -= FINE_TUNE_CALIB_SPEED;\n            }\n            motor->driver->SetFocCurrentVector(goPosition, motor->config.motionParams.caliCurrent);\n            if (goPosition < motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS)\n            {\n                state = CALI_CALCULATING;\n            }\n            break;\n        case CALI_CALCULATING:\n            motor->driver->SetFocCurrentVector(0, 0);\n            break;\n        default:\n            break;\n    }\n}\n\n\nvoid EncoderCalibratorBase::TickMainLoop()\n{\n    int32_t dataI32;\n    uint16_t dataU16;\n\n    if (state != CALI_CALCULATING)\n        return;\n\n    motor->driver->Sleep();\n\n    CalibrationDataCheck();\n\n    if (errorCode == CALI_NO_ERROR)\n    {\n        int32_t stepX, stepY;\n        resultNum = 0;\n\n        ClearFlash();\n        BeginWriteFlash();\n\n        if (goDirection)\n        {\n            for (stepX = rcdX; stepX < rcdX + motor->MOTOR_ONE_CIRCLE_HARD_STEPS + 1; stepX++)\n            {\n                dataI32 = CycleSubtract(\n                    sampleDataAverageForward[CycleMod(stepX + 1, motor->MOTOR_ONE_CIRCLE_HARD_STEPS)],\n                    sampleDataAverageForward[CycleMod(stepX, motor->MOTOR_ONE_CIRCLE_HARD_STEPS)],\n                    motor->encoder->RESOLUTION);\n                if (stepX == rcdX)\n                {\n                    for (stepY = rcdY; stepY < dataI32; stepY++)\n                    {\n                        dataU16 = CycleMod(motor->SOFT_DIVIDE_NUM * stepX +\n                                           motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                                           motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                } else if (stepX == rcdX + motor->MOTOR_ONE_CIRCLE_HARD_STEPS)\n                {\n                    for (stepY = 0; stepY < rcdY; stepY++)\n                    {\n                        dataU16 = CycleMod(motor->SOFT_DIVIDE_NUM * stepX +\n                                           motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                                           motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                } else\n                {\n                    for (stepY = 0; stepY < dataI32; stepY++)\n                    {\n                        dataU16 = CycleMod(motor->SOFT_DIVIDE_NUM * stepX +\n                                           motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                                           motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                }\n            }\n        } else\n        {\n            for (stepX = rcdX + motor->MOTOR_ONE_CIRCLE_HARD_STEPS; stepX > rcdX - 1; stepX--)\n            {\n                dataI32 = CycleSubtract(\n                    sampleDataAverageForward[CycleMod(stepX, motor->MOTOR_ONE_CIRCLE_HARD_STEPS)],\n                    sampleDataAverageForward[CycleMod(stepX + 1, motor->MOTOR_ONE_CIRCLE_HARD_STEPS)],\n                    motor->encoder->RESOLUTION);\n                if (stepX == rcdX + motor->MOTOR_ONE_CIRCLE_HARD_STEPS)\n                {\n                    for (stepY = rcdY; stepY < dataI32; stepY++)\n                    {\n                        dataU16 = CycleMod(\n                            motor->SOFT_DIVIDE_NUM * (stepX + 1) -\n                            motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                            motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                } else if (stepX == rcdX)\n                {\n                    for (stepY = 0; stepY < rcdY; stepY++)\n                    {\n                        dataU16 = CycleMod(\n                            motor->SOFT_DIVIDE_NUM * (stepX + 1) -\n                            motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                            motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                } else\n                {\n                    for (stepY = 0; stepY < dataI32; stepY++)\n                    {\n                        dataU16 = CycleMod(\n                            motor->SOFT_DIVIDE_NUM * (stepX + 1) -\n                            motor->SOFT_DIVIDE_NUM * stepY / dataI32,\n                            motor->MOTOR_ONE_CIRCLE_SUBDIVIDE_STEPS);\n                        WriteFlash16bitsAppend(dataU16);\n                        resultNum++;\n                    }\n                }\n            }\n        }\n\n        EndWriteFlash();\n\n        if (resultNum != motor->encoder->RESOLUTION)\n            errorCode = CALI_ERROR_ANALYSIS_QUANTITY;\n    }\n\n    if (errorCode == CALI_NO_ERROR)\n    {\n        motor->encoder->angleData.rectifyValid = true;\n    } else\n    {\n        motor->encoder->angleData.rectifyValid = false;\n        ClearFlash();\n    }\n\n    motor->controller->isStalled = true;\n\n    state = CALI_DISABLE;\n    isTriggered = false;\n\n    if (errorCode == CALI_NO_ERROR)\n        HAL_NVIC_SystemReset();\n}\n\n\nuint32_t EncoderCalibratorBase::CycleMod(uint32_t _a, uint32_t _b)\n{\n    return (_a + _b) % _b;\n}\n\n\nint32_t EncoderCalibratorBase::CycleSubtract(int32_t _a, int32_t _b, int32_t _cyc)\n{\n    int32_t sub_data;\n\n    sub_data = _a - _b;\n    if (sub_data > (_cyc >> 1)) sub_data -= _cyc;\n    if (sub_data < (-_cyc >> 1)) sub_data += _cyc;\n    return sub_data;\n}\n\n\nint32_t EncoderCalibratorBase::CycleAverage(int32_t _a, int32_t _b, int32_t _cyc)\n{\n    int32_t sub_data;\n    int32_t ave_data;\n\n    sub_data = _a - _b;\n    ave_data = (_a + _b) >> 1;\n\n    if (abs(sub_data) > (_cyc >> 1))\n    {\n        if (ave_data >= (_cyc >> 1)) ave_data -= (_cyc >> 1);\n        else ave_data += (_cyc >> 1);\n    }\n    return ave_data;\n}"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Sensor/Encoder/encoder_calibrator_base.h",
    "content": "#ifndef CTRL_STEP_FW_ENCODER_CALIBRATOR_BASE_H\n#define CTRL_STEP_FW_ENCODER_CALIBRATOR_BASE_H\n\n#include \"Motor/motor.h\"\n\nclass EncoderCalibratorBase\n{\npublic:\n    static const int32_t MOTOR_ONE_CIRCLE_HARD_STEPS = 200;   // for 1.8° step-motors\n    static const uint8_t SAMPLE_COUNTS_PER_STEP = 16;\n    static const uint8_t AUTO_CALIB_SPEED = 2;\n    static const uint8_t FINE_TUNE_CALIB_SPEED = 1;\n\n\n    typedef enum\n    {\n        CALI_NO_ERROR = 0x00,\n        CALI_ERROR_AVERAGE_DIR,\n        CALI_ERROR_AVERAGE_CONTINUTY,\n        CALI_ERROR_PHASE_STEP,\n        CALI_ERROR_ANALYSIS_QUANTITY,\n    } Error_t;\n\n    typedef enum\n    {\n        CALI_DISABLE = 0x00,\n        CALI_FORWARD_PREPARE,\n        CALI_FORWARD_MEASURE,\n        CALI_BACKWARD_RETURN,\n        CALI_BACKWARD_GAP_DISMISS,\n        CALI_BACKWARD_MEASURE,\n        CALI_CALCULATING,\n    } State_t;\n\n\n    explicit EncoderCalibratorBase(Motor* _motor)\n    {\n        motor = _motor;\n\n        isTriggered = false;\n        errorCode = CALI_NO_ERROR;\n        state = CALI_DISABLE;\n        goPosition = 0;\n        rcdX = 0;\n        rcdY = 0;\n        resultNum = 0;\n    }\n\n\n    bool isTriggered;\n\n\n    void Tick20kHz();\n    void TickMainLoop();\n\n\nprivate:\n    Motor* motor;\n\n    Error_t errorCode;\n    State_t state;\n    uint32_t goPosition;\n    bool goDirection;\n    uint16_t sampleCount = 0;\n    uint16_t sampleDataRaw[SAMPLE_COUNTS_PER_STEP]{};\n    uint16_t sampleDataAverageForward[MOTOR_ONE_CIRCLE_HARD_STEPS + 1]{};\n    uint16_t sampleDataAverageBackward[MOTOR_ONE_CIRCLE_HARD_STEPS + 1]{};\n    int32_t rcdX, rcdY;\n    uint32_t resultNum;\n\n\n    void CalibrationDataCheck();\n    static uint32_t CycleMod(uint32_t _a, uint32_t _b);\n    static int32_t CycleSubtract(int32_t _a, int32_t _b, int32_t _cyc);\n    static int32_t CycleAverage(int32_t _a, int32_t _b, int32_t _cyc);\n    static int32_t CycleDataAverage(const uint16_t* _data, uint16_t _length, int32_t _cyc);\n\n\n    /***** Port Specified Implements *****/\n    virtual void BeginWriteFlash() = 0;\n    virtual void EndWriteFlash() = 0;\n    virtual void ClearFlash() = 0;\n    virtual void WriteFlash16bitsAppend(uint16_t _data) = 0;\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Sensor/Encoder/mt6816_base.cpp",
    "content": "#include \"mt6816_base.h\"\n\nbool MT6816Base::Init()\n{\n    SpiInit();\n    UpdateAngle();\n\n    // Check if the stored calibration data are valid\n    angleData.rectifyValid = true;\n    for (uint32_t i = 0; i < RESOLUTION; i++)\n    {\n        if (quickCaliDataPtr[i] == 0xFFFF)\n            angleData.rectifyValid = false;\n    }\n\n    return angleData.rectifyValid;\n}\n\n\nuint16_t MT6816Base::UpdateAngle()\n{\n    dataTx[0] = (0x80 | 0x03) << 8;\n    dataTx[1] = (0x80 | 0x04) << 8;\n\n    for (uint8_t i = 0; i < 3; i++)\n    {\n        dataRx[0] = SpiTransmitAndRead16Bits(dataTx[0]);\n        dataRx[1] = SpiTransmitAndRead16Bits(dataTx[1]);\n\n        spiRawData.rawData = ((dataRx[0] & 0x00FF) << 8) | (dataRx[1] & 0x00FF);\n\n        //奇偶校验\n        hCount = 0;\n        for (uint8_t j = 0; j < 16; j++)\n        {\n            if (spiRawData.rawData & (0x0001 << j))\n                hCount++;\n        }\n        if (hCount & 0x01)\n        {\n            spiRawData.checksumFlag = false;\n        } else\n        {\n            spiRawData.checksumFlag = true;\n            break;\n        }\n    }\n\n    if (spiRawData.checksumFlag)\n    {\n        spiRawData.rawAngle = spiRawData.rawData >> 2;\n        spiRawData.noMagFlag = (bool) (spiRawData.rawData & (0x0001 << 1));\n    }\n\n    angleData.rawAngle = spiRawData.rawAngle;\n    angleData.rectifiedAngle = quickCaliDataPtr[angleData.rawAngle];\n\n    return angleData.rectifiedAngle;\n}\n\n\nbool MT6816Base::IsCalibrated()\n{\n    return angleData.rectifyValid;\n}\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Sensor/Encoder/mt6816_base.h",
    "content": "#ifndef CTRL_STEP_FW_MT6816_H\n#define CTRL_STEP_FW_MT6816_H\n\n#include \"encoder_base.h\"\n#include <cstdint>\n\nclass MT6816Base : public EncoderBase\n{\npublic:\n    explicit MT6816Base(uint16_t* _quickCaliDataPtr) :\n        quickCaliDataPtr(_quickCaliDataPtr),\n        spiRawData(SpiRawData_t{0})\n    {\n    }\n\n\n    bool Init() override;\n    uint16_t UpdateAngle() override;  // Get current rawAngle (rad)\n    bool IsCalibrated() override;\n\n\nprivate:\n    typedef struct\n    {\n        uint16_t rawData;       // SPI raw 16bits data\n        uint16_t rawAngle;      // 14bits rawAngle in rawData\n        bool noMagFlag;\n        bool checksumFlag;\n    } SpiRawData_t;\n\n\n    SpiRawData_t spiRawData;\n    uint16_t* quickCaliDataPtr;\n    uint16_t dataTx[2];\n    uint16_t dataRx[2];\n    uint8_t hCount;\n\n\n    /***** Port Specified Implements *****/\n    virtual void SpiInit();\n\n    virtual uint16_t SpiTransmitAndRead16Bits(uint16_t _dataTx);\n\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Signal/button_base.h",
    "content": "#ifndef CTRL_STEP_FW_BUTTON_BASE_H\n#define CTRL_STEP_FW_BUTTON_BASE_H\n\n#include <cstdint>\n\nclass ButtonBase\n{\npublic:\n    enum Event\n    {\n        UP,\n        DOWN,\n        LONG_PRESS,\n        CLICK\n    };\n\n    explicit ButtonBase(uint8_t _id) :\n        id(_id)\n    {}\n\n    ButtonBase(uint8_t _id, uint32_t _longPressTime) :\n        id(_id), longPressTime(_longPressTime)\n    {}\n\n    void Tick(uint32_t _timeElapseMillis);\n    void SetOnEventListener(void (* _callback)(Event));\n\nprotected:\n    uint8_t id;\n    bool lastPinIO{};\n    uint32_t timer=0;\n    uint32_t pressTime{};\n    uint32_t longPressTime = 2000;\n\n    void (* OnEventFunc)(Event){};\n\n    virtual bool ReadButtonPinIO(uint8_t _id) = 0;\n};\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Signal/led_base.cpp",
    "content": "#include \"led_base.h\"\n\nvoid LedBase::Tick(uint32_t _timeElapseMillis, Motor::State_t _state)\n{\n    timer += _timeElapseMillis;\n\n    switch (_state)\n    {\n        case Motor::STATE_NO_CALIB:\n            motorEnable = false;\n            heartBeatEnable = false;\n            targetBlinkNum = 1;\n            break;\n        case Motor::STATE_RUNNING:\n            motorEnable = true;\n            heartBeatEnable = true;\n            targetBlinkNum = 0;\n            break;\n        case Motor::STATE_FINISH:\n            motorEnable = true;\n            heartBeatEnable = false;\n            targetBlinkNum = 0;\n            break;\n        case Motor::STATE_STOP:\n            motorEnable = false;\n            heartBeatEnable = false;\n            targetBlinkNum = 0;\n            break;\n        case Motor::STATE_OVERLOAD:\n            motorEnable = true;\n            heartBeatEnable = false;\n            targetBlinkNum = 3;\n            break;\n        case Motor::STATE_STALL:\n            motorEnable = false;\n            heartBeatEnable = false;\n            targetBlinkNum = 2;\n            break;\n    }\n\n    if (motorEnable)\n        if (heartBeatEnable)\n        {\n            switch (heartBeatPhase)\n            {\n                case 1:\n                    if (timer - timerHeartBeat > 100)\n                    {\n                        SetLedState(0, false);\n                        timerHeartBeat = timer;\n                        heartBeatPhase = 2;\n                    }\n                    break;\n                case 2:\n                    if (timer - timerHeartBeat > 100)\n                    {\n                        SetLedState(0, true);\n                        timerHeartBeat = timer;\n                        heartBeatPhase = 3;\n                    }\n                    break;\n                case 3:\n                    if (timer - timerHeartBeat > 100)\n                    {\n                        SetLedState(0, false);\n                        timerHeartBeat = timer;\n                        heartBeatPhase = 4;\n                    }\n                    break;\n                case 4:\n                    if (timer - timerHeartBeat > 700)\n                    {\n                        SetLedState(0, true);\n                        timerHeartBeat = timer;\n                        heartBeatPhase = 1;\n                    }\n                    break;\n            }\n        } else\n        {\n            SetLedState(0, true);\n            heartBeatPhase = 1;\n        }\n    else\n        SetLedState(0, false);\n\n\n    switch (blinkPhase)\n    {\n        case 1:\n            if (timer - timerBlink > 100)\n            {\n                SetLedState(1, false);\n                timerBlink = timer;\n                blinkPhase = 2;\n            }\n            break;\n        case 2:\n            if (timer - timerBlink > 100)\n            {\n                blinkNum++;\n                if (targetBlinkNum > blinkNum)\n                {\n                    SetLedState(1, true);\n                    blinkPhase = 1;\n                    timerBlink = timer;\n                } else\n                {\n                    SetLedState(1, false);\n                    blinkPhase = 3;\n                    timerBlink = timer;\n                }\n            }\n            break;\n        case 3:\n            if (timer - timerBlink > 1000)\n            {\n                blinkNum = 0;\n                SetLedState(1, targetBlinkNum > 0);\n                timerBlink = timer;\n                blinkPhase = 1;\n            }\n            break;\n    }\n\n}\n\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl/Signal/led_base.h",
    "content": "#ifndef CTRL_STEP_FW_LED_BASE_H\n#define CTRL_STEP_FW_LED_BASE_H\n\n#include <cstdint>\n#include \"Motor/motor.h\"\n\nclass LedBase\n{\npublic:\n    LedBase()\n    = default;\n\n    void Tick(uint32_t _timeElapseMillis, Motor::State_t _state);\n\nprivate:\n    uint32_t timer = 0;\n    uint32_t timerHeartBeat = 0;\n    bool motorEnable = false;\n    bool heartBeatEnable = false;\n    uint8_t heartBeatPhase = 1;\n    uint8_t blinkNum = 0;\n    uint8_t targetBlinkNum = 0;\n    uint32_t timerBlink = 0;\n    uint8_t blinkPhase = 1;\n\n    virtual void SetLedState(uint8_t _id, bool _state) = 0;\n};\n\n\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Ctrl-Step-fw.xml",
    "content": "<?xml version=\"1.0\" encoding=\"UTF-8\"?>\n<targetDefinitions xmlns=\"http://openstm32.org/stm32TargetDefinitions\" xmlns:xsi=\"http://www.w3.org/2001/XMLSchema-instance\" xsi:schemaLocation=\"http://openstm32.org/stm32TargetDefinitions stm32TargetDefinitions.xsd\">\n  <board id=\"Ctrl-Step-fw\">\n    <name>Ctrl-Step-fw</name>\n    <mcuId>STM32F103CBTx</mcuId>  <!-- mcu-->\n    <dbgIF>SWD</dbgIF>\n    <dbgDEV>ST-LinkV2-1</dbgDEV>\n  </board>\n</targetDefinitions>\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f103xb.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. \n  *          This file contains all the peripheral register's definitions, bits \n  *          definitions and memory mapping for STM32F1xx devices.            \n  *            \n  *          This file contains:\n  *           - Data structures and the address mapping for all peripherals\n  *           - Peripheral's registers declarations and bits definition\n  *           - Macros to access peripherals registers hardware\n  *  \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f103xb\n  * @{\n  */\n    \n#ifndef __STM32F103xB_H\n#define __STM32F103xB_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup Configuration_section_for_CMSIS\n  * @{\n  */\n/**\n  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals \n */\n#define __CM3_REV                  0x0200U  /*!< Core Revision r2p0                           */\n #define __MPU_PRESENT             0U       /*!< Other STM32 devices does not provide an MPU  */\n#define __NVIC_PRIO_BITS           4U       /*!< STM32 uses 4 Bits for the Priority Levels    */\n#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */\n\n/**\n  * @}\n  */\n\n/** @addtogroup Peripheral_interrupt_number_definition\n  * @{\n  */\n\n/**\n * @brief STM32F10x Interrupt Number Definition, according to the selected device \n *        in @ref Library_configuration_section \n */\n\n /*!< Interrupt Number Definition */\ntypedef enum\n{\n/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/\n  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */\n  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                     */\n  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */\n  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */\n  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */\n  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */\n  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */\n  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */\n  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   */\n\n/******  STM32 specific Interrupt Numbers *********************************************************/\n  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */\n  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */\n  TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */\n  RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */\n  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */\n  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */\n  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */\n  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */\n  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */\n  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */\n  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */\n  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */\n  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */\n  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */\n  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */\n  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */\n  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */\n  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */\n  ADC1_2_IRQn                 = 18,     /*!< ADC1 and ADC2 global Interrupt                       */\n  USB_HP_CAN1_TX_IRQn         = 19,     /*!< USB Device High Priority or CAN1 TX Interrupts       */\n  USB_LP_CAN1_RX0_IRQn        = 20,     /*!< USB Device Low Priority or CAN1 RX0 Interrupts       */\n  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                   */\n  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                   */\n  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                        */\n  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                 */\n  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                */\n  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt               */\n  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                       */\n  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                */\n  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                */\n  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                */\n  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                 */\n  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                 */\n  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                 */\n  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                 */\n  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                */\n  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                */\n  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                              */\n  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                              */\n  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                              */\n  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                      */\n  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                */\n  USBWakeUp_IRQn              = 42,     /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */\n} IRQn_Type;\n\n/**\n  * @}\n  */\n\n#include \"core_cm3.h\"\n#include \"system_stm32f1xx.h\"\n#include <stdint.h>\n\n/** @addtogroup Peripheral_registers_structures\n  * @{\n  */   \n\n/** \n  * @brief Analog to Digital Converter  \n  */\n\ntypedef struct\n{\n  __IO uint32_t SR;\n  __IO uint32_t CR1;\n  __IO uint32_t CR2;\n  __IO uint32_t SMPR1;\n  __IO uint32_t SMPR2;\n  __IO uint32_t JOFR1;\n  __IO uint32_t JOFR2;\n  __IO uint32_t JOFR3;\n  __IO uint32_t JOFR4;\n  __IO uint32_t HTR;\n  __IO uint32_t LTR;\n  __IO uint32_t SQR1;\n  __IO uint32_t SQR2;\n  __IO uint32_t SQR3;\n  __IO uint32_t JSQR;\n  __IO uint32_t JDR1;\n  __IO uint32_t JDR2;\n  __IO uint32_t JDR3;\n  __IO uint32_t JDR4;\n  __IO uint32_t DR;\n} ADC_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t SR;               /*!< ADC status register,    used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address         */\n  __IO uint32_t CR1;              /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04  */\n  __IO uint32_t CR2;              /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08  */\n  uint32_t  RESERVED[16];\n  __IO uint32_t DR;               /*!< ADC data register,      used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C  */\n} ADC_Common_TypeDef;\n\n/** \n  * @brief Backup Registers  \n  */\n\ntypedef struct\n{\n  uint32_t  RESERVED0;\n  __IO uint32_t DR1;\n  __IO uint32_t DR2;\n  __IO uint32_t DR3;\n  __IO uint32_t DR4;\n  __IO uint32_t DR5;\n  __IO uint32_t DR6;\n  __IO uint32_t DR7;\n  __IO uint32_t DR8;\n  __IO uint32_t DR9;\n  __IO uint32_t DR10;\n  __IO uint32_t RTCCR;\n  __IO uint32_t CR;\n  __IO uint32_t CSR;\n} BKP_TypeDef;\n  \n/** \n  * @brief Controller Area Network TxMailBox \n  */\n\ntypedef struct\n{\n  __IO uint32_t TIR;\n  __IO uint32_t TDTR;\n  __IO uint32_t TDLR;\n  __IO uint32_t TDHR;\n} CAN_TxMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FIFOMailBox \n  */\n  \ntypedef struct\n{\n  __IO uint32_t RIR;\n  __IO uint32_t RDTR;\n  __IO uint32_t RDLR;\n  __IO uint32_t RDHR;\n} CAN_FIFOMailBox_TypeDef;\n\n/** \n  * @brief Controller Area Network FilterRegister \n  */\n  \ntypedef struct\n{\n  __IO uint32_t FR1;\n  __IO uint32_t FR2;\n} CAN_FilterRegister_TypeDef;\n\n/** \n  * @brief Controller Area Network \n  */\n  \ntypedef struct\n{\n  __IO uint32_t MCR;\n  __IO uint32_t MSR;\n  __IO uint32_t TSR;\n  __IO uint32_t RF0R;\n  __IO uint32_t RF1R;\n  __IO uint32_t IER;\n  __IO uint32_t ESR;\n  __IO uint32_t BTR;\n  uint32_t  RESERVED0[88];\n  CAN_TxMailBox_TypeDef sTxMailBox[3];\n  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];\n  uint32_t  RESERVED1[12];\n  __IO uint32_t FMR;\n  __IO uint32_t FM1R;\n  uint32_t  RESERVED2;\n  __IO uint32_t FS1R;\n  uint32_t  RESERVED3;\n  __IO uint32_t FFA1R;\n  uint32_t  RESERVED4;\n  __IO uint32_t FA1R;\n  uint32_t  RESERVED5[8];\n  CAN_FilterRegister_TypeDef sFilterRegister[14];\n} CAN_TypeDef;\n\n/** \n  * @brief CRC calculation unit \n  */\n\ntypedef struct\n{\n  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */\n  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */\n  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */\n  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */  \n  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ \n} CRC_TypeDef;\n\n\n/** \n  * @brief Debug MCU\n  */\n\ntypedef struct\n{\n  __IO uint32_t IDCODE;\n  __IO uint32_t CR;\n}DBGMCU_TypeDef;\n\n/** \n  * @brief DMA Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t CCR;\n  __IO uint32_t CNDTR;\n  __IO uint32_t CPAR;\n  __IO uint32_t CMAR;\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n  __IO uint32_t ISR;\n  __IO uint32_t IFCR;\n} DMA_TypeDef;\n\n\n\n/** \n  * @brief External Interrupt/Event Controller\n  */\n\ntypedef struct\n{\n  __IO uint32_t IMR;\n  __IO uint32_t EMR;\n  __IO uint32_t RTSR;\n  __IO uint32_t FTSR;\n  __IO uint32_t SWIER;\n  __IO uint32_t PR;\n} EXTI_TypeDef;\n\n/** \n  * @brief FLASH Registers\n  */\n\ntypedef struct\n{\n  __IO uint32_t ACR;\n  __IO uint32_t KEYR;\n  __IO uint32_t OPTKEYR;\n  __IO uint32_t SR;\n  __IO uint32_t CR;\n  __IO uint32_t AR;\n  __IO uint32_t RESERVED;\n  __IO uint32_t OBR;\n  __IO uint32_t WRPR;\n} FLASH_TypeDef;\n\n/** \n  * @brief Option Bytes Registers\n  */\n  \ntypedef struct\n{\n  __IO uint16_t RDP;\n  __IO uint16_t USER;\n  __IO uint16_t Data0;\n  __IO uint16_t Data1;\n  __IO uint16_t WRP0;\n  __IO uint16_t WRP1;\n  __IO uint16_t WRP2;\n  __IO uint16_t WRP3;\n} OB_TypeDef;\n\n/** \n  * @brief General Purpose I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t CRL;\n  __IO uint32_t CRH;\n  __IO uint32_t IDR;\n  __IO uint32_t ODR;\n  __IO uint32_t BSRR;\n  __IO uint32_t BRR;\n  __IO uint32_t LCKR;\n} GPIO_TypeDef;\n\n/** \n  * @brief Alternate Function I/O\n  */\n\ntypedef struct\n{\n  __IO uint32_t EVCR;\n  __IO uint32_t MAPR;\n  __IO uint32_t EXTICR[4];\n  uint32_t RESERVED0;\n  __IO uint32_t MAPR2;  \n} AFIO_TypeDef;\n/** \n  * @brief Inter Integrated Circuit Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;\n  __IO uint32_t CR2;\n  __IO uint32_t OAR1;\n  __IO uint32_t OAR2;\n  __IO uint32_t DR;\n  __IO uint32_t SR1;\n  __IO uint32_t SR2;\n  __IO uint32_t CCR;\n  __IO uint32_t TRISE;\n} I2C_TypeDef;\n\n/** \n  * @brief Independent WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */\n  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */\n  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */\n  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */\n} IWDG_TypeDef;\n\n/** \n  * @brief Power Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t CSR;\n} PWR_TypeDef;\n\n/** \n  * @brief Reset and Clock Control\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;\n  __IO uint32_t CFGR;\n  __IO uint32_t CIR;\n  __IO uint32_t APB2RSTR;\n  __IO uint32_t APB1RSTR;\n  __IO uint32_t AHBENR;\n  __IO uint32_t APB2ENR;\n  __IO uint32_t APB1ENR;\n  __IO uint32_t BDCR;\n  __IO uint32_t CSR;\n\n\n} RCC_TypeDef;\n\n/** \n  * @brief Real-Time Clock\n  */\n\ntypedef struct\n{\n  __IO uint32_t CRH;\n  __IO uint32_t CRL;\n  __IO uint32_t PRLH;\n  __IO uint32_t PRLL;\n  __IO uint32_t DIVH;\n  __IO uint32_t DIVL;\n  __IO uint32_t CNTH;\n  __IO uint32_t CNTL;\n  __IO uint32_t ALRH;\n  __IO uint32_t ALRL;\n} RTC_TypeDef;\n\n/** \n  * @brief Serial Peripheral Interface\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR1;\n  __IO uint32_t CR2;\n  __IO uint32_t SR;\n  __IO uint32_t DR;\n  __IO uint32_t CRCPR;\n  __IO uint32_t RXCRCR;\n  __IO uint32_t TXCRCR;\n  __IO uint32_t I2SCFGR;\n} SPI_TypeDef;\n\n/**\n  * @brief TIM Timers\n  */\ntypedef struct\n{\n  __IO uint32_t CR1;             /*!< TIM control register 1,                      Address offset: 0x00 */\n  __IO uint32_t CR2;             /*!< TIM control register 2,                      Address offset: 0x04 */\n  __IO uint32_t SMCR;            /*!< TIM slave Mode Control register,             Address offset: 0x08 */\n  __IO uint32_t DIER;            /*!< TIM DMA/interrupt enable register,           Address offset: 0x0C */\n  __IO uint32_t SR;              /*!< TIM status register,                         Address offset: 0x10 */\n  __IO uint32_t EGR;             /*!< TIM event generation register,               Address offset: 0x14 */\n  __IO uint32_t CCMR1;           /*!< TIM  capture/compare mode register 1,        Address offset: 0x18 */\n  __IO uint32_t CCMR2;           /*!< TIM  capture/compare mode register 2,        Address offset: 0x1C */\n  __IO uint32_t CCER;            /*!< TIM capture/compare enable register,         Address offset: 0x20 */\n  __IO uint32_t CNT;             /*!< TIM counter register,                        Address offset: 0x24 */\n  __IO uint32_t PSC;             /*!< TIM prescaler register,                      Address offset: 0x28 */\n  __IO uint32_t ARR;             /*!< TIM auto-reload register,                    Address offset: 0x2C */\n  __IO uint32_t RCR;             /*!< TIM  repetition counter register,            Address offset: 0x30 */\n  __IO uint32_t CCR1;            /*!< TIM capture/compare register 1,              Address offset: 0x34 */\n  __IO uint32_t CCR2;            /*!< TIM capture/compare register 2,              Address offset: 0x38 */\n  __IO uint32_t CCR3;            /*!< TIM capture/compare register 3,              Address offset: 0x3C */\n  __IO uint32_t CCR4;            /*!< TIM capture/compare register 4,              Address offset: 0x40 */\n  __IO uint32_t BDTR;            /*!< TIM break and dead-time register,            Address offset: 0x44 */\n  __IO uint32_t DCR;             /*!< TIM DMA control register,                    Address offset: 0x48 */\n  __IO uint32_t DMAR;            /*!< TIM DMA address for full transfer register,  Address offset: 0x4C */\n  __IO uint32_t OR;              /*!< TIM option register,                         Address offset: 0x50 */\n}TIM_TypeDef;\n\n\n/** \n  * @brief Universal Synchronous Asynchronous Receiver Transmitter\n  */\n \ntypedef struct\n{\n  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\n  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\n  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\n  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\n  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\n  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\n  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\n} USART_TypeDef;\n\n/** \n  * @brief Universal Serial Bus Full Speed Device\n  */\n  \ntypedef struct\n{\n  __IO uint16_t EP0R;                 /*!< USB Endpoint 0 register,                   Address offset: 0x00 */ \n  __IO uint16_t RESERVED0;            /*!< Reserved */     \n  __IO uint16_t EP1R;                 /*!< USB Endpoint 1 register,                   Address offset: 0x04 */\n  __IO uint16_t RESERVED1;            /*!< Reserved */       \n  __IO uint16_t EP2R;                 /*!< USB Endpoint 2 register,                   Address offset: 0x08 */\n  __IO uint16_t RESERVED2;            /*!< Reserved */       \n  __IO uint16_t EP3R;                 /*!< USB Endpoint 3 register,                   Address offset: 0x0C */ \n  __IO uint16_t RESERVED3;            /*!< Reserved */       \n  __IO uint16_t EP4R;                 /*!< USB Endpoint 4 register,                   Address offset: 0x10 */\n  __IO uint16_t RESERVED4;            /*!< Reserved */       \n  __IO uint16_t EP5R;                 /*!< USB Endpoint 5 register,                   Address offset: 0x14 */\n  __IO uint16_t RESERVED5;            /*!< Reserved */       \n  __IO uint16_t EP6R;                 /*!< USB Endpoint 6 register,                   Address offset: 0x18 */\n  __IO uint16_t RESERVED6;            /*!< Reserved */       \n  __IO uint16_t EP7R;                 /*!< USB Endpoint 7 register,                   Address offset: 0x1C */\n  __IO uint16_t RESERVED7[17];        /*!< Reserved */     \n  __IO uint16_t CNTR;                 /*!< Control register,                          Address offset: 0x40 */\n  __IO uint16_t RESERVED8;            /*!< Reserved */       \n  __IO uint16_t ISTR;                 /*!< Interrupt status register,                 Address offset: 0x44 */\n  __IO uint16_t RESERVED9;            /*!< Reserved */       \n  __IO uint16_t FNR;                  /*!< Frame number register,                     Address offset: 0x48 */\n  __IO uint16_t RESERVEDA;            /*!< Reserved */       \n  __IO uint16_t DADDR;                /*!< Device address register,                   Address offset: 0x4C */\n  __IO uint16_t RESERVEDB;            /*!< Reserved */       \n  __IO uint16_t BTABLE;               /*!< Buffer Table address register,             Address offset: 0x50 */\n  __IO uint16_t RESERVEDC;            /*!< Reserved */       \n} USB_TypeDef;\n\n\n/** \n  * @brief Window WATCHDOG\n  */\n\ntypedef struct\n{\n  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\n  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\n  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_memory_map\n  * @{\n  */\n\n\n#define FLASH_BASE            0x08000000UL /*!< FLASH base address in the alias region */\n#define FLASH_BANK1_END       0x0801FFFFUL /*!< FLASH END address of bank1 */\n#define SRAM_BASE             0x20000000UL /*!< SRAM base address in the alias region */\n#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region */\n\n#define SRAM_BB_BASE          0x22000000UL /*!< SRAM base address in the bit-band region */\n#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region */\n\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE       PERIPH_BASE\n#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)\n#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)\n\n#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000UL)\n#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400UL)\n#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800UL)\n#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800UL)\n#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00UL)\n#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000UL)\n#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800UL)\n#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400UL)\n#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800UL)\n#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400UL)\n#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800UL)\n#define CAN1_BASE             (APB1PERIPH_BASE + 0x00006400UL)\n#define BKP_BASE              (APB1PERIPH_BASE + 0x00006C00UL)\n#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000UL)\n#define AFIO_BASE             (APB2PERIPH_BASE + 0x00000000UL)\n#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400UL)\n#define GPIOA_BASE            (APB2PERIPH_BASE + 0x00000800UL)\n#define GPIOB_BASE            (APB2PERIPH_BASE + 0x00000C00UL)\n#define GPIOC_BASE            (APB2PERIPH_BASE + 0x00001000UL)\n#define GPIOD_BASE            (APB2PERIPH_BASE + 0x00001400UL)\n#define GPIOE_BASE            (APB2PERIPH_BASE + 0x00001800UL)\n#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400UL)\n#define ADC2_BASE             (APB2PERIPH_BASE + 0x00002800UL)\n#define TIM1_BASE             (APB2PERIPH_BASE + 0x00002C00UL)\n#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000UL)\n#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800UL)\n\n\n#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000UL)\n#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x00000008UL)\n#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x0000001CUL)\n#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x00000030UL)\n#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x00000044UL)\n#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x00000058UL)\n#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x0000006CUL)\n#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x00000080UL)\n#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000UL)\n#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000UL)\n\n#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */\n#define FLASHSIZE_BASE        0x1FFFF7E0UL    /*!< FLASH Size register base address */\n#define UID_BASE              0x1FFFF7E8UL    /*!< Unique device ID register base address */\n#define OB_BASE               0x1FFFF800UL    /*!< Flash Option Bytes base address */\n\n\n\n#define DBGMCU_BASE          0xE0042000UL /*!< Debug MCU registers base address */\n\n/* USB device FS */\n#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */\n\n\n/**\n  * @}\n  */\n  \n/** @addtogroup Peripheral_declaration\n  * @{\n  */  \n\n#define TIM2                ((TIM_TypeDef *)TIM2_BASE)\n#define TIM3                ((TIM_TypeDef *)TIM3_BASE)\n#define TIM4                ((TIM_TypeDef *)TIM4_BASE)\n#define RTC                 ((RTC_TypeDef *)RTC_BASE)\n#define WWDG                ((WWDG_TypeDef *)WWDG_BASE)\n#define IWDG                ((IWDG_TypeDef *)IWDG_BASE)\n#define SPI2                ((SPI_TypeDef *)SPI2_BASE)\n#define USART2              ((USART_TypeDef *)USART2_BASE)\n#define USART3              ((USART_TypeDef *)USART3_BASE)\n#define I2C1                ((I2C_TypeDef *)I2C1_BASE)\n#define I2C2                ((I2C_TypeDef *)I2C2_BASE)\n#define USB                 ((USB_TypeDef *)USB_BASE)\n#define CAN1                ((CAN_TypeDef *)CAN1_BASE)\n#define BKP                 ((BKP_TypeDef *)BKP_BASE)\n#define PWR                 ((PWR_TypeDef *)PWR_BASE)\n#define AFIO                ((AFIO_TypeDef *)AFIO_BASE)\n#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)\n#define GPIOA               ((GPIO_TypeDef *)GPIOA_BASE)\n#define GPIOB               ((GPIO_TypeDef *)GPIOB_BASE)\n#define GPIOC               ((GPIO_TypeDef *)GPIOC_BASE)\n#define GPIOD               ((GPIO_TypeDef *)GPIOD_BASE)\n#define GPIOE               ((GPIO_TypeDef *)GPIOE_BASE)\n#define ADC1                ((ADC_TypeDef *)ADC1_BASE)\n#define ADC2                ((ADC_TypeDef *)ADC2_BASE)\n#define ADC12_COMMON        ((ADC_Common_TypeDef *)ADC1_BASE)\n#define TIM1                ((TIM_TypeDef *)TIM1_BASE)\n#define SPI1                ((SPI_TypeDef *)SPI1_BASE)\n#define USART1              ((USART_TypeDef *)USART1_BASE)\n#define DMA1                ((DMA_TypeDef *)DMA1_BASE)\n#define DMA1_Channel1       ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)\n#define DMA1_Channel2       ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)\n#define DMA1_Channel3       ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)\n#define DMA1_Channel4       ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)\n#define DMA1_Channel5       ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)\n#define DMA1_Channel6       ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)\n#define DMA1_Channel7       ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)\n#define RCC                 ((RCC_TypeDef *)RCC_BASE)\n#define CRC                 ((CRC_TypeDef *)CRC_BASE)\n#define FLASH               ((FLASH_TypeDef *)FLASH_R_BASE)\n#define OB                  ((OB_TypeDef *)OB_BASE)\n#define DBGMCU              ((DBGMCU_TypeDef *)DBGMCU_BASE)\n\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_constants\n  * @{\n  */\n\n  /** @addtogroup Hardware_Constant_Definition\n    * @{\n    */\n#define LSI_STARTUP_TIME                85U /*!< LSI Maximum startup time in us */\n  /**\n    * @}\n    */\n\n  /** @addtogroup Peripheral_Registers_Bits_Definition\n  * @{\n  */\n    \n/******************************************************************************/\n/*                         Peripheral Registers_Bits_Definition               */\n/******************************************************************************/\n\n/******************************************************************************/\n/*                                                                            */\n/*                       CRC calculation unit (CRC)                           */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for CRC_DR register  *********************/\n#define CRC_DR_DR_Pos                       (0U)                               \n#define CRC_DR_DR_Msk                       (0xFFFFFFFFUL << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */\n#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */\n\n/*******************  Bit definition for CRC_IDR register  ********************/\n#define CRC_IDR_IDR_Pos                     (0U)                               \n#define CRC_IDR_IDR_Msk                     (0xFFUL << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */\n#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */\n\n/********************  Bit definition for CRC_CR register  ********************/\n#define CRC_CR_RESET_Pos                    (0U)                               \n#define CRC_CR_RESET_Msk                    (0x1UL << CRC_CR_RESET_Pos)         /*!< 0x00000001 */\n#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Power Control                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for PWR_CR register  ********************/\n#define PWR_CR_LPDS_Pos                     (0U)                               \n#define PWR_CR_LPDS_Msk                     (0x1UL << PWR_CR_LPDS_Pos)          /*!< 0x00000001 */\n#define PWR_CR_LPDS                         PWR_CR_LPDS_Msk                    /*!< Low-Power Deepsleep */\n#define PWR_CR_PDDS_Pos                     (1U)                               \n#define PWR_CR_PDDS_Msk                     (0x1UL << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */\n#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */\n#define PWR_CR_CWUF_Pos                     (2U)                               \n#define PWR_CR_CWUF_Msk                     (0x1UL << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */\n#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */\n#define PWR_CR_CSBF_Pos                     (3U)                               \n#define PWR_CR_CSBF_Msk                     (0x1UL << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */\n#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */\n#define PWR_CR_PVDE_Pos                     (4U)                               \n#define PWR_CR_PVDE_Msk                     (0x1UL << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */\n#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */\n\n#define PWR_CR_PLS_Pos                      (5U)                               \n#define PWR_CR_PLS_Msk                      (0x7UL << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */\n#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */\n#define PWR_CR_PLS_0                        (0x1UL << PWR_CR_PLS_Pos)           /*!< 0x00000020 */\n#define PWR_CR_PLS_1                        (0x2UL << PWR_CR_PLS_Pos)           /*!< 0x00000040 */\n#define PWR_CR_PLS_2                        (0x4UL << PWR_CR_PLS_Pos)           /*!< 0x00000080 */\n\n/*!< PVD level configuration */\n#define PWR_CR_PLS_LEV0                      0x00000000U                           /*!< PVD level 2.2V */\n#define PWR_CR_PLS_LEV1                      0x00000020U                           /*!< PVD level 2.3V */\n#define PWR_CR_PLS_LEV2                      0x00000040U                           /*!< PVD level 2.4V */\n#define PWR_CR_PLS_LEV3                      0x00000060U                           /*!< PVD level 2.5V */\n#define PWR_CR_PLS_LEV4                      0x00000080U                           /*!< PVD level 2.6V */\n#define PWR_CR_PLS_LEV5                      0x000000A0U                           /*!< PVD level 2.7V */\n#define PWR_CR_PLS_LEV6                      0x000000C0U                           /*!< PVD level 2.8V */\n#define PWR_CR_PLS_LEV7                      0x000000E0U                           /*!< PVD level 2.9V */\n\n/* Legacy defines */\n#define PWR_CR_PLS_2V2                       PWR_CR_PLS_LEV0\n#define PWR_CR_PLS_2V3                       PWR_CR_PLS_LEV1\n#define PWR_CR_PLS_2V4                       PWR_CR_PLS_LEV2\n#define PWR_CR_PLS_2V5                       PWR_CR_PLS_LEV3\n#define PWR_CR_PLS_2V6                       PWR_CR_PLS_LEV4\n#define PWR_CR_PLS_2V7                       PWR_CR_PLS_LEV5\n#define PWR_CR_PLS_2V8                       PWR_CR_PLS_LEV6\n#define PWR_CR_PLS_2V9                       PWR_CR_PLS_LEV7\n\n#define PWR_CR_DBP_Pos                      (8U)                               \n#define PWR_CR_DBP_Msk                      (0x1UL << PWR_CR_DBP_Pos)           /*!< 0x00000100 */\n#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */\n\n\n/*******************  Bit definition for PWR_CSR register  ********************/\n#define PWR_CSR_WUF_Pos                     (0U)                               \n#define PWR_CSR_WUF_Msk                     (0x1UL << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */\n#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */\n#define PWR_CSR_SBF_Pos                     (1U)                               \n#define PWR_CSR_SBF_Msk                     (0x1UL << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */\n#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */\n#define PWR_CSR_PVDO_Pos                    (2U)                               \n#define PWR_CSR_PVDO_Msk                    (0x1UL << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */\n#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */\n#define PWR_CSR_EWUP_Pos                    (8U)                               \n#define PWR_CSR_EWUP_Msk                    (0x1UL << PWR_CSR_EWUP_Pos)         /*!< 0x00000100 */\n#define PWR_CSR_EWUP                        PWR_CSR_EWUP_Msk                   /*!< Enable WKUP pin */\n\n/******************************************************************************/\n/*                                                                            */\n/*                            Backup registers                                */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for BKP_DR1 register  ********************/\n#define BKP_DR1_D_Pos                       (0U)                               \n#define BKP_DR1_D_Msk                       (0xFFFFUL << BKP_DR1_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR1_D                           BKP_DR1_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR2 register  ********************/\n#define BKP_DR2_D_Pos                       (0U)                               \n#define BKP_DR2_D_Msk                       (0xFFFFUL << BKP_DR2_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR2_D                           BKP_DR2_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR3 register  ********************/\n#define BKP_DR3_D_Pos                       (0U)                               \n#define BKP_DR3_D_Msk                       (0xFFFFUL << BKP_DR3_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR3_D                           BKP_DR3_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR4 register  ********************/\n#define BKP_DR4_D_Pos                       (0U)                               \n#define BKP_DR4_D_Msk                       (0xFFFFUL << BKP_DR4_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR4_D                           BKP_DR4_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR5 register  ********************/\n#define BKP_DR5_D_Pos                       (0U)                               \n#define BKP_DR5_D_Msk                       (0xFFFFUL << BKP_DR5_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR5_D                           BKP_DR5_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR6 register  ********************/\n#define BKP_DR6_D_Pos                       (0U)                               \n#define BKP_DR6_D_Msk                       (0xFFFFUL << BKP_DR6_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR6_D                           BKP_DR6_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR7 register  ********************/\n#define BKP_DR7_D_Pos                       (0U)                               \n#define BKP_DR7_D_Msk                       (0xFFFFUL << BKP_DR7_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR7_D                           BKP_DR7_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR8 register  ********************/\n#define BKP_DR8_D_Pos                       (0U)                               \n#define BKP_DR8_D_Msk                       (0xFFFFUL << BKP_DR8_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR8_D                           BKP_DR8_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR9 register  ********************/\n#define BKP_DR9_D_Pos                       (0U)                               \n#define BKP_DR9_D_Msk                       (0xFFFFUL << BKP_DR9_D_Pos)         /*!< 0x0000FFFF */\n#define BKP_DR9_D                           BKP_DR9_D_Msk                      /*!< Backup data */\n\n/*******************  Bit definition for BKP_DR10 register  *******************/\n#define BKP_DR10_D_Pos                      (0U)                               \n#define BKP_DR10_D_Msk                      (0xFFFFUL << BKP_DR10_D_Pos)        /*!< 0x0000FFFF */\n#define BKP_DR10_D                          BKP_DR10_D_Msk                     /*!< Backup data */\n\n#define RTC_BKP_NUMBER 10\n\n/******************  Bit definition for BKP_RTCCR register  *******************/\n#define BKP_RTCCR_CAL_Pos                   (0U)                               \n#define BKP_RTCCR_CAL_Msk                   (0x7FUL << BKP_RTCCR_CAL_Pos)       /*!< 0x0000007F */\n#define BKP_RTCCR_CAL                       BKP_RTCCR_CAL_Msk                  /*!< Calibration value */\n#define BKP_RTCCR_CCO_Pos                   (7U)                               \n#define BKP_RTCCR_CCO_Msk                   (0x1UL << BKP_RTCCR_CCO_Pos)        /*!< 0x00000080 */\n#define BKP_RTCCR_CCO                       BKP_RTCCR_CCO_Msk                  /*!< Calibration Clock Output */\n#define BKP_RTCCR_ASOE_Pos                  (8U)                               \n#define BKP_RTCCR_ASOE_Msk                  (0x1UL << BKP_RTCCR_ASOE_Pos)       /*!< 0x00000100 */\n#define BKP_RTCCR_ASOE                      BKP_RTCCR_ASOE_Msk                 /*!< Alarm or Second Output Enable */\n#define BKP_RTCCR_ASOS_Pos                  (9U)                               \n#define BKP_RTCCR_ASOS_Msk                  (0x1UL << BKP_RTCCR_ASOS_Pos)       /*!< 0x00000200 */\n#define BKP_RTCCR_ASOS                      BKP_RTCCR_ASOS_Msk                 /*!< Alarm or Second Output Selection */\n\n/********************  Bit definition for BKP_CR register  ********************/\n#define BKP_CR_TPE_Pos                      (0U)                               \n#define BKP_CR_TPE_Msk                      (0x1UL << BKP_CR_TPE_Pos)           /*!< 0x00000001 */\n#define BKP_CR_TPE                          BKP_CR_TPE_Msk                     /*!< TAMPER pin enable */\n#define BKP_CR_TPAL_Pos                     (1U)                               \n#define BKP_CR_TPAL_Msk                     (0x1UL << BKP_CR_TPAL_Pos)          /*!< 0x00000002 */\n#define BKP_CR_TPAL                         BKP_CR_TPAL_Msk                    /*!< TAMPER pin active level */\n\n/*******************  Bit definition for BKP_CSR register  ********************/\n#define BKP_CSR_CTE_Pos                     (0U)                               \n#define BKP_CSR_CTE_Msk                     (0x1UL << BKP_CSR_CTE_Pos)          /*!< 0x00000001 */\n#define BKP_CSR_CTE                         BKP_CSR_CTE_Msk                    /*!< Clear Tamper event */\n#define BKP_CSR_CTI_Pos                     (1U)                               \n#define BKP_CSR_CTI_Msk                     (0x1UL << BKP_CSR_CTI_Pos)          /*!< 0x00000002 */\n#define BKP_CSR_CTI                         BKP_CSR_CTI_Msk                    /*!< Clear Tamper Interrupt */\n#define BKP_CSR_TPIE_Pos                    (2U)                               \n#define BKP_CSR_TPIE_Msk                    (0x1UL << BKP_CSR_TPIE_Pos)         /*!< 0x00000004 */\n#define BKP_CSR_TPIE                        BKP_CSR_TPIE_Msk                   /*!< TAMPER Pin interrupt enable */\n#define BKP_CSR_TEF_Pos                     (8U)                               \n#define BKP_CSR_TEF_Msk                     (0x1UL << BKP_CSR_TEF_Pos)          /*!< 0x00000100 */\n#define BKP_CSR_TEF                         BKP_CSR_TEF_Msk                    /*!< Tamper Event Flag */\n#define BKP_CSR_TIF_Pos                     (9U)                               \n#define BKP_CSR_TIF_Msk                     (0x1UL << BKP_CSR_TIF_Pos)          /*!< 0x00000200 */\n#define BKP_CSR_TIF                         BKP_CSR_TIF_Msk                    /*!< Tamper Interrupt Flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Reset and Clock Control                            */\n/*                                                                            */\n/******************************************************************************/\n\n/********************  Bit definition for RCC_CR register  ********************/\n#define RCC_CR_HSION_Pos                     (0U)                              \n#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)        /*!< 0x00000001 */\n#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed clock enable */\n#define RCC_CR_HSIRDY_Pos                    (1U)                              \n#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)       /*!< 0x00000002 */\n#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed clock ready flag */\n#define RCC_CR_HSITRIM_Pos                   (3U)                              \n#define RCC_CR_HSITRIM_Msk                   (0x1FUL << RCC_CR_HSITRIM_Pos)     /*!< 0x000000F8 */\n#define RCC_CR_HSITRIM                       RCC_CR_HSITRIM_Msk                /*!< Internal High Speed clock trimming */\n#define RCC_CR_HSICAL_Pos                    (8U)                              \n#define RCC_CR_HSICAL_Msk                    (0xFFUL << RCC_CR_HSICAL_Pos)      /*!< 0x0000FF00 */\n#define RCC_CR_HSICAL                        RCC_CR_HSICAL_Msk                 /*!< Internal High Speed clock Calibration */\n#define RCC_CR_HSEON_Pos                     (16U)                             \n#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)        /*!< 0x00010000 */\n#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed clock enable */\n#define RCC_CR_HSERDY_Pos                    (17U)                             \n#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)       /*!< 0x00020000 */\n#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed clock ready flag */\n#define RCC_CR_HSEBYP_Pos                    (18U)                             \n#define RCC_CR_HSEBYP_Msk                    (0x1UL << RCC_CR_HSEBYP_Pos)       /*!< 0x00040000 */\n#define RCC_CR_HSEBYP                        RCC_CR_HSEBYP_Msk                 /*!< External High Speed clock Bypass */\n#define RCC_CR_CSSON_Pos                     (19U)                             \n#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)        /*!< 0x00080000 */\n#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< Clock Security System enable */\n#define RCC_CR_PLLON_Pos                     (24U)                             \n#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)        /*!< 0x01000000 */\n#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< PLL enable */\n#define RCC_CR_PLLRDY_Pos                    (25U)                             \n#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)       /*!< 0x02000000 */\n#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< PLL clock ready flag */\n\n\n/*******************  Bit definition for RCC_CFGR register  *******************/\n/*!< SW configuration */\n#define RCC_CFGR_SW_Pos                      (0U)                              \n#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)         /*!< 0x00000003 */\n#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */\n#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)         /*!< 0x00000001 */\n#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)         /*!< 0x00000002 */\n\n#define RCC_CFGR_SW_HSI                      0x00000000U                       /*!< HSI selected as system clock */\n#define RCC_CFGR_SW_HSE                      0x00000001U                       /*!< HSE selected as system clock */\n#define RCC_CFGR_SW_PLL                      0x00000002U                       /*!< PLL selected as system clock */\n\n/*!< SWS configuration */\n#define RCC_CFGR_SWS_Pos                     (2U)                              \n#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)        /*!< 0x0000000C */\n#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */\n#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000004 */\n#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)        /*!< 0x00000008 */\n\n#define RCC_CFGR_SWS_HSI                     0x00000000U                       /*!< HSI oscillator used as system clock */\n#define RCC_CFGR_SWS_HSE                     0x00000004U                       /*!< HSE oscillator used as system clock */\n#define RCC_CFGR_SWS_PLL                     0x00000008U                       /*!< PLL used as system clock */\n\n/*!< HPRE configuration */\n#define RCC_CFGR_HPRE_Pos                    (4U)                              \n#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)       /*!< 0x000000F0 */\n#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */\n#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000010 */\n#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000020 */\n#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000040 */\n#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)       /*!< 0x00000080 */\n\n#define RCC_CFGR_HPRE_DIV1                   0x00000000U                       /*!< SYSCLK not divided */\n#define RCC_CFGR_HPRE_DIV2                   0x00000080U                       /*!< SYSCLK divided by 2 */\n#define RCC_CFGR_HPRE_DIV4                   0x00000090U                       /*!< SYSCLK divided by 4 */\n#define RCC_CFGR_HPRE_DIV8                   0x000000A0U                       /*!< SYSCLK divided by 8 */\n#define RCC_CFGR_HPRE_DIV16                  0x000000B0U                       /*!< SYSCLK divided by 16 */\n#define RCC_CFGR_HPRE_DIV64                  0x000000C0U                       /*!< SYSCLK divided by 64 */\n#define RCC_CFGR_HPRE_DIV128                 0x000000D0U                       /*!< SYSCLK divided by 128 */\n#define RCC_CFGR_HPRE_DIV256                 0x000000E0U                       /*!< SYSCLK divided by 256 */\n#define RCC_CFGR_HPRE_DIV512                 0x000000F0U                       /*!< SYSCLK divided by 512 */\n\n/*!< PPRE1 configuration */\n#define RCC_CFGR_PPRE1_Pos                   (8U)                              \n#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000700 */\n#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */\n#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000100 */\n#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000200 */\n#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)      /*!< 0x00000400 */\n\n#define RCC_CFGR_PPRE1_DIV1                  0x00000000U                       /*!< HCLK not divided */\n#define RCC_CFGR_PPRE1_DIV2                  0x00000400U                       /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE1_DIV4                  0x00000500U                       /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE1_DIV8                  0x00000600U                       /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE1_DIV16                 0x00000700U                       /*!< HCLK divided by 16 */\n\n/*!< PPRE2 configuration */\n#define RCC_CFGR_PPRE2_Pos                   (11U)                             \n#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00003800 */\n#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */\n#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00000800 */\n#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00001000 */\n#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)      /*!< 0x00002000 */\n\n#define RCC_CFGR_PPRE2_DIV1                  0x00000000U                       /*!< HCLK not divided */\n#define RCC_CFGR_PPRE2_DIV2                  0x00002000U                       /*!< HCLK divided by 2 */\n#define RCC_CFGR_PPRE2_DIV4                  0x00002800U                       /*!< HCLK divided by 4 */\n#define RCC_CFGR_PPRE2_DIV8                  0x00003000U                       /*!< HCLK divided by 8 */\n#define RCC_CFGR_PPRE2_DIV16                 0x00003800U                       /*!< HCLK divided by 16 */\n\n/*!< ADCPPRE configuration */\n#define RCC_CFGR_ADCPRE_Pos                  (14U)                             \n#define RCC_CFGR_ADCPRE_Msk                  (0x3UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x0000C000 */\n#define RCC_CFGR_ADCPRE                      RCC_CFGR_ADCPRE_Msk               /*!< ADCPRE[1:0] bits (ADC prescaler) */\n#define RCC_CFGR_ADCPRE_0                    (0x1UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00004000 */\n#define RCC_CFGR_ADCPRE_1                    (0x2UL << RCC_CFGR_ADCPRE_Pos)     /*!< 0x00008000 */\n\n#define RCC_CFGR_ADCPRE_DIV2                 0x00000000U                       /*!< PCLK2 divided by 2 */\n#define RCC_CFGR_ADCPRE_DIV4                 0x00004000U                       /*!< PCLK2 divided by 4 */\n#define RCC_CFGR_ADCPRE_DIV6                 0x00008000U                       /*!< PCLK2 divided by 6 */\n#define RCC_CFGR_ADCPRE_DIV8                 0x0000C000U                       /*!< PCLK2 divided by 8 */\n\n#define RCC_CFGR_PLLSRC_Pos                  (16U)                             \n#define RCC_CFGR_PLLSRC_Msk                  (0x1UL << RCC_CFGR_PLLSRC_Pos)     /*!< 0x00010000 */\n#define RCC_CFGR_PLLSRC                      RCC_CFGR_PLLSRC_Msk               /*!< PLL entry clock source */\n\n#define RCC_CFGR_PLLXTPRE_Pos                (17U)                             \n#define RCC_CFGR_PLLXTPRE_Msk                (0x1UL << RCC_CFGR_PLLXTPRE_Pos)   /*!< 0x00020000 */\n#define RCC_CFGR_PLLXTPRE                    RCC_CFGR_PLLXTPRE_Msk             /*!< HSE divider for PLL entry */\n\n/*!< PLLMUL configuration */\n#define RCC_CFGR_PLLMULL_Pos                 (18U)                             \n#define RCC_CFGR_PLLMULL_Msk                 (0xFUL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x003C0000 */\n#define RCC_CFGR_PLLMULL                     RCC_CFGR_PLLMULL_Msk              /*!< PLLMUL[3:0] bits (PLL multiplication factor) */\n#define RCC_CFGR_PLLMULL_0                   (0x1UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00040000 */\n#define RCC_CFGR_PLLMULL_1                   (0x2UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00080000 */\n#define RCC_CFGR_PLLMULL_2                   (0x4UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00100000 */\n#define RCC_CFGR_PLLMULL_3                   (0x8UL << RCC_CFGR_PLLMULL_Pos)    /*!< 0x00200000 */\n\n#define RCC_CFGR_PLLXTPRE_HSE                0x00000000U                      /*!< HSE clock not divided for PLL entry */\n#define RCC_CFGR_PLLXTPRE_HSE_DIV2           0x00020000U                      /*!< HSE clock divided by 2 for PLL entry */\n\n#define RCC_CFGR_PLLMULL2                    0x00000000U                       /*!< PLL input clock*2 */\n#define RCC_CFGR_PLLMULL3_Pos                (18U)                             \n#define RCC_CFGR_PLLMULL3_Msk                (0x1UL << RCC_CFGR_PLLMULL3_Pos)   /*!< 0x00040000 */\n#define RCC_CFGR_PLLMULL3                    RCC_CFGR_PLLMULL3_Msk             /*!< PLL input clock*3 */\n#define RCC_CFGR_PLLMULL4_Pos                (19U)                             \n#define RCC_CFGR_PLLMULL4_Msk                (0x1UL << RCC_CFGR_PLLMULL4_Pos)   /*!< 0x00080000 */\n#define RCC_CFGR_PLLMULL4                    RCC_CFGR_PLLMULL4_Msk             /*!< PLL input clock*4 */\n#define RCC_CFGR_PLLMULL5_Pos                (18U)                             \n#define RCC_CFGR_PLLMULL5_Msk                (0x3UL << RCC_CFGR_PLLMULL5_Pos)   /*!< 0x000C0000 */\n#define RCC_CFGR_PLLMULL5                    RCC_CFGR_PLLMULL5_Msk             /*!< PLL input clock*5 */\n#define RCC_CFGR_PLLMULL6_Pos                (20U)                             \n#define RCC_CFGR_PLLMULL6_Msk                (0x1UL << RCC_CFGR_PLLMULL6_Pos)   /*!< 0x00100000 */\n#define RCC_CFGR_PLLMULL6                    RCC_CFGR_PLLMULL6_Msk             /*!< PLL input clock*6 */\n#define RCC_CFGR_PLLMULL7_Pos                (18U)                             \n#define RCC_CFGR_PLLMULL7_Msk                (0x5UL << RCC_CFGR_PLLMULL7_Pos)   /*!< 0x00140000 */\n#define RCC_CFGR_PLLMULL7                    RCC_CFGR_PLLMULL7_Msk             /*!< PLL input clock*7 */\n#define RCC_CFGR_PLLMULL8_Pos                (19U)                             \n#define RCC_CFGR_PLLMULL8_Msk                (0x3UL << RCC_CFGR_PLLMULL8_Pos)   /*!< 0x00180000 */\n#define RCC_CFGR_PLLMULL8                    RCC_CFGR_PLLMULL8_Msk             /*!< PLL input clock*8 */\n#define RCC_CFGR_PLLMULL9_Pos                (18U)                             \n#define RCC_CFGR_PLLMULL9_Msk                (0x7UL << RCC_CFGR_PLLMULL9_Pos)   /*!< 0x001C0000 */\n#define RCC_CFGR_PLLMULL9                    RCC_CFGR_PLLMULL9_Msk             /*!< PLL input clock*9 */\n#define RCC_CFGR_PLLMULL10_Pos               (21U)                             \n#define RCC_CFGR_PLLMULL10_Msk               (0x1UL << RCC_CFGR_PLLMULL10_Pos)  /*!< 0x00200000 */\n#define RCC_CFGR_PLLMULL10                   RCC_CFGR_PLLMULL10_Msk            /*!< PLL input clock10 */\n#define RCC_CFGR_PLLMULL11_Pos               (18U)                             \n#define RCC_CFGR_PLLMULL11_Msk               (0x9UL << RCC_CFGR_PLLMULL11_Pos)  /*!< 0x00240000 */\n#define RCC_CFGR_PLLMULL11                   RCC_CFGR_PLLMULL11_Msk            /*!< PLL input clock*11 */\n#define RCC_CFGR_PLLMULL12_Pos               (19U)                             \n#define RCC_CFGR_PLLMULL12_Msk               (0x5UL << RCC_CFGR_PLLMULL12_Pos)  /*!< 0x00280000 */\n#define RCC_CFGR_PLLMULL12                   RCC_CFGR_PLLMULL12_Msk            /*!< PLL input clock*12 */\n#define RCC_CFGR_PLLMULL13_Pos               (18U)                             \n#define RCC_CFGR_PLLMULL13_Msk               (0xBUL << RCC_CFGR_PLLMULL13_Pos)  /*!< 0x002C0000 */\n#define RCC_CFGR_PLLMULL13                   RCC_CFGR_PLLMULL13_Msk            /*!< PLL input clock*13 */\n#define RCC_CFGR_PLLMULL14_Pos               (20U)                             \n#define RCC_CFGR_PLLMULL14_Msk               (0x3UL << RCC_CFGR_PLLMULL14_Pos)  /*!< 0x00300000 */\n#define RCC_CFGR_PLLMULL14                   RCC_CFGR_PLLMULL14_Msk            /*!< PLL input clock*14 */\n#define RCC_CFGR_PLLMULL15_Pos               (18U)                             \n#define RCC_CFGR_PLLMULL15_Msk               (0xDUL << RCC_CFGR_PLLMULL15_Pos)  /*!< 0x00340000 */\n#define RCC_CFGR_PLLMULL15                   RCC_CFGR_PLLMULL15_Msk            /*!< PLL input clock*15 */\n#define RCC_CFGR_PLLMULL16_Pos               (19U)                             \n#define RCC_CFGR_PLLMULL16_Msk               (0x7UL << RCC_CFGR_PLLMULL16_Pos)  /*!< 0x00380000 */\n#define RCC_CFGR_PLLMULL16                   RCC_CFGR_PLLMULL16_Msk            /*!< PLL input clock*16 */\n#define RCC_CFGR_USBPRE_Pos                  (22U)                             \n#define RCC_CFGR_USBPRE_Msk                  (0x1UL << RCC_CFGR_USBPRE_Pos)     /*!< 0x00400000 */\n#define RCC_CFGR_USBPRE                      RCC_CFGR_USBPRE_Msk               /*!< USB Device prescaler */\n\n/*!< MCO configuration */\n#define RCC_CFGR_MCO_Pos                     (24U)                             \n#define RCC_CFGR_MCO_Msk                     (0x7UL << RCC_CFGR_MCO_Pos)        /*!< 0x07000000 */\n#define RCC_CFGR_MCO                         RCC_CFGR_MCO_Msk                  /*!< MCO[2:0] bits (Microcontroller Clock Output) */\n#define RCC_CFGR_MCO_0                       (0x1UL << RCC_CFGR_MCO_Pos)        /*!< 0x01000000 */\n#define RCC_CFGR_MCO_1                       (0x2UL << RCC_CFGR_MCO_Pos)        /*!< 0x02000000 */\n#define RCC_CFGR_MCO_2                       (0x4UL << RCC_CFGR_MCO_Pos)        /*!< 0x04000000 */\n\n#define RCC_CFGR_MCO_NOCLOCK                 0x00000000U                        /*!< No clock */\n#define RCC_CFGR_MCO_SYSCLK                  0x04000000U                        /*!< System clock selected as MCO source */\n#define RCC_CFGR_MCO_HSI                     0x05000000U                        /*!< HSI clock selected as MCO source */\n#define RCC_CFGR_MCO_HSE                     0x06000000U                        /*!< HSE clock selected as MCO source  */\n#define RCC_CFGR_MCO_PLLCLK_DIV2             0x07000000U                        /*!< PLL clock divided by 2 selected as MCO source */\n\n /* Reference defines */\n #define RCC_CFGR_MCOSEL                      RCC_CFGR_MCO\n #define RCC_CFGR_MCOSEL_0                    RCC_CFGR_MCO_0\n #define RCC_CFGR_MCOSEL_1                    RCC_CFGR_MCO_1\n #define RCC_CFGR_MCOSEL_2                    RCC_CFGR_MCO_2\n #define RCC_CFGR_MCOSEL_NOCLOCK              RCC_CFGR_MCO_NOCLOCK\n #define RCC_CFGR_MCOSEL_SYSCLK               RCC_CFGR_MCO_SYSCLK\n #define RCC_CFGR_MCOSEL_HSI                  RCC_CFGR_MCO_HSI\n #define RCC_CFGR_MCOSEL_HSE                  RCC_CFGR_MCO_HSE\n #define RCC_CFGR_MCOSEL_PLL_DIV2             RCC_CFGR_MCO_PLLCLK_DIV2\n\n/*!<******************  Bit definition for RCC_CIR register  ********************/\n#define RCC_CIR_LSIRDYF_Pos                  (0U)                              \n#define RCC_CIR_LSIRDYF_Msk                  (0x1UL << RCC_CIR_LSIRDYF_Pos)     /*!< 0x00000001 */\n#define RCC_CIR_LSIRDYF                      RCC_CIR_LSIRDYF_Msk               /*!< LSI Ready Interrupt flag */\n#define RCC_CIR_LSERDYF_Pos                  (1U)                              \n#define RCC_CIR_LSERDYF_Msk                  (0x1UL << RCC_CIR_LSERDYF_Pos)     /*!< 0x00000002 */\n#define RCC_CIR_LSERDYF                      RCC_CIR_LSERDYF_Msk               /*!< LSE Ready Interrupt flag */\n#define RCC_CIR_HSIRDYF_Pos                  (2U)                              \n#define RCC_CIR_HSIRDYF_Msk                  (0x1UL << RCC_CIR_HSIRDYF_Pos)     /*!< 0x00000004 */\n#define RCC_CIR_HSIRDYF                      RCC_CIR_HSIRDYF_Msk               /*!< HSI Ready Interrupt flag */\n#define RCC_CIR_HSERDYF_Pos                  (3U)                              \n#define RCC_CIR_HSERDYF_Msk                  (0x1UL << RCC_CIR_HSERDYF_Pos)     /*!< 0x00000008 */\n#define RCC_CIR_HSERDYF                      RCC_CIR_HSERDYF_Msk               /*!< HSE Ready Interrupt flag */\n#define RCC_CIR_PLLRDYF_Pos                  (4U)                              \n#define RCC_CIR_PLLRDYF_Msk                  (0x1UL << RCC_CIR_PLLRDYF_Pos)     /*!< 0x00000010 */\n#define RCC_CIR_PLLRDYF                      RCC_CIR_PLLRDYF_Msk               /*!< PLL Ready Interrupt flag */\n#define RCC_CIR_CSSF_Pos                     (7U)                              \n#define RCC_CIR_CSSF_Msk                     (0x1UL << RCC_CIR_CSSF_Pos)        /*!< 0x00000080 */\n#define RCC_CIR_CSSF                         RCC_CIR_CSSF_Msk                  /*!< Clock Security System Interrupt flag */\n#define RCC_CIR_LSIRDYIE_Pos                 (8U)                              \n#define RCC_CIR_LSIRDYIE_Msk                 (0x1UL << RCC_CIR_LSIRDYIE_Pos)    /*!< 0x00000100 */\n#define RCC_CIR_LSIRDYIE                     RCC_CIR_LSIRDYIE_Msk              /*!< LSI Ready Interrupt Enable */\n#define RCC_CIR_LSERDYIE_Pos                 (9U)                              \n#define RCC_CIR_LSERDYIE_Msk                 (0x1UL << RCC_CIR_LSERDYIE_Pos)    /*!< 0x00000200 */\n#define RCC_CIR_LSERDYIE                     RCC_CIR_LSERDYIE_Msk              /*!< LSE Ready Interrupt Enable */\n#define RCC_CIR_HSIRDYIE_Pos                 (10U)                             \n#define RCC_CIR_HSIRDYIE_Msk                 (0x1UL << RCC_CIR_HSIRDYIE_Pos)    /*!< 0x00000400 */\n#define RCC_CIR_HSIRDYIE                     RCC_CIR_HSIRDYIE_Msk              /*!< HSI Ready Interrupt Enable */\n#define RCC_CIR_HSERDYIE_Pos                 (11U)                             \n#define RCC_CIR_HSERDYIE_Msk                 (0x1UL << RCC_CIR_HSERDYIE_Pos)    /*!< 0x00000800 */\n#define RCC_CIR_HSERDYIE                     RCC_CIR_HSERDYIE_Msk              /*!< HSE Ready Interrupt Enable */\n#define RCC_CIR_PLLRDYIE_Pos                 (12U)                             \n#define RCC_CIR_PLLRDYIE_Msk                 (0x1UL << RCC_CIR_PLLRDYIE_Pos)    /*!< 0x00001000 */\n#define RCC_CIR_PLLRDYIE                     RCC_CIR_PLLRDYIE_Msk              /*!< PLL Ready Interrupt Enable */\n#define RCC_CIR_LSIRDYC_Pos                  (16U)                             \n#define RCC_CIR_LSIRDYC_Msk                  (0x1UL << RCC_CIR_LSIRDYC_Pos)     /*!< 0x00010000 */\n#define RCC_CIR_LSIRDYC                      RCC_CIR_LSIRDYC_Msk               /*!< LSI Ready Interrupt Clear */\n#define RCC_CIR_LSERDYC_Pos                  (17U)                             \n#define RCC_CIR_LSERDYC_Msk                  (0x1UL << RCC_CIR_LSERDYC_Pos)     /*!< 0x00020000 */\n#define RCC_CIR_LSERDYC                      RCC_CIR_LSERDYC_Msk               /*!< LSE Ready Interrupt Clear */\n#define RCC_CIR_HSIRDYC_Pos                  (18U)                             \n#define RCC_CIR_HSIRDYC_Msk                  (0x1UL << RCC_CIR_HSIRDYC_Pos)     /*!< 0x00040000 */\n#define RCC_CIR_HSIRDYC                      RCC_CIR_HSIRDYC_Msk               /*!< HSI Ready Interrupt Clear */\n#define RCC_CIR_HSERDYC_Pos                  (19U)                             \n#define RCC_CIR_HSERDYC_Msk                  (0x1UL << RCC_CIR_HSERDYC_Pos)     /*!< 0x00080000 */\n#define RCC_CIR_HSERDYC                      RCC_CIR_HSERDYC_Msk               /*!< HSE Ready Interrupt Clear */\n#define RCC_CIR_PLLRDYC_Pos                  (20U)                             \n#define RCC_CIR_PLLRDYC_Msk                  (0x1UL << RCC_CIR_PLLRDYC_Pos)     /*!< 0x00100000 */\n#define RCC_CIR_PLLRDYC                      RCC_CIR_PLLRDYC_Msk               /*!< PLL Ready Interrupt Clear */\n#define RCC_CIR_CSSC_Pos                     (23U)                             \n#define RCC_CIR_CSSC_Msk                     (0x1UL << RCC_CIR_CSSC_Pos)        /*!< 0x00800000 */\n#define RCC_CIR_CSSC                         RCC_CIR_CSSC_Msk                  /*!< Clock Security System Interrupt Clear */\n\n\n/*****************  Bit definition for RCC_APB2RSTR register  *****************/\n#define RCC_APB2RSTR_AFIORST_Pos             (0U)                              \n#define RCC_APB2RSTR_AFIORST_Msk             (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */\n#define RCC_APB2RSTR_AFIORST                 RCC_APB2RSTR_AFIORST_Msk          /*!< Alternate Function I/O reset */\n#define RCC_APB2RSTR_IOPARST_Pos             (2U)                              \n#define RCC_APB2RSTR_IOPARST_Msk             (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */\n#define RCC_APB2RSTR_IOPARST                 RCC_APB2RSTR_IOPARST_Msk          /*!< I/O port A reset */\n#define RCC_APB2RSTR_IOPBRST_Pos             (3U)                              \n#define RCC_APB2RSTR_IOPBRST_Msk             (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */\n#define RCC_APB2RSTR_IOPBRST                 RCC_APB2RSTR_IOPBRST_Msk          /*!< I/O port B reset */\n#define RCC_APB2RSTR_IOPCRST_Pos             (4U)                              \n#define RCC_APB2RSTR_IOPCRST_Msk             (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */\n#define RCC_APB2RSTR_IOPCRST                 RCC_APB2RSTR_IOPCRST_Msk          /*!< I/O port C reset */\n#define RCC_APB2RSTR_IOPDRST_Pos             (5U)                              \n#define RCC_APB2RSTR_IOPDRST_Msk             (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */\n#define RCC_APB2RSTR_IOPDRST                 RCC_APB2RSTR_IOPDRST_Msk          /*!< I/O port D reset */\n#define RCC_APB2RSTR_ADC1RST_Pos             (9U)                              \n#define RCC_APB2RSTR_ADC1RST_Msk             (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */\n#define RCC_APB2RSTR_ADC1RST                 RCC_APB2RSTR_ADC1RST_Msk          /*!< ADC 1 interface reset */\n\n#define RCC_APB2RSTR_ADC2RST_Pos             (10U)                             \n#define RCC_APB2RSTR_ADC2RST_Msk             (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */\n#define RCC_APB2RSTR_ADC2RST                 RCC_APB2RSTR_ADC2RST_Msk          /*!< ADC 2 interface reset */\n\n#define RCC_APB2RSTR_TIM1RST_Pos             (11U)                             \n#define RCC_APB2RSTR_TIM1RST_Msk             (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */\n#define RCC_APB2RSTR_TIM1RST                 RCC_APB2RSTR_TIM1RST_Msk          /*!< TIM1 Timer reset */\n#define RCC_APB2RSTR_SPI1RST_Pos             (12U)                             \n#define RCC_APB2RSTR_SPI1RST_Msk             (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\n#define RCC_APB2RSTR_SPI1RST                 RCC_APB2RSTR_SPI1RST_Msk          /*!< SPI 1 reset */\n#define RCC_APB2RSTR_USART1RST_Pos           (14U)                             \n#define RCC_APB2RSTR_USART1RST_Msk           (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */\n#define RCC_APB2RSTR_USART1RST               RCC_APB2RSTR_USART1RST_Msk        /*!< USART1 reset */\n\n\n#define RCC_APB2RSTR_IOPERST_Pos             (6U)                              \n#define RCC_APB2RSTR_IOPERST_Msk             (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */\n#define RCC_APB2RSTR_IOPERST                 RCC_APB2RSTR_IOPERST_Msk          /*!< I/O port E reset */\n\n\n\n\n/*****************  Bit definition for RCC_APB1RSTR register  *****************/\n#define RCC_APB1RSTR_TIM2RST_Pos             (0U)                              \n#define RCC_APB1RSTR_TIM2RST_Msk             (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\n#define RCC_APB1RSTR_TIM2RST                 RCC_APB1RSTR_TIM2RST_Msk          /*!< Timer 2 reset */\n#define RCC_APB1RSTR_TIM3RST_Pos             (1U)                              \n#define RCC_APB1RSTR_TIM3RST_Msk             (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\n#define RCC_APB1RSTR_TIM3RST                 RCC_APB1RSTR_TIM3RST_Msk          /*!< Timer 3 reset */\n#define RCC_APB1RSTR_WWDGRST_Pos             (11U)                             \n#define RCC_APB1RSTR_WWDGRST_Msk             (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\n#define RCC_APB1RSTR_WWDGRST                 RCC_APB1RSTR_WWDGRST_Msk          /*!< Window Watchdog reset */\n#define RCC_APB1RSTR_USART2RST_Pos           (17U)                             \n#define RCC_APB1RSTR_USART2RST_Msk           (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\n#define RCC_APB1RSTR_USART2RST               RCC_APB1RSTR_USART2RST_Msk        /*!< USART 2 reset */\n#define RCC_APB1RSTR_I2C1RST_Pos             (21U)                             \n#define RCC_APB1RSTR_I2C1RST_Msk             (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\n#define RCC_APB1RSTR_I2C1RST                 RCC_APB1RSTR_I2C1RST_Msk          /*!< I2C 1 reset */\n\n#define RCC_APB1RSTR_CAN1RST_Pos             (25U)                             \n#define RCC_APB1RSTR_CAN1RST_Msk             (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */\n#define RCC_APB1RSTR_CAN1RST                 RCC_APB1RSTR_CAN1RST_Msk          /*!< CAN1 reset */\n\n#define RCC_APB1RSTR_BKPRST_Pos              (27U)                             \n#define RCC_APB1RSTR_BKPRST_Msk              (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */\n#define RCC_APB1RSTR_BKPRST                  RCC_APB1RSTR_BKPRST_Msk           /*!< Backup interface reset */\n#define RCC_APB1RSTR_PWRRST_Pos              (28U)                             \n#define RCC_APB1RSTR_PWRRST_Msk              (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\n#define RCC_APB1RSTR_PWRRST                  RCC_APB1RSTR_PWRRST_Msk           /*!< Power interface reset */\n\n#define RCC_APB1RSTR_TIM4RST_Pos             (2U)                              \n#define RCC_APB1RSTR_TIM4RST_Msk             (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\n#define RCC_APB1RSTR_TIM4RST                 RCC_APB1RSTR_TIM4RST_Msk          /*!< Timer 4 reset */\n#define RCC_APB1RSTR_SPI2RST_Pos             (14U)                             \n#define RCC_APB1RSTR_SPI2RST_Msk             (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\n#define RCC_APB1RSTR_SPI2RST                 RCC_APB1RSTR_SPI2RST_Msk          /*!< SPI 2 reset */\n#define RCC_APB1RSTR_USART3RST_Pos           (18U)                             \n#define RCC_APB1RSTR_USART3RST_Msk           (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\n#define RCC_APB1RSTR_USART3RST               RCC_APB1RSTR_USART3RST_Msk        /*!< USART 3 reset */\n#define RCC_APB1RSTR_I2C2RST_Pos             (22U)                             \n#define RCC_APB1RSTR_I2C2RST_Msk             (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\n#define RCC_APB1RSTR_I2C2RST                 RCC_APB1RSTR_I2C2RST_Msk          /*!< I2C 2 reset */\n\n#define RCC_APB1RSTR_USBRST_Pos              (23U)                             \n#define RCC_APB1RSTR_USBRST_Msk              (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */\n#define RCC_APB1RSTR_USBRST                  RCC_APB1RSTR_USBRST_Msk           /*!< USB Device reset */\n\n\n\n\n\n\n/******************  Bit definition for RCC_AHBENR register  ******************/\n#define RCC_AHBENR_DMA1EN_Pos                (0U)                              \n#define RCC_AHBENR_DMA1EN_Msk                (0x1UL << RCC_AHBENR_DMA1EN_Pos)   /*!< 0x00000001 */\n#define RCC_AHBENR_DMA1EN                    RCC_AHBENR_DMA1EN_Msk             /*!< DMA1 clock enable */\n#define RCC_AHBENR_SRAMEN_Pos                (2U)                              \n#define RCC_AHBENR_SRAMEN_Msk                (0x1UL << RCC_AHBENR_SRAMEN_Pos)   /*!< 0x00000004 */\n#define RCC_AHBENR_SRAMEN                    RCC_AHBENR_SRAMEN_Msk             /*!< SRAM interface clock enable */\n#define RCC_AHBENR_FLITFEN_Pos               (4U)                              \n#define RCC_AHBENR_FLITFEN_Msk               (0x1UL << RCC_AHBENR_FLITFEN_Pos)  /*!< 0x00000010 */\n#define RCC_AHBENR_FLITFEN                   RCC_AHBENR_FLITFEN_Msk            /*!< FLITF clock enable */\n#define RCC_AHBENR_CRCEN_Pos                 (6U)                              \n#define RCC_AHBENR_CRCEN_Msk                 (0x1UL << RCC_AHBENR_CRCEN_Pos)    /*!< 0x00000040 */\n#define RCC_AHBENR_CRCEN                     RCC_AHBENR_CRCEN_Msk              /*!< CRC clock enable */\n\n\n\n\n/******************  Bit definition for RCC_APB2ENR register  *****************/\n#define RCC_APB2ENR_AFIOEN_Pos               (0U)                              \n#define RCC_APB2ENR_AFIOEN_Msk               (0x1UL << RCC_APB2ENR_AFIOEN_Pos)  /*!< 0x00000001 */\n#define RCC_APB2ENR_AFIOEN                   RCC_APB2ENR_AFIOEN_Msk            /*!< Alternate Function I/O clock enable */\n#define RCC_APB2ENR_IOPAEN_Pos               (2U)                              \n#define RCC_APB2ENR_IOPAEN_Msk               (0x1UL << RCC_APB2ENR_IOPAEN_Pos)  /*!< 0x00000004 */\n#define RCC_APB2ENR_IOPAEN                   RCC_APB2ENR_IOPAEN_Msk            /*!< I/O port A clock enable */\n#define RCC_APB2ENR_IOPBEN_Pos               (3U)                              \n#define RCC_APB2ENR_IOPBEN_Msk               (0x1UL << RCC_APB2ENR_IOPBEN_Pos)  /*!< 0x00000008 */\n#define RCC_APB2ENR_IOPBEN                   RCC_APB2ENR_IOPBEN_Msk            /*!< I/O port B clock enable */\n#define RCC_APB2ENR_IOPCEN_Pos               (4U)                              \n#define RCC_APB2ENR_IOPCEN_Msk               (0x1UL << RCC_APB2ENR_IOPCEN_Pos)  /*!< 0x00000010 */\n#define RCC_APB2ENR_IOPCEN                   RCC_APB2ENR_IOPCEN_Msk            /*!< I/O port C clock enable */\n#define RCC_APB2ENR_IOPDEN_Pos               (5U)                              \n#define RCC_APB2ENR_IOPDEN_Msk               (0x1UL << RCC_APB2ENR_IOPDEN_Pos)  /*!< 0x00000020 */\n#define RCC_APB2ENR_IOPDEN                   RCC_APB2ENR_IOPDEN_Msk            /*!< I/O port D clock enable */\n#define RCC_APB2ENR_ADC1EN_Pos               (9U)                              \n#define RCC_APB2ENR_ADC1EN_Msk               (0x1UL << RCC_APB2ENR_ADC1EN_Pos)  /*!< 0x00000200 */\n#define RCC_APB2ENR_ADC1EN                   RCC_APB2ENR_ADC1EN_Msk            /*!< ADC 1 interface clock enable */\n\n#define RCC_APB2ENR_ADC2EN_Pos               (10U)                             \n#define RCC_APB2ENR_ADC2EN_Msk               (0x1UL << RCC_APB2ENR_ADC2EN_Pos)  /*!< 0x00000400 */\n#define RCC_APB2ENR_ADC2EN                   RCC_APB2ENR_ADC2EN_Msk            /*!< ADC 2 interface clock enable */\n\n#define RCC_APB2ENR_TIM1EN_Pos               (11U)                             \n#define RCC_APB2ENR_TIM1EN_Msk               (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */\n#define RCC_APB2ENR_TIM1EN                   RCC_APB2ENR_TIM1EN_Msk            /*!< TIM1 Timer clock enable */\n#define RCC_APB2ENR_SPI1EN_Pos               (12U)                             \n#define RCC_APB2ENR_SPI1EN_Msk               (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */\n#define RCC_APB2ENR_SPI1EN                   RCC_APB2ENR_SPI1EN_Msk            /*!< SPI 1 clock enable */\n#define RCC_APB2ENR_USART1EN_Pos             (14U)                             \n#define RCC_APB2ENR_USART1EN_Msk             (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */\n#define RCC_APB2ENR_USART1EN                 RCC_APB2ENR_USART1EN_Msk          /*!< USART1 clock enable */\n\n\n#define RCC_APB2ENR_IOPEEN_Pos               (6U)                              \n#define RCC_APB2ENR_IOPEEN_Msk               (0x1UL << RCC_APB2ENR_IOPEEN_Pos)  /*!< 0x00000040 */\n#define RCC_APB2ENR_IOPEEN                   RCC_APB2ENR_IOPEEN_Msk            /*!< I/O port E clock enable */\n\n\n\n\n/*****************  Bit definition for RCC_APB1ENR register  ******************/\n#define RCC_APB1ENR_TIM2EN_Pos               (0U)                              \n#define RCC_APB1ENR_TIM2EN_Msk               (0x1UL << RCC_APB1ENR_TIM2EN_Pos)  /*!< 0x00000001 */\n#define RCC_APB1ENR_TIM2EN                   RCC_APB1ENR_TIM2EN_Msk            /*!< Timer 2 clock enabled*/\n#define RCC_APB1ENR_TIM3EN_Pos               (1U)                              \n#define RCC_APB1ENR_TIM3EN_Msk               (0x1UL << RCC_APB1ENR_TIM3EN_Pos)  /*!< 0x00000002 */\n#define RCC_APB1ENR_TIM3EN                   RCC_APB1ENR_TIM3EN_Msk            /*!< Timer 3 clock enable */\n#define RCC_APB1ENR_WWDGEN_Pos               (11U)                             \n#define RCC_APB1ENR_WWDGEN_Msk               (0x1UL << RCC_APB1ENR_WWDGEN_Pos)  /*!< 0x00000800 */\n#define RCC_APB1ENR_WWDGEN                   RCC_APB1ENR_WWDGEN_Msk            /*!< Window Watchdog clock enable */\n#define RCC_APB1ENR_USART2EN_Pos             (17U)                             \n#define RCC_APB1ENR_USART2EN_Msk             (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\n#define RCC_APB1ENR_USART2EN                 RCC_APB1ENR_USART2EN_Msk          /*!< USART 2 clock enable */\n#define RCC_APB1ENR_I2C1EN_Pos               (21U)                             \n#define RCC_APB1ENR_I2C1EN_Msk               (0x1UL << RCC_APB1ENR_I2C1EN_Pos)  /*!< 0x00200000 */\n#define RCC_APB1ENR_I2C1EN                   RCC_APB1ENR_I2C1EN_Msk            /*!< I2C 1 clock enable */\n\n#define RCC_APB1ENR_CAN1EN_Pos               (25U)                             \n#define RCC_APB1ENR_CAN1EN_Msk               (0x1UL << RCC_APB1ENR_CAN1EN_Pos)  /*!< 0x02000000 */\n#define RCC_APB1ENR_CAN1EN                   RCC_APB1ENR_CAN1EN_Msk            /*!< CAN1 clock enable */\n\n#define RCC_APB1ENR_BKPEN_Pos                (27U)                             \n#define RCC_APB1ENR_BKPEN_Msk                (0x1UL << RCC_APB1ENR_BKPEN_Pos)   /*!< 0x08000000 */\n#define RCC_APB1ENR_BKPEN                    RCC_APB1ENR_BKPEN_Msk             /*!< Backup interface clock enable */\n#define RCC_APB1ENR_PWREN_Pos                (28U)                             \n#define RCC_APB1ENR_PWREN_Msk                (0x1UL << RCC_APB1ENR_PWREN_Pos)   /*!< 0x10000000 */\n#define RCC_APB1ENR_PWREN                    RCC_APB1ENR_PWREN_Msk             /*!< Power interface clock enable */\n\n#define RCC_APB1ENR_TIM4EN_Pos               (2U)                              \n#define RCC_APB1ENR_TIM4EN_Msk               (0x1UL << RCC_APB1ENR_TIM4EN_Pos)  /*!< 0x00000004 */\n#define RCC_APB1ENR_TIM4EN                   RCC_APB1ENR_TIM4EN_Msk            /*!< Timer 4 clock enable */\n#define RCC_APB1ENR_SPI2EN_Pos               (14U)                             \n#define RCC_APB1ENR_SPI2EN_Msk               (0x1UL << RCC_APB1ENR_SPI2EN_Pos)  /*!< 0x00004000 */\n#define RCC_APB1ENR_SPI2EN                   RCC_APB1ENR_SPI2EN_Msk            /*!< SPI 2 clock enable */\n#define RCC_APB1ENR_USART3EN_Pos             (18U)                             \n#define RCC_APB1ENR_USART3EN_Msk             (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\n#define RCC_APB1ENR_USART3EN                 RCC_APB1ENR_USART3EN_Msk          /*!< USART 3 clock enable */\n#define RCC_APB1ENR_I2C2EN_Pos               (22U)                             \n#define RCC_APB1ENR_I2C2EN_Msk               (0x1UL << RCC_APB1ENR_I2C2EN_Pos)  /*!< 0x00400000 */\n#define RCC_APB1ENR_I2C2EN                   RCC_APB1ENR_I2C2EN_Msk            /*!< I2C 2 clock enable */\n\n#define RCC_APB1ENR_USBEN_Pos                (23U)                             \n#define RCC_APB1ENR_USBEN_Msk                (0x1UL << RCC_APB1ENR_USBEN_Pos)   /*!< 0x00800000 */\n#define RCC_APB1ENR_USBEN                    RCC_APB1ENR_USBEN_Msk             /*!< USB Device clock enable */\n\n\n\n\n\n\n/*******************  Bit definition for RCC_BDCR register  *******************/\n#define RCC_BDCR_LSEON_Pos                   (0U)                              \n#define RCC_BDCR_LSEON_Msk                   (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */\n#define RCC_BDCR_LSEON                       RCC_BDCR_LSEON_Msk                /*!< External Low Speed oscillator enable */\n#define RCC_BDCR_LSERDY_Pos                  (1U)                              \n#define RCC_BDCR_LSERDY_Msk                  (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */\n#define RCC_BDCR_LSERDY                      RCC_BDCR_LSERDY_Msk               /*!< External Low Speed oscillator Ready */\n#define RCC_BDCR_LSEBYP_Pos                  (2U)                              \n#define RCC_BDCR_LSEBYP_Msk                  (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */\n#define RCC_BDCR_LSEBYP                      RCC_BDCR_LSEBYP_Msk               /*!< External Low Speed oscillator Bypass */\n\n#define RCC_BDCR_RTCSEL_Pos                  (8U)                              \n#define RCC_BDCR_RTCSEL_Msk                  (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */\n#define RCC_BDCR_RTCSEL                      RCC_BDCR_RTCSEL_Msk               /*!< RTCSEL[1:0] bits (RTC clock source selection) */\n#define RCC_BDCR_RTCSEL_0                    (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */\n#define RCC_BDCR_RTCSEL_1                    (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */\n\n/*!< RTC congiguration */\n#define RCC_BDCR_RTCSEL_NOCLOCK              0x00000000U                       /*!< No clock */\n#define RCC_BDCR_RTCSEL_LSE                  0x00000100U                       /*!< LSE oscillator clock used as RTC clock */\n#define RCC_BDCR_RTCSEL_LSI                  0x00000200U                       /*!< LSI oscillator clock used as RTC clock */\n#define RCC_BDCR_RTCSEL_HSE                  0x00000300U                       /*!< HSE oscillator clock divided by 128 used as RTC clock */\n\n#define RCC_BDCR_RTCEN_Pos                   (15U)                             \n#define RCC_BDCR_RTCEN_Msk                   (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */\n#define RCC_BDCR_RTCEN                       RCC_BDCR_RTCEN_Msk                /*!< RTC clock enable */\n#define RCC_BDCR_BDRST_Pos                   (16U)                             \n#define RCC_BDCR_BDRST_Msk                   (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */\n#define RCC_BDCR_BDRST                       RCC_BDCR_BDRST_Msk                /*!< Backup domain software reset  */\n\n/*******************  Bit definition for RCC_CSR register  ********************/  \n#define RCC_CSR_LSION_Pos                    (0U)                              \n#define RCC_CSR_LSION_Msk                    (0x1UL << RCC_CSR_LSION_Pos)       /*!< 0x00000001 */\n#define RCC_CSR_LSION                        RCC_CSR_LSION_Msk                 /*!< Internal Low Speed oscillator enable */\n#define RCC_CSR_LSIRDY_Pos                   (1U)                              \n#define RCC_CSR_LSIRDY_Msk                   (0x1UL << RCC_CSR_LSIRDY_Pos)      /*!< 0x00000002 */\n#define RCC_CSR_LSIRDY                       RCC_CSR_LSIRDY_Msk                /*!< Internal Low Speed oscillator Ready */\n#define RCC_CSR_RMVF_Pos                     (24U)                             \n#define RCC_CSR_RMVF_Msk                     (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x01000000 */\n#define RCC_CSR_RMVF                         RCC_CSR_RMVF_Msk                  /*!< Remove reset flag */\n#define RCC_CSR_PINRSTF_Pos                  (26U)                             \n#define RCC_CSR_PINRSTF_Msk                  (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */\n#define RCC_CSR_PINRSTF                      RCC_CSR_PINRSTF_Msk               /*!< PIN reset flag */\n#define RCC_CSR_PORRSTF_Pos                  (27U)                             \n#define RCC_CSR_PORRSTF_Msk                  (0x1UL << RCC_CSR_PORRSTF_Pos)     /*!< 0x08000000 */\n#define RCC_CSR_PORRSTF                      RCC_CSR_PORRSTF_Msk               /*!< POR/PDR reset flag */\n#define RCC_CSR_SFTRSTF_Pos                  (28U)                             \n#define RCC_CSR_SFTRSTF_Msk                  (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */\n#define RCC_CSR_SFTRSTF                      RCC_CSR_SFTRSTF_Msk               /*!< Software Reset flag */\n#define RCC_CSR_IWDGRSTF_Pos                 (29U)                             \n#define RCC_CSR_IWDGRSTF_Msk                 (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */\n#define RCC_CSR_IWDGRSTF                     RCC_CSR_IWDGRSTF_Msk              /*!< Independent Watchdog reset flag */\n#define RCC_CSR_WWDGRSTF_Pos                 (30U)                             \n#define RCC_CSR_WWDGRSTF_Msk                 (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */\n#define RCC_CSR_WWDGRSTF                     RCC_CSR_WWDGRSTF_Msk              /*!< Window watchdog reset flag */\n#define RCC_CSR_LPWRRSTF_Pos                 (31U)                             \n#define RCC_CSR_LPWRRSTF_Msk                 (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */\n#define RCC_CSR_LPWRRSTF                     RCC_CSR_LPWRRSTF_Msk              /*!< Low-Power reset flag */\n\n\n \n/******************************************************************************/\n/*                                                                            */\n/*                General Purpose and Alternate Function I/O                  */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for GPIO_CRL register  *******************/\n#define GPIO_CRL_MODE_Pos                    (0U)                              \n#define GPIO_CRL_MODE_Msk                    (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */\n#define GPIO_CRL_MODE                        GPIO_CRL_MODE_Msk                 /*!< Port x mode bits */\n\n#define GPIO_CRL_MODE0_Pos                   (0U)                              \n#define GPIO_CRL_MODE0_Msk                   (0x3UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000003 */\n#define GPIO_CRL_MODE0                       GPIO_CRL_MODE0_Msk                /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */\n#define GPIO_CRL_MODE0_0                     (0x1UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000001 */\n#define GPIO_CRL_MODE0_1                     (0x2UL << GPIO_CRL_MODE0_Pos)      /*!< 0x00000002 */\n\n#define GPIO_CRL_MODE1_Pos                   (4U)                              \n#define GPIO_CRL_MODE1_Msk                   (0x3UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000030 */\n#define GPIO_CRL_MODE1                       GPIO_CRL_MODE1_Msk                /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */\n#define GPIO_CRL_MODE1_0                     (0x1UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000010 */\n#define GPIO_CRL_MODE1_1                     (0x2UL << GPIO_CRL_MODE1_Pos)      /*!< 0x00000020 */\n\n#define GPIO_CRL_MODE2_Pos                   (8U)                              \n#define GPIO_CRL_MODE2_Msk                   (0x3UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000300 */\n#define GPIO_CRL_MODE2                       GPIO_CRL_MODE2_Msk                /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */\n#define GPIO_CRL_MODE2_0                     (0x1UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000100 */\n#define GPIO_CRL_MODE2_1                     (0x2UL << GPIO_CRL_MODE2_Pos)      /*!< 0x00000200 */\n\n#define GPIO_CRL_MODE3_Pos                   (12U)                             \n#define GPIO_CRL_MODE3_Msk                   (0x3UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00003000 */\n#define GPIO_CRL_MODE3                       GPIO_CRL_MODE3_Msk                /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */\n#define GPIO_CRL_MODE3_0                     (0x1UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00001000 */\n#define GPIO_CRL_MODE3_1                     (0x2UL << GPIO_CRL_MODE3_Pos)      /*!< 0x00002000 */\n\n#define GPIO_CRL_MODE4_Pos                   (16U)                             \n#define GPIO_CRL_MODE4_Msk                   (0x3UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00030000 */\n#define GPIO_CRL_MODE4                       GPIO_CRL_MODE4_Msk                /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */\n#define GPIO_CRL_MODE4_0                     (0x1UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00010000 */\n#define GPIO_CRL_MODE4_1                     (0x2UL << GPIO_CRL_MODE4_Pos)      /*!< 0x00020000 */\n\n#define GPIO_CRL_MODE5_Pos                   (20U)                             \n#define GPIO_CRL_MODE5_Msk                   (0x3UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00300000 */\n#define GPIO_CRL_MODE5                       GPIO_CRL_MODE5_Msk                /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */\n#define GPIO_CRL_MODE5_0                     (0x1UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00100000 */\n#define GPIO_CRL_MODE5_1                     (0x2UL << GPIO_CRL_MODE5_Pos)      /*!< 0x00200000 */\n\n#define GPIO_CRL_MODE6_Pos                   (24U)                             \n#define GPIO_CRL_MODE6_Msk                   (0x3UL << GPIO_CRL_MODE6_Pos)      /*!< 0x03000000 */\n#define GPIO_CRL_MODE6                       GPIO_CRL_MODE6_Msk                /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */\n#define GPIO_CRL_MODE6_0                     (0x1UL << GPIO_CRL_MODE6_Pos)      /*!< 0x01000000 */\n#define GPIO_CRL_MODE6_1                     (0x2UL << GPIO_CRL_MODE6_Pos)      /*!< 0x02000000 */\n\n#define GPIO_CRL_MODE7_Pos                   (28U)                             \n#define GPIO_CRL_MODE7_Msk                   (0x3UL << GPIO_CRL_MODE7_Pos)      /*!< 0x30000000 */\n#define GPIO_CRL_MODE7                       GPIO_CRL_MODE7_Msk                /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */\n#define GPIO_CRL_MODE7_0                     (0x1UL << GPIO_CRL_MODE7_Pos)      /*!< 0x10000000 */\n#define GPIO_CRL_MODE7_1                     (0x2UL << GPIO_CRL_MODE7_Pos)      /*!< 0x20000000 */\n\n#define GPIO_CRL_CNF_Pos                     (2U)                              \n#define GPIO_CRL_CNF_Msk                     (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */\n#define GPIO_CRL_CNF                         GPIO_CRL_CNF_Msk                  /*!< Port x configuration bits */\n\n#define GPIO_CRL_CNF0_Pos                    (2U)                              \n#define GPIO_CRL_CNF0_Msk                    (0x3UL << GPIO_CRL_CNF0_Pos)       /*!< 0x0000000C */\n#define GPIO_CRL_CNF0                        GPIO_CRL_CNF0_Msk                 /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */\n#define GPIO_CRL_CNF0_0                      (0x1UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000004 */\n#define GPIO_CRL_CNF0_1                      (0x2UL << GPIO_CRL_CNF0_Pos)       /*!< 0x00000008 */\n\n#define GPIO_CRL_CNF1_Pos                    (6U)                              \n#define GPIO_CRL_CNF1_Msk                    (0x3UL << GPIO_CRL_CNF1_Pos)       /*!< 0x000000C0 */\n#define GPIO_CRL_CNF1                        GPIO_CRL_CNF1_Msk                 /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */\n#define GPIO_CRL_CNF1_0                      (0x1UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000040 */\n#define GPIO_CRL_CNF1_1                      (0x2UL << GPIO_CRL_CNF1_Pos)       /*!< 0x00000080 */\n\n#define GPIO_CRL_CNF2_Pos                    (10U)                             \n#define GPIO_CRL_CNF2_Msk                    (0x3UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000C00 */\n#define GPIO_CRL_CNF2                        GPIO_CRL_CNF2_Msk                 /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */\n#define GPIO_CRL_CNF2_0                      (0x1UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000400 */\n#define GPIO_CRL_CNF2_1                      (0x2UL << GPIO_CRL_CNF2_Pos)       /*!< 0x00000800 */\n\n#define GPIO_CRL_CNF3_Pos                    (14U)                             \n#define GPIO_CRL_CNF3_Msk                    (0x3UL << GPIO_CRL_CNF3_Pos)       /*!< 0x0000C000 */\n#define GPIO_CRL_CNF3                        GPIO_CRL_CNF3_Msk                 /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */\n#define GPIO_CRL_CNF3_0                      (0x1UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00004000 */\n#define GPIO_CRL_CNF3_1                      (0x2UL << GPIO_CRL_CNF3_Pos)       /*!< 0x00008000 */\n\n#define GPIO_CRL_CNF4_Pos                    (18U)                             \n#define GPIO_CRL_CNF4_Msk                    (0x3UL << GPIO_CRL_CNF4_Pos)       /*!< 0x000C0000 */\n#define GPIO_CRL_CNF4                        GPIO_CRL_CNF4_Msk                 /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */\n#define GPIO_CRL_CNF4_0                      (0x1UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00040000 */\n#define GPIO_CRL_CNF4_1                      (0x2UL << GPIO_CRL_CNF4_Pos)       /*!< 0x00080000 */\n\n#define GPIO_CRL_CNF5_Pos                    (22U)                             \n#define GPIO_CRL_CNF5_Msk                    (0x3UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00C00000 */\n#define GPIO_CRL_CNF5                        GPIO_CRL_CNF5_Msk                 /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */\n#define GPIO_CRL_CNF5_0                      (0x1UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00400000 */\n#define GPIO_CRL_CNF5_1                      (0x2UL << GPIO_CRL_CNF5_Pos)       /*!< 0x00800000 */\n\n#define GPIO_CRL_CNF6_Pos                    (26U)                             \n#define GPIO_CRL_CNF6_Msk                    (0x3UL << GPIO_CRL_CNF6_Pos)       /*!< 0x0C000000 */\n#define GPIO_CRL_CNF6                        GPIO_CRL_CNF6_Msk                 /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */\n#define GPIO_CRL_CNF6_0                      (0x1UL << GPIO_CRL_CNF6_Pos)       /*!< 0x04000000 */\n#define GPIO_CRL_CNF6_1                      (0x2UL << GPIO_CRL_CNF6_Pos)       /*!< 0x08000000 */\n\n#define GPIO_CRL_CNF7_Pos                    (30U)                             \n#define GPIO_CRL_CNF7_Msk                    (0x3UL << GPIO_CRL_CNF7_Pos)       /*!< 0xC0000000 */\n#define GPIO_CRL_CNF7                        GPIO_CRL_CNF7_Msk                 /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */\n#define GPIO_CRL_CNF7_0                      (0x1UL << GPIO_CRL_CNF7_Pos)       /*!< 0x40000000 */\n#define GPIO_CRL_CNF7_1                      (0x2UL << GPIO_CRL_CNF7_Pos)       /*!< 0x80000000 */\n\n/*******************  Bit definition for GPIO_CRH register  *******************/\n#define GPIO_CRH_MODE_Pos                    (0U)                              \n#define GPIO_CRH_MODE_Msk                    (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */\n#define GPIO_CRH_MODE                        GPIO_CRH_MODE_Msk                 /*!< Port x mode bits */\n\n#define GPIO_CRH_MODE8_Pos                   (0U)                              \n#define GPIO_CRH_MODE8_Msk                   (0x3UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000003 */\n#define GPIO_CRH_MODE8                       GPIO_CRH_MODE8_Msk                /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */\n#define GPIO_CRH_MODE8_0                     (0x1UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000001 */\n#define GPIO_CRH_MODE8_1                     (0x2UL << GPIO_CRH_MODE8_Pos)      /*!< 0x00000002 */\n\n#define GPIO_CRH_MODE9_Pos                   (4U)                              \n#define GPIO_CRH_MODE9_Msk                   (0x3UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000030 */\n#define GPIO_CRH_MODE9                       GPIO_CRH_MODE9_Msk                /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */\n#define GPIO_CRH_MODE9_0                     (0x1UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000010 */\n#define GPIO_CRH_MODE9_1                     (0x2UL << GPIO_CRH_MODE9_Pos)      /*!< 0x00000020 */\n\n#define GPIO_CRH_MODE10_Pos                  (8U)                              \n#define GPIO_CRH_MODE10_Msk                  (0x3UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000300 */\n#define GPIO_CRH_MODE10                      GPIO_CRH_MODE10_Msk               /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */\n#define GPIO_CRH_MODE10_0                    (0x1UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000100 */\n#define GPIO_CRH_MODE10_1                    (0x2UL << GPIO_CRH_MODE10_Pos)     /*!< 0x00000200 */\n\n#define GPIO_CRH_MODE11_Pos                  (12U)                             \n#define GPIO_CRH_MODE11_Msk                  (0x3UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00003000 */\n#define GPIO_CRH_MODE11                      GPIO_CRH_MODE11_Msk               /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */\n#define GPIO_CRH_MODE11_0                    (0x1UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00001000 */\n#define GPIO_CRH_MODE11_1                    (0x2UL << GPIO_CRH_MODE11_Pos)     /*!< 0x00002000 */\n\n#define GPIO_CRH_MODE12_Pos                  (16U)                             \n#define GPIO_CRH_MODE12_Msk                  (0x3UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00030000 */\n#define GPIO_CRH_MODE12                      GPIO_CRH_MODE12_Msk               /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */\n#define GPIO_CRH_MODE12_0                    (0x1UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00010000 */\n#define GPIO_CRH_MODE12_1                    (0x2UL << GPIO_CRH_MODE12_Pos)     /*!< 0x00020000 */\n\n#define GPIO_CRH_MODE13_Pos                  (20U)                             \n#define GPIO_CRH_MODE13_Msk                  (0x3UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00300000 */\n#define GPIO_CRH_MODE13                      GPIO_CRH_MODE13_Msk               /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */\n#define GPIO_CRH_MODE13_0                    (0x1UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00100000 */\n#define GPIO_CRH_MODE13_1                    (0x2UL << GPIO_CRH_MODE13_Pos)     /*!< 0x00200000 */\n\n#define GPIO_CRH_MODE14_Pos                  (24U)                             \n#define GPIO_CRH_MODE14_Msk                  (0x3UL << GPIO_CRH_MODE14_Pos)     /*!< 0x03000000 */\n#define GPIO_CRH_MODE14                      GPIO_CRH_MODE14_Msk               /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */\n#define GPIO_CRH_MODE14_0                    (0x1UL << GPIO_CRH_MODE14_Pos)     /*!< 0x01000000 */\n#define GPIO_CRH_MODE14_1                    (0x2UL << GPIO_CRH_MODE14_Pos)     /*!< 0x02000000 */\n\n#define GPIO_CRH_MODE15_Pos                  (28U)                             \n#define GPIO_CRH_MODE15_Msk                  (0x3UL << GPIO_CRH_MODE15_Pos)     /*!< 0x30000000 */\n#define GPIO_CRH_MODE15                      GPIO_CRH_MODE15_Msk               /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */\n#define GPIO_CRH_MODE15_0                    (0x1UL << GPIO_CRH_MODE15_Pos)     /*!< 0x10000000 */\n#define GPIO_CRH_MODE15_1                    (0x2UL << GPIO_CRH_MODE15_Pos)     /*!< 0x20000000 */\n\n#define GPIO_CRH_CNF_Pos                     (2U)                              \n#define GPIO_CRH_CNF_Msk                     (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */\n#define GPIO_CRH_CNF                         GPIO_CRH_CNF_Msk                  /*!< Port x configuration bits */\n\n#define GPIO_CRH_CNF8_Pos                    (2U)                              \n#define GPIO_CRH_CNF8_Msk                    (0x3UL << GPIO_CRH_CNF8_Pos)       /*!< 0x0000000C */\n#define GPIO_CRH_CNF8                        GPIO_CRH_CNF8_Msk                 /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */\n#define GPIO_CRH_CNF8_0                      (0x1UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000004 */\n#define GPIO_CRH_CNF8_1                      (0x2UL << GPIO_CRH_CNF8_Pos)       /*!< 0x00000008 */\n\n#define GPIO_CRH_CNF9_Pos                    (6U)                              \n#define GPIO_CRH_CNF9_Msk                    (0x3UL << GPIO_CRH_CNF9_Pos)       /*!< 0x000000C0 */\n#define GPIO_CRH_CNF9                        GPIO_CRH_CNF9_Msk                 /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */\n#define GPIO_CRH_CNF9_0                      (0x1UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000040 */\n#define GPIO_CRH_CNF9_1                      (0x2UL << GPIO_CRH_CNF9_Pos)       /*!< 0x00000080 */\n\n#define GPIO_CRH_CNF10_Pos                   (10U)                             \n#define GPIO_CRH_CNF10_Msk                   (0x3UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000C00 */\n#define GPIO_CRH_CNF10                       GPIO_CRH_CNF10_Msk                /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */\n#define GPIO_CRH_CNF10_0                     (0x1UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000400 */\n#define GPIO_CRH_CNF10_1                     (0x2UL << GPIO_CRH_CNF10_Pos)      /*!< 0x00000800 */\n\n#define GPIO_CRH_CNF11_Pos                   (14U)                             \n#define GPIO_CRH_CNF11_Msk                   (0x3UL << GPIO_CRH_CNF11_Pos)      /*!< 0x0000C000 */\n#define GPIO_CRH_CNF11                       GPIO_CRH_CNF11_Msk                /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */\n#define GPIO_CRH_CNF11_0                     (0x1UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00004000 */\n#define GPIO_CRH_CNF11_1                     (0x2UL << GPIO_CRH_CNF11_Pos)      /*!< 0x00008000 */\n\n#define GPIO_CRH_CNF12_Pos                   (18U)                             \n#define GPIO_CRH_CNF12_Msk                   (0x3UL << GPIO_CRH_CNF12_Pos)      /*!< 0x000C0000 */\n#define GPIO_CRH_CNF12                       GPIO_CRH_CNF12_Msk                /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */\n#define GPIO_CRH_CNF12_0                     (0x1UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00040000 */\n#define GPIO_CRH_CNF12_1                     (0x2UL << GPIO_CRH_CNF12_Pos)      /*!< 0x00080000 */\n\n#define GPIO_CRH_CNF13_Pos                   (22U)                             \n#define GPIO_CRH_CNF13_Msk                   (0x3UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00C00000 */\n#define GPIO_CRH_CNF13                       GPIO_CRH_CNF13_Msk                /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */\n#define GPIO_CRH_CNF13_0                     (0x1UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00400000 */\n#define GPIO_CRH_CNF13_1                     (0x2UL << GPIO_CRH_CNF13_Pos)      /*!< 0x00800000 */\n\n#define GPIO_CRH_CNF14_Pos                   (26U)                             \n#define GPIO_CRH_CNF14_Msk                   (0x3UL << GPIO_CRH_CNF14_Pos)      /*!< 0x0C000000 */\n#define GPIO_CRH_CNF14                       GPIO_CRH_CNF14_Msk                /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */\n#define GPIO_CRH_CNF14_0                     (0x1UL << GPIO_CRH_CNF14_Pos)      /*!< 0x04000000 */\n#define GPIO_CRH_CNF14_1                     (0x2UL << GPIO_CRH_CNF14_Pos)      /*!< 0x08000000 */\n\n#define GPIO_CRH_CNF15_Pos                   (30U)                             \n#define GPIO_CRH_CNF15_Msk                   (0x3UL << GPIO_CRH_CNF15_Pos)      /*!< 0xC0000000 */\n#define GPIO_CRH_CNF15                       GPIO_CRH_CNF15_Msk                /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */\n#define GPIO_CRH_CNF15_0                     (0x1UL << GPIO_CRH_CNF15_Pos)      /*!< 0x40000000 */\n#define GPIO_CRH_CNF15_1                     (0x2UL << GPIO_CRH_CNF15_Pos)      /*!< 0x80000000 */\n\n/*!<******************  Bit definition for GPIO_IDR register  *******************/\n#define GPIO_IDR_IDR0_Pos                    (0U)                              \n#define GPIO_IDR_IDR0_Msk                    (0x1UL << GPIO_IDR_IDR0_Pos)       /*!< 0x00000001 */\n#define GPIO_IDR_IDR0                        GPIO_IDR_IDR0_Msk                 /*!< Port input data, bit 0 */\n#define GPIO_IDR_IDR1_Pos                    (1U)                              \n#define GPIO_IDR_IDR1_Msk                    (0x1UL << GPIO_IDR_IDR1_Pos)       /*!< 0x00000002 */\n#define GPIO_IDR_IDR1                        GPIO_IDR_IDR1_Msk                 /*!< Port input data, bit 1 */\n#define GPIO_IDR_IDR2_Pos                    (2U)                              \n#define GPIO_IDR_IDR2_Msk                    (0x1UL << GPIO_IDR_IDR2_Pos)       /*!< 0x00000004 */\n#define GPIO_IDR_IDR2                        GPIO_IDR_IDR2_Msk                 /*!< Port input data, bit 2 */\n#define GPIO_IDR_IDR3_Pos                    (3U)                              \n#define GPIO_IDR_IDR3_Msk                    (0x1UL << GPIO_IDR_IDR3_Pos)       /*!< 0x00000008 */\n#define GPIO_IDR_IDR3                        GPIO_IDR_IDR3_Msk                 /*!< Port input data, bit 3 */\n#define GPIO_IDR_IDR4_Pos                    (4U)                              \n#define GPIO_IDR_IDR4_Msk                    (0x1UL << GPIO_IDR_IDR4_Pos)       /*!< 0x00000010 */\n#define GPIO_IDR_IDR4                        GPIO_IDR_IDR4_Msk                 /*!< Port input data, bit 4 */\n#define GPIO_IDR_IDR5_Pos                    (5U)                              \n#define GPIO_IDR_IDR5_Msk                    (0x1UL << GPIO_IDR_IDR5_Pos)       /*!< 0x00000020 */\n#define GPIO_IDR_IDR5                        GPIO_IDR_IDR5_Msk                 /*!< Port input data, bit 5 */\n#define GPIO_IDR_IDR6_Pos                    (6U)                              \n#define GPIO_IDR_IDR6_Msk                    (0x1UL << GPIO_IDR_IDR6_Pos)       /*!< 0x00000040 */\n#define GPIO_IDR_IDR6                        GPIO_IDR_IDR6_Msk                 /*!< Port input data, bit 6 */\n#define GPIO_IDR_IDR7_Pos                    (7U)                              \n#define GPIO_IDR_IDR7_Msk                    (0x1UL << GPIO_IDR_IDR7_Pos)       /*!< 0x00000080 */\n#define GPIO_IDR_IDR7                        GPIO_IDR_IDR7_Msk                 /*!< Port input data, bit 7 */\n#define GPIO_IDR_IDR8_Pos                    (8U)                              \n#define GPIO_IDR_IDR8_Msk                    (0x1UL << GPIO_IDR_IDR8_Pos)       /*!< 0x00000100 */\n#define GPIO_IDR_IDR8                        GPIO_IDR_IDR8_Msk                 /*!< Port input data, bit 8 */\n#define GPIO_IDR_IDR9_Pos                    (9U)                              \n#define GPIO_IDR_IDR9_Msk                    (0x1UL << GPIO_IDR_IDR9_Pos)       /*!< 0x00000200 */\n#define GPIO_IDR_IDR9                        GPIO_IDR_IDR9_Msk                 /*!< Port input data, bit 9 */\n#define GPIO_IDR_IDR10_Pos                   (10U)                             \n#define GPIO_IDR_IDR10_Msk                   (0x1UL << GPIO_IDR_IDR10_Pos)      /*!< 0x00000400 */\n#define GPIO_IDR_IDR10                       GPIO_IDR_IDR10_Msk                /*!< Port input data, bit 10 */\n#define GPIO_IDR_IDR11_Pos                   (11U)                             \n#define GPIO_IDR_IDR11_Msk                   (0x1UL << GPIO_IDR_IDR11_Pos)      /*!< 0x00000800 */\n#define GPIO_IDR_IDR11                       GPIO_IDR_IDR11_Msk                /*!< Port input data, bit 11 */\n#define GPIO_IDR_IDR12_Pos                   (12U)                             \n#define GPIO_IDR_IDR12_Msk                   (0x1UL << GPIO_IDR_IDR12_Pos)      /*!< 0x00001000 */\n#define GPIO_IDR_IDR12                       GPIO_IDR_IDR12_Msk                /*!< Port input data, bit 12 */\n#define GPIO_IDR_IDR13_Pos                   (13U)                             \n#define GPIO_IDR_IDR13_Msk                   (0x1UL << GPIO_IDR_IDR13_Pos)      /*!< 0x00002000 */\n#define GPIO_IDR_IDR13                       GPIO_IDR_IDR13_Msk                /*!< Port input data, bit 13 */\n#define GPIO_IDR_IDR14_Pos                   (14U)                             \n#define GPIO_IDR_IDR14_Msk                   (0x1UL << GPIO_IDR_IDR14_Pos)      /*!< 0x00004000 */\n#define GPIO_IDR_IDR14                       GPIO_IDR_IDR14_Msk                /*!< Port input data, bit 14 */\n#define GPIO_IDR_IDR15_Pos                   (15U)                             \n#define GPIO_IDR_IDR15_Msk                   (0x1UL << GPIO_IDR_IDR15_Pos)      /*!< 0x00008000 */\n#define GPIO_IDR_IDR15                       GPIO_IDR_IDR15_Msk                /*!< Port input data, bit 15 */\n\n/*******************  Bit definition for GPIO_ODR register  *******************/\n#define GPIO_ODR_ODR0_Pos                    (0U)                              \n#define GPIO_ODR_ODR0_Msk                    (0x1UL << GPIO_ODR_ODR0_Pos)       /*!< 0x00000001 */\n#define GPIO_ODR_ODR0                        GPIO_ODR_ODR0_Msk                 /*!< Port output data, bit 0 */\n#define GPIO_ODR_ODR1_Pos                    (1U)                              \n#define GPIO_ODR_ODR1_Msk                    (0x1UL << GPIO_ODR_ODR1_Pos)       /*!< 0x00000002 */\n#define GPIO_ODR_ODR1                        GPIO_ODR_ODR1_Msk                 /*!< Port output data, bit 1 */\n#define GPIO_ODR_ODR2_Pos                    (2U)                              \n#define GPIO_ODR_ODR2_Msk                    (0x1UL << GPIO_ODR_ODR2_Pos)       /*!< 0x00000004 */\n#define GPIO_ODR_ODR2                        GPIO_ODR_ODR2_Msk                 /*!< Port output data, bit 2 */\n#define GPIO_ODR_ODR3_Pos                    (3U)                              \n#define GPIO_ODR_ODR3_Msk                    (0x1UL << GPIO_ODR_ODR3_Pos)       /*!< 0x00000008 */\n#define GPIO_ODR_ODR3                        GPIO_ODR_ODR3_Msk                 /*!< Port output data, bit 3 */\n#define GPIO_ODR_ODR4_Pos                    (4U)                              \n#define GPIO_ODR_ODR4_Msk                    (0x1UL << GPIO_ODR_ODR4_Pos)       /*!< 0x00000010 */\n#define GPIO_ODR_ODR4                        GPIO_ODR_ODR4_Msk                 /*!< Port output data, bit 4 */\n#define GPIO_ODR_ODR5_Pos                    (5U)                              \n#define GPIO_ODR_ODR5_Msk                    (0x1UL << GPIO_ODR_ODR5_Pos)       /*!< 0x00000020 */\n#define GPIO_ODR_ODR5                        GPIO_ODR_ODR5_Msk                 /*!< Port output data, bit 5 */\n#define GPIO_ODR_ODR6_Pos                    (6U)                              \n#define GPIO_ODR_ODR6_Msk                    (0x1UL << GPIO_ODR_ODR6_Pos)       /*!< 0x00000040 */\n#define GPIO_ODR_ODR6                        GPIO_ODR_ODR6_Msk                 /*!< Port output data, bit 6 */\n#define GPIO_ODR_ODR7_Pos                    (7U)                              \n#define GPIO_ODR_ODR7_Msk                    (0x1UL << GPIO_ODR_ODR7_Pos)       /*!< 0x00000080 */\n#define GPIO_ODR_ODR7                        GPIO_ODR_ODR7_Msk                 /*!< Port output data, bit 7 */\n#define GPIO_ODR_ODR8_Pos                    (8U)                              \n#define GPIO_ODR_ODR8_Msk                    (0x1UL << GPIO_ODR_ODR8_Pos)       /*!< 0x00000100 */\n#define GPIO_ODR_ODR8                        GPIO_ODR_ODR8_Msk                 /*!< Port output data, bit 8 */\n#define GPIO_ODR_ODR9_Pos                    (9U)                              \n#define GPIO_ODR_ODR9_Msk                    (0x1UL << GPIO_ODR_ODR9_Pos)       /*!< 0x00000200 */\n#define GPIO_ODR_ODR9                        GPIO_ODR_ODR9_Msk                 /*!< Port output data, bit 9 */\n#define GPIO_ODR_ODR10_Pos                   (10U)                             \n#define GPIO_ODR_ODR10_Msk                   (0x1UL << GPIO_ODR_ODR10_Pos)      /*!< 0x00000400 */\n#define GPIO_ODR_ODR10                       GPIO_ODR_ODR10_Msk                /*!< Port output data, bit 10 */\n#define GPIO_ODR_ODR11_Pos                   (11U)                             \n#define GPIO_ODR_ODR11_Msk                   (0x1UL << GPIO_ODR_ODR11_Pos)      /*!< 0x00000800 */\n#define GPIO_ODR_ODR11                       GPIO_ODR_ODR11_Msk                /*!< Port output data, bit 11 */\n#define GPIO_ODR_ODR12_Pos                   (12U)                             \n#define GPIO_ODR_ODR12_Msk                   (0x1UL << GPIO_ODR_ODR12_Pos)      /*!< 0x00001000 */\n#define GPIO_ODR_ODR12                       GPIO_ODR_ODR12_Msk                /*!< Port output data, bit 12 */\n#define GPIO_ODR_ODR13_Pos                   (13U)                             \n#define GPIO_ODR_ODR13_Msk                   (0x1UL << GPIO_ODR_ODR13_Pos)      /*!< 0x00002000 */\n#define GPIO_ODR_ODR13                       GPIO_ODR_ODR13_Msk                /*!< Port output data, bit 13 */\n#define GPIO_ODR_ODR14_Pos                   (14U)                             \n#define GPIO_ODR_ODR14_Msk                   (0x1UL << GPIO_ODR_ODR14_Pos)      /*!< 0x00004000 */\n#define GPIO_ODR_ODR14                       GPIO_ODR_ODR14_Msk                /*!< Port output data, bit 14 */\n#define GPIO_ODR_ODR15_Pos                   (15U)                             \n#define GPIO_ODR_ODR15_Msk                   (0x1UL << GPIO_ODR_ODR15_Pos)      /*!< 0x00008000 */\n#define GPIO_ODR_ODR15                       GPIO_ODR_ODR15_Msk                /*!< Port output data, bit 15 */\n\n/******************  Bit definition for GPIO_BSRR register  *******************/\n#define GPIO_BSRR_BS0_Pos                    (0U)                              \n#define GPIO_BSRR_BS0_Msk                    (0x1UL << GPIO_BSRR_BS0_Pos)       /*!< 0x00000001 */\n#define GPIO_BSRR_BS0                        GPIO_BSRR_BS0_Msk                 /*!< Port x Set bit 0 */\n#define GPIO_BSRR_BS1_Pos                    (1U)                              \n#define GPIO_BSRR_BS1_Msk                    (0x1UL << GPIO_BSRR_BS1_Pos)       /*!< 0x00000002 */\n#define GPIO_BSRR_BS1                        GPIO_BSRR_BS1_Msk                 /*!< Port x Set bit 1 */\n#define GPIO_BSRR_BS2_Pos                    (2U)                              \n#define GPIO_BSRR_BS2_Msk                    (0x1UL << GPIO_BSRR_BS2_Pos)       /*!< 0x00000004 */\n#define GPIO_BSRR_BS2                        GPIO_BSRR_BS2_Msk                 /*!< Port x Set bit 2 */\n#define GPIO_BSRR_BS3_Pos                    (3U)                              \n#define GPIO_BSRR_BS3_Msk                    (0x1UL << GPIO_BSRR_BS3_Pos)       /*!< 0x00000008 */\n#define GPIO_BSRR_BS3                        GPIO_BSRR_BS3_Msk                 /*!< Port x Set bit 3 */\n#define GPIO_BSRR_BS4_Pos                    (4U)                              \n#define GPIO_BSRR_BS4_Msk                    (0x1UL << GPIO_BSRR_BS4_Pos)       /*!< 0x00000010 */\n#define GPIO_BSRR_BS4                        GPIO_BSRR_BS4_Msk                 /*!< Port x Set bit 4 */\n#define GPIO_BSRR_BS5_Pos                    (5U)                              \n#define GPIO_BSRR_BS5_Msk                    (0x1UL << GPIO_BSRR_BS5_Pos)       /*!< 0x00000020 */\n#define GPIO_BSRR_BS5                        GPIO_BSRR_BS5_Msk                 /*!< Port x Set bit 5 */\n#define GPIO_BSRR_BS6_Pos                    (6U)                              \n#define GPIO_BSRR_BS6_Msk                    (0x1UL << GPIO_BSRR_BS6_Pos)       /*!< 0x00000040 */\n#define GPIO_BSRR_BS6                        GPIO_BSRR_BS6_Msk                 /*!< Port x Set bit 6 */\n#define GPIO_BSRR_BS7_Pos                    (7U)                              \n#define GPIO_BSRR_BS7_Msk                    (0x1UL << GPIO_BSRR_BS7_Pos)       /*!< 0x00000080 */\n#define GPIO_BSRR_BS7                        GPIO_BSRR_BS7_Msk                 /*!< Port x Set bit 7 */\n#define GPIO_BSRR_BS8_Pos                    (8U)                              \n#define GPIO_BSRR_BS8_Msk                    (0x1UL << GPIO_BSRR_BS8_Pos)       /*!< 0x00000100 */\n#define GPIO_BSRR_BS8                        GPIO_BSRR_BS8_Msk                 /*!< Port x Set bit 8 */\n#define GPIO_BSRR_BS9_Pos                    (9U)                              \n#define GPIO_BSRR_BS9_Msk                    (0x1UL << GPIO_BSRR_BS9_Pos)       /*!< 0x00000200 */\n#define GPIO_BSRR_BS9                        GPIO_BSRR_BS9_Msk                 /*!< Port x Set bit 9 */\n#define GPIO_BSRR_BS10_Pos                   (10U)                             \n#define GPIO_BSRR_BS10_Msk                   (0x1UL << GPIO_BSRR_BS10_Pos)      /*!< 0x00000400 */\n#define GPIO_BSRR_BS10                       GPIO_BSRR_BS10_Msk                /*!< Port x Set bit 10 */\n#define GPIO_BSRR_BS11_Pos                   (11U)                             \n#define GPIO_BSRR_BS11_Msk                   (0x1UL << GPIO_BSRR_BS11_Pos)      /*!< 0x00000800 */\n#define GPIO_BSRR_BS11                       GPIO_BSRR_BS11_Msk                /*!< Port x Set bit 11 */\n#define GPIO_BSRR_BS12_Pos                   (12U)                             \n#define GPIO_BSRR_BS12_Msk                   (0x1UL << GPIO_BSRR_BS12_Pos)      /*!< 0x00001000 */\n#define GPIO_BSRR_BS12                       GPIO_BSRR_BS12_Msk                /*!< Port x Set bit 12 */\n#define GPIO_BSRR_BS13_Pos                   (13U)                             \n#define GPIO_BSRR_BS13_Msk                   (0x1UL << GPIO_BSRR_BS13_Pos)      /*!< 0x00002000 */\n#define GPIO_BSRR_BS13                       GPIO_BSRR_BS13_Msk                /*!< Port x Set bit 13 */\n#define GPIO_BSRR_BS14_Pos                   (14U)                             \n#define GPIO_BSRR_BS14_Msk                   (0x1UL << GPIO_BSRR_BS14_Pos)      /*!< 0x00004000 */\n#define GPIO_BSRR_BS14                       GPIO_BSRR_BS14_Msk                /*!< Port x Set bit 14 */\n#define GPIO_BSRR_BS15_Pos                   (15U)                             \n#define GPIO_BSRR_BS15_Msk                   (0x1UL << GPIO_BSRR_BS15_Pos)      /*!< 0x00008000 */\n#define GPIO_BSRR_BS15                       GPIO_BSRR_BS15_Msk                /*!< Port x Set bit 15 */\n\n#define GPIO_BSRR_BR0_Pos                    (16U)                             \n#define GPIO_BSRR_BR0_Msk                    (0x1UL << GPIO_BSRR_BR0_Pos)       /*!< 0x00010000 */\n#define GPIO_BSRR_BR0                        GPIO_BSRR_BR0_Msk                 /*!< Port x Reset bit 0 */\n#define GPIO_BSRR_BR1_Pos                    (17U)                             \n#define GPIO_BSRR_BR1_Msk                    (0x1UL << GPIO_BSRR_BR1_Pos)       /*!< 0x00020000 */\n#define GPIO_BSRR_BR1                        GPIO_BSRR_BR1_Msk                 /*!< Port x Reset bit 1 */\n#define GPIO_BSRR_BR2_Pos                    (18U)                             \n#define GPIO_BSRR_BR2_Msk                    (0x1UL << GPIO_BSRR_BR2_Pos)       /*!< 0x00040000 */\n#define GPIO_BSRR_BR2                        GPIO_BSRR_BR2_Msk                 /*!< Port x Reset bit 2 */\n#define GPIO_BSRR_BR3_Pos                    (19U)                             \n#define GPIO_BSRR_BR3_Msk                    (0x1UL << GPIO_BSRR_BR3_Pos)       /*!< 0x00080000 */\n#define GPIO_BSRR_BR3                        GPIO_BSRR_BR3_Msk                 /*!< Port x Reset bit 3 */\n#define GPIO_BSRR_BR4_Pos                    (20U)                             \n#define GPIO_BSRR_BR4_Msk                    (0x1UL << GPIO_BSRR_BR4_Pos)       /*!< 0x00100000 */\n#define GPIO_BSRR_BR4                        GPIO_BSRR_BR4_Msk                 /*!< Port x Reset bit 4 */\n#define GPIO_BSRR_BR5_Pos                    (21U)                             \n#define GPIO_BSRR_BR5_Msk                    (0x1UL << GPIO_BSRR_BR5_Pos)       /*!< 0x00200000 */\n#define GPIO_BSRR_BR5                        GPIO_BSRR_BR5_Msk                 /*!< Port x Reset bit 5 */\n#define GPIO_BSRR_BR6_Pos                    (22U)                             \n#define GPIO_BSRR_BR6_Msk                    (0x1UL << GPIO_BSRR_BR6_Pos)       /*!< 0x00400000 */\n#define GPIO_BSRR_BR6                        GPIO_BSRR_BR6_Msk                 /*!< Port x Reset bit 6 */\n#define GPIO_BSRR_BR7_Pos                    (23U)                             \n#define GPIO_BSRR_BR7_Msk                    (0x1UL << GPIO_BSRR_BR7_Pos)       /*!< 0x00800000 */\n#define GPIO_BSRR_BR7                        GPIO_BSRR_BR7_Msk                 /*!< Port x Reset bit 7 */\n#define GPIO_BSRR_BR8_Pos                    (24U)                             \n#define GPIO_BSRR_BR8_Msk                    (0x1UL << GPIO_BSRR_BR8_Pos)       /*!< 0x01000000 */\n#define GPIO_BSRR_BR8                        GPIO_BSRR_BR8_Msk                 /*!< Port x Reset bit 8 */\n#define GPIO_BSRR_BR9_Pos                    (25U)                             \n#define GPIO_BSRR_BR9_Msk                    (0x1UL << GPIO_BSRR_BR9_Pos)       /*!< 0x02000000 */\n#define GPIO_BSRR_BR9                        GPIO_BSRR_BR9_Msk                 /*!< Port x Reset bit 9 */\n#define GPIO_BSRR_BR10_Pos                   (26U)                             \n#define GPIO_BSRR_BR10_Msk                   (0x1UL << GPIO_BSRR_BR10_Pos)      /*!< 0x04000000 */\n#define GPIO_BSRR_BR10                       GPIO_BSRR_BR10_Msk                /*!< Port x Reset bit 10 */\n#define GPIO_BSRR_BR11_Pos                   (27U)                             \n#define GPIO_BSRR_BR11_Msk                   (0x1UL << GPIO_BSRR_BR11_Pos)      /*!< 0x08000000 */\n#define GPIO_BSRR_BR11                       GPIO_BSRR_BR11_Msk                /*!< Port x Reset bit 11 */\n#define GPIO_BSRR_BR12_Pos                   (28U)                             \n#define GPIO_BSRR_BR12_Msk                   (0x1UL << GPIO_BSRR_BR12_Pos)      /*!< 0x10000000 */\n#define GPIO_BSRR_BR12                       GPIO_BSRR_BR12_Msk                /*!< Port x Reset bit 12 */\n#define GPIO_BSRR_BR13_Pos                   (29U)                             \n#define GPIO_BSRR_BR13_Msk                   (0x1UL << GPIO_BSRR_BR13_Pos)      /*!< 0x20000000 */\n#define GPIO_BSRR_BR13                       GPIO_BSRR_BR13_Msk                /*!< Port x Reset bit 13 */\n#define GPIO_BSRR_BR14_Pos                   (30U)                             \n#define GPIO_BSRR_BR14_Msk                   (0x1UL << GPIO_BSRR_BR14_Pos)      /*!< 0x40000000 */\n#define GPIO_BSRR_BR14                       GPIO_BSRR_BR14_Msk                /*!< Port x Reset bit 14 */\n#define GPIO_BSRR_BR15_Pos                   (31U)                             \n#define GPIO_BSRR_BR15_Msk                   (0x1UL << GPIO_BSRR_BR15_Pos)      /*!< 0x80000000 */\n#define GPIO_BSRR_BR15                       GPIO_BSRR_BR15_Msk                /*!< Port x Reset bit 15 */\n\n/*******************  Bit definition for GPIO_BRR register  *******************/\n#define GPIO_BRR_BR0_Pos                     (0U)                              \n#define GPIO_BRR_BR0_Msk                     (0x1UL << GPIO_BRR_BR0_Pos)        /*!< 0x00000001 */\n#define GPIO_BRR_BR0                         GPIO_BRR_BR0_Msk                  /*!< Port x Reset bit 0 */\n#define GPIO_BRR_BR1_Pos                     (1U)                              \n#define GPIO_BRR_BR1_Msk                     (0x1UL << GPIO_BRR_BR1_Pos)        /*!< 0x00000002 */\n#define GPIO_BRR_BR1                         GPIO_BRR_BR1_Msk                  /*!< Port x Reset bit 1 */\n#define GPIO_BRR_BR2_Pos                     (2U)                              \n#define GPIO_BRR_BR2_Msk                     (0x1UL << GPIO_BRR_BR2_Pos)        /*!< 0x00000004 */\n#define GPIO_BRR_BR2                         GPIO_BRR_BR2_Msk                  /*!< Port x Reset bit 2 */\n#define GPIO_BRR_BR3_Pos                     (3U)                              \n#define GPIO_BRR_BR3_Msk                     (0x1UL << GPIO_BRR_BR3_Pos)        /*!< 0x00000008 */\n#define GPIO_BRR_BR3                         GPIO_BRR_BR3_Msk                  /*!< Port x Reset bit 3 */\n#define GPIO_BRR_BR4_Pos                     (4U)                              \n#define GPIO_BRR_BR4_Msk                     (0x1UL << GPIO_BRR_BR4_Pos)        /*!< 0x00000010 */\n#define GPIO_BRR_BR4                         GPIO_BRR_BR4_Msk                  /*!< Port x Reset bit 4 */\n#define GPIO_BRR_BR5_Pos                     (5U)                              \n#define GPIO_BRR_BR5_Msk                     (0x1UL << GPIO_BRR_BR5_Pos)        /*!< 0x00000020 */\n#define GPIO_BRR_BR5                         GPIO_BRR_BR5_Msk                  /*!< Port x Reset bit 5 */\n#define GPIO_BRR_BR6_Pos                     (6U)                              \n#define GPIO_BRR_BR6_Msk                     (0x1UL << GPIO_BRR_BR6_Pos)        /*!< 0x00000040 */\n#define GPIO_BRR_BR6                         GPIO_BRR_BR6_Msk                  /*!< Port x Reset bit 6 */\n#define GPIO_BRR_BR7_Pos                     (7U)                              \n#define GPIO_BRR_BR7_Msk                     (0x1UL << GPIO_BRR_BR7_Pos)        /*!< 0x00000080 */\n#define GPIO_BRR_BR7                         GPIO_BRR_BR7_Msk                  /*!< Port x Reset bit 7 */\n#define GPIO_BRR_BR8_Pos                     (8U)                              \n#define GPIO_BRR_BR8_Msk                     (0x1UL << GPIO_BRR_BR8_Pos)        /*!< 0x00000100 */\n#define GPIO_BRR_BR8                         GPIO_BRR_BR8_Msk                  /*!< Port x Reset bit 8 */\n#define GPIO_BRR_BR9_Pos                     (9U)                              \n#define GPIO_BRR_BR9_Msk                     (0x1UL << GPIO_BRR_BR9_Pos)        /*!< 0x00000200 */\n#define GPIO_BRR_BR9                         GPIO_BRR_BR9_Msk                  /*!< Port x Reset bit 9 */\n#define GPIO_BRR_BR10_Pos                    (10U)                             \n#define GPIO_BRR_BR10_Msk                    (0x1UL << GPIO_BRR_BR10_Pos)       /*!< 0x00000400 */\n#define GPIO_BRR_BR10                        GPIO_BRR_BR10_Msk                 /*!< Port x Reset bit 10 */\n#define GPIO_BRR_BR11_Pos                    (11U)                             \n#define GPIO_BRR_BR11_Msk                    (0x1UL << GPIO_BRR_BR11_Pos)       /*!< 0x00000800 */\n#define GPIO_BRR_BR11                        GPIO_BRR_BR11_Msk                 /*!< Port x Reset bit 11 */\n#define GPIO_BRR_BR12_Pos                    (12U)                             \n#define GPIO_BRR_BR12_Msk                    (0x1UL << GPIO_BRR_BR12_Pos)       /*!< 0x00001000 */\n#define GPIO_BRR_BR12                        GPIO_BRR_BR12_Msk                 /*!< Port x Reset bit 12 */\n#define GPIO_BRR_BR13_Pos                    (13U)                             \n#define GPIO_BRR_BR13_Msk                    (0x1UL << GPIO_BRR_BR13_Pos)       /*!< 0x00002000 */\n#define GPIO_BRR_BR13                        GPIO_BRR_BR13_Msk                 /*!< Port x Reset bit 13 */\n#define GPIO_BRR_BR14_Pos                    (14U)                             \n#define GPIO_BRR_BR14_Msk                    (0x1UL << GPIO_BRR_BR14_Pos)       /*!< 0x00004000 */\n#define GPIO_BRR_BR14                        GPIO_BRR_BR14_Msk                 /*!< Port x Reset bit 14 */\n#define GPIO_BRR_BR15_Pos                    (15U)                             \n#define GPIO_BRR_BR15_Msk                    (0x1UL << GPIO_BRR_BR15_Pos)       /*!< 0x00008000 */\n#define GPIO_BRR_BR15                        GPIO_BRR_BR15_Msk                 /*!< Port x Reset bit 15 */\n\n/******************  Bit definition for GPIO_LCKR register  *******************/\n#define GPIO_LCKR_LCK0_Pos                   (0U)                              \n#define GPIO_LCKR_LCK0_Msk                   (0x1UL << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */\n#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk                /*!< Port x Lock bit 0 */\n#define GPIO_LCKR_LCK1_Pos                   (1U)                              \n#define GPIO_LCKR_LCK1_Msk                   (0x1UL << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */\n#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk                /*!< Port x Lock bit 1 */\n#define GPIO_LCKR_LCK2_Pos                   (2U)                              \n#define GPIO_LCKR_LCK2_Msk                   (0x1UL << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */\n#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk                /*!< Port x Lock bit 2 */\n#define GPIO_LCKR_LCK3_Pos                   (3U)                              \n#define GPIO_LCKR_LCK3_Msk                   (0x1UL << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */\n#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk                /*!< Port x Lock bit 3 */\n#define GPIO_LCKR_LCK4_Pos                   (4U)                              \n#define GPIO_LCKR_LCK4_Msk                   (0x1UL << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */\n#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk                /*!< Port x Lock bit 4 */\n#define GPIO_LCKR_LCK5_Pos                   (5U)                              \n#define GPIO_LCKR_LCK5_Msk                   (0x1UL << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */\n#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk                /*!< Port x Lock bit 5 */\n#define GPIO_LCKR_LCK6_Pos                   (6U)                              \n#define GPIO_LCKR_LCK6_Msk                   (0x1UL << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */\n#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk                /*!< Port x Lock bit 6 */\n#define GPIO_LCKR_LCK7_Pos                   (7U)                              \n#define GPIO_LCKR_LCK7_Msk                   (0x1UL << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */\n#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk                /*!< Port x Lock bit 7 */\n#define GPIO_LCKR_LCK8_Pos                   (8U)                              \n#define GPIO_LCKR_LCK8_Msk                   (0x1UL << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */\n#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk                /*!< Port x Lock bit 8 */\n#define GPIO_LCKR_LCK9_Pos                   (9U)                              \n#define GPIO_LCKR_LCK9_Msk                   (0x1UL << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */\n#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk                /*!< Port x Lock bit 9 */\n#define GPIO_LCKR_LCK10_Pos                  (10U)                             \n#define GPIO_LCKR_LCK10_Msk                  (0x1UL << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */\n#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk               /*!< Port x Lock bit 10 */\n#define GPIO_LCKR_LCK11_Pos                  (11U)                             \n#define GPIO_LCKR_LCK11_Msk                  (0x1UL << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */\n#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk               /*!< Port x Lock bit 11 */\n#define GPIO_LCKR_LCK12_Pos                  (12U)                             \n#define GPIO_LCKR_LCK12_Msk                  (0x1UL << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */\n#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk               /*!< Port x Lock bit 12 */\n#define GPIO_LCKR_LCK13_Pos                  (13U)                             \n#define GPIO_LCKR_LCK13_Msk                  (0x1UL << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */\n#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk               /*!< Port x Lock bit 13 */\n#define GPIO_LCKR_LCK14_Pos                  (14U)                             \n#define GPIO_LCKR_LCK14_Msk                  (0x1UL << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */\n#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk               /*!< Port x Lock bit 14 */\n#define GPIO_LCKR_LCK15_Pos                  (15U)                             \n#define GPIO_LCKR_LCK15_Msk                  (0x1UL << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */\n#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk               /*!< Port x Lock bit 15 */\n#define GPIO_LCKR_LCKK_Pos                   (16U)                             \n#define GPIO_LCKR_LCKK_Msk                   (0x1UL << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */\n#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                /*!< Lock key */\n\n/*----------------------------------------------------------------------------*/\n\n/******************  Bit definition for AFIO_EVCR register  *******************/\n#define AFIO_EVCR_PIN_Pos                    (0U)                              \n#define AFIO_EVCR_PIN_Msk                    (0xFUL << AFIO_EVCR_PIN_Pos)       /*!< 0x0000000F */\n#define AFIO_EVCR_PIN                        AFIO_EVCR_PIN_Msk                 /*!< PIN[3:0] bits (Pin selection) */\n#define AFIO_EVCR_PIN_0                      (0x1UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000001 */\n#define AFIO_EVCR_PIN_1                      (0x2UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000002 */\n#define AFIO_EVCR_PIN_2                      (0x4UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000004 */\n#define AFIO_EVCR_PIN_3                      (0x8UL << AFIO_EVCR_PIN_Pos)       /*!< 0x00000008 */\n\n/*!< PIN configuration */\n#define AFIO_EVCR_PIN_PX0                    0x00000000U                       /*!< Pin 0 selected */\n#define AFIO_EVCR_PIN_PX1_Pos                (0U)                              \n#define AFIO_EVCR_PIN_PX1_Msk                (0x1UL << AFIO_EVCR_PIN_PX1_Pos)   /*!< 0x00000001 */\n#define AFIO_EVCR_PIN_PX1                    AFIO_EVCR_PIN_PX1_Msk             /*!< Pin 1 selected */\n#define AFIO_EVCR_PIN_PX2_Pos                (1U)                              \n#define AFIO_EVCR_PIN_PX2_Msk                (0x1UL << AFIO_EVCR_PIN_PX2_Pos)   /*!< 0x00000002 */\n#define AFIO_EVCR_PIN_PX2                    AFIO_EVCR_PIN_PX2_Msk             /*!< Pin 2 selected */\n#define AFIO_EVCR_PIN_PX3_Pos                (0U)                              \n#define AFIO_EVCR_PIN_PX3_Msk                (0x3UL << AFIO_EVCR_PIN_PX3_Pos)   /*!< 0x00000003 */\n#define AFIO_EVCR_PIN_PX3                    AFIO_EVCR_PIN_PX3_Msk             /*!< Pin 3 selected */\n#define AFIO_EVCR_PIN_PX4_Pos                (2U)                              \n#define AFIO_EVCR_PIN_PX4_Msk                (0x1UL << AFIO_EVCR_PIN_PX4_Pos)   /*!< 0x00000004 */\n#define AFIO_EVCR_PIN_PX4                    AFIO_EVCR_PIN_PX4_Msk             /*!< Pin 4 selected */\n#define AFIO_EVCR_PIN_PX5_Pos                (0U)                              \n#define AFIO_EVCR_PIN_PX5_Msk                (0x5UL << AFIO_EVCR_PIN_PX5_Pos)   /*!< 0x00000005 */\n#define AFIO_EVCR_PIN_PX5                    AFIO_EVCR_PIN_PX5_Msk             /*!< Pin 5 selected */\n#define AFIO_EVCR_PIN_PX6_Pos                (1U)                              \n#define AFIO_EVCR_PIN_PX6_Msk                (0x3UL << AFIO_EVCR_PIN_PX6_Pos)   /*!< 0x00000006 */\n#define AFIO_EVCR_PIN_PX6                    AFIO_EVCR_PIN_PX6_Msk             /*!< Pin 6 selected */\n#define AFIO_EVCR_PIN_PX7_Pos                (0U)                              \n#define AFIO_EVCR_PIN_PX7_Msk                (0x7UL << AFIO_EVCR_PIN_PX7_Pos)   /*!< 0x00000007 */\n#define AFIO_EVCR_PIN_PX7                    AFIO_EVCR_PIN_PX7_Msk             /*!< Pin 7 selected */\n#define AFIO_EVCR_PIN_PX8_Pos                (3U)                              \n#define AFIO_EVCR_PIN_PX8_Msk                (0x1UL << AFIO_EVCR_PIN_PX8_Pos)   /*!< 0x00000008 */\n#define AFIO_EVCR_PIN_PX8                    AFIO_EVCR_PIN_PX8_Msk             /*!< Pin 8 selected */\n#define AFIO_EVCR_PIN_PX9_Pos                (0U)                              \n#define AFIO_EVCR_PIN_PX9_Msk                (0x9UL << AFIO_EVCR_PIN_PX9_Pos)   /*!< 0x00000009 */\n#define AFIO_EVCR_PIN_PX9                    AFIO_EVCR_PIN_PX9_Msk             /*!< Pin 9 selected */\n#define AFIO_EVCR_PIN_PX10_Pos               (1U)                              \n#define AFIO_EVCR_PIN_PX10_Msk               (0x5UL << AFIO_EVCR_PIN_PX10_Pos)  /*!< 0x0000000A */\n#define AFIO_EVCR_PIN_PX10                   AFIO_EVCR_PIN_PX10_Msk            /*!< Pin 10 selected */\n#define AFIO_EVCR_PIN_PX11_Pos               (0U)                              \n#define AFIO_EVCR_PIN_PX11_Msk               (0xBUL << AFIO_EVCR_PIN_PX11_Pos)  /*!< 0x0000000B */\n#define AFIO_EVCR_PIN_PX11                   AFIO_EVCR_PIN_PX11_Msk            /*!< Pin 11 selected */\n#define AFIO_EVCR_PIN_PX12_Pos               (2U)                              \n#define AFIO_EVCR_PIN_PX12_Msk               (0x3UL << AFIO_EVCR_PIN_PX12_Pos)  /*!< 0x0000000C */\n#define AFIO_EVCR_PIN_PX12                   AFIO_EVCR_PIN_PX12_Msk            /*!< Pin 12 selected */\n#define AFIO_EVCR_PIN_PX13_Pos               (0U)                              \n#define AFIO_EVCR_PIN_PX13_Msk               (0xDUL << AFIO_EVCR_PIN_PX13_Pos)  /*!< 0x0000000D */\n#define AFIO_EVCR_PIN_PX13                   AFIO_EVCR_PIN_PX13_Msk            /*!< Pin 13 selected */\n#define AFIO_EVCR_PIN_PX14_Pos               (1U)                              \n#define AFIO_EVCR_PIN_PX14_Msk               (0x7UL << AFIO_EVCR_PIN_PX14_Pos)  /*!< 0x0000000E */\n#define AFIO_EVCR_PIN_PX14                   AFIO_EVCR_PIN_PX14_Msk            /*!< Pin 14 selected */\n#define AFIO_EVCR_PIN_PX15_Pos               (0U)                              \n#define AFIO_EVCR_PIN_PX15_Msk               (0xFUL << AFIO_EVCR_PIN_PX15_Pos)  /*!< 0x0000000F */\n#define AFIO_EVCR_PIN_PX15                   AFIO_EVCR_PIN_PX15_Msk            /*!< Pin 15 selected */\n\n#define AFIO_EVCR_PORT_Pos                   (4U)                              \n#define AFIO_EVCR_PORT_Msk                   (0x7UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000070 */\n#define AFIO_EVCR_PORT                       AFIO_EVCR_PORT_Msk                /*!< PORT[2:0] bits (Port selection) */\n#define AFIO_EVCR_PORT_0                     (0x1UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000010 */\n#define AFIO_EVCR_PORT_1                     (0x2UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000020 */\n#define AFIO_EVCR_PORT_2                     (0x4UL << AFIO_EVCR_PORT_Pos)      /*!< 0x00000040 */\n\n/*!< PORT configuration */\n#define AFIO_EVCR_PORT_PA                    0x00000000                        /*!< Port A selected */\n#define AFIO_EVCR_PORT_PB_Pos                (4U)                              \n#define AFIO_EVCR_PORT_PB_Msk                (0x1UL << AFIO_EVCR_PORT_PB_Pos)   /*!< 0x00000010 */\n#define AFIO_EVCR_PORT_PB                    AFIO_EVCR_PORT_PB_Msk             /*!< Port B selected */\n#define AFIO_EVCR_PORT_PC_Pos                (5U)                              \n#define AFIO_EVCR_PORT_PC_Msk                (0x1UL << AFIO_EVCR_PORT_PC_Pos)   /*!< 0x00000020 */\n#define AFIO_EVCR_PORT_PC                    AFIO_EVCR_PORT_PC_Msk             /*!< Port C selected */\n#define AFIO_EVCR_PORT_PD_Pos                (4U)                              \n#define AFIO_EVCR_PORT_PD_Msk                (0x3UL << AFIO_EVCR_PORT_PD_Pos)   /*!< 0x00000030 */\n#define AFIO_EVCR_PORT_PD                    AFIO_EVCR_PORT_PD_Msk             /*!< Port D selected */\n#define AFIO_EVCR_PORT_PE_Pos                (6U)                              \n#define AFIO_EVCR_PORT_PE_Msk                (0x1UL << AFIO_EVCR_PORT_PE_Pos)   /*!< 0x00000040 */\n#define AFIO_EVCR_PORT_PE                    AFIO_EVCR_PORT_PE_Msk             /*!< Port E selected */\n\n#define AFIO_EVCR_EVOE_Pos                   (7U)                              \n#define AFIO_EVCR_EVOE_Msk                   (0x1UL << AFIO_EVCR_EVOE_Pos)      /*!< 0x00000080 */\n#define AFIO_EVCR_EVOE                       AFIO_EVCR_EVOE_Msk                /*!< Event Output Enable */\n\n/******************  Bit definition for AFIO_MAPR register  *******************/\n#define AFIO_MAPR_SPI1_REMAP_Pos             (0U)                              \n#define AFIO_MAPR_SPI1_REMAP_Msk             (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */\n#define AFIO_MAPR_SPI1_REMAP                 AFIO_MAPR_SPI1_REMAP_Msk          /*!< SPI1 remapping */\n#define AFIO_MAPR_I2C1_REMAP_Pos             (1U)                              \n#define AFIO_MAPR_I2C1_REMAP_Msk             (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */\n#define AFIO_MAPR_I2C1_REMAP                 AFIO_MAPR_I2C1_REMAP_Msk          /*!< I2C1 remapping */\n#define AFIO_MAPR_USART1_REMAP_Pos           (2U)                              \n#define AFIO_MAPR_USART1_REMAP_Msk           (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */\n#define AFIO_MAPR_USART1_REMAP               AFIO_MAPR_USART1_REMAP_Msk        /*!< USART1 remapping */\n#define AFIO_MAPR_USART2_REMAP_Pos           (3U)                              \n#define AFIO_MAPR_USART2_REMAP_Msk           (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */\n#define AFIO_MAPR_USART2_REMAP               AFIO_MAPR_USART2_REMAP_Msk        /*!< USART2 remapping */\n\n#define AFIO_MAPR_USART3_REMAP_Pos           (4U)                              \n#define AFIO_MAPR_USART3_REMAP_Msk           (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */\n#define AFIO_MAPR_USART3_REMAP               AFIO_MAPR_USART3_REMAP_Msk        /*!< USART3_REMAP[1:0] bits (USART3 remapping) */\n#define AFIO_MAPR_USART3_REMAP_0             (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */\n#define AFIO_MAPR_USART3_REMAP_1             (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */\n\n/* USART3_REMAP configuration */\n#define AFIO_MAPR_USART3_REMAP_NOREMAP       0x00000000U                          /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)                           \n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */\n#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP  AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */\n#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)                              \n#define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */\n#define AFIO_MAPR_USART3_REMAP_FULLREMAP     AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */\n\n#define AFIO_MAPR_TIM1_REMAP_Pos             (6U)                              \n#define AFIO_MAPR_TIM1_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */\n#define AFIO_MAPR_TIM1_REMAP                 AFIO_MAPR_TIM1_REMAP_Msk          /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */\n#define AFIO_MAPR_TIM1_REMAP_0               (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */\n#define AFIO_MAPR_TIM1_REMAP_1               (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */\n\n/*!< TIM1_REMAP configuration */\n#define AFIO_MAPR_TIM1_REMAP_NOREMAP         0x00000000U                          /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */\n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)                             \n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */\n#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP    AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */\n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos   (6U)                              \n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */\n#define AFIO_MAPR_TIM1_REMAP_FULLREMAP       AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */\n\n#define AFIO_MAPR_TIM2_REMAP_Pos             (8U)                              \n#define AFIO_MAPR_TIM2_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */\n#define AFIO_MAPR_TIM2_REMAP                 AFIO_MAPR_TIM2_REMAP_Msk          /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */\n#define AFIO_MAPR_TIM2_REMAP_0               (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */\n#define AFIO_MAPR_TIM2_REMAP_1               (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */\n\n/*!< TIM2_REMAP configuration */\n#define AFIO_MAPR_TIM2_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)                            \n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)                            \n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */\n#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */\n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos   (8U)                              \n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */\n#define AFIO_MAPR_TIM2_REMAP_FULLREMAP       AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */\n\n#define AFIO_MAPR_TIM3_REMAP_Pos             (10U)                             \n#define AFIO_MAPR_TIM3_REMAP_Msk             (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */\n#define AFIO_MAPR_TIM3_REMAP                 AFIO_MAPR_TIM3_REMAP_Msk          /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */\n#define AFIO_MAPR_TIM3_REMAP_0               (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */\n#define AFIO_MAPR_TIM3_REMAP_1               (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */\n\n/*!< TIM3_REMAP configuration */\n#define AFIO_MAPR_TIM3_REMAP_NOREMAP         0x00000000U                          /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)                            \n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */\n#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP    AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */\n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos   (10U)                             \n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk   (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */\n#define AFIO_MAPR_TIM3_REMAP_FULLREMAP       AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */\n\n#define AFIO_MAPR_TIM4_REMAP_Pos             (12U)                             \n#define AFIO_MAPR_TIM4_REMAP_Msk             (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */\n#define AFIO_MAPR_TIM4_REMAP                 AFIO_MAPR_TIM4_REMAP_Msk          /*!< TIM4_REMAP bit (TIM4 remapping) */\n\n#define AFIO_MAPR_CAN_REMAP_Pos              (13U)                             \n#define AFIO_MAPR_CAN_REMAP_Msk              (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */\n#define AFIO_MAPR_CAN_REMAP                  AFIO_MAPR_CAN_REMAP_Msk           /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */\n#define AFIO_MAPR_CAN_REMAP_0                (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */\n#define AFIO_MAPR_CAN_REMAP_1                (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */\n\n/*!< CAN_REMAP configuration */\n#define AFIO_MAPR_CAN_REMAP_REMAP1           0x00000000U                          /*!< CANRX mapped to PA11, CANTX mapped to PA12 */\n#define AFIO_MAPR_CAN_REMAP_REMAP2_Pos       (14U)                             \n#define AFIO_MAPR_CAN_REMAP_REMAP2_Msk       (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */\n#define AFIO_MAPR_CAN_REMAP_REMAP2           AFIO_MAPR_CAN_REMAP_REMAP2_Msk    /*!< CANRX mapped to PB8, CANTX mapped to PB9 */\n#define AFIO_MAPR_CAN_REMAP_REMAP3_Pos       (13U)                             \n#define AFIO_MAPR_CAN_REMAP_REMAP3_Msk       (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */\n#define AFIO_MAPR_CAN_REMAP_REMAP3           AFIO_MAPR_CAN_REMAP_REMAP3_Msk    /*!< CANRX mapped to PD0, CANTX mapped to PD1 */\n\n#define AFIO_MAPR_PD01_REMAP_Pos             (15U)                             \n#define AFIO_MAPR_PD01_REMAP_Msk             (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */\n#define AFIO_MAPR_PD01_REMAP                 AFIO_MAPR_PD01_REMAP_Msk          /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */\n\n/*!< SWJ_CFG configuration */\n#define AFIO_MAPR_SWJ_CFG_Pos                (24U)                             \n#define AFIO_MAPR_SWJ_CFG_Msk                (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x07000000 */\n#define AFIO_MAPR_SWJ_CFG                    AFIO_MAPR_SWJ_CFG_Msk             /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */\n#define AFIO_MAPR_SWJ_CFG_0                  (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x01000000 */\n#define AFIO_MAPR_SWJ_CFG_1                  (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x02000000 */\n#define AFIO_MAPR_SWJ_CFG_2                  (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)   /*!< 0x04000000 */\n\n#define AFIO_MAPR_SWJ_CFG_RESET              0x00000000U                          /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */\n#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos       (24U)                             \n#define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk       (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */\n#define AFIO_MAPR_SWJ_CFG_NOJNTRST           AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk    /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */\n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos    (25U)                             \n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk    (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */\n#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE        AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */\n#define AFIO_MAPR_SWJ_CFG_DISABLE_Pos        (26U)                             \n#define AFIO_MAPR_SWJ_CFG_DISABLE_Msk        (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */\n#define AFIO_MAPR_SWJ_CFG_DISABLE            AFIO_MAPR_SWJ_CFG_DISABLE_Msk     /*!< JTAG-DP Disabled and SW-DP Disabled */\n\n\n/*****************  Bit definition for AFIO_EXTICR1 register  *****************/\n#define AFIO_EXTICR1_EXTI0_Pos               (0U)                              \n#define AFIO_EXTICR1_EXTI0_Msk               (0xFUL << AFIO_EXTICR1_EXTI0_Pos)  /*!< 0x0000000F */\n#define AFIO_EXTICR1_EXTI0                   AFIO_EXTICR1_EXTI0_Msk            /*!< EXTI 0 configuration */\n#define AFIO_EXTICR1_EXTI1_Pos               (4U)                              \n#define AFIO_EXTICR1_EXTI1_Msk               (0xFUL << AFIO_EXTICR1_EXTI1_Pos)  /*!< 0x000000F0 */\n#define AFIO_EXTICR1_EXTI1                   AFIO_EXTICR1_EXTI1_Msk            /*!< EXTI 1 configuration */\n#define AFIO_EXTICR1_EXTI2_Pos               (8U)                              \n#define AFIO_EXTICR1_EXTI2_Msk               (0xFUL << AFIO_EXTICR1_EXTI2_Pos)  /*!< 0x00000F00 */\n#define AFIO_EXTICR1_EXTI2                   AFIO_EXTICR1_EXTI2_Msk            /*!< EXTI 2 configuration */\n#define AFIO_EXTICR1_EXTI3_Pos               (12U)                             \n#define AFIO_EXTICR1_EXTI3_Msk               (0xFUL << AFIO_EXTICR1_EXTI3_Pos)  /*!< 0x0000F000 */\n#define AFIO_EXTICR1_EXTI3                   AFIO_EXTICR1_EXTI3_Msk            /*!< EXTI 3 configuration */\n\n/*!< EXTI0 configuration */\n#define AFIO_EXTICR1_EXTI0_PA                0x00000000U                          /*!< PA[0] pin */\n#define AFIO_EXTICR1_EXTI0_PB_Pos            (0U)                              \n#define AFIO_EXTICR1_EXTI0_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR1_EXTI0_PB                AFIO_EXTICR1_EXTI0_PB_Msk         /*!< PB[0] pin */\n#define AFIO_EXTICR1_EXTI0_PC_Pos            (1U)                              \n#define AFIO_EXTICR1_EXTI0_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR1_EXTI0_PC                AFIO_EXTICR1_EXTI0_PC_Msk         /*!< PC[0] pin */\n#define AFIO_EXTICR1_EXTI0_PD_Pos            (0U)                              \n#define AFIO_EXTICR1_EXTI0_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR1_EXTI0_PD                AFIO_EXTICR1_EXTI0_PD_Msk         /*!< PD[0] pin */\n#define AFIO_EXTICR1_EXTI0_PE_Pos            (2U)                              \n#define AFIO_EXTICR1_EXTI0_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR1_EXTI0_PE                AFIO_EXTICR1_EXTI0_PE_Msk         /*!< PE[0] pin */\n#define AFIO_EXTICR1_EXTI0_PF_Pos            (0U)                              \n#define AFIO_EXTICR1_EXTI0_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR1_EXTI0_PF                AFIO_EXTICR1_EXTI0_PF_Msk         /*!< PF[0] pin */\n#define AFIO_EXTICR1_EXTI0_PG_Pos            (1U)                              \n#define AFIO_EXTICR1_EXTI0_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR1_EXTI0_PG                AFIO_EXTICR1_EXTI0_PG_Msk         /*!< PG[0] pin */\n\n/*!< EXTI1 configuration */\n#define AFIO_EXTICR1_EXTI1_PA                0x00000000U                          /*!< PA[1] pin */\n#define AFIO_EXTICR1_EXTI1_PB_Pos            (4U)                              \n#define AFIO_EXTICR1_EXTI1_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR1_EXTI1_PB                AFIO_EXTICR1_EXTI1_PB_Msk         /*!< PB[1] pin */\n#define AFIO_EXTICR1_EXTI1_PC_Pos            (5U)                              \n#define AFIO_EXTICR1_EXTI1_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR1_EXTI1_PC                AFIO_EXTICR1_EXTI1_PC_Msk         /*!< PC[1] pin */\n#define AFIO_EXTICR1_EXTI1_PD_Pos            (4U)                              \n#define AFIO_EXTICR1_EXTI1_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR1_EXTI1_PD                AFIO_EXTICR1_EXTI1_PD_Msk         /*!< PD[1] pin */\n#define AFIO_EXTICR1_EXTI1_PE_Pos            (6U)                              \n#define AFIO_EXTICR1_EXTI1_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR1_EXTI1_PE                AFIO_EXTICR1_EXTI1_PE_Msk         /*!< PE[1] pin */\n#define AFIO_EXTICR1_EXTI1_PF_Pos            (4U)                              \n#define AFIO_EXTICR1_EXTI1_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR1_EXTI1_PF                AFIO_EXTICR1_EXTI1_PF_Msk         /*!< PF[1] pin */\n#define AFIO_EXTICR1_EXTI1_PG_Pos            (5U)                              \n#define AFIO_EXTICR1_EXTI1_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR1_EXTI1_PG                AFIO_EXTICR1_EXTI1_PG_Msk         /*!< PG[1] pin */\n\n/*!< EXTI2 configuration */  \n#define AFIO_EXTICR1_EXTI2_PA                0x00000000U                          /*!< PA[2] pin */\n#define AFIO_EXTICR1_EXTI2_PB_Pos            (8U)                              \n#define AFIO_EXTICR1_EXTI2_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR1_EXTI2_PB                AFIO_EXTICR1_EXTI2_PB_Msk         /*!< PB[2] pin */\n#define AFIO_EXTICR1_EXTI2_PC_Pos            (9U)                              \n#define AFIO_EXTICR1_EXTI2_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR1_EXTI2_PC                AFIO_EXTICR1_EXTI2_PC_Msk         /*!< PC[2] pin */\n#define AFIO_EXTICR1_EXTI2_PD_Pos            (8U)                              \n#define AFIO_EXTICR1_EXTI2_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR1_EXTI2_PD                AFIO_EXTICR1_EXTI2_PD_Msk         /*!< PD[2] pin */\n#define AFIO_EXTICR1_EXTI2_PE_Pos            (10U)                             \n#define AFIO_EXTICR1_EXTI2_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR1_EXTI2_PE                AFIO_EXTICR1_EXTI2_PE_Msk         /*!< PE[2] pin */\n#define AFIO_EXTICR1_EXTI2_PF_Pos            (8U)                              \n#define AFIO_EXTICR1_EXTI2_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR1_EXTI2_PF                AFIO_EXTICR1_EXTI2_PF_Msk         /*!< PF[2] pin */\n#define AFIO_EXTICR1_EXTI2_PG_Pos            (9U)                              \n#define AFIO_EXTICR1_EXTI2_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR1_EXTI2_PG                AFIO_EXTICR1_EXTI2_PG_Msk         /*!< PG[2] pin */\n\n/*!< EXTI3 configuration */\n#define AFIO_EXTICR1_EXTI3_PA                0x00000000U                          /*!< PA[3] pin */\n#define AFIO_EXTICR1_EXTI3_PB_Pos            (12U)                             \n#define AFIO_EXTICR1_EXTI3_PB_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR1_EXTI3_PB                AFIO_EXTICR1_EXTI3_PB_Msk         /*!< PB[3] pin */\n#define AFIO_EXTICR1_EXTI3_PC_Pos            (13U)                             \n#define AFIO_EXTICR1_EXTI3_PC_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR1_EXTI3_PC                AFIO_EXTICR1_EXTI3_PC_Msk         /*!< PC[3] pin */\n#define AFIO_EXTICR1_EXTI3_PD_Pos            (12U)                             \n#define AFIO_EXTICR1_EXTI3_PD_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR1_EXTI3_PD                AFIO_EXTICR1_EXTI3_PD_Msk         /*!< PD[3] pin */\n#define AFIO_EXTICR1_EXTI3_PE_Pos            (14U)                             \n#define AFIO_EXTICR1_EXTI3_PE_Msk            (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR1_EXTI3_PE                AFIO_EXTICR1_EXTI3_PE_Msk         /*!< PE[3] pin */\n#define AFIO_EXTICR1_EXTI3_PF_Pos            (12U)                             \n#define AFIO_EXTICR1_EXTI3_PF_Msk            (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR1_EXTI3_PF                AFIO_EXTICR1_EXTI3_PF_Msk         /*!< PF[3] pin */\n#define AFIO_EXTICR1_EXTI3_PG_Pos            (13U)                             \n#define AFIO_EXTICR1_EXTI3_PG_Msk            (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR1_EXTI3_PG                AFIO_EXTICR1_EXTI3_PG_Msk         /*!< PG[3] pin */\n\n/*****************  Bit definition for AFIO_EXTICR2 register  *****************/\n#define AFIO_EXTICR2_EXTI4_Pos               (0U)                              \n#define AFIO_EXTICR2_EXTI4_Msk               (0xFUL << AFIO_EXTICR2_EXTI4_Pos)  /*!< 0x0000000F */\n#define AFIO_EXTICR2_EXTI4                   AFIO_EXTICR2_EXTI4_Msk            /*!< EXTI 4 configuration */\n#define AFIO_EXTICR2_EXTI5_Pos               (4U)                              \n#define AFIO_EXTICR2_EXTI5_Msk               (0xFUL << AFIO_EXTICR2_EXTI5_Pos)  /*!< 0x000000F0 */\n#define AFIO_EXTICR2_EXTI5                   AFIO_EXTICR2_EXTI5_Msk            /*!< EXTI 5 configuration */\n#define AFIO_EXTICR2_EXTI6_Pos               (8U)                              \n#define AFIO_EXTICR2_EXTI6_Msk               (0xFUL << AFIO_EXTICR2_EXTI6_Pos)  /*!< 0x00000F00 */\n#define AFIO_EXTICR2_EXTI6                   AFIO_EXTICR2_EXTI6_Msk            /*!< EXTI 6 configuration */\n#define AFIO_EXTICR2_EXTI7_Pos               (12U)                             \n#define AFIO_EXTICR2_EXTI7_Msk               (0xFUL << AFIO_EXTICR2_EXTI7_Pos)  /*!< 0x0000F000 */\n#define AFIO_EXTICR2_EXTI7                   AFIO_EXTICR2_EXTI7_Msk            /*!< EXTI 7 configuration */\n\n/*!< EXTI4 configuration */\n#define AFIO_EXTICR2_EXTI4_PA                0x00000000U                          /*!< PA[4] pin */\n#define AFIO_EXTICR2_EXTI4_PB_Pos            (0U)                              \n#define AFIO_EXTICR2_EXTI4_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR2_EXTI4_PB                AFIO_EXTICR2_EXTI4_PB_Msk         /*!< PB[4] pin */\n#define AFIO_EXTICR2_EXTI4_PC_Pos            (1U)                              \n#define AFIO_EXTICR2_EXTI4_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR2_EXTI4_PC                AFIO_EXTICR2_EXTI4_PC_Msk         /*!< PC[4] pin */\n#define AFIO_EXTICR2_EXTI4_PD_Pos            (0U)                              \n#define AFIO_EXTICR2_EXTI4_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR2_EXTI4_PD                AFIO_EXTICR2_EXTI4_PD_Msk         /*!< PD[4] pin */\n#define AFIO_EXTICR2_EXTI4_PE_Pos            (2U)                              \n#define AFIO_EXTICR2_EXTI4_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR2_EXTI4_PE                AFIO_EXTICR2_EXTI4_PE_Msk         /*!< PE[4] pin */\n#define AFIO_EXTICR2_EXTI4_PF_Pos            (0U)                              \n#define AFIO_EXTICR2_EXTI4_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR2_EXTI4_PF                AFIO_EXTICR2_EXTI4_PF_Msk         /*!< PF[4] pin */\n#define AFIO_EXTICR2_EXTI4_PG_Pos            (1U)                              \n#define AFIO_EXTICR2_EXTI4_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR2_EXTI4_PG                AFIO_EXTICR2_EXTI4_PG_Msk         /*!< PG[4] pin */\n\n/* EXTI5 configuration */\n#define AFIO_EXTICR2_EXTI5_PA                0x00000000U                          /*!< PA[5] pin */\n#define AFIO_EXTICR2_EXTI5_PB_Pos            (4U)                              \n#define AFIO_EXTICR2_EXTI5_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR2_EXTI5_PB                AFIO_EXTICR2_EXTI5_PB_Msk         /*!< PB[5] pin */\n#define AFIO_EXTICR2_EXTI5_PC_Pos            (5U)                              \n#define AFIO_EXTICR2_EXTI5_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR2_EXTI5_PC                AFIO_EXTICR2_EXTI5_PC_Msk         /*!< PC[5] pin */\n#define AFIO_EXTICR2_EXTI5_PD_Pos            (4U)                              \n#define AFIO_EXTICR2_EXTI5_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR2_EXTI5_PD                AFIO_EXTICR2_EXTI5_PD_Msk         /*!< PD[5] pin */\n#define AFIO_EXTICR2_EXTI5_PE_Pos            (6U)                              \n#define AFIO_EXTICR2_EXTI5_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR2_EXTI5_PE                AFIO_EXTICR2_EXTI5_PE_Msk         /*!< PE[5] pin */\n#define AFIO_EXTICR2_EXTI5_PF_Pos            (4U)                              \n#define AFIO_EXTICR2_EXTI5_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR2_EXTI5_PF                AFIO_EXTICR2_EXTI5_PF_Msk         /*!< PF[5] pin */\n#define AFIO_EXTICR2_EXTI5_PG_Pos            (5U)                              \n#define AFIO_EXTICR2_EXTI5_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR2_EXTI5_PG                AFIO_EXTICR2_EXTI5_PG_Msk         /*!< PG[5] pin */\n\n/*!< EXTI6 configuration */  \n#define AFIO_EXTICR2_EXTI6_PA                0x00000000U                          /*!< PA[6] pin */\n#define AFIO_EXTICR2_EXTI6_PB_Pos            (8U)                              \n#define AFIO_EXTICR2_EXTI6_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR2_EXTI6_PB                AFIO_EXTICR2_EXTI6_PB_Msk         /*!< PB[6] pin */\n#define AFIO_EXTICR2_EXTI6_PC_Pos            (9U)                              \n#define AFIO_EXTICR2_EXTI6_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR2_EXTI6_PC                AFIO_EXTICR2_EXTI6_PC_Msk         /*!< PC[6] pin */\n#define AFIO_EXTICR2_EXTI6_PD_Pos            (8U)                              \n#define AFIO_EXTICR2_EXTI6_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR2_EXTI6_PD                AFIO_EXTICR2_EXTI6_PD_Msk         /*!< PD[6] pin */\n#define AFIO_EXTICR2_EXTI6_PE_Pos            (10U)                             \n#define AFIO_EXTICR2_EXTI6_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR2_EXTI6_PE                AFIO_EXTICR2_EXTI6_PE_Msk         /*!< PE[6] pin */\n#define AFIO_EXTICR2_EXTI6_PF_Pos            (8U)                              \n#define AFIO_EXTICR2_EXTI6_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR2_EXTI6_PF                AFIO_EXTICR2_EXTI6_PF_Msk         /*!< PF[6] pin */\n#define AFIO_EXTICR2_EXTI6_PG_Pos            (9U)                              \n#define AFIO_EXTICR2_EXTI6_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR2_EXTI6_PG                AFIO_EXTICR2_EXTI6_PG_Msk         /*!< PG[6] pin */\n\n/*!< EXTI7 configuration */\n#define AFIO_EXTICR2_EXTI7_PA                0x00000000U                          /*!< PA[7] pin */\n#define AFIO_EXTICR2_EXTI7_PB_Pos            (12U)                             \n#define AFIO_EXTICR2_EXTI7_PB_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR2_EXTI7_PB                AFIO_EXTICR2_EXTI7_PB_Msk         /*!< PB[7] pin */\n#define AFIO_EXTICR2_EXTI7_PC_Pos            (13U)                             \n#define AFIO_EXTICR2_EXTI7_PC_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR2_EXTI7_PC                AFIO_EXTICR2_EXTI7_PC_Msk         /*!< PC[7] pin */\n#define AFIO_EXTICR2_EXTI7_PD_Pos            (12U)                             \n#define AFIO_EXTICR2_EXTI7_PD_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR2_EXTI7_PD                AFIO_EXTICR2_EXTI7_PD_Msk         /*!< PD[7] pin */\n#define AFIO_EXTICR2_EXTI7_PE_Pos            (14U)                             \n#define AFIO_EXTICR2_EXTI7_PE_Msk            (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR2_EXTI7_PE                AFIO_EXTICR2_EXTI7_PE_Msk         /*!< PE[7] pin */\n#define AFIO_EXTICR2_EXTI7_PF_Pos            (12U)                             \n#define AFIO_EXTICR2_EXTI7_PF_Msk            (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR2_EXTI7_PF                AFIO_EXTICR2_EXTI7_PF_Msk         /*!< PF[7] pin */\n#define AFIO_EXTICR2_EXTI7_PG_Pos            (13U)                             \n#define AFIO_EXTICR2_EXTI7_PG_Msk            (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR2_EXTI7_PG                AFIO_EXTICR2_EXTI7_PG_Msk         /*!< PG[7] pin */\n\n/*****************  Bit definition for AFIO_EXTICR3 register  *****************/\n#define AFIO_EXTICR3_EXTI8_Pos               (0U)                              \n#define AFIO_EXTICR3_EXTI8_Msk               (0xFUL << AFIO_EXTICR3_EXTI8_Pos)  /*!< 0x0000000F */\n#define AFIO_EXTICR3_EXTI8                   AFIO_EXTICR3_EXTI8_Msk            /*!< EXTI 8 configuration */\n#define AFIO_EXTICR3_EXTI9_Pos               (4U)                              \n#define AFIO_EXTICR3_EXTI9_Msk               (0xFUL << AFIO_EXTICR3_EXTI9_Pos)  /*!< 0x000000F0 */\n#define AFIO_EXTICR3_EXTI9                   AFIO_EXTICR3_EXTI9_Msk            /*!< EXTI 9 configuration */\n#define AFIO_EXTICR3_EXTI10_Pos              (8U)                              \n#define AFIO_EXTICR3_EXTI10_Msk              (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR3_EXTI10                  AFIO_EXTICR3_EXTI10_Msk           /*!< EXTI 10 configuration */\n#define AFIO_EXTICR3_EXTI11_Pos              (12U)                             \n#define AFIO_EXTICR3_EXTI11_Msk              (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR3_EXTI11                  AFIO_EXTICR3_EXTI11_Msk           /*!< EXTI 11 configuration */\n\n/*!< EXTI8 configuration */\n#define AFIO_EXTICR3_EXTI8_PA                0x00000000U                          /*!< PA[8] pin */\n#define AFIO_EXTICR3_EXTI8_PB_Pos            (0U)                              \n#define AFIO_EXTICR3_EXTI8_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR3_EXTI8_PB                AFIO_EXTICR3_EXTI8_PB_Msk         /*!< PB[8] pin */\n#define AFIO_EXTICR3_EXTI8_PC_Pos            (1U)                              \n#define AFIO_EXTICR3_EXTI8_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR3_EXTI8_PC                AFIO_EXTICR3_EXTI8_PC_Msk         /*!< PC[8] pin */\n#define AFIO_EXTICR3_EXTI8_PD_Pos            (0U)                              \n#define AFIO_EXTICR3_EXTI8_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR3_EXTI8_PD                AFIO_EXTICR3_EXTI8_PD_Msk         /*!< PD[8] pin */\n#define AFIO_EXTICR3_EXTI8_PE_Pos            (2U)                              \n#define AFIO_EXTICR3_EXTI8_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR3_EXTI8_PE                AFIO_EXTICR3_EXTI8_PE_Msk         /*!< PE[8] pin */\n#define AFIO_EXTICR3_EXTI8_PF_Pos            (0U)                              \n#define AFIO_EXTICR3_EXTI8_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR3_EXTI8_PF                AFIO_EXTICR3_EXTI8_PF_Msk         /*!< PF[8] pin */\n#define AFIO_EXTICR3_EXTI8_PG_Pos            (1U)                              \n#define AFIO_EXTICR3_EXTI8_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR3_EXTI8_PG                AFIO_EXTICR3_EXTI8_PG_Msk         /*!< PG[8] pin */\n\n/*!< EXTI9 configuration */\n#define AFIO_EXTICR3_EXTI9_PA                0x00000000U                          /*!< PA[9] pin */\n#define AFIO_EXTICR3_EXTI9_PB_Pos            (4U)                              \n#define AFIO_EXTICR3_EXTI9_PB_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR3_EXTI9_PB                AFIO_EXTICR3_EXTI9_PB_Msk         /*!< PB[9] pin */\n#define AFIO_EXTICR3_EXTI9_PC_Pos            (5U)                              \n#define AFIO_EXTICR3_EXTI9_PC_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR3_EXTI9_PC                AFIO_EXTICR3_EXTI9_PC_Msk         /*!< PC[9] pin */\n#define AFIO_EXTICR3_EXTI9_PD_Pos            (4U)                              \n#define AFIO_EXTICR3_EXTI9_PD_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR3_EXTI9_PD                AFIO_EXTICR3_EXTI9_PD_Msk         /*!< PD[9] pin */\n#define AFIO_EXTICR3_EXTI9_PE_Pos            (6U)                              \n#define AFIO_EXTICR3_EXTI9_PE_Msk            (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR3_EXTI9_PE                AFIO_EXTICR3_EXTI9_PE_Msk         /*!< PE[9] pin */\n#define AFIO_EXTICR3_EXTI9_PF_Pos            (4U)                              \n#define AFIO_EXTICR3_EXTI9_PF_Msk            (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR3_EXTI9_PF                AFIO_EXTICR3_EXTI9_PF_Msk         /*!< PF[9] pin */\n#define AFIO_EXTICR3_EXTI9_PG_Pos            (5U)                              \n#define AFIO_EXTICR3_EXTI9_PG_Msk            (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR3_EXTI9_PG                AFIO_EXTICR3_EXTI9_PG_Msk         /*!< PG[9] pin */\n\n/*!< EXTI10 configuration */  \n#define AFIO_EXTICR3_EXTI10_PA               0x00000000U                          /*!< PA[10] pin */\n#define AFIO_EXTICR3_EXTI10_PB_Pos           (8U)                              \n#define AFIO_EXTICR3_EXTI10_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR3_EXTI10_PB               AFIO_EXTICR3_EXTI10_PB_Msk        /*!< PB[10] pin */\n#define AFIO_EXTICR3_EXTI10_PC_Pos           (9U)                              \n#define AFIO_EXTICR3_EXTI10_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR3_EXTI10_PC               AFIO_EXTICR3_EXTI10_PC_Msk        /*!< PC[10] pin */\n#define AFIO_EXTICR3_EXTI10_PD_Pos           (8U)                              \n#define AFIO_EXTICR3_EXTI10_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR3_EXTI10_PD               AFIO_EXTICR3_EXTI10_PD_Msk        /*!< PD[10] pin */\n#define AFIO_EXTICR3_EXTI10_PE_Pos           (10U)                             \n#define AFIO_EXTICR3_EXTI10_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR3_EXTI10_PE               AFIO_EXTICR3_EXTI10_PE_Msk        /*!< PE[10] pin */\n#define AFIO_EXTICR3_EXTI10_PF_Pos           (8U)                              \n#define AFIO_EXTICR3_EXTI10_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR3_EXTI10_PF               AFIO_EXTICR3_EXTI10_PF_Msk        /*!< PF[10] pin */\n#define AFIO_EXTICR3_EXTI10_PG_Pos           (9U)                              \n#define AFIO_EXTICR3_EXTI10_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR3_EXTI10_PG               AFIO_EXTICR3_EXTI10_PG_Msk        /*!< PG[10] pin */\n\n/*!< EXTI11 configuration */\n#define AFIO_EXTICR3_EXTI11_PA               0x00000000U                          /*!< PA[11] pin */\n#define AFIO_EXTICR3_EXTI11_PB_Pos           (12U)                             \n#define AFIO_EXTICR3_EXTI11_PB_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR3_EXTI11_PB               AFIO_EXTICR3_EXTI11_PB_Msk        /*!< PB[11] pin */\n#define AFIO_EXTICR3_EXTI11_PC_Pos           (13U)                             \n#define AFIO_EXTICR3_EXTI11_PC_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR3_EXTI11_PC               AFIO_EXTICR3_EXTI11_PC_Msk        /*!< PC[11] pin */\n#define AFIO_EXTICR3_EXTI11_PD_Pos           (12U)                             \n#define AFIO_EXTICR3_EXTI11_PD_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR3_EXTI11_PD               AFIO_EXTICR3_EXTI11_PD_Msk        /*!< PD[11] pin */\n#define AFIO_EXTICR3_EXTI11_PE_Pos           (14U)                             \n#define AFIO_EXTICR3_EXTI11_PE_Msk           (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR3_EXTI11_PE               AFIO_EXTICR3_EXTI11_PE_Msk        /*!< PE[11] pin */\n#define AFIO_EXTICR3_EXTI11_PF_Pos           (12U)                             \n#define AFIO_EXTICR3_EXTI11_PF_Msk           (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR3_EXTI11_PF               AFIO_EXTICR3_EXTI11_PF_Msk        /*!< PF[11] pin */\n#define AFIO_EXTICR3_EXTI11_PG_Pos           (13U)                             \n#define AFIO_EXTICR3_EXTI11_PG_Msk           (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR3_EXTI11_PG               AFIO_EXTICR3_EXTI11_PG_Msk        /*!< PG[11] pin */\n\n/*****************  Bit definition for AFIO_EXTICR4 register  *****************/\n#define AFIO_EXTICR4_EXTI12_Pos              (0U)                              \n#define AFIO_EXTICR4_EXTI12_Msk              (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\n#define AFIO_EXTICR4_EXTI12                  AFIO_EXTICR4_EXTI12_Msk           /*!< EXTI 12 configuration */\n#define AFIO_EXTICR4_EXTI13_Pos              (4U)                              \n#define AFIO_EXTICR4_EXTI13_Msk              (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\n#define AFIO_EXTICR4_EXTI13                  AFIO_EXTICR4_EXTI13_Msk           /*!< EXTI 13 configuration */\n#define AFIO_EXTICR4_EXTI14_Pos              (8U)                              \n#define AFIO_EXTICR4_EXTI14_Msk              (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\n#define AFIO_EXTICR4_EXTI14                  AFIO_EXTICR4_EXTI14_Msk           /*!< EXTI 14 configuration */\n#define AFIO_EXTICR4_EXTI15_Pos              (12U)                             \n#define AFIO_EXTICR4_EXTI15_Msk              (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\n#define AFIO_EXTICR4_EXTI15                  AFIO_EXTICR4_EXTI15_Msk           /*!< EXTI 15 configuration */\n\n/* EXTI12 configuration */\n#define AFIO_EXTICR4_EXTI12_PA               0x00000000U                          /*!< PA[12] pin */\n#define AFIO_EXTICR4_EXTI12_PB_Pos           (0U)                              \n#define AFIO_EXTICR4_EXTI12_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */\n#define AFIO_EXTICR4_EXTI12_PB               AFIO_EXTICR4_EXTI12_PB_Msk        /*!< PB[12] pin */\n#define AFIO_EXTICR4_EXTI12_PC_Pos           (1U)                              \n#define AFIO_EXTICR4_EXTI12_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */\n#define AFIO_EXTICR4_EXTI12_PC               AFIO_EXTICR4_EXTI12_PC_Msk        /*!< PC[12] pin */\n#define AFIO_EXTICR4_EXTI12_PD_Pos           (0U)                              \n#define AFIO_EXTICR4_EXTI12_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */\n#define AFIO_EXTICR4_EXTI12_PD               AFIO_EXTICR4_EXTI12_PD_Msk        /*!< PD[12] pin */\n#define AFIO_EXTICR4_EXTI12_PE_Pos           (2U)                              \n#define AFIO_EXTICR4_EXTI12_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */\n#define AFIO_EXTICR4_EXTI12_PE               AFIO_EXTICR4_EXTI12_PE_Msk        /*!< PE[12] pin */\n#define AFIO_EXTICR4_EXTI12_PF_Pos           (0U)                              \n#define AFIO_EXTICR4_EXTI12_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */\n#define AFIO_EXTICR4_EXTI12_PF               AFIO_EXTICR4_EXTI12_PF_Msk        /*!< PF[12] pin */\n#define AFIO_EXTICR4_EXTI12_PG_Pos           (1U)                              \n#define AFIO_EXTICR4_EXTI12_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */\n#define AFIO_EXTICR4_EXTI12_PG               AFIO_EXTICR4_EXTI12_PG_Msk        /*!< PG[12] pin */\n\n/* EXTI13 configuration */\n#define AFIO_EXTICR4_EXTI13_PA               0x00000000U                          /*!< PA[13] pin */\n#define AFIO_EXTICR4_EXTI13_PB_Pos           (4U)                              \n#define AFIO_EXTICR4_EXTI13_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */\n#define AFIO_EXTICR4_EXTI13_PB               AFIO_EXTICR4_EXTI13_PB_Msk        /*!< PB[13] pin */\n#define AFIO_EXTICR4_EXTI13_PC_Pos           (5U)                              \n#define AFIO_EXTICR4_EXTI13_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */\n#define AFIO_EXTICR4_EXTI13_PC               AFIO_EXTICR4_EXTI13_PC_Msk        /*!< PC[13] pin */\n#define AFIO_EXTICR4_EXTI13_PD_Pos           (4U)                              \n#define AFIO_EXTICR4_EXTI13_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */\n#define AFIO_EXTICR4_EXTI13_PD               AFIO_EXTICR4_EXTI13_PD_Msk        /*!< PD[13] pin */\n#define AFIO_EXTICR4_EXTI13_PE_Pos           (6U)                              \n#define AFIO_EXTICR4_EXTI13_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */\n#define AFIO_EXTICR4_EXTI13_PE               AFIO_EXTICR4_EXTI13_PE_Msk        /*!< PE[13] pin */\n#define AFIO_EXTICR4_EXTI13_PF_Pos           (4U)                              \n#define AFIO_EXTICR4_EXTI13_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */\n#define AFIO_EXTICR4_EXTI13_PF               AFIO_EXTICR4_EXTI13_PF_Msk        /*!< PF[13] pin */\n#define AFIO_EXTICR4_EXTI13_PG_Pos           (5U)                              \n#define AFIO_EXTICR4_EXTI13_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */\n#define AFIO_EXTICR4_EXTI13_PG               AFIO_EXTICR4_EXTI13_PG_Msk        /*!< PG[13] pin */\n\n/*!< EXTI14 configuration */  \n#define AFIO_EXTICR4_EXTI14_PA               0x00000000U                          /*!< PA[14] pin */\n#define AFIO_EXTICR4_EXTI14_PB_Pos           (8U)                              \n#define AFIO_EXTICR4_EXTI14_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */\n#define AFIO_EXTICR4_EXTI14_PB               AFIO_EXTICR4_EXTI14_PB_Msk        /*!< PB[14] pin */\n#define AFIO_EXTICR4_EXTI14_PC_Pos           (9U)                              \n#define AFIO_EXTICR4_EXTI14_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */\n#define AFIO_EXTICR4_EXTI14_PC               AFIO_EXTICR4_EXTI14_PC_Msk        /*!< PC[14] pin */\n#define AFIO_EXTICR4_EXTI14_PD_Pos           (8U)                              \n#define AFIO_EXTICR4_EXTI14_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */\n#define AFIO_EXTICR4_EXTI14_PD               AFIO_EXTICR4_EXTI14_PD_Msk        /*!< PD[14] pin */\n#define AFIO_EXTICR4_EXTI14_PE_Pos           (10U)                             \n#define AFIO_EXTICR4_EXTI14_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */\n#define AFIO_EXTICR4_EXTI14_PE               AFIO_EXTICR4_EXTI14_PE_Msk        /*!< PE[14] pin */\n#define AFIO_EXTICR4_EXTI14_PF_Pos           (8U)                              \n#define AFIO_EXTICR4_EXTI14_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */\n#define AFIO_EXTICR4_EXTI14_PF               AFIO_EXTICR4_EXTI14_PF_Msk        /*!< PF[14] pin */\n#define AFIO_EXTICR4_EXTI14_PG_Pos           (9U)                              \n#define AFIO_EXTICR4_EXTI14_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */\n#define AFIO_EXTICR4_EXTI14_PG               AFIO_EXTICR4_EXTI14_PG_Msk        /*!< PG[14] pin */\n\n/*!< EXTI15 configuration */\n#define AFIO_EXTICR4_EXTI15_PA               0x00000000U                          /*!< PA[15] pin */\n#define AFIO_EXTICR4_EXTI15_PB_Pos           (12U)                             \n#define AFIO_EXTICR4_EXTI15_PB_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */\n#define AFIO_EXTICR4_EXTI15_PB               AFIO_EXTICR4_EXTI15_PB_Msk        /*!< PB[15] pin */\n#define AFIO_EXTICR4_EXTI15_PC_Pos           (13U)                             \n#define AFIO_EXTICR4_EXTI15_PC_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */\n#define AFIO_EXTICR4_EXTI15_PC               AFIO_EXTICR4_EXTI15_PC_Msk        /*!< PC[15] pin */\n#define AFIO_EXTICR4_EXTI15_PD_Pos           (12U)                             \n#define AFIO_EXTICR4_EXTI15_PD_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */\n#define AFIO_EXTICR4_EXTI15_PD               AFIO_EXTICR4_EXTI15_PD_Msk        /*!< PD[15] pin */\n#define AFIO_EXTICR4_EXTI15_PE_Pos           (14U)                             \n#define AFIO_EXTICR4_EXTI15_PE_Msk           (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */\n#define AFIO_EXTICR4_EXTI15_PE               AFIO_EXTICR4_EXTI15_PE_Msk        /*!< PE[15] pin */\n#define AFIO_EXTICR4_EXTI15_PF_Pos           (12U)                             \n#define AFIO_EXTICR4_EXTI15_PF_Msk           (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */\n#define AFIO_EXTICR4_EXTI15_PF               AFIO_EXTICR4_EXTI15_PF_Msk        /*!< PF[15] pin */\n#define AFIO_EXTICR4_EXTI15_PG_Pos           (13U)                             \n#define AFIO_EXTICR4_EXTI15_PG_Msk           (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */\n#define AFIO_EXTICR4_EXTI15_PG               AFIO_EXTICR4_EXTI15_PG_Msk        /*!< PG[15] pin */\n\n/******************  Bit definition for AFIO_MAPR2 register  ******************/\n\n\n\n/******************************************************************************/\n/*                                                                            */\n/*                    External Interrupt/Event Controller                     */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for EXTI_IMR register  *******************/\n#define EXTI_IMR_MR0_Pos                    (0U)                               \n#define EXTI_IMR_MR0_Msk                    (0x1UL << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */\n#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */\n#define EXTI_IMR_MR1_Pos                    (1U)                               \n#define EXTI_IMR_MR1_Msk                    (0x1UL << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */\n#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */\n#define EXTI_IMR_MR2_Pos                    (2U)                               \n#define EXTI_IMR_MR2_Msk                    (0x1UL << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */\n#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */\n#define EXTI_IMR_MR3_Pos                    (3U)                               \n#define EXTI_IMR_MR3_Msk                    (0x1UL << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */\n#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */\n#define EXTI_IMR_MR4_Pos                    (4U)                               \n#define EXTI_IMR_MR4_Msk                    (0x1UL << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */\n#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */\n#define EXTI_IMR_MR5_Pos                    (5U)                               \n#define EXTI_IMR_MR5_Msk                    (0x1UL << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */\n#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */\n#define EXTI_IMR_MR6_Pos                    (6U)                               \n#define EXTI_IMR_MR6_Msk                    (0x1UL << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */\n#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */\n#define EXTI_IMR_MR7_Pos                    (7U)                               \n#define EXTI_IMR_MR7_Msk                    (0x1UL << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */\n#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */\n#define EXTI_IMR_MR8_Pos                    (8U)                               \n#define EXTI_IMR_MR8_Msk                    (0x1UL << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */\n#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */\n#define EXTI_IMR_MR9_Pos                    (9U)                               \n#define EXTI_IMR_MR9_Msk                    (0x1UL << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */\n#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */\n#define EXTI_IMR_MR10_Pos                   (10U)                              \n#define EXTI_IMR_MR10_Msk                   (0x1UL << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */\n#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */\n#define EXTI_IMR_MR11_Pos                   (11U)                              \n#define EXTI_IMR_MR11_Msk                   (0x1UL << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */\n#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */\n#define EXTI_IMR_MR12_Pos                   (12U)                              \n#define EXTI_IMR_MR12_Msk                   (0x1UL << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */\n#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */\n#define EXTI_IMR_MR13_Pos                   (13U)                              \n#define EXTI_IMR_MR13_Msk                   (0x1UL << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */\n#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */\n#define EXTI_IMR_MR14_Pos                   (14U)                              \n#define EXTI_IMR_MR14_Msk                   (0x1UL << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */\n#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */\n#define EXTI_IMR_MR15_Pos                   (15U)                              \n#define EXTI_IMR_MR15_Msk                   (0x1UL << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */\n#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */\n#define EXTI_IMR_MR16_Pos                   (16U)                              \n#define EXTI_IMR_MR16_Msk                   (0x1UL << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */\n#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */\n#define EXTI_IMR_MR17_Pos                   (17U)                              \n#define EXTI_IMR_MR17_Msk                   (0x1UL << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */\n#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */\n#define EXTI_IMR_MR18_Pos                   (18U)                              \n#define EXTI_IMR_MR18_Msk                   (0x1UL << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */\n#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */\n\n/* References Defines */\n#define  EXTI_IMR_IM0 EXTI_IMR_MR0\n#define  EXTI_IMR_IM1 EXTI_IMR_MR1\n#define  EXTI_IMR_IM2 EXTI_IMR_MR2\n#define  EXTI_IMR_IM3 EXTI_IMR_MR3\n#define  EXTI_IMR_IM4 EXTI_IMR_MR4\n#define  EXTI_IMR_IM5 EXTI_IMR_MR5\n#define  EXTI_IMR_IM6 EXTI_IMR_MR6\n#define  EXTI_IMR_IM7 EXTI_IMR_MR7\n#define  EXTI_IMR_IM8 EXTI_IMR_MR8\n#define  EXTI_IMR_IM9 EXTI_IMR_MR9\n#define  EXTI_IMR_IM10 EXTI_IMR_MR10\n#define  EXTI_IMR_IM11 EXTI_IMR_MR11\n#define  EXTI_IMR_IM12 EXTI_IMR_MR12\n#define  EXTI_IMR_IM13 EXTI_IMR_MR13\n#define  EXTI_IMR_IM14 EXTI_IMR_MR14\n#define  EXTI_IMR_IM15 EXTI_IMR_MR15\n#define  EXTI_IMR_IM16 EXTI_IMR_MR16\n#define  EXTI_IMR_IM17 EXTI_IMR_MR17\n#define  EXTI_IMR_IM18 EXTI_IMR_MR18\n#define  EXTI_IMR_IM   0x0007FFFFU        /*!< Interrupt Mask All */\n \n/*******************  Bit definition for EXTI_EMR register  *******************/\n#define EXTI_EMR_MR0_Pos                    (0U)                               \n#define EXTI_EMR_MR0_Msk                    (0x1UL << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */\n#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */\n#define EXTI_EMR_MR1_Pos                    (1U)                               \n#define EXTI_EMR_MR1_Msk                    (0x1UL << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */\n#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */\n#define EXTI_EMR_MR2_Pos                    (2U)                               \n#define EXTI_EMR_MR2_Msk                    (0x1UL << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */\n#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */\n#define EXTI_EMR_MR3_Pos                    (3U)                               \n#define EXTI_EMR_MR3_Msk                    (0x1UL << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */\n#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */\n#define EXTI_EMR_MR4_Pos                    (4U)                               \n#define EXTI_EMR_MR4_Msk                    (0x1UL << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */\n#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */\n#define EXTI_EMR_MR5_Pos                    (5U)                               \n#define EXTI_EMR_MR5_Msk                    (0x1UL << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */\n#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */\n#define EXTI_EMR_MR6_Pos                    (6U)                               \n#define EXTI_EMR_MR6_Msk                    (0x1UL << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */\n#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */\n#define EXTI_EMR_MR7_Pos                    (7U)                               \n#define EXTI_EMR_MR7_Msk                    (0x1UL << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */\n#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */\n#define EXTI_EMR_MR8_Pos                    (8U)                               \n#define EXTI_EMR_MR8_Msk                    (0x1UL << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */\n#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */\n#define EXTI_EMR_MR9_Pos                    (9U)                               \n#define EXTI_EMR_MR9_Msk                    (0x1UL << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */\n#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */\n#define EXTI_EMR_MR10_Pos                   (10U)                              \n#define EXTI_EMR_MR10_Msk                   (0x1UL << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */\n#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */\n#define EXTI_EMR_MR11_Pos                   (11U)                              \n#define EXTI_EMR_MR11_Msk                   (0x1UL << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */\n#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */\n#define EXTI_EMR_MR12_Pos                   (12U)                              \n#define EXTI_EMR_MR12_Msk                   (0x1UL << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */\n#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */\n#define EXTI_EMR_MR13_Pos                   (13U)                              \n#define EXTI_EMR_MR13_Msk                   (0x1UL << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */\n#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */\n#define EXTI_EMR_MR14_Pos                   (14U)                              \n#define EXTI_EMR_MR14_Msk                   (0x1UL << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */\n#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */\n#define EXTI_EMR_MR15_Pos                   (15U)                              \n#define EXTI_EMR_MR15_Msk                   (0x1UL << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */\n#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */\n#define EXTI_EMR_MR16_Pos                   (16U)                              \n#define EXTI_EMR_MR16_Msk                   (0x1UL << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */\n#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */\n#define EXTI_EMR_MR17_Pos                   (17U)                              \n#define EXTI_EMR_MR17_Msk                   (0x1UL << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */\n#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */\n#define EXTI_EMR_MR18_Pos                   (18U)                              \n#define EXTI_EMR_MR18_Msk                   (0x1UL << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */\n#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */\n\n/* References Defines */\n#define  EXTI_EMR_EM0 EXTI_EMR_MR0\n#define  EXTI_EMR_EM1 EXTI_EMR_MR1\n#define  EXTI_EMR_EM2 EXTI_EMR_MR2\n#define  EXTI_EMR_EM3 EXTI_EMR_MR3\n#define  EXTI_EMR_EM4 EXTI_EMR_MR4\n#define  EXTI_EMR_EM5 EXTI_EMR_MR5\n#define  EXTI_EMR_EM6 EXTI_EMR_MR6\n#define  EXTI_EMR_EM7 EXTI_EMR_MR7\n#define  EXTI_EMR_EM8 EXTI_EMR_MR8\n#define  EXTI_EMR_EM9 EXTI_EMR_MR9\n#define  EXTI_EMR_EM10 EXTI_EMR_MR10\n#define  EXTI_EMR_EM11 EXTI_EMR_MR11\n#define  EXTI_EMR_EM12 EXTI_EMR_MR12\n#define  EXTI_EMR_EM13 EXTI_EMR_MR13\n#define  EXTI_EMR_EM14 EXTI_EMR_MR14\n#define  EXTI_EMR_EM15 EXTI_EMR_MR15\n#define  EXTI_EMR_EM16 EXTI_EMR_MR16\n#define  EXTI_EMR_EM17 EXTI_EMR_MR17\n#define  EXTI_EMR_EM18 EXTI_EMR_MR18\n\n/******************  Bit definition for EXTI_RTSR register  *******************/\n#define EXTI_RTSR_TR0_Pos                   (0U)                               \n#define EXTI_RTSR_TR0_Msk                   (0x1UL << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */\n#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */\n#define EXTI_RTSR_TR1_Pos                   (1U)                               \n#define EXTI_RTSR_TR1_Msk                   (0x1UL << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */\n#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */\n#define EXTI_RTSR_TR2_Pos                   (2U)                               \n#define EXTI_RTSR_TR2_Msk                   (0x1UL << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */\n#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */\n#define EXTI_RTSR_TR3_Pos                   (3U)                               \n#define EXTI_RTSR_TR3_Msk                   (0x1UL << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */\n#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */\n#define EXTI_RTSR_TR4_Pos                   (4U)                               \n#define EXTI_RTSR_TR4_Msk                   (0x1UL << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */\n#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */\n#define EXTI_RTSR_TR5_Pos                   (5U)                               \n#define EXTI_RTSR_TR5_Msk                   (0x1UL << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */\n#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */\n#define EXTI_RTSR_TR6_Pos                   (6U)                               \n#define EXTI_RTSR_TR6_Msk                   (0x1UL << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */\n#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */\n#define EXTI_RTSR_TR7_Pos                   (7U)                               \n#define EXTI_RTSR_TR7_Msk                   (0x1UL << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */\n#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */\n#define EXTI_RTSR_TR8_Pos                   (8U)                               \n#define EXTI_RTSR_TR8_Msk                   (0x1UL << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */\n#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */\n#define EXTI_RTSR_TR9_Pos                   (9U)                               \n#define EXTI_RTSR_TR9_Msk                   (0x1UL << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */\n#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */\n#define EXTI_RTSR_TR10_Pos                  (10U)                              \n#define EXTI_RTSR_TR10_Msk                  (0x1UL << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */\n#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */\n#define EXTI_RTSR_TR11_Pos                  (11U)                              \n#define EXTI_RTSR_TR11_Msk                  (0x1UL << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */\n#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */\n#define EXTI_RTSR_TR12_Pos                  (12U)                              \n#define EXTI_RTSR_TR12_Msk                  (0x1UL << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */\n#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */\n#define EXTI_RTSR_TR13_Pos                  (13U)                              \n#define EXTI_RTSR_TR13_Msk                  (0x1UL << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */\n#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */\n#define EXTI_RTSR_TR14_Pos                  (14U)                              \n#define EXTI_RTSR_TR14_Msk                  (0x1UL << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */\n#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */\n#define EXTI_RTSR_TR15_Pos                  (15U)                              \n#define EXTI_RTSR_TR15_Msk                  (0x1UL << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */\n#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */\n#define EXTI_RTSR_TR16_Pos                  (16U)                              \n#define EXTI_RTSR_TR16_Msk                  (0x1UL << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */\n#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */\n#define EXTI_RTSR_TR17_Pos                  (17U)                              \n#define EXTI_RTSR_TR17_Msk                  (0x1UL << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */\n#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */\n#define EXTI_RTSR_TR18_Pos                  (18U)                              \n#define EXTI_RTSR_TR18_Msk                  (0x1UL << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */\n#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */\n\n/* References Defines */\n#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0\n#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1\n#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2\n#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3\n#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4\n#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5\n#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6\n#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7\n#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8\n#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9\n#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10\n#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11\n#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12\n#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13\n#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14\n#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15\n#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16\n#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17\n#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18\n\n/******************  Bit definition for EXTI_FTSR register  *******************/\n#define EXTI_FTSR_TR0_Pos                   (0U)                               \n#define EXTI_FTSR_TR0_Msk                   (0x1UL << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */\n#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */\n#define EXTI_FTSR_TR1_Pos                   (1U)                               \n#define EXTI_FTSR_TR1_Msk                   (0x1UL << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */\n#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */\n#define EXTI_FTSR_TR2_Pos                   (2U)                               \n#define EXTI_FTSR_TR2_Msk                   (0x1UL << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */\n#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */\n#define EXTI_FTSR_TR3_Pos                   (3U)                               \n#define EXTI_FTSR_TR3_Msk                   (0x1UL << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */\n#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */\n#define EXTI_FTSR_TR4_Pos                   (4U)                               \n#define EXTI_FTSR_TR4_Msk                   (0x1UL << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */\n#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */\n#define EXTI_FTSR_TR5_Pos                   (5U)                               \n#define EXTI_FTSR_TR5_Msk                   (0x1UL << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */\n#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */\n#define EXTI_FTSR_TR6_Pos                   (6U)                               \n#define EXTI_FTSR_TR6_Msk                   (0x1UL << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */\n#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */\n#define EXTI_FTSR_TR7_Pos                   (7U)                               \n#define EXTI_FTSR_TR7_Msk                   (0x1UL << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */\n#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */\n#define EXTI_FTSR_TR8_Pos                   (8U)                               \n#define EXTI_FTSR_TR8_Msk                   (0x1UL << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */\n#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */\n#define EXTI_FTSR_TR9_Pos                   (9U)                               \n#define EXTI_FTSR_TR9_Msk                   (0x1UL << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */\n#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */\n#define EXTI_FTSR_TR10_Pos                  (10U)                              \n#define EXTI_FTSR_TR10_Msk                  (0x1UL << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */\n#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */\n#define EXTI_FTSR_TR11_Pos                  (11U)                              \n#define EXTI_FTSR_TR11_Msk                  (0x1UL << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */\n#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */\n#define EXTI_FTSR_TR12_Pos                  (12U)                              \n#define EXTI_FTSR_TR12_Msk                  (0x1UL << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */\n#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */\n#define EXTI_FTSR_TR13_Pos                  (13U)                              \n#define EXTI_FTSR_TR13_Msk                  (0x1UL << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */\n#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */\n#define EXTI_FTSR_TR14_Pos                  (14U)                              \n#define EXTI_FTSR_TR14_Msk                  (0x1UL << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */\n#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */\n#define EXTI_FTSR_TR15_Pos                  (15U)                              \n#define EXTI_FTSR_TR15_Msk                  (0x1UL << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */\n#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */\n#define EXTI_FTSR_TR16_Pos                  (16U)                              \n#define EXTI_FTSR_TR16_Msk                  (0x1UL << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */\n#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */\n#define EXTI_FTSR_TR17_Pos                  (17U)                              \n#define EXTI_FTSR_TR17_Msk                  (0x1UL << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */\n#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */\n#define EXTI_FTSR_TR18_Pos                  (18U)                              \n#define EXTI_FTSR_TR18_Msk                  (0x1UL << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */\n#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */\n\n/* References Defines */\n#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0\n#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1\n#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2\n#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3\n#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4\n#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5\n#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6\n#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7\n#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8\n#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9\n#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10\n#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11\n#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12\n#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13\n#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14\n#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15\n#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16\n#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17\n#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18\n\n/******************  Bit definition for EXTI_SWIER register  ******************/\n#define EXTI_SWIER_SWIER0_Pos               (0U)                               \n#define EXTI_SWIER_SWIER0_Msk               (0x1UL << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */\n#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */\n#define EXTI_SWIER_SWIER1_Pos               (1U)                               \n#define EXTI_SWIER_SWIER1_Msk               (0x1UL << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */\n#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */\n#define EXTI_SWIER_SWIER2_Pos               (2U)                               \n#define EXTI_SWIER_SWIER2_Msk               (0x1UL << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */\n#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */\n#define EXTI_SWIER_SWIER3_Pos               (3U)                               \n#define EXTI_SWIER_SWIER3_Msk               (0x1UL << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */\n#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */\n#define EXTI_SWIER_SWIER4_Pos               (4U)                               \n#define EXTI_SWIER_SWIER4_Msk               (0x1UL << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */\n#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */\n#define EXTI_SWIER_SWIER5_Pos               (5U)                               \n#define EXTI_SWIER_SWIER5_Msk               (0x1UL << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */\n#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */\n#define EXTI_SWIER_SWIER6_Pos               (6U)                               \n#define EXTI_SWIER_SWIER6_Msk               (0x1UL << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */\n#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */\n#define EXTI_SWIER_SWIER7_Pos               (7U)                               \n#define EXTI_SWIER_SWIER7_Msk               (0x1UL << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */\n#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */\n#define EXTI_SWIER_SWIER8_Pos               (8U)                               \n#define EXTI_SWIER_SWIER8_Msk               (0x1UL << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */\n#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */\n#define EXTI_SWIER_SWIER9_Pos               (9U)                               \n#define EXTI_SWIER_SWIER9_Msk               (0x1UL << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */\n#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */\n#define EXTI_SWIER_SWIER10_Pos              (10U)                              \n#define EXTI_SWIER_SWIER10_Msk              (0x1UL << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */\n#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */\n#define EXTI_SWIER_SWIER11_Pos              (11U)                              \n#define EXTI_SWIER_SWIER11_Msk              (0x1UL << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */\n#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */\n#define EXTI_SWIER_SWIER12_Pos              (12U)                              \n#define EXTI_SWIER_SWIER12_Msk              (0x1UL << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */\n#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */\n#define EXTI_SWIER_SWIER13_Pos              (13U)                              \n#define EXTI_SWIER_SWIER13_Msk              (0x1UL << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */\n#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */\n#define EXTI_SWIER_SWIER14_Pos              (14U)                              \n#define EXTI_SWIER_SWIER14_Msk              (0x1UL << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */\n#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */\n#define EXTI_SWIER_SWIER15_Pos              (15U)                              \n#define EXTI_SWIER_SWIER15_Msk              (0x1UL << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */\n#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */\n#define EXTI_SWIER_SWIER16_Pos              (16U)                              \n#define EXTI_SWIER_SWIER16_Msk              (0x1UL << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */\n#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */\n#define EXTI_SWIER_SWIER17_Pos              (17U)                              \n#define EXTI_SWIER_SWIER17_Msk              (0x1UL << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */\n#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */\n#define EXTI_SWIER_SWIER18_Pos              (18U)                              \n#define EXTI_SWIER_SWIER18_Msk              (0x1UL << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */\n#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */\n\n/* References Defines */\n#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0\n#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1\n#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2\n#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3\n#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4\n#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5\n#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6\n#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7\n#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8\n#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9\n#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10\n#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11\n#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12\n#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13\n#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14\n#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15\n#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16\n#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17\n#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18\n\n/*******************  Bit definition for EXTI_PR register  ********************/\n#define EXTI_PR_PR0_Pos                     (0U)                               \n#define EXTI_PR_PR0_Msk                     (0x1UL << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */\n#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */\n#define EXTI_PR_PR1_Pos                     (1U)                               \n#define EXTI_PR_PR1_Msk                     (0x1UL << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */\n#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */\n#define EXTI_PR_PR2_Pos                     (2U)                               \n#define EXTI_PR_PR2_Msk                     (0x1UL << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */\n#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */\n#define EXTI_PR_PR3_Pos                     (3U)                               \n#define EXTI_PR_PR3_Msk                     (0x1UL << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */\n#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */\n#define EXTI_PR_PR4_Pos                     (4U)                               \n#define EXTI_PR_PR4_Msk                     (0x1UL << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */\n#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */\n#define EXTI_PR_PR5_Pos                     (5U)                               \n#define EXTI_PR_PR5_Msk                     (0x1UL << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */\n#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */\n#define EXTI_PR_PR6_Pos                     (6U)                               \n#define EXTI_PR_PR6_Msk                     (0x1UL << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */\n#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */\n#define EXTI_PR_PR7_Pos                     (7U)                               \n#define EXTI_PR_PR7_Msk                     (0x1UL << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */\n#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */\n#define EXTI_PR_PR8_Pos                     (8U)                               \n#define EXTI_PR_PR8_Msk                     (0x1UL << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */\n#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */\n#define EXTI_PR_PR9_Pos                     (9U)                               \n#define EXTI_PR_PR9_Msk                     (0x1UL << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */\n#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */\n#define EXTI_PR_PR10_Pos                    (10U)                              \n#define EXTI_PR_PR10_Msk                    (0x1UL << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */\n#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */\n#define EXTI_PR_PR11_Pos                    (11U)                              \n#define EXTI_PR_PR11_Msk                    (0x1UL << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */\n#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */\n#define EXTI_PR_PR12_Pos                    (12U)                              \n#define EXTI_PR_PR12_Msk                    (0x1UL << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */\n#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */\n#define EXTI_PR_PR13_Pos                    (13U)                              \n#define EXTI_PR_PR13_Msk                    (0x1UL << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */\n#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */\n#define EXTI_PR_PR14_Pos                    (14U)                              \n#define EXTI_PR_PR14_Msk                    (0x1UL << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */\n#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */\n#define EXTI_PR_PR15_Pos                    (15U)                              \n#define EXTI_PR_PR15_Msk                    (0x1UL << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */\n#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */\n#define EXTI_PR_PR16_Pos                    (16U)                              \n#define EXTI_PR_PR16_Msk                    (0x1UL << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */\n#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */\n#define EXTI_PR_PR17_Pos                    (17U)                              \n#define EXTI_PR_PR17_Msk                    (0x1UL << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */\n#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */\n#define EXTI_PR_PR18_Pos                    (18U)                              \n#define EXTI_PR_PR18_Msk                    (0x1UL << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */\n#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */\n\n/* References Defines */\n#define  EXTI_PR_PIF0 EXTI_PR_PR0\n#define  EXTI_PR_PIF1 EXTI_PR_PR1\n#define  EXTI_PR_PIF2 EXTI_PR_PR2\n#define  EXTI_PR_PIF3 EXTI_PR_PR3\n#define  EXTI_PR_PIF4 EXTI_PR_PR4\n#define  EXTI_PR_PIF5 EXTI_PR_PR5\n#define  EXTI_PR_PIF6 EXTI_PR_PR6\n#define  EXTI_PR_PIF7 EXTI_PR_PR7\n#define  EXTI_PR_PIF8 EXTI_PR_PR8\n#define  EXTI_PR_PIF9 EXTI_PR_PR9\n#define  EXTI_PR_PIF10 EXTI_PR_PR10\n#define  EXTI_PR_PIF11 EXTI_PR_PR11\n#define  EXTI_PR_PIF12 EXTI_PR_PR12\n#define  EXTI_PR_PIF13 EXTI_PR_PR13\n#define  EXTI_PR_PIF14 EXTI_PR_PR14\n#define  EXTI_PR_PIF15 EXTI_PR_PR15\n#define  EXTI_PR_PIF16 EXTI_PR_PR16\n#define  EXTI_PR_PIF17 EXTI_PR_PR17\n#define  EXTI_PR_PIF18 EXTI_PR_PR18\n\n/******************************************************************************/\n/*                                                                            */\n/*                             DMA Controller                                 */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for DMA_ISR register  ********************/\n#define DMA_ISR_GIF1_Pos                    (0U)                               \n#define DMA_ISR_GIF1_Msk                    (0x1UL << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */\n#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */\n#define DMA_ISR_TCIF1_Pos                   (1U)                               \n#define DMA_ISR_TCIF1_Msk                   (0x1UL << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */\n#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */\n#define DMA_ISR_HTIF1_Pos                   (2U)                               \n#define DMA_ISR_HTIF1_Msk                   (0x1UL << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */\n#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */\n#define DMA_ISR_TEIF1_Pos                   (3U)                               \n#define DMA_ISR_TEIF1_Msk                   (0x1UL << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */\n#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */\n#define DMA_ISR_GIF2_Pos                    (4U)                               \n#define DMA_ISR_GIF2_Msk                    (0x1UL << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */\n#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */\n#define DMA_ISR_TCIF2_Pos                   (5U)                               \n#define DMA_ISR_TCIF2_Msk                   (0x1UL << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */\n#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */\n#define DMA_ISR_HTIF2_Pos                   (6U)                               \n#define DMA_ISR_HTIF2_Msk                   (0x1UL << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */\n#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */\n#define DMA_ISR_TEIF2_Pos                   (7U)                               \n#define DMA_ISR_TEIF2_Msk                   (0x1UL << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */\n#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */\n#define DMA_ISR_GIF3_Pos                    (8U)                               \n#define DMA_ISR_GIF3_Msk                    (0x1UL << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */\n#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */\n#define DMA_ISR_TCIF3_Pos                   (9U)                               \n#define DMA_ISR_TCIF3_Msk                   (0x1UL << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */\n#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */\n#define DMA_ISR_HTIF3_Pos                   (10U)                              \n#define DMA_ISR_HTIF3_Msk                   (0x1UL << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */\n#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */\n#define DMA_ISR_TEIF3_Pos                   (11U)                              \n#define DMA_ISR_TEIF3_Msk                   (0x1UL << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */\n#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */\n#define DMA_ISR_GIF4_Pos                    (12U)                              \n#define DMA_ISR_GIF4_Msk                    (0x1UL << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */\n#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */\n#define DMA_ISR_TCIF4_Pos                   (13U)                              \n#define DMA_ISR_TCIF4_Msk                   (0x1UL << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */\n#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */\n#define DMA_ISR_HTIF4_Pos                   (14U)                              \n#define DMA_ISR_HTIF4_Msk                   (0x1UL << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */\n#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */\n#define DMA_ISR_TEIF4_Pos                   (15U)                              \n#define DMA_ISR_TEIF4_Msk                   (0x1UL << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */\n#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */\n#define DMA_ISR_GIF5_Pos                    (16U)                              \n#define DMA_ISR_GIF5_Msk                    (0x1UL << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */\n#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */\n#define DMA_ISR_TCIF5_Pos                   (17U)                              \n#define DMA_ISR_TCIF5_Msk                   (0x1UL << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */\n#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */\n#define DMA_ISR_HTIF5_Pos                   (18U)                              \n#define DMA_ISR_HTIF5_Msk                   (0x1UL << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */\n#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */\n#define DMA_ISR_TEIF5_Pos                   (19U)                              \n#define DMA_ISR_TEIF5_Msk                   (0x1UL << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */\n#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */\n#define DMA_ISR_GIF6_Pos                    (20U)                              \n#define DMA_ISR_GIF6_Msk                    (0x1UL << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */\n#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */\n#define DMA_ISR_TCIF6_Pos                   (21U)                              \n#define DMA_ISR_TCIF6_Msk                   (0x1UL << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */\n#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */\n#define DMA_ISR_HTIF6_Pos                   (22U)                              \n#define DMA_ISR_HTIF6_Msk                   (0x1UL << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */\n#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */\n#define DMA_ISR_TEIF6_Pos                   (23U)                              \n#define DMA_ISR_TEIF6_Msk                   (0x1UL << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */\n#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */\n#define DMA_ISR_GIF7_Pos                    (24U)                              \n#define DMA_ISR_GIF7_Msk                    (0x1UL << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */\n#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */\n#define DMA_ISR_TCIF7_Pos                   (25U)                              \n#define DMA_ISR_TCIF7_Msk                   (0x1UL << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */\n#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */\n#define DMA_ISR_HTIF7_Pos                   (26U)                              \n#define DMA_ISR_HTIF7_Msk                   (0x1UL << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */\n#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */\n#define DMA_ISR_TEIF7_Pos                   (27U)                              \n#define DMA_ISR_TEIF7_Msk                   (0x1UL << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */\n#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */\n\n/*******************  Bit definition for DMA_IFCR register  *******************/\n#define DMA_IFCR_CGIF1_Pos                  (0U)                               \n#define DMA_IFCR_CGIF1_Msk                  (0x1UL << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */\n#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */\n#define DMA_IFCR_CTCIF1_Pos                 (1U)                               \n#define DMA_IFCR_CTCIF1_Msk                 (0x1UL << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */\n#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */\n#define DMA_IFCR_CHTIF1_Pos                 (2U)                               \n#define DMA_IFCR_CHTIF1_Msk                 (0x1UL << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */\n#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */\n#define DMA_IFCR_CTEIF1_Pos                 (3U)                               \n#define DMA_IFCR_CTEIF1_Msk                 (0x1UL << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */\n#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */\n#define DMA_IFCR_CGIF2_Pos                  (4U)                               \n#define DMA_IFCR_CGIF2_Msk                  (0x1UL << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */\n#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */\n#define DMA_IFCR_CTCIF2_Pos                 (5U)                               \n#define DMA_IFCR_CTCIF2_Msk                 (0x1UL << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */\n#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */\n#define DMA_IFCR_CHTIF2_Pos                 (6U)                               \n#define DMA_IFCR_CHTIF2_Msk                 (0x1UL << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */\n#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */\n#define DMA_IFCR_CTEIF2_Pos                 (7U)                               \n#define DMA_IFCR_CTEIF2_Msk                 (0x1UL << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */\n#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */\n#define DMA_IFCR_CGIF3_Pos                  (8U)                               \n#define DMA_IFCR_CGIF3_Msk                  (0x1UL << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */\n#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */\n#define DMA_IFCR_CTCIF3_Pos                 (9U)                               \n#define DMA_IFCR_CTCIF3_Msk                 (0x1UL << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */\n#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */\n#define DMA_IFCR_CHTIF3_Pos                 (10U)                              \n#define DMA_IFCR_CHTIF3_Msk                 (0x1UL << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */\n#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */\n#define DMA_IFCR_CTEIF3_Pos                 (11U)                              \n#define DMA_IFCR_CTEIF3_Msk                 (0x1UL << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */\n#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */\n#define DMA_IFCR_CGIF4_Pos                  (12U)                              \n#define DMA_IFCR_CGIF4_Msk                  (0x1UL << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */\n#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */\n#define DMA_IFCR_CTCIF4_Pos                 (13U)                              \n#define DMA_IFCR_CTCIF4_Msk                 (0x1UL << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */\n#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */\n#define DMA_IFCR_CHTIF4_Pos                 (14U)                              \n#define DMA_IFCR_CHTIF4_Msk                 (0x1UL << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */\n#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */\n#define DMA_IFCR_CTEIF4_Pos                 (15U)                              \n#define DMA_IFCR_CTEIF4_Msk                 (0x1UL << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */\n#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */\n#define DMA_IFCR_CGIF5_Pos                  (16U)                              \n#define DMA_IFCR_CGIF5_Msk                  (0x1UL << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */\n#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */\n#define DMA_IFCR_CTCIF5_Pos                 (17U)                              \n#define DMA_IFCR_CTCIF5_Msk                 (0x1UL << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */\n#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */\n#define DMA_IFCR_CHTIF5_Pos                 (18U)                              \n#define DMA_IFCR_CHTIF5_Msk                 (0x1UL << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */\n#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */\n#define DMA_IFCR_CTEIF5_Pos                 (19U)                              \n#define DMA_IFCR_CTEIF5_Msk                 (0x1UL << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */\n#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */\n#define DMA_IFCR_CGIF6_Pos                  (20U)                              \n#define DMA_IFCR_CGIF6_Msk                  (0x1UL << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */\n#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */\n#define DMA_IFCR_CTCIF6_Pos                 (21U)                              \n#define DMA_IFCR_CTCIF6_Msk                 (0x1UL << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */\n#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */\n#define DMA_IFCR_CHTIF6_Pos                 (22U)                              \n#define DMA_IFCR_CHTIF6_Msk                 (0x1UL << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */\n#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */\n#define DMA_IFCR_CTEIF6_Pos                 (23U)                              \n#define DMA_IFCR_CTEIF6_Msk                 (0x1UL << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */\n#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */\n#define DMA_IFCR_CGIF7_Pos                  (24U)                              \n#define DMA_IFCR_CGIF7_Msk                  (0x1UL << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */\n#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */\n#define DMA_IFCR_CTCIF7_Pos                 (25U)                              \n#define DMA_IFCR_CTCIF7_Msk                 (0x1UL << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */\n#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */\n#define DMA_IFCR_CHTIF7_Pos                 (26U)                              \n#define DMA_IFCR_CHTIF7_Msk                 (0x1UL << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */\n#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */\n#define DMA_IFCR_CTEIF7_Pos                 (27U)                              \n#define DMA_IFCR_CTEIF7_Msk                 (0x1UL << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */\n#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */\n\n/*******************  Bit definition for DMA_CCR register   *******************/\n#define DMA_CCR_EN_Pos                      (0U)                               \n#define DMA_CCR_EN_Msk                      (0x1UL << DMA_CCR_EN_Pos)           /*!< 0x00000001 */\n#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable */\n#define DMA_CCR_TCIE_Pos                    (1U)                               \n#define DMA_CCR_TCIE_Msk                    (0x1UL << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */\n#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */\n#define DMA_CCR_HTIE_Pos                    (2U)                               \n#define DMA_CCR_HTIE_Msk                    (0x1UL << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */\n#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */\n#define DMA_CCR_TEIE_Pos                    (3U)                               \n#define DMA_CCR_TEIE_Msk                    (0x1UL << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */\n#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */\n#define DMA_CCR_DIR_Pos                     (4U)                               \n#define DMA_CCR_DIR_Msk                     (0x1UL << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */\n#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */\n#define DMA_CCR_CIRC_Pos                    (5U)                               \n#define DMA_CCR_CIRC_Msk                    (0x1UL << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */\n#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */\n#define DMA_CCR_PINC_Pos                    (6U)                               \n#define DMA_CCR_PINC_Msk                    (0x1UL << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */\n#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */\n#define DMA_CCR_MINC_Pos                    (7U)                               \n#define DMA_CCR_MINC_Msk                    (0x1UL << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */\n#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */\n\n#define DMA_CCR_PSIZE_Pos                   (8U)                               \n#define DMA_CCR_PSIZE_Msk                   (0x3UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */\n#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */\n#define DMA_CCR_PSIZE_0                     (0x1UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */\n#define DMA_CCR_PSIZE_1                     (0x2UL << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */\n\n#define DMA_CCR_MSIZE_Pos                   (10U)                              \n#define DMA_CCR_MSIZE_Msk                   (0x3UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */\n#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */\n#define DMA_CCR_MSIZE_0                     (0x1UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */\n#define DMA_CCR_MSIZE_1                     (0x2UL << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */\n\n#define DMA_CCR_PL_Pos                      (12U)                              \n#define DMA_CCR_PL_Msk                      (0x3UL << DMA_CCR_PL_Pos)           /*!< 0x00003000 */\n#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */\n#define DMA_CCR_PL_0                        (0x1UL << DMA_CCR_PL_Pos)           /*!< 0x00001000 */\n#define DMA_CCR_PL_1                        (0x2UL << DMA_CCR_PL_Pos)           /*!< 0x00002000 */\n\n#define DMA_CCR_MEM2MEM_Pos                 (14U)                              \n#define DMA_CCR_MEM2MEM_Msk                 (0x1UL << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */\n#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */\n\n/******************  Bit definition for DMA_CNDTR  register  ******************/\n#define DMA_CNDTR_NDT_Pos                   (0U)                               \n#define DMA_CNDTR_NDT_Msk                   (0xFFFFUL << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */\n#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */\n\n/******************  Bit definition for DMA_CPAR  register  *******************/\n#define DMA_CPAR_PA_Pos                     (0U)                               \n#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */\n#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */\n\n/******************  Bit definition for DMA_CMAR  register  *******************/\n#define DMA_CMAR_MA_Pos                     (0U)                               \n#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */\n#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Analog to Digital Converter (ADC)                     */\n/*                                                                            */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)\n */\n#define ADC_MULTIMODE_SUPPORT                          /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/********************  Bit definition for ADC_SR register  ********************/\n#define ADC_SR_AWD_Pos                      (0U)                               \n#define ADC_SR_AWD_Msk                      (0x1UL << ADC_SR_AWD_Pos)           /*!< 0x00000001 */\n#define ADC_SR_AWD                          ADC_SR_AWD_Msk                     /*!< ADC analog watchdog 1 flag */\n#define ADC_SR_EOS_Pos                      (1U)                               \n#define ADC_SR_EOS_Msk                      (0x1UL << ADC_SR_EOS_Pos)           /*!< 0x00000002 */\n#define ADC_SR_EOS                          ADC_SR_EOS_Msk                     /*!< ADC group regular end of sequence conversions flag */\n#define ADC_SR_JEOS_Pos                     (2U)                               \n#define ADC_SR_JEOS_Msk                     (0x1UL << ADC_SR_JEOS_Pos)          /*!< 0x00000004 */\n#define ADC_SR_JEOS                         ADC_SR_JEOS_Msk                    /*!< ADC group injected end of sequence conversions flag */\n#define ADC_SR_JSTRT_Pos                    (3U)                               \n#define ADC_SR_JSTRT_Msk                    (0x1UL << ADC_SR_JSTRT_Pos)         /*!< 0x00000008 */\n#define ADC_SR_JSTRT                        ADC_SR_JSTRT_Msk                   /*!< ADC group injected conversion start flag */\n#define ADC_SR_STRT_Pos                     (4U)                               \n#define ADC_SR_STRT_Msk                     (0x1UL << ADC_SR_STRT_Pos)          /*!< 0x00000010 */\n#define ADC_SR_STRT                         ADC_SR_STRT_Msk                    /*!< ADC group regular conversion start flag */\n\n/* Legacy defines */\n#define  ADC_SR_EOC                          (ADC_SR_EOS)\n#define  ADC_SR_JEOC                         (ADC_SR_JEOS)\n\n/*******************  Bit definition for ADC_CR1 register  ********************/\n#define ADC_CR1_AWDCH_Pos                   (0U)                               \n#define ADC_CR1_AWDCH_Msk                   (0x1FUL << ADC_CR1_AWDCH_Pos)       /*!< 0x0000001F */\n#define ADC_CR1_AWDCH                       ADC_CR1_AWDCH_Msk                  /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CR1_AWDCH_0                     (0x01UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000001 */\n#define ADC_CR1_AWDCH_1                     (0x02UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000002 */\n#define ADC_CR1_AWDCH_2                     (0x04UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000004 */\n#define ADC_CR1_AWDCH_3                     (0x08UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000008 */\n#define ADC_CR1_AWDCH_4                     (0x10UL << ADC_CR1_AWDCH_Pos)       /*!< 0x00000010 */\n\n#define ADC_CR1_EOSIE_Pos                   (5U)                               \n#define ADC_CR1_EOSIE_Msk                   (0x1UL << ADC_CR1_EOSIE_Pos)        /*!< 0x00000020 */\n#define ADC_CR1_EOSIE                       ADC_CR1_EOSIE_Msk                  /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_CR1_AWDIE_Pos                   (6U)                               \n#define ADC_CR1_AWDIE_Msk                   (0x1UL << ADC_CR1_AWDIE_Pos)        /*!< 0x00000040 */\n#define ADC_CR1_AWDIE                       ADC_CR1_AWDIE_Msk                  /*!< ADC analog watchdog 1 interrupt */\n#define ADC_CR1_JEOSIE_Pos                  (7U)                               \n#define ADC_CR1_JEOSIE_Msk                  (0x1UL << ADC_CR1_JEOSIE_Pos)       /*!< 0x00000080 */\n#define ADC_CR1_JEOSIE                      ADC_CR1_JEOSIE_Msk                 /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_CR1_SCAN_Pos                    (8U)                               \n#define ADC_CR1_SCAN_Msk                    (0x1UL << ADC_CR1_SCAN_Pos)         /*!< 0x00000100 */\n#define ADC_CR1_SCAN                        ADC_CR1_SCAN_Msk                   /*!< ADC scan mode */\n#define ADC_CR1_AWDSGL_Pos                  (9U)                               \n#define ADC_CR1_AWDSGL_Msk                  (0x1UL << ADC_CR1_AWDSGL_Pos)       /*!< 0x00000200 */\n#define ADC_CR1_AWDSGL                      ADC_CR1_AWDSGL_Msk                 /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CR1_JAUTO_Pos                   (10U)                              \n#define ADC_CR1_JAUTO_Msk                   (0x1UL << ADC_CR1_JAUTO_Pos)        /*!< 0x00000400 */\n#define ADC_CR1_JAUTO                       ADC_CR1_JAUTO_Msk                  /*!< ADC group injected automatic trigger mode */\n#define ADC_CR1_DISCEN_Pos                  (11U)                              \n#define ADC_CR1_DISCEN_Msk                  (0x1UL << ADC_CR1_DISCEN_Pos)       /*!< 0x00000800 */\n#define ADC_CR1_DISCEN                      ADC_CR1_DISCEN_Msk                 /*!< ADC group regular sequencer discontinuous mode */\n#define ADC_CR1_JDISCEN_Pos                 (12U)                              \n#define ADC_CR1_JDISCEN_Msk                 (0x1UL << ADC_CR1_JDISCEN_Pos)      /*!< 0x00001000 */\n#define ADC_CR1_JDISCEN                     ADC_CR1_JDISCEN_Msk                /*!< ADC group injected sequencer discontinuous mode */\n\n#define ADC_CR1_DISCNUM_Pos                 (13U)                              \n#define ADC_CR1_DISCNUM_Msk                 (0x7UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x0000E000 */\n#define ADC_CR1_DISCNUM                     ADC_CR1_DISCNUM_Msk                /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CR1_DISCNUM_0                   (0x1UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00002000 */\n#define ADC_CR1_DISCNUM_1                   (0x2UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00004000 */\n#define ADC_CR1_DISCNUM_2                   (0x4UL << ADC_CR1_DISCNUM_Pos)      /*!< 0x00008000 */\n\n#define ADC_CR1_DUALMOD_Pos                 (16U)                              \n#define ADC_CR1_DUALMOD_Msk                 (0xFUL << ADC_CR1_DUALMOD_Pos)      /*!< 0x000F0000 */\n#define ADC_CR1_DUALMOD                     ADC_CR1_DUALMOD_Msk                /*!< ADC multimode mode selection */\n#define ADC_CR1_DUALMOD_0                   (0x1UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00010000 */\n#define ADC_CR1_DUALMOD_1                   (0x2UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00020000 */\n#define ADC_CR1_DUALMOD_2                   (0x4UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00040000 */\n#define ADC_CR1_DUALMOD_3                   (0x8UL << ADC_CR1_DUALMOD_Pos)      /*!< 0x00080000 */\n\n#define ADC_CR1_JAWDEN_Pos                  (22U)                              \n#define ADC_CR1_JAWDEN_Msk                  (0x1UL << ADC_CR1_JAWDEN_Pos)       /*!< 0x00400000 */\n#define ADC_CR1_JAWDEN                      ADC_CR1_JAWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CR1_AWDEN_Pos                   (23U)                              \n#define ADC_CR1_AWDEN_Msk                   (0x1UL << ADC_CR1_AWDEN_Pos)        /*!< 0x00800000 */\n#define ADC_CR1_AWDEN                       ADC_CR1_AWDEN_Msk                  /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n\n/* Legacy defines */\n#define  ADC_CR1_EOCIE                       (ADC_CR1_EOSIE)\n#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)\n\n/*******************  Bit definition for ADC_CR2 register  ********************/\n#define ADC_CR2_ADON_Pos                    (0U)                               \n#define ADC_CR2_ADON_Msk                    (0x1UL << ADC_CR2_ADON_Pos)         /*!< 0x00000001 */\n#define ADC_CR2_ADON                        ADC_CR2_ADON_Msk                   /*!< ADC enable */\n#define ADC_CR2_CONT_Pos                    (1U)                               \n#define ADC_CR2_CONT_Msk                    (0x1UL << ADC_CR2_CONT_Pos)         /*!< 0x00000002 */\n#define ADC_CR2_CONT                        ADC_CR2_CONT_Msk                   /*!< ADC group regular continuous conversion mode */\n#define ADC_CR2_CAL_Pos                     (2U)                               \n#define ADC_CR2_CAL_Msk                     (0x1UL << ADC_CR2_CAL_Pos)          /*!< 0x00000004 */\n#define ADC_CR2_CAL                         ADC_CR2_CAL_Msk                    /*!< ADC calibration start */\n#define ADC_CR2_RSTCAL_Pos                  (3U)                               \n#define ADC_CR2_RSTCAL_Msk                  (0x1UL << ADC_CR2_RSTCAL_Pos)       /*!< 0x00000008 */\n#define ADC_CR2_RSTCAL                      ADC_CR2_RSTCAL_Msk                 /*!< ADC calibration reset */\n#define ADC_CR2_DMA_Pos                     (8U)                               \n#define ADC_CR2_DMA_Msk                     (0x1UL << ADC_CR2_DMA_Pos)          /*!< 0x00000100 */\n#define ADC_CR2_DMA                         ADC_CR2_DMA_Msk                    /*!< ADC DMA transfer enable */\n#define ADC_CR2_ALIGN_Pos                   (11U)                              \n#define ADC_CR2_ALIGN_Msk                   (0x1UL << ADC_CR2_ALIGN_Pos)        /*!< 0x00000800 */\n#define ADC_CR2_ALIGN                       ADC_CR2_ALIGN_Msk                  /*!< ADC data alignement */\n\n#define ADC_CR2_JEXTSEL_Pos                 (12U)                              \n#define ADC_CR2_JEXTSEL_Msk                 (0x7UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00007000 */\n#define ADC_CR2_JEXTSEL                     ADC_CR2_JEXTSEL_Msk                /*!< ADC group injected external trigger source */\n#define ADC_CR2_JEXTSEL_0                   (0x1UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00001000 */\n#define ADC_CR2_JEXTSEL_1                   (0x2UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00002000 */\n#define ADC_CR2_JEXTSEL_2                   (0x4UL << ADC_CR2_JEXTSEL_Pos)      /*!< 0x00004000 */\n\n#define ADC_CR2_JEXTTRIG_Pos                (15U)                              \n#define ADC_CR2_JEXTTRIG_Msk                (0x1UL << ADC_CR2_JEXTTRIG_Pos)     /*!< 0x00008000 */\n#define ADC_CR2_JEXTTRIG                    ADC_CR2_JEXTTRIG_Msk               /*!< ADC group injected external trigger enable */\n\n#define ADC_CR2_EXTSEL_Pos                  (17U)                              \n#define ADC_CR2_EXTSEL_Msk                  (0x7UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x000E0000 */\n#define ADC_CR2_EXTSEL                      ADC_CR2_EXTSEL_Msk                 /*!< ADC group regular external trigger source */\n#define ADC_CR2_EXTSEL_0                    (0x1UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00020000 */\n#define ADC_CR2_EXTSEL_1                    (0x2UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00040000 */\n#define ADC_CR2_EXTSEL_2                    (0x4UL << ADC_CR2_EXTSEL_Pos)       /*!< 0x00080000 */\n\n#define ADC_CR2_EXTTRIG_Pos                 (20U)                              \n#define ADC_CR2_EXTTRIG_Msk                 (0x1UL << ADC_CR2_EXTTRIG_Pos)      /*!< 0x00100000 */\n#define ADC_CR2_EXTTRIG                     ADC_CR2_EXTTRIG_Msk                /*!< ADC group regular external trigger enable */\n#define ADC_CR2_JSWSTART_Pos                (21U)                              \n#define ADC_CR2_JSWSTART_Msk                (0x1UL << ADC_CR2_JSWSTART_Pos)     /*!< 0x00200000 */\n#define ADC_CR2_JSWSTART                    ADC_CR2_JSWSTART_Msk               /*!< ADC group injected conversion start */\n#define ADC_CR2_SWSTART_Pos                 (22U)                              \n#define ADC_CR2_SWSTART_Msk                 (0x1UL << ADC_CR2_SWSTART_Pos)      /*!< 0x00400000 */\n#define ADC_CR2_SWSTART                     ADC_CR2_SWSTART_Msk                /*!< ADC group regular conversion start */\n#define ADC_CR2_TSVREFE_Pos                 (23U)                              \n#define ADC_CR2_TSVREFE_Msk                 (0x1UL << ADC_CR2_TSVREFE_Pos)      /*!< 0x00800000 */\n#define ADC_CR2_TSVREFE                     ADC_CR2_TSVREFE_Msk                /*!< ADC internal path to VrefInt and temperature sensor enable */\n\n/******************  Bit definition for ADC_SMPR1 register  *******************/\n#define ADC_SMPR1_SMP10_Pos                 (0U)                               \n#define ADC_SMPR1_SMP10_Msk                 (0x7UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000007 */\n#define ADC_SMPR1_SMP10                     ADC_SMPR1_SMP10_Msk                /*!< ADC channel 10 sampling time selection  */\n#define ADC_SMPR1_SMP10_0                   (0x1UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000001 */\n#define ADC_SMPR1_SMP10_1                   (0x2UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000002 */\n#define ADC_SMPR1_SMP10_2                   (0x4UL << ADC_SMPR1_SMP10_Pos)      /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP11_Pos                 (3U)                               \n#define ADC_SMPR1_SMP11_Msk                 (0x7UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000038 */\n#define ADC_SMPR1_SMP11                     ADC_SMPR1_SMP11_Msk                /*!< ADC channel 11 sampling time selection  */\n#define ADC_SMPR1_SMP11_0                   (0x1UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000008 */\n#define ADC_SMPR1_SMP11_1                   (0x2UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000010 */\n#define ADC_SMPR1_SMP11_2                   (0x4UL << ADC_SMPR1_SMP11_Pos)      /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP12_Pos                 (6U)                               \n#define ADC_SMPR1_SMP12_Msk                 (0x7UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP12                     ADC_SMPR1_SMP12_Msk                /*!< ADC channel 12 sampling time selection  */\n#define ADC_SMPR1_SMP12_0                   (0x1UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000040 */\n#define ADC_SMPR1_SMP12_1                   (0x2UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000080 */\n#define ADC_SMPR1_SMP12_2                   (0x4UL << ADC_SMPR1_SMP12_Pos)      /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP13_Pos                 (9U)                               \n#define ADC_SMPR1_SMP13_Msk                 (0x7UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP13                     ADC_SMPR1_SMP13_Msk                /*!< ADC channel 13 sampling time selection  */\n#define ADC_SMPR1_SMP13_0                   (0x1UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000200 */\n#define ADC_SMPR1_SMP13_1                   (0x2UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000400 */\n#define ADC_SMPR1_SMP13_2                   (0x4UL << ADC_SMPR1_SMP13_Pos)      /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP14_Pos                 (12U)                              \n#define ADC_SMPR1_SMP14_Msk                 (0x7UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00007000 */\n#define ADC_SMPR1_SMP14                     ADC_SMPR1_SMP14_Msk                /*!< ADC channel 14 sampling time selection  */\n#define ADC_SMPR1_SMP14_0                   (0x1UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00001000 */\n#define ADC_SMPR1_SMP14_1                   (0x2UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00002000 */\n#define ADC_SMPR1_SMP14_2                   (0x4UL << ADC_SMPR1_SMP14_Pos)      /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP15_Pos                 (15U)                              \n#define ADC_SMPR1_SMP15_Msk                 (0x7UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00038000 */\n#define ADC_SMPR1_SMP15                     ADC_SMPR1_SMP15_Msk                /*!< ADC channel 15 sampling time selection  */\n#define ADC_SMPR1_SMP15_0                   (0x1UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00008000 */\n#define ADC_SMPR1_SMP15_1                   (0x2UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00010000 */\n#define ADC_SMPR1_SMP15_2                   (0x4UL << ADC_SMPR1_SMP15_Pos)      /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP16_Pos                 (18U)                              \n#define ADC_SMPR1_SMP16_Msk                 (0x7UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP16                     ADC_SMPR1_SMP16_Msk                /*!< ADC channel 16 sampling time selection  */\n#define ADC_SMPR1_SMP16_0                   (0x1UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00040000 */\n#define ADC_SMPR1_SMP16_1                   (0x2UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00080000 */\n#define ADC_SMPR1_SMP16_2                   (0x4UL << ADC_SMPR1_SMP16_Pos)      /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP17_Pos                 (21U)                              \n#define ADC_SMPR1_SMP17_Msk                 (0x7UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP17                     ADC_SMPR1_SMP17_Msk                /*!< ADC channel 17 sampling time selection  */\n#define ADC_SMPR1_SMP17_0                   (0x1UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00200000 */\n#define ADC_SMPR1_SMP17_1                   (0x2UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00400000 */\n#define ADC_SMPR1_SMP17_2                   (0x4UL << ADC_SMPR1_SMP17_Pos)      /*!< 0x00800000 */\n\n/******************  Bit definition for ADC_SMPR2 register  *******************/\n#define ADC_SMPR2_SMP0_Pos                  (0U)                               \n#define ADC_SMPR2_SMP0_Msk                  (0x7UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000007 */\n#define ADC_SMPR2_SMP0                      ADC_SMPR2_SMP0_Msk                 /*!< ADC channel 0 sampling time selection  */\n#define ADC_SMPR2_SMP0_0                    (0x1UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000001 */\n#define ADC_SMPR2_SMP0_1                    (0x2UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000002 */\n#define ADC_SMPR2_SMP0_2                    (0x4UL << ADC_SMPR2_SMP0_Pos)       /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP1_Pos                  (3U)                               \n#define ADC_SMPR2_SMP1_Msk                  (0x7UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000038 */\n#define ADC_SMPR2_SMP1                      ADC_SMPR2_SMP1_Msk                 /*!< ADC channel 1 sampling time selection  */\n#define ADC_SMPR2_SMP1_0                    (0x1UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000008 */\n#define ADC_SMPR2_SMP1_1                    (0x2UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000010 */\n#define ADC_SMPR2_SMP1_2                    (0x4UL << ADC_SMPR2_SMP1_Pos)       /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP2_Pos                  (6U)                               \n#define ADC_SMPR2_SMP2_Msk                  (0x7UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP2                      ADC_SMPR2_SMP2_Msk                 /*!< ADC channel 2 sampling time selection  */\n#define ADC_SMPR2_SMP2_0                    (0x1UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000040 */\n#define ADC_SMPR2_SMP2_1                    (0x2UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000080 */\n#define ADC_SMPR2_SMP2_2                    (0x4UL << ADC_SMPR2_SMP2_Pos)       /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP3_Pos                  (9U)                               \n#define ADC_SMPR2_SMP3_Msk                  (0x7UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP3                      ADC_SMPR2_SMP3_Msk                 /*!< ADC channel 3 sampling time selection  */\n#define ADC_SMPR2_SMP3_0                    (0x1UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000200 */\n#define ADC_SMPR2_SMP3_1                    (0x2UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000400 */\n#define ADC_SMPR2_SMP3_2                    (0x4UL << ADC_SMPR2_SMP3_Pos)       /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP4_Pos                  (12U)                              \n#define ADC_SMPR2_SMP4_Msk                  (0x7UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00007000 */\n#define ADC_SMPR2_SMP4                      ADC_SMPR2_SMP4_Msk                 /*!< ADC channel 4 sampling time selection  */\n#define ADC_SMPR2_SMP4_0                    (0x1UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00001000 */\n#define ADC_SMPR2_SMP4_1                    (0x2UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00002000 */\n#define ADC_SMPR2_SMP4_2                    (0x4UL << ADC_SMPR2_SMP4_Pos)       /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP5_Pos                  (15U)                              \n#define ADC_SMPR2_SMP5_Msk                  (0x7UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00038000 */\n#define ADC_SMPR2_SMP5                      ADC_SMPR2_SMP5_Msk                 /*!< ADC channel 5 sampling time selection  */\n#define ADC_SMPR2_SMP5_0                    (0x1UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00008000 */\n#define ADC_SMPR2_SMP5_1                    (0x2UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00010000 */\n#define ADC_SMPR2_SMP5_2                    (0x4UL << ADC_SMPR2_SMP5_Pos)       /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP6_Pos                  (18U)                              \n#define ADC_SMPR2_SMP6_Msk                  (0x7UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP6                      ADC_SMPR2_SMP6_Msk                 /*!< ADC channel 6 sampling time selection  */\n#define ADC_SMPR2_SMP6_0                    (0x1UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00040000 */\n#define ADC_SMPR2_SMP6_1                    (0x2UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00080000 */\n#define ADC_SMPR2_SMP6_2                    (0x4UL << ADC_SMPR2_SMP6_Pos)       /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP7_Pos                  (21U)                              \n#define ADC_SMPR2_SMP7_Msk                  (0x7UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP7                      ADC_SMPR2_SMP7_Msk                 /*!< ADC channel 7 sampling time selection  */\n#define ADC_SMPR2_SMP7_0                    (0x1UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00200000 */\n#define ADC_SMPR2_SMP7_1                    (0x2UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00400000 */\n#define ADC_SMPR2_SMP7_2                    (0x4UL << ADC_SMPR2_SMP7_Pos)       /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP8_Pos                  (24U)                              \n#define ADC_SMPR2_SMP8_Msk                  (0x7UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x07000000 */\n#define ADC_SMPR2_SMP8                      ADC_SMPR2_SMP8_Msk                 /*!< ADC channel 8 sampling time selection  */\n#define ADC_SMPR2_SMP8_0                    (0x1UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x01000000 */\n#define ADC_SMPR2_SMP8_1                    (0x2UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x02000000 */\n#define ADC_SMPR2_SMP8_2                    (0x4UL << ADC_SMPR2_SMP8_Pos)       /*!< 0x04000000 */\n\n#define ADC_SMPR2_SMP9_Pos                  (27U)                              \n#define ADC_SMPR2_SMP9_Msk                  (0x7UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x38000000 */\n#define ADC_SMPR2_SMP9                      ADC_SMPR2_SMP9_Msk                 /*!< ADC channel 9 sampling time selection  */\n#define ADC_SMPR2_SMP9_0                    (0x1UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x08000000 */\n#define ADC_SMPR2_SMP9_1                    (0x2UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x10000000 */\n#define ADC_SMPR2_SMP9_2                    (0x4UL << ADC_SMPR2_SMP9_Pos)       /*!< 0x20000000 */\n\n/******************  Bit definition for ADC_JOFR1 register  *******************/\n#define ADC_JOFR1_JOFFSET1_Pos              (0U)                               \n#define ADC_JOFR1_JOFFSET1_Msk              (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR1_JOFFSET1                  ADC_JOFR1_JOFFSET1_Msk             /*!< ADC group injected sequencer rank 1 offset value */\n\n/******************  Bit definition for ADC_JOFR2 register  *******************/\n#define ADC_JOFR2_JOFFSET2_Pos              (0U)                               \n#define ADC_JOFR2_JOFFSET2_Msk              (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR2_JOFFSET2                  ADC_JOFR2_JOFFSET2_Msk             /*!< ADC group injected sequencer rank 2 offset value */\n\n/******************  Bit definition for ADC_JOFR3 register  *******************/\n#define ADC_JOFR3_JOFFSET3_Pos              (0U)                               \n#define ADC_JOFR3_JOFFSET3_Msk              (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR3_JOFFSET3                  ADC_JOFR3_JOFFSET3_Msk             /*!< ADC group injected sequencer rank 3 offset value */\n\n/******************  Bit definition for ADC_JOFR4 register  *******************/\n#define ADC_JOFR4_JOFFSET4_Pos              (0U)                               \n#define ADC_JOFR4_JOFFSET4_Msk              (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\n#define ADC_JOFR4_JOFFSET4                  ADC_JOFR4_JOFFSET4_Msk             /*!< ADC group injected sequencer rank 4 offset value */\n\n/*******************  Bit definition for ADC_HTR register  ********************/\n#define ADC_HTR_HT_Pos                      (0U)                               \n#define ADC_HTR_HT_Msk                      (0xFFFUL << ADC_HTR_HT_Pos)         /*!< 0x00000FFF */\n#define ADC_HTR_HT                          ADC_HTR_HT_Msk                     /*!< ADC analog watchdog 1 threshold high */\n\n/*******************  Bit definition for ADC_LTR register  ********************/\n#define ADC_LTR_LT_Pos                      (0U)                               \n#define ADC_LTR_LT_Msk                      (0xFFFUL << ADC_LTR_LT_Pos)         /*!< 0x00000FFF */\n#define ADC_LTR_LT                          ADC_LTR_LT_Msk                     /*!< ADC analog watchdog 1 threshold low */\n\n/*******************  Bit definition for ADC_SQR1 register  *******************/\n#define ADC_SQR1_SQ13_Pos                   (0U)                               \n#define ADC_SQR1_SQ13_Msk                   (0x1FUL << ADC_SQR1_SQ13_Pos)       /*!< 0x0000001F */\n#define ADC_SQR1_SQ13                       ADC_SQR1_SQ13_Msk                  /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR1_SQ13_0                     (0x01UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000001 */\n#define ADC_SQR1_SQ13_1                     (0x02UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000002 */\n#define ADC_SQR1_SQ13_2                     (0x04UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000004 */\n#define ADC_SQR1_SQ13_3                     (0x08UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000008 */\n#define ADC_SQR1_SQ13_4                     (0x10UL << ADC_SQR1_SQ13_Pos)       /*!< 0x00000010 */\n\n#define ADC_SQR1_SQ14_Pos                   (5U)                               \n#define ADC_SQR1_SQ14_Msk                   (0x1FUL << ADC_SQR1_SQ14_Pos)       /*!< 0x000003E0 */\n#define ADC_SQR1_SQ14                       ADC_SQR1_SQ14_Msk                  /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR1_SQ14_0                     (0x01UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000020 */\n#define ADC_SQR1_SQ14_1                     (0x02UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000040 */\n#define ADC_SQR1_SQ14_2                     (0x04UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000080 */\n#define ADC_SQR1_SQ14_3                     (0x08UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000100 */\n#define ADC_SQR1_SQ14_4                     (0x10UL << ADC_SQR1_SQ14_Pos)       /*!< 0x00000200 */\n\n#define ADC_SQR1_SQ15_Pos                   (10U)                              \n#define ADC_SQR1_SQ15_Msk                   (0x1FUL << ADC_SQR1_SQ15_Pos)       /*!< 0x00007C00 */\n#define ADC_SQR1_SQ15                       ADC_SQR1_SQ15_Msk                  /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR1_SQ15_0                     (0x01UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000400 */\n#define ADC_SQR1_SQ15_1                     (0x02UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00000800 */\n#define ADC_SQR1_SQ15_2                     (0x04UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00001000 */\n#define ADC_SQR1_SQ15_3                     (0x08UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00002000 */\n#define ADC_SQR1_SQ15_4                     (0x10UL << ADC_SQR1_SQ15_Pos)       /*!< 0x00004000 */\n\n#define ADC_SQR1_SQ16_Pos                   (15U)                              \n#define ADC_SQR1_SQ16_Msk                   (0x1FUL << ADC_SQR1_SQ16_Pos)       /*!< 0x000F8000 */\n#define ADC_SQR1_SQ16                       ADC_SQR1_SQ16_Msk                  /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR1_SQ16_0                     (0x01UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00008000 */\n#define ADC_SQR1_SQ16_1                     (0x02UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00010000 */\n#define ADC_SQR1_SQ16_2                     (0x04UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00020000 */\n#define ADC_SQR1_SQ16_3                     (0x08UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00040000 */\n#define ADC_SQR1_SQ16_4                     (0x10UL << ADC_SQR1_SQ16_Pos)       /*!< 0x00080000 */\n\n#define ADC_SQR1_L_Pos                      (20U)                              \n#define ADC_SQR1_L_Msk                      (0xFUL << ADC_SQR1_L_Pos)           /*!< 0x00F00000 */\n#define ADC_SQR1_L                          ADC_SQR1_L_Msk                     /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0                        (0x1UL << ADC_SQR1_L_Pos)           /*!< 0x00100000 */\n#define ADC_SQR1_L_1                        (0x2UL << ADC_SQR1_L_Pos)           /*!< 0x00200000 */\n#define ADC_SQR1_L_2                        (0x4UL << ADC_SQR1_L_Pos)           /*!< 0x00400000 */\n#define ADC_SQR1_L_3                        (0x8UL << ADC_SQR1_L_Pos)           /*!< 0x00800000 */\n\n/*******************  Bit definition for ADC_SQR2 register  *******************/\n#define ADC_SQR2_SQ7_Pos                    (0U)                               \n#define ADC_SQR2_SQ7_Msk                    (0x1FUL << ADC_SQR2_SQ7_Pos)        /*!< 0x0000001F */\n#define ADC_SQR2_SQ7                        ADC_SQR2_SQ7_Msk                   /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0                      (0x01UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000001 */\n#define ADC_SQR2_SQ7_1                      (0x02UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000002 */\n#define ADC_SQR2_SQ7_2                      (0x04UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000004 */\n#define ADC_SQR2_SQ7_3                      (0x08UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000008 */\n#define ADC_SQR2_SQ7_4                      (0x10UL << ADC_SQR2_SQ7_Pos)        /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ8_Pos                    (5U)                               \n#define ADC_SQR2_SQ8_Msk                    (0x1FUL << ADC_SQR2_SQ8_Pos)        /*!< 0x000003E0 */\n#define ADC_SQR2_SQ8                        ADC_SQR2_SQ8_Msk                   /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0                      (0x01UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000020 */\n#define ADC_SQR2_SQ8_1                      (0x02UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000040 */\n#define ADC_SQR2_SQ8_2                      (0x04UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000080 */\n#define ADC_SQR2_SQ8_3                      (0x08UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000100 */\n#define ADC_SQR2_SQ8_4                      (0x10UL << ADC_SQR2_SQ8_Pos)        /*!< 0x00000200 */\n\n#define ADC_SQR2_SQ9_Pos                    (10U)                              \n#define ADC_SQR2_SQ9_Msk                    (0x1FUL << ADC_SQR2_SQ9_Pos)        /*!< 0x00007C00 */\n#define ADC_SQR2_SQ9                        ADC_SQR2_SQ9_Msk                   /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0                      (0x01UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000400 */\n#define ADC_SQR2_SQ9_1                      (0x02UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00000800 */\n#define ADC_SQR2_SQ9_2                      (0x04UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00001000 */\n#define ADC_SQR2_SQ9_3                      (0x08UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00002000 */\n#define ADC_SQR2_SQ9_4                      (0x10UL << ADC_SQR2_SQ9_Pos)        /*!< 0x00004000 */\n\n#define ADC_SQR2_SQ10_Pos                   (15U)                              \n#define ADC_SQR2_SQ10_Msk                   (0x1FUL << ADC_SQR2_SQ10_Pos)       /*!< 0x000F8000 */\n#define ADC_SQR2_SQ10                       ADC_SQR2_SQ10_Msk                  /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR2_SQ10_0                     (0x01UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00008000 */\n#define ADC_SQR2_SQ10_1                     (0x02UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00010000 */\n#define ADC_SQR2_SQ10_2                     (0x04UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00020000 */\n#define ADC_SQR2_SQ10_3                     (0x08UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00040000 */\n#define ADC_SQR2_SQ10_4                     (0x10UL << ADC_SQR2_SQ10_Pos)       /*!< 0x00080000 */\n\n#define ADC_SQR2_SQ11_Pos                   (20U)                              \n#define ADC_SQR2_SQ11_Msk                   (0x1FUL << ADC_SQR2_SQ11_Pos)       /*!< 0x01F00000 */\n#define ADC_SQR2_SQ11                       ADC_SQR2_SQ11_Msk                  /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR2_SQ11_0                     (0x01UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00100000 */\n#define ADC_SQR2_SQ11_1                     (0x02UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00200000 */\n#define ADC_SQR2_SQ11_2                     (0x04UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00400000 */\n#define ADC_SQR2_SQ11_3                     (0x08UL << ADC_SQR2_SQ11_Pos)       /*!< 0x00800000 */\n#define ADC_SQR2_SQ11_4                     (0x10UL << ADC_SQR2_SQ11_Pos)       /*!< 0x01000000 */\n\n#define ADC_SQR2_SQ12_Pos                   (25U)                              \n#define ADC_SQR2_SQ12_Msk                   (0x1FUL << ADC_SQR2_SQ12_Pos)       /*!< 0x3E000000 */\n#define ADC_SQR2_SQ12                       ADC_SQR2_SQ12_Msk                  /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR2_SQ12_0                     (0x01UL << ADC_SQR2_SQ12_Pos)       /*!< 0x02000000 */\n#define ADC_SQR2_SQ12_1                     (0x02UL << ADC_SQR2_SQ12_Pos)       /*!< 0x04000000 */\n#define ADC_SQR2_SQ12_2                     (0x04UL << ADC_SQR2_SQ12_Pos)       /*!< 0x08000000 */\n#define ADC_SQR2_SQ12_3                     (0x08UL << ADC_SQR2_SQ12_Pos)       /*!< 0x10000000 */\n#define ADC_SQR2_SQ12_4                     (0x10UL << ADC_SQR2_SQ12_Pos)       /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_SQR3 register  *******************/\n#define ADC_SQR3_SQ1_Pos                    (0U)                               \n#define ADC_SQR3_SQ1_Msk                    (0x1FUL << ADC_SQR3_SQ1_Pos)        /*!< 0x0000001F */\n#define ADC_SQR3_SQ1                        ADC_SQR3_SQ1_Msk                   /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR3_SQ1_0                      (0x01UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000001 */\n#define ADC_SQR3_SQ1_1                      (0x02UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000002 */\n#define ADC_SQR3_SQ1_2                      (0x04UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000004 */\n#define ADC_SQR3_SQ1_3                      (0x08UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000008 */\n#define ADC_SQR3_SQ1_4                      (0x10UL << ADC_SQR3_SQ1_Pos)        /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ2_Pos                    (5U)                               \n#define ADC_SQR3_SQ2_Msk                    (0x1FUL << ADC_SQR3_SQ2_Pos)        /*!< 0x000003E0 */\n#define ADC_SQR3_SQ2                        ADC_SQR3_SQ2_Msk                   /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR3_SQ2_0                      (0x01UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000020 */\n#define ADC_SQR3_SQ2_1                      (0x02UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000040 */\n#define ADC_SQR3_SQ2_2                      (0x04UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000080 */\n#define ADC_SQR3_SQ2_3                      (0x08UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000100 */\n#define ADC_SQR3_SQ2_4                      (0x10UL << ADC_SQR3_SQ2_Pos)        /*!< 0x00000200 */\n\n#define ADC_SQR3_SQ3_Pos                    (10U)                              \n#define ADC_SQR3_SQ3_Msk                    (0x1FUL << ADC_SQR3_SQ3_Pos)        /*!< 0x00007C00 */\n#define ADC_SQR3_SQ3                        ADC_SQR3_SQ3_Msk                   /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR3_SQ3_0                      (0x01UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000400 */\n#define ADC_SQR3_SQ3_1                      (0x02UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00000800 */\n#define ADC_SQR3_SQ3_2                      (0x04UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00001000 */\n#define ADC_SQR3_SQ3_3                      (0x08UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00002000 */\n#define ADC_SQR3_SQ3_4                      (0x10UL << ADC_SQR3_SQ3_Pos)        /*!< 0x00004000 */\n\n#define ADC_SQR3_SQ4_Pos                    (15U)                              \n#define ADC_SQR3_SQ4_Msk                    (0x1FUL << ADC_SQR3_SQ4_Pos)        /*!< 0x000F8000 */\n#define ADC_SQR3_SQ4                        ADC_SQR3_SQ4_Msk                   /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR3_SQ4_0                      (0x01UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00008000 */\n#define ADC_SQR3_SQ4_1                      (0x02UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00010000 */\n#define ADC_SQR3_SQ4_2                      (0x04UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00020000 */\n#define ADC_SQR3_SQ4_3                      (0x08UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00040000 */\n#define ADC_SQR3_SQ4_4                      (0x10UL << ADC_SQR3_SQ4_Pos)        /*!< 0x00080000 */\n\n#define ADC_SQR3_SQ5_Pos                    (20U)                              \n#define ADC_SQR3_SQ5_Msk                    (0x1FUL << ADC_SQR3_SQ5_Pos)        /*!< 0x01F00000 */\n#define ADC_SQR3_SQ5                        ADC_SQR3_SQ5_Msk                   /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR3_SQ5_0                      (0x01UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00100000 */\n#define ADC_SQR3_SQ5_1                      (0x02UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00200000 */\n#define ADC_SQR3_SQ5_2                      (0x04UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00400000 */\n#define ADC_SQR3_SQ5_3                      (0x08UL << ADC_SQR3_SQ5_Pos)        /*!< 0x00800000 */\n#define ADC_SQR3_SQ5_4                      (0x10UL << ADC_SQR3_SQ5_Pos)        /*!< 0x01000000 */\n\n#define ADC_SQR3_SQ6_Pos                    (25U)                              \n#define ADC_SQR3_SQ6_Msk                    (0x1FUL << ADC_SQR3_SQ6_Pos)        /*!< 0x3E000000 */\n#define ADC_SQR3_SQ6                        ADC_SQR3_SQ6_Msk                   /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR3_SQ6_0                      (0x01UL << ADC_SQR3_SQ6_Pos)        /*!< 0x02000000 */\n#define ADC_SQR3_SQ6_1                      (0x02UL << ADC_SQR3_SQ6_Pos)        /*!< 0x04000000 */\n#define ADC_SQR3_SQ6_2                      (0x04UL << ADC_SQR3_SQ6_Pos)        /*!< 0x08000000 */\n#define ADC_SQR3_SQ6_3                      (0x08UL << ADC_SQR3_SQ6_Pos)        /*!< 0x10000000 */\n#define ADC_SQR3_SQ6_4                      (0x10UL << ADC_SQR3_SQ6_Pos)        /*!< 0x20000000 */\n\n/*******************  Bit definition for ADC_JSQR register  *******************/\n#define ADC_JSQR_JSQ1_Pos                   (0U)                               \n#define ADC_JSQR_JSQ1_Msk                   (0x1FUL << ADC_JSQR_JSQ1_Pos)       /*!< 0x0000001F */\n#define ADC_JSQR_JSQ1                       ADC_JSQR_JSQ1_Msk                  /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0                     (0x01UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000001 */\n#define ADC_JSQR_JSQ1_1                     (0x02UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000002 */\n#define ADC_JSQR_JSQ1_2                     (0x04UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000004 */\n#define ADC_JSQR_JSQ1_3                     (0x08UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000008 */\n#define ADC_JSQR_JSQ1_4                     (0x10UL << ADC_JSQR_JSQ1_Pos)       /*!< 0x00000010 */\n\n#define ADC_JSQR_JSQ2_Pos                   (5U)                               \n#define ADC_JSQR_JSQ2_Msk                   (0x1FUL << ADC_JSQR_JSQ2_Pos)       /*!< 0x000003E0 */\n#define ADC_JSQR_JSQ2                       ADC_JSQR_JSQ2_Msk                  /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0                     (0x01UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000020 */\n#define ADC_JSQR_JSQ2_1                     (0x02UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000040 */\n#define ADC_JSQR_JSQ2_2                     (0x04UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000080 */\n#define ADC_JSQR_JSQ2_3                     (0x08UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000100 */\n#define ADC_JSQR_JSQ2_4                     (0x10UL << ADC_JSQR_JSQ2_Pos)       /*!< 0x00000200 */\n\n#define ADC_JSQR_JSQ3_Pos                   (10U)                              \n#define ADC_JSQR_JSQ3_Msk                   (0x1FUL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00007C00 */\n#define ADC_JSQR_JSQ3                       ADC_JSQR_JSQ3_Msk                  /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0                     (0x01UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000400 */\n#define ADC_JSQR_JSQ3_1                     (0x02UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00000800 */\n#define ADC_JSQR_JSQ3_2                     (0x04UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00001000 */\n#define ADC_JSQR_JSQ3_3                     (0x08UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00002000 */\n#define ADC_JSQR_JSQ3_4                     (0x10UL << ADC_JSQR_JSQ3_Pos)       /*!< 0x00004000 */\n\n#define ADC_JSQR_JSQ4_Pos                   (15U)                              \n#define ADC_JSQR_JSQ4_Msk                   (0x1FUL << ADC_JSQR_JSQ4_Pos)       /*!< 0x000F8000 */\n#define ADC_JSQR_JSQ4                       ADC_JSQR_JSQ4_Msk                  /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0                     (0x01UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00008000 */\n#define ADC_JSQR_JSQ4_1                     (0x02UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00010000 */\n#define ADC_JSQR_JSQ4_2                     (0x04UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00020000 */\n#define ADC_JSQR_JSQ4_3                     (0x08UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00040000 */\n#define ADC_JSQR_JSQ4_4                     (0x10UL << ADC_JSQR_JSQ4_Pos)       /*!< 0x00080000 */\n\n#define ADC_JSQR_JL_Pos                     (20U)                              \n#define ADC_JSQR_JL_Msk                     (0x3UL << ADC_JSQR_JL_Pos)          /*!< 0x00300000 */\n#define ADC_JSQR_JL                         ADC_JSQR_JL_Msk                    /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0                       (0x1UL << ADC_JSQR_JL_Pos)          /*!< 0x00100000 */\n#define ADC_JSQR_JL_1                       (0x2UL << ADC_JSQR_JL_Pos)          /*!< 0x00200000 */\n\n/*******************  Bit definition for ADC_JDR1 register  *******************/\n#define ADC_JDR1_JDATA_Pos                  (0U)                               \n#define ADC_JDR1_JDATA_Msk                  (0xFFFFUL << ADC_JDR1_JDATA_Pos)    /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA                      ADC_JDR1_JDATA_Msk                 /*!< ADC group injected sequencer rank 1 conversion data */\n\n/*******************  Bit definition for ADC_JDR2 register  *******************/\n#define ADC_JDR2_JDATA_Pos                  (0U)                               \n#define ADC_JDR2_JDATA_Msk                  (0xFFFFUL << ADC_JDR2_JDATA_Pos)    /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA                      ADC_JDR2_JDATA_Msk                 /*!< ADC group injected sequencer rank 2 conversion data */\n\n/*******************  Bit definition for ADC_JDR3 register  *******************/\n#define ADC_JDR3_JDATA_Pos                  (0U)                               \n#define ADC_JDR3_JDATA_Msk                  (0xFFFFUL << ADC_JDR3_JDATA_Pos)    /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA                      ADC_JDR3_JDATA_Msk                 /*!< ADC group injected sequencer rank 3 conversion data */\n\n/*******************  Bit definition for ADC_JDR4 register  *******************/\n#define ADC_JDR4_JDATA_Pos                  (0U)                               \n#define ADC_JDR4_JDATA_Msk                  (0xFFFFUL << ADC_JDR4_JDATA_Pos)    /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA                      ADC_JDR4_JDATA_Msk                 /*!< ADC group injected sequencer rank 4 conversion data */\n\n/********************  Bit definition for ADC_DR register  ********************/\n#define ADC_DR_DATA_Pos                     (0U)                               \n#define ADC_DR_DATA_Msk                     (0xFFFFUL << ADC_DR_DATA_Pos)       /*!< 0x0000FFFF */\n#define ADC_DR_DATA                         ADC_DR_DATA_Msk                    /*!< ADC group regular conversion data */\n#define ADC_DR_ADC2DATA_Pos                 (16U)                              \n#define ADC_DR_ADC2DATA_Msk                 (0xFFFFUL << ADC_DR_ADC2DATA_Pos)   /*!< 0xFFFF0000 */\n#define ADC_DR_ADC2DATA                     ADC_DR_ADC2DATA_Msk                /*!< ADC group regular conversion data for ADC slave, in multimode */\n\n\n/*****************************************************************************/\n/*                                                                           */\n/*                               Timers (TIM)                                */\n/*                                                                           */\n/*****************************************************************************/\n/*******************  Bit definition for TIM_CR1 register  *******************/\n#define TIM_CR1_CEN_Pos                     (0U)                               \n#define TIM_CR1_CEN_Msk                     (0x1UL << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */\n#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */\n#define TIM_CR1_UDIS_Pos                    (1U)                               \n#define TIM_CR1_UDIS_Msk                    (0x1UL << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */\n#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */\n#define TIM_CR1_URS_Pos                     (2U)                               \n#define TIM_CR1_URS_Msk                     (0x1UL << TIM_CR1_URS_Pos)          /*!< 0x00000004 */\n#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */\n#define TIM_CR1_OPM_Pos                     (3U)                               \n#define TIM_CR1_OPM_Msk                     (0x1UL << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */\n#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */\n#define TIM_CR1_DIR_Pos                     (4U)                               \n#define TIM_CR1_DIR_Msk                     (0x1UL << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */\n#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */\n\n#define TIM_CR1_CMS_Pos                     (5U)                               \n#define TIM_CR1_CMS_Msk                     (0x3UL << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */\n#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */\n#define TIM_CR1_CMS_0                       (0x1UL << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */\n#define TIM_CR1_CMS_1                       (0x2UL << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */\n\n#define TIM_CR1_ARPE_Pos                    (7U)                               \n#define TIM_CR1_ARPE_Msk                    (0x1UL << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */\n#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */\n\n#define TIM_CR1_CKD_Pos                     (8U)                               \n#define TIM_CR1_CKD_Msk                     (0x3UL << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */\n#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */\n#define TIM_CR1_CKD_0                       (0x1UL << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */\n#define TIM_CR1_CKD_1                       (0x2UL << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */\n\n/*******************  Bit definition for TIM_CR2 register  *******************/\n#define TIM_CR2_CCPC_Pos                    (0U)                               \n#define TIM_CR2_CCPC_Msk                    (0x1UL << TIM_CR2_CCPC_Pos)         /*!< 0x00000001 */\n#define TIM_CR2_CCPC                        TIM_CR2_CCPC_Msk                   /*!<Capture/Compare Preloaded Control */\n#define TIM_CR2_CCUS_Pos                    (2U)                               \n#define TIM_CR2_CCUS_Msk                    (0x1UL << TIM_CR2_CCUS_Pos)         /*!< 0x00000004 */\n#define TIM_CR2_CCUS                        TIM_CR2_CCUS_Msk                   /*!<Capture/Compare Control Update Selection */\n#define TIM_CR2_CCDS_Pos                    (3U)                               \n#define TIM_CR2_CCDS_Msk                    (0x1UL << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */\n#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */\n\n#define TIM_CR2_MMS_Pos                     (4U)                               \n#define TIM_CR2_MMS_Msk                     (0x7UL << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */\n#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */\n#define TIM_CR2_MMS_0                       (0x1UL << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */\n#define TIM_CR2_MMS_1                       (0x2UL << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */\n#define TIM_CR2_MMS_2                       (0x4UL << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */\n\n#define TIM_CR2_TI1S_Pos                    (7U)                               \n#define TIM_CR2_TI1S_Msk                    (0x1UL << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */\n#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */\n#define TIM_CR2_OIS1_Pos                    (8U)                               \n#define TIM_CR2_OIS1_Msk                    (0x1UL << TIM_CR2_OIS1_Pos)         /*!< 0x00000100 */\n#define TIM_CR2_OIS1                        TIM_CR2_OIS1_Msk                   /*!<Output Idle state 1 (OC1 output) */\n#define TIM_CR2_OIS1N_Pos                   (9U)                               \n#define TIM_CR2_OIS1N_Msk                   (0x1UL << TIM_CR2_OIS1N_Pos)        /*!< 0x00000200 */\n#define TIM_CR2_OIS1N                       TIM_CR2_OIS1N_Msk                  /*!<Output Idle state 1 (OC1N output) */\n#define TIM_CR2_OIS2_Pos                    (10U)                              \n#define TIM_CR2_OIS2_Msk                    (0x1UL << TIM_CR2_OIS2_Pos)         /*!< 0x00000400 */\n#define TIM_CR2_OIS2                        TIM_CR2_OIS2_Msk                   /*!<Output Idle state 2 (OC2 output) */\n#define TIM_CR2_OIS2N_Pos                   (11U)                              \n#define TIM_CR2_OIS2N_Msk                   (0x1UL << TIM_CR2_OIS2N_Pos)        /*!< 0x00000800 */\n#define TIM_CR2_OIS2N                       TIM_CR2_OIS2N_Msk                  /*!<Output Idle state 2 (OC2N output) */\n#define TIM_CR2_OIS3_Pos                    (12U)                              \n#define TIM_CR2_OIS3_Msk                    (0x1UL << TIM_CR2_OIS3_Pos)         /*!< 0x00001000 */\n#define TIM_CR2_OIS3                        TIM_CR2_OIS3_Msk                   /*!<Output Idle state 3 (OC3 output) */\n#define TIM_CR2_OIS3N_Pos                   (13U)                              \n#define TIM_CR2_OIS3N_Msk                   (0x1UL << TIM_CR2_OIS3N_Pos)        /*!< 0x00002000 */\n#define TIM_CR2_OIS3N                       TIM_CR2_OIS3N_Msk                  /*!<Output Idle state 3 (OC3N output) */\n#define TIM_CR2_OIS4_Pos                    (14U)                              \n#define TIM_CR2_OIS4_Msk                    (0x1UL << TIM_CR2_OIS4_Pos)         /*!< 0x00004000 */\n#define TIM_CR2_OIS4                        TIM_CR2_OIS4_Msk                   /*!<Output Idle state 4 (OC4 output) */\n\n/*******************  Bit definition for TIM_SMCR register  ******************/\n#define TIM_SMCR_SMS_Pos                    (0U)                               \n#define TIM_SMCR_SMS_Msk                    (0x7UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */\n#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */\n#define TIM_SMCR_SMS_0                      (0x1UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */\n#define TIM_SMCR_SMS_1                      (0x2UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */\n#define TIM_SMCR_SMS_2                      (0x4UL << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */\n\n#define TIM_SMCR_TS_Pos                     (4U)                               \n#define TIM_SMCR_TS_Msk                     (0x7UL << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */\n#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */\n#define TIM_SMCR_TS_0                       (0x1UL << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */\n#define TIM_SMCR_TS_1                       (0x2UL << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */\n#define TIM_SMCR_TS_2                       (0x4UL << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */\n\n#define TIM_SMCR_MSM_Pos                    (7U)                               \n#define TIM_SMCR_MSM_Msk                    (0x1UL << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */\n#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */\n\n#define TIM_SMCR_ETF_Pos                    (8U)                               \n#define TIM_SMCR_ETF_Msk                    (0xFUL << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */\n#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */\n#define TIM_SMCR_ETF_0                      (0x1UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */\n#define TIM_SMCR_ETF_1                      (0x2UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */\n#define TIM_SMCR_ETF_2                      (0x4UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */\n#define TIM_SMCR_ETF_3                      (0x8UL << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */\n\n#define TIM_SMCR_ETPS_Pos                   (12U)                              \n#define TIM_SMCR_ETPS_Msk                   (0x3UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */\n#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */\n#define TIM_SMCR_ETPS_0                     (0x1UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */\n#define TIM_SMCR_ETPS_1                     (0x2UL << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */\n\n#define TIM_SMCR_ECE_Pos                    (14U)                              \n#define TIM_SMCR_ECE_Msk                    (0x1UL << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */\n#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */\n#define TIM_SMCR_ETP_Pos                    (15U)                              \n#define TIM_SMCR_ETP_Msk                    (0x1UL << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */\n#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */\n\n/*******************  Bit definition for TIM_DIER register  ******************/\n#define TIM_DIER_UIE_Pos                    (0U)                               \n#define TIM_DIER_UIE_Msk                    (0x1UL << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */\n#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */\n#define TIM_DIER_CC1IE_Pos                  (1U)                               \n#define TIM_DIER_CC1IE_Msk                  (0x1UL << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */\n#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */\n#define TIM_DIER_CC2IE_Pos                  (2U)                               \n#define TIM_DIER_CC2IE_Msk                  (0x1UL << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */\n#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */\n#define TIM_DIER_CC3IE_Pos                  (3U)                               \n#define TIM_DIER_CC3IE_Msk                  (0x1UL << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */\n#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */\n#define TIM_DIER_CC4IE_Pos                  (4U)                               \n#define TIM_DIER_CC4IE_Msk                  (0x1UL << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */\n#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */\n#define TIM_DIER_COMIE_Pos                  (5U)                               \n#define TIM_DIER_COMIE_Msk                  (0x1UL << TIM_DIER_COMIE_Pos)       /*!< 0x00000020 */\n#define TIM_DIER_COMIE                      TIM_DIER_COMIE_Msk                 /*!<COM interrupt enable */\n#define TIM_DIER_TIE_Pos                    (6U)                               \n#define TIM_DIER_TIE_Msk                    (0x1UL << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */\n#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */\n#define TIM_DIER_BIE_Pos                    (7U)                               \n#define TIM_DIER_BIE_Msk                    (0x1UL << TIM_DIER_BIE_Pos)         /*!< 0x00000080 */\n#define TIM_DIER_BIE                        TIM_DIER_BIE_Msk                   /*!<Break interrupt enable */\n#define TIM_DIER_UDE_Pos                    (8U)                               \n#define TIM_DIER_UDE_Msk                    (0x1UL << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */\n#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */\n#define TIM_DIER_CC1DE_Pos                  (9U)                               \n#define TIM_DIER_CC1DE_Msk                  (0x1UL << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */\n#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */\n#define TIM_DIER_CC2DE_Pos                  (10U)                              \n#define TIM_DIER_CC2DE_Msk                  (0x1UL << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */\n#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */\n#define TIM_DIER_CC3DE_Pos                  (11U)                              \n#define TIM_DIER_CC3DE_Msk                  (0x1UL << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */\n#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */\n#define TIM_DIER_CC4DE_Pos                  (12U)                              \n#define TIM_DIER_CC4DE_Msk                  (0x1UL << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */\n#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */\n#define TIM_DIER_COMDE_Pos                  (13U)                              \n#define TIM_DIER_COMDE_Msk                  (0x1UL << TIM_DIER_COMDE_Pos)       /*!< 0x00002000 */\n#define TIM_DIER_COMDE                      TIM_DIER_COMDE_Msk                 /*!<COM DMA request enable */\n#define TIM_DIER_TDE_Pos                    (14U)                              \n#define TIM_DIER_TDE_Msk                    (0x1UL << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */\n#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */\n\n/********************  Bit definition for TIM_SR register  *******************/\n#define TIM_SR_UIF_Pos                      (0U)                               \n#define TIM_SR_UIF_Msk                      (0x1UL << TIM_SR_UIF_Pos)           /*!< 0x00000001 */\n#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */\n#define TIM_SR_CC1IF_Pos                    (1U)                               \n#define TIM_SR_CC1IF_Msk                    (0x1UL << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */\n#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */\n#define TIM_SR_CC2IF_Pos                    (2U)                               \n#define TIM_SR_CC2IF_Msk                    (0x1UL << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */\n#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */\n#define TIM_SR_CC3IF_Pos                    (3U)                               \n#define TIM_SR_CC3IF_Msk                    (0x1UL << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */\n#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */\n#define TIM_SR_CC4IF_Pos                    (4U)                               \n#define TIM_SR_CC4IF_Msk                    (0x1UL << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */\n#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */\n#define TIM_SR_COMIF_Pos                    (5U)                               \n#define TIM_SR_COMIF_Msk                    (0x1UL << TIM_SR_COMIF_Pos)         /*!< 0x00000020 */\n#define TIM_SR_COMIF                        TIM_SR_COMIF_Msk                   /*!<COM interrupt Flag */\n#define TIM_SR_TIF_Pos                      (6U)                               \n#define TIM_SR_TIF_Msk                      (0x1UL << TIM_SR_TIF_Pos)           /*!< 0x00000040 */\n#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */\n#define TIM_SR_BIF_Pos                      (7U)                               \n#define TIM_SR_BIF_Msk                      (0x1UL << TIM_SR_BIF_Pos)           /*!< 0x00000080 */\n#define TIM_SR_BIF                          TIM_SR_BIF_Msk                     /*!<Break interrupt Flag */\n#define TIM_SR_CC1OF_Pos                    (9U)                               \n#define TIM_SR_CC1OF_Msk                    (0x1UL << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */\n#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */\n#define TIM_SR_CC2OF_Pos                    (10U)                              \n#define TIM_SR_CC2OF_Msk                    (0x1UL << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */\n#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */\n#define TIM_SR_CC3OF_Pos                    (11U)                              \n#define TIM_SR_CC3OF_Msk                    (0x1UL << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */\n#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */\n#define TIM_SR_CC4OF_Pos                    (12U)                              \n#define TIM_SR_CC4OF_Msk                    (0x1UL << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */\n#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */\n\n/*******************  Bit definition for TIM_EGR register  *******************/\n#define TIM_EGR_UG_Pos                      (0U)                               \n#define TIM_EGR_UG_Msk                      (0x1UL << TIM_EGR_UG_Pos)           /*!< 0x00000001 */\n#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */\n#define TIM_EGR_CC1G_Pos                    (1U)                               \n#define TIM_EGR_CC1G_Msk                    (0x1UL << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */\n#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */\n#define TIM_EGR_CC2G_Pos                    (2U)                               \n#define TIM_EGR_CC2G_Msk                    (0x1UL << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */\n#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */\n#define TIM_EGR_CC3G_Pos                    (3U)                               \n#define TIM_EGR_CC3G_Msk                    (0x1UL << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */\n#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */\n#define TIM_EGR_CC4G_Pos                    (4U)                               \n#define TIM_EGR_CC4G_Msk                    (0x1UL << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */\n#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */\n#define TIM_EGR_COMG_Pos                    (5U)                               \n#define TIM_EGR_COMG_Msk                    (0x1UL << TIM_EGR_COMG_Pos)         /*!< 0x00000020 */\n#define TIM_EGR_COMG                        TIM_EGR_COMG_Msk                   /*!<Capture/Compare Control Update Generation */\n#define TIM_EGR_TG_Pos                      (6U)                               \n#define TIM_EGR_TG_Msk                      (0x1UL << TIM_EGR_TG_Pos)           /*!< 0x00000040 */\n#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */\n#define TIM_EGR_BG_Pos                      (7U)                               \n#define TIM_EGR_BG_Msk                      (0x1UL << TIM_EGR_BG_Pos)           /*!< 0x00000080 */\n#define TIM_EGR_BG                          TIM_EGR_BG_Msk                     /*!<Break Generation */\n\n/******************  Bit definition for TIM_CCMR1 register  ******************/\n#define TIM_CCMR1_CC1S_Pos                  (0U)                               \n#define TIM_CCMR1_CC1S_Msk                  (0x3UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */\n#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\n#define TIM_CCMR1_CC1S_0                    (0x1UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */\n#define TIM_CCMR1_CC1S_1                    (0x2UL << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */\n\n#define TIM_CCMR1_OC1FE_Pos                 (2U)                               \n#define TIM_CCMR1_OC1FE_Msk                 (0x1UL << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */\n#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */\n#define TIM_CCMR1_OC1PE_Pos                 (3U)                               \n#define TIM_CCMR1_OC1PE_Msk                 (0x1UL << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */\n#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */\n\n#define TIM_CCMR1_OC1M_Pos                  (4U)                               \n#define TIM_CCMR1_OC1M_Msk                  (0x7UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */\n#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\n#define TIM_CCMR1_OC1M_0                    (0x1UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */\n#define TIM_CCMR1_OC1M_1                    (0x2UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */\n#define TIM_CCMR1_OC1M_2                    (0x4UL << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */\n\n#define TIM_CCMR1_OC1CE_Pos                 (7U)                               \n#define TIM_CCMR1_OC1CE_Msk                 (0x1UL << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */\n#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */\n\n#define TIM_CCMR1_CC2S_Pos                  (8U)                               \n#define TIM_CCMR1_CC2S_Msk                  (0x3UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */\n#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\n#define TIM_CCMR1_CC2S_0                    (0x1UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */\n#define TIM_CCMR1_CC2S_1                    (0x2UL << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */\n\n#define TIM_CCMR1_OC2FE_Pos                 (10U)                              \n#define TIM_CCMR1_OC2FE_Msk                 (0x1UL << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */\n#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */\n#define TIM_CCMR1_OC2PE_Pos                 (11U)                              \n#define TIM_CCMR1_OC2PE_Msk                 (0x1UL << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */\n#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */\n\n#define TIM_CCMR1_OC2M_Pos                  (12U)                              \n#define TIM_CCMR1_OC2M_Msk                  (0x7UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */\n#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\n#define TIM_CCMR1_OC2M_0                    (0x1UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */\n#define TIM_CCMR1_OC2M_1                    (0x2UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */\n#define TIM_CCMR1_OC2M_2                    (0x4UL << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */\n\n#define TIM_CCMR1_OC2CE_Pos                 (15U)                              \n#define TIM_CCMR1_OC2CE_Msk                 (0x1UL << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */\n#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */\n\n/*---------------------------------------------------------------------------*/\n\n#define TIM_CCMR1_IC1PSC_Pos                (2U)                               \n#define TIM_CCMR1_IC1PSC_Msk                (0x3UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */\n#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\n#define TIM_CCMR1_IC1PSC_0                  (0x1UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */\n#define TIM_CCMR1_IC1PSC_1                  (0x2UL << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */\n\n#define TIM_CCMR1_IC1F_Pos                  (4U)                               \n#define TIM_CCMR1_IC1F_Msk                  (0xFUL << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */\n#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\n#define TIM_CCMR1_IC1F_0                    (0x1UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */\n#define TIM_CCMR1_IC1F_1                    (0x2UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */\n#define TIM_CCMR1_IC1F_2                    (0x4UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */\n#define TIM_CCMR1_IC1F_3                    (0x8UL << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */\n\n#define TIM_CCMR1_IC2PSC_Pos                (10U)                              \n#define TIM_CCMR1_IC2PSC_Msk                (0x3UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */\n#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\n#define TIM_CCMR1_IC2PSC_0                  (0x1UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */\n#define TIM_CCMR1_IC2PSC_1                  (0x2UL << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */\n\n#define TIM_CCMR1_IC2F_Pos                  (12U)                              \n#define TIM_CCMR1_IC2F_Msk                  (0xFUL << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */\n#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\n#define TIM_CCMR1_IC2F_0                    (0x1UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */\n#define TIM_CCMR1_IC2F_1                    (0x2UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */\n#define TIM_CCMR1_IC2F_2                    (0x4UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */\n#define TIM_CCMR1_IC2F_3                    (0x8UL << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */\n\n/******************  Bit definition for TIM_CCMR2 register  ******************/\n#define TIM_CCMR2_CC3S_Pos                  (0U)                               \n#define TIM_CCMR2_CC3S_Msk                  (0x3UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */\n#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\n#define TIM_CCMR2_CC3S_0                    (0x1UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */\n#define TIM_CCMR2_CC3S_1                    (0x2UL << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */\n\n#define TIM_CCMR2_OC3FE_Pos                 (2U)                               \n#define TIM_CCMR2_OC3FE_Msk                 (0x1UL << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */\n#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */\n#define TIM_CCMR2_OC3PE_Pos                 (3U)                               \n#define TIM_CCMR2_OC3PE_Msk                 (0x1UL << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */\n#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */\n\n#define TIM_CCMR2_OC3M_Pos                  (4U)                               \n#define TIM_CCMR2_OC3M_Msk                  (0x7UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */\n#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\n#define TIM_CCMR2_OC3M_0                    (0x1UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */\n#define TIM_CCMR2_OC3M_1                    (0x2UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */\n#define TIM_CCMR2_OC3M_2                    (0x4UL << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */\n\n#define TIM_CCMR2_OC3CE_Pos                 (7U)                               \n#define TIM_CCMR2_OC3CE_Msk                 (0x1UL << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */\n#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */\n\n#define TIM_CCMR2_CC4S_Pos                  (8U)                               \n#define TIM_CCMR2_CC4S_Msk                  (0x3UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */\n#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\n#define TIM_CCMR2_CC4S_0                    (0x1UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */\n#define TIM_CCMR2_CC4S_1                    (0x2UL << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */\n\n#define TIM_CCMR2_OC4FE_Pos                 (10U)                              \n#define TIM_CCMR2_OC4FE_Msk                 (0x1UL << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */\n#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */\n#define TIM_CCMR2_OC4PE_Pos                 (11U)                              \n#define TIM_CCMR2_OC4PE_Msk                 (0x1UL << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */\n#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */\n\n#define TIM_CCMR2_OC4M_Pos                  (12U)                              \n#define TIM_CCMR2_OC4M_Msk                  (0x7UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */\n#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\n#define TIM_CCMR2_OC4M_0                    (0x1UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */\n#define TIM_CCMR2_OC4M_1                    (0x2UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */\n#define TIM_CCMR2_OC4M_2                    (0x4UL << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */\n\n#define TIM_CCMR2_OC4CE_Pos                 (15U)                              \n#define TIM_CCMR2_OC4CE_Msk                 (0x1UL << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */\n#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */\n\n/*---------------------------------------------------------------------------*/\n\n#define TIM_CCMR2_IC3PSC_Pos                (2U)                               \n#define TIM_CCMR2_IC3PSC_Msk                (0x3UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */\n#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\n#define TIM_CCMR2_IC3PSC_0                  (0x1UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */\n#define TIM_CCMR2_IC3PSC_1                  (0x2UL << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */\n\n#define TIM_CCMR2_IC3F_Pos                  (4U)                               \n#define TIM_CCMR2_IC3F_Msk                  (0xFUL << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */\n#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\n#define TIM_CCMR2_IC3F_0                    (0x1UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */\n#define TIM_CCMR2_IC3F_1                    (0x2UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */\n#define TIM_CCMR2_IC3F_2                    (0x4UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */\n#define TIM_CCMR2_IC3F_3                    (0x8UL << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */\n\n#define TIM_CCMR2_IC4PSC_Pos                (10U)                              \n#define TIM_CCMR2_IC4PSC_Msk                (0x3UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */\n#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\n#define TIM_CCMR2_IC4PSC_0                  (0x1UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */\n#define TIM_CCMR2_IC4PSC_1                  (0x2UL << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */\n\n#define TIM_CCMR2_IC4F_Pos                  (12U)                              \n#define TIM_CCMR2_IC4F_Msk                  (0xFUL << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */\n#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\n#define TIM_CCMR2_IC4F_0                    (0x1UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */\n#define TIM_CCMR2_IC4F_1                    (0x2UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */\n#define TIM_CCMR2_IC4F_2                    (0x4UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */\n#define TIM_CCMR2_IC4F_3                    (0x8UL << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */\n\n/*******************  Bit definition for TIM_CCER register  ******************/\n#define TIM_CCER_CC1E_Pos                   (0U)                               \n#define TIM_CCER_CC1E_Msk                   (0x1UL << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */\n#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */\n#define TIM_CCER_CC1P_Pos                   (1U)                               \n#define TIM_CCER_CC1P_Msk                   (0x1UL << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */\n#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */\n#define TIM_CCER_CC1NE_Pos                  (2U)                               \n#define TIM_CCER_CC1NE_Msk                  (0x1UL << TIM_CCER_CC1NE_Pos)       /*!< 0x00000004 */\n#define TIM_CCER_CC1NE                      TIM_CCER_CC1NE_Msk                 /*!<Capture/Compare 1 Complementary output enable */\n#define TIM_CCER_CC1NP_Pos                  (3U)                               \n#define TIM_CCER_CC1NP_Msk                  (0x1UL << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */\n#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */\n#define TIM_CCER_CC2E_Pos                   (4U)                               \n#define TIM_CCER_CC2E_Msk                   (0x1UL << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */\n#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */\n#define TIM_CCER_CC2P_Pos                   (5U)                               \n#define TIM_CCER_CC2P_Msk                   (0x1UL << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */\n#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */\n#define TIM_CCER_CC2NE_Pos                  (6U)                               \n#define TIM_CCER_CC2NE_Msk                  (0x1UL << TIM_CCER_CC2NE_Pos)       /*!< 0x00000040 */\n#define TIM_CCER_CC2NE                      TIM_CCER_CC2NE_Msk                 /*!<Capture/Compare 2 Complementary output enable */\n#define TIM_CCER_CC2NP_Pos                  (7U)                               \n#define TIM_CCER_CC2NP_Msk                  (0x1UL << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */\n#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */\n#define TIM_CCER_CC3E_Pos                   (8U)                               \n#define TIM_CCER_CC3E_Msk                   (0x1UL << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */\n#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */\n#define TIM_CCER_CC3P_Pos                   (9U)                               \n#define TIM_CCER_CC3P_Msk                   (0x1UL << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */\n#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */\n#define TIM_CCER_CC3NE_Pos                  (10U)                              \n#define TIM_CCER_CC3NE_Msk                  (0x1UL << TIM_CCER_CC3NE_Pos)       /*!< 0x00000400 */\n#define TIM_CCER_CC3NE                      TIM_CCER_CC3NE_Msk                 /*!<Capture/Compare 3 Complementary output enable */\n#define TIM_CCER_CC3NP_Pos                  (11U)                              \n#define TIM_CCER_CC3NP_Msk                  (0x1UL << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */\n#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */\n#define TIM_CCER_CC4E_Pos                   (12U)                              \n#define TIM_CCER_CC4E_Msk                   (0x1UL << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */\n#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */\n#define TIM_CCER_CC4P_Pos                   (13U)                              \n#define TIM_CCER_CC4P_Msk                   (0x1UL << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */\n#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */\n\n/*******************  Bit definition for TIM_CNT register  *******************/\n#define TIM_CNT_CNT_Pos                     (0U)                               \n#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */\n#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */\n\n/*******************  Bit definition for TIM_PSC register  *******************/\n#define TIM_PSC_PSC_Pos                     (0U)                               \n#define TIM_PSC_PSC_Msk                     (0xFFFFUL << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */\n#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */\n\n/*******************  Bit definition for TIM_ARR register  *******************/\n#define TIM_ARR_ARR_Pos                     (0U)                               \n#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */\n#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */\n\n/*******************  Bit definition for TIM_RCR register  *******************/\n#define TIM_RCR_REP_Pos                     (0U)                               \n#define TIM_RCR_REP_Msk                     (0xFFUL << TIM_RCR_REP_Pos)         /*!< 0x000000FF */\n#define TIM_RCR_REP                         TIM_RCR_REP_Msk                    /*!<Repetition Counter Value */\n\n/*******************  Bit definition for TIM_CCR1 register  ******************/\n#define TIM_CCR1_CCR1_Pos                   (0U)                               \n#define TIM_CCR1_CCR1_Msk                   (0xFFFFUL << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */\n#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */\n\n/*******************  Bit definition for TIM_CCR2 register  ******************/\n#define TIM_CCR2_CCR2_Pos                   (0U)                               \n#define TIM_CCR2_CCR2_Msk                   (0xFFFFUL << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */\n#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */\n\n/*******************  Bit definition for TIM_CCR3 register  ******************/\n#define TIM_CCR3_CCR3_Pos                   (0U)                               \n#define TIM_CCR3_CCR3_Msk                   (0xFFFFUL << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */\n#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */\n\n/*******************  Bit definition for TIM_CCR4 register  ******************/\n#define TIM_CCR4_CCR4_Pos                   (0U)                               \n#define TIM_CCR4_CCR4_Msk                   (0xFFFFUL << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */\n#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */\n\n/*******************  Bit definition for TIM_BDTR register  ******************/\n#define TIM_BDTR_DTG_Pos                    (0U)                               \n#define TIM_BDTR_DTG_Msk                    (0xFFUL << TIM_BDTR_DTG_Pos)        /*!< 0x000000FF */\n#define TIM_BDTR_DTG                        TIM_BDTR_DTG_Msk                   /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\n#define TIM_BDTR_DTG_0                      (0x01UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000001 */\n#define TIM_BDTR_DTG_1                      (0x02UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000002 */\n#define TIM_BDTR_DTG_2                      (0x04UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000004 */\n#define TIM_BDTR_DTG_3                      (0x08UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000008 */\n#define TIM_BDTR_DTG_4                      (0x10UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000010 */\n#define TIM_BDTR_DTG_5                      (0x20UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000020 */\n#define TIM_BDTR_DTG_6                      (0x40UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000040 */\n#define TIM_BDTR_DTG_7                      (0x80UL << TIM_BDTR_DTG_Pos)        /*!< 0x00000080 */\n\n#define TIM_BDTR_LOCK_Pos                   (8U)                               \n#define TIM_BDTR_LOCK_Msk                   (0x3UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000300 */\n#define TIM_BDTR_LOCK                       TIM_BDTR_LOCK_Msk                  /*!<LOCK[1:0] bits (Lock Configuration) */\n#define TIM_BDTR_LOCK_0                     (0x1UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000100 */\n#define TIM_BDTR_LOCK_1                     (0x2UL << TIM_BDTR_LOCK_Pos)        /*!< 0x00000200 */\n\n#define TIM_BDTR_OSSI_Pos                   (10U)                              \n#define TIM_BDTR_OSSI_Msk                   (0x1UL << TIM_BDTR_OSSI_Pos)        /*!< 0x00000400 */\n#define TIM_BDTR_OSSI                       TIM_BDTR_OSSI_Msk                  /*!<Off-State Selection for Idle mode */\n#define TIM_BDTR_OSSR_Pos                   (11U)                              \n#define TIM_BDTR_OSSR_Msk                   (0x1UL << TIM_BDTR_OSSR_Pos)        /*!< 0x00000800 */\n#define TIM_BDTR_OSSR                       TIM_BDTR_OSSR_Msk                  /*!<Off-State Selection for Run mode */\n#define TIM_BDTR_BKE_Pos                    (12U)                              \n#define TIM_BDTR_BKE_Msk                    (0x1UL << TIM_BDTR_BKE_Pos)         /*!< 0x00001000 */\n#define TIM_BDTR_BKE                        TIM_BDTR_BKE_Msk                   /*!<Break enable */\n#define TIM_BDTR_BKP_Pos                    (13U)                              \n#define TIM_BDTR_BKP_Msk                    (0x1UL << TIM_BDTR_BKP_Pos)         /*!< 0x00002000 */\n#define TIM_BDTR_BKP                        TIM_BDTR_BKP_Msk                   /*!<Break Polarity */\n#define TIM_BDTR_AOE_Pos                    (14U)                              \n#define TIM_BDTR_AOE_Msk                    (0x1UL << TIM_BDTR_AOE_Pos)         /*!< 0x00004000 */\n#define TIM_BDTR_AOE                        TIM_BDTR_AOE_Msk                   /*!<Automatic Output enable */\n#define TIM_BDTR_MOE_Pos                    (15U)                              \n#define TIM_BDTR_MOE_Msk                    (0x1UL << TIM_BDTR_MOE_Pos)         /*!< 0x00008000 */\n#define TIM_BDTR_MOE                        TIM_BDTR_MOE_Msk                   /*!<Main Output enable */\n\n/*******************  Bit definition for TIM_DCR register  *******************/\n#define TIM_DCR_DBA_Pos                     (0U)                               \n#define TIM_DCR_DBA_Msk                     (0x1FUL << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */\n#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */\n#define TIM_DCR_DBA_0                       (0x01UL << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */\n#define TIM_DCR_DBA_1                       (0x02UL << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */\n#define TIM_DCR_DBA_2                       (0x04UL << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */\n#define TIM_DCR_DBA_3                       (0x08UL << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */\n#define TIM_DCR_DBA_4                       (0x10UL << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */\n\n#define TIM_DCR_DBL_Pos                     (8U)                               \n#define TIM_DCR_DBL_Msk                     (0x1FUL << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */\n#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */\n#define TIM_DCR_DBL_0                       (0x01UL << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */\n#define TIM_DCR_DBL_1                       (0x02UL << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */\n#define TIM_DCR_DBL_2                       (0x04UL << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */\n#define TIM_DCR_DBL_3                       (0x08UL << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */\n#define TIM_DCR_DBL_4                       (0x10UL << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */\n\n/*******************  Bit definition for TIM_DMAR register  ******************/\n#define TIM_DMAR_DMAB_Pos                   (0U)                               \n#define TIM_DMAR_DMAB_Msk                   (0xFFFFUL << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */\n#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */\n\n/******************************************************************************/\n/*                                                                            */\n/*                             Real-Time Clock                                */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for RTC_CRH register  ********************/\n#define RTC_CRH_SECIE_Pos                   (0U)                               \n#define RTC_CRH_SECIE_Msk                   (0x1UL << RTC_CRH_SECIE_Pos)        /*!< 0x00000001 */\n#define RTC_CRH_SECIE                       RTC_CRH_SECIE_Msk                  /*!< Second Interrupt Enable */\n#define RTC_CRH_ALRIE_Pos                   (1U)                               \n#define RTC_CRH_ALRIE_Msk                   (0x1UL << RTC_CRH_ALRIE_Pos)        /*!< 0x00000002 */\n#define RTC_CRH_ALRIE                       RTC_CRH_ALRIE_Msk                  /*!< Alarm Interrupt Enable */\n#define RTC_CRH_OWIE_Pos                    (2U)                               \n#define RTC_CRH_OWIE_Msk                    (0x1UL << RTC_CRH_OWIE_Pos)         /*!< 0x00000004 */\n#define RTC_CRH_OWIE                        RTC_CRH_OWIE_Msk                   /*!< OverfloW Interrupt Enable */\n\n/*******************  Bit definition for RTC_CRL register  ********************/\n#define RTC_CRL_SECF_Pos                    (0U)                               \n#define RTC_CRL_SECF_Msk                    (0x1UL << RTC_CRL_SECF_Pos)         /*!< 0x00000001 */\n#define RTC_CRL_SECF                        RTC_CRL_SECF_Msk                   /*!< Second Flag */\n#define RTC_CRL_ALRF_Pos                    (1U)                               \n#define RTC_CRL_ALRF_Msk                    (0x1UL << RTC_CRL_ALRF_Pos)         /*!< 0x00000002 */\n#define RTC_CRL_ALRF                        RTC_CRL_ALRF_Msk                   /*!< Alarm Flag */\n#define RTC_CRL_OWF_Pos                     (2U)                               \n#define RTC_CRL_OWF_Msk                     (0x1UL << RTC_CRL_OWF_Pos)          /*!< 0x00000004 */\n#define RTC_CRL_OWF                         RTC_CRL_OWF_Msk                    /*!< OverfloW Flag */\n#define RTC_CRL_RSF_Pos                     (3U)                               \n#define RTC_CRL_RSF_Msk                     (0x1UL << RTC_CRL_RSF_Pos)          /*!< 0x00000008 */\n#define RTC_CRL_RSF                         RTC_CRL_RSF_Msk                    /*!< Registers Synchronized Flag */\n#define RTC_CRL_CNF_Pos                     (4U)                               \n#define RTC_CRL_CNF_Msk                     (0x1UL << RTC_CRL_CNF_Pos)          /*!< 0x00000010 */\n#define RTC_CRL_CNF                         RTC_CRL_CNF_Msk                    /*!< Configuration Flag */\n#define RTC_CRL_RTOFF_Pos                   (5U)                               \n#define RTC_CRL_RTOFF_Msk                   (0x1UL << RTC_CRL_RTOFF_Pos)        /*!< 0x00000020 */\n#define RTC_CRL_RTOFF                       RTC_CRL_RTOFF_Msk                  /*!< RTC operation OFF */\n\n/*******************  Bit definition for RTC_PRLH register  *******************/\n#define RTC_PRLH_PRL_Pos                    (0U)                               \n#define RTC_PRLH_PRL_Msk                    (0xFUL << RTC_PRLH_PRL_Pos)         /*!< 0x0000000F */\n#define RTC_PRLH_PRL                        RTC_PRLH_PRL_Msk                   /*!< RTC Prescaler Reload Value High */\n\n/*******************  Bit definition for RTC_PRLL register  *******************/\n#define RTC_PRLL_PRL_Pos                    (0U)                               \n#define RTC_PRLL_PRL_Msk                    (0xFFFFUL << RTC_PRLL_PRL_Pos)      /*!< 0x0000FFFF */\n#define RTC_PRLL_PRL                        RTC_PRLL_PRL_Msk                   /*!< RTC Prescaler Reload Value Low */\n\n/*******************  Bit definition for RTC_DIVH register  *******************/\n#define RTC_DIVH_RTC_DIV_Pos                (0U)                               \n#define RTC_DIVH_RTC_DIV_Msk                (0xFUL << RTC_DIVH_RTC_DIV_Pos)     /*!< 0x0000000F */\n#define RTC_DIVH_RTC_DIV                    RTC_DIVH_RTC_DIV_Msk               /*!< RTC Clock Divider High */\n\n/*******************  Bit definition for RTC_DIVL register  *******************/\n#define RTC_DIVL_RTC_DIV_Pos                (0U)                               \n#define RTC_DIVL_RTC_DIV_Msk                (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)  /*!< 0x0000FFFF */\n#define RTC_DIVL_RTC_DIV                    RTC_DIVL_RTC_DIV_Msk               /*!< RTC Clock Divider Low */\n\n/*******************  Bit definition for RTC_CNTH register  *******************/\n#define RTC_CNTH_RTC_CNT_Pos                (0U)                               \n#define RTC_CNTH_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)  /*!< 0x0000FFFF */\n#define RTC_CNTH_RTC_CNT                    RTC_CNTH_RTC_CNT_Msk               /*!< RTC Counter High */\n\n/*******************  Bit definition for RTC_CNTL register  *******************/\n#define RTC_CNTL_RTC_CNT_Pos                (0U)                               \n#define RTC_CNTL_RTC_CNT_Msk                (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)  /*!< 0x0000FFFF */\n#define RTC_CNTL_RTC_CNT                    RTC_CNTL_RTC_CNT_Msk               /*!< RTC Counter Low */\n\n/*******************  Bit definition for RTC_ALRH register  *******************/\n#define RTC_ALRH_RTC_ALR_Pos                (0U)                               \n#define RTC_ALRH_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)  /*!< 0x0000FFFF */\n#define RTC_ALRH_RTC_ALR                    RTC_ALRH_RTC_ALR_Msk               /*!< RTC Alarm High */\n\n/*******************  Bit definition for RTC_ALRL register  *******************/\n#define RTC_ALRL_RTC_ALR_Pos                (0U)                               \n#define RTC_ALRL_RTC_ALR_Msk                (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)  /*!< 0x0000FFFF */\n#define RTC_ALRL_RTC_ALR                    RTC_ALRL_RTC_ALR_Msk               /*!< RTC Alarm Low */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Independent WATCHDOG (IWDG)                         */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for IWDG_KR register  ********************/\n#define IWDG_KR_KEY_Pos                     (0U)                               \n#define IWDG_KR_KEY_Msk                     (0xFFFFUL << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */\n#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */\n\n/*******************  Bit definition for IWDG_PR register  ********************/\n#define IWDG_PR_PR_Pos                      (0U)                               \n#define IWDG_PR_PR_Msk                      (0x7UL << IWDG_PR_PR_Pos)           /*!< 0x00000007 */\n#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */\n#define IWDG_PR_PR_0                        (0x1UL << IWDG_PR_PR_Pos)           /*!< 0x00000001 */\n#define IWDG_PR_PR_1                        (0x2UL << IWDG_PR_PR_Pos)           /*!< 0x00000002 */\n#define IWDG_PR_PR_2                        (0x4UL << IWDG_PR_PR_Pos)           /*!< 0x00000004 */\n\n/*******************  Bit definition for IWDG_RLR register  *******************/\n#define IWDG_RLR_RL_Pos                     (0U)                               \n#define IWDG_RLR_RL_Msk                     (0xFFFUL << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */\n#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */\n\n/*******************  Bit definition for IWDG_SR register  ********************/\n#define IWDG_SR_PVU_Pos                     (0U)                               \n#define IWDG_SR_PVU_Msk                     (0x1UL << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */\n#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */\n#define IWDG_SR_RVU_Pos                     (1U)                               \n#define IWDG_SR_RVU_Msk                     (0x1UL << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */\n#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Window WATCHDOG (WWDG)                             */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for WWDG_CR register  ********************/\n#define WWDG_CR_T_Pos                       (0U)                               \n#define WWDG_CR_T_Msk                       (0x7FUL << WWDG_CR_T_Pos)           /*!< 0x0000007F */\n#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */\n#define WWDG_CR_T_0                         (0x01UL << WWDG_CR_T_Pos)           /*!< 0x00000001 */\n#define WWDG_CR_T_1                         (0x02UL << WWDG_CR_T_Pos)           /*!< 0x00000002 */\n#define WWDG_CR_T_2                         (0x04UL << WWDG_CR_T_Pos)           /*!< 0x00000004 */\n#define WWDG_CR_T_3                         (0x08UL << WWDG_CR_T_Pos)           /*!< 0x00000008 */\n#define WWDG_CR_T_4                         (0x10UL << WWDG_CR_T_Pos)           /*!< 0x00000010 */\n#define WWDG_CR_T_5                         (0x20UL << WWDG_CR_T_Pos)           /*!< 0x00000020 */\n#define WWDG_CR_T_6                         (0x40UL << WWDG_CR_T_Pos)           /*!< 0x00000040 */\n\n/* Legacy defines */\n#define  WWDG_CR_T0 WWDG_CR_T_0\n#define  WWDG_CR_T1 WWDG_CR_T_1\n#define  WWDG_CR_T2 WWDG_CR_T_2\n#define  WWDG_CR_T3 WWDG_CR_T_3\n#define  WWDG_CR_T4 WWDG_CR_T_4\n#define  WWDG_CR_T5 WWDG_CR_T_5\n#define  WWDG_CR_T6 WWDG_CR_T_6\n\n#define WWDG_CR_WDGA_Pos                    (7U)                               \n#define WWDG_CR_WDGA_Msk                    (0x1UL << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */\n#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */\n\n/*******************  Bit definition for WWDG_CFR register  *******************/\n#define WWDG_CFR_W_Pos                      (0U)                               \n#define WWDG_CFR_W_Msk                      (0x7FUL << WWDG_CFR_W_Pos)          /*!< 0x0000007F */\n#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */\n#define WWDG_CFR_W_0                        (0x01UL << WWDG_CFR_W_Pos)          /*!< 0x00000001 */\n#define WWDG_CFR_W_1                        (0x02UL << WWDG_CFR_W_Pos)          /*!< 0x00000002 */\n#define WWDG_CFR_W_2                        (0x04UL << WWDG_CFR_W_Pos)          /*!< 0x00000004 */\n#define WWDG_CFR_W_3                        (0x08UL << WWDG_CFR_W_Pos)          /*!< 0x00000008 */\n#define WWDG_CFR_W_4                        (0x10UL << WWDG_CFR_W_Pos)          /*!< 0x00000010 */\n#define WWDG_CFR_W_5                        (0x20UL << WWDG_CFR_W_Pos)          /*!< 0x00000020 */\n#define WWDG_CFR_W_6                        (0x40UL << WWDG_CFR_W_Pos)          /*!< 0x00000040 */\n\n/* Legacy defines */\n#define  WWDG_CFR_W0 WWDG_CFR_W_0\n#define  WWDG_CFR_W1 WWDG_CFR_W_1\n#define  WWDG_CFR_W2 WWDG_CFR_W_2\n#define  WWDG_CFR_W3 WWDG_CFR_W_3\n#define  WWDG_CFR_W4 WWDG_CFR_W_4\n#define  WWDG_CFR_W5 WWDG_CFR_W_5\n#define  WWDG_CFR_W6 WWDG_CFR_W_6\n\n#define WWDG_CFR_WDGTB_Pos                  (7U)                               \n#define WWDG_CFR_WDGTB_Msk                  (0x3UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */\n#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */\n#define WWDG_CFR_WDGTB_0                    (0x1UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */\n#define WWDG_CFR_WDGTB_1                    (0x2UL << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */\n\n/* Legacy defines */\n#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0\n#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1\n\n#define WWDG_CFR_EWI_Pos                    (9U)                               \n#define WWDG_CFR_EWI_Msk                    (0x1UL << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */\n#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */\n\n/*******************  Bit definition for WWDG_SR register  ********************/\n#define WWDG_SR_EWIF_Pos                    (0U)                               \n#define WWDG_SR_EWIF_Msk                    (0x1UL << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */\n#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                   USB Device FS                            */\n/*                                                                            */\n/******************************************************************************/\n\n/*!< Endpoint-specific registers */\n#define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */\n#define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */\n#define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */\n#define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */\n#define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */\n#define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */\n#define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */\n#define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */\n\n/* bit positions */ \n#define USB_EP_CTR_RX_Pos                       (15U)                          \n#define USB_EP_CTR_RX_Msk                       (0x1UL << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */\n#define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */\n#define USB_EP_DTOG_RX_Pos                      (14U)                          \n#define USB_EP_DTOG_RX_Msk                      (0x1UL << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */\n#define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */\n#define USB_EPRX_STAT_Pos                       (12U)                          \n#define USB_EPRX_STAT_Msk                       (0x3UL << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */\n#define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */\n#define USB_EP_SETUP_Pos                        (11U)                          \n#define USB_EP_SETUP_Msk                        (0x1UL << USB_EP_SETUP_Pos)     /*!< 0x00000800 */\n#define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */\n#define USB_EP_T_FIELD_Pos                      (9U)                           \n#define USB_EP_T_FIELD_Msk                      (0x3UL << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */\n#define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */\n#define USB_EP_KIND_Pos                         (8U)                           \n#define USB_EP_KIND_Msk                         (0x1UL << USB_EP_KIND_Pos)      /*!< 0x00000100 */\n#define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */\n#define USB_EP_CTR_TX_Pos                       (7U)                           \n#define USB_EP_CTR_TX_Msk                       (0x1UL << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */\n#define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */\n#define USB_EP_DTOG_TX_Pos                      (6U)                           \n#define USB_EP_DTOG_TX_Msk                      (0x1UL << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */\n#define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */\n#define USB_EPTX_STAT_Pos                       (4U)                           \n#define USB_EPTX_STAT_Msk                       (0x3UL << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */\n#define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */\n#define USB_EPADDR_FIELD_Pos                    (0U)                           \n#define USB_EPADDR_FIELD_Msk                    (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */\n#define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */\n\n/* EndPoint REGister MASK (no toggle fields) */\n#define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)\n                                                                           /*!< EP_TYPE[1:0] EndPoint TYPE */\n#define USB_EP_TYPE_MASK_Pos                    (9U)                           \n#define USB_EP_TYPE_MASK_Msk                    (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */\n#define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */\n#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */\n#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */\n#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */\n#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */\n#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)\n\n#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */\n                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */\n#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */\n#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */\n#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */\n#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */\n#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */\n#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */\n#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)\n                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */\n#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */\n#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */\n#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */\n#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */\n#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */\n#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */\n#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)\n\n/*******************  Bit definition for USB_EP0R register  *******************/\n#define USB_EP0R_EA_Pos                         (0U)                           \n#define USB_EP0R_EA_Msk                         (0xFUL << USB_EP0R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP0R_STAT_TX_Pos                    (4U)                           \n#define USB_EP0R_STAT_TX_Msk                    (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP0R_STAT_TX_0                      (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP0R_STAT_TX_1                      (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP0R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP0R_DTOG_TX_Msk                    (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP0R_CTR_TX_Pos                     (7U)                           \n#define USB_EP0R_CTR_TX_Msk                     (0x1UL << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP0R_EP_KIND_Pos                    (8U)                           \n#define USB_EP0R_EP_KIND_Msk                    (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */\n                                                                           \n#define USB_EP0R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP0R_EP_TYPE_Msk                    (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP0R_EP_TYPE_0                      (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP0R_EP_TYPE_1                      (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP0R_SETUP_Pos                      (11U)                          \n#define USB_EP0R_SETUP_Msk                      (0x1UL << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP0R_STAT_RX_Pos                    (12U)                          \n#define USB_EP0R_STAT_RX_Msk                    (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP0R_STAT_RX_0                      (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP0R_STAT_RX_1                      (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP0R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP0R_DTOG_RX_Msk                    (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP0R_CTR_RX_Pos                     (15U)                          \n#define USB_EP0R_CTR_RX_Msk                     (0x1UL << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP1R register  *******************/\n#define USB_EP1R_EA_Pos                         (0U)                           \n#define USB_EP1R_EA_Msk                         (0xFUL << USB_EP1R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */\n                                                                          \n#define USB_EP1R_STAT_TX_Pos                    (4U)                           \n#define USB_EP1R_STAT_TX_Msk                    (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP1R_STAT_TX_0                      (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP1R_STAT_TX_1                      (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP1R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP1R_DTOG_TX_Msk                    (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP1R_CTR_TX_Pos                     (7U)                           \n#define USB_EP1R_CTR_TX_Msk                     (0x1UL << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP1R_EP_KIND_Pos                    (8U)                           \n#define USB_EP1R_EP_KIND_Msk                    (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP1R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP1R_EP_TYPE_Msk                    (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP1R_EP_TYPE_0                      (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP1R_EP_TYPE_1                      (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP1R_SETUP_Pos                      (11U)                          \n#define USB_EP1R_SETUP_Msk                      (0x1UL << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */\n                                                                           \n#define USB_EP1R_STAT_RX_Pos                    (12U)                          \n#define USB_EP1R_STAT_RX_Msk                    (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP1R_STAT_RX_0                      (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP1R_STAT_RX_1                      (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP1R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP1R_DTOG_RX_Msk                    (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP1R_CTR_RX_Pos                     (15U)                          \n#define USB_EP1R_CTR_RX_Msk                     (0x1UL << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP2R register  *******************/\n#define USB_EP2R_EA_Pos                         (0U)                           \n#define USB_EP2R_EA_Msk                         (0xFUL << USB_EP2R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP2R_STAT_TX_Pos                    (4U)                           \n#define USB_EP2R_STAT_TX_Msk                    (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP2R_STAT_TX_0                      (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP2R_STAT_TX_1                      (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP2R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP2R_DTOG_TX_Msk                    (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP2R_CTR_TX_Pos                     (7U)                           \n#define USB_EP2R_CTR_TX_Msk                     (0x1UL << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP2R_EP_KIND_Pos                    (8U)                           \n#define USB_EP2R_EP_KIND_Msk                    (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP2R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP2R_EP_TYPE_Msk                    (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP2R_EP_TYPE_0                      (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP2R_EP_TYPE_1                      (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP2R_SETUP_Pos                      (11U)                          \n#define USB_EP2R_SETUP_Msk                      (0x1UL << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP2R_STAT_RX_Pos                    (12U)                          \n#define USB_EP2R_STAT_RX_Msk                    (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP2R_STAT_RX_0                      (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP2R_STAT_RX_1                      (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP2R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP2R_DTOG_RX_Msk                    (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP2R_CTR_RX_Pos                     (15U)                          \n#define USB_EP2R_CTR_RX_Msk                     (0x1UL << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP3R register  *******************/\n#define USB_EP3R_EA_Pos                         (0U)                           \n#define USB_EP3R_EA_Msk                         (0xFUL << USB_EP3R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP3R_STAT_TX_Pos                    (4U)                           \n#define USB_EP3R_STAT_TX_Msk                    (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP3R_STAT_TX_0                      (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP3R_STAT_TX_1                      (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP3R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP3R_DTOG_TX_Msk                    (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP3R_CTR_TX_Pos                     (7U)                           \n#define USB_EP3R_CTR_TX_Msk                     (0x1UL << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP3R_EP_KIND_Pos                    (8U)                           \n#define USB_EP3R_EP_KIND_Msk                    (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP3R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP3R_EP_TYPE_Msk                    (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP3R_EP_TYPE_0                      (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP3R_EP_TYPE_1                      (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP3R_SETUP_Pos                      (11U)                          \n#define USB_EP3R_SETUP_Msk                      (0x1UL << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP3R_STAT_RX_Pos                    (12U)                          \n#define USB_EP3R_STAT_RX_Msk                    (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP3R_STAT_RX_0                      (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP3R_STAT_RX_1                      (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP3R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP3R_DTOG_RX_Msk                    (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP3R_CTR_RX_Pos                     (15U)                          \n#define USB_EP3R_CTR_RX_Msk                     (0x1UL << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP4R register  *******************/\n#define USB_EP4R_EA_Pos                         (0U)                           \n#define USB_EP4R_EA_Msk                         (0xFUL << USB_EP4R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP4R_STAT_TX_Pos                    (4U)                           \n#define USB_EP4R_STAT_TX_Msk                    (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP4R_STAT_TX_0                      (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP4R_STAT_TX_1                      (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP4R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP4R_DTOG_TX_Msk                    (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP4R_CTR_TX_Pos                     (7U)                           \n#define USB_EP4R_CTR_TX_Msk                     (0x1UL << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP4R_EP_KIND_Pos                    (8U)                           \n#define USB_EP4R_EP_KIND_Msk                    (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP4R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP4R_EP_TYPE_Msk                    (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP4R_EP_TYPE_0                      (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP4R_EP_TYPE_1                      (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP4R_SETUP_Pos                      (11U)                          \n#define USB_EP4R_SETUP_Msk                      (0x1UL << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP4R_STAT_RX_Pos                    (12U)                          \n#define USB_EP4R_STAT_RX_Msk                    (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP4R_STAT_RX_0                      (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP4R_STAT_RX_1                      (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP4R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP4R_DTOG_RX_Msk                    (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP4R_CTR_RX_Pos                     (15U)                          \n#define USB_EP4R_CTR_RX_Msk                     (0x1UL << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP5R register  *******************/\n#define USB_EP5R_EA_Pos                         (0U)                           \n#define USB_EP5R_EA_Msk                         (0xFUL << USB_EP5R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP5R_STAT_TX_Pos                    (4U)                           \n#define USB_EP5R_STAT_TX_Msk                    (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP5R_STAT_TX_0                      (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP5R_STAT_TX_1                      (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP5R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP5R_DTOG_TX_Msk                    (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP5R_CTR_TX_Pos                     (7U)                           \n#define USB_EP5R_CTR_TX_Msk                     (0x1UL << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP5R_EP_KIND_Pos                    (8U)                           \n#define USB_EP5R_EP_KIND_Msk                    (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP5R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP5R_EP_TYPE_Msk                    (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP5R_EP_TYPE_0                      (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP5R_EP_TYPE_1                      (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP5R_SETUP_Pos                      (11U)                          \n#define USB_EP5R_SETUP_Msk                      (0x1UL << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP5R_STAT_RX_Pos                    (12U)                          \n#define USB_EP5R_STAT_RX_Msk                    (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP5R_STAT_RX_0                      (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP5R_STAT_RX_1                      (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP5R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP5R_DTOG_RX_Msk                    (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP5R_CTR_RX_Pos                     (15U)                          \n#define USB_EP5R_CTR_RX_Msk                     (0x1UL << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP6R register  *******************/\n#define USB_EP6R_EA_Pos                         (0U)                           \n#define USB_EP6R_EA_Msk                         (0xFUL << USB_EP6R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP6R_STAT_TX_Pos                    (4U)                           \n#define USB_EP6R_STAT_TX_Msk                    (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP6R_STAT_TX_0                      (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP6R_STAT_TX_1                      (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP6R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP6R_DTOG_TX_Msk                    (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP6R_CTR_TX_Pos                     (7U)                           \n#define USB_EP6R_CTR_TX_Msk                     (0x1UL << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP6R_EP_KIND_Pos                    (8U)                           \n#define USB_EP6R_EP_KIND_Msk                    (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP6R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP6R_EP_TYPE_Msk                    (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP6R_EP_TYPE_0                      (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP6R_EP_TYPE_1                      (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP6R_SETUP_Pos                      (11U)                          \n#define USB_EP6R_SETUP_Msk                      (0x1UL << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP6R_STAT_RX_Pos                    (12U)                          \n#define USB_EP6R_STAT_RX_Msk                    (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP6R_STAT_RX_0                      (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP6R_STAT_RX_1                      (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP6R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP6R_DTOG_RX_Msk                    (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP6R_CTR_RX_Pos                     (15U)                          \n#define USB_EP6R_CTR_RX_Msk                     (0x1UL << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*******************  Bit definition for USB_EP7R register  *******************/\n#define USB_EP7R_EA_Pos                         (0U)                           \n#define USB_EP7R_EA_Msk                         (0xFUL << USB_EP7R_EA_Pos)      /*!< 0x0000000F */\n#define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */\n\n#define USB_EP7R_STAT_TX_Pos                    (4U)                           \n#define USB_EP7R_STAT_TX_Msk                    (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */\n#define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */\n#define USB_EP7R_STAT_TX_0                      (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */\n#define USB_EP7R_STAT_TX_1                      (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */\n\n#define USB_EP7R_DTOG_TX_Pos                    (6U)                           \n#define USB_EP7R_DTOG_TX_Msk                    (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */\n#define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */\n#define USB_EP7R_CTR_TX_Pos                     (7U)                           \n#define USB_EP7R_CTR_TX_Msk                     (0x1UL << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */\n#define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */\n#define USB_EP7R_EP_KIND_Pos                    (8U)                           \n#define USB_EP7R_EP_KIND_Msk                    (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */\n#define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */\n\n#define USB_EP7R_EP_TYPE_Pos                    (9U)                           \n#define USB_EP7R_EP_TYPE_Msk                    (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */\n#define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */\n#define USB_EP7R_EP_TYPE_0                      (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */\n#define USB_EP7R_EP_TYPE_1                      (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */\n\n#define USB_EP7R_SETUP_Pos                      (11U)                          \n#define USB_EP7R_SETUP_Msk                      (0x1UL << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */\n#define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */\n\n#define USB_EP7R_STAT_RX_Pos                    (12U)                          \n#define USB_EP7R_STAT_RX_Msk                    (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */\n#define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */\n#define USB_EP7R_STAT_RX_0                      (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */\n#define USB_EP7R_STAT_RX_1                      (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */\n\n#define USB_EP7R_DTOG_RX_Pos                    (14U)                          \n#define USB_EP7R_DTOG_RX_Msk                    (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */\n#define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */\n#define USB_EP7R_CTR_RX_Pos                     (15U)                          \n#define USB_EP7R_CTR_RX_Msk                     (0x1UL << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */\n#define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */\n\n/*!< Common registers */\n/*******************  Bit definition for USB_CNTR register  *******************/\n#define USB_CNTR_FRES_Pos                       (0U)                           \n#define USB_CNTR_FRES_Msk                       (0x1UL << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */\n#define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */\n#define USB_CNTR_PDWN_Pos                       (1U)                           \n#define USB_CNTR_PDWN_Msk                       (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */\n#define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */\n#define USB_CNTR_LP_MODE_Pos                    (2U)                           \n#define USB_CNTR_LP_MODE_Msk                    (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */\n#define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */\n#define USB_CNTR_FSUSP_Pos                      (3U)                           \n#define USB_CNTR_FSUSP_Msk                      (0x1UL << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */\n#define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */\n#define USB_CNTR_RESUME_Pos                     (4U)                           \n#define USB_CNTR_RESUME_Msk                     (0x1UL << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */\n#define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */\n#define USB_CNTR_ESOFM_Pos                      (8U)                           \n#define USB_CNTR_ESOFM_Msk                      (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */\n#define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */\n#define USB_CNTR_SOFM_Pos                       (9U)                           \n#define USB_CNTR_SOFM_Msk                       (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */\n#define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */\n#define USB_CNTR_RESETM_Pos                     (10U)                          \n#define USB_CNTR_RESETM_Msk                     (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */\n#define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */\n#define USB_CNTR_SUSPM_Pos                      (11U)                          \n#define USB_CNTR_SUSPM_Msk                      (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */\n#define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */\n#define USB_CNTR_WKUPM_Pos                      (12U)                          \n#define USB_CNTR_WKUPM_Msk                      (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */\n#define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */\n#define USB_CNTR_ERRM_Pos                       (13U)                          \n#define USB_CNTR_ERRM_Msk                       (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */\n#define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */\n#define USB_CNTR_PMAOVRM_Pos                    (14U)                          \n#define USB_CNTR_PMAOVRM_Msk                    (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */\n#define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */\n#define USB_CNTR_CTRM_Pos                       (15U)                          \n#define USB_CNTR_CTRM_Msk                       (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */\n#define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */\n\n/*******************  Bit definition for USB_ISTR register  *******************/\n#define USB_ISTR_EP_ID_Pos                      (0U)                           \n#define USB_ISTR_EP_ID_Msk                      (0xFUL << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */\n#define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */\n#define USB_ISTR_DIR_Pos                        (4U)                           \n#define USB_ISTR_DIR_Msk                        (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */\n#define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */\n#define USB_ISTR_ESOF_Pos                       (8U)                           \n#define USB_ISTR_ESOF_Msk                       (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */\n#define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */\n#define USB_ISTR_SOF_Pos                        (9U)                           \n#define USB_ISTR_SOF_Msk                        (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */\n#define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */\n#define USB_ISTR_RESET_Pos                      (10U)                          \n#define USB_ISTR_RESET_Msk                      (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */\n#define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */\n#define USB_ISTR_SUSP_Pos                       (11U)                          \n#define USB_ISTR_SUSP_Msk                       (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */\n#define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */\n#define USB_ISTR_WKUP_Pos                       (12U)                          \n#define USB_ISTR_WKUP_Msk                       (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */\n#define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */\n#define USB_ISTR_ERR_Pos                        (13U)                          \n#define USB_ISTR_ERR_Msk                        (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */\n#define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */\n#define USB_ISTR_PMAOVR_Pos                     (14U)                          \n#define USB_ISTR_PMAOVR_Msk                     (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */\n#define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */\n#define USB_ISTR_CTR_Pos                        (15U)                          \n#define USB_ISTR_CTR_Msk                        (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */\n#define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */\n\n/*******************  Bit definition for USB_FNR register  ********************/\n#define USB_FNR_FN_Pos                          (0U)                           \n#define USB_FNR_FN_Msk                          (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */\n#define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */\n#define USB_FNR_LSOF_Pos                        (11U)                          \n#define USB_FNR_LSOF_Msk                        (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */\n#define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */\n#define USB_FNR_LCK_Pos                         (13U)                          \n#define USB_FNR_LCK_Msk                         (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */\n#define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */\n#define USB_FNR_RXDM_Pos                        (14U)                          \n#define USB_FNR_RXDM_Msk                        (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */\n#define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */\n#define USB_FNR_RXDP_Pos                        (15U)                          \n#define USB_FNR_RXDP_Msk                        (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */\n#define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */\n\n/******************  Bit definition for USB_DADDR register  *******************/\n#define USB_DADDR_ADD_Pos                       (0U)                           \n#define USB_DADDR_ADD_Msk                       (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */\n#define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */\n#define USB_DADDR_ADD0_Pos                      (0U)                           \n#define USB_DADDR_ADD0_Msk                      (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */\n#define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */\n#define USB_DADDR_ADD1_Pos                      (1U)                           \n#define USB_DADDR_ADD1_Msk                      (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */\n#define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */\n#define USB_DADDR_ADD2_Pos                      (2U)                           \n#define USB_DADDR_ADD2_Msk                      (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */\n#define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */\n#define USB_DADDR_ADD3_Pos                      (3U)                           \n#define USB_DADDR_ADD3_Msk                      (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */\n#define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */\n#define USB_DADDR_ADD4_Pos                      (4U)                           \n#define USB_DADDR_ADD4_Msk                      (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */\n#define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */\n#define USB_DADDR_ADD5_Pos                      (5U)                           \n#define USB_DADDR_ADD5_Msk                      (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */\n#define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */\n#define USB_DADDR_ADD6_Pos                      (6U)                           \n#define USB_DADDR_ADD6_Msk                      (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */\n#define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */\n\n#define USB_DADDR_EF_Pos                        (7U)                           \n#define USB_DADDR_EF_Msk                        (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */\n#define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */\n\n/******************  Bit definition for USB_BTABLE register  ******************/    \n#define USB_BTABLE_BTABLE_Pos                   (3U)                           \n#define USB_BTABLE_BTABLE_Msk                   (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */\n#define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */\n\n/*!< Buffer descriptor table */\n/*****************  Bit definition for USB_ADDR0_TX register  *****************/\n#define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)                           \n#define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */\n\n/*****************  Bit definition for USB_ADDR1_TX register  *****************/\n#define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)                           \n#define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */\n\n/*****************  Bit definition for USB_ADDR2_TX register  *****************/\n#define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)                           \n#define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */\n\n/*****************  Bit definition for USB_ADDR3_TX register  *****************/\n#define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)                           \n#define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */\n\n/*****************  Bit definition for USB_ADDR4_TX register  *****************/\n#define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)                           \n#define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */\n\n/*****************  Bit definition for USB_ADDR5_TX register  *****************/\n#define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)                           \n#define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */\n\n/*****************  Bit definition for USB_ADDR6_TX register  *****************/\n#define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)                           \n#define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */\n\n/*****************  Bit definition for USB_ADDR7_TX register  *****************/\n#define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)                           \n#define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_COUNT0_TX register  ****************/\n#define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)                           \n#define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */\n\n/*****************  Bit definition for USB_COUNT1_TX register  ****************/\n#define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)                           \n#define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */\n\n/*****************  Bit definition for USB_COUNT2_TX register  ****************/\n#define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)                           \n#define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */\n\n/*****************  Bit definition for USB_COUNT3_TX register  ****************/\n#define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)                           \n#define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */\n\n/*****************  Bit definition for USB_COUNT4_TX register  ****************/\n#define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)                           \n#define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */\n\n/*****************  Bit definition for USB_COUNT5_TX register  ****************/\n#define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)                           \n#define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */\n\n/*****************  Bit definition for USB_COUNT6_TX register  ****************/\n#define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)                           \n#define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */\n\n/*****************  Bit definition for USB_COUNT7_TX register  ****************/\n#define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)                           \n#define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */\n#define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/\n#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */\n\n/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/\n#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */\n\n/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/\n#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */\n\n/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/\n#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */\n\n/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/\n#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */\n\n/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/\n#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */\n\n/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/\n#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */\n\n/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/\n#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */\n\n/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/\n#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */\n\n/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/\n#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */\n\n/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/\n#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */\n\n/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/\n#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */\n\n/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/\n#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */\n\n/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/\n#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */\n\n/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/\n#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */\n\n/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/\n#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_ADDR0_RX register  *****************/\n#define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)                           \n#define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */\n\n/*****************  Bit definition for USB_ADDR1_RX register  *****************/\n#define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)                           \n#define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */\n\n/*****************  Bit definition for USB_ADDR2_RX register  *****************/\n#define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)                           \n#define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */\n\n/*****************  Bit definition for USB_ADDR3_RX register  *****************/\n#define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)                           \n#define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */\n\n/*****************  Bit definition for USB_ADDR4_RX register  *****************/\n#define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)                           \n#define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */\n\n/*****************  Bit definition for USB_ADDR5_RX register  *****************/\n#define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)                           \n#define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */\n\n/*****************  Bit definition for USB_ADDR6_RX register  *****************/\n#define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)                           \n#define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */\n\n/*****************  Bit definition for USB_ADDR7_RX register  *****************/\n#define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)                           \n#define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */\n#define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */\n\n/*----------------------------------------------------------------------------*/\n\n/*****************  Bit definition for USB_COUNT0_RX register  ****************/\n#define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)                           \n#define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT0_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT0_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT0_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT0_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT0_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT0_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT0_RX_BLSIZE_Msk                (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT1_RX register  ****************/\n#define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)                           \n#define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT1_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT1_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT1_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT1_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT1_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT1_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT1_RX_BLSIZE_Msk                (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT2_RX register  ****************/\n#define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)                           \n#define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT2_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT2_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT2_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT2_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT2_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT2_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT2_RX_BLSIZE_Msk                (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT3_RX register  ****************/\n#define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)                           \n#define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT3_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT3_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT3_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT3_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT3_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT3_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT3_RX_BLSIZE_Msk                (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT4_RX register  ****************/\n#define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)                           \n#define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT4_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT4_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT4_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT4_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT4_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT4_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT4_RX_BLSIZE_Msk                (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT5_RX register  ****************/\n#define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)                           \n#define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT5_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT5_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT5_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT5_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT5_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT5_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT5_RX_BLSIZE_Msk                (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT6_RX register  ****************/\n#define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)                           \n#define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT6_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT6_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT6_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT6_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT6_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT6_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT6_RX_BLSIZE_Msk                (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*****************  Bit definition for USB_COUNT7_RX register  ****************/\n#define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)                           \n#define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */\n#define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */\n\n#define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)                          \n#define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */\n#define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */\n#define USB_COUNT7_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */\n#define USB_COUNT7_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */\n#define USB_COUNT7_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */\n#define USB_COUNT7_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */\n#define USB_COUNT7_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */\n\n#define USB_COUNT7_RX_BLSIZE_Pos                (15U)                          \n#define USB_COUNT7_RX_BLSIZE_Msk                (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */\n#define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */\n\n/*----------------------------------------------------------------------------*/\n\n/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/\n#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/\n#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */\n#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/\n#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/\n#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/\n#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/\n#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/\n#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/\n#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/\n#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/\n#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/\n#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/\n#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/\n#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/\n#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */\n\n#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */\n#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */\n#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */\n#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */\n#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */\n\n#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */\n\n/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/\n#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */\n\n#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */\n#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */\n#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */\n#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */\n#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */\n#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */\n\n#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */\n\n/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/\n#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */\n\n#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */\n#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */\n#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */\n#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */\n#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */\n#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */\n\n#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */\n\n/******************************************************************************/\n/*                                                                            */\n/*                         Controller Area Network                            */\n/*                                                                            */\n/******************************************************************************/\n\n/*!< CAN control and status registers */\n/*******************  Bit definition for CAN_MCR register  ********************/\n#define CAN_MCR_INRQ_Pos                     (0U)                              \n#define CAN_MCR_INRQ_Msk                     (0x1UL << CAN_MCR_INRQ_Pos)        /*!< 0x00000001 */\n#define CAN_MCR_INRQ                         CAN_MCR_INRQ_Msk                  /*!< Initialization Request */\n#define CAN_MCR_SLEEP_Pos                    (1U)                              \n#define CAN_MCR_SLEEP_Msk                    (0x1UL << CAN_MCR_SLEEP_Pos)       /*!< 0x00000002 */\n#define CAN_MCR_SLEEP                        CAN_MCR_SLEEP_Msk                 /*!< Sleep Mode Request */\n#define CAN_MCR_TXFP_Pos                     (2U)                              \n#define CAN_MCR_TXFP_Msk                     (0x1UL << CAN_MCR_TXFP_Pos)        /*!< 0x00000004 */\n#define CAN_MCR_TXFP                         CAN_MCR_TXFP_Msk                  /*!< Transmit FIFO Priority */\n#define CAN_MCR_RFLM_Pos                     (3U)                              \n#define CAN_MCR_RFLM_Msk                     (0x1UL << CAN_MCR_RFLM_Pos)        /*!< 0x00000008 */\n#define CAN_MCR_RFLM                         CAN_MCR_RFLM_Msk                  /*!< Receive FIFO Locked Mode */\n#define CAN_MCR_NART_Pos                     (4U)                              \n#define CAN_MCR_NART_Msk                     (0x1UL << CAN_MCR_NART_Pos)        /*!< 0x00000010 */\n#define CAN_MCR_NART                         CAN_MCR_NART_Msk                  /*!< No Automatic Retransmission */\n#define CAN_MCR_AWUM_Pos                     (5U)                              \n#define CAN_MCR_AWUM_Msk                     (0x1UL << CAN_MCR_AWUM_Pos)        /*!< 0x00000020 */\n#define CAN_MCR_AWUM                         CAN_MCR_AWUM_Msk                  /*!< Automatic Wakeup Mode */\n#define CAN_MCR_ABOM_Pos                     (6U)                              \n#define CAN_MCR_ABOM_Msk                     (0x1UL << CAN_MCR_ABOM_Pos)        /*!< 0x00000040 */\n#define CAN_MCR_ABOM                         CAN_MCR_ABOM_Msk                  /*!< Automatic Bus-Off Management */\n#define CAN_MCR_TTCM_Pos                     (7U)                              \n#define CAN_MCR_TTCM_Msk                     (0x1UL << CAN_MCR_TTCM_Pos)        /*!< 0x00000080 */\n#define CAN_MCR_TTCM                         CAN_MCR_TTCM_Msk                  /*!< Time Triggered Communication Mode */\n#define CAN_MCR_RESET_Pos                    (15U)                             \n#define CAN_MCR_RESET_Msk                    (0x1UL << CAN_MCR_RESET_Pos)       /*!< 0x00008000 */\n#define CAN_MCR_RESET                        CAN_MCR_RESET_Msk                 /*!< CAN software master reset */\n#define CAN_MCR_DBF_Pos                      (16U)                             \n#define CAN_MCR_DBF_Msk                      (0x1UL << CAN_MCR_DBF_Pos)         /*!< 0x00010000 */\n#define CAN_MCR_DBF                          CAN_MCR_DBF_Msk                   /*!< CAN Debug freeze */\n\n/*******************  Bit definition for CAN_MSR register  ********************/\n#define CAN_MSR_INAK_Pos                     (0U)                              \n#define CAN_MSR_INAK_Msk                     (0x1UL << CAN_MSR_INAK_Pos)        /*!< 0x00000001 */\n#define CAN_MSR_INAK                         CAN_MSR_INAK_Msk                  /*!< Initialization Acknowledge */\n#define CAN_MSR_SLAK_Pos                     (1U)                              \n#define CAN_MSR_SLAK_Msk                     (0x1UL << CAN_MSR_SLAK_Pos)        /*!< 0x00000002 */\n#define CAN_MSR_SLAK                         CAN_MSR_SLAK_Msk                  /*!< Sleep Acknowledge */\n#define CAN_MSR_ERRI_Pos                     (2U)                              \n#define CAN_MSR_ERRI_Msk                     (0x1UL << CAN_MSR_ERRI_Pos)        /*!< 0x00000004 */\n#define CAN_MSR_ERRI                         CAN_MSR_ERRI_Msk                  /*!< Error Interrupt */\n#define CAN_MSR_WKUI_Pos                     (3U)                              \n#define CAN_MSR_WKUI_Msk                     (0x1UL << CAN_MSR_WKUI_Pos)        /*!< 0x00000008 */\n#define CAN_MSR_WKUI                         CAN_MSR_WKUI_Msk                  /*!< Wakeup Interrupt */\n#define CAN_MSR_SLAKI_Pos                    (4U)                              \n#define CAN_MSR_SLAKI_Msk                    (0x1UL << CAN_MSR_SLAKI_Pos)       /*!< 0x00000010 */\n#define CAN_MSR_SLAKI                        CAN_MSR_SLAKI_Msk                 /*!< Sleep Acknowledge Interrupt */\n#define CAN_MSR_TXM_Pos                      (8U)                              \n#define CAN_MSR_TXM_Msk                      (0x1UL << CAN_MSR_TXM_Pos)         /*!< 0x00000100 */\n#define CAN_MSR_TXM                          CAN_MSR_TXM_Msk                   /*!< Transmit Mode */\n#define CAN_MSR_RXM_Pos                      (9U)                              \n#define CAN_MSR_RXM_Msk                      (0x1UL << CAN_MSR_RXM_Pos)         /*!< 0x00000200 */\n#define CAN_MSR_RXM                          CAN_MSR_RXM_Msk                   /*!< Receive Mode */\n#define CAN_MSR_SAMP_Pos                     (10U)                             \n#define CAN_MSR_SAMP_Msk                     (0x1UL << CAN_MSR_SAMP_Pos)        /*!< 0x00000400 */\n#define CAN_MSR_SAMP                         CAN_MSR_SAMP_Msk                  /*!< Last Sample Point */\n#define CAN_MSR_RX_Pos                       (11U)                             \n#define CAN_MSR_RX_Msk                       (0x1UL << CAN_MSR_RX_Pos)          /*!< 0x00000800 */\n#define CAN_MSR_RX                           CAN_MSR_RX_Msk                    /*!< CAN Rx Signal */\n\n/*******************  Bit definition for CAN_TSR register  ********************/\n#define CAN_TSR_RQCP0_Pos                    (0U)                              \n#define CAN_TSR_RQCP0_Msk                    (0x1UL << CAN_TSR_RQCP0_Pos)       /*!< 0x00000001 */\n#define CAN_TSR_RQCP0                        CAN_TSR_RQCP0_Msk                 /*!< Request Completed Mailbox0 */\n#define CAN_TSR_TXOK0_Pos                    (1U)                              \n#define CAN_TSR_TXOK0_Msk                    (0x1UL << CAN_TSR_TXOK0_Pos)       /*!< 0x00000002 */\n#define CAN_TSR_TXOK0                        CAN_TSR_TXOK0_Msk                 /*!< Transmission OK of Mailbox0 */\n#define CAN_TSR_ALST0_Pos                    (2U)                              \n#define CAN_TSR_ALST0_Msk                    (0x1UL << CAN_TSR_ALST0_Pos)       /*!< 0x00000004 */\n#define CAN_TSR_ALST0                        CAN_TSR_ALST0_Msk                 /*!< Arbitration Lost for Mailbox0 */\n#define CAN_TSR_TERR0_Pos                    (3U)                              \n#define CAN_TSR_TERR0_Msk                    (0x1UL << CAN_TSR_TERR0_Pos)       /*!< 0x00000008 */\n#define CAN_TSR_TERR0                        CAN_TSR_TERR0_Msk                 /*!< Transmission Error of Mailbox0 */\n#define CAN_TSR_ABRQ0_Pos                    (7U)                              \n#define CAN_TSR_ABRQ0_Msk                    (0x1UL << CAN_TSR_ABRQ0_Pos)       /*!< 0x00000080 */\n#define CAN_TSR_ABRQ0                        CAN_TSR_ABRQ0_Msk                 /*!< Abort Request for Mailbox0 */\n#define CAN_TSR_RQCP1_Pos                    (8U)                              \n#define CAN_TSR_RQCP1_Msk                    (0x1UL << CAN_TSR_RQCP1_Pos)       /*!< 0x00000100 */\n#define CAN_TSR_RQCP1                        CAN_TSR_RQCP1_Msk                 /*!< Request Completed Mailbox1 */\n#define CAN_TSR_TXOK1_Pos                    (9U)                              \n#define CAN_TSR_TXOK1_Msk                    (0x1UL << CAN_TSR_TXOK1_Pos)       /*!< 0x00000200 */\n#define CAN_TSR_TXOK1                        CAN_TSR_TXOK1_Msk                 /*!< Transmission OK of Mailbox1 */\n#define CAN_TSR_ALST1_Pos                    (10U)                             \n#define CAN_TSR_ALST1_Msk                    (0x1UL << CAN_TSR_ALST1_Pos)       /*!< 0x00000400 */\n#define CAN_TSR_ALST1                        CAN_TSR_ALST1_Msk                 /*!< Arbitration Lost for Mailbox1 */\n#define CAN_TSR_TERR1_Pos                    (11U)                             \n#define CAN_TSR_TERR1_Msk                    (0x1UL << CAN_TSR_TERR1_Pos)       /*!< 0x00000800 */\n#define CAN_TSR_TERR1                        CAN_TSR_TERR1_Msk                 /*!< Transmission Error of Mailbox1 */\n#define CAN_TSR_ABRQ1_Pos                    (15U)                             \n#define CAN_TSR_ABRQ1_Msk                    (0x1UL << CAN_TSR_ABRQ1_Pos)       /*!< 0x00008000 */\n#define CAN_TSR_ABRQ1                        CAN_TSR_ABRQ1_Msk                 /*!< Abort Request for Mailbox 1 */\n#define CAN_TSR_RQCP2_Pos                    (16U)                             \n#define CAN_TSR_RQCP2_Msk                    (0x1UL << CAN_TSR_RQCP2_Pos)       /*!< 0x00010000 */\n#define CAN_TSR_RQCP2                        CAN_TSR_RQCP2_Msk                 /*!< Request Completed Mailbox2 */\n#define CAN_TSR_TXOK2_Pos                    (17U)                             \n#define CAN_TSR_TXOK2_Msk                    (0x1UL << CAN_TSR_TXOK2_Pos)       /*!< 0x00020000 */\n#define CAN_TSR_TXOK2                        CAN_TSR_TXOK2_Msk                 /*!< Transmission OK of Mailbox 2 */\n#define CAN_TSR_ALST2_Pos                    (18U)                             \n#define CAN_TSR_ALST2_Msk                    (0x1UL << CAN_TSR_ALST2_Pos)       /*!< 0x00040000 */\n#define CAN_TSR_ALST2                        CAN_TSR_ALST2_Msk                 /*!< Arbitration Lost for mailbox 2 */\n#define CAN_TSR_TERR2_Pos                    (19U)                             \n#define CAN_TSR_TERR2_Msk                    (0x1UL << CAN_TSR_TERR2_Pos)       /*!< 0x00080000 */\n#define CAN_TSR_TERR2                        CAN_TSR_TERR2_Msk                 /*!< Transmission Error of Mailbox 2 */\n#define CAN_TSR_ABRQ2_Pos                    (23U)                             \n#define CAN_TSR_ABRQ2_Msk                    (0x1UL << CAN_TSR_ABRQ2_Pos)       /*!< 0x00800000 */\n#define CAN_TSR_ABRQ2                        CAN_TSR_ABRQ2_Msk                 /*!< Abort Request for Mailbox 2 */\n#define CAN_TSR_CODE_Pos                     (24U)                             \n#define CAN_TSR_CODE_Msk                     (0x3UL << CAN_TSR_CODE_Pos)        /*!< 0x03000000 */\n#define CAN_TSR_CODE                         CAN_TSR_CODE_Msk                  /*!< Mailbox Code */\n\n#define CAN_TSR_TME_Pos                      (26U)                             \n#define CAN_TSR_TME_Msk                      (0x7UL << CAN_TSR_TME_Pos)         /*!< 0x1C000000 */\n#define CAN_TSR_TME                          CAN_TSR_TME_Msk                   /*!< TME[2:0] bits */\n#define CAN_TSR_TME0_Pos                     (26U)                             \n#define CAN_TSR_TME0_Msk                     (0x1UL << CAN_TSR_TME0_Pos)        /*!< 0x04000000 */\n#define CAN_TSR_TME0                         CAN_TSR_TME0_Msk                  /*!< Transmit Mailbox 0 Empty */\n#define CAN_TSR_TME1_Pos                     (27U)                             \n#define CAN_TSR_TME1_Msk                     (0x1UL << CAN_TSR_TME1_Pos)        /*!< 0x08000000 */\n#define CAN_TSR_TME1                         CAN_TSR_TME1_Msk                  /*!< Transmit Mailbox 1 Empty */\n#define CAN_TSR_TME2_Pos                     (28U)                             \n#define CAN_TSR_TME2_Msk                     (0x1UL << CAN_TSR_TME2_Pos)        /*!< 0x10000000 */\n#define CAN_TSR_TME2                         CAN_TSR_TME2_Msk                  /*!< Transmit Mailbox 2 Empty */\n\n#define CAN_TSR_LOW_Pos                      (29U)                             \n#define CAN_TSR_LOW_Msk                      (0x7UL << CAN_TSR_LOW_Pos)         /*!< 0xE0000000 */\n#define CAN_TSR_LOW                          CAN_TSR_LOW_Msk                   /*!< LOW[2:0] bits */\n#define CAN_TSR_LOW0_Pos                     (29U)                             \n#define CAN_TSR_LOW0_Msk                     (0x1UL << CAN_TSR_LOW0_Pos)        /*!< 0x20000000 */\n#define CAN_TSR_LOW0                         CAN_TSR_LOW0_Msk                  /*!< Lowest Priority Flag for Mailbox 0 */\n#define CAN_TSR_LOW1_Pos                     (30U)                             \n#define CAN_TSR_LOW1_Msk                     (0x1UL << CAN_TSR_LOW1_Pos)        /*!< 0x40000000 */\n#define CAN_TSR_LOW1                         CAN_TSR_LOW1_Msk                  /*!< Lowest Priority Flag for Mailbox 1 */\n#define CAN_TSR_LOW2_Pos                     (31U)                             \n#define CAN_TSR_LOW2_Msk                     (0x1UL << CAN_TSR_LOW2_Pos)        /*!< 0x80000000 */\n#define CAN_TSR_LOW2                         CAN_TSR_LOW2_Msk                  /*!< Lowest Priority Flag for Mailbox 2 */\n\n/*******************  Bit definition for CAN_RF0R register  *******************/\n#define CAN_RF0R_FMP0_Pos                    (0U)                              \n#define CAN_RF0R_FMP0_Msk                    (0x3UL << CAN_RF0R_FMP0_Pos)       /*!< 0x00000003 */\n#define CAN_RF0R_FMP0                        CAN_RF0R_FMP0_Msk                 /*!< FIFO 0 Message Pending */\n#define CAN_RF0R_FULL0_Pos                   (3U)                              \n#define CAN_RF0R_FULL0_Msk                   (0x1UL << CAN_RF0R_FULL0_Pos)      /*!< 0x00000008 */\n#define CAN_RF0R_FULL0                       CAN_RF0R_FULL0_Msk                /*!< FIFO 0 Full */\n#define CAN_RF0R_FOVR0_Pos                   (4U)                              \n#define CAN_RF0R_FOVR0_Msk                   (0x1UL << CAN_RF0R_FOVR0_Pos)      /*!< 0x00000010 */\n#define CAN_RF0R_FOVR0                       CAN_RF0R_FOVR0_Msk                /*!< FIFO 0 Overrun */\n#define CAN_RF0R_RFOM0_Pos                   (5U)                              \n#define CAN_RF0R_RFOM0_Msk                   (0x1UL << CAN_RF0R_RFOM0_Pos)      /*!< 0x00000020 */\n#define CAN_RF0R_RFOM0                       CAN_RF0R_RFOM0_Msk                /*!< Release FIFO 0 Output Mailbox */\n\n/*******************  Bit definition for CAN_RF1R register  *******************/\n#define CAN_RF1R_FMP1_Pos                    (0U)                              \n#define CAN_RF1R_FMP1_Msk                    (0x3UL << CAN_RF1R_FMP1_Pos)       /*!< 0x00000003 */\n#define CAN_RF1R_FMP1                        CAN_RF1R_FMP1_Msk                 /*!< FIFO 1 Message Pending */\n#define CAN_RF1R_FULL1_Pos                   (3U)                              \n#define CAN_RF1R_FULL1_Msk                   (0x1UL << CAN_RF1R_FULL1_Pos)      /*!< 0x00000008 */\n#define CAN_RF1R_FULL1                       CAN_RF1R_FULL1_Msk                /*!< FIFO 1 Full */\n#define CAN_RF1R_FOVR1_Pos                   (4U)                              \n#define CAN_RF1R_FOVR1_Msk                   (0x1UL << CAN_RF1R_FOVR1_Pos)      /*!< 0x00000010 */\n#define CAN_RF1R_FOVR1                       CAN_RF1R_FOVR1_Msk                /*!< FIFO 1 Overrun */\n#define CAN_RF1R_RFOM1_Pos                   (5U)                              \n#define CAN_RF1R_RFOM1_Msk                   (0x1UL << CAN_RF1R_RFOM1_Pos)      /*!< 0x00000020 */\n#define CAN_RF1R_RFOM1                       CAN_RF1R_RFOM1_Msk                /*!< Release FIFO 1 Output Mailbox */\n\n/********************  Bit definition for CAN_IER register  *******************/\n#define CAN_IER_TMEIE_Pos                    (0U)                              \n#define CAN_IER_TMEIE_Msk                    (0x1UL << CAN_IER_TMEIE_Pos)       /*!< 0x00000001 */\n#define CAN_IER_TMEIE                        CAN_IER_TMEIE_Msk                 /*!< Transmit Mailbox Empty Interrupt Enable */\n#define CAN_IER_FMPIE0_Pos                   (1U)                              \n#define CAN_IER_FMPIE0_Msk                   (0x1UL << CAN_IER_FMPIE0_Pos)      /*!< 0x00000002 */\n#define CAN_IER_FMPIE0                       CAN_IER_FMPIE0_Msk                /*!< FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE0_Pos                    (2U)                              \n#define CAN_IER_FFIE0_Msk                    (0x1UL << CAN_IER_FFIE0_Pos)       /*!< 0x00000004 */\n#define CAN_IER_FFIE0                        CAN_IER_FFIE0_Msk                 /*!< FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE0_Pos                   (3U)                              \n#define CAN_IER_FOVIE0_Msk                   (0x1UL << CAN_IER_FOVIE0_Pos)      /*!< 0x00000008 */\n#define CAN_IER_FOVIE0                       CAN_IER_FOVIE0_Msk                /*!< FIFO Overrun Interrupt Enable */\n#define CAN_IER_FMPIE1_Pos                   (4U)                              \n#define CAN_IER_FMPIE1_Msk                   (0x1UL << CAN_IER_FMPIE1_Pos)      /*!< 0x00000010 */\n#define CAN_IER_FMPIE1                       CAN_IER_FMPIE1_Msk                /*!< FIFO Message Pending Interrupt Enable */\n#define CAN_IER_FFIE1_Pos                    (5U)                              \n#define CAN_IER_FFIE1_Msk                    (0x1UL << CAN_IER_FFIE1_Pos)       /*!< 0x00000020 */\n#define CAN_IER_FFIE1                        CAN_IER_FFIE1_Msk                 /*!< FIFO Full Interrupt Enable */\n#define CAN_IER_FOVIE1_Pos                   (6U)                              \n#define CAN_IER_FOVIE1_Msk                   (0x1UL << CAN_IER_FOVIE1_Pos)      /*!< 0x00000040 */\n#define CAN_IER_FOVIE1                       CAN_IER_FOVIE1_Msk                /*!< FIFO Overrun Interrupt Enable */\n#define CAN_IER_EWGIE_Pos                    (8U)                              \n#define CAN_IER_EWGIE_Msk                    (0x1UL << CAN_IER_EWGIE_Pos)       /*!< 0x00000100 */\n#define CAN_IER_EWGIE                        CAN_IER_EWGIE_Msk                 /*!< Error Warning Interrupt Enable */\n#define CAN_IER_EPVIE_Pos                    (9U)                              \n#define CAN_IER_EPVIE_Msk                    (0x1UL << CAN_IER_EPVIE_Pos)       /*!< 0x00000200 */\n#define CAN_IER_EPVIE                        CAN_IER_EPVIE_Msk                 /*!< Error Passive Interrupt Enable */\n#define CAN_IER_BOFIE_Pos                    (10U)                             \n#define CAN_IER_BOFIE_Msk                    (0x1UL << CAN_IER_BOFIE_Pos)       /*!< 0x00000400 */\n#define CAN_IER_BOFIE                        CAN_IER_BOFIE_Msk                 /*!< Bus-Off Interrupt Enable */\n#define CAN_IER_LECIE_Pos                    (11U)                             \n#define CAN_IER_LECIE_Msk                    (0x1UL << CAN_IER_LECIE_Pos)       /*!< 0x00000800 */\n#define CAN_IER_LECIE                        CAN_IER_LECIE_Msk                 /*!< Last Error Code Interrupt Enable */\n#define CAN_IER_ERRIE_Pos                    (15U)                             \n#define CAN_IER_ERRIE_Msk                    (0x1UL << CAN_IER_ERRIE_Pos)       /*!< 0x00008000 */\n#define CAN_IER_ERRIE                        CAN_IER_ERRIE_Msk                 /*!< Error Interrupt Enable */\n#define CAN_IER_WKUIE_Pos                    (16U)                             \n#define CAN_IER_WKUIE_Msk                    (0x1UL << CAN_IER_WKUIE_Pos)       /*!< 0x00010000 */\n#define CAN_IER_WKUIE                        CAN_IER_WKUIE_Msk                 /*!< Wakeup Interrupt Enable */\n#define CAN_IER_SLKIE_Pos                    (17U)                             \n#define CAN_IER_SLKIE_Msk                    (0x1UL << CAN_IER_SLKIE_Pos)       /*!< 0x00020000 */\n#define CAN_IER_SLKIE                        CAN_IER_SLKIE_Msk                 /*!< Sleep Interrupt Enable */\n\n/********************  Bit definition for CAN_ESR register  *******************/\n#define CAN_ESR_EWGF_Pos                     (0U)                              \n#define CAN_ESR_EWGF_Msk                     (0x1UL << CAN_ESR_EWGF_Pos)        /*!< 0x00000001 */\n#define CAN_ESR_EWGF                         CAN_ESR_EWGF_Msk                  /*!< Error Warning Flag */\n#define CAN_ESR_EPVF_Pos                     (1U)                              \n#define CAN_ESR_EPVF_Msk                     (0x1UL << CAN_ESR_EPVF_Pos)        /*!< 0x00000002 */\n#define CAN_ESR_EPVF                         CAN_ESR_EPVF_Msk                  /*!< Error Passive Flag */\n#define CAN_ESR_BOFF_Pos                     (2U)                              \n#define CAN_ESR_BOFF_Msk                     (0x1UL << CAN_ESR_BOFF_Pos)        /*!< 0x00000004 */\n#define CAN_ESR_BOFF                         CAN_ESR_BOFF_Msk                  /*!< Bus-Off Flag */\n\n#define CAN_ESR_LEC_Pos                      (4U)                              \n#define CAN_ESR_LEC_Msk                      (0x7UL << CAN_ESR_LEC_Pos)         /*!< 0x00000070 */\n#define CAN_ESR_LEC                          CAN_ESR_LEC_Msk                   /*!< LEC[2:0] bits (Last Error Code) */\n#define CAN_ESR_LEC_0                        (0x1UL << CAN_ESR_LEC_Pos)         /*!< 0x00000010 */\n#define CAN_ESR_LEC_1                        (0x2UL << CAN_ESR_LEC_Pos)         /*!< 0x00000020 */\n#define CAN_ESR_LEC_2                        (0x4UL << CAN_ESR_LEC_Pos)         /*!< 0x00000040 */\n\n#define CAN_ESR_TEC_Pos                      (16U)                             \n#define CAN_ESR_TEC_Msk                      (0xFFUL << CAN_ESR_TEC_Pos)        /*!< 0x00FF0000 */\n#define CAN_ESR_TEC                          CAN_ESR_TEC_Msk                   /*!< Least significant byte of the 9-bit Transmit Error Counter */\n#define CAN_ESR_REC_Pos                      (24U)                             \n#define CAN_ESR_REC_Msk                      (0xFFUL << CAN_ESR_REC_Pos)        /*!< 0xFF000000 */\n#define CAN_ESR_REC                          CAN_ESR_REC_Msk                   /*!< Receive Error Counter */\n\n/*******************  Bit definition for CAN_BTR register  ********************/\n#define CAN_BTR_BRP_Pos                      (0U)                              \n#define CAN_BTR_BRP_Msk                      (0x3FFUL << CAN_BTR_BRP_Pos)       /*!< 0x000003FF */\n#define CAN_BTR_BRP                          CAN_BTR_BRP_Msk                   /*!<Baud Rate Prescaler */\n#define CAN_BTR_TS1_Pos                      (16U)                             \n#define CAN_BTR_TS1_Msk                      (0xFUL << CAN_BTR_TS1_Pos)         /*!< 0x000F0000 */\n#define CAN_BTR_TS1                          CAN_BTR_TS1_Msk                   /*!<Time Segment 1 */\n#define CAN_BTR_TS1_0                        (0x1UL << CAN_BTR_TS1_Pos)         /*!< 0x00010000 */\n#define CAN_BTR_TS1_1                        (0x2UL << CAN_BTR_TS1_Pos)         /*!< 0x00020000 */\n#define CAN_BTR_TS1_2                        (0x4UL << CAN_BTR_TS1_Pos)         /*!< 0x00040000 */\n#define CAN_BTR_TS1_3                        (0x8UL << CAN_BTR_TS1_Pos)         /*!< 0x00080000 */\n#define CAN_BTR_TS2_Pos                      (20U)                             \n#define CAN_BTR_TS2_Msk                      (0x7UL << CAN_BTR_TS2_Pos)         /*!< 0x00700000 */\n#define CAN_BTR_TS2                          CAN_BTR_TS2_Msk                   /*!<Time Segment 2 */\n#define CAN_BTR_TS2_0                        (0x1UL << CAN_BTR_TS2_Pos)         /*!< 0x00100000 */\n#define CAN_BTR_TS2_1                        (0x2UL << CAN_BTR_TS2_Pos)         /*!< 0x00200000 */\n#define CAN_BTR_TS2_2                        (0x4UL << CAN_BTR_TS2_Pos)         /*!< 0x00400000 */\n#define CAN_BTR_SJW_Pos                      (24U)                             \n#define CAN_BTR_SJW_Msk                      (0x3UL << CAN_BTR_SJW_Pos)         /*!< 0x03000000 */\n#define CAN_BTR_SJW                          CAN_BTR_SJW_Msk                   /*!<Resynchronization Jump Width */\n#define CAN_BTR_SJW_0                        (0x1UL << CAN_BTR_SJW_Pos)         /*!< 0x01000000 */\n#define CAN_BTR_SJW_1                        (0x2UL << CAN_BTR_SJW_Pos)         /*!< 0x02000000 */\n#define CAN_BTR_LBKM_Pos                     (30U)                             \n#define CAN_BTR_LBKM_Msk                     (0x1UL << CAN_BTR_LBKM_Pos)        /*!< 0x40000000 */\n#define CAN_BTR_LBKM                         CAN_BTR_LBKM_Msk                  /*!<Loop Back Mode (Debug) */\n#define CAN_BTR_SILM_Pos                     (31U)                             \n#define CAN_BTR_SILM_Msk                     (0x1UL << CAN_BTR_SILM_Pos)        /*!< 0x80000000 */\n#define CAN_BTR_SILM                         CAN_BTR_SILM_Msk                  /*!<Silent Mode */\n\n/*!< Mailbox registers */\n/******************  Bit definition for CAN_TI0R register  ********************/\n#define CAN_TI0R_TXRQ_Pos                    (0U)                              \n#define CAN_TI0R_TXRQ_Msk                    (0x1UL << CAN_TI0R_TXRQ_Pos)       /*!< 0x00000001 */\n#define CAN_TI0R_TXRQ                        CAN_TI0R_TXRQ_Msk                 /*!< Transmit Mailbox Request */\n#define CAN_TI0R_RTR_Pos                     (1U)                              \n#define CAN_TI0R_RTR_Msk                     (0x1UL << CAN_TI0R_RTR_Pos)        /*!< 0x00000002 */\n#define CAN_TI0R_RTR                         CAN_TI0R_RTR_Msk                  /*!< Remote Transmission Request */\n#define CAN_TI0R_IDE_Pos                     (2U)                              \n#define CAN_TI0R_IDE_Msk                     (0x1UL << CAN_TI0R_IDE_Pos)        /*!< 0x00000004 */\n#define CAN_TI0R_IDE                         CAN_TI0R_IDE_Msk                  /*!< Identifier Extension */\n#define CAN_TI0R_EXID_Pos                    (3U)                              \n#define CAN_TI0R_EXID_Msk                    (0x3FFFFUL << CAN_TI0R_EXID_Pos)   /*!< 0x001FFFF8 */\n#define CAN_TI0R_EXID                        CAN_TI0R_EXID_Msk                 /*!< Extended Identifier */\n#define CAN_TI0R_STID_Pos                    (21U)                             \n#define CAN_TI0R_STID_Msk                    (0x7FFUL << CAN_TI0R_STID_Pos)     /*!< 0xFFE00000 */\n#define CAN_TI0R_STID                        CAN_TI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */\n\n/******************  Bit definition for CAN_TDT0R register  *******************/\n#define CAN_TDT0R_DLC_Pos                    (0U)                              \n#define CAN_TDT0R_DLC_Msk                    (0xFUL << CAN_TDT0R_DLC_Pos)       /*!< 0x0000000F */\n#define CAN_TDT0R_DLC                        CAN_TDT0R_DLC_Msk                 /*!< Data Length Code */\n#define CAN_TDT0R_TGT_Pos                    (8U)                              \n#define CAN_TDT0R_TGT_Msk                    (0x1UL << CAN_TDT0R_TGT_Pos)       /*!< 0x00000100 */\n#define CAN_TDT0R_TGT                        CAN_TDT0R_TGT_Msk                 /*!< Transmit Global Time */\n#define CAN_TDT0R_TIME_Pos                   (16U)                             \n#define CAN_TDT0R_TIME_Msk                   (0xFFFFUL << CAN_TDT0R_TIME_Pos)   /*!< 0xFFFF0000 */\n#define CAN_TDT0R_TIME                       CAN_TDT0R_TIME_Msk                /*!< Message Time Stamp */\n\n/******************  Bit definition for CAN_TDL0R register  *******************/\n#define CAN_TDL0R_DATA0_Pos                  (0U)                              \n#define CAN_TDL0R_DATA0_Msk                  (0xFFUL << CAN_TDL0R_DATA0_Pos)    /*!< 0x000000FF */\n#define CAN_TDL0R_DATA0                      CAN_TDL0R_DATA0_Msk               /*!< Data byte 0 */\n#define CAN_TDL0R_DATA1_Pos                  (8U)                              \n#define CAN_TDL0R_DATA1_Msk                  (0xFFUL << CAN_TDL0R_DATA1_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDL0R_DATA1                      CAN_TDL0R_DATA1_Msk               /*!< Data byte 1 */\n#define CAN_TDL0R_DATA2_Pos                  (16U)                             \n#define CAN_TDL0R_DATA2_Msk                  (0xFFUL << CAN_TDL0R_DATA2_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDL0R_DATA2                      CAN_TDL0R_DATA2_Msk               /*!< Data byte 2 */\n#define CAN_TDL0R_DATA3_Pos                  (24U)                             \n#define CAN_TDL0R_DATA3_Msk                  (0xFFUL << CAN_TDL0R_DATA3_Pos)    /*!< 0xFF000000 */\n#define CAN_TDL0R_DATA3                      CAN_TDL0R_DATA3_Msk               /*!< Data byte 3 */\n\n/******************  Bit definition for CAN_TDH0R register  *******************/\n#define CAN_TDH0R_DATA4_Pos                  (0U)                              \n#define CAN_TDH0R_DATA4_Msk                  (0xFFUL << CAN_TDH0R_DATA4_Pos)    /*!< 0x000000FF */\n#define CAN_TDH0R_DATA4                      CAN_TDH0R_DATA4_Msk               /*!< Data byte 4 */\n#define CAN_TDH0R_DATA5_Pos                  (8U)                              \n#define CAN_TDH0R_DATA5_Msk                  (0xFFUL << CAN_TDH0R_DATA5_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDH0R_DATA5                      CAN_TDH0R_DATA5_Msk               /*!< Data byte 5 */\n#define CAN_TDH0R_DATA6_Pos                  (16U)                             \n#define CAN_TDH0R_DATA6_Msk                  (0xFFUL << CAN_TDH0R_DATA6_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDH0R_DATA6                      CAN_TDH0R_DATA6_Msk               /*!< Data byte 6 */\n#define CAN_TDH0R_DATA7_Pos                  (24U)                             \n#define CAN_TDH0R_DATA7_Msk                  (0xFFUL << CAN_TDH0R_DATA7_Pos)    /*!< 0xFF000000 */\n#define CAN_TDH0R_DATA7                      CAN_TDH0R_DATA7_Msk               /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_TI1R register  *******************/\n#define CAN_TI1R_TXRQ_Pos                    (0U)                              \n#define CAN_TI1R_TXRQ_Msk                    (0x1UL << CAN_TI1R_TXRQ_Pos)       /*!< 0x00000001 */\n#define CAN_TI1R_TXRQ                        CAN_TI1R_TXRQ_Msk                 /*!< Transmit Mailbox Request */\n#define CAN_TI1R_RTR_Pos                     (1U)                              \n#define CAN_TI1R_RTR_Msk                     (0x1UL << CAN_TI1R_RTR_Pos)        /*!< 0x00000002 */\n#define CAN_TI1R_RTR                         CAN_TI1R_RTR_Msk                  /*!< Remote Transmission Request */\n#define CAN_TI1R_IDE_Pos                     (2U)                              \n#define CAN_TI1R_IDE_Msk                     (0x1UL << CAN_TI1R_IDE_Pos)        /*!< 0x00000004 */\n#define CAN_TI1R_IDE                         CAN_TI1R_IDE_Msk                  /*!< Identifier Extension */\n#define CAN_TI1R_EXID_Pos                    (3U)                              \n#define CAN_TI1R_EXID_Msk                    (0x3FFFFUL << CAN_TI1R_EXID_Pos)   /*!< 0x001FFFF8 */\n#define CAN_TI1R_EXID                        CAN_TI1R_EXID_Msk                 /*!< Extended Identifier */\n#define CAN_TI1R_STID_Pos                    (21U)                             \n#define CAN_TI1R_STID_Msk                    (0x7FFUL << CAN_TI1R_STID_Pos)     /*!< 0xFFE00000 */\n#define CAN_TI1R_STID                        CAN_TI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT1R register  ******************/\n#define CAN_TDT1R_DLC_Pos                    (0U)                              \n#define CAN_TDT1R_DLC_Msk                    (0xFUL << CAN_TDT1R_DLC_Pos)       /*!< 0x0000000F */\n#define CAN_TDT1R_DLC                        CAN_TDT1R_DLC_Msk                 /*!< Data Length Code */\n#define CAN_TDT1R_TGT_Pos                    (8U)                              \n#define CAN_TDT1R_TGT_Msk                    (0x1UL << CAN_TDT1R_TGT_Pos)       /*!< 0x00000100 */\n#define CAN_TDT1R_TGT                        CAN_TDT1R_TGT_Msk                 /*!< Transmit Global Time */\n#define CAN_TDT1R_TIME_Pos                   (16U)                             \n#define CAN_TDT1R_TIME_Msk                   (0xFFFFUL << CAN_TDT1R_TIME_Pos)   /*!< 0xFFFF0000 */\n#define CAN_TDT1R_TIME                       CAN_TDT1R_TIME_Msk                /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL1R register  ******************/\n#define CAN_TDL1R_DATA0_Pos                  (0U)                              \n#define CAN_TDL1R_DATA0_Msk                  (0xFFUL << CAN_TDL1R_DATA0_Pos)    /*!< 0x000000FF */\n#define CAN_TDL1R_DATA0                      CAN_TDL1R_DATA0_Msk               /*!< Data byte 0 */\n#define CAN_TDL1R_DATA1_Pos                  (8U)                              \n#define CAN_TDL1R_DATA1_Msk                  (0xFFUL << CAN_TDL1R_DATA1_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDL1R_DATA1                      CAN_TDL1R_DATA1_Msk               /*!< Data byte 1 */\n#define CAN_TDL1R_DATA2_Pos                  (16U)                             \n#define CAN_TDL1R_DATA2_Msk                  (0xFFUL << CAN_TDL1R_DATA2_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDL1R_DATA2                      CAN_TDL1R_DATA2_Msk               /*!< Data byte 2 */\n#define CAN_TDL1R_DATA3_Pos                  (24U)                             \n#define CAN_TDL1R_DATA3_Msk                  (0xFFUL << CAN_TDL1R_DATA3_Pos)    /*!< 0xFF000000 */\n#define CAN_TDL1R_DATA3                      CAN_TDL1R_DATA3_Msk               /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH1R register  ******************/\n#define CAN_TDH1R_DATA4_Pos                  (0U)                              \n#define CAN_TDH1R_DATA4_Msk                  (0xFFUL << CAN_TDH1R_DATA4_Pos)    /*!< 0x000000FF */\n#define CAN_TDH1R_DATA4                      CAN_TDH1R_DATA4_Msk               /*!< Data byte 4 */\n#define CAN_TDH1R_DATA5_Pos                  (8U)                              \n#define CAN_TDH1R_DATA5_Msk                  (0xFFUL << CAN_TDH1R_DATA5_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDH1R_DATA5                      CAN_TDH1R_DATA5_Msk               /*!< Data byte 5 */\n#define CAN_TDH1R_DATA6_Pos                  (16U)                             \n#define CAN_TDH1R_DATA6_Msk                  (0xFFUL << CAN_TDH1R_DATA6_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDH1R_DATA6                      CAN_TDH1R_DATA6_Msk               /*!< Data byte 6 */\n#define CAN_TDH1R_DATA7_Pos                  (24U)                             \n#define CAN_TDH1R_DATA7_Msk                  (0xFFUL << CAN_TDH1R_DATA7_Pos)    /*!< 0xFF000000 */\n#define CAN_TDH1R_DATA7                      CAN_TDH1R_DATA7_Msk               /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_TI2R register  *******************/\n#define CAN_TI2R_TXRQ_Pos                    (0U)                              \n#define CAN_TI2R_TXRQ_Msk                    (0x1UL << CAN_TI2R_TXRQ_Pos)       /*!< 0x00000001 */\n#define CAN_TI2R_TXRQ                        CAN_TI2R_TXRQ_Msk                 /*!< Transmit Mailbox Request */\n#define CAN_TI2R_RTR_Pos                     (1U)                              \n#define CAN_TI2R_RTR_Msk                     (0x1UL << CAN_TI2R_RTR_Pos)        /*!< 0x00000002 */\n#define CAN_TI2R_RTR                         CAN_TI2R_RTR_Msk                  /*!< Remote Transmission Request */\n#define CAN_TI2R_IDE_Pos                     (2U)                              \n#define CAN_TI2R_IDE_Msk                     (0x1UL << CAN_TI2R_IDE_Pos)        /*!< 0x00000004 */\n#define CAN_TI2R_IDE                         CAN_TI2R_IDE_Msk                  /*!< Identifier Extension */\n#define CAN_TI2R_EXID_Pos                    (3U)                              \n#define CAN_TI2R_EXID_Msk                    (0x3FFFFUL << CAN_TI2R_EXID_Pos)   /*!< 0x001FFFF8 */\n#define CAN_TI2R_EXID                        CAN_TI2R_EXID_Msk                 /*!< Extended identifier */\n#define CAN_TI2R_STID_Pos                    (21U)                             \n#define CAN_TI2R_STID_Msk                    (0x7FFUL << CAN_TI2R_STID_Pos)     /*!< 0xFFE00000 */\n#define CAN_TI2R_STID                        CAN_TI2R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_TDT2R register  ******************/  \n#define CAN_TDT2R_DLC_Pos                    (0U)                              \n#define CAN_TDT2R_DLC_Msk                    (0xFUL << CAN_TDT2R_DLC_Pos)       /*!< 0x0000000F */\n#define CAN_TDT2R_DLC                        CAN_TDT2R_DLC_Msk                 /*!< Data Length Code */\n#define CAN_TDT2R_TGT_Pos                    (8U)                              \n#define CAN_TDT2R_TGT_Msk                    (0x1UL << CAN_TDT2R_TGT_Pos)       /*!< 0x00000100 */\n#define CAN_TDT2R_TGT                        CAN_TDT2R_TGT_Msk                 /*!< Transmit Global Time */\n#define CAN_TDT2R_TIME_Pos                   (16U)                             \n#define CAN_TDT2R_TIME_Msk                   (0xFFFFUL << CAN_TDT2R_TIME_Pos)   /*!< 0xFFFF0000 */\n#define CAN_TDT2R_TIME                       CAN_TDT2R_TIME_Msk                /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_TDL2R register  ******************/\n#define CAN_TDL2R_DATA0_Pos                  (0U)                              \n#define CAN_TDL2R_DATA0_Msk                  (0xFFUL << CAN_TDL2R_DATA0_Pos)    /*!< 0x000000FF */\n#define CAN_TDL2R_DATA0                      CAN_TDL2R_DATA0_Msk               /*!< Data byte 0 */\n#define CAN_TDL2R_DATA1_Pos                  (8U)                              \n#define CAN_TDL2R_DATA1_Msk                  (0xFFUL << CAN_TDL2R_DATA1_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDL2R_DATA1                      CAN_TDL2R_DATA1_Msk               /*!< Data byte 1 */\n#define CAN_TDL2R_DATA2_Pos                  (16U)                             \n#define CAN_TDL2R_DATA2_Msk                  (0xFFUL << CAN_TDL2R_DATA2_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDL2R_DATA2                      CAN_TDL2R_DATA2_Msk               /*!< Data byte 2 */\n#define CAN_TDL2R_DATA3_Pos                  (24U)                             \n#define CAN_TDL2R_DATA3_Msk                  (0xFFUL << CAN_TDL2R_DATA3_Pos)    /*!< 0xFF000000 */\n#define CAN_TDL2R_DATA3                      CAN_TDL2R_DATA3_Msk               /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_TDH2R register  ******************/\n#define CAN_TDH2R_DATA4_Pos                  (0U)                              \n#define CAN_TDH2R_DATA4_Msk                  (0xFFUL << CAN_TDH2R_DATA4_Pos)    /*!< 0x000000FF */\n#define CAN_TDH2R_DATA4                      CAN_TDH2R_DATA4_Msk               /*!< Data byte 4 */\n#define CAN_TDH2R_DATA5_Pos                  (8U)                              \n#define CAN_TDH2R_DATA5_Msk                  (0xFFUL << CAN_TDH2R_DATA5_Pos)    /*!< 0x0000FF00 */\n#define CAN_TDH2R_DATA5                      CAN_TDH2R_DATA5_Msk               /*!< Data byte 5 */\n#define CAN_TDH2R_DATA6_Pos                  (16U)                             \n#define CAN_TDH2R_DATA6_Msk                  (0xFFUL << CAN_TDH2R_DATA6_Pos)    /*!< 0x00FF0000 */\n#define CAN_TDH2R_DATA6                      CAN_TDH2R_DATA6_Msk               /*!< Data byte 6 */\n#define CAN_TDH2R_DATA7_Pos                  (24U)                             \n#define CAN_TDH2R_DATA7_Msk                  (0xFFUL << CAN_TDH2R_DATA7_Pos)    /*!< 0xFF000000 */\n#define CAN_TDH2R_DATA7                      CAN_TDH2R_DATA7_Msk               /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_RI0R register  *******************/\n#define CAN_RI0R_RTR_Pos                     (1U)                              \n#define CAN_RI0R_RTR_Msk                     (0x1UL << CAN_RI0R_RTR_Pos)        /*!< 0x00000002 */\n#define CAN_RI0R_RTR                         CAN_RI0R_RTR_Msk                  /*!< Remote Transmission Request */\n#define CAN_RI0R_IDE_Pos                     (2U)                              \n#define CAN_RI0R_IDE_Msk                     (0x1UL << CAN_RI0R_IDE_Pos)        /*!< 0x00000004 */\n#define CAN_RI0R_IDE                         CAN_RI0R_IDE_Msk                  /*!< Identifier Extension */\n#define CAN_RI0R_EXID_Pos                    (3U)                              \n#define CAN_RI0R_EXID_Msk                    (0x3FFFFUL << CAN_RI0R_EXID_Pos)   /*!< 0x001FFFF8 */\n#define CAN_RI0R_EXID                        CAN_RI0R_EXID_Msk                 /*!< Extended Identifier */\n#define CAN_RI0R_STID_Pos                    (21U)                             \n#define CAN_RI0R_STID_Msk                    (0x7FFUL << CAN_RI0R_STID_Pos)     /*!< 0xFFE00000 */\n#define CAN_RI0R_STID                        CAN_RI0R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT0R register  ******************/\n#define CAN_RDT0R_DLC_Pos                    (0U)                              \n#define CAN_RDT0R_DLC_Msk                    (0xFUL << CAN_RDT0R_DLC_Pos)       /*!< 0x0000000F */\n#define CAN_RDT0R_DLC                        CAN_RDT0R_DLC_Msk                 /*!< Data Length Code */\n#define CAN_RDT0R_FMI_Pos                    (8U)                              \n#define CAN_RDT0R_FMI_Msk                    (0xFFUL << CAN_RDT0R_FMI_Pos)      /*!< 0x0000FF00 */\n#define CAN_RDT0R_FMI                        CAN_RDT0R_FMI_Msk                 /*!< Filter Match Index */\n#define CAN_RDT0R_TIME_Pos                   (16U)                             \n#define CAN_RDT0R_TIME_Msk                   (0xFFFFUL << CAN_RDT0R_TIME_Pos)   /*!< 0xFFFF0000 */\n#define CAN_RDT0R_TIME                       CAN_RDT0R_TIME_Msk                /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL0R register  ******************/\n#define CAN_RDL0R_DATA0_Pos                  (0U)                              \n#define CAN_RDL0R_DATA0_Msk                  (0xFFUL << CAN_RDL0R_DATA0_Pos)    /*!< 0x000000FF */\n#define CAN_RDL0R_DATA0                      CAN_RDL0R_DATA0_Msk               /*!< Data byte 0 */\n#define CAN_RDL0R_DATA1_Pos                  (8U)                              \n#define CAN_RDL0R_DATA1_Msk                  (0xFFUL << CAN_RDL0R_DATA1_Pos)    /*!< 0x0000FF00 */\n#define CAN_RDL0R_DATA1                      CAN_RDL0R_DATA1_Msk               /*!< Data byte 1 */\n#define CAN_RDL0R_DATA2_Pos                  (16U)                             \n#define CAN_RDL0R_DATA2_Msk                  (0xFFUL << CAN_RDL0R_DATA2_Pos)    /*!< 0x00FF0000 */\n#define CAN_RDL0R_DATA2                      CAN_RDL0R_DATA2_Msk               /*!< Data byte 2 */\n#define CAN_RDL0R_DATA3_Pos                  (24U)                             \n#define CAN_RDL0R_DATA3_Msk                  (0xFFUL << CAN_RDL0R_DATA3_Pos)    /*!< 0xFF000000 */\n#define CAN_RDL0R_DATA3                      CAN_RDL0R_DATA3_Msk               /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH0R register  ******************/\n#define CAN_RDH0R_DATA4_Pos                  (0U)                              \n#define CAN_RDH0R_DATA4_Msk                  (0xFFUL << CAN_RDH0R_DATA4_Pos)    /*!< 0x000000FF */\n#define CAN_RDH0R_DATA4                      CAN_RDH0R_DATA4_Msk               /*!< Data byte 4 */\n#define CAN_RDH0R_DATA5_Pos                  (8U)                              \n#define CAN_RDH0R_DATA5_Msk                  (0xFFUL << CAN_RDH0R_DATA5_Pos)    /*!< 0x0000FF00 */\n#define CAN_RDH0R_DATA5                      CAN_RDH0R_DATA5_Msk               /*!< Data byte 5 */\n#define CAN_RDH0R_DATA6_Pos                  (16U)                             \n#define CAN_RDH0R_DATA6_Msk                  (0xFFUL << CAN_RDH0R_DATA6_Pos)    /*!< 0x00FF0000 */\n#define CAN_RDH0R_DATA6                      CAN_RDH0R_DATA6_Msk               /*!< Data byte 6 */\n#define CAN_RDH0R_DATA7_Pos                  (24U)                             \n#define CAN_RDH0R_DATA7_Msk                  (0xFFUL << CAN_RDH0R_DATA7_Pos)    /*!< 0xFF000000 */\n#define CAN_RDH0R_DATA7                      CAN_RDH0R_DATA7_Msk               /*!< Data byte 7 */\n\n/*******************  Bit definition for CAN_RI1R register  *******************/\n#define CAN_RI1R_RTR_Pos                     (1U)                              \n#define CAN_RI1R_RTR_Msk                     (0x1UL << CAN_RI1R_RTR_Pos)        /*!< 0x00000002 */\n#define CAN_RI1R_RTR                         CAN_RI1R_RTR_Msk                  /*!< Remote Transmission Request */\n#define CAN_RI1R_IDE_Pos                     (2U)                              \n#define CAN_RI1R_IDE_Msk                     (0x1UL << CAN_RI1R_IDE_Pos)        /*!< 0x00000004 */\n#define CAN_RI1R_IDE                         CAN_RI1R_IDE_Msk                  /*!< Identifier Extension */\n#define CAN_RI1R_EXID_Pos                    (3U)                              \n#define CAN_RI1R_EXID_Msk                    (0x3FFFFUL << CAN_RI1R_EXID_Pos)   /*!< 0x001FFFF8 */\n#define CAN_RI1R_EXID                        CAN_RI1R_EXID_Msk                 /*!< Extended identifier */\n#define CAN_RI1R_STID_Pos                    (21U)                             \n#define CAN_RI1R_STID_Msk                    (0x7FFUL << CAN_RI1R_STID_Pos)     /*!< 0xFFE00000 */\n#define CAN_RI1R_STID                        CAN_RI1R_STID_Msk                 /*!< Standard Identifier or Extended Identifier */\n\n/*******************  Bit definition for CAN_RDT1R register  ******************/\n#define CAN_RDT1R_DLC_Pos                    (0U)                              \n#define CAN_RDT1R_DLC_Msk                    (0xFUL << CAN_RDT1R_DLC_Pos)       /*!< 0x0000000F */\n#define CAN_RDT1R_DLC                        CAN_RDT1R_DLC_Msk                 /*!< Data Length Code */\n#define CAN_RDT1R_FMI_Pos                    (8U)                              \n#define CAN_RDT1R_FMI_Msk                    (0xFFUL << CAN_RDT1R_FMI_Pos)      /*!< 0x0000FF00 */\n#define CAN_RDT1R_FMI                        CAN_RDT1R_FMI_Msk                 /*!< Filter Match Index */\n#define CAN_RDT1R_TIME_Pos                   (16U)                             \n#define CAN_RDT1R_TIME_Msk                   (0xFFFFUL << CAN_RDT1R_TIME_Pos)   /*!< 0xFFFF0000 */\n#define CAN_RDT1R_TIME                       CAN_RDT1R_TIME_Msk                /*!< Message Time Stamp */\n\n/*******************  Bit definition for CAN_RDL1R register  ******************/\n#define CAN_RDL1R_DATA0_Pos                  (0U)                              \n#define CAN_RDL1R_DATA0_Msk                  (0xFFUL << CAN_RDL1R_DATA0_Pos)    /*!< 0x000000FF */\n#define CAN_RDL1R_DATA0                      CAN_RDL1R_DATA0_Msk               /*!< Data byte 0 */\n#define CAN_RDL1R_DATA1_Pos                  (8U)                              \n#define CAN_RDL1R_DATA1_Msk                  (0xFFUL << CAN_RDL1R_DATA1_Pos)    /*!< 0x0000FF00 */\n#define CAN_RDL1R_DATA1                      CAN_RDL1R_DATA1_Msk               /*!< Data byte 1 */\n#define CAN_RDL1R_DATA2_Pos                  (16U)                             \n#define CAN_RDL1R_DATA2_Msk                  (0xFFUL << CAN_RDL1R_DATA2_Pos)    /*!< 0x00FF0000 */\n#define CAN_RDL1R_DATA2                      CAN_RDL1R_DATA2_Msk               /*!< Data byte 2 */\n#define CAN_RDL1R_DATA3_Pos                  (24U)                             \n#define CAN_RDL1R_DATA3_Msk                  (0xFFUL << CAN_RDL1R_DATA3_Pos)    /*!< 0xFF000000 */\n#define CAN_RDL1R_DATA3                      CAN_RDL1R_DATA3_Msk               /*!< Data byte 3 */\n\n/*******************  Bit definition for CAN_RDH1R register  ******************/\n#define CAN_RDH1R_DATA4_Pos                  (0U)                              \n#define CAN_RDH1R_DATA4_Msk                  (0xFFUL << CAN_RDH1R_DATA4_Pos)    /*!< 0x000000FF */\n#define CAN_RDH1R_DATA4                      CAN_RDH1R_DATA4_Msk               /*!< Data byte 4 */\n#define CAN_RDH1R_DATA5_Pos                  (8U)                              \n#define CAN_RDH1R_DATA5_Msk                  (0xFFUL << CAN_RDH1R_DATA5_Pos)    /*!< 0x0000FF00 */\n#define CAN_RDH1R_DATA5                      CAN_RDH1R_DATA5_Msk               /*!< Data byte 5 */\n#define CAN_RDH1R_DATA6_Pos                  (16U)                             \n#define CAN_RDH1R_DATA6_Msk                  (0xFFUL << CAN_RDH1R_DATA6_Pos)    /*!< 0x00FF0000 */\n#define CAN_RDH1R_DATA6                      CAN_RDH1R_DATA6_Msk               /*!< Data byte 6 */\n#define CAN_RDH1R_DATA7_Pos                  (24U)                             \n#define CAN_RDH1R_DATA7_Msk                  (0xFFUL << CAN_RDH1R_DATA7_Pos)    /*!< 0xFF000000 */\n#define CAN_RDH1R_DATA7                      CAN_RDH1R_DATA7_Msk               /*!< Data byte 7 */\n\n/*!< CAN filter registers */\n/*******************  Bit definition for CAN_FMR register  ********************/\n#define CAN_FMR_FINIT_Pos                    (0U)                              \n#define CAN_FMR_FINIT_Msk                    (0x1UL << CAN_FMR_FINIT_Pos)       /*!< 0x00000001 */\n#define CAN_FMR_FINIT                        CAN_FMR_FINIT_Msk                 /*!< Filter Init Mode */\n#define CAN_FMR_CAN2SB_Pos                   (8U)                              \n#define CAN_FMR_CAN2SB_Msk                   (0x3FUL << CAN_FMR_CAN2SB_Pos)     /*!< 0x00003F00 */\n#define CAN_FMR_CAN2SB                       CAN_FMR_CAN2SB_Msk                /*!< CAN2 start bank */\n\n/*******************  Bit definition for CAN_FM1R register  *******************/\n#define CAN_FM1R_FBM_Pos                     (0U)                              \n#define CAN_FM1R_FBM_Msk                     (0x3FFFUL << CAN_FM1R_FBM_Pos)     /*!< 0x00003FFF */\n#define CAN_FM1R_FBM                         CAN_FM1R_FBM_Msk                  /*!< Filter Mode */\n#define CAN_FM1R_FBM0_Pos                    (0U)                              \n#define CAN_FM1R_FBM0_Msk                    (0x1UL << CAN_FM1R_FBM0_Pos)       /*!< 0x00000001 */\n#define CAN_FM1R_FBM0                        CAN_FM1R_FBM0_Msk                 /*!< Filter Init Mode for filter 0 */\n#define CAN_FM1R_FBM1_Pos                    (1U)                              \n#define CAN_FM1R_FBM1_Msk                    (0x1UL << CAN_FM1R_FBM1_Pos)       /*!< 0x00000002 */\n#define CAN_FM1R_FBM1                        CAN_FM1R_FBM1_Msk                 /*!< Filter Init Mode for filter 1 */\n#define CAN_FM1R_FBM2_Pos                    (2U)                              \n#define CAN_FM1R_FBM2_Msk                    (0x1UL << CAN_FM1R_FBM2_Pos)       /*!< 0x00000004 */\n#define CAN_FM1R_FBM2                        CAN_FM1R_FBM2_Msk                 /*!< Filter Init Mode for filter 2 */\n#define CAN_FM1R_FBM3_Pos                    (3U)                              \n#define CAN_FM1R_FBM3_Msk                    (0x1UL << CAN_FM1R_FBM3_Pos)       /*!< 0x00000008 */\n#define CAN_FM1R_FBM3                        CAN_FM1R_FBM3_Msk                 /*!< Filter Init Mode for filter 3 */\n#define CAN_FM1R_FBM4_Pos                    (4U)                              \n#define CAN_FM1R_FBM4_Msk                    (0x1UL << CAN_FM1R_FBM4_Pos)       /*!< 0x00000010 */\n#define CAN_FM1R_FBM4                        CAN_FM1R_FBM4_Msk                 /*!< Filter Init Mode for filter 4 */\n#define CAN_FM1R_FBM5_Pos                    (5U)                              \n#define CAN_FM1R_FBM5_Msk                    (0x1UL << CAN_FM1R_FBM5_Pos)       /*!< 0x00000020 */\n#define CAN_FM1R_FBM5                        CAN_FM1R_FBM5_Msk                 /*!< Filter Init Mode for filter 5 */\n#define CAN_FM1R_FBM6_Pos                    (6U)                              \n#define CAN_FM1R_FBM6_Msk                    (0x1UL << CAN_FM1R_FBM6_Pos)       /*!< 0x00000040 */\n#define CAN_FM1R_FBM6                        CAN_FM1R_FBM6_Msk                 /*!< Filter Init Mode for filter 6 */\n#define CAN_FM1R_FBM7_Pos                    (7U)                              \n#define CAN_FM1R_FBM7_Msk                    (0x1UL << CAN_FM1R_FBM7_Pos)       /*!< 0x00000080 */\n#define CAN_FM1R_FBM7                        CAN_FM1R_FBM7_Msk                 /*!< Filter Init Mode for filter 7 */\n#define CAN_FM1R_FBM8_Pos                    (8U)                              \n#define CAN_FM1R_FBM8_Msk                    (0x1UL << CAN_FM1R_FBM8_Pos)       /*!< 0x00000100 */\n#define CAN_FM1R_FBM8                        CAN_FM1R_FBM8_Msk                 /*!< Filter Init Mode for filter 8 */\n#define CAN_FM1R_FBM9_Pos                    (9U)                              \n#define CAN_FM1R_FBM9_Msk                    (0x1UL << CAN_FM1R_FBM9_Pos)       /*!< 0x00000200 */\n#define CAN_FM1R_FBM9                        CAN_FM1R_FBM9_Msk                 /*!< Filter Init Mode for filter 9 */\n#define CAN_FM1R_FBM10_Pos                   (10U)                             \n#define CAN_FM1R_FBM10_Msk                   (0x1UL << CAN_FM1R_FBM10_Pos)      /*!< 0x00000400 */\n#define CAN_FM1R_FBM10                       CAN_FM1R_FBM10_Msk                /*!< Filter Init Mode for filter 10 */\n#define CAN_FM1R_FBM11_Pos                   (11U)                             \n#define CAN_FM1R_FBM11_Msk                   (0x1UL << CAN_FM1R_FBM11_Pos)      /*!< 0x00000800 */\n#define CAN_FM1R_FBM11                       CAN_FM1R_FBM11_Msk                /*!< Filter Init Mode for filter 11 */\n#define CAN_FM1R_FBM12_Pos                   (12U)                             \n#define CAN_FM1R_FBM12_Msk                   (0x1UL << CAN_FM1R_FBM12_Pos)      /*!< 0x00001000 */\n#define CAN_FM1R_FBM12                       CAN_FM1R_FBM12_Msk                /*!< Filter Init Mode for filter 12 */\n#define CAN_FM1R_FBM13_Pos                   (13U)                             \n#define CAN_FM1R_FBM13_Msk                   (0x1UL << CAN_FM1R_FBM13_Pos)      /*!< 0x00002000 */\n#define CAN_FM1R_FBM13                       CAN_FM1R_FBM13_Msk                /*!< Filter Init Mode for filter 13 */\n\n/*******************  Bit definition for CAN_FS1R register  *******************/\n#define CAN_FS1R_FSC_Pos                     (0U)                              \n#define CAN_FS1R_FSC_Msk                     (0x3FFFUL << CAN_FS1R_FSC_Pos)     /*!< 0x00003FFF */\n#define CAN_FS1R_FSC                         CAN_FS1R_FSC_Msk                  /*!< Filter Scale Configuration */\n#define CAN_FS1R_FSC0_Pos                    (0U)                              \n#define CAN_FS1R_FSC0_Msk                    (0x1UL << CAN_FS1R_FSC0_Pos)       /*!< 0x00000001 */\n#define CAN_FS1R_FSC0                        CAN_FS1R_FSC0_Msk                 /*!< Filter Scale Configuration for filter 0 */\n#define CAN_FS1R_FSC1_Pos                    (1U)                              \n#define CAN_FS1R_FSC1_Msk                    (0x1UL << CAN_FS1R_FSC1_Pos)       /*!< 0x00000002 */\n#define CAN_FS1R_FSC1                        CAN_FS1R_FSC1_Msk                 /*!< Filter Scale Configuration for filter 1 */\n#define CAN_FS1R_FSC2_Pos                    (2U)                              \n#define CAN_FS1R_FSC2_Msk                    (0x1UL << CAN_FS1R_FSC2_Pos)       /*!< 0x00000004 */\n#define CAN_FS1R_FSC2                        CAN_FS1R_FSC2_Msk                 /*!< Filter Scale Configuration for filter 2 */\n#define CAN_FS1R_FSC3_Pos                    (3U)                              \n#define CAN_FS1R_FSC3_Msk                    (0x1UL << CAN_FS1R_FSC3_Pos)       /*!< 0x00000008 */\n#define CAN_FS1R_FSC3                        CAN_FS1R_FSC3_Msk                 /*!< Filter Scale Configuration for filter 3 */\n#define CAN_FS1R_FSC4_Pos                    (4U)                              \n#define CAN_FS1R_FSC4_Msk                    (0x1UL << CAN_FS1R_FSC4_Pos)       /*!< 0x00000010 */\n#define CAN_FS1R_FSC4                        CAN_FS1R_FSC4_Msk                 /*!< Filter Scale Configuration for filter 4 */\n#define CAN_FS1R_FSC5_Pos                    (5U)                              \n#define CAN_FS1R_FSC5_Msk                    (0x1UL << CAN_FS1R_FSC5_Pos)       /*!< 0x00000020 */\n#define CAN_FS1R_FSC5                        CAN_FS1R_FSC5_Msk                 /*!< Filter Scale Configuration for filter 5 */\n#define CAN_FS1R_FSC6_Pos                    (6U)                              \n#define CAN_FS1R_FSC6_Msk                    (0x1UL << CAN_FS1R_FSC6_Pos)       /*!< 0x00000040 */\n#define CAN_FS1R_FSC6                        CAN_FS1R_FSC6_Msk                 /*!< Filter Scale Configuration for filter 6 */\n#define CAN_FS1R_FSC7_Pos                    (7U)                              \n#define CAN_FS1R_FSC7_Msk                    (0x1UL << CAN_FS1R_FSC7_Pos)       /*!< 0x00000080 */\n#define CAN_FS1R_FSC7                        CAN_FS1R_FSC7_Msk                 /*!< Filter Scale Configuration for filter 7 */\n#define CAN_FS1R_FSC8_Pos                    (8U)                              \n#define CAN_FS1R_FSC8_Msk                    (0x1UL << CAN_FS1R_FSC8_Pos)       /*!< 0x00000100 */\n#define CAN_FS1R_FSC8                        CAN_FS1R_FSC8_Msk                 /*!< Filter Scale Configuration for filter 8 */\n#define CAN_FS1R_FSC9_Pos                    (9U)                              \n#define CAN_FS1R_FSC9_Msk                    (0x1UL << CAN_FS1R_FSC9_Pos)       /*!< 0x00000200 */\n#define CAN_FS1R_FSC9                        CAN_FS1R_FSC9_Msk                 /*!< Filter Scale Configuration for filter 9 */\n#define CAN_FS1R_FSC10_Pos                   (10U)                             \n#define CAN_FS1R_FSC10_Msk                   (0x1UL << CAN_FS1R_FSC10_Pos)      /*!< 0x00000400 */\n#define CAN_FS1R_FSC10                       CAN_FS1R_FSC10_Msk                /*!< Filter Scale Configuration for filter 10 */\n#define CAN_FS1R_FSC11_Pos                   (11U)                             \n#define CAN_FS1R_FSC11_Msk                   (0x1UL << CAN_FS1R_FSC11_Pos)      /*!< 0x00000800 */\n#define CAN_FS1R_FSC11                       CAN_FS1R_FSC11_Msk                /*!< Filter Scale Configuration for filter 11 */\n#define CAN_FS1R_FSC12_Pos                   (12U)                             \n#define CAN_FS1R_FSC12_Msk                   (0x1UL << CAN_FS1R_FSC12_Pos)      /*!< 0x00001000 */\n#define CAN_FS1R_FSC12                       CAN_FS1R_FSC12_Msk                /*!< Filter Scale Configuration for filter 12 */\n#define CAN_FS1R_FSC13_Pos                   (13U)                             \n#define CAN_FS1R_FSC13_Msk                   (0x1UL << CAN_FS1R_FSC13_Pos)      /*!< 0x00002000 */\n#define CAN_FS1R_FSC13                       CAN_FS1R_FSC13_Msk                /*!< Filter Scale Configuration for filter 13 */\n\n/******************  Bit definition for CAN_FFA1R register  *******************/\n#define CAN_FFA1R_FFA_Pos                    (0U)                              \n#define CAN_FFA1R_FFA_Msk                    (0x3FFFUL << CAN_FFA1R_FFA_Pos)    /*!< 0x00003FFF */\n#define CAN_FFA1R_FFA                        CAN_FFA1R_FFA_Msk                 /*!< Filter FIFO Assignment */\n#define CAN_FFA1R_FFA0_Pos                   (0U)                              \n#define CAN_FFA1R_FFA0_Msk                   (0x1UL << CAN_FFA1R_FFA0_Pos)      /*!< 0x00000001 */\n#define CAN_FFA1R_FFA0                       CAN_FFA1R_FFA0_Msk                /*!< Filter FIFO Assignment for filter 0 */\n#define CAN_FFA1R_FFA1_Pos                   (1U)                              \n#define CAN_FFA1R_FFA1_Msk                   (0x1UL << CAN_FFA1R_FFA1_Pos)      /*!< 0x00000002 */\n#define CAN_FFA1R_FFA1                       CAN_FFA1R_FFA1_Msk                /*!< Filter FIFO Assignment for filter 1 */\n#define CAN_FFA1R_FFA2_Pos                   (2U)                              \n#define CAN_FFA1R_FFA2_Msk                   (0x1UL << CAN_FFA1R_FFA2_Pos)      /*!< 0x00000004 */\n#define CAN_FFA1R_FFA2                       CAN_FFA1R_FFA2_Msk                /*!< Filter FIFO Assignment for filter 2 */\n#define CAN_FFA1R_FFA3_Pos                   (3U)                              \n#define CAN_FFA1R_FFA3_Msk                   (0x1UL << CAN_FFA1R_FFA3_Pos)      /*!< 0x00000008 */\n#define CAN_FFA1R_FFA3                       CAN_FFA1R_FFA3_Msk                /*!< Filter FIFO Assignment for filter 3 */\n#define CAN_FFA1R_FFA4_Pos                   (4U)                              \n#define CAN_FFA1R_FFA4_Msk                   (0x1UL << CAN_FFA1R_FFA4_Pos)      /*!< 0x00000010 */\n#define CAN_FFA1R_FFA4                       CAN_FFA1R_FFA4_Msk                /*!< Filter FIFO Assignment for filter 4 */\n#define CAN_FFA1R_FFA5_Pos                   (5U)                              \n#define CAN_FFA1R_FFA5_Msk                   (0x1UL << CAN_FFA1R_FFA5_Pos)      /*!< 0x00000020 */\n#define CAN_FFA1R_FFA5                       CAN_FFA1R_FFA5_Msk                /*!< Filter FIFO Assignment for filter 5 */\n#define CAN_FFA1R_FFA6_Pos                   (6U)                              \n#define CAN_FFA1R_FFA6_Msk                   (0x1UL << CAN_FFA1R_FFA6_Pos)      /*!< 0x00000040 */\n#define CAN_FFA1R_FFA6                       CAN_FFA1R_FFA6_Msk                /*!< Filter FIFO Assignment for filter 6 */\n#define CAN_FFA1R_FFA7_Pos                   (7U)                              \n#define CAN_FFA1R_FFA7_Msk                   (0x1UL << CAN_FFA1R_FFA7_Pos)      /*!< 0x00000080 */\n#define CAN_FFA1R_FFA7                       CAN_FFA1R_FFA7_Msk                /*!< Filter FIFO Assignment for filter 7 */\n#define CAN_FFA1R_FFA8_Pos                   (8U)                              \n#define CAN_FFA1R_FFA8_Msk                   (0x1UL << CAN_FFA1R_FFA8_Pos)      /*!< 0x00000100 */\n#define CAN_FFA1R_FFA8                       CAN_FFA1R_FFA8_Msk                /*!< Filter FIFO Assignment for filter 8 */\n#define CAN_FFA1R_FFA9_Pos                   (9U)                              \n#define CAN_FFA1R_FFA9_Msk                   (0x1UL << CAN_FFA1R_FFA9_Pos)      /*!< 0x00000200 */\n#define CAN_FFA1R_FFA9                       CAN_FFA1R_FFA9_Msk                /*!< Filter FIFO Assignment for filter 9 */\n#define CAN_FFA1R_FFA10_Pos                  (10U)                             \n#define CAN_FFA1R_FFA10_Msk                  (0x1UL << CAN_FFA1R_FFA10_Pos)     /*!< 0x00000400 */\n#define CAN_FFA1R_FFA10                      CAN_FFA1R_FFA10_Msk               /*!< Filter FIFO Assignment for filter 10 */\n#define CAN_FFA1R_FFA11_Pos                  (11U)                             \n#define CAN_FFA1R_FFA11_Msk                  (0x1UL << CAN_FFA1R_FFA11_Pos)     /*!< 0x00000800 */\n#define CAN_FFA1R_FFA11                      CAN_FFA1R_FFA11_Msk               /*!< Filter FIFO Assignment for filter 11 */\n#define CAN_FFA1R_FFA12_Pos                  (12U)                             \n#define CAN_FFA1R_FFA12_Msk                  (0x1UL << CAN_FFA1R_FFA12_Pos)     /*!< 0x00001000 */\n#define CAN_FFA1R_FFA12                      CAN_FFA1R_FFA12_Msk               /*!< Filter FIFO Assignment for filter 12 */\n#define CAN_FFA1R_FFA13_Pos                  (13U)                             \n#define CAN_FFA1R_FFA13_Msk                  (0x1UL << CAN_FFA1R_FFA13_Pos)     /*!< 0x00002000 */\n#define CAN_FFA1R_FFA13                      CAN_FFA1R_FFA13_Msk               /*!< Filter FIFO Assignment for filter 13 */\n\n/*******************  Bit definition for CAN_FA1R register  *******************/\n#define CAN_FA1R_FACT_Pos                    (0U)                              \n#define CAN_FA1R_FACT_Msk                    (0x3FFFUL << CAN_FA1R_FACT_Pos)    /*!< 0x00003FFF */\n#define CAN_FA1R_FACT                        CAN_FA1R_FACT_Msk                 /*!< Filter Active */\n#define CAN_FA1R_FACT0_Pos                   (0U)                              \n#define CAN_FA1R_FACT0_Msk                   (0x1UL << CAN_FA1R_FACT0_Pos)      /*!< 0x00000001 */\n#define CAN_FA1R_FACT0                       CAN_FA1R_FACT0_Msk                /*!< Filter 0 Active */\n#define CAN_FA1R_FACT1_Pos                   (1U)                              \n#define CAN_FA1R_FACT1_Msk                   (0x1UL << CAN_FA1R_FACT1_Pos)      /*!< 0x00000002 */\n#define CAN_FA1R_FACT1                       CAN_FA1R_FACT1_Msk                /*!< Filter 1 Active */\n#define CAN_FA1R_FACT2_Pos                   (2U)                              \n#define CAN_FA1R_FACT2_Msk                   (0x1UL << CAN_FA1R_FACT2_Pos)      /*!< 0x00000004 */\n#define CAN_FA1R_FACT2                       CAN_FA1R_FACT2_Msk                /*!< Filter 2 Active */\n#define CAN_FA1R_FACT3_Pos                   (3U)                              \n#define CAN_FA1R_FACT3_Msk                   (0x1UL << CAN_FA1R_FACT3_Pos)      /*!< 0x00000008 */\n#define CAN_FA1R_FACT3                       CAN_FA1R_FACT3_Msk                /*!< Filter 3 Active */\n#define CAN_FA1R_FACT4_Pos                   (4U)                              \n#define CAN_FA1R_FACT4_Msk                   (0x1UL << CAN_FA1R_FACT4_Pos)      /*!< 0x00000010 */\n#define CAN_FA1R_FACT4                       CAN_FA1R_FACT4_Msk                /*!< Filter 4 Active */\n#define CAN_FA1R_FACT5_Pos                   (5U)                              \n#define CAN_FA1R_FACT5_Msk                   (0x1UL << CAN_FA1R_FACT5_Pos)      /*!< 0x00000020 */\n#define CAN_FA1R_FACT5                       CAN_FA1R_FACT5_Msk                /*!< Filter 5 Active */\n#define CAN_FA1R_FACT6_Pos                   (6U)                              \n#define CAN_FA1R_FACT6_Msk                   (0x1UL << CAN_FA1R_FACT6_Pos)      /*!< 0x00000040 */\n#define CAN_FA1R_FACT6                       CAN_FA1R_FACT6_Msk                /*!< Filter 6 Active */\n#define CAN_FA1R_FACT7_Pos                   (7U)                              \n#define CAN_FA1R_FACT7_Msk                   (0x1UL << CAN_FA1R_FACT7_Pos)      /*!< 0x00000080 */\n#define CAN_FA1R_FACT7                       CAN_FA1R_FACT7_Msk                /*!< Filter 7 Active */\n#define CAN_FA1R_FACT8_Pos                   (8U)                              \n#define CAN_FA1R_FACT8_Msk                   (0x1UL << CAN_FA1R_FACT8_Pos)      /*!< 0x00000100 */\n#define CAN_FA1R_FACT8                       CAN_FA1R_FACT8_Msk                /*!< Filter 8 Active */\n#define CAN_FA1R_FACT9_Pos                   (9U)                              \n#define CAN_FA1R_FACT9_Msk                   (0x1UL << CAN_FA1R_FACT9_Pos)      /*!< 0x00000200 */\n#define CAN_FA1R_FACT9                       CAN_FA1R_FACT9_Msk                /*!< Filter 9 Active */\n#define CAN_FA1R_FACT10_Pos                  (10U)                             \n#define CAN_FA1R_FACT10_Msk                  (0x1UL << CAN_FA1R_FACT10_Pos)     /*!< 0x00000400 */\n#define CAN_FA1R_FACT10                      CAN_FA1R_FACT10_Msk               /*!< Filter 10 Active */\n#define CAN_FA1R_FACT11_Pos                  (11U)                             \n#define CAN_FA1R_FACT11_Msk                  (0x1UL << CAN_FA1R_FACT11_Pos)     /*!< 0x00000800 */\n#define CAN_FA1R_FACT11                      CAN_FA1R_FACT11_Msk               /*!< Filter 11 Active */\n#define CAN_FA1R_FACT12_Pos                  (12U)                             \n#define CAN_FA1R_FACT12_Msk                  (0x1UL << CAN_FA1R_FACT12_Pos)     /*!< 0x00001000 */\n#define CAN_FA1R_FACT12                      CAN_FA1R_FACT12_Msk               /*!< Filter 12 Active */\n#define CAN_FA1R_FACT13_Pos                  (13U)                             \n#define CAN_FA1R_FACT13_Msk                  (0x1UL << CAN_FA1R_FACT13_Pos)     /*!< 0x00002000 */\n#define CAN_FA1R_FACT13                      CAN_FA1R_FACT13_Msk               /*!< Filter 13 Active */\n\n/*******************  Bit definition for CAN_F0R1 register  *******************/\n#define CAN_F0R1_FB0_Pos                     (0U)                              \n#define CAN_F0R1_FB0_Msk                     (0x1UL << CAN_F0R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F0R1_FB0                         CAN_F0R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F0R1_FB1_Pos                     (1U)                              \n#define CAN_F0R1_FB1_Msk                     (0x1UL << CAN_F0R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F0R1_FB1                         CAN_F0R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F0R1_FB2_Pos                     (2U)                              \n#define CAN_F0R1_FB2_Msk                     (0x1UL << CAN_F0R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F0R1_FB2                         CAN_F0R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F0R1_FB3_Pos                     (3U)                              \n#define CAN_F0R1_FB3_Msk                     (0x1UL << CAN_F0R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F0R1_FB3                         CAN_F0R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F0R1_FB4_Pos                     (4U)                              \n#define CAN_F0R1_FB4_Msk                     (0x1UL << CAN_F0R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F0R1_FB4                         CAN_F0R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F0R1_FB5_Pos                     (5U)                              \n#define CAN_F0R1_FB5_Msk                     (0x1UL << CAN_F0R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F0R1_FB5                         CAN_F0R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F0R1_FB6_Pos                     (6U)                              \n#define CAN_F0R1_FB6_Msk                     (0x1UL << CAN_F0R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F0R1_FB6                         CAN_F0R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F0R1_FB7_Pos                     (7U)                              \n#define CAN_F0R1_FB7_Msk                     (0x1UL << CAN_F0R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F0R1_FB7                         CAN_F0R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F0R1_FB8_Pos                     (8U)                              \n#define CAN_F0R1_FB8_Msk                     (0x1UL << CAN_F0R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F0R1_FB8                         CAN_F0R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F0R1_FB9_Pos                     (9U)                              \n#define CAN_F0R1_FB9_Msk                     (0x1UL << CAN_F0R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F0R1_FB9                         CAN_F0R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F0R1_FB10_Pos                    (10U)                             \n#define CAN_F0R1_FB10_Msk                    (0x1UL << CAN_F0R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F0R1_FB10                        CAN_F0R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F0R1_FB11_Pos                    (11U)                             \n#define CAN_F0R1_FB11_Msk                    (0x1UL << CAN_F0R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F0R1_FB11                        CAN_F0R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F0R1_FB12_Pos                    (12U)                             \n#define CAN_F0R1_FB12_Msk                    (0x1UL << CAN_F0R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F0R1_FB12                        CAN_F0R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F0R1_FB13_Pos                    (13U)                             \n#define CAN_F0R1_FB13_Msk                    (0x1UL << CAN_F0R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F0R1_FB13                        CAN_F0R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F0R1_FB14_Pos                    (14U)                             \n#define CAN_F0R1_FB14_Msk                    (0x1UL << CAN_F0R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F0R1_FB14                        CAN_F0R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F0R1_FB15_Pos                    (15U)                             \n#define CAN_F0R1_FB15_Msk                    (0x1UL << CAN_F0R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F0R1_FB15                        CAN_F0R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F0R1_FB16_Pos                    (16U)                             \n#define CAN_F0R1_FB16_Msk                    (0x1UL << CAN_F0R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F0R1_FB16                        CAN_F0R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F0R1_FB17_Pos                    (17U)                             \n#define CAN_F0R1_FB17_Msk                    (0x1UL << CAN_F0R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F0R1_FB17                        CAN_F0R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F0R1_FB18_Pos                    (18U)                             \n#define CAN_F0R1_FB18_Msk                    (0x1UL << CAN_F0R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F0R1_FB18                        CAN_F0R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F0R1_FB19_Pos                    (19U)                             \n#define CAN_F0R1_FB19_Msk                    (0x1UL << CAN_F0R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F0R1_FB19                        CAN_F0R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F0R1_FB20_Pos                    (20U)                             \n#define CAN_F0R1_FB20_Msk                    (0x1UL << CAN_F0R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F0R1_FB20                        CAN_F0R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F0R1_FB21_Pos                    (21U)                             \n#define CAN_F0R1_FB21_Msk                    (0x1UL << CAN_F0R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F0R1_FB21                        CAN_F0R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F0R1_FB22_Pos                    (22U)                             \n#define CAN_F0R1_FB22_Msk                    (0x1UL << CAN_F0R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F0R1_FB22                        CAN_F0R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F0R1_FB23_Pos                    (23U)                             \n#define CAN_F0R1_FB23_Msk                    (0x1UL << CAN_F0R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F0R1_FB23                        CAN_F0R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F0R1_FB24_Pos                    (24U)                             \n#define CAN_F0R1_FB24_Msk                    (0x1UL << CAN_F0R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F0R1_FB24                        CAN_F0R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F0R1_FB25_Pos                    (25U)                             \n#define CAN_F0R1_FB25_Msk                    (0x1UL << CAN_F0R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F0R1_FB25                        CAN_F0R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F0R1_FB26_Pos                    (26U)                             \n#define CAN_F0R1_FB26_Msk                    (0x1UL << CAN_F0R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F0R1_FB26                        CAN_F0R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F0R1_FB27_Pos                    (27U)                             \n#define CAN_F0R1_FB27_Msk                    (0x1UL << CAN_F0R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F0R1_FB27                        CAN_F0R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F0R1_FB28_Pos                    (28U)                             \n#define CAN_F0R1_FB28_Msk                    (0x1UL << CAN_F0R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F0R1_FB28                        CAN_F0R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F0R1_FB29_Pos                    (29U)                             \n#define CAN_F0R1_FB29_Msk                    (0x1UL << CAN_F0R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F0R1_FB29                        CAN_F0R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F0R1_FB30_Pos                    (30U)                             \n#define CAN_F0R1_FB30_Msk                    (0x1UL << CAN_F0R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F0R1_FB30                        CAN_F0R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F0R1_FB31_Pos                    (31U)                             \n#define CAN_F0R1_FB31_Msk                    (0x1UL << CAN_F0R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F0R1_FB31                        CAN_F0R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R1 register  *******************/\n#define CAN_F1R1_FB0_Pos                     (0U)                              \n#define CAN_F1R1_FB0_Msk                     (0x1UL << CAN_F1R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F1R1_FB0                         CAN_F1R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F1R1_FB1_Pos                     (1U)                              \n#define CAN_F1R1_FB1_Msk                     (0x1UL << CAN_F1R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F1R1_FB1                         CAN_F1R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F1R1_FB2_Pos                     (2U)                              \n#define CAN_F1R1_FB2_Msk                     (0x1UL << CAN_F1R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F1R1_FB2                         CAN_F1R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F1R1_FB3_Pos                     (3U)                              \n#define CAN_F1R1_FB3_Msk                     (0x1UL << CAN_F1R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F1R1_FB3                         CAN_F1R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F1R1_FB4_Pos                     (4U)                              \n#define CAN_F1R1_FB4_Msk                     (0x1UL << CAN_F1R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F1R1_FB4                         CAN_F1R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F1R1_FB5_Pos                     (5U)                              \n#define CAN_F1R1_FB5_Msk                     (0x1UL << CAN_F1R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F1R1_FB5                         CAN_F1R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F1R1_FB6_Pos                     (6U)                              \n#define CAN_F1R1_FB6_Msk                     (0x1UL << CAN_F1R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F1R1_FB6                         CAN_F1R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F1R1_FB7_Pos                     (7U)                              \n#define CAN_F1R1_FB7_Msk                     (0x1UL << CAN_F1R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F1R1_FB7                         CAN_F1R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F1R1_FB8_Pos                     (8U)                              \n#define CAN_F1R1_FB8_Msk                     (0x1UL << CAN_F1R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F1R1_FB8                         CAN_F1R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F1R1_FB9_Pos                     (9U)                              \n#define CAN_F1R1_FB9_Msk                     (0x1UL << CAN_F1R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F1R1_FB9                         CAN_F1R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F1R1_FB10_Pos                    (10U)                             \n#define CAN_F1R1_FB10_Msk                    (0x1UL << CAN_F1R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F1R1_FB10                        CAN_F1R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F1R1_FB11_Pos                    (11U)                             \n#define CAN_F1R1_FB11_Msk                    (0x1UL << CAN_F1R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F1R1_FB11                        CAN_F1R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F1R1_FB12_Pos                    (12U)                             \n#define CAN_F1R1_FB12_Msk                    (0x1UL << CAN_F1R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F1R1_FB12                        CAN_F1R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F1R1_FB13_Pos                    (13U)                             \n#define CAN_F1R1_FB13_Msk                    (0x1UL << CAN_F1R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F1R1_FB13                        CAN_F1R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F1R1_FB14_Pos                    (14U)                             \n#define CAN_F1R1_FB14_Msk                    (0x1UL << CAN_F1R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F1R1_FB14                        CAN_F1R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F1R1_FB15_Pos                    (15U)                             \n#define CAN_F1R1_FB15_Msk                    (0x1UL << CAN_F1R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F1R1_FB15                        CAN_F1R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F1R1_FB16_Pos                    (16U)                             \n#define CAN_F1R1_FB16_Msk                    (0x1UL << CAN_F1R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F1R1_FB16                        CAN_F1R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F1R1_FB17_Pos                    (17U)                             \n#define CAN_F1R1_FB17_Msk                    (0x1UL << CAN_F1R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F1R1_FB17                        CAN_F1R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F1R1_FB18_Pos                    (18U)                             \n#define CAN_F1R1_FB18_Msk                    (0x1UL << CAN_F1R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F1R1_FB18                        CAN_F1R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F1R1_FB19_Pos                    (19U)                             \n#define CAN_F1R1_FB19_Msk                    (0x1UL << CAN_F1R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F1R1_FB19                        CAN_F1R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F1R1_FB20_Pos                    (20U)                             \n#define CAN_F1R1_FB20_Msk                    (0x1UL << CAN_F1R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F1R1_FB20                        CAN_F1R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F1R1_FB21_Pos                    (21U)                             \n#define CAN_F1R1_FB21_Msk                    (0x1UL << CAN_F1R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F1R1_FB21                        CAN_F1R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F1R1_FB22_Pos                    (22U)                             \n#define CAN_F1R1_FB22_Msk                    (0x1UL << CAN_F1R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F1R1_FB22                        CAN_F1R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F1R1_FB23_Pos                    (23U)                             \n#define CAN_F1R1_FB23_Msk                    (0x1UL << CAN_F1R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F1R1_FB23                        CAN_F1R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F1R1_FB24_Pos                    (24U)                             \n#define CAN_F1R1_FB24_Msk                    (0x1UL << CAN_F1R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F1R1_FB24                        CAN_F1R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F1R1_FB25_Pos                    (25U)                             \n#define CAN_F1R1_FB25_Msk                    (0x1UL << CAN_F1R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F1R1_FB25                        CAN_F1R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F1R1_FB26_Pos                    (26U)                             \n#define CAN_F1R1_FB26_Msk                    (0x1UL << CAN_F1R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F1R1_FB26                        CAN_F1R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F1R1_FB27_Pos                    (27U)                             \n#define CAN_F1R1_FB27_Msk                    (0x1UL << CAN_F1R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F1R1_FB27                        CAN_F1R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F1R1_FB28_Pos                    (28U)                             \n#define CAN_F1R1_FB28_Msk                    (0x1UL << CAN_F1R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F1R1_FB28                        CAN_F1R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F1R1_FB29_Pos                    (29U)                             \n#define CAN_F1R1_FB29_Msk                    (0x1UL << CAN_F1R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F1R1_FB29                        CAN_F1R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F1R1_FB30_Pos                    (30U)                             \n#define CAN_F1R1_FB30_Msk                    (0x1UL << CAN_F1R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F1R1_FB30                        CAN_F1R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F1R1_FB31_Pos                    (31U)                             \n#define CAN_F1R1_FB31_Msk                    (0x1UL << CAN_F1R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F1R1_FB31                        CAN_F1R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R1 register  *******************/\n#define CAN_F2R1_FB0_Pos                     (0U)                              \n#define CAN_F2R1_FB0_Msk                     (0x1UL << CAN_F2R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F2R1_FB0                         CAN_F2R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F2R1_FB1_Pos                     (1U)                              \n#define CAN_F2R1_FB1_Msk                     (0x1UL << CAN_F2R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F2R1_FB1                         CAN_F2R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F2R1_FB2_Pos                     (2U)                              \n#define CAN_F2R1_FB2_Msk                     (0x1UL << CAN_F2R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F2R1_FB2                         CAN_F2R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F2R1_FB3_Pos                     (3U)                              \n#define CAN_F2R1_FB3_Msk                     (0x1UL << CAN_F2R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F2R1_FB3                         CAN_F2R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F2R1_FB4_Pos                     (4U)                              \n#define CAN_F2R1_FB4_Msk                     (0x1UL << CAN_F2R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F2R1_FB4                         CAN_F2R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F2R1_FB5_Pos                     (5U)                              \n#define CAN_F2R1_FB5_Msk                     (0x1UL << CAN_F2R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F2R1_FB5                         CAN_F2R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F2R1_FB6_Pos                     (6U)                              \n#define CAN_F2R1_FB6_Msk                     (0x1UL << CAN_F2R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F2R1_FB6                         CAN_F2R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F2R1_FB7_Pos                     (7U)                              \n#define CAN_F2R1_FB7_Msk                     (0x1UL << CAN_F2R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F2R1_FB7                         CAN_F2R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F2R1_FB8_Pos                     (8U)                              \n#define CAN_F2R1_FB8_Msk                     (0x1UL << CAN_F2R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F2R1_FB8                         CAN_F2R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F2R1_FB9_Pos                     (9U)                              \n#define CAN_F2R1_FB9_Msk                     (0x1UL << CAN_F2R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F2R1_FB9                         CAN_F2R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F2R1_FB10_Pos                    (10U)                             \n#define CAN_F2R1_FB10_Msk                    (0x1UL << CAN_F2R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F2R1_FB10                        CAN_F2R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F2R1_FB11_Pos                    (11U)                             \n#define CAN_F2R1_FB11_Msk                    (0x1UL << CAN_F2R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F2R1_FB11                        CAN_F2R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F2R1_FB12_Pos                    (12U)                             \n#define CAN_F2R1_FB12_Msk                    (0x1UL << CAN_F2R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F2R1_FB12                        CAN_F2R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F2R1_FB13_Pos                    (13U)                             \n#define CAN_F2R1_FB13_Msk                    (0x1UL << CAN_F2R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F2R1_FB13                        CAN_F2R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F2R1_FB14_Pos                    (14U)                             \n#define CAN_F2R1_FB14_Msk                    (0x1UL << CAN_F2R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F2R1_FB14                        CAN_F2R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F2R1_FB15_Pos                    (15U)                             \n#define CAN_F2R1_FB15_Msk                    (0x1UL << CAN_F2R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F2R1_FB15                        CAN_F2R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F2R1_FB16_Pos                    (16U)                             \n#define CAN_F2R1_FB16_Msk                    (0x1UL << CAN_F2R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F2R1_FB16                        CAN_F2R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F2R1_FB17_Pos                    (17U)                             \n#define CAN_F2R1_FB17_Msk                    (0x1UL << CAN_F2R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F2R1_FB17                        CAN_F2R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F2R1_FB18_Pos                    (18U)                             \n#define CAN_F2R1_FB18_Msk                    (0x1UL << CAN_F2R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F2R1_FB18                        CAN_F2R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F2R1_FB19_Pos                    (19U)                             \n#define CAN_F2R1_FB19_Msk                    (0x1UL << CAN_F2R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F2R1_FB19                        CAN_F2R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F2R1_FB20_Pos                    (20U)                             \n#define CAN_F2R1_FB20_Msk                    (0x1UL << CAN_F2R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F2R1_FB20                        CAN_F2R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F2R1_FB21_Pos                    (21U)                             \n#define CAN_F2R1_FB21_Msk                    (0x1UL << CAN_F2R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F2R1_FB21                        CAN_F2R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F2R1_FB22_Pos                    (22U)                             \n#define CAN_F2R1_FB22_Msk                    (0x1UL << CAN_F2R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F2R1_FB22                        CAN_F2R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F2R1_FB23_Pos                    (23U)                             \n#define CAN_F2R1_FB23_Msk                    (0x1UL << CAN_F2R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F2R1_FB23                        CAN_F2R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F2R1_FB24_Pos                    (24U)                             \n#define CAN_F2R1_FB24_Msk                    (0x1UL << CAN_F2R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F2R1_FB24                        CAN_F2R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F2R1_FB25_Pos                    (25U)                             \n#define CAN_F2R1_FB25_Msk                    (0x1UL << CAN_F2R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F2R1_FB25                        CAN_F2R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F2R1_FB26_Pos                    (26U)                             \n#define CAN_F2R1_FB26_Msk                    (0x1UL << CAN_F2R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F2R1_FB26                        CAN_F2R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F2R1_FB27_Pos                    (27U)                             \n#define CAN_F2R1_FB27_Msk                    (0x1UL << CAN_F2R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F2R1_FB27                        CAN_F2R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F2R1_FB28_Pos                    (28U)                             \n#define CAN_F2R1_FB28_Msk                    (0x1UL << CAN_F2R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F2R1_FB28                        CAN_F2R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F2R1_FB29_Pos                    (29U)                             \n#define CAN_F2R1_FB29_Msk                    (0x1UL << CAN_F2R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F2R1_FB29                        CAN_F2R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F2R1_FB30_Pos                    (30U)                             \n#define CAN_F2R1_FB30_Msk                    (0x1UL << CAN_F2R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F2R1_FB30                        CAN_F2R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F2R1_FB31_Pos                    (31U)                             \n#define CAN_F2R1_FB31_Msk                    (0x1UL << CAN_F2R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F2R1_FB31                        CAN_F2R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R1 register  *******************/\n#define CAN_F3R1_FB0_Pos                     (0U)                              \n#define CAN_F3R1_FB0_Msk                     (0x1UL << CAN_F3R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F3R1_FB0                         CAN_F3R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F3R1_FB1_Pos                     (1U)                              \n#define CAN_F3R1_FB1_Msk                     (0x1UL << CAN_F3R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F3R1_FB1                         CAN_F3R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F3R1_FB2_Pos                     (2U)                              \n#define CAN_F3R1_FB2_Msk                     (0x1UL << CAN_F3R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F3R1_FB2                         CAN_F3R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F3R1_FB3_Pos                     (3U)                              \n#define CAN_F3R1_FB3_Msk                     (0x1UL << CAN_F3R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F3R1_FB3                         CAN_F3R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F3R1_FB4_Pos                     (4U)                              \n#define CAN_F3R1_FB4_Msk                     (0x1UL << CAN_F3R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F3R1_FB4                         CAN_F3R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F3R1_FB5_Pos                     (5U)                              \n#define CAN_F3R1_FB5_Msk                     (0x1UL << CAN_F3R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F3R1_FB5                         CAN_F3R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F3R1_FB6_Pos                     (6U)                              \n#define CAN_F3R1_FB6_Msk                     (0x1UL << CAN_F3R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F3R1_FB6                         CAN_F3R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F3R1_FB7_Pos                     (7U)                              \n#define CAN_F3R1_FB7_Msk                     (0x1UL << CAN_F3R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F3R1_FB7                         CAN_F3R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F3R1_FB8_Pos                     (8U)                              \n#define CAN_F3R1_FB8_Msk                     (0x1UL << CAN_F3R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F3R1_FB8                         CAN_F3R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F3R1_FB9_Pos                     (9U)                              \n#define CAN_F3R1_FB9_Msk                     (0x1UL << CAN_F3R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F3R1_FB9                         CAN_F3R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F3R1_FB10_Pos                    (10U)                             \n#define CAN_F3R1_FB10_Msk                    (0x1UL << CAN_F3R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F3R1_FB10                        CAN_F3R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F3R1_FB11_Pos                    (11U)                             \n#define CAN_F3R1_FB11_Msk                    (0x1UL << CAN_F3R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F3R1_FB11                        CAN_F3R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F3R1_FB12_Pos                    (12U)                             \n#define CAN_F3R1_FB12_Msk                    (0x1UL << CAN_F3R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F3R1_FB12                        CAN_F3R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F3R1_FB13_Pos                    (13U)                             \n#define CAN_F3R1_FB13_Msk                    (0x1UL << CAN_F3R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F3R1_FB13                        CAN_F3R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F3R1_FB14_Pos                    (14U)                             \n#define CAN_F3R1_FB14_Msk                    (0x1UL << CAN_F3R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F3R1_FB14                        CAN_F3R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F3R1_FB15_Pos                    (15U)                             \n#define CAN_F3R1_FB15_Msk                    (0x1UL << CAN_F3R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F3R1_FB15                        CAN_F3R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F3R1_FB16_Pos                    (16U)                             \n#define CAN_F3R1_FB16_Msk                    (0x1UL << CAN_F3R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F3R1_FB16                        CAN_F3R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F3R1_FB17_Pos                    (17U)                             \n#define CAN_F3R1_FB17_Msk                    (0x1UL << CAN_F3R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F3R1_FB17                        CAN_F3R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F3R1_FB18_Pos                    (18U)                             \n#define CAN_F3R1_FB18_Msk                    (0x1UL << CAN_F3R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F3R1_FB18                        CAN_F3R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F3R1_FB19_Pos                    (19U)                             \n#define CAN_F3R1_FB19_Msk                    (0x1UL << CAN_F3R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F3R1_FB19                        CAN_F3R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F3R1_FB20_Pos                    (20U)                             \n#define CAN_F3R1_FB20_Msk                    (0x1UL << CAN_F3R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F3R1_FB20                        CAN_F3R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F3R1_FB21_Pos                    (21U)                             \n#define CAN_F3R1_FB21_Msk                    (0x1UL << CAN_F3R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F3R1_FB21                        CAN_F3R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F3R1_FB22_Pos                    (22U)                             \n#define CAN_F3R1_FB22_Msk                    (0x1UL << CAN_F3R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F3R1_FB22                        CAN_F3R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F3R1_FB23_Pos                    (23U)                             \n#define CAN_F3R1_FB23_Msk                    (0x1UL << CAN_F3R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F3R1_FB23                        CAN_F3R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F3R1_FB24_Pos                    (24U)                             \n#define CAN_F3R1_FB24_Msk                    (0x1UL << CAN_F3R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F3R1_FB24                        CAN_F3R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F3R1_FB25_Pos                    (25U)                             \n#define CAN_F3R1_FB25_Msk                    (0x1UL << CAN_F3R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F3R1_FB25                        CAN_F3R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F3R1_FB26_Pos                    (26U)                             \n#define CAN_F3R1_FB26_Msk                    (0x1UL << CAN_F3R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F3R1_FB26                        CAN_F3R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F3R1_FB27_Pos                    (27U)                             \n#define CAN_F3R1_FB27_Msk                    (0x1UL << CAN_F3R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F3R1_FB27                        CAN_F3R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F3R1_FB28_Pos                    (28U)                             \n#define CAN_F3R1_FB28_Msk                    (0x1UL << CAN_F3R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F3R1_FB28                        CAN_F3R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F3R1_FB29_Pos                    (29U)                             \n#define CAN_F3R1_FB29_Msk                    (0x1UL << CAN_F3R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F3R1_FB29                        CAN_F3R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F3R1_FB30_Pos                    (30U)                             \n#define CAN_F3R1_FB30_Msk                    (0x1UL << CAN_F3R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F3R1_FB30                        CAN_F3R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F3R1_FB31_Pos                    (31U)                             \n#define CAN_F3R1_FB31_Msk                    (0x1UL << CAN_F3R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F3R1_FB31                        CAN_F3R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R1 register  *******************/\n#define CAN_F4R1_FB0_Pos                     (0U)                              \n#define CAN_F4R1_FB0_Msk                     (0x1UL << CAN_F4R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F4R1_FB0                         CAN_F4R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F4R1_FB1_Pos                     (1U)                              \n#define CAN_F4R1_FB1_Msk                     (0x1UL << CAN_F4R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F4R1_FB1                         CAN_F4R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F4R1_FB2_Pos                     (2U)                              \n#define CAN_F4R1_FB2_Msk                     (0x1UL << CAN_F4R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F4R1_FB2                         CAN_F4R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F4R1_FB3_Pos                     (3U)                              \n#define CAN_F4R1_FB3_Msk                     (0x1UL << CAN_F4R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F4R1_FB3                         CAN_F4R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F4R1_FB4_Pos                     (4U)                              \n#define CAN_F4R1_FB4_Msk                     (0x1UL << CAN_F4R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F4R1_FB4                         CAN_F4R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F4R1_FB5_Pos                     (5U)                              \n#define CAN_F4R1_FB5_Msk                     (0x1UL << CAN_F4R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F4R1_FB5                         CAN_F4R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F4R1_FB6_Pos                     (6U)                              \n#define CAN_F4R1_FB6_Msk                     (0x1UL << CAN_F4R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F4R1_FB6                         CAN_F4R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F4R1_FB7_Pos                     (7U)                              \n#define CAN_F4R1_FB7_Msk                     (0x1UL << CAN_F4R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F4R1_FB7                         CAN_F4R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F4R1_FB8_Pos                     (8U)                              \n#define CAN_F4R1_FB8_Msk                     (0x1UL << CAN_F4R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F4R1_FB8                         CAN_F4R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F4R1_FB9_Pos                     (9U)                              \n#define CAN_F4R1_FB9_Msk                     (0x1UL << CAN_F4R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F4R1_FB9                         CAN_F4R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F4R1_FB10_Pos                    (10U)                             \n#define CAN_F4R1_FB10_Msk                    (0x1UL << CAN_F4R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F4R1_FB10                        CAN_F4R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F4R1_FB11_Pos                    (11U)                             \n#define CAN_F4R1_FB11_Msk                    (0x1UL << CAN_F4R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F4R1_FB11                        CAN_F4R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F4R1_FB12_Pos                    (12U)                             \n#define CAN_F4R1_FB12_Msk                    (0x1UL << CAN_F4R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F4R1_FB12                        CAN_F4R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F4R1_FB13_Pos                    (13U)                             \n#define CAN_F4R1_FB13_Msk                    (0x1UL << CAN_F4R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F4R1_FB13                        CAN_F4R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F4R1_FB14_Pos                    (14U)                             \n#define CAN_F4R1_FB14_Msk                    (0x1UL << CAN_F4R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F4R1_FB14                        CAN_F4R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F4R1_FB15_Pos                    (15U)                             \n#define CAN_F4R1_FB15_Msk                    (0x1UL << CAN_F4R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F4R1_FB15                        CAN_F4R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F4R1_FB16_Pos                    (16U)                             \n#define CAN_F4R1_FB16_Msk                    (0x1UL << CAN_F4R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F4R1_FB16                        CAN_F4R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F4R1_FB17_Pos                    (17U)                             \n#define CAN_F4R1_FB17_Msk                    (0x1UL << CAN_F4R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F4R1_FB17                        CAN_F4R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F4R1_FB18_Pos                    (18U)                             \n#define CAN_F4R1_FB18_Msk                    (0x1UL << CAN_F4R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F4R1_FB18                        CAN_F4R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F4R1_FB19_Pos                    (19U)                             \n#define CAN_F4R1_FB19_Msk                    (0x1UL << CAN_F4R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F4R1_FB19                        CAN_F4R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F4R1_FB20_Pos                    (20U)                             \n#define CAN_F4R1_FB20_Msk                    (0x1UL << CAN_F4R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F4R1_FB20                        CAN_F4R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F4R1_FB21_Pos                    (21U)                             \n#define CAN_F4R1_FB21_Msk                    (0x1UL << CAN_F4R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F4R1_FB21                        CAN_F4R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F4R1_FB22_Pos                    (22U)                             \n#define CAN_F4R1_FB22_Msk                    (0x1UL << CAN_F4R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F4R1_FB22                        CAN_F4R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F4R1_FB23_Pos                    (23U)                             \n#define CAN_F4R1_FB23_Msk                    (0x1UL << CAN_F4R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F4R1_FB23                        CAN_F4R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F4R1_FB24_Pos                    (24U)                             \n#define CAN_F4R1_FB24_Msk                    (0x1UL << CAN_F4R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F4R1_FB24                        CAN_F4R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F4R1_FB25_Pos                    (25U)                             \n#define CAN_F4R1_FB25_Msk                    (0x1UL << CAN_F4R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F4R1_FB25                        CAN_F4R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F4R1_FB26_Pos                    (26U)                             \n#define CAN_F4R1_FB26_Msk                    (0x1UL << CAN_F4R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F4R1_FB26                        CAN_F4R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F4R1_FB27_Pos                    (27U)                             \n#define CAN_F4R1_FB27_Msk                    (0x1UL << CAN_F4R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F4R1_FB27                        CAN_F4R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F4R1_FB28_Pos                    (28U)                             \n#define CAN_F4R1_FB28_Msk                    (0x1UL << CAN_F4R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F4R1_FB28                        CAN_F4R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F4R1_FB29_Pos                    (29U)                             \n#define CAN_F4R1_FB29_Msk                    (0x1UL << CAN_F4R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F4R1_FB29                        CAN_F4R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F4R1_FB30_Pos                    (30U)                             \n#define CAN_F4R1_FB30_Msk                    (0x1UL << CAN_F4R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F4R1_FB30                        CAN_F4R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F4R1_FB31_Pos                    (31U)                             \n#define CAN_F4R1_FB31_Msk                    (0x1UL << CAN_F4R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F4R1_FB31                        CAN_F4R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R1 register  *******************/\n#define CAN_F5R1_FB0_Pos                     (0U)                              \n#define CAN_F5R1_FB0_Msk                     (0x1UL << CAN_F5R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F5R1_FB0                         CAN_F5R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F5R1_FB1_Pos                     (1U)                              \n#define CAN_F5R1_FB1_Msk                     (0x1UL << CAN_F5R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F5R1_FB1                         CAN_F5R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F5R1_FB2_Pos                     (2U)                              \n#define CAN_F5R1_FB2_Msk                     (0x1UL << CAN_F5R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F5R1_FB2                         CAN_F5R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F5R1_FB3_Pos                     (3U)                              \n#define CAN_F5R1_FB3_Msk                     (0x1UL << CAN_F5R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F5R1_FB3                         CAN_F5R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F5R1_FB4_Pos                     (4U)                              \n#define CAN_F5R1_FB4_Msk                     (0x1UL << CAN_F5R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F5R1_FB4                         CAN_F5R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F5R1_FB5_Pos                     (5U)                              \n#define CAN_F5R1_FB5_Msk                     (0x1UL << CAN_F5R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F5R1_FB5                         CAN_F5R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F5R1_FB6_Pos                     (6U)                              \n#define CAN_F5R1_FB6_Msk                     (0x1UL << CAN_F5R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F5R1_FB6                         CAN_F5R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F5R1_FB7_Pos                     (7U)                              \n#define CAN_F5R1_FB7_Msk                     (0x1UL << CAN_F5R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F5R1_FB7                         CAN_F5R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F5R1_FB8_Pos                     (8U)                              \n#define CAN_F5R1_FB8_Msk                     (0x1UL << CAN_F5R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F5R1_FB8                         CAN_F5R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F5R1_FB9_Pos                     (9U)                              \n#define CAN_F5R1_FB9_Msk                     (0x1UL << CAN_F5R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F5R1_FB9                         CAN_F5R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F5R1_FB10_Pos                    (10U)                             \n#define CAN_F5R1_FB10_Msk                    (0x1UL << CAN_F5R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F5R1_FB10                        CAN_F5R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F5R1_FB11_Pos                    (11U)                             \n#define CAN_F5R1_FB11_Msk                    (0x1UL << CAN_F5R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F5R1_FB11                        CAN_F5R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F5R1_FB12_Pos                    (12U)                             \n#define CAN_F5R1_FB12_Msk                    (0x1UL << CAN_F5R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F5R1_FB12                        CAN_F5R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F5R1_FB13_Pos                    (13U)                             \n#define CAN_F5R1_FB13_Msk                    (0x1UL << CAN_F5R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F5R1_FB13                        CAN_F5R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F5R1_FB14_Pos                    (14U)                             \n#define CAN_F5R1_FB14_Msk                    (0x1UL << CAN_F5R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F5R1_FB14                        CAN_F5R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F5R1_FB15_Pos                    (15U)                             \n#define CAN_F5R1_FB15_Msk                    (0x1UL << CAN_F5R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F5R1_FB15                        CAN_F5R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F5R1_FB16_Pos                    (16U)                             \n#define CAN_F5R1_FB16_Msk                    (0x1UL << CAN_F5R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F5R1_FB16                        CAN_F5R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F5R1_FB17_Pos                    (17U)                             \n#define CAN_F5R1_FB17_Msk                    (0x1UL << CAN_F5R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F5R1_FB17                        CAN_F5R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F5R1_FB18_Pos                    (18U)                             \n#define CAN_F5R1_FB18_Msk                    (0x1UL << CAN_F5R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F5R1_FB18                        CAN_F5R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F5R1_FB19_Pos                    (19U)                             \n#define CAN_F5R1_FB19_Msk                    (0x1UL << CAN_F5R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F5R1_FB19                        CAN_F5R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F5R1_FB20_Pos                    (20U)                             \n#define CAN_F5R1_FB20_Msk                    (0x1UL << CAN_F5R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F5R1_FB20                        CAN_F5R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F5R1_FB21_Pos                    (21U)                             \n#define CAN_F5R1_FB21_Msk                    (0x1UL << CAN_F5R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F5R1_FB21                        CAN_F5R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F5R1_FB22_Pos                    (22U)                             \n#define CAN_F5R1_FB22_Msk                    (0x1UL << CAN_F5R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F5R1_FB22                        CAN_F5R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F5R1_FB23_Pos                    (23U)                             \n#define CAN_F5R1_FB23_Msk                    (0x1UL << CAN_F5R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F5R1_FB23                        CAN_F5R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F5R1_FB24_Pos                    (24U)                             \n#define CAN_F5R1_FB24_Msk                    (0x1UL << CAN_F5R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F5R1_FB24                        CAN_F5R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F5R1_FB25_Pos                    (25U)                             \n#define CAN_F5R1_FB25_Msk                    (0x1UL << CAN_F5R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F5R1_FB25                        CAN_F5R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F5R1_FB26_Pos                    (26U)                             \n#define CAN_F5R1_FB26_Msk                    (0x1UL << CAN_F5R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F5R1_FB26                        CAN_F5R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F5R1_FB27_Pos                    (27U)                             \n#define CAN_F5R1_FB27_Msk                    (0x1UL << CAN_F5R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F5R1_FB27                        CAN_F5R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F5R1_FB28_Pos                    (28U)                             \n#define CAN_F5R1_FB28_Msk                    (0x1UL << CAN_F5R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F5R1_FB28                        CAN_F5R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F5R1_FB29_Pos                    (29U)                             \n#define CAN_F5R1_FB29_Msk                    (0x1UL << CAN_F5R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F5R1_FB29                        CAN_F5R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F5R1_FB30_Pos                    (30U)                             \n#define CAN_F5R1_FB30_Msk                    (0x1UL << CAN_F5R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F5R1_FB30                        CAN_F5R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F5R1_FB31_Pos                    (31U)                             \n#define CAN_F5R1_FB31_Msk                    (0x1UL << CAN_F5R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F5R1_FB31                        CAN_F5R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R1 register  *******************/\n#define CAN_F6R1_FB0_Pos                     (0U)                              \n#define CAN_F6R1_FB0_Msk                     (0x1UL << CAN_F6R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F6R1_FB0                         CAN_F6R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F6R1_FB1_Pos                     (1U)                              \n#define CAN_F6R1_FB1_Msk                     (0x1UL << CAN_F6R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F6R1_FB1                         CAN_F6R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F6R1_FB2_Pos                     (2U)                              \n#define CAN_F6R1_FB2_Msk                     (0x1UL << CAN_F6R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F6R1_FB2                         CAN_F6R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F6R1_FB3_Pos                     (3U)                              \n#define CAN_F6R1_FB3_Msk                     (0x1UL << CAN_F6R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F6R1_FB3                         CAN_F6R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F6R1_FB4_Pos                     (4U)                              \n#define CAN_F6R1_FB4_Msk                     (0x1UL << CAN_F6R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F6R1_FB4                         CAN_F6R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F6R1_FB5_Pos                     (5U)                              \n#define CAN_F6R1_FB5_Msk                     (0x1UL << CAN_F6R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F6R1_FB5                         CAN_F6R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F6R1_FB6_Pos                     (6U)                              \n#define CAN_F6R1_FB6_Msk                     (0x1UL << CAN_F6R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F6R1_FB6                         CAN_F6R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F6R1_FB7_Pos                     (7U)                              \n#define CAN_F6R1_FB7_Msk                     (0x1UL << CAN_F6R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F6R1_FB7                         CAN_F6R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F6R1_FB8_Pos                     (8U)                              \n#define CAN_F6R1_FB8_Msk                     (0x1UL << CAN_F6R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F6R1_FB8                         CAN_F6R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F6R1_FB9_Pos                     (9U)                              \n#define CAN_F6R1_FB9_Msk                     (0x1UL << CAN_F6R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F6R1_FB9                         CAN_F6R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F6R1_FB10_Pos                    (10U)                             \n#define CAN_F6R1_FB10_Msk                    (0x1UL << CAN_F6R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F6R1_FB10                        CAN_F6R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F6R1_FB11_Pos                    (11U)                             \n#define CAN_F6R1_FB11_Msk                    (0x1UL << CAN_F6R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F6R1_FB11                        CAN_F6R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F6R1_FB12_Pos                    (12U)                             \n#define CAN_F6R1_FB12_Msk                    (0x1UL << CAN_F6R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F6R1_FB12                        CAN_F6R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F6R1_FB13_Pos                    (13U)                             \n#define CAN_F6R1_FB13_Msk                    (0x1UL << CAN_F6R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F6R1_FB13                        CAN_F6R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F6R1_FB14_Pos                    (14U)                             \n#define CAN_F6R1_FB14_Msk                    (0x1UL << CAN_F6R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F6R1_FB14                        CAN_F6R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F6R1_FB15_Pos                    (15U)                             \n#define CAN_F6R1_FB15_Msk                    (0x1UL << CAN_F6R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F6R1_FB15                        CAN_F6R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F6R1_FB16_Pos                    (16U)                             \n#define CAN_F6R1_FB16_Msk                    (0x1UL << CAN_F6R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F6R1_FB16                        CAN_F6R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F6R1_FB17_Pos                    (17U)                             \n#define CAN_F6R1_FB17_Msk                    (0x1UL << CAN_F6R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F6R1_FB17                        CAN_F6R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F6R1_FB18_Pos                    (18U)                             \n#define CAN_F6R1_FB18_Msk                    (0x1UL << CAN_F6R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F6R1_FB18                        CAN_F6R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F6R1_FB19_Pos                    (19U)                             \n#define CAN_F6R1_FB19_Msk                    (0x1UL << CAN_F6R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F6R1_FB19                        CAN_F6R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F6R1_FB20_Pos                    (20U)                             \n#define CAN_F6R1_FB20_Msk                    (0x1UL << CAN_F6R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F6R1_FB20                        CAN_F6R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F6R1_FB21_Pos                    (21U)                             \n#define CAN_F6R1_FB21_Msk                    (0x1UL << CAN_F6R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F6R1_FB21                        CAN_F6R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F6R1_FB22_Pos                    (22U)                             \n#define CAN_F6R1_FB22_Msk                    (0x1UL << CAN_F6R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F6R1_FB22                        CAN_F6R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F6R1_FB23_Pos                    (23U)                             \n#define CAN_F6R1_FB23_Msk                    (0x1UL << CAN_F6R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F6R1_FB23                        CAN_F6R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F6R1_FB24_Pos                    (24U)                             \n#define CAN_F6R1_FB24_Msk                    (0x1UL << CAN_F6R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F6R1_FB24                        CAN_F6R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F6R1_FB25_Pos                    (25U)                             \n#define CAN_F6R1_FB25_Msk                    (0x1UL << CAN_F6R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F6R1_FB25                        CAN_F6R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F6R1_FB26_Pos                    (26U)                             \n#define CAN_F6R1_FB26_Msk                    (0x1UL << CAN_F6R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F6R1_FB26                        CAN_F6R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F6R1_FB27_Pos                    (27U)                             \n#define CAN_F6R1_FB27_Msk                    (0x1UL << CAN_F6R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F6R1_FB27                        CAN_F6R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F6R1_FB28_Pos                    (28U)                             \n#define CAN_F6R1_FB28_Msk                    (0x1UL << CAN_F6R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F6R1_FB28                        CAN_F6R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F6R1_FB29_Pos                    (29U)                             \n#define CAN_F6R1_FB29_Msk                    (0x1UL << CAN_F6R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F6R1_FB29                        CAN_F6R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F6R1_FB30_Pos                    (30U)                             \n#define CAN_F6R1_FB30_Msk                    (0x1UL << CAN_F6R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F6R1_FB30                        CAN_F6R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F6R1_FB31_Pos                    (31U)                             \n#define CAN_F6R1_FB31_Msk                    (0x1UL << CAN_F6R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F6R1_FB31                        CAN_F6R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R1 register  *******************/\n#define CAN_F7R1_FB0_Pos                     (0U)                              \n#define CAN_F7R1_FB0_Msk                     (0x1UL << CAN_F7R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F7R1_FB0                         CAN_F7R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F7R1_FB1_Pos                     (1U)                              \n#define CAN_F7R1_FB1_Msk                     (0x1UL << CAN_F7R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F7R1_FB1                         CAN_F7R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F7R1_FB2_Pos                     (2U)                              \n#define CAN_F7R1_FB2_Msk                     (0x1UL << CAN_F7R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F7R1_FB2                         CAN_F7R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F7R1_FB3_Pos                     (3U)                              \n#define CAN_F7R1_FB3_Msk                     (0x1UL << CAN_F7R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F7R1_FB3                         CAN_F7R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F7R1_FB4_Pos                     (4U)                              \n#define CAN_F7R1_FB4_Msk                     (0x1UL << CAN_F7R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F7R1_FB4                         CAN_F7R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F7R1_FB5_Pos                     (5U)                              \n#define CAN_F7R1_FB5_Msk                     (0x1UL << CAN_F7R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F7R1_FB5                         CAN_F7R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F7R1_FB6_Pos                     (6U)                              \n#define CAN_F7R1_FB6_Msk                     (0x1UL << CAN_F7R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F7R1_FB6                         CAN_F7R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F7R1_FB7_Pos                     (7U)                              \n#define CAN_F7R1_FB7_Msk                     (0x1UL << CAN_F7R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F7R1_FB7                         CAN_F7R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F7R1_FB8_Pos                     (8U)                              \n#define CAN_F7R1_FB8_Msk                     (0x1UL << CAN_F7R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F7R1_FB8                         CAN_F7R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F7R1_FB9_Pos                     (9U)                              \n#define CAN_F7R1_FB9_Msk                     (0x1UL << CAN_F7R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F7R1_FB9                         CAN_F7R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F7R1_FB10_Pos                    (10U)                             \n#define CAN_F7R1_FB10_Msk                    (0x1UL << CAN_F7R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F7R1_FB10                        CAN_F7R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F7R1_FB11_Pos                    (11U)                             \n#define CAN_F7R1_FB11_Msk                    (0x1UL << CAN_F7R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F7R1_FB11                        CAN_F7R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F7R1_FB12_Pos                    (12U)                             \n#define CAN_F7R1_FB12_Msk                    (0x1UL << CAN_F7R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F7R1_FB12                        CAN_F7R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F7R1_FB13_Pos                    (13U)                             \n#define CAN_F7R1_FB13_Msk                    (0x1UL << CAN_F7R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F7R1_FB13                        CAN_F7R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F7R1_FB14_Pos                    (14U)                             \n#define CAN_F7R1_FB14_Msk                    (0x1UL << CAN_F7R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F7R1_FB14                        CAN_F7R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F7R1_FB15_Pos                    (15U)                             \n#define CAN_F7R1_FB15_Msk                    (0x1UL << CAN_F7R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F7R1_FB15                        CAN_F7R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F7R1_FB16_Pos                    (16U)                             \n#define CAN_F7R1_FB16_Msk                    (0x1UL << CAN_F7R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F7R1_FB16                        CAN_F7R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F7R1_FB17_Pos                    (17U)                             \n#define CAN_F7R1_FB17_Msk                    (0x1UL << CAN_F7R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F7R1_FB17                        CAN_F7R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F7R1_FB18_Pos                    (18U)                             \n#define CAN_F7R1_FB18_Msk                    (0x1UL << CAN_F7R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F7R1_FB18                        CAN_F7R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F7R1_FB19_Pos                    (19U)                             \n#define CAN_F7R1_FB19_Msk                    (0x1UL << CAN_F7R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F7R1_FB19                        CAN_F7R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F7R1_FB20_Pos                    (20U)                             \n#define CAN_F7R1_FB20_Msk                    (0x1UL << CAN_F7R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F7R1_FB20                        CAN_F7R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F7R1_FB21_Pos                    (21U)                             \n#define CAN_F7R1_FB21_Msk                    (0x1UL << CAN_F7R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F7R1_FB21                        CAN_F7R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F7R1_FB22_Pos                    (22U)                             \n#define CAN_F7R1_FB22_Msk                    (0x1UL << CAN_F7R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F7R1_FB22                        CAN_F7R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F7R1_FB23_Pos                    (23U)                             \n#define CAN_F7R1_FB23_Msk                    (0x1UL << CAN_F7R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F7R1_FB23                        CAN_F7R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F7R1_FB24_Pos                    (24U)                             \n#define CAN_F7R1_FB24_Msk                    (0x1UL << CAN_F7R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F7R1_FB24                        CAN_F7R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F7R1_FB25_Pos                    (25U)                             \n#define CAN_F7R1_FB25_Msk                    (0x1UL << CAN_F7R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F7R1_FB25                        CAN_F7R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F7R1_FB26_Pos                    (26U)                             \n#define CAN_F7R1_FB26_Msk                    (0x1UL << CAN_F7R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F7R1_FB26                        CAN_F7R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F7R1_FB27_Pos                    (27U)                             \n#define CAN_F7R1_FB27_Msk                    (0x1UL << CAN_F7R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F7R1_FB27                        CAN_F7R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F7R1_FB28_Pos                    (28U)                             \n#define CAN_F7R1_FB28_Msk                    (0x1UL << CAN_F7R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F7R1_FB28                        CAN_F7R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F7R1_FB29_Pos                    (29U)                             \n#define CAN_F7R1_FB29_Msk                    (0x1UL << CAN_F7R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F7R1_FB29                        CAN_F7R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F7R1_FB30_Pos                    (30U)                             \n#define CAN_F7R1_FB30_Msk                    (0x1UL << CAN_F7R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F7R1_FB30                        CAN_F7R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F7R1_FB31_Pos                    (31U)                             \n#define CAN_F7R1_FB31_Msk                    (0x1UL << CAN_F7R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F7R1_FB31                        CAN_F7R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R1 register  *******************/\n#define CAN_F8R1_FB0_Pos                     (0U)                              \n#define CAN_F8R1_FB0_Msk                     (0x1UL << CAN_F8R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F8R1_FB0                         CAN_F8R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F8R1_FB1_Pos                     (1U)                              \n#define CAN_F8R1_FB1_Msk                     (0x1UL << CAN_F8R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F8R1_FB1                         CAN_F8R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F8R1_FB2_Pos                     (2U)                              \n#define CAN_F8R1_FB2_Msk                     (0x1UL << CAN_F8R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F8R1_FB2                         CAN_F8R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F8R1_FB3_Pos                     (3U)                              \n#define CAN_F8R1_FB3_Msk                     (0x1UL << CAN_F8R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F8R1_FB3                         CAN_F8R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F8R1_FB4_Pos                     (4U)                              \n#define CAN_F8R1_FB4_Msk                     (0x1UL << CAN_F8R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F8R1_FB4                         CAN_F8R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F8R1_FB5_Pos                     (5U)                              \n#define CAN_F8R1_FB5_Msk                     (0x1UL << CAN_F8R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F8R1_FB5                         CAN_F8R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F8R1_FB6_Pos                     (6U)                              \n#define CAN_F8R1_FB6_Msk                     (0x1UL << CAN_F8R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F8R1_FB6                         CAN_F8R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F8R1_FB7_Pos                     (7U)                              \n#define CAN_F8R1_FB7_Msk                     (0x1UL << CAN_F8R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F8R1_FB7                         CAN_F8R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F8R1_FB8_Pos                     (8U)                              \n#define CAN_F8R1_FB8_Msk                     (0x1UL << CAN_F8R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F8R1_FB8                         CAN_F8R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F8R1_FB9_Pos                     (9U)                              \n#define CAN_F8R1_FB9_Msk                     (0x1UL << CAN_F8R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F8R1_FB9                         CAN_F8R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F8R1_FB10_Pos                    (10U)                             \n#define CAN_F8R1_FB10_Msk                    (0x1UL << CAN_F8R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F8R1_FB10                        CAN_F8R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F8R1_FB11_Pos                    (11U)                             \n#define CAN_F8R1_FB11_Msk                    (0x1UL << CAN_F8R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F8R1_FB11                        CAN_F8R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F8R1_FB12_Pos                    (12U)                             \n#define CAN_F8R1_FB12_Msk                    (0x1UL << CAN_F8R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F8R1_FB12                        CAN_F8R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F8R1_FB13_Pos                    (13U)                             \n#define CAN_F8R1_FB13_Msk                    (0x1UL << CAN_F8R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F8R1_FB13                        CAN_F8R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F8R1_FB14_Pos                    (14U)                             \n#define CAN_F8R1_FB14_Msk                    (0x1UL << CAN_F8R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F8R1_FB14                        CAN_F8R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F8R1_FB15_Pos                    (15U)                             \n#define CAN_F8R1_FB15_Msk                    (0x1UL << CAN_F8R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F8R1_FB15                        CAN_F8R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F8R1_FB16_Pos                    (16U)                             \n#define CAN_F8R1_FB16_Msk                    (0x1UL << CAN_F8R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F8R1_FB16                        CAN_F8R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F8R1_FB17_Pos                    (17U)                             \n#define CAN_F8R1_FB17_Msk                    (0x1UL << CAN_F8R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F8R1_FB17                        CAN_F8R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F8R1_FB18_Pos                    (18U)                             \n#define CAN_F8R1_FB18_Msk                    (0x1UL << CAN_F8R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F8R1_FB18                        CAN_F8R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F8R1_FB19_Pos                    (19U)                             \n#define CAN_F8R1_FB19_Msk                    (0x1UL << CAN_F8R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F8R1_FB19                        CAN_F8R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F8R1_FB20_Pos                    (20U)                             \n#define CAN_F8R1_FB20_Msk                    (0x1UL << CAN_F8R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F8R1_FB20                        CAN_F8R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F8R1_FB21_Pos                    (21U)                             \n#define CAN_F8R1_FB21_Msk                    (0x1UL << CAN_F8R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F8R1_FB21                        CAN_F8R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F8R1_FB22_Pos                    (22U)                             \n#define CAN_F8R1_FB22_Msk                    (0x1UL << CAN_F8R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F8R1_FB22                        CAN_F8R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F8R1_FB23_Pos                    (23U)                             \n#define CAN_F8R1_FB23_Msk                    (0x1UL << CAN_F8R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F8R1_FB23                        CAN_F8R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F8R1_FB24_Pos                    (24U)                             \n#define CAN_F8R1_FB24_Msk                    (0x1UL << CAN_F8R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F8R1_FB24                        CAN_F8R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F8R1_FB25_Pos                    (25U)                             \n#define CAN_F8R1_FB25_Msk                    (0x1UL << CAN_F8R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F8R1_FB25                        CAN_F8R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F8R1_FB26_Pos                    (26U)                             \n#define CAN_F8R1_FB26_Msk                    (0x1UL << CAN_F8R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F8R1_FB26                        CAN_F8R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F8R1_FB27_Pos                    (27U)                             \n#define CAN_F8R1_FB27_Msk                    (0x1UL << CAN_F8R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F8R1_FB27                        CAN_F8R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F8R1_FB28_Pos                    (28U)                             \n#define CAN_F8R1_FB28_Msk                    (0x1UL << CAN_F8R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F8R1_FB28                        CAN_F8R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F8R1_FB29_Pos                    (29U)                             \n#define CAN_F8R1_FB29_Msk                    (0x1UL << CAN_F8R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F8R1_FB29                        CAN_F8R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F8R1_FB30_Pos                    (30U)                             \n#define CAN_F8R1_FB30_Msk                    (0x1UL << CAN_F8R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F8R1_FB30                        CAN_F8R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F8R1_FB31_Pos                    (31U)                             \n#define CAN_F8R1_FB31_Msk                    (0x1UL << CAN_F8R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F8R1_FB31                        CAN_F8R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R1 register  *******************/\n#define CAN_F9R1_FB0_Pos                     (0U)                              \n#define CAN_F9R1_FB0_Msk                     (0x1UL << CAN_F9R1_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F9R1_FB0                         CAN_F9R1_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F9R1_FB1_Pos                     (1U)                              \n#define CAN_F9R1_FB1_Msk                     (0x1UL << CAN_F9R1_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F9R1_FB1                         CAN_F9R1_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F9R1_FB2_Pos                     (2U)                              \n#define CAN_F9R1_FB2_Msk                     (0x1UL << CAN_F9R1_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F9R1_FB2                         CAN_F9R1_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F9R1_FB3_Pos                     (3U)                              \n#define CAN_F9R1_FB3_Msk                     (0x1UL << CAN_F9R1_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F9R1_FB3                         CAN_F9R1_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F9R1_FB4_Pos                     (4U)                              \n#define CAN_F9R1_FB4_Msk                     (0x1UL << CAN_F9R1_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F9R1_FB4                         CAN_F9R1_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F9R1_FB5_Pos                     (5U)                              \n#define CAN_F9R1_FB5_Msk                     (0x1UL << CAN_F9R1_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F9R1_FB5                         CAN_F9R1_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F9R1_FB6_Pos                     (6U)                              \n#define CAN_F9R1_FB6_Msk                     (0x1UL << CAN_F9R1_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F9R1_FB6                         CAN_F9R1_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F9R1_FB7_Pos                     (7U)                              \n#define CAN_F9R1_FB7_Msk                     (0x1UL << CAN_F9R1_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F9R1_FB7                         CAN_F9R1_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F9R1_FB8_Pos                     (8U)                              \n#define CAN_F9R1_FB8_Msk                     (0x1UL << CAN_F9R1_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F9R1_FB8                         CAN_F9R1_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F9R1_FB9_Pos                     (9U)                              \n#define CAN_F9R1_FB9_Msk                     (0x1UL << CAN_F9R1_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F9R1_FB9                         CAN_F9R1_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F9R1_FB10_Pos                    (10U)                             \n#define CAN_F9R1_FB10_Msk                    (0x1UL << CAN_F9R1_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F9R1_FB10                        CAN_F9R1_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F9R1_FB11_Pos                    (11U)                             \n#define CAN_F9R1_FB11_Msk                    (0x1UL << CAN_F9R1_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F9R1_FB11                        CAN_F9R1_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F9R1_FB12_Pos                    (12U)                             \n#define CAN_F9R1_FB12_Msk                    (0x1UL << CAN_F9R1_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F9R1_FB12                        CAN_F9R1_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F9R1_FB13_Pos                    (13U)                             \n#define CAN_F9R1_FB13_Msk                    (0x1UL << CAN_F9R1_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F9R1_FB13                        CAN_F9R1_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F9R1_FB14_Pos                    (14U)                             \n#define CAN_F9R1_FB14_Msk                    (0x1UL << CAN_F9R1_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F9R1_FB14                        CAN_F9R1_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F9R1_FB15_Pos                    (15U)                             \n#define CAN_F9R1_FB15_Msk                    (0x1UL << CAN_F9R1_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F9R1_FB15                        CAN_F9R1_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F9R1_FB16_Pos                    (16U)                             \n#define CAN_F9R1_FB16_Msk                    (0x1UL << CAN_F9R1_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F9R1_FB16                        CAN_F9R1_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F9R1_FB17_Pos                    (17U)                             \n#define CAN_F9R1_FB17_Msk                    (0x1UL << CAN_F9R1_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F9R1_FB17                        CAN_F9R1_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F9R1_FB18_Pos                    (18U)                             \n#define CAN_F9R1_FB18_Msk                    (0x1UL << CAN_F9R1_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F9R1_FB18                        CAN_F9R1_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F9R1_FB19_Pos                    (19U)                             \n#define CAN_F9R1_FB19_Msk                    (0x1UL << CAN_F9R1_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F9R1_FB19                        CAN_F9R1_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F9R1_FB20_Pos                    (20U)                             \n#define CAN_F9R1_FB20_Msk                    (0x1UL << CAN_F9R1_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F9R1_FB20                        CAN_F9R1_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F9R1_FB21_Pos                    (21U)                             \n#define CAN_F9R1_FB21_Msk                    (0x1UL << CAN_F9R1_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F9R1_FB21                        CAN_F9R1_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F9R1_FB22_Pos                    (22U)                             \n#define CAN_F9R1_FB22_Msk                    (0x1UL << CAN_F9R1_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F9R1_FB22                        CAN_F9R1_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F9R1_FB23_Pos                    (23U)                             \n#define CAN_F9R1_FB23_Msk                    (0x1UL << CAN_F9R1_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F9R1_FB23                        CAN_F9R1_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F9R1_FB24_Pos                    (24U)                             \n#define CAN_F9R1_FB24_Msk                    (0x1UL << CAN_F9R1_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F9R1_FB24                        CAN_F9R1_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F9R1_FB25_Pos                    (25U)                             \n#define CAN_F9R1_FB25_Msk                    (0x1UL << CAN_F9R1_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F9R1_FB25                        CAN_F9R1_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F9R1_FB26_Pos                    (26U)                             \n#define CAN_F9R1_FB26_Msk                    (0x1UL << CAN_F9R1_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F9R1_FB26                        CAN_F9R1_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F9R1_FB27_Pos                    (27U)                             \n#define CAN_F9R1_FB27_Msk                    (0x1UL << CAN_F9R1_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F9R1_FB27                        CAN_F9R1_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F9R1_FB28_Pos                    (28U)                             \n#define CAN_F9R1_FB28_Msk                    (0x1UL << CAN_F9R1_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F9R1_FB28                        CAN_F9R1_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F9R1_FB29_Pos                    (29U)                             \n#define CAN_F9R1_FB29_Msk                    (0x1UL << CAN_F9R1_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F9R1_FB29                        CAN_F9R1_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F9R1_FB30_Pos                    (30U)                             \n#define CAN_F9R1_FB30_Msk                    (0x1UL << CAN_F9R1_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F9R1_FB30                        CAN_F9R1_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F9R1_FB31_Pos                    (31U)                             \n#define CAN_F9R1_FB31_Msk                    (0x1UL << CAN_F9R1_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F9R1_FB31                        CAN_F9R1_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R1 register  ******************/\n#define CAN_F10R1_FB0_Pos                    (0U)                              \n#define CAN_F10R1_FB0_Msk                    (0x1UL << CAN_F10R1_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F10R1_FB0                        CAN_F10R1_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F10R1_FB1_Pos                    (1U)                              \n#define CAN_F10R1_FB1_Msk                    (0x1UL << CAN_F10R1_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F10R1_FB1                        CAN_F10R1_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F10R1_FB2_Pos                    (2U)                              \n#define CAN_F10R1_FB2_Msk                    (0x1UL << CAN_F10R1_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F10R1_FB2                        CAN_F10R1_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F10R1_FB3_Pos                    (3U)                              \n#define CAN_F10R1_FB3_Msk                    (0x1UL << CAN_F10R1_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F10R1_FB3                        CAN_F10R1_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F10R1_FB4_Pos                    (4U)                              \n#define CAN_F10R1_FB4_Msk                    (0x1UL << CAN_F10R1_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F10R1_FB4                        CAN_F10R1_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F10R1_FB5_Pos                    (5U)                              \n#define CAN_F10R1_FB5_Msk                    (0x1UL << CAN_F10R1_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F10R1_FB5                        CAN_F10R1_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F10R1_FB6_Pos                    (6U)                              \n#define CAN_F10R1_FB6_Msk                    (0x1UL << CAN_F10R1_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F10R1_FB6                        CAN_F10R1_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F10R1_FB7_Pos                    (7U)                              \n#define CAN_F10R1_FB7_Msk                    (0x1UL << CAN_F10R1_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F10R1_FB7                        CAN_F10R1_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F10R1_FB8_Pos                    (8U)                              \n#define CAN_F10R1_FB8_Msk                    (0x1UL << CAN_F10R1_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F10R1_FB8                        CAN_F10R1_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F10R1_FB9_Pos                    (9U)                              \n#define CAN_F10R1_FB9_Msk                    (0x1UL << CAN_F10R1_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F10R1_FB9                        CAN_F10R1_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F10R1_FB10_Pos                   (10U)                             \n#define CAN_F10R1_FB10_Msk                   (0x1UL << CAN_F10R1_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F10R1_FB10                       CAN_F10R1_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F10R1_FB11_Pos                   (11U)                             \n#define CAN_F10R1_FB11_Msk                   (0x1UL << CAN_F10R1_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F10R1_FB11                       CAN_F10R1_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F10R1_FB12_Pos                   (12U)                             \n#define CAN_F10R1_FB12_Msk                   (0x1UL << CAN_F10R1_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F10R1_FB12                       CAN_F10R1_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F10R1_FB13_Pos                   (13U)                             \n#define CAN_F10R1_FB13_Msk                   (0x1UL << CAN_F10R1_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F10R1_FB13                       CAN_F10R1_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F10R1_FB14_Pos                   (14U)                             \n#define CAN_F10R1_FB14_Msk                   (0x1UL << CAN_F10R1_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F10R1_FB14                       CAN_F10R1_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F10R1_FB15_Pos                   (15U)                             \n#define CAN_F10R1_FB15_Msk                   (0x1UL << CAN_F10R1_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F10R1_FB15                       CAN_F10R1_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F10R1_FB16_Pos                   (16U)                             \n#define CAN_F10R1_FB16_Msk                   (0x1UL << CAN_F10R1_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F10R1_FB16                       CAN_F10R1_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F10R1_FB17_Pos                   (17U)                             \n#define CAN_F10R1_FB17_Msk                   (0x1UL << CAN_F10R1_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F10R1_FB17                       CAN_F10R1_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F10R1_FB18_Pos                   (18U)                             \n#define CAN_F10R1_FB18_Msk                   (0x1UL << CAN_F10R1_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F10R1_FB18                       CAN_F10R1_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F10R1_FB19_Pos                   (19U)                             \n#define CAN_F10R1_FB19_Msk                   (0x1UL << CAN_F10R1_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F10R1_FB19                       CAN_F10R1_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F10R1_FB20_Pos                   (20U)                             \n#define CAN_F10R1_FB20_Msk                   (0x1UL << CAN_F10R1_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F10R1_FB20                       CAN_F10R1_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F10R1_FB21_Pos                   (21U)                             \n#define CAN_F10R1_FB21_Msk                   (0x1UL << CAN_F10R1_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F10R1_FB21                       CAN_F10R1_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F10R1_FB22_Pos                   (22U)                             \n#define CAN_F10R1_FB22_Msk                   (0x1UL << CAN_F10R1_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F10R1_FB22                       CAN_F10R1_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F10R1_FB23_Pos                   (23U)                             \n#define CAN_F10R1_FB23_Msk                   (0x1UL << CAN_F10R1_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F10R1_FB23                       CAN_F10R1_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F10R1_FB24_Pos                   (24U)                             \n#define CAN_F10R1_FB24_Msk                   (0x1UL << CAN_F10R1_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F10R1_FB24                       CAN_F10R1_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F10R1_FB25_Pos                   (25U)                             \n#define CAN_F10R1_FB25_Msk                   (0x1UL << CAN_F10R1_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F10R1_FB25                       CAN_F10R1_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F10R1_FB26_Pos                   (26U)                             \n#define CAN_F10R1_FB26_Msk                   (0x1UL << CAN_F10R1_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F10R1_FB26                       CAN_F10R1_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F10R1_FB27_Pos                   (27U)                             \n#define CAN_F10R1_FB27_Msk                   (0x1UL << CAN_F10R1_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F10R1_FB27                       CAN_F10R1_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F10R1_FB28_Pos                   (28U)                             \n#define CAN_F10R1_FB28_Msk                   (0x1UL << CAN_F10R1_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F10R1_FB28                       CAN_F10R1_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F10R1_FB29_Pos                   (29U)                             \n#define CAN_F10R1_FB29_Msk                   (0x1UL << CAN_F10R1_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F10R1_FB29                       CAN_F10R1_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F10R1_FB30_Pos                   (30U)                             \n#define CAN_F10R1_FB30_Msk                   (0x1UL << CAN_F10R1_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F10R1_FB30                       CAN_F10R1_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F10R1_FB31_Pos                   (31U)                             \n#define CAN_F10R1_FB31_Msk                   (0x1UL << CAN_F10R1_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F10R1_FB31                       CAN_F10R1_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R1 register  ******************/\n#define CAN_F11R1_FB0_Pos                    (0U)                              \n#define CAN_F11R1_FB0_Msk                    (0x1UL << CAN_F11R1_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F11R1_FB0                        CAN_F11R1_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F11R1_FB1_Pos                    (1U)                              \n#define CAN_F11R1_FB1_Msk                    (0x1UL << CAN_F11R1_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F11R1_FB1                        CAN_F11R1_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F11R1_FB2_Pos                    (2U)                              \n#define CAN_F11R1_FB2_Msk                    (0x1UL << CAN_F11R1_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F11R1_FB2                        CAN_F11R1_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F11R1_FB3_Pos                    (3U)                              \n#define CAN_F11R1_FB3_Msk                    (0x1UL << CAN_F11R1_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F11R1_FB3                        CAN_F11R1_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F11R1_FB4_Pos                    (4U)                              \n#define CAN_F11R1_FB4_Msk                    (0x1UL << CAN_F11R1_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F11R1_FB4                        CAN_F11R1_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F11R1_FB5_Pos                    (5U)                              \n#define CAN_F11R1_FB5_Msk                    (0x1UL << CAN_F11R1_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F11R1_FB5                        CAN_F11R1_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F11R1_FB6_Pos                    (6U)                              \n#define CAN_F11R1_FB6_Msk                    (0x1UL << CAN_F11R1_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F11R1_FB6                        CAN_F11R1_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F11R1_FB7_Pos                    (7U)                              \n#define CAN_F11R1_FB7_Msk                    (0x1UL << CAN_F11R1_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F11R1_FB7                        CAN_F11R1_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F11R1_FB8_Pos                    (8U)                              \n#define CAN_F11R1_FB8_Msk                    (0x1UL << CAN_F11R1_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F11R1_FB8                        CAN_F11R1_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F11R1_FB9_Pos                    (9U)                              \n#define CAN_F11R1_FB9_Msk                    (0x1UL << CAN_F11R1_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F11R1_FB9                        CAN_F11R1_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F11R1_FB10_Pos                   (10U)                             \n#define CAN_F11R1_FB10_Msk                   (0x1UL << CAN_F11R1_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F11R1_FB10                       CAN_F11R1_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F11R1_FB11_Pos                   (11U)                             \n#define CAN_F11R1_FB11_Msk                   (0x1UL << CAN_F11R1_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F11R1_FB11                       CAN_F11R1_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F11R1_FB12_Pos                   (12U)                             \n#define CAN_F11R1_FB12_Msk                   (0x1UL << CAN_F11R1_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F11R1_FB12                       CAN_F11R1_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F11R1_FB13_Pos                   (13U)                             \n#define CAN_F11R1_FB13_Msk                   (0x1UL << CAN_F11R1_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F11R1_FB13                       CAN_F11R1_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F11R1_FB14_Pos                   (14U)                             \n#define CAN_F11R1_FB14_Msk                   (0x1UL << CAN_F11R1_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F11R1_FB14                       CAN_F11R1_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F11R1_FB15_Pos                   (15U)                             \n#define CAN_F11R1_FB15_Msk                   (0x1UL << CAN_F11R1_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F11R1_FB15                       CAN_F11R1_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F11R1_FB16_Pos                   (16U)                             \n#define CAN_F11R1_FB16_Msk                   (0x1UL << CAN_F11R1_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F11R1_FB16                       CAN_F11R1_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F11R1_FB17_Pos                   (17U)                             \n#define CAN_F11R1_FB17_Msk                   (0x1UL << CAN_F11R1_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F11R1_FB17                       CAN_F11R1_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F11R1_FB18_Pos                   (18U)                             \n#define CAN_F11R1_FB18_Msk                   (0x1UL << CAN_F11R1_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F11R1_FB18                       CAN_F11R1_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F11R1_FB19_Pos                   (19U)                             \n#define CAN_F11R1_FB19_Msk                   (0x1UL << CAN_F11R1_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F11R1_FB19                       CAN_F11R1_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F11R1_FB20_Pos                   (20U)                             \n#define CAN_F11R1_FB20_Msk                   (0x1UL << CAN_F11R1_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F11R1_FB20                       CAN_F11R1_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F11R1_FB21_Pos                   (21U)                             \n#define CAN_F11R1_FB21_Msk                   (0x1UL << CAN_F11R1_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F11R1_FB21                       CAN_F11R1_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F11R1_FB22_Pos                   (22U)                             \n#define CAN_F11R1_FB22_Msk                   (0x1UL << CAN_F11R1_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F11R1_FB22                       CAN_F11R1_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F11R1_FB23_Pos                   (23U)                             \n#define CAN_F11R1_FB23_Msk                   (0x1UL << CAN_F11R1_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F11R1_FB23                       CAN_F11R1_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F11R1_FB24_Pos                   (24U)                             \n#define CAN_F11R1_FB24_Msk                   (0x1UL << CAN_F11R1_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F11R1_FB24                       CAN_F11R1_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F11R1_FB25_Pos                   (25U)                             \n#define CAN_F11R1_FB25_Msk                   (0x1UL << CAN_F11R1_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F11R1_FB25                       CAN_F11R1_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F11R1_FB26_Pos                   (26U)                             \n#define CAN_F11R1_FB26_Msk                   (0x1UL << CAN_F11R1_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F11R1_FB26                       CAN_F11R1_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F11R1_FB27_Pos                   (27U)                             \n#define CAN_F11R1_FB27_Msk                   (0x1UL << CAN_F11R1_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F11R1_FB27                       CAN_F11R1_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F11R1_FB28_Pos                   (28U)                             \n#define CAN_F11R1_FB28_Msk                   (0x1UL << CAN_F11R1_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F11R1_FB28                       CAN_F11R1_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F11R1_FB29_Pos                   (29U)                             \n#define CAN_F11R1_FB29_Msk                   (0x1UL << CAN_F11R1_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F11R1_FB29                       CAN_F11R1_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F11R1_FB30_Pos                   (30U)                             \n#define CAN_F11R1_FB30_Msk                   (0x1UL << CAN_F11R1_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F11R1_FB30                       CAN_F11R1_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F11R1_FB31_Pos                   (31U)                             \n#define CAN_F11R1_FB31_Msk                   (0x1UL << CAN_F11R1_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F11R1_FB31                       CAN_F11R1_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R1 register  ******************/\n#define CAN_F12R1_FB0_Pos                    (0U)                              \n#define CAN_F12R1_FB0_Msk                    (0x1UL << CAN_F12R1_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F12R1_FB0                        CAN_F12R1_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F12R1_FB1_Pos                    (1U)                              \n#define CAN_F12R1_FB1_Msk                    (0x1UL << CAN_F12R1_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F12R1_FB1                        CAN_F12R1_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F12R1_FB2_Pos                    (2U)                              \n#define CAN_F12R1_FB2_Msk                    (0x1UL << CAN_F12R1_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F12R1_FB2                        CAN_F12R1_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F12R1_FB3_Pos                    (3U)                              \n#define CAN_F12R1_FB3_Msk                    (0x1UL << CAN_F12R1_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F12R1_FB3                        CAN_F12R1_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F12R1_FB4_Pos                    (4U)                              \n#define CAN_F12R1_FB4_Msk                    (0x1UL << CAN_F12R1_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F12R1_FB4                        CAN_F12R1_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F12R1_FB5_Pos                    (5U)                              \n#define CAN_F12R1_FB5_Msk                    (0x1UL << CAN_F12R1_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F12R1_FB5                        CAN_F12R1_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F12R1_FB6_Pos                    (6U)                              \n#define CAN_F12R1_FB6_Msk                    (0x1UL << CAN_F12R1_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F12R1_FB6                        CAN_F12R1_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F12R1_FB7_Pos                    (7U)                              \n#define CAN_F12R1_FB7_Msk                    (0x1UL << CAN_F12R1_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F12R1_FB7                        CAN_F12R1_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F12R1_FB8_Pos                    (8U)                              \n#define CAN_F12R1_FB8_Msk                    (0x1UL << CAN_F12R1_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F12R1_FB8                        CAN_F12R1_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F12R1_FB9_Pos                    (9U)                              \n#define CAN_F12R1_FB9_Msk                    (0x1UL << CAN_F12R1_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F12R1_FB9                        CAN_F12R1_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F12R1_FB10_Pos                   (10U)                             \n#define CAN_F12R1_FB10_Msk                   (0x1UL << CAN_F12R1_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F12R1_FB10                       CAN_F12R1_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F12R1_FB11_Pos                   (11U)                             \n#define CAN_F12R1_FB11_Msk                   (0x1UL << CAN_F12R1_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F12R1_FB11                       CAN_F12R1_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F12R1_FB12_Pos                   (12U)                             \n#define CAN_F12R1_FB12_Msk                   (0x1UL << CAN_F12R1_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F12R1_FB12                       CAN_F12R1_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F12R1_FB13_Pos                   (13U)                             \n#define CAN_F12R1_FB13_Msk                   (0x1UL << CAN_F12R1_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F12R1_FB13                       CAN_F12R1_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F12R1_FB14_Pos                   (14U)                             \n#define CAN_F12R1_FB14_Msk                   (0x1UL << CAN_F12R1_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F12R1_FB14                       CAN_F12R1_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F12R1_FB15_Pos                   (15U)                             \n#define CAN_F12R1_FB15_Msk                   (0x1UL << CAN_F12R1_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F12R1_FB15                       CAN_F12R1_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F12R1_FB16_Pos                   (16U)                             \n#define CAN_F12R1_FB16_Msk                   (0x1UL << CAN_F12R1_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F12R1_FB16                       CAN_F12R1_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F12R1_FB17_Pos                   (17U)                             \n#define CAN_F12R1_FB17_Msk                   (0x1UL << CAN_F12R1_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F12R1_FB17                       CAN_F12R1_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F12R1_FB18_Pos                   (18U)                             \n#define CAN_F12R1_FB18_Msk                   (0x1UL << CAN_F12R1_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F12R1_FB18                       CAN_F12R1_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F12R1_FB19_Pos                   (19U)                             \n#define CAN_F12R1_FB19_Msk                   (0x1UL << CAN_F12R1_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F12R1_FB19                       CAN_F12R1_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F12R1_FB20_Pos                   (20U)                             \n#define CAN_F12R1_FB20_Msk                   (0x1UL << CAN_F12R1_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F12R1_FB20                       CAN_F12R1_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F12R1_FB21_Pos                   (21U)                             \n#define CAN_F12R1_FB21_Msk                   (0x1UL << CAN_F12R1_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F12R1_FB21                       CAN_F12R1_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F12R1_FB22_Pos                   (22U)                             \n#define CAN_F12R1_FB22_Msk                   (0x1UL << CAN_F12R1_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F12R1_FB22                       CAN_F12R1_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F12R1_FB23_Pos                   (23U)                             \n#define CAN_F12R1_FB23_Msk                   (0x1UL << CAN_F12R1_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F12R1_FB23                       CAN_F12R1_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F12R1_FB24_Pos                   (24U)                             \n#define CAN_F12R1_FB24_Msk                   (0x1UL << CAN_F12R1_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F12R1_FB24                       CAN_F12R1_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F12R1_FB25_Pos                   (25U)                             \n#define CAN_F12R1_FB25_Msk                   (0x1UL << CAN_F12R1_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F12R1_FB25                       CAN_F12R1_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F12R1_FB26_Pos                   (26U)                             \n#define CAN_F12R1_FB26_Msk                   (0x1UL << CAN_F12R1_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F12R1_FB26                       CAN_F12R1_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F12R1_FB27_Pos                   (27U)                             \n#define CAN_F12R1_FB27_Msk                   (0x1UL << CAN_F12R1_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F12R1_FB27                       CAN_F12R1_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F12R1_FB28_Pos                   (28U)                             \n#define CAN_F12R1_FB28_Msk                   (0x1UL << CAN_F12R1_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F12R1_FB28                       CAN_F12R1_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F12R1_FB29_Pos                   (29U)                             \n#define CAN_F12R1_FB29_Msk                   (0x1UL << CAN_F12R1_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F12R1_FB29                       CAN_F12R1_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F12R1_FB30_Pos                   (30U)                             \n#define CAN_F12R1_FB30_Msk                   (0x1UL << CAN_F12R1_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F12R1_FB30                       CAN_F12R1_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F12R1_FB31_Pos                   (31U)                             \n#define CAN_F12R1_FB31_Msk                   (0x1UL << CAN_F12R1_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F12R1_FB31                       CAN_F12R1_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R1 register  ******************/\n#define CAN_F13R1_FB0_Pos                    (0U)                              \n#define CAN_F13R1_FB0_Msk                    (0x1UL << CAN_F13R1_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F13R1_FB0                        CAN_F13R1_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F13R1_FB1_Pos                    (1U)                              \n#define CAN_F13R1_FB1_Msk                    (0x1UL << CAN_F13R1_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F13R1_FB1                        CAN_F13R1_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F13R1_FB2_Pos                    (2U)                              \n#define CAN_F13R1_FB2_Msk                    (0x1UL << CAN_F13R1_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F13R1_FB2                        CAN_F13R1_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F13R1_FB3_Pos                    (3U)                              \n#define CAN_F13R1_FB3_Msk                    (0x1UL << CAN_F13R1_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F13R1_FB3                        CAN_F13R1_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F13R1_FB4_Pos                    (4U)                              \n#define CAN_F13R1_FB4_Msk                    (0x1UL << CAN_F13R1_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F13R1_FB4                        CAN_F13R1_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F13R1_FB5_Pos                    (5U)                              \n#define CAN_F13R1_FB5_Msk                    (0x1UL << CAN_F13R1_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F13R1_FB5                        CAN_F13R1_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F13R1_FB6_Pos                    (6U)                              \n#define CAN_F13R1_FB6_Msk                    (0x1UL << CAN_F13R1_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F13R1_FB6                        CAN_F13R1_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F13R1_FB7_Pos                    (7U)                              \n#define CAN_F13R1_FB7_Msk                    (0x1UL << CAN_F13R1_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F13R1_FB7                        CAN_F13R1_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F13R1_FB8_Pos                    (8U)                              \n#define CAN_F13R1_FB8_Msk                    (0x1UL << CAN_F13R1_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F13R1_FB8                        CAN_F13R1_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F13R1_FB9_Pos                    (9U)                              \n#define CAN_F13R1_FB9_Msk                    (0x1UL << CAN_F13R1_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F13R1_FB9                        CAN_F13R1_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F13R1_FB10_Pos                   (10U)                             \n#define CAN_F13R1_FB10_Msk                   (0x1UL << CAN_F13R1_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F13R1_FB10                       CAN_F13R1_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F13R1_FB11_Pos                   (11U)                             \n#define CAN_F13R1_FB11_Msk                   (0x1UL << CAN_F13R1_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F13R1_FB11                       CAN_F13R1_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F13R1_FB12_Pos                   (12U)                             \n#define CAN_F13R1_FB12_Msk                   (0x1UL << CAN_F13R1_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F13R1_FB12                       CAN_F13R1_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F13R1_FB13_Pos                   (13U)                             \n#define CAN_F13R1_FB13_Msk                   (0x1UL << CAN_F13R1_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F13R1_FB13                       CAN_F13R1_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F13R1_FB14_Pos                   (14U)                             \n#define CAN_F13R1_FB14_Msk                   (0x1UL << CAN_F13R1_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F13R1_FB14                       CAN_F13R1_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F13R1_FB15_Pos                   (15U)                             \n#define CAN_F13R1_FB15_Msk                   (0x1UL << CAN_F13R1_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F13R1_FB15                       CAN_F13R1_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F13R1_FB16_Pos                   (16U)                             \n#define CAN_F13R1_FB16_Msk                   (0x1UL << CAN_F13R1_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F13R1_FB16                       CAN_F13R1_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F13R1_FB17_Pos                   (17U)                             \n#define CAN_F13R1_FB17_Msk                   (0x1UL << CAN_F13R1_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F13R1_FB17                       CAN_F13R1_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F13R1_FB18_Pos                   (18U)                             \n#define CAN_F13R1_FB18_Msk                   (0x1UL << CAN_F13R1_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F13R1_FB18                       CAN_F13R1_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F13R1_FB19_Pos                   (19U)                             \n#define CAN_F13R1_FB19_Msk                   (0x1UL << CAN_F13R1_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F13R1_FB19                       CAN_F13R1_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F13R1_FB20_Pos                   (20U)                             \n#define CAN_F13R1_FB20_Msk                   (0x1UL << CAN_F13R1_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F13R1_FB20                       CAN_F13R1_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F13R1_FB21_Pos                   (21U)                             \n#define CAN_F13R1_FB21_Msk                   (0x1UL << CAN_F13R1_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F13R1_FB21                       CAN_F13R1_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F13R1_FB22_Pos                   (22U)                             \n#define CAN_F13R1_FB22_Msk                   (0x1UL << CAN_F13R1_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F13R1_FB22                       CAN_F13R1_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F13R1_FB23_Pos                   (23U)                             \n#define CAN_F13R1_FB23_Msk                   (0x1UL << CAN_F13R1_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F13R1_FB23                       CAN_F13R1_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F13R1_FB24_Pos                   (24U)                             \n#define CAN_F13R1_FB24_Msk                   (0x1UL << CAN_F13R1_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F13R1_FB24                       CAN_F13R1_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F13R1_FB25_Pos                   (25U)                             \n#define CAN_F13R1_FB25_Msk                   (0x1UL << CAN_F13R1_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F13R1_FB25                       CAN_F13R1_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F13R1_FB26_Pos                   (26U)                             \n#define CAN_F13R1_FB26_Msk                   (0x1UL << CAN_F13R1_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F13R1_FB26                       CAN_F13R1_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F13R1_FB27_Pos                   (27U)                             \n#define CAN_F13R1_FB27_Msk                   (0x1UL << CAN_F13R1_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F13R1_FB27                       CAN_F13R1_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F13R1_FB28_Pos                   (28U)                             \n#define CAN_F13R1_FB28_Msk                   (0x1UL << CAN_F13R1_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F13R1_FB28                       CAN_F13R1_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F13R1_FB29_Pos                   (29U)                             \n#define CAN_F13R1_FB29_Msk                   (0x1UL << CAN_F13R1_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F13R1_FB29                       CAN_F13R1_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F13R1_FB30_Pos                   (30U)                             \n#define CAN_F13R1_FB30_Msk                   (0x1UL << CAN_F13R1_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F13R1_FB30                       CAN_F13R1_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F13R1_FB31_Pos                   (31U)                             \n#define CAN_F13R1_FB31_Msk                   (0x1UL << CAN_F13R1_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F13R1_FB31                       CAN_F13R1_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F0R2 register  *******************/\n#define CAN_F0R2_FB0_Pos                     (0U)                              \n#define CAN_F0R2_FB0_Msk                     (0x1UL << CAN_F0R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F0R2_FB0                         CAN_F0R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F0R2_FB1_Pos                     (1U)                              \n#define CAN_F0R2_FB1_Msk                     (0x1UL << CAN_F0R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F0R2_FB1                         CAN_F0R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F0R2_FB2_Pos                     (2U)                              \n#define CAN_F0R2_FB2_Msk                     (0x1UL << CAN_F0R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F0R2_FB2                         CAN_F0R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F0R2_FB3_Pos                     (3U)                              \n#define CAN_F0R2_FB3_Msk                     (0x1UL << CAN_F0R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F0R2_FB3                         CAN_F0R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F0R2_FB4_Pos                     (4U)                              \n#define CAN_F0R2_FB4_Msk                     (0x1UL << CAN_F0R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F0R2_FB4                         CAN_F0R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F0R2_FB5_Pos                     (5U)                              \n#define CAN_F0R2_FB5_Msk                     (0x1UL << CAN_F0R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F0R2_FB5                         CAN_F0R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F0R2_FB6_Pos                     (6U)                              \n#define CAN_F0R2_FB6_Msk                     (0x1UL << CAN_F0R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F0R2_FB6                         CAN_F0R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F0R2_FB7_Pos                     (7U)                              \n#define CAN_F0R2_FB7_Msk                     (0x1UL << CAN_F0R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F0R2_FB7                         CAN_F0R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F0R2_FB8_Pos                     (8U)                              \n#define CAN_F0R2_FB8_Msk                     (0x1UL << CAN_F0R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F0R2_FB8                         CAN_F0R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F0R2_FB9_Pos                     (9U)                              \n#define CAN_F0R2_FB9_Msk                     (0x1UL << CAN_F0R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F0R2_FB9                         CAN_F0R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F0R2_FB10_Pos                    (10U)                             \n#define CAN_F0R2_FB10_Msk                    (0x1UL << CAN_F0R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F0R2_FB10                        CAN_F0R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F0R2_FB11_Pos                    (11U)                             \n#define CAN_F0R2_FB11_Msk                    (0x1UL << CAN_F0R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F0R2_FB11                        CAN_F0R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F0R2_FB12_Pos                    (12U)                             \n#define CAN_F0R2_FB12_Msk                    (0x1UL << CAN_F0R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F0R2_FB12                        CAN_F0R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F0R2_FB13_Pos                    (13U)                             \n#define CAN_F0R2_FB13_Msk                    (0x1UL << CAN_F0R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F0R2_FB13                        CAN_F0R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F0R2_FB14_Pos                    (14U)                             \n#define CAN_F0R2_FB14_Msk                    (0x1UL << CAN_F0R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F0R2_FB14                        CAN_F0R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F0R2_FB15_Pos                    (15U)                             \n#define CAN_F0R2_FB15_Msk                    (0x1UL << CAN_F0R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F0R2_FB15                        CAN_F0R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F0R2_FB16_Pos                    (16U)                             \n#define CAN_F0R2_FB16_Msk                    (0x1UL << CAN_F0R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F0R2_FB16                        CAN_F0R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F0R2_FB17_Pos                    (17U)                             \n#define CAN_F0R2_FB17_Msk                    (0x1UL << CAN_F0R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F0R2_FB17                        CAN_F0R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F0R2_FB18_Pos                    (18U)                             \n#define CAN_F0R2_FB18_Msk                    (0x1UL << CAN_F0R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F0R2_FB18                        CAN_F0R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F0R2_FB19_Pos                    (19U)                             \n#define CAN_F0R2_FB19_Msk                    (0x1UL << CAN_F0R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F0R2_FB19                        CAN_F0R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F0R2_FB20_Pos                    (20U)                             \n#define CAN_F0R2_FB20_Msk                    (0x1UL << CAN_F0R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F0R2_FB20                        CAN_F0R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F0R2_FB21_Pos                    (21U)                             \n#define CAN_F0R2_FB21_Msk                    (0x1UL << CAN_F0R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F0R2_FB21                        CAN_F0R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F0R2_FB22_Pos                    (22U)                             \n#define CAN_F0R2_FB22_Msk                    (0x1UL << CAN_F0R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F0R2_FB22                        CAN_F0R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F0R2_FB23_Pos                    (23U)                             \n#define CAN_F0R2_FB23_Msk                    (0x1UL << CAN_F0R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F0R2_FB23                        CAN_F0R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F0R2_FB24_Pos                    (24U)                             \n#define CAN_F0R2_FB24_Msk                    (0x1UL << CAN_F0R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F0R2_FB24                        CAN_F0R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F0R2_FB25_Pos                    (25U)                             \n#define CAN_F0R2_FB25_Msk                    (0x1UL << CAN_F0R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F0R2_FB25                        CAN_F0R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F0R2_FB26_Pos                    (26U)                             \n#define CAN_F0R2_FB26_Msk                    (0x1UL << CAN_F0R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F0R2_FB26                        CAN_F0R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F0R2_FB27_Pos                    (27U)                             \n#define CAN_F0R2_FB27_Msk                    (0x1UL << CAN_F0R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F0R2_FB27                        CAN_F0R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F0R2_FB28_Pos                    (28U)                             \n#define CAN_F0R2_FB28_Msk                    (0x1UL << CAN_F0R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F0R2_FB28                        CAN_F0R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F0R2_FB29_Pos                    (29U)                             \n#define CAN_F0R2_FB29_Msk                    (0x1UL << CAN_F0R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F0R2_FB29                        CAN_F0R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F0R2_FB30_Pos                    (30U)                             \n#define CAN_F0R2_FB30_Msk                    (0x1UL << CAN_F0R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F0R2_FB30                        CAN_F0R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F0R2_FB31_Pos                    (31U)                             \n#define CAN_F0R2_FB31_Msk                    (0x1UL << CAN_F0R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F0R2_FB31                        CAN_F0R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F1R2 register  *******************/\n#define CAN_F1R2_FB0_Pos                     (0U)                              \n#define CAN_F1R2_FB0_Msk                     (0x1UL << CAN_F1R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F1R2_FB0                         CAN_F1R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F1R2_FB1_Pos                     (1U)                              \n#define CAN_F1R2_FB1_Msk                     (0x1UL << CAN_F1R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F1R2_FB1                         CAN_F1R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F1R2_FB2_Pos                     (2U)                              \n#define CAN_F1R2_FB2_Msk                     (0x1UL << CAN_F1R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F1R2_FB2                         CAN_F1R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F1R2_FB3_Pos                     (3U)                              \n#define CAN_F1R2_FB3_Msk                     (0x1UL << CAN_F1R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F1R2_FB3                         CAN_F1R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F1R2_FB4_Pos                     (4U)                              \n#define CAN_F1R2_FB4_Msk                     (0x1UL << CAN_F1R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F1R2_FB4                         CAN_F1R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F1R2_FB5_Pos                     (5U)                              \n#define CAN_F1R2_FB5_Msk                     (0x1UL << CAN_F1R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F1R2_FB5                         CAN_F1R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F1R2_FB6_Pos                     (6U)                              \n#define CAN_F1R2_FB6_Msk                     (0x1UL << CAN_F1R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F1R2_FB6                         CAN_F1R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F1R2_FB7_Pos                     (7U)                              \n#define CAN_F1R2_FB7_Msk                     (0x1UL << CAN_F1R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F1R2_FB7                         CAN_F1R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F1R2_FB8_Pos                     (8U)                              \n#define CAN_F1R2_FB8_Msk                     (0x1UL << CAN_F1R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F1R2_FB8                         CAN_F1R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F1R2_FB9_Pos                     (9U)                              \n#define CAN_F1R2_FB9_Msk                     (0x1UL << CAN_F1R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F1R2_FB9                         CAN_F1R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F1R2_FB10_Pos                    (10U)                             \n#define CAN_F1R2_FB10_Msk                    (0x1UL << CAN_F1R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F1R2_FB10                        CAN_F1R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F1R2_FB11_Pos                    (11U)                             \n#define CAN_F1R2_FB11_Msk                    (0x1UL << CAN_F1R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F1R2_FB11                        CAN_F1R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F1R2_FB12_Pos                    (12U)                             \n#define CAN_F1R2_FB12_Msk                    (0x1UL << CAN_F1R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F1R2_FB12                        CAN_F1R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F1R2_FB13_Pos                    (13U)                             \n#define CAN_F1R2_FB13_Msk                    (0x1UL << CAN_F1R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F1R2_FB13                        CAN_F1R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F1R2_FB14_Pos                    (14U)                             \n#define CAN_F1R2_FB14_Msk                    (0x1UL << CAN_F1R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F1R2_FB14                        CAN_F1R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F1R2_FB15_Pos                    (15U)                             \n#define CAN_F1R2_FB15_Msk                    (0x1UL << CAN_F1R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F1R2_FB15                        CAN_F1R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F1R2_FB16_Pos                    (16U)                             \n#define CAN_F1R2_FB16_Msk                    (0x1UL << CAN_F1R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F1R2_FB16                        CAN_F1R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F1R2_FB17_Pos                    (17U)                             \n#define CAN_F1R2_FB17_Msk                    (0x1UL << CAN_F1R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F1R2_FB17                        CAN_F1R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F1R2_FB18_Pos                    (18U)                             \n#define CAN_F1R2_FB18_Msk                    (0x1UL << CAN_F1R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F1R2_FB18                        CAN_F1R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F1R2_FB19_Pos                    (19U)                             \n#define CAN_F1R2_FB19_Msk                    (0x1UL << CAN_F1R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F1R2_FB19                        CAN_F1R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F1R2_FB20_Pos                    (20U)                             \n#define CAN_F1R2_FB20_Msk                    (0x1UL << CAN_F1R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F1R2_FB20                        CAN_F1R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F1R2_FB21_Pos                    (21U)                             \n#define CAN_F1R2_FB21_Msk                    (0x1UL << CAN_F1R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F1R2_FB21                        CAN_F1R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F1R2_FB22_Pos                    (22U)                             \n#define CAN_F1R2_FB22_Msk                    (0x1UL << CAN_F1R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F1R2_FB22                        CAN_F1R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F1R2_FB23_Pos                    (23U)                             \n#define CAN_F1R2_FB23_Msk                    (0x1UL << CAN_F1R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F1R2_FB23                        CAN_F1R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F1R2_FB24_Pos                    (24U)                             \n#define CAN_F1R2_FB24_Msk                    (0x1UL << CAN_F1R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F1R2_FB24                        CAN_F1R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F1R2_FB25_Pos                    (25U)                             \n#define CAN_F1R2_FB25_Msk                    (0x1UL << CAN_F1R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F1R2_FB25                        CAN_F1R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F1R2_FB26_Pos                    (26U)                             \n#define CAN_F1R2_FB26_Msk                    (0x1UL << CAN_F1R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F1R2_FB26                        CAN_F1R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F1R2_FB27_Pos                    (27U)                             \n#define CAN_F1R2_FB27_Msk                    (0x1UL << CAN_F1R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F1R2_FB27                        CAN_F1R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F1R2_FB28_Pos                    (28U)                             \n#define CAN_F1R2_FB28_Msk                    (0x1UL << CAN_F1R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F1R2_FB28                        CAN_F1R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F1R2_FB29_Pos                    (29U)                             \n#define CAN_F1R2_FB29_Msk                    (0x1UL << CAN_F1R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F1R2_FB29                        CAN_F1R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F1R2_FB30_Pos                    (30U)                             \n#define CAN_F1R2_FB30_Msk                    (0x1UL << CAN_F1R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F1R2_FB30                        CAN_F1R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F1R2_FB31_Pos                    (31U)                             \n#define CAN_F1R2_FB31_Msk                    (0x1UL << CAN_F1R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F1R2_FB31                        CAN_F1R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F2R2 register  *******************/\n#define CAN_F2R2_FB0_Pos                     (0U)                              \n#define CAN_F2R2_FB0_Msk                     (0x1UL << CAN_F2R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F2R2_FB0                         CAN_F2R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F2R2_FB1_Pos                     (1U)                              \n#define CAN_F2R2_FB1_Msk                     (0x1UL << CAN_F2R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F2R2_FB1                         CAN_F2R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F2R2_FB2_Pos                     (2U)                              \n#define CAN_F2R2_FB2_Msk                     (0x1UL << CAN_F2R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F2R2_FB2                         CAN_F2R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F2R2_FB3_Pos                     (3U)                              \n#define CAN_F2R2_FB3_Msk                     (0x1UL << CAN_F2R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F2R2_FB3                         CAN_F2R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F2R2_FB4_Pos                     (4U)                              \n#define CAN_F2R2_FB4_Msk                     (0x1UL << CAN_F2R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F2R2_FB4                         CAN_F2R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F2R2_FB5_Pos                     (5U)                              \n#define CAN_F2R2_FB5_Msk                     (0x1UL << CAN_F2R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F2R2_FB5                         CAN_F2R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F2R2_FB6_Pos                     (6U)                              \n#define CAN_F2R2_FB6_Msk                     (0x1UL << CAN_F2R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F2R2_FB6                         CAN_F2R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F2R2_FB7_Pos                     (7U)                              \n#define CAN_F2R2_FB7_Msk                     (0x1UL << CAN_F2R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F2R2_FB7                         CAN_F2R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F2R2_FB8_Pos                     (8U)                              \n#define CAN_F2R2_FB8_Msk                     (0x1UL << CAN_F2R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F2R2_FB8                         CAN_F2R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F2R2_FB9_Pos                     (9U)                              \n#define CAN_F2R2_FB9_Msk                     (0x1UL << CAN_F2R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F2R2_FB9                         CAN_F2R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F2R2_FB10_Pos                    (10U)                             \n#define CAN_F2R2_FB10_Msk                    (0x1UL << CAN_F2R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F2R2_FB10                        CAN_F2R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F2R2_FB11_Pos                    (11U)                             \n#define CAN_F2R2_FB11_Msk                    (0x1UL << CAN_F2R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F2R2_FB11                        CAN_F2R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F2R2_FB12_Pos                    (12U)                             \n#define CAN_F2R2_FB12_Msk                    (0x1UL << CAN_F2R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F2R2_FB12                        CAN_F2R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F2R2_FB13_Pos                    (13U)                             \n#define CAN_F2R2_FB13_Msk                    (0x1UL << CAN_F2R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F2R2_FB13                        CAN_F2R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F2R2_FB14_Pos                    (14U)                             \n#define CAN_F2R2_FB14_Msk                    (0x1UL << CAN_F2R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F2R2_FB14                        CAN_F2R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F2R2_FB15_Pos                    (15U)                             \n#define CAN_F2R2_FB15_Msk                    (0x1UL << CAN_F2R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F2R2_FB15                        CAN_F2R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F2R2_FB16_Pos                    (16U)                             \n#define CAN_F2R2_FB16_Msk                    (0x1UL << CAN_F2R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F2R2_FB16                        CAN_F2R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F2R2_FB17_Pos                    (17U)                             \n#define CAN_F2R2_FB17_Msk                    (0x1UL << CAN_F2R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F2R2_FB17                        CAN_F2R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F2R2_FB18_Pos                    (18U)                             \n#define CAN_F2R2_FB18_Msk                    (0x1UL << CAN_F2R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F2R2_FB18                        CAN_F2R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F2R2_FB19_Pos                    (19U)                             \n#define CAN_F2R2_FB19_Msk                    (0x1UL << CAN_F2R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F2R2_FB19                        CAN_F2R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F2R2_FB20_Pos                    (20U)                             \n#define CAN_F2R2_FB20_Msk                    (0x1UL << CAN_F2R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F2R2_FB20                        CAN_F2R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F2R2_FB21_Pos                    (21U)                             \n#define CAN_F2R2_FB21_Msk                    (0x1UL << CAN_F2R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F2R2_FB21                        CAN_F2R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F2R2_FB22_Pos                    (22U)                             \n#define CAN_F2R2_FB22_Msk                    (0x1UL << CAN_F2R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F2R2_FB22                        CAN_F2R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F2R2_FB23_Pos                    (23U)                             \n#define CAN_F2R2_FB23_Msk                    (0x1UL << CAN_F2R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F2R2_FB23                        CAN_F2R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F2R2_FB24_Pos                    (24U)                             \n#define CAN_F2R2_FB24_Msk                    (0x1UL << CAN_F2R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F2R2_FB24                        CAN_F2R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F2R2_FB25_Pos                    (25U)                             \n#define CAN_F2R2_FB25_Msk                    (0x1UL << CAN_F2R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F2R2_FB25                        CAN_F2R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F2R2_FB26_Pos                    (26U)                             \n#define CAN_F2R2_FB26_Msk                    (0x1UL << CAN_F2R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F2R2_FB26                        CAN_F2R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F2R2_FB27_Pos                    (27U)                             \n#define CAN_F2R2_FB27_Msk                    (0x1UL << CAN_F2R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F2R2_FB27                        CAN_F2R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F2R2_FB28_Pos                    (28U)                             \n#define CAN_F2R2_FB28_Msk                    (0x1UL << CAN_F2R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F2R2_FB28                        CAN_F2R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F2R2_FB29_Pos                    (29U)                             \n#define CAN_F2R2_FB29_Msk                    (0x1UL << CAN_F2R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F2R2_FB29                        CAN_F2R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F2R2_FB30_Pos                    (30U)                             \n#define CAN_F2R2_FB30_Msk                    (0x1UL << CAN_F2R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F2R2_FB30                        CAN_F2R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F2R2_FB31_Pos                    (31U)                             \n#define CAN_F2R2_FB31_Msk                    (0x1UL << CAN_F2R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F2R2_FB31                        CAN_F2R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F3R2 register  *******************/\n#define CAN_F3R2_FB0_Pos                     (0U)                              \n#define CAN_F3R2_FB0_Msk                     (0x1UL << CAN_F3R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F3R2_FB0                         CAN_F3R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F3R2_FB1_Pos                     (1U)                              \n#define CAN_F3R2_FB1_Msk                     (0x1UL << CAN_F3R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F3R2_FB1                         CAN_F3R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F3R2_FB2_Pos                     (2U)                              \n#define CAN_F3R2_FB2_Msk                     (0x1UL << CAN_F3R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F3R2_FB2                         CAN_F3R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F3R2_FB3_Pos                     (3U)                              \n#define CAN_F3R2_FB3_Msk                     (0x1UL << CAN_F3R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F3R2_FB3                         CAN_F3R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F3R2_FB4_Pos                     (4U)                              \n#define CAN_F3R2_FB4_Msk                     (0x1UL << CAN_F3R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F3R2_FB4                         CAN_F3R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F3R2_FB5_Pos                     (5U)                              \n#define CAN_F3R2_FB5_Msk                     (0x1UL << CAN_F3R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F3R2_FB5                         CAN_F3R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F3R2_FB6_Pos                     (6U)                              \n#define CAN_F3R2_FB6_Msk                     (0x1UL << CAN_F3R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F3R2_FB6                         CAN_F3R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F3R2_FB7_Pos                     (7U)                              \n#define CAN_F3R2_FB7_Msk                     (0x1UL << CAN_F3R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F3R2_FB7                         CAN_F3R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F3R2_FB8_Pos                     (8U)                              \n#define CAN_F3R2_FB8_Msk                     (0x1UL << CAN_F3R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F3R2_FB8                         CAN_F3R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F3R2_FB9_Pos                     (9U)                              \n#define CAN_F3R2_FB9_Msk                     (0x1UL << CAN_F3R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F3R2_FB9                         CAN_F3R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F3R2_FB10_Pos                    (10U)                             \n#define CAN_F3R2_FB10_Msk                    (0x1UL << CAN_F3R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F3R2_FB10                        CAN_F3R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F3R2_FB11_Pos                    (11U)                             \n#define CAN_F3R2_FB11_Msk                    (0x1UL << CAN_F3R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F3R2_FB11                        CAN_F3R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F3R2_FB12_Pos                    (12U)                             \n#define CAN_F3R2_FB12_Msk                    (0x1UL << CAN_F3R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F3R2_FB12                        CAN_F3R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F3R2_FB13_Pos                    (13U)                             \n#define CAN_F3R2_FB13_Msk                    (0x1UL << CAN_F3R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F3R2_FB13                        CAN_F3R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F3R2_FB14_Pos                    (14U)                             \n#define CAN_F3R2_FB14_Msk                    (0x1UL << CAN_F3R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F3R2_FB14                        CAN_F3R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F3R2_FB15_Pos                    (15U)                             \n#define CAN_F3R2_FB15_Msk                    (0x1UL << CAN_F3R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F3R2_FB15                        CAN_F3R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F3R2_FB16_Pos                    (16U)                             \n#define CAN_F3R2_FB16_Msk                    (0x1UL << CAN_F3R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F3R2_FB16                        CAN_F3R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F3R2_FB17_Pos                    (17U)                             \n#define CAN_F3R2_FB17_Msk                    (0x1UL << CAN_F3R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F3R2_FB17                        CAN_F3R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F3R2_FB18_Pos                    (18U)                             \n#define CAN_F3R2_FB18_Msk                    (0x1UL << CAN_F3R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F3R2_FB18                        CAN_F3R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F3R2_FB19_Pos                    (19U)                             \n#define CAN_F3R2_FB19_Msk                    (0x1UL << CAN_F3R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F3R2_FB19                        CAN_F3R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F3R2_FB20_Pos                    (20U)                             \n#define CAN_F3R2_FB20_Msk                    (0x1UL << CAN_F3R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F3R2_FB20                        CAN_F3R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F3R2_FB21_Pos                    (21U)                             \n#define CAN_F3R2_FB21_Msk                    (0x1UL << CAN_F3R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F3R2_FB21                        CAN_F3R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F3R2_FB22_Pos                    (22U)                             \n#define CAN_F3R2_FB22_Msk                    (0x1UL << CAN_F3R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F3R2_FB22                        CAN_F3R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F3R2_FB23_Pos                    (23U)                             \n#define CAN_F3R2_FB23_Msk                    (0x1UL << CAN_F3R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F3R2_FB23                        CAN_F3R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F3R2_FB24_Pos                    (24U)                             \n#define CAN_F3R2_FB24_Msk                    (0x1UL << CAN_F3R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F3R2_FB24                        CAN_F3R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F3R2_FB25_Pos                    (25U)                             \n#define CAN_F3R2_FB25_Msk                    (0x1UL << CAN_F3R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F3R2_FB25                        CAN_F3R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F3R2_FB26_Pos                    (26U)                             \n#define CAN_F3R2_FB26_Msk                    (0x1UL << CAN_F3R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F3R2_FB26                        CAN_F3R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F3R2_FB27_Pos                    (27U)                             \n#define CAN_F3R2_FB27_Msk                    (0x1UL << CAN_F3R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F3R2_FB27                        CAN_F3R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F3R2_FB28_Pos                    (28U)                             \n#define CAN_F3R2_FB28_Msk                    (0x1UL << CAN_F3R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F3R2_FB28                        CAN_F3R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F3R2_FB29_Pos                    (29U)                             \n#define CAN_F3R2_FB29_Msk                    (0x1UL << CAN_F3R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F3R2_FB29                        CAN_F3R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F3R2_FB30_Pos                    (30U)                             \n#define CAN_F3R2_FB30_Msk                    (0x1UL << CAN_F3R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F3R2_FB30                        CAN_F3R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F3R2_FB31_Pos                    (31U)                             \n#define CAN_F3R2_FB31_Msk                    (0x1UL << CAN_F3R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F3R2_FB31                        CAN_F3R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F4R2 register  *******************/\n#define CAN_F4R2_FB0_Pos                     (0U)                              \n#define CAN_F4R2_FB0_Msk                     (0x1UL << CAN_F4R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F4R2_FB0                         CAN_F4R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F4R2_FB1_Pos                     (1U)                              \n#define CAN_F4R2_FB1_Msk                     (0x1UL << CAN_F4R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F4R2_FB1                         CAN_F4R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F4R2_FB2_Pos                     (2U)                              \n#define CAN_F4R2_FB2_Msk                     (0x1UL << CAN_F4R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F4R2_FB2                         CAN_F4R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F4R2_FB3_Pos                     (3U)                              \n#define CAN_F4R2_FB3_Msk                     (0x1UL << CAN_F4R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F4R2_FB3                         CAN_F4R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F4R2_FB4_Pos                     (4U)                              \n#define CAN_F4R2_FB4_Msk                     (0x1UL << CAN_F4R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F4R2_FB4                         CAN_F4R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F4R2_FB5_Pos                     (5U)                              \n#define CAN_F4R2_FB5_Msk                     (0x1UL << CAN_F4R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F4R2_FB5                         CAN_F4R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F4R2_FB6_Pos                     (6U)                              \n#define CAN_F4R2_FB6_Msk                     (0x1UL << CAN_F4R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F4R2_FB6                         CAN_F4R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F4R2_FB7_Pos                     (7U)                              \n#define CAN_F4R2_FB7_Msk                     (0x1UL << CAN_F4R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F4R2_FB7                         CAN_F4R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F4R2_FB8_Pos                     (8U)                              \n#define CAN_F4R2_FB8_Msk                     (0x1UL << CAN_F4R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F4R2_FB8                         CAN_F4R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F4R2_FB9_Pos                     (9U)                              \n#define CAN_F4R2_FB9_Msk                     (0x1UL << CAN_F4R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F4R2_FB9                         CAN_F4R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F4R2_FB10_Pos                    (10U)                             \n#define CAN_F4R2_FB10_Msk                    (0x1UL << CAN_F4R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F4R2_FB10                        CAN_F4R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F4R2_FB11_Pos                    (11U)                             \n#define CAN_F4R2_FB11_Msk                    (0x1UL << CAN_F4R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F4R2_FB11                        CAN_F4R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F4R2_FB12_Pos                    (12U)                             \n#define CAN_F4R2_FB12_Msk                    (0x1UL << CAN_F4R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F4R2_FB12                        CAN_F4R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F4R2_FB13_Pos                    (13U)                             \n#define CAN_F4R2_FB13_Msk                    (0x1UL << CAN_F4R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F4R2_FB13                        CAN_F4R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F4R2_FB14_Pos                    (14U)                             \n#define CAN_F4R2_FB14_Msk                    (0x1UL << CAN_F4R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F4R2_FB14                        CAN_F4R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F4R2_FB15_Pos                    (15U)                             \n#define CAN_F4R2_FB15_Msk                    (0x1UL << CAN_F4R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F4R2_FB15                        CAN_F4R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F4R2_FB16_Pos                    (16U)                             \n#define CAN_F4R2_FB16_Msk                    (0x1UL << CAN_F4R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F4R2_FB16                        CAN_F4R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F4R2_FB17_Pos                    (17U)                             \n#define CAN_F4R2_FB17_Msk                    (0x1UL << CAN_F4R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F4R2_FB17                        CAN_F4R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F4R2_FB18_Pos                    (18U)                             \n#define CAN_F4R2_FB18_Msk                    (0x1UL << CAN_F4R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F4R2_FB18                        CAN_F4R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F4R2_FB19_Pos                    (19U)                             \n#define CAN_F4R2_FB19_Msk                    (0x1UL << CAN_F4R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F4R2_FB19                        CAN_F4R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F4R2_FB20_Pos                    (20U)                             \n#define CAN_F4R2_FB20_Msk                    (0x1UL << CAN_F4R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F4R2_FB20                        CAN_F4R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F4R2_FB21_Pos                    (21U)                             \n#define CAN_F4R2_FB21_Msk                    (0x1UL << CAN_F4R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F4R2_FB21                        CAN_F4R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F4R2_FB22_Pos                    (22U)                             \n#define CAN_F4R2_FB22_Msk                    (0x1UL << CAN_F4R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F4R2_FB22                        CAN_F4R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F4R2_FB23_Pos                    (23U)                             \n#define CAN_F4R2_FB23_Msk                    (0x1UL << CAN_F4R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F4R2_FB23                        CAN_F4R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F4R2_FB24_Pos                    (24U)                             \n#define CAN_F4R2_FB24_Msk                    (0x1UL << CAN_F4R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F4R2_FB24                        CAN_F4R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F4R2_FB25_Pos                    (25U)                             \n#define CAN_F4R2_FB25_Msk                    (0x1UL << CAN_F4R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F4R2_FB25                        CAN_F4R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F4R2_FB26_Pos                    (26U)                             \n#define CAN_F4R2_FB26_Msk                    (0x1UL << CAN_F4R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F4R2_FB26                        CAN_F4R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F4R2_FB27_Pos                    (27U)                             \n#define CAN_F4R2_FB27_Msk                    (0x1UL << CAN_F4R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F4R2_FB27                        CAN_F4R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F4R2_FB28_Pos                    (28U)                             \n#define CAN_F4R2_FB28_Msk                    (0x1UL << CAN_F4R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F4R2_FB28                        CAN_F4R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F4R2_FB29_Pos                    (29U)                             \n#define CAN_F4R2_FB29_Msk                    (0x1UL << CAN_F4R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F4R2_FB29                        CAN_F4R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F4R2_FB30_Pos                    (30U)                             \n#define CAN_F4R2_FB30_Msk                    (0x1UL << CAN_F4R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F4R2_FB30                        CAN_F4R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F4R2_FB31_Pos                    (31U)                             \n#define CAN_F4R2_FB31_Msk                    (0x1UL << CAN_F4R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F4R2_FB31                        CAN_F4R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F5R2 register  *******************/\n#define CAN_F5R2_FB0_Pos                     (0U)                              \n#define CAN_F5R2_FB0_Msk                     (0x1UL << CAN_F5R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F5R2_FB0                         CAN_F5R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F5R2_FB1_Pos                     (1U)                              \n#define CAN_F5R2_FB1_Msk                     (0x1UL << CAN_F5R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F5R2_FB1                         CAN_F5R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F5R2_FB2_Pos                     (2U)                              \n#define CAN_F5R2_FB2_Msk                     (0x1UL << CAN_F5R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F5R2_FB2                         CAN_F5R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F5R2_FB3_Pos                     (3U)                              \n#define CAN_F5R2_FB3_Msk                     (0x1UL << CAN_F5R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F5R2_FB3                         CAN_F5R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F5R2_FB4_Pos                     (4U)                              \n#define CAN_F5R2_FB4_Msk                     (0x1UL << CAN_F5R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F5R2_FB4                         CAN_F5R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F5R2_FB5_Pos                     (5U)                              \n#define CAN_F5R2_FB5_Msk                     (0x1UL << CAN_F5R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F5R2_FB5                         CAN_F5R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F5R2_FB6_Pos                     (6U)                              \n#define CAN_F5R2_FB6_Msk                     (0x1UL << CAN_F5R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F5R2_FB6                         CAN_F5R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F5R2_FB7_Pos                     (7U)                              \n#define CAN_F5R2_FB7_Msk                     (0x1UL << CAN_F5R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F5R2_FB7                         CAN_F5R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F5R2_FB8_Pos                     (8U)                              \n#define CAN_F5R2_FB8_Msk                     (0x1UL << CAN_F5R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F5R2_FB8                         CAN_F5R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F5R2_FB9_Pos                     (9U)                              \n#define CAN_F5R2_FB9_Msk                     (0x1UL << CAN_F5R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F5R2_FB9                         CAN_F5R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F5R2_FB10_Pos                    (10U)                             \n#define CAN_F5R2_FB10_Msk                    (0x1UL << CAN_F5R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F5R2_FB10                        CAN_F5R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F5R2_FB11_Pos                    (11U)                             \n#define CAN_F5R2_FB11_Msk                    (0x1UL << CAN_F5R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F5R2_FB11                        CAN_F5R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F5R2_FB12_Pos                    (12U)                             \n#define CAN_F5R2_FB12_Msk                    (0x1UL << CAN_F5R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F5R2_FB12                        CAN_F5R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F5R2_FB13_Pos                    (13U)                             \n#define CAN_F5R2_FB13_Msk                    (0x1UL << CAN_F5R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F5R2_FB13                        CAN_F5R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F5R2_FB14_Pos                    (14U)                             \n#define CAN_F5R2_FB14_Msk                    (0x1UL << CAN_F5R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F5R2_FB14                        CAN_F5R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F5R2_FB15_Pos                    (15U)                             \n#define CAN_F5R2_FB15_Msk                    (0x1UL << CAN_F5R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F5R2_FB15                        CAN_F5R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F5R2_FB16_Pos                    (16U)                             \n#define CAN_F5R2_FB16_Msk                    (0x1UL << CAN_F5R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F5R2_FB16                        CAN_F5R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F5R2_FB17_Pos                    (17U)                             \n#define CAN_F5R2_FB17_Msk                    (0x1UL << CAN_F5R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F5R2_FB17                        CAN_F5R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F5R2_FB18_Pos                    (18U)                             \n#define CAN_F5R2_FB18_Msk                    (0x1UL << CAN_F5R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F5R2_FB18                        CAN_F5R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F5R2_FB19_Pos                    (19U)                             \n#define CAN_F5R2_FB19_Msk                    (0x1UL << CAN_F5R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F5R2_FB19                        CAN_F5R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F5R2_FB20_Pos                    (20U)                             \n#define CAN_F5R2_FB20_Msk                    (0x1UL << CAN_F5R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F5R2_FB20                        CAN_F5R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F5R2_FB21_Pos                    (21U)                             \n#define CAN_F5R2_FB21_Msk                    (0x1UL << CAN_F5R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F5R2_FB21                        CAN_F5R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F5R2_FB22_Pos                    (22U)                             \n#define CAN_F5R2_FB22_Msk                    (0x1UL << CAN_F5R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F5R2_FB22                        CAN_F5R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F5R2_FB23_Pos                    (23U)                             \n#define CAN_F5R2_FB23_Msk                    (0x1UL << CAN_F5R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F5R2_FB23                        CAN_F5R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F5R2_FB24_Pos                    (24U)                             \n#define CAN_F5R2_FB24_Msk                    (0x1UL << CAN_F5R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F5R2_FB24                        CAN_F5R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F5R2_FB25_Pos                    (25U)                             \n#define CAN_F5R2_FB25_Msk                    (0x1UL << CAN_F5R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F5R2_FB25                        CAN_F5R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F5R2_FB26_Pos                    (26U)                             \n#define CAN_F5R2_FB26_Msk                    (0x1UL << CAN_F5R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F5R2_FB26                        CAN_F5R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F5R2_FB27_Pos                    (27U)                             \n#define CAN_F5R2_FB27_Msk                    (0x1UL << CAN_F5R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F5R2_FB27                        CAN_F5R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F5R2_FB28_Pos                    (28U)                             \n#define CAN_F5R2_FB28_Msk                    (0x1UL << CAN_F5R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F5R2_FB28                        CAN_F5R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F5R2_FB29_Pos                    (29U)                             \n#define CAN_F5R2_FB29_Msk                    (0x1UL << CAN_F5R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F5R2_FB29                        CAN_F5R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F5R2_FB30_Pos                    (30U)                             \n#define CAN_F5R2_FB30_Msk                    (0x1UL << CAN_F5R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F5R2_FB30                        CAN_F5R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F5R2_FB31_Pos                    (31U)                             \n#define CAN_F5R2_FB31_Msk                    (0x1UL << CAN_F5R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F5R2_FB31                        CAN_F5R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F6R2 register  *******************/\n#define CAN_F6R2_FB0_Pos                     (0U)                              \n#define CAN_F6R2_FB0_Msk                     (0x1UL << CAN_F6R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F6R2_FB0                         CAN_F6R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F6R2_FB1_Pos                     (1U)                              \n#define CAN_F6R2_FB1_Msk                     (0x1UL << CAN_F6R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F6R2_FB1                         CAN_F6R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F6R2_FB2_Pos                     (2U)                              \n#define CAN_F6R2_FB2_Msk                     (0x1UL << CAN_F6R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F6R2_FB2                         CAN_F6R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F6R2_FB3_Pos                     (3U)                              \n#define CAN_F6R2_FB3_Msk                     (0x1UL << CAN_F6R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F6R2_FB3                         CAN_F6R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F6R2_FB4_Pos                     (4U)                              \n#define CAN_F6R2_FB4_Msk                     (0x1UL << CAN_F6R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F6R2_FB4                         CAN_F6R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F6R2_FB5_Pos                     (5U)                              \n#define CAN_F6R2_FB5_Msk                     (0x1UL << CAN_F6R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F6R2_FB5                         CAN_F6R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F6R2_FB6_Pos                     (6U)                              \n#define CAN_F6R2_FB6_Msk                     (0x1UL << CAN_F6R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F6R2_FB6                         CAN_F6R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F6R2_FB7_Pos                     (7U)                              \n#define CAN_F6R2_FB7_Msk                     (0x1UL << CAN_F6R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F6R2_FB7                         CAN_F6R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F6R2_FB8_Pos                     (8U)                              \n#define CAN_F6R2_FB8_Msk                     (0x1UL << CAN_F6R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F6R2_FB8                         CAN_F6R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F6R2_FB9_Pos                     (9U)                              \n#define CAN_F6R2_FB9_Msk                     (0x1UL << CAN_F6R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F6R2_FB9                         CAN_F6R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F6R2_FB10_Pos                    (10U)                             \n#define CAN_F6R2_FB10_Msk                    (0x1UL << CAN_F6R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F6R2_FB10                        CAN_F6R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F6R2_FB11_Pos                    (11U)                             \n#define CAN_F6R2_FB11_Msk                    (0x1UL << CAN_F6R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F6R2_FB11                        CAN_F6R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F6R2_FB12_Pos                    (12U)                             \n#define CAN_F6R2_FB12_Msk                    (0x1UL << CAN_F6R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F6R2_FB12                        CAN_F6R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F6R2_FB13_Pos                    (13U)                             \n#define CAN_F6R2_FB13_Msk                    (0x1UL << CAN_F6R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F6R2_FB13                        CAN_F6R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F6R2_FB14_Pos                    (14U)                             \n#define CAN_F6R2_FB14_Msk                    (0x1UL << CAN_F6R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F6R2_FB14                        CAN_F6R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F6R2_FB15_Pos                    (15U)                             \n#define CAN_F6R2_FB15_Msk                    (0x1UL << CAN_F6R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F6R2_FB15                        CAN_F6R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F6R2_FB16_Pos                    (16U)                             \n#define CAN_F6R2_FB16_Msk                    (0x1UL << CAN_F6R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F6R2_FB16                        CAN_F6R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F6R2_FB17_Pos                    (17U)                             \n#define CAN_F6R2_FB17_Msk                    (0x1UL << CAN_F6R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F6R2_FB17                        CAN_F6R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F6R2_FB18_Pos                    (18U)                             \n#define CAN_F6R2_FB18_Msk                    (0x1UL << CAN_F6R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F6R2_FB18                        CAN_F6R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F6R2_FB19_Pos                    (19U)                             \n#define CAN_F6R2_FB19_Msk                    (0x1UL << CAN_F6R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F6R2_FB19                        CAN_F6R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F6R2_FB20_Pos                    (20U)                             \n#define CAN_F6R2_FB20_Msk                    (0x1UL << CAN_F6R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F6R2_FB20                        CAN_F6R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F6R2_FB21_Pos                    (21U)                             \n#define CAN_F6R2_FB21_Msk                    (0x1UL << CAN_F6R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F6R2_FB21                        CAN_F6R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F6R2_FB22_Pos                    (22U)                             \n#define CAN_F6R2_FB22_Msk                    (0x1UL << CAN_F6R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F6R2_FB22                        CAN_F6R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F6R2_FB23_Pos                    (23U)                             \n#define CAN_F6R2_FB23_Msk                    (0x1UL << CAN_F6R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F6R2_FB23                        CAN_F6R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F6R2_FB24_Pos                    (24U)                             \n#define CAN_F6R2_FB24_Msk                    (0x1UL << CAN_F6R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F6R2_FB24                        CAN_F6R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F6R2_FB25_Pos                    (25U)                             \n#define CAN_F6R2_FB25_Msk                    (0x1UL << CAN_F6R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F6R2_FB25                        CAN_F6R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F6R2_FB26_Pos                    (26U)                             \n#define CAN_F6R2_FB26_Msk                    (0x1UL << CAN_F6R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F6R2_FB26                        CAN_F6R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F6R2_FB27_Pos                    (27U)                             \n#define CAN_F6R2_FB27_Msk                    (0x1UL << CAN_F6R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F6R2_FB27                        CAN_F6R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F6R2_FB28_Pos                    (28U)                             \n#define CAN_F6R2_FB28_Msk                    (0x1UL << CAN_F6R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F6R2_FB28                        CAN_F6R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F6R2_FB29_Pos                    (29U)                             \n#define CAN_F6R2_FB29_Msk                    (0x1UL << CAN_F6R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F6R2_FB29                        CAN_F6R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F6R2_FB30_Pos                    (30U)                             \n#define CAN_F6R2_FB30_Msk                    (0x1UL << CAN_F6R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F6R2_FB30                        CAN_F6R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F6R2_FB31_Pos                    (31U)                             \n#define CAN_F6R2_FB31_Msk                    (0x1UL << CAN_F6R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F6R2_FB31                        CAN_F6R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F7R2 register  *******************/\n#define CAN_F7R2_FB0_Pos                     (0U)                              \n#define CAN_F7R2_FB0_Msk                     (0x1UL << CAN_F7R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F7R2_FB0                         CAN_F7R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F7R2_FB1_Pos                     (1U)                              \n#define CAN_F7R2_FB1_Msk                     (0x1UL << CAN_F7R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F7R2_FB1                         CAN_F7R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F7R2_FB2_Pos                     (2U)                              \n#define CAN_F7R2_FB2_Msk                     (0x1UL << CAN_F7R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F7R2_FB2                         CAN_F7R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F7R2_FB3_Pos                     (3U)                              \n#define CAN_F7R2_FB3_Msk                     (0x1UL << CAN_F7R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F7R2_FB3                         CAN_F7R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F7R2_FB4_Pos                     (4U)                              \n#define CAN_F7R2_FB4_Msk                     (0x1UL << CAN_F7R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F7R2_FB4                         CAN_F7R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F7R2_FB5_Pos                     (5U)                              \n#define CAN_F7R2_FB5_Msk                     (0x1UL << CAN_F7R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F7R2_FB5                         CAN_F7R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F7R2_FB6_Pos                     (6U)                              \n#define CAN_F7R2_FB6_Msk                     (0x1UL << CAN_F7R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F7R2_FB6                         CAN_F7R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F7R2_FB7_Pos                     (7U)                              \n#define CAN_F7R2_FB7_Msk                     (0x1UL << CAN_F7R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F7R2_FB7                         CAN_F7R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F7R2_FB8_Pos                     (8U)                              \n#define CAN_F7R2_FB8_Msk                     (0x1UL << CAN_F7R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F7R2_FB8                         CAN_F7R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F7R2_FB9_Pos                     (9U)                              \n#define CAN_F7R2_FB9_Msk                     (0x1UL << CAN_F7R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F7R2_FB9                         CAN_F7R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F7R2_FB10_Pos                    (10U)                             \n#define CAN_F7R2_FB10_Msk                    (0x1UL << CAN_F7R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F7R2_FB10                        CAN_F7R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F7R2_FB11_Pos                    (11U)                             \n#define CAN_F7R2_FB11_Msk                    (0x1UL << CAN_F7R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F7R2_FB11                        CAN_F7R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F7R2_FB12_Pos                    (12U)                             \n#define CAN_F7R2_FB12_Msk                    (0x1UL << CAN_F7R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F7R2_FB12                        CAN_F7R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F7R2_FB13_Pos                    (13U)                             \n#define CAN_F7R2_FB13_Msk                    (0x1UL << CAN_F7R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F7R2_FB13                        CAN_F7R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F7R2_FB14_Pos                    (14U)                             \n#define CAN_F7R2_FB14_Msk                    (0x1UL << CAN_F7R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F7R2_FB14                        CAN_F7R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F7R2_FB15_Pos                    (15U)                             \n#define CAN_F7R2_FB15_Msk                    (0x1UL << CAN_F7R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F7R2_FB15                        CAN_F7R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F7R2_FB16_Pos                    (16U)                             \n#define CAN_F7R2_FB16_Msk                    (0x1UL << CAN_F7R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F7R2_FB16                        CAN_F7R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F7R2_FB17_Pos                    (17U)                             \n#define CAN_F7R2_FB17_Msk                    (0x1UL << CAN_F7R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F7R2_FB17                        CAN_F7R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F7R2_FB18_Pos                    (18U)                             \n#define CAN_F7R2_FB18_Msk                    (0x1UL << CAN_F7R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F7R2_FB18                        CAN_F7R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F7R2_FB19_Pos                    (19U)                             \n#define CAN_F7R2_FB19_Msk                    (0x1UL << CAN_F7R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F7R2_FB19                        CAN_F7R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F7R2_FB20_Pos                    (20U)                             \n#define CAN_F7R2_FB20_Msk                    (0x1UL << CAN_F7R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F7R2_FB20                        CAN_F7R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F7R2_FB21_Pos                    (21U)                             \n#define CAN_F7R2_FB21_Msk                    (0x1UL << CAN_F7R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F7R2_FB21                        CAN_F7R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F7R2_FB22_Pos                    (22U)                             \n#define CAN_F7R2_FB22_Msk                    (0x1UL << CAN_F7R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F7R2_FB22                        CAN_F7R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F7R2_FB23_Pos                    (23U)                             \n#define CAN_F7R2_FB23_Msk                    (0x1UL << CAN_F7R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F7R2_FB23                        CAN_F7R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F7R2_FB24_Pos                    (24U)                             \n#define CAN_F7R2_FB24_Msk                    (0x1UL << CAN_F7R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F7R2_FB24                        CAN_F7R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F7R2_FB25_Pos                    (25U)                             \n#define CAN_F7R2_FB25_Msk                    (0x1UL << CAN_F7R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F7R2_FB25                        CAN_F7R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F7R2_FB26_Pos                    (26U)                             \n#define CAN_F7R2_FB26_Msk                    (0x1UL << CAN_F7R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F7R2_FB26                        CAN_F7R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F7R2_FB27_Pos                    (27U)                             \n#define CAN_F7R2_FB27_Msk                    (0x1UL << CAN_F7R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F7R2_FB27                        CAN_F7R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F7R2_FB28_Pos                    (28U)                             \n#define CAN_F7R2_FB28_Msk                    (0x1UL << CAN_F7R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F7R2_FB28                        CAN_F7R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F7R2_FB29_Pos                    (29U)                             \n#define CAN_F7R2_FB29_Msk                    (0x1UL << CAN_F7R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F7R2_FB29                        CAN_F7R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F7R2_FB30_Pos                    (30U)                             \n#define CAN_F7R2_FB30_Msk                    (0x1UL << CAN_F7R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F7R2_FB30                        CAN_F7R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F7R2_FB31_Pos                    (31U)                             \n#define CAN_F7R2_FB31_Msk                    (0x1UL << CAN_F7R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F7R2_FB31                        CAN_F7R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F8R2 register  *******************/\n#define CAN_F8R2_FB0_Pos                     (0U)                              \n#define CAN_F8R2_FB0_Msk                     (0x1UL << CAN_F8R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F8R2_FB0                         CAN_F8R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F8R2_FB1_Pos                     (1U)                              \n#define CAN_F8R2_FB1_Msk                     (0x1UL << CAN_F8R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F8R2_FB1                         CAN_F8R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F8R2_FB2_Pos                     (2U)                              \n#define CAN_F8R2_FB2_Msk                     (0x1UL << CAN_F8R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F8R2_FB2                         CAN_F8R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F8R2_FB3_Pos                     (3U)                              \n#define CAN_F8R2_FB3_Msk                     (0x1UL << CAN_F8R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F8R2_FB3                         CAN_F8R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F8R2_FB4_Pos                     (4U)                              \n#define CAN_F8R2_FB4_Msk                     (0x1UL << CAN_F8R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F8R2_FB4                         CAN_F8R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F8R2_FB5_Pos                     (5U)                              \n#define CAN_F8R2_FB5_Msk                     (0x1UL << CAN_F8R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F8R2_FB5                         CAN_F8R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F8R2_FB6_Pos                     (6U)                              \n#define CAN_F8R2_FB6_Msk                     (0x1UL << CAN_F8R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F8R2_FB6                         CAN_F8R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F8R2_FB7_Pos                     (7U)                              \n#define CAN_F8R2_FB7_Msk                     (0x1UL << CAN_F8R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F8R2_FB7                         CAN_F8R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F8R2_FB8_Pos                     (8U)                              \n#define CAN_F8R2_FB8_Msk                     (0x1UL << CAN_F8R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F8R2_FB8                         CAN_F8R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F8R2_FB9_Pos                     (9U)                              \n#define CAN_F8R2_FB9_Msk                     (0x1UL << CAN_F8R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F8R2_FB9                         CAN_F8R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F8R2_FB10_Pos                    (10U)                             \n#define CAN_F8R2_FB10_Msk                    (0x1UL << CAN_F8R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F8R2_FB10                        CAN_F8R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F8R2_FB11_Pos                    (11U)                             \n#define CAN_F8R2_FB11_Msk                    (0x1UL << CAN_F8R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F8R2_FB11                        CAN_F8R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F8R2_FB12_Pos                    (12U)                             \n#define CAN_F8R2_FB12_Msk                    (0x1UL << CAN_F8R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F8R2_FB12                        CAN_F8R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F8R2_FB13_Pos                    (13U)                             \n#define CAN_F8R2_FB13_Msk                    (0x1UL << CAN_F8R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F8R2_FB13                        CAN_F8R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F8R2_FB14_Pos                    (14U)                             \n#define CAN_F8R2_FB14_Msk                    (0x1UL << CAN_F8R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F8R2_FB14                        CAN_F8R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F8R2_FB15_Pos                    (15U)                             \n#define CAN_F8R2_FB15_Msk                    (0x1UL << CAN_F8R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F8R2_FB15                        CAN_F8R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F8R2_FB16_Pos                    (16U)                             \n#define CAN_F8R2_FB16_Msk                    (0x1UL << CAN_F8R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F8R2_FB16                        CAN_F8R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F8R2_FB17_Pos                    (17U)                             \n#define CAN_F8R2_FB17_Msk                    (0x1UL << CAN_F8R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F8R2_FB17                        CAN_F8R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F8R2_FB18_Pos                    (18U)                             \n#define CAN_F8R2_FB18_Msk                    (0x1UL << CAN_F8R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F8R2_FB18                        CAN_F8R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F8R2_FB19_Pos                    (19U)                             \n#define CAN_F8R2_FB19_Msk                    (0x1UL << CAN_F8R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F8R2_FB19                        CAN_F8R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F8R2_FB20_Pos                    (20U)                             \n#define CAN_F8R2_FB20_Msk                    (0x1UL << CAN_F8R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F8R2_FB20                        CAN_F8R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F8R2_FB21_Pos                    (21U)                             \n#define CAN_F8R2_FB21_Msk                    (0x1UL << CAN_F8R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F8R2_FB21                        CAN_F8R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F8R2_FB22_Pos                    (22U)                             \n#define CAN_F8R2_FB22_Msk                    (0x1UL << CAN_F8R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F8R2_FB22                        CAN_F8R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F8R2_FB23_Pos                    (23U)                             \n#define CAN_F8R2_FB23_Msk                    (0x1UL << CAN_F8R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F8R2_FB23                        CAN_F8R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F8R2_FB24_Pos                    (24U)                             \n#define CAN_F8R2_FB24_Msk                    (0x1UL << CAN_F8R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F8R2_FB24                        CAN_F8R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F8R2_FB25_Pos                    (25U)                             \n#define CAN_F8R2_FB25_Msk                    (0x1UL << CAN_F8R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F8R2_FB25                        CAN_F8R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F8R2_FB26_Pos                    (26U)                             \n#define CAN_F8R2_FB26_Msk                    (0x1UL << CAN_F8R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F8R2_FB26                        CAN_F8R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F8R2_FB27_Pos                    (27U)                             \n#define CAN_F8R2_FB27_Msk                    (0x1UL << CAN_F8R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F8R2_FB27                        CAN_F8R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F8R2_FB28_Pos                    (28U)                             \n#define CAN_F8R2_FB28_Msk                    (0x1UL << CAN_F8R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F8R2_FB28                        CAN_F8R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F8R2_FB29_Pos                    (29U)                             \n#define CAN_F8R2_FB29_Msk                    (0x1UL << CAN_F8R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F8R2_FB29                        CAN_F8R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F8R2_FB30_Pos                    (30U)                             \n#define CAN_F8R2_FB30_Msk                    (0x1UL << CAN_F8R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F8R2_FB30                        CAN_F8R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F8R2_FB31_Pos                    (31U)                             \n#define CAN_F8R2_FB31_Msk                    (0x1UL << CAN_F8R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F8R2_FB31                        CAN_F8R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F9R2 register  *******************/\n#define CAN_F9R2_FB0_Pos                     (0U)                              \n#define CAN_F9R2_FB0_Msk                     (0x1UL << CAN_F9R2_FB0_Pos)        /*!< 0x00000001 */\n#define CAN_F9R2_FB0                         CAN_F9R2_FB0_Msk                  /*!< Filter bit 0 */\n#define CAN_F9R2_FB1_Pos                     (1U)                              \n#define CAN_F9R2_FB1_Msk                     (0x1UL << CAN_F9R2_FB1_Pos)        /*!< 0x00000002 */\n#define CAN_F9R2_FB1                         CAN_F9R2_FB1_Msk                  /*!< Filter bit 1 */\n#define CAN_F9R2_FB2_Pos                     (2U)                              \n#define CAN_F9R2_FB2_Msk                     (0x1UL << CAN_F9R2_FB2_Pos)        /*!< 0x00000004 */\n#define CAN_F9R2_FB2                         CAN_F9R2_FB2_Msk                  /*!< Filter bit 2 */\n#define CAN_F9R2_FB3_Pos                     (3U)                              \n#define CAN_F9R2_FB3_Msk                     (0x1UL << CAN_F9R2_FB3_Pos)        /*!< 0x00000008 */\n#define CAN_F9R2_FB3                         CAN_F9R2_FB3_Msk                  /*!< Filter bit 3 */\n#define CAN_F9R2_FB4_Pos                     (4U)                              \n#define CAN_F9R2_FB4_Msk                     (0x1UL << CAN_F9R2_FB4_Pos)        /*!< 0x00000010 */\n#define CAN_F9R2_FB4                         CAN_F9R2_FB4_Msk                  /*!< Filter bit 4 */\n#define CAN_F9R2_FB5_Pos                     (5U)                              \n#define CAN_F9R2_FB5_Msk                     (0x1UL << CAN_F9R2_FB5_Pos)        /*!< 0x00000020 */\n#define CAN_F9R2_FB5                         CAN_F9R2_FB5_Msk                  /*!< Filter bit 5 */\n#define CAN_F9R2_FB6_Pos                     (6U)                              \n#define CAN_F9R2_FB6_Msk                     (0x1UL << CAN_F9R2_FB6_Pos)        /*!< 0x00000040 */\n#define CAN_F9R2_FB6                         CAN_F9R2_FB6_Msk                  /*!< Filter bit 6 */\n#define CAN_F9R2_FB7_Pos                     (7U)                              \n#define CAN_F9R2_FB7_Msk                     (0x1UL << CAN_F9R2_FB7_Pos)        /*!< 0x00000080 */\n#define CAN_F9R2_FB7                         CAN_F9R2_FB7_Msk                  /*!< Filter bit 7 */\n#define CAN_F9R2_FB8_Pos                     (8U)                              \n#define CAN_F9R2_FB8_Msk                     (0x1UL << CAN_F9R2_FB8_Pos)        /*!< 0x00000100 */\n#define CAN_F9R2_FB8                         CAN_F9R2_FB8_Msk                  /*!< Filter bit 8 */\n#define CAN_F9R2_FB9_Pos                     (9U)                              \n#define CAN_F9R2_FB9_Msk                     (0x1UL << CAN_F9R2_FB9_Pos)        /*!< 0x00000200 */\n#define CAN_F9R2_FB9                         CAN_F9R2_FB9_Msk                  /*!< Filter bit 9 */\n#define CAN_F9R2_FB10_Pos                    (10U)                             \n#define CAN_F9R2_FB10_Msk                    (0x1UL << CAN_F9R2_FB10_Pos)       /*!< 0x00000400 */\n#define CAN_F9R2_FB10                        CAN_F9R2_FB10_Msk                 /*!< Filter bit 10 */\n#define CAN_F9R2_FB11_Pos                    (11U)                             \n#define CAN_F9R2_FB11_Msk                    (0x1UL << CAN_F9R2_FB11_Pos)       /*!< 0x00000800 */\n#define CAN_F9R2_FB11                        CAN_F9R2_FB11_Msk                 /*!< Filter bit 11 */\n#define CAN_F9R2_FB12_Pos                    (12U)                             \n#define CAN_F9R2_FB12_Msk                    (0x1UL << CAN_F9R2_FB12_Pos)       /*!< 0x00001000 */\n#define CAN_F9R2_FB12                        CAN_F9R2_FB12_Msk                 /*!< Filter bit 12 */\n#define CAN_F9R2_FB13_Pos                    (13U)                             \n#define CAN_F9R2_FB13_Msk                    (0x1UL << CAN_F9R2_FB13_Pos)       /*!< 0x00002000 */\n#define CAN_F9R2_FB13                        CAN_F9R2_FB13_Msk                 /*!< Filter bit 13 */\n#define CAN_F9R2_FB14_Pos                    (14U)                             \n#define CAN_F9R2_FB14_Msk                    (0x1UL << CAN_F9R2_FB14_Pos)       /*!< 0x00004000 */\n#define CAN_F9R2_FB14                        CAN_F9R2_FB14_Msk                 /*!< Filter bit 14 */\n#define CAN_F9R2_FB15_Pos                    (15U)                             \n#define CAN_F9R2_FB15_Msk                    (0x1UL << CAN_F9R2_FB15_Pos)       /*!< 0x00008000 */\n#define CAN_F9R2_FB15                        CAN_F9R2_FB15_Msk                 /*!< Filter bit 15 */\n#define CAN_F9R2_FB16_Pos                    (16U)                             \n#define CAN_F9R2_FB16_Msk                    (0x1UL << CAN_F9R2_FB16_Pos)       /*!< 0x00010000 */\n#define CAN_F9R2_FB16                        CAN_F9R2_FB16_Msk                 /*!< Filter bit 16 */\n#define CAN_F9R2_FB17_Pos                    (17U)                             \n#define CAN_F9R2_FB17_Msk                    (0x1UL << CAN_F9R2_FB17_Pos)       /*!< 0x00020000 */\n#define CAN_F9R2_FB17                        CAN_F9R2_FB17_Msk                 /*!< Filter bit 17 */\n#define CAN_F9R2_FB18_Pos                    (18U)                             \n#define CAN_F9R2_FB18_Msk                    (0x1UL << CAN_F9R2_FB18_Pos)       /*!< 0x00040000 */\n#define CAN_F9R2_FB18                        CAN_F9R2_FB18_Msk                 /*!< Filter bit 18 */\n#define CAN_F9R2_FB19_Pos                    (19U)                             \n#define CAN_F9R2_FB19_Msk                    (0x1UL << CAN_F9R2_FB19_Pos)       /*!< 0x00080000 */\n#define CAN_F9R2_FB19                        CAN_F9R2_FB19_Msk                 /*!< Filter bit 19 */\n#define CAN_F9R2_FB20_Pos                    (20U)                             \n#define CAN_F9R2_FB20_Msk                    (0x1UL << CAN_F9R2_FB20_Pos)       /*!< 0x00100000 */\n#define CAN_F9R2_FB20                        CAN_F9R2_FB20_Msk                 /*!< Filter bit 20 */\n#define CAN_F9R2_FB21_Pos                    (21U)                             \n#define CAN_F9R2_FB21_Msk                    (0x1UL << CAN_F9R2_FB21_Pos)       /*!< 0x00200000 */\n#define CAN_F9R2_FB21                        CAN_F9R2_FB21_Msk                 /*!< Filter bit 21 */\n#define CAN_F9R2_FB22_Pos                    (22U)                             \n#define CAN_F9R2_FB22_Msk                    (0x1UL << CAN_F9R2_FB22_Pos)       /*!< 0x00400000 */\n#define CAN_F9R2_FB22                        CAN_F9R2_FB22_Msk                 /*!< Filter bit 22 */\n#define CAN_F9R2_FB23_Pos                    (23U)                             \n#define CAN_F9R2_FB23_Msk                    (0x1UL << CAN_F9R2_FB23_Pos)       /*!< 0x00800000 */\n#define CAN_F9R2_FB23                        CAN_F9R2_FB23_Msk                 /*!< Filter bit 23 */\n#define CAN_F9R2_FB24_Pos                    (24U)                             \n#define CAN_F9R2_FB24_Msk                    (0x1UL << CAN_F9R2_FB24_Pos)       /*!< 0x01000000 */\n#define CAN_F9R2_FB24                        CAN_F9R2_FB24_Msk                 /*!< Filter bit 24 */\n#define CAN_F9R2_FB25_Pos                    (25U)                             \n#define CAN_F9R2_FB25_Msk                    (0x1UL << CAN_F9R2_FB25_Pos)       /*!< 0x02000000 */\n#define CAN_F9R2_FB25                        CAN_F9R2_FB25_Msk                 /*!< Filter bit 25 */\n#define CAN_F9R2_FB26_Pos                    (26U)                             \n#define CAN_F9R2_FB26_Msk                    (0x1UL << CAN_F9R2_FB26_Pos)       /*!< 0x04000000 */\n#define CAN_F9R2_FB26                        CAN_F9R2_FB26_Msk                 /*!< Filter bit 26 */\n#define CAN_F9R2_FB27_Pos                    (27U)                             \n#define CAN_F9R2_FB27_Msk                    (0x1UL << CAN_F9R2_FB27_Pos)       /*!< 0x08000000 */\n#define CAN_F9R2_FB27                        CAN_F9R2_FB27_Msk                 /*!< Filter bit 27 */\n#define CAN_F9R2_FB28_Pos                    (28U)                             \n#define CAN_F9R2_FB28_Msk                    (0x1UL << CAN_F9R2_FB28_Pos)       /*!< 0x10000000 */\n#define CAN_F9R2_FB28                        CAN_F9R2_FB28_Msk                 /*!< Filter bit 28 */\n#define CAN_F9R2_FB29_Pos                    (29U)                             \n#define CAN_F9R2_FB29_Msk                    (0x1UL << CAN_F9R2_FB29_Pos)       /*!< 0x20000000 */\n#define CAN_F9R2_FB29                        CAN_F9R2_FB29_Msk                 /*!< Filter bit 29 */\n#define CAN_F9R2_FB30_Pos                    (30U)                             \n#define CAN_F9R2_FB30_Msk                    (0x1UL << CAN_F9R2_FB30_Pos)       /*!< 0x40000000 */\n#define CAN_F9R2_FB30                        CAN_F9R2_FB30_Msk                 /*!< Filter bit 30 */\n#define CAN_F9R2_FB31_Pos                    (31U)                             \n#define CAN_F9R2_FB31_Msk                    (0x1UL << CAN_F9R2_FB31_Pos)       /*!< 0x80000000 */\n#define CAN_F9R2_FB31                        CAN_F9R2_FB31_Msk                 /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F10R2 register  ******************/\n#define CAN_F10R2_FB0_Pos                    (0U)                              \n#define CAN_F10R2_FB0_Msk                    (0x1UL << CAN_F10R2_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F10R2_FB0                        CAN_F10R2_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F10R2_FB1_Pos                    (1U)                              \n#define CAN_F10R2_FB1_Msk                    (0x1UL << CAN_F10R2_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F10R2_FB1                        CAN_F10R2_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F10R2_FB2_Pos                    (2U)                              \n#define CAN_F10R2_FB2_Msk                    (0x1UL << CAN_F10R2_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F10R2_FB2                        CAN_F10R2_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F10R2_FB3_Pos                    (3U)                              \n#define CAN_F10R2_FB3_Msk                    (0x1UL << CAN_F10R2_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F10R2_FB3                        CAN_F10R2_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F10R2_FB4_Pos                    (4U)                              \n#define CAN_F10R2_FB4_Msk                    (0x1UL << CAN_F10R2_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F10R2_FB4                        CAN_F10R2_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F10R2_FB5_Pos                    (5U)                              \n#define CAN_F10R2_FB5_Msk                    (0x1UL << CAN_F10R2_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F10R2_FB5                        CAN_F10R2_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F10R2_FB6_Pos                    (6U)                              \n#define CAN_F10R2_FB6_Msk                    (0x1UL << CAN_F10R2_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F10R2_FB6                        CAN_F10R2_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F10R2_FB7_Pos                    (7U)                              \n#define CAN_F10R2_FB7_Msk                    (0x1UL << CAN_F10R2_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F10R2_FB7                        CAN_F10R2_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F10R2_FB8_Pos                    (8U)                              \n#define CAN_F10R2_FB8_Msk                    (0x1UL << CAN_F10R2_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F10R2_FB8                        CAN_F10R2_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F10R2_FB9_Pos                    (9U)                              \n#define CAN_F10R2_FB9_Msk                    (0x1UL << CAN_F10R2_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F10R2_FB9                        CAN_F10R2_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F10R2_FB10_Pos                   (10U)                             \n#define CAN_F10R2_FB10_Msk                   (0x1UL << CAN_F10R2_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F10R2_FB10                       CAN_F10R2_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F10R2_FB11_Pos                   (11U)                             \n#define CAN_F10R2_FB11_Msk                   (0x1UL << CAN_F10R2_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F10R2_FB11                       CAN_F10R2_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F10R2_FB12_Pos                   (12U)                             \n#define CAN_F10R2_FB12_Msk                   (0x1UL << CAN_F10R2_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F10R2_FB12                       CAN_F10R2_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F10R2_FB13_Pos                   (13U)                             \n#define CAN_F10R2_FB13_Msk                   (0x1UL << CAN_F10R2_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F10R2_FB13                       CAN_F10R2_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F10R2_FB14_Pos                   (14U)                             \n#define CAN_F10R2_FB14_Msk                   (0x1UL << CAN_F10R2_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F10R2_FB14                       CAN_F10R2_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F10R2_FB15_Pos                   (15U)                             \n#define CAN_F10R2_FB15_Msk                   (0x1UL << CAN_F10R2_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F10R2_FB15                       CAN_F10R2_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F10R2_FB16_Pos                   (16U)                             \n#define CAN_F10R2_FB16_Msk                   (0x1UL << CAN_F10R2_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F10R2_FB16                       CAN_F10R2_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F10R2_FB17_Pos                   (17U)                             \n#define CAN_F10R2_FB17_Msk                   (0x1UL << CAN_F10R2_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F10R2_FB17                       CAN_F10R2_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F10R2_FB18_Pos                   (18U)                             \n#define CAN_F10R2_FB18_Msk                   (0x1UL << CAN_F10R2_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F10R2_FB18                       CAN_F10R2_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F10R2_FB19_Pos                   (19U)                             \n#define CAN_F10R2_FB19_Msk                   (0x1UL << CAN_F10R2_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F10R2_FB19                       CAN_F10R2_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F10R2_FB20_Pos                   (20U)                             \n#define CAN_F10R2_FB20_Msk                   (0x1UL << CAN_F10R2_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F10R2_FB20                       CAN_F10R2_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F10R2_FB21_Pos                   (21U)                             \n#define CAN_F10R2_FB21_Msk                   (0x1UL << CAN_F10R2_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F10R2_FB21                       CAN_F10R2_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F10R2_FB22_Pos                   (22U)                             \n#define CAN_F10R2_FB22_Msk                   (0x1UL << CAN_F10R2_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F10R2_FB22                       CAN_F10R2_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F10R2_FB23_Pos                   (23U)                             \n#define CAN_F10R2_FB23_Msk                   (0x1UL << CAN_F10R2_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F10R2_FB23                       CAN_F10R2_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F10R2_FB24_Pos                   (24U)                             \n#define CAN_F10R2_FB24_Msk                   (0x1UL << CAN_F10R2_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F10R2_FB24                       CAN_F10R2_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F10R2_FB25_Pos                   (25U)                             \n#define CAN_F10R2_FB25_Msk                   (0x1UL << CAN_F10R2_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F10R2_FB25                       CAN_F10R2_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F10R2_FB26_Pos                   (26U)                             \n#define CAN_F10R2_FB26_Msk                   (0x1UL << CAN_F10R2_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F10R2_FB26                       CAN_F10R2_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F10R2_FB27_Pos                   (27U)                             \n#define CAN_F10R2_FB27_Msk                   (0x1UL << CAN_F10R2_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F10R2_FB27                       CAN_F10R2_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F10R2_FB28_Pos                   (28U)                             \n#define CAN_F10R2_FB28_Msk                   (0x1UL << CAN_F10R2_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F10R2_FB28                       CAN_F10R2_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F10R2_FB29_Pos                   (29U)                             \n#define CAN_F10R2_FB29_Msk                   (0x1UL << CAN_F10R2_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F10R2_FB29                       CAN_F10R2_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F10R2_FB30_Pos                   (30U)                             \n#define CAN_F10R2_FB30_Msk                   (0x1UL << CAN_F10R2_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F10R2_FB30                       CAN_F10R2_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F10R2_FB31_Pos                   (31U)                             \n#define CAN_F10R2_FB31_Msk                   (0x1UL << CAN_F10R2_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F10R2_FB31                       CAN_F10R2_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F11R2 register  ******************/\n#define CAN_F11R2_FB0_Pos                    (0U)                              \n#define CAN_F11R2_FB0_Msk                    (0x1UL << CAN_F11R2_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F11R2_FB0                        CAN_F11R2_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F11R2_FB1_Pos                    (1U)                              \n#define CAN_F11R2_FB1_Msk                    (0x1UL << CAN_F11R2_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F11R2_FB1                        CAN_F11R2_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F11R2_FB2_Pos                    (2U)                              \n#define CAN_F11R2_FB2_Msk                    (0x1UL << CAN_F11R2_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F11R2_FB2                        CAN_F11R2_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F11R2_FB3_Pos                    (3U)                              \n#define CAN_F11R2_FB3_Msk                    (0x1UL << CAN_F11R2_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F11R2_FB3                        CAN_F11R2_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F11R2_FB4_Pos                    (4U)                              \n#define CAN_F11R2_FB4_Msk                    (0x1UL << CAN_F11R2_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F11R2_FB4                        CAN_F11R2_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F11R2_FB5_Pos                    (5U)                              \n#define CAN_F11R2_FB5_Msk                    (0x1UL << CAN_F11R2_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F11R2_FB5                        CAN_F11R2_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F11R2_FB6_Pos                    (6U)                              \n#define CAN_F11R2_FB6_Msk                    (0x1UL << CAN_F11R2_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F11R2_FB6                        CAN_F11R2_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F11R2_FB7_Pos                    (7U)                              \n#define CAN_F11R2_FB7_Msk                    (0x1UL << CAN_F11R2_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F11R2_FB7                        CAN_F11R2_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F11R2_FB8_Pos                    (8U)                              \n#define CAN_F11R2_FB8_Msk                    (0x1UL << CAN_F11R2_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F11R2_FB8                        CAN_F11R2_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F11R2_FB9_Pos                    (9U)                              \n#define CAN_F11R2_FB9_Msk                    (0x1UL << CAN_F11R2_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F11R2_FB9                        CAN_F11R2_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F11R2_FB10_Pos                   (10U)                             \n#define CAN_F11R2_FB10_Msk                   (0x1UL << CAN_F11R2_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F11R2_FB10                       CAN_F11R2_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F11R2_FB11_Pos                   (11U)                             \n#define CAN_F11R2_FB11_Msk                   (0x1UL << CAN_F11R2_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F11R2_FB11                       CAN_F11R2_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F11R2_FB12_Pos                   (12U)                             \n#define CAN_F11R2_FB12_Msk                   (0x1UL << CAN_F11R2_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F11R2_FB12                       CAN_F11R2_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F11R2_FB13_Pos                   (13U)                             \n#define CAN_F11R2_FB13_Msk                   (0x1UL << CAN_F11R2_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F11R2_FB13                       CAN_F11R2_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F11R2_FB14_Pos                   (14U)                             \n#define CAN_F11R2_FB14_Msk                   (0x1UL << CAN_F11R2_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F11R2_FB14                       CAN_F11R2_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F11R2_FB15_Pos                   (15U)                             \n#define CAN_F11R2_FB15_Msk                   (0x1UL << CAN_F11R2_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F11R2_FB15                       CAN_F11R2_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F11R2_FB16_Pos                   (16U)                             \n#define CAN_F11R2_FB16_Msk                   (0x1UL << CAN_F11R2_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F11R2_FB16                       CAN_F11R2_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F11R2_FB17_Pos                   (17U)                             \n#define CAN_F11R2_FB17_Msk                   (0x1UL << CAN_F11R2_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F11R2_FB17                       CAN_F11R2_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F11R2_FB18_Pos                   (18U)                             \n#define CAN_F11R2_FB18_Msk                   (0x1UL << CAN_F11R2_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F11R2_FB18                       CAN_F11R2_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F11R2_FB19_Pos                   (19U)                             \n#define CAN_F11R2_FB19_Msk                   (0x1UL << CAN_F11R2_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F11R2_FB19                       CAN_F11R2_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F11R2_FB20_Pos                   (20U)                             \n#define CAN_F11R2_FB20_Msk                   (0x1UL << CAN_F11R2_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F11R2_FB20                       CAN_F11R2_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F11R2_FB21_Pos                   (21U)                             \n#define CAN_F11R2_FB21_Msk                   (0x1UL << CAN_F11R2_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F11R2_FB21                       CAN_F11R2_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F11R2_FB22_Pos                   (22U)                             \n#define CAN_F11R2_FB22_Msk                   (0x1UL << CAN_F11R2_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F11R2_FB22                       CAN_F11R2_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F11R2_FB23_Pos                   (23U)                             \n#define CAN_F11R2_FB23_Msk                   (0x1UL << CAN_F11R2_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F11R2_FB23                       CAN_F11R2_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F11R2_FB24_Pos                   (24U)                             \n#define CAN_F11R2_FB24_Msk                   (0x1UL << CAN_F11R2_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F11R2_FB24                       CAN_F11R2_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F11R2_FB25_Pos                   (25U)                             \n#define CAN_F11R2_FB25_Msk                   (0x1UL << CAN_F11R2_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F11R2_FB25                       CAN_F11R2_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F11R2_FB26_Pos                   (26U)                             \n#define CAN_F11R2_FB26_Msk                   (0x1UL << CAN_F11R2_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F11R2_FB26                       CAN_F11R2_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F11R2_FB27_Pos                   (27U)                             \n#define CAN_F11R2_FB27_Msk                   (0x1UL << CAN_F11R2_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F11R2_FB27                       CAN_F11R2_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F11R2_FB28_Pos                   (28U)                             \n#define CAN_F11R2_FB28_Msk                   (0x1UL << CAN_F11R2_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F11R2_FB28                       CAN_F11R2_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F11R2_FB29_Pos                   (29U)                             \n#define CAN_F11R2_FB29_Msk                   (0x1UL << CAN_F11R2_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F11R2_FB29                       CAN_F11R2_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F11R2_FB30_Pos                   (30U)                             \n#define CAN_F11R2_FB30_Msk                   (0x1UL << CAN_F11R2_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F11R2_FB30                       CAN_F11R2_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F11R2_FB31_Pos                   (31U)                             \n#define CAN_F11R2_FB31_Msk                   (0x1UL << CAN_F11R2_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F11R2_FB31                       CAN_F11R2_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F12R2 register  ******************/\n#define CAN_F12R2_FB0_Pos                    (0U)                              \n#define CAN_F12R2_FB0_Msk                    (0x1UL << CAN_F12R2_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F12R2_FB0                        CAN_F12R2_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F12R2_FB1_Pos                    (1U)                              \n#define CAN_F12R2_FB1_Msk                    (0x1UL << CAN_F12R2_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F12R2_FB1                        CAN_F12R2_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F12R2_FB2_Pos                    (2U)                              \n#define CAN_F12R2_FB2_Msk                    (0x1UL << CAN_F12R2_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F12R2_FB2                        CAN_F12R2_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F12R2_FB3_Pos                    (3U)                              \n#define CAN_F12R2_FB3_Msk                    (0x1UL << CAN_F12R2_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F12R2_FB3                        CAN_F12R2_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F12R2_FB4_Pos                    (4U)                              \n#define CAN_F12R2_FB4_Msk                    (0x1UL << CAN_F12R2_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F12R2_FB4                        CAN_F12R2_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F12R2_FB5_Pos                    (5U)                              \n#define CAN_F12R2_FB5_Msk                    (0x1UL << CAN_F12R2_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F12R2_FB5                        CAN_F12R2_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F12R2_FB6_Pos                    (6U)                              \n#define CAN_F12R2_FB6_Msk                    (0x1UL << CAN_F12R2_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F12R2_FB6                        CAN_F12R2_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F12R2_FB7_Pos                    (7U)                              \n#define CAN_F12R2_FB7_Msk                    (0x1UL << CAN_F12R2_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F12R2_FB7                        CAN_F12R2_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F12R2_FB8_Pos                    (8U)                              \n#define CAN_F12R2_FB8_Msk                    (0x1UL << CAN_F12R2_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F12R2_FB8                        CAN_F12R2_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F12R2_FB9_Pos                    (9U)                              \n#define CAN_F12R2_FB9_Msk                    (0x1UL << CAN_F12R2_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F12R2_FB9                        CAN_F12R2_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F12R2_FB10_Pos                   (10U)                             \n#define CAN_F12R2_FB10_Msk                   (0x1UL << CAN_F12R2_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F12R2_FB10                       CAN_F12R2_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F12R2_FB11_Pos                   (11U)                             \n#define CAN_F12R2_FB11_Msk                   (0x1UL << CAN_F12R2_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F12R2_FB11                       CAN_F12R2_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F12R2_FB12_Pos                   (12U)                             \n#define CAN_F12R2_FB12_Msk                   (0x1UL << CAN_F12R2_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F12R2_FB12                       CAN_F12R2_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F12R2_FB13_Pos                   (13U)                             \n#define CAN_F12R2_FB13_Msk                   (0x1UL << CAN_F12R2_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F12R2_FB13                       CAN_F12R2_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F12R2_FB14_Pos                   (14U)                             \n#define CAN_F12R2_FB14_Msk                   (0x1UL << CAN_F12R2_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F12R2_FB14                       CAN_F12R2_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F12R2_FB15_Pos                   (15U)                             \n#define CAN_F12R2_FB15_Msk                   (0x1UL << CAN_F12R2_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F12R2_FB15                       CAN_F12R2_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F12R2_FB16_Pos                   (16U)                             \n#define CAN_F12R2_FB16_Msk                   (0x1UL << CAN_F12R2_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F12R2_FB16                       CAN_F12R2_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F12R2_FB17_Pos                   (17U)                             \n#define CAN_F12R2_FB17_Msk                   (0x1UL << CAN_F12R2_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F12R2_FB17                       CAN_F12R2_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F12R2_FB18_Pos                   (18U)                             \n#define CAN_F12R2_FB18_Msk                   (0x1UL << CAN_F12R2_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F12R2_FB18                       CAN_F12R2_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F12R2_FB19_Pos                   (19U)                             \n#define CAN_F12R2_FB19_Msk                   (0x1UL << CAN_F12R2_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F12R2_FB19                       CAN_F12R2_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F12R2_FB20_Pos                   (20U)                             \n#define CAN_F12R2_FB20_Msk                   (0x1UL << CAN_F12R2_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F12R2_FB20                       CAN_F12R2_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F12R2_FB21_Pos                   (21U)                             \n#define CAN_F12R2_FB21_Msk                   (0x1UL << CAN_F12R2_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F12R2_FB21                       CAN_F12R2_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F12R2_FB22_Pos                   (22U)                             \n#define CAN_F12R2_FB22_Msk                   (0x1UL << CAN_F12R2_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F12R2_FB22                       CAN_F12R2_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F12R2_FB23_Pos                   (23U)                             \n#define CAN_F12R2_FB23_Msk                   (0x1UL << CAN_F12R2_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F12R2_FB23                       CAN_F12R2_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F12R2_FB24_Pos                   (24U)                             \n#define CAN_F12R2_FB24_Msk                   (0x1UL << CAN_F12R2_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F12R2_FB24                       CAN_F12R2_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F12R2_FB25_Pos                   (25U)                             \n#define CAN_F12R2_FB25_Msk                   (0x1UL << CAN_F12R2_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F12R2_FB25                       CAN_F12R2_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F12R2_FB26_Pos                   (26U)                             \n#define CAN_F12R2_FB26_Msk                   (0x1UL << CAN_F12R2_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F12R2_FB26                       CAN_F12R2_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F12R2_FB27_Pos                   (27U)                             \n#define CAN_F12R2_FB27_Msk                   (0x1UL << CAN_F12R2_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F12R2_FB27                       CAN_F12R2_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F12R2_FB28_Pos                   (28U)                             \n#define CAN_F12R2_FB28_Msk                   (0x1UL << CAN_F12R2_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F12R2_FB28                       CAN_F12R2_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F12R2_FB29_Pos                   (29U)                             \n#define CAN_F12R2_FB29_Msk                   (0x1UL << CAN_F12R2_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F12R2_FB29                       CAN_F12R2_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F12R2_FB30_Pos                   (30U)                             \n#define CAN_F12R2_FB30_Msk                   (0x1UL << CAN_F12R2_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F12R2_FB30                       CAN_F12R2_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F12R2_FB31_Pos                   (31U)                             \n#define CAN_F12R2_FB31_Msk                   (0x1UL << CAN_F12R2_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F12R2_FB31                       CAN_F12R2_FB31_Msk                /*!< Filter bit 31 */\n\n/*******************  Bit definition for CAN_F13R2 register  ******************/\n#define CAN_F13R2_FB0_Pos                    (0U)                              \n#define CAN_F13R2_FB0_Msk                    (0x1UL << CAN_F13R2_FB0_Pos)       /*!< 0x00000001 */\n#define CAN_F13R2_FB0                        CAN_F13R2_FB0_Msk                 /*!< Filter bit 0 */\n#define CAN_F13R2_FB1_Pos                    (1U)                              \n#define CAN_F13R2_FB1_Msk                    (0x1UL << CAN_F13R2_FB1_Pos)       /*!< 0x00000002 */\n#define CAN_F13R2_FB1                        CAN_F13R2_FB1_Msk                 /*!< Filter bit 1 */\n#define CAN_F13R2_FB2_Pos                    (2U)                              \n#define CAN_F13R2_FB2_Msk                    (0x1UL << CAN_F13R2_FB2_Pos)       /*!< 0x00000004 */\n#define CAN_F13R2_FB2                        CAN_F13R2_FB2_Msk                 /*!< Filter bit 2 */\n#define CAN_F13R2_FB3_Pos                    (3U)                              \n#define CAN_F13R2_FB3_Msk                    (0x1UL << CAN_F13R2_FB3_Pos)       /*!< 0x00000008 */\n#define CAN_F13R2_FB3                        CAN_F13R2_FB3_Msk                 /*!< Filter bit 3 */\n#define CAN_F13R2_FB4_Pos                    (4U)                              \n#define CAN_F13R2_FB4_Msk                    (0x1UL << CAN_F13R2_FB4_Pos)       /*!< 0x00000010 */\n#define CAN_F13R2_FB4                        CAN_F13R2_FB4_Msk                 /*!< Filter bit 4 */\n#define CAN_F13R2_FB5_Pos                    (5U)                              \n#define CAN_F13R2_FB5_Msk                    (0x1UL << CAN_F13R2_FB5_Pos)       /*!< 0x00000020 */\n#define CAN_F13R2_FB5                        CAN_F13R2_FB5_Msk                 /*!< Filter bit 5 */\n#define CAN_F13R2_FB6_Pos                    (6U)                              \n#define CAN_F13R2_FB6_Msk                    (0x1UL << CAN_F13R2_FB6_Pos)       /*!< 0x00000040 */\n#define CAN_F13R2_FB6                        CAN_F13R2_FB6_Msk                 /*!< Filter bit 6 */\n#define CAN_F13R2_FB7_Pos                    (7U)                              \n#define CAN_F13R2_FB7_Msk                    (0x1UL << CAN_F13R2_FB7_Pos)       /*!< 0x00000080 */\n#define CAN_F13R2_FB7                        CAN_F13R2_FB7_Msk                 /*!< Filter bit 7 */\n#define CAN_F13R2_FB8_Pos                    (8U)                              \n#define CAN_F13R2_FB8_Msk                    (0x1UL << CAN_F13R2_FB8_Pos)       /*!< 0x00000100 */\n#define CAN_F13R2_FB8                        CAN_F13R2_FB8_Msk                 /*!< Filter bit 8 */\n#define CAN_F13R2_FB9_Pos                    (9U)                              \n#define CAN_F13R2_FB9_Msk                    (0x1UL << CAN_F13R2_FB9_Pos)       /*!< 0x00000200 */\n#define CAN_F13R2_FB9                        CAN_F13R2_FB9_Msk                 /*!< Filter bit 9 */\n#define CAN_F13R2_FB10_Pos                   (10U)                             \n#define CAN_F13R2_FB10_Msk                   (0x1UL << CAN_F13R2_FB10_Pos)      /*!< 0x00000400 */\n#define CAN_F13R2_FB10                       CAN_F13R2_FB10_Msk                /*!< Filter bit 10 */\n#define CAN_F13R2_FB11_Pos                   (11U)                             \n#define CAN_F13R2_FB11_Msk                   (0x1UL << CAN_F13R2_FB11_Pos)      /*!< 0x00000800 */\n#define CAN_F13R2_FB11                       CAN_F13R2_FB11_Msk                /*!< Filter bit 11 */\n#define CAN_F13R2_FB12_Pos                   (12U)                             \n#define CAN_F13R2_FB12_Msk                   (0x1UL << CAN_F13R2_FB12_Pos)      /*!< 0x00001000 */\n#define CAN_F13R2_FB12                       CAN_F13R2_FB12_Msk                /*!< Filter bit 12 */\n#define CAN_F13R2_FB13_Pos                   (13U)                             \n#define CAN_F13R2_FB13_Msk                   (0x1UL << CAN_F13R2_FB13_Pos)      /*!< 0x00002000 */\n#define CAN_F13R2_FB13                       CAN_F13R2_FB13_Msk                /*!< Filter bit 13 */\n#define CAN_F13R2_FB14_Pos                   (14U)                             \n#define CAN_F13R2_FB14_Msk                   (0x1UL << CAN_F13R2_FB14_Pos)      /*!< 0x00004000 */\n#define CAN_F13R2_FB14                       CAN_F13R2_FB14_Msk                /*!< Filter bit 14 */\n#define CAN_F13R2_FB15_Pos                   (15U)                             \n#define CAN_F13R2_FB15_Msk                   (0x1UL << CAN_F13R2_FB15_Pos)      /*!< 0x00008000 */\n#define CAN_F13R2_FB15                       CAN_F13R2_FB15_Msk                /*!< Filter bit 15 */\n#define CAN_F13R2_FB16_Pos                   (16U)                             \n#define CAN_F13R2_FB16_Msk                   (0x1UL << CAN_F13R2_FB16_Pos)      /*!< 0x00010000 */\n#define CAN_F13R2_FB16                       CAN_F13R2_FB16_Msk                /*!< Filter bit 16 */\n#define CAN_F13R2_FB17_Pos                   (17U)                             \n#define CAN_F13R2_FB17_Msk                   (0x1UL << CAN_F13R2_FB17_Pos)      /*!< 0x00020000 */\n#define CAN_F13R2_FB17                       CAN_F13R2_FB17_Msk                /*!< Filter bit 17 */\n#define CAN_F13R2_FB18_Pos                   (18U)                             \n#define CAN_F13R2_FB18_Msk                   (0x1UL << CAN_F13R2_FB18_Pos)      /*!< 0x00040000 */\n#define CAN_F13R2_FB18                       CAN_F13R2_FB18_Msk                /*!< Filter bit 18 */\n#define CAN_F13R2_FB19_Pos                   (19U)                             \n#define CAN_F13R2_FB19_Msk                   (0x1UL << CAN_F13R2_FB19_Pos)      /*!< 0x00080000 */\n#define CAN_F13R2_FB19                       CAN_F13R2_FB19_Msk                /*!< Filter bit 19 */\n#define CAN_F13R2_FB20_Pos                   (20U)                             \n#define CAN_F13R2_FB20_Msk                   (0x1UL << CAN_F13R2_FB20_Pos)      /*!< 0x00100000 */\n#define CAN_F13R2_FB20                       CAN_F13R2_FB20_Msk                /*!< Filter bit 20 */\n#define CAN_F13R2_FB21_Pos                   (21U)                             \n#define CAN_F13R2_FB21_Msk                   (0x1UL << CAN_F13R2_FB21_Pos)      /*!< 0x00200000 */\n#define CAN_F13R2_FB21                       CAN_F13R2_FB21_Msk                /*!< Filter bit 21 */\n#define CAN_F13R2_FB22_Pos                   (22U)                             \n#define CAN_F13R2_FB22_Msk                   (0x1UL << CAN_F13R2_FB22_Pos)      /*!< 0x00400000 */\n#define CAN_F13R2_FB22                       CAN_F13R2_FB22_Msk                /*!< Filter bit 22 */\n#define CAN_F13R2_FB23_Pos                   (23U)                             \n#define CAN_F13R2_FB23_Msk                   (0x1UL << CAN_F13R2_FB23_Pos)      /*!< 0x00800000 */\n#define CAN_F13R2_FB23                       CAN_F13R2_FB23_Msk                /*!< Filter bit 23 */\n#define CAN_F13R2_FB24_Pos                   (24U)                             \n#define CAN_F13R2_FB24_Msk                   (0x1UL << CAN_F13R2_FB24_Pos)      /*!< 0x01000000 */\n#define CAN_F13R2_FB24                       CAN_F13R2_FB24_Msk                /*!< Filter bit 24 */\n#define CAN_F13R2_FB25_Pos                   (25U)                             \n#define CAN_F13R2_FB25_Msk                   (0x1UL << CAN_F13R2_FB25_Pos)      /*!< 0x02000000 */\n#define CAN_F13R2_FB25                       CAN_F13R2_FB25_Msk                /*!< Filter bit 25 */\n#define CAN_F13R2_FB26_Pos                   (26U)                             \n#define CAN_F13R2_FB26_Msk                   (0x1UL << CAN_F13R2_FB26_Pos)      /*!< 0x04000000 */\n#define CAN_F13R2_FB26                       CAN_F13R2_FB26_Msk                /*!< Filter bit 26 */\n#define CAN_F13R2_FB27_Pos                   (27U)                             \n#define CAN_F13R2_FB27_Msk                   (0x1UL << CAN_F13R2_FB27_Pos)      /*!< 0x08000000 */\n#define CAN_F13R2_FB27                       CAN_F13R2_FB27_Msk                /*!< Filter bit 27 */\n#define CAN_F13R2_FB28_Pos                   (28U)                             \n#define CAN_F13R2_FB28_Msk                   (0x1UL << CAN_F13R2_FB28_Pos)      /*!< 0x10000000 */\n#define CAN_F13R2_FB28                       CAN_F13R2_FB28_Msk                /*!< Filter bit 28 */\n#define CAN_F13R2_FB29_Pos                   (29U)                             \n#define CAN_F13R2_FB29_Msk                   (0x1UL << CAN_F13R2_FB29_Pos)      /*!< 0x20000000 */\n#define CAN_F13R2_FB29                       CAN_F13R2_FB29_Msk                /*!< Filter bit 29 */\n#define CAN_F13R2_FB30_Pos                   (30U)                             \n#define CAN_F13R2_FB30_Msk                   (0x1UL << CAN_F13R2_FB30_Pos)      /*!< 0x40000000 */\n#define CAN_F13R2_FB30                       CAN_F13R2_FB30_Msk                /*!< Filter bit 30 */\n#define CAN_F13R2_FB31_Pos                   (31U)                             \n#define CAN_F13R2_FB31_Msk                   (0x1UL << CAN_F13R2_FB31_Pos)      /*!< 0x80000000 */\n#define CAN_F13R2_FB31                       CAN_F13R2_FB31_Msk                /*!< Filter bit 31 */\n\n/******************************************************************************/\n/*                                                                            */\n/*                        Serial Peripheral Interface                         */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for SPI_CR1 register  ********************/\n#define SPI_CR1_CPHA_Pos                    (0U)                               \n#define SPI_CR1_CPHA_Msk                    (0x1UL << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */\n#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */\n#define SPI_CR1_CPOL_Pos                    (1U)                               \n#define SPI_CR1_CPOL_Msk                    (0x1UL << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */\n#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */\n#define SPI_CR1_MSTR_Pos                    (2U)                               \n#define SPI_CR1_MSTR_Msk                    (0x1UL << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */\n#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */\n\n#define SPI_CR1_BR_Pos                      (3U)                               \n#define SPI_CR1_BR_Msk                      (0x7UL << SPI_CR1_BR_Pos)           /*!< 0x00000038 */\n#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */\n#define SPI_CR1_BR_0                        (0x1UL << SPI_CR1_BR_Pos)           /*!< 0x00000008 */\n#define SPI_CR1_BR_1                        (0x2UL << SPI_CR1_BR_Pos)           /*!< 0x00000010 */\n#define SPI_CR1_BR_2                        (0x4UL << SPI_CR1_BR_Pos)           /*!< 0x00000020 */\n\n#define SPI_CR1_SPE_Pos                     (6U)                               \n#define SPI_CR1_SPE_Msk                     (0x1UL << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */\n#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */\n#define SPI_CR1_LSBFIRST_Pos                (7U)                               \n#define SPI_CR1_LSBFIRST_Msk                (0x1UL << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */\n#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */\n#define SPI_CR1_SSI_Pos                     (8U)                               \n#define SPI_CR1_SSI_Msk                     (0x1UL << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */\n#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */\n#define SPI_CR1_SSM_Pos                     (9U)                               \n#define SPI_CR1_SSM_Msk                     (0x1UL << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */\n#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */\n#define SPI_CR1_RXONLY_Pos                  (10U)                              \n#define SPI_CR1_RXONLY_Msk                  (0x1UL << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */\n#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */\n#define SPI_CR1_DFF_Pos                     (11U)                              \n#define SPI_CR1_DFF_Msk                     (0x1UL << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */\n#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */\n#define SPI_CR1_CRCNEXT_Pos                 (12U)                              \n#define SPI_CR1_CRCNEXT_Msk                 (0x1UL << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */\n#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */\n#define SPI_CR1_CRCEN_Pos                   (13U)                              \n#define SPI_CR1_CRCEN_Msk                   (0x1UL << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */\n#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */\n#define SPI_CR1_BIDIOE_Pos                  (14U)                              \n#define SPI_CR1_BIDIOE_Msk                  (0x1UL << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */\n#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */\n#define SPI_CR1_BIDIMODE_Pos                (15U)                              \n#define SPI_CR1_BIDIMODE_Msk                (0x1UL << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */\n#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */\n\n/*******************  Bit definition for SPI_CR2 register  ********************/\n#define SPI_CR2_RXDMAEN_Pos                 (0U)                               \n#define SPI_CR2_RXDMAEN_Msk                 (0x1UL << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */\n#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */\n#define SPI_CR2_TXDMAEN_Pos                 (1U)                               \n#define SPI_CR2_TXDMAEN_Msk                 (0x1UL << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */\n#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */\n#define SPI_CR2_SSOE_Pos                    (2U)                               \n#define SPI_CR2_SSOE_Msk                    (0x1UL << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */\n#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */\n#define SPI_CR2_ERRIE_Pos                   (5U)                               \n#define SPI_CR2_ERRIE_Msk                   (0x1UL << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */\n#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */\n#define SPI_CR2_RXNEIE_Pos                  (6U)                               \n#define SPI_CR2_RXNEIE_Msk                  (0x1UL << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */\n#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */\n#define SPI_CR2_TXEIE_Pos                   (7U)                               \n#define SPI_CR2_TXEIE_Msk                   (0x1UL << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */\n#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */\n\n/********************  Bit definition for SPI_SR register  ********************/\n#define SPI_SR_RXNE_Pos                     (0U)                               \n#define SPI_SR_RXNE_Msk                     (0x1UL << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */\n#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */\n#define SPI_SR_TXE_Pos                      (1U)                               \n#define SPI_SR_TXE_Msk                      (0x1UL << SPI_SR_TXE_Pos)           /*!< 0x00000002 */\n#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */\n#define SPI_SR_CHSIDE_Pos                   (2U)                               \n#define SPI_SR_CHSIDE_Msk                   (0x1UL << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */\n#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */\n#define SPI_SR_UDR_Pos                      (3U)                               \n#define SPI_SR_UDR_Msk                      (0x1UL << SPI_SR_UDR_Pos)           /*!< 0x00000008 */\n#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */\n#define SPI_SR_CRCERR_Pos                   (4U)                               \n#define SPI_SR_CRCERR_Msk                   (0x1UL << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */\n#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */\n#define SPI_SR_MODF_Pos                     (5U)                               \n#define SPI_SR_MODF_Msk                     (0x1UL << SPI_SR_MODF_Pos)          /*!< 0x00000020 */\n#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */\n#define SPI_SR_OVR_Pos                      (6U)                               \n#define SPI_SR_OVR_Msk                      (0x1UL << SPI_SR_OVR_Pos)           /*!< 0x00000040 */\n#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */\n#define SPI_SR_BSY_Pos                      (7U)                               \n#define SPI_SR_BSY_Msk                      (0x1UL << SPI_SR_BSY_Pos)           /*!< 0x00000080 */\n#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */\n\n/********************  Bit definition for SPI_DR register  ********************/\n#define SPI_DR_DR_Pos                       (0U)                               \n#define SPI_DR_DR_Msk                       (0xFFFFUL << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */\n#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */\n\n/*******************  Bit definition for SPI_CRCPR register  ******************/\n#define SPI_CRCPR_CRCPOLY_Pos               (0U)                               \n#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */\n#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */\n\n/******************  Bit definition for SPI_RXCRCR register  ******************/\n#define SPI_RXCRCR_RXCRC_Pos                (0U)                               \n#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */\n#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */\n\n/******************  Bit definition for SPI_TXCRCR register  ******************/\n#define SPI_TXCRCR_TXCRC_Pos                (0U)                               \n#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */\n#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */\n\n#define SPI_I2SCFGR_I2SMOD_Pos              (11U)                              \n#define SPI_I2SCFGR_I2SMOD_Msk              (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */\n#define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!< I2S mode selection */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      Inter-integrated Circuit Interface                    */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for I2C_CR1 register  ********************/\n#define I2C_CR1_PE_Pos                      (0U)                               \n#define I2C_CR1_PE_Msk                      (0x1UL << I2C_CR1_PE_Pos)           /*!< 0x00000001 */\n#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */\n#define I2C_CR1_SMBUS_Pos                   (1U)                               \n#define I2C_CR1_SMBUS_Msk                   (0x1UL << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */\n#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */\n#define I2C_CR1_SMBTYPE_Pos                 (3U)                               \n#define I2C_CR1_SMBTYPE_Msk                 (0x1UL << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */\n#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */\n#define I2C_CR1_ENARP_Pos                   (4U)                               \n#define I2C_CR1_ENARP_Msk                   (0x1UL << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */\n#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */\n#define I2C_CR1_ENPEC_Pos                   (5U)                               \n#define I2C_CR1_ENPEC_Msk                   (0x1UL << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */\n#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */\n#define I2C_CR1_ENGC_Pos                    (6U)                               \n#define I2C_CR1_ENGC_Msk                    (0x1UL << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */\n#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */\n#define I2C_CR1_NOSTRETCH_Pos               (7U)                               \n#define I2C_CR1_NOSTRETCH_Msk               (0x1UL << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */\n#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */\n#define I2C_CR1_START_Pos                   (8U)                               \n#define I2C_CR1_START_Msk                   (0x1UL << I2C_CR1_START_Pos)        /*!< 0x00000100 */\n#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */\n#define I2C_CR1_STOP_Pos                    (9U)                               \n#define I2C_CR1_STOP_Msk                    (0x1UL << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */\n#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */\n#define I2C_CR1_ACK_Pos                     (10U)                              \n#define I2C_CR1_ACK_Msk                     (0x1UL << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */\n#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */\n#define I2C_CR1_POS_Pos                     (11U)                              \n#define I2C_CR1_POS_Msk                     (0x1UL << I2C_CR1_POS_Pos)          /*!< 0x00000800 */\n#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */\n#define I2C_CR1_PEC_Pos                     (12U)                              \n#define I2C_CR1_PEC_Msk                     (0x1UL << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */\n#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */\n#define I2C_CR1_ALERT_Pos                   (13U)                              \n#define I2C_CR1_ALERT_Msk                   (0x1UL << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */\n#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */\n#define I2C_CR1_SWRST_Pos                   (15U)                              \n#define I2C_CR1_SWRST_Msk                   (0x1UL << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */\n#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */\n\n/*******************  Bit definition for I2C_CR2 register  ********************/\n#define I2C_CR2_FREQ_Pos                    (0U)                               \n#define I2C_CR2_FREQ_Msk                    (0x3FUL << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */\n#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */\n#define I2C_CR2_FREQ_0                      (0x01UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */\n#define I2C_CR2_FREQ_1                      (0x02UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */\n#define I2C_CR2_FREQ_2                      (0x04UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */\n#define I2C_CR2_FREQ_3                      (0x08UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */\n#define I2C_CR2_FREQ_4                      (0x10UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */\n#define I2C_CR2_FREQ_5                      (0x20UL << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */\n\n#define I2C_CR2_ITERREN_Pos                 (8U)                               \n#define I2C_CR2_ITERREN_Msk                 (0x1UL << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */\n#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */\n#define I2C_CR2_ITEVTEN_Pos                 (9U)                               \n#define I2C_CR2_ITEVTEN_Msk                 (0x1UL << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */\n#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */\n#define I2C_CR2_ITBUFEN_Pos                 (10U)                              \n#define I2C_CR2_ITBUFEN_Msk                 (0x1UL << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */\n#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */\n#define I2C_CR2_DMAEN_Pos                   (11U)                              \n#define I2C_CR2_DMAEN_Msk                   (0x1UL << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */\n#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */\n#define I2C_CR2_LAST_Pos                    (12U)                              \n#define I2C_CR2_LAST_Msk                    (0x1UL << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */\n#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */\n\n/*******************  Bit definition for I2C_OAR1 register  *******************/\n#define I2C_OAR1_ADD1_7                     0x000000FEU             /*!< Interface Address */\n#define I2C_OAR1_ADD8_9                     0x00000300U             /*!< Interface Address */\n\n#define I2C_OAR1_ADD0_Pos                   (0U)                               \n#define I2C_OAR1_ADD0_Msk                   (0x1UL << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */\n#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */\n#define I2C_OAR1_ADD1_Pos                   (1U)                               \n#define I2C_OAR1_ADD1_Msk                   (0x1UL << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */\n#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */\n#define I2C_OAR1_ADD2_Pos                   (2U)                               \n#define I2C_OAR1_ADD2_Msk                   (0x1UL << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */\n#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */\n#define I2C_OAR1_ADD3_Pos                   (3U)                               \n#define I2C_OAR1_ADD3_Msk                   (0x1UL << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */\n#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */\n#define I2C_OAR1_ADD4_Pos                   (4U)                               \n#define I2C_OAR1_ADD4_Msk                   (0x1UL << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */\n#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */\n#define I2C_OAR1_ADD5_Pos                   (5U)                               \n#define I2C_OAR1_ADD5_Msk                   (0x1UL << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */\n#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */\n#define I2C_OAR1_ADD6_Pos                   (6U)                               \n#define I2C_OAR1_ADD6_Msk                   (0x1UL << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */\n#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */\n#define I2C_OAR1_ADD7_Pos                   (7U)                               \n#define I2C_OAR1_ADD7_Msk                   (0x1UL << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */\n#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */\n#define I2C_OAR1_ADD8_Pos                   (8U)                               \n#define I2C_OAR1_ADD8_Msk                   (0x1UL << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */\n#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */\n#define I2C_OAR1_ADD9_Pos                   (9U)                               \n#define I2C_OAR1_ADD9_Msk                   (0x1UL << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */\n#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */\n\n#define I2C_OAR1_ADDMODE_Pos                (15U)                              \n#define I2C_OAR1_ADDMODE_Msk                (0x1UL << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */\n#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */\n\n/*******************  Bit definition for I2C_OAR2 register  *******************/\n#define I2C_OAR2_ENDUAL_Pos                 (0U)                               \n#define I2C_OAR2_ENDUAL_Msk                 (0x1UL << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */\n#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */\n#define I2C_OAR2_ADD2_Pos                   (1U)                               \n#define I2C_OAR2_ADD2_Msk                   (0x7FUL << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */\n#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */\n\n/********************  Bit definition for I2C_DR register  ********************/\n#define I2C_DR_DR_Pos             (0U)                                         \n#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */\n#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!< 8-bit Data Register         */\n\n/*******************  Bit definition for I2C_SR1 register  ********************/\n#define I2C_SR1_SB_Pos                      (0U)                               \n#define I2C_SR1_SB_Msk                      (0x1UL << I2C_SR1_SB_Pos)           /*!< 0x00000001 */\n#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */\n#define I2C_SR1_ADDR_Pos                    (1U)                               \n#define I2C_SR1_ADDR_Msk                    (0x1UL << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */\n#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */\n#define I2C_SR1_BTF_Pos                     (2U)                               \n#define I2C_SR1_BTF_Msk                     (0x1UL << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */\n#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */\n#define I2C_SR1_ADD10_Pos                   (3U)                               \n#define I2C_SR1_ADD10_Msk                   (0x1UL << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */\n#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */\n#define I2C_SR1_STOPF_Pos                   (4U)                               \n#define I2C_SR1_STOPF_Msk                   (0x1UL << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */\n#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */\n#define I2C_SR1_RXNE_Pos                    (6U)                               \n#define I2C_SR1_RXNE_Msk                    (0x1UL << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */\n#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */\n#define I2C_SR1_TXE_Pos                     (7U)                               \n#define I2C_SR1_TXE_Msk                     (0x1UL << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */\n#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */\n#define I2C_SR1_BERR_Pos                    (8U)                               \n#define I2C_SR1_BERR_Msk                    (0x1UL << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */\n#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */\n#define I2C_SR1_ARLO_Pos                    (9U)                               \n#define I2C_SR1_ARLO_Msk                    (0x1UL << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */\n#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */\n#define I2C_SR1_AF_Pos                      (10U)                              \n#define I2C_SR1_AF_Msk                      (0x1UL << I2C_SR1_AF_Pos)           /*!< 0x00000400 */\n#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */\n#define I2C_SR1_OVR_Pos                     (11U)                              \n#define I2C_SR1_OVR_Msk                     (0x1UL << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */\n#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */\n#define I2C_SR1_PECERR_Pos                  (12U)                              \n#define I2C_SR1_PECERR_Msk                  (0x1UL << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */\n#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */\n#define I2C_SR1_TIMEOUT_Pos                 (14U)                              \n#define I2C_SR1_TIMEOUT_Msk                 (0x1UL << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */\n#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */\n#define I2C_SR1_SMBALERT_Pos                (15U)                              \n#define I2C_SR1_SMBALERT_Msk                (0x1UL << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */\n#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */\n\n/*******************  Bit definition for I2C_SR2 register  ********************/\n#define I2C_SR2_MSL_Pos                     (0U)                               \n#define I2C_SR2_MSL_Msk                     (0x1UL << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */\n#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */\n#define I2C_SR2_BUSY_Pos                    (1U)                               \n#define I2C_SR2_BUSY_Msk                    (0x1UL << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */\n#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */\n#define I2C_SR2_TRA_Pos                     (2U)                               \n#define I2C_SR2_TRA_Msk                     (0x1UL << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */\n#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */\n#define I2C_SR2_GENCALL_Pos                 (4U)                               \n#define I2C_SR2_GENCALL_Msk                 (0x1UL << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */\n#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */\n#define I2C_SR2_SMBDEFAULT_Pos              (5U)                               \n#define I2C_SR2_SMBDEFAULT_Msk              (0x1UL << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */\n#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */\n#define I2C_SR2_SMBHOST_Pos                 (6U)                               \n#define I2C_SR2_SMBHOST_Msk                 (0x1UL << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */\n#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */\n#define I2C_SR2_DUALF_Pos                   (7U)                               \n#define I2C_SR2_DUALF_Msk                   (0x1UL << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */\n#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */\n#define I2C_SR2_PEC_Pos                     (8U)                               \n#define I2C_SR2_PEC_Msk                     (0xFFUL << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */\n#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */\n\n/*******************  Bit definition for I2C_CCR register  ********************/\n#define I2C_CCR_CCR_Pos                     (0U)                               \n#define I2C_CCR_CCR_Msk                     (0xFFFUL << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */\n#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */\n#define I2C_CCR_DUTY_Pos                    (14U)                              \n#define I2C_CCR_DUTY_Msk                    (0x1UL << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */\n#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */\n#define I2C_CCR_FS_Pos                      (15U)                              \n#define I2C_CCR_FS_Msk                      (0x1UL << I2C_CCR_FS_Pos)           /*!< 0x00008000 */\n#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */\n\n/******************  Bit definition for I2C_TRISE register  *******************/\n#define I2C_TRISE_TRISE_Pos                 (0U)                               \n#define I2C_TRISE_TRISE_Msk                 (0x3FUL << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */\n#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */\n\n/******************************************************************************/\n/*                                                                            */\n/*         Universal Synchronous Asynchronous Receiver Transmitter            */\n/*                                                                            */\n/******************************************************************************/\n\n/*******************  Bit definition for USART_SR register  *******************/\n#define USART_SR_PE_Pos                     (0U)                               \n#define USART_SR_PE_Msk                     (0x1UL << USART_SR_PE_Pos)          /*!< 0x00000001 */\n#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */\n#define USART_SR_FE_Pos                     (1U)                               \n#define USART_SR_FE_Msk                     (0x1UL << USART_SR_FE_Pos)          /*!< 0x00000002 */\n#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */\n#define USART_SR_NE_Pos                     (2U)                               \n#define USART_SR_NE_Msk                     (0x1UL << USART_SR_NE_Pos)          /*!< 0x00000004 */\n#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */\n#define USART_SR_ORE_Pos                    (3U)                               \n#define USART_SR_ORE_Msk                    (0x1UL << USART_SR_ORE_Pos)         /*!< 0x00000008 */\n#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */\n#define USART_SR_IDLE_Pos                   (4U)                               \n#define USART_SR_IDLE_Msk                   (0x1UL << USART_SR_IDLE_Pos)        /*!< 0x00000010 */\n#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */\n#define USART_SR_RXNE_Pos                   (5U)                               \n#define USART_SR_RXNE_Msk                   (0x1UL << USART_SR_RXNE_Pos)        /*!< 0x00000020 */\n#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */\n#define USART_SR_TC_Pos                     (6U)                               \n#define USART_SR_TC_Msk                     (0x1UL << USART_SR_TC_Pos)          /*!< 0x00000040 */\n#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */\n#define USART_SR_TXE_Pos                    (7U)                               \n#define USART_SR_TXE_Msk                    (0x1UL << USART_SR_TXE_Pos)         /*!< 0x00000080 */\n#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */\n#define USART_SR_LBD_Pos                    (8U)                               \n#define USART_SR_LBD_Msk                    (0x1UL << USART_SR_LBD_Pos)         /*!< 0x00000100 */\n#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */\n#define USART_SR_CTS_Pos                    (9U)                               \n#define USART_SR_CTS_Msk                    (0x1UL << USART_SR_CTS_Pos)         /*!< 0x00000200 */\n#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */\n\n/*******************  Bit definition for USART_DR register  *******************/\n#define USART_DR_DR_Pos                     (0U)                               \n#define USART_DR_DR_Msk                     (0x1FFUL << USART_DR_DR_Pos)        /*!< 0x000001FF */\n#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */\n\n/******************  Bit definition for USART_BRR register  *******************/\n#define USART_BRR_DIV_Fraction_Pos          (0U)                               \n#define USART_BRR_DIV_Fraction_Msk          (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */\n#define USART_BRR_DIV_Fraction              USART_BRR_DIV_Fraction_Msk         /*!< Fraction of USARTDIV */\n#define USART_BRR_DIV_Mantissa_Pos          (4U)                               \n#define USART_BRR_DIV_Mantissa_Msk          (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */\n#define USART_BRR_DIV_Mantissa              USART_BRR_DIV_Mantissa_Msk         /*!< Mantissa of USARTDIV */\n\n/******************  Bit definition for USART_CR1 register  *******************/\n#define USART_CR1_SBK_Pos                   (0U)                               \n#define USART_CR1_SBK_Msk                   (0x1UL << USART_CR1_SBK_Pos)        /*!< 0x00000001 */\n#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */\n#define USART_CR1_RWU_Pos                   (1U)                               \n#define USART_CR1_RWU_Msk                   (0x1UL << USART_CR1_RWU_Pos)        /*!< 0x00000002 */\n#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */\n#define USART_CR1_RE_Pos                    (2U)                               \n#define USART_CR1_RE_Msk                    (0x1UL << USART_CR1_RE_Pos)         /*!< 0x00000004 */\n#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */\n#define USART_CR1_TE_Pos                    (3U)                               \n#define USART_CR1_TE_Msk                    (0x1UL << USART_CR1_TE_Pos)         /*!< 0x00000008 */\n#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */\n#define USART_CR1_IDLEIE_Pos                (4U)                               \n#define USART_CR1_IDLEIE_Msk                (0x1UL << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */\n#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */\n#define USART_CR1_RXNEIE_Pos                (5U)                               \n#define USART_CR1_RXNEIE_Msk                (0x1UL << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */\n#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */\n#define USART_CR1_TCIE_Pos                  (6U)                               \n#define USART_CR1_TCIE_Msk                  (0x1UL << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */\n#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */\n#define USART_CR1_TXEIE_Pos                 (7U)                               \n#define USART_CR1_TXEIE_Msk                 (0x1UL << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */\n#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */\n#define USART_CR1_PEIE_Pos                  (8U)                               \n#define USART_CR1_PEIE_Msk                  (0x1UL << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */\n#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */\n#define USART_CR1_PS_Pos                    (9U)                               \n#define USART_CR1_PS_Msk                    (0x1UL << USART_CR1_PS_Pos)         /*!< 0x00000200 */\n#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */\n#define USART_CR1_PCE_Pos                   (10U)                              \n#define USART_CR1_PCE_Msk                   (0x1UL << USART_CR1_PCE_Pos)        /*!< 0x00000400 */\n#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */\n#define USART_CR1_WAKE_Pos                  (11U)                              \n#define USART_CR1_WAKE_Msk                  (0x1UL << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */\n#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */\n#define USART_CR1_M_Pos                     (12U)                              \n#define USART_CR1_M_Msk                     (0x1UL << USART_CR1_M_Pos)          /*!< 0x00001000 */\n#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */\n#define USART_CR1_UE_Pos                    (13U)                              \n#define USART_CR1_UE_Msk                    (0x1UL << USART_CR1_UE_Pos)         /*!< 0x00002000 */\n#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */\n\n/******************  Bit definition for USART_CR2 register  *******************/\n#define USART_CR2_ADD_Pos                   (0U)                               \n#define USART_CR2_ADD_Msk                   (0xFUL << USART_CR2_ADD_Pos)        /*!< 0x0000000F */\n#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */\n#define USART_CR2_LBDL_Pos                  (5U)                               \n#define USART_CR2_LBDL_Msk                  (0x1UL << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */\n#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */\n#define USART_CR2_LBDIE_Pos                 (6U)                               \n#define USART_CR2_LBDIE_Msk                 (0x1UL << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */\n#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */\n#define USART_CR2_LBCL_Pos                  (8U)                               \n#define USART_CR2_LBCL_Msk                  (0x1UL << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */\n#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */\n#define USART_CR2_CPHA_Pos                  (9U)                               \n#define USART_CR2_CPHA_Msk                  (0x1UL << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */\n#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */\n#define USART_CR2_CPOL_Pos                  (10U)                              \n#define USART_CR2_CPOL_Msk                  (0x1UL << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */\n#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */\n#define USART_CR2_CLKEN_Pos                 (11U)                              \n#define USART_CR2_CLKEN_Msk                 (0x1UL << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */\n#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */\n\n#define USART_CR2_STOP_Pos                  (12U)                              \n#define USART_CR2_STOP_Msk                  (0x3UL << USART_CR2_STOP_Pos)       /*!< 0x00003000 */\n#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */\n#define USART_CR2_STOP_0                    (0x1UL << USART_CR2_STOP_Pos)       /*!< 0x00001000 */\n#define USART_CR2_STOP_1                    (0x2UL << USART_CR2_STOP_Pos)       /*!< 0x00002000 */\n\n#define USART_CR2_LINEN_Pos                 (14U)                              \n#define USART_CR2_LINEN_Msk                 (0x1UL << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */\n#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */\n\n/******************  Bit definition for USART_CR3 register  *******************/\n#define USART_CR3_EIE_Pos                   (0U)                               \n#define USART_CR3_EIE_Msk                   (0x1UL << USART_CR3_EIE_Pos)        /*!< 0x00000001 */\n#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */\n#define USART_CR3_IREN_Pos                  (1U)                               \n#define USART_CR3_IREN_Msk                  (0x1UL << USART_CR3_IREN_Pos)       /*!< 0x00000002 */\n#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */\n#define USART_CR3_IRLP_Pos                  (2U)                               \n#define USART_CR3_IRLP_Msk                  (0x1UL << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */\n#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */\n#define USART_CR3_HDSEL_Pos                 (3U)                               \n#define USART_CR3_HDSEL_Msk                 (0x1UL << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */\n#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */\n#define USART_CR3_NACK_Pos                  (4U)                               \n#define USART_CR3_NACK_Msk                  (0x1UL << USART_CR3_NACK_Pos)       /*!< 0x00000010 */\n#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */\n#define USART_CR3_SCEN_Pos                  (5U)                               \n#define USART_CR3_SCEN_Msk                  (0x1UL << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */\n#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */\n#define USART_CR3_DMAR_Pos                  (6U)                               \n#define USART_CR3_DMAR_Msk                  (0x1UL << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */\n#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */\n#define USART_CR3_DMAT_Pos                  (7U)                               \n#define USART_CR3_DMAT_Msk                  (0x1UL << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */\n#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */\n#define USART_CR3_RTSE_Pos                  (8U)                               \n#define USART_CR3_RTSE_Msk                  (0x1UL << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */\n#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */\n#define USART_CR3_CTSE_Pos                  (9U)                               \n#define USART_CR3_CTSE_Msk                  (0x1UL << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */\n#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */\n#define USART_CR3_CTSIE_Pos                 (10U)                              \n#define USART_CR3_CTSIE_Msk                 (0x1UL << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */\n#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */\n\n/******************  Bit definition for USART_GTPR register  ******************/\n#define USART_GTPR_PSC_Pos                  (0U)                               \n#define USART_GTPR_PSC_Msk                  (0xFFUL << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */\n#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */\n#define USART_GTPR_PSC_0                    (0x01UL << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */\n#define USART_GTPR_PSC_1                    (0x02UL << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */\n#define USART_GTPR_PSC_2                    (0x04UL << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */\n#define USART_GTPR_PSC_3                    (0x08UL << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */\n#define USART_GTPR_PSC_4                    (0x10UL << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */\n#define USART_GTPR_PSC_5                    (0x20UL << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */\n#define USART_GTPR_PSC_6                    (0x40UL << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */\n#define USART_GTPR_PSC_7                    (0x80UL << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */\n\n#define USART_GTPR_GT_Pos                   (8U)                               \n#define USART_GTPR_GT_Msk                   (0xFFUL << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */\n#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */\n\n/******************************************************************************/\n/*                                                                            */\n/*                                 Debug MCU                                  */\n/*                                                                            */\n/******************************************************************************/\n\n/****************  Bit definition for DBGMCU_IDCODE register  *****************/\n#define DBGMCU_IDCODE_DEV_ID_Pos            (0U)                               \n#define DBGMCU_IDCODE_DEV_ID_Msk            (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\n#define DBGMCU_IDCODE_DEV_ID                DBGMCU_IDCODE_DEV_ID_Msk           /*!< Device Identifier */\n\n#define DBGMCU_IDCODE_REV_ID_Pos            (16U)                              \n#define DBGMCU_IDCODE_REV_ID_Msk            (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\n#define DBGMCU_IDCODE_REV_ID                DBGMCU_IDCODE_REV_ID_Msk           /*!< REV_ID[15:0] bits (Revision Identifier) */\n#define DBGMCU_IDCODE_REV_ID_0              (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */\n#define DBGMCU_IDCODE_REV_ID_1              (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */\n#define DBGMCU_IDCODE_REV_ID_2              (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */\n#define DBGMCU_IDCODE_REV_ID_3              (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */\n#define DBGMCU_IDCODE_REV_ID_4              (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */\n#define DBGMCU_IDCODE_REV_ID_5              (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */\n#define DBGMCU_IDCODE_REV_ID_6              (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */\n#define DBGMCU_IDCODE_REV_ID_7              (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */\n#define DBGMCU_IDCODE_REV_ID_8              (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */\n#define DBGMCU_IDCODE_REV_ID_9              (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */\n#define DBGMCU_IDCODE_REV_ID_10             (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */\n#define DBGMCU_IDCODE_REV_ID_11             (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */\n#define DBGMCU_IDCODE_REV_ID_12             (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */\n#define DBGMCU_IDCODE_REV_ID_13             (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */\n#define DBGMCU_IDCODE_REV_ID_14             (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */\n#define DBGMCU_IDCODE_REV_ID_15             (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */\n\n/******************  Bit definition for DBGMCU_CR register  *******************/\n#define DBGMCU_CR_DBG_SLEEP_Pos             (0U)                               \n#define DBGMCU_CR_DBG_SLEEP_Msk             (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */\n#define DBGMCU_CR_DBG_SLEEP                 DBGMCU_CR_DBG_SLEEP_Msk            /*!< Debug Sleep Mode */\n#define DBGMCU_CR_DBG_STOP_Pos              (1U)                               \n#define DBGMCU_CR_DBG_STOP_Msk              (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */\n#define DBGMCU_CR_DBG_STOP                  DBGMCU_CR_DBG_STOP_Msk             /*!< Debug Stop Mode */\n#define DBGMCU_CR_DBG_STANDBY_Pos           (2U)                               \n#define DBGMCU_CR_DBG_STANDBY_Msk           (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\n#define DBGMCU_CR_DBG_STANDBY               DBGMCU_CR_DBG_STANDBY_Msk          /*!< Debug Standby mode */\n#define DBGMCU_CR_TRACE_IOEN_Pos            (5U)                               \n#define DBGMCU_CR_TRACE_IOEN_Msk            (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\n#define DBGMCU_CR_TRACE_IOEN                DBGMCU_CR_TRACE_IOEN_Msk           /*!< Trace Pin Assignment Control */\n\n#define DBGMCU_CR_TRACE_MODE_Pos            (6U)                               \n#define DBGMCU_CR_TRACE_MODE_Msk            (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\n#define DBGMCU_CR_TRACE_MODE                DBGMCU_CR_TRACE_MODE_Msk           /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */\n#define DBGMCU_CR_TRACE_MODE_0              (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\n#define DBGMCU_CR_TRACE_MODE_1              (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\n\n#define DBGMCU_CR_DBG_IWDG_STOP_Pos         (8U)                               \n#define DBGMCU_CR_DBG_IWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */\n#define DBGMCU_CR_DBG_IWDG_STOP             DBGMCU_CR_DBG_IWDG_STOP_Msk        /*!< Debug Independent Watchdog stopped when Core is halted */\n#define DBGMCU_CR_DBG_WWDG_STOP_Pos         (9U)                               \n#define DBGMCU_CR_DBG_WWDG_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */\n#define DBGMCU_CR_DBG_WWDG_STOP             DBGMCU_CR_DBG_WWDG_STOP_Msk        /*!< Debug Window Watchdog stopped when Core is halted */\n#define DBGMCU_CR_DBG_TIM1_STOP_Pos         (10U)                              \n#define DBGMCU_CR_DBG_TIM1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */\n#define DBGMCU_CR_DBG_TIM1_STOP             DBGMCU_CR_DBG_TIM1_STOP_Msk        /*!< TIM1 counter stopped when core is halted */\n#define DBGMCU_CR_DBG_TIM2_STOP_Pos         (11U)                              \n#define DBGMCU_CR_DBG_TIM2_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */\n#define DBGMCU_CR_DBG_TIM2_STOP             DBGMCU_CR_DBG_TIM2_STOP_Msk        /*!< TIM2 counter stopped when core is halted */\n#define DBGMCU_CR_DBG_TIM3_STOP_Pos         (12U)                              \n#define DBGMCU_CR_DBG_TIM3_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */\n#define DBGMCU_CR_DBG_TIM3_STOP             DBGMCU_CR_DBG_TIM3_STOP_Msk        /*!< TIM3 counter stopped when core is halted */\n#define DBGMCU_CR_DBG_TIM4_STOP_Pos         (13U)                              \n#define DBGMCU_CR_DBG_TIM4_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */\n#define DBGMCU_CR_DBG_TIM4_STOP             DBGMCU_CR_DBG_TIM4_STOP_Msk        /*!< TIM4 counter stopped when core is halted */\n#define DBGMCU_CR_DBG_CAN1_STOP_Pos         (14U)                              \n#define DBGMCU_CR_DBG_CAN1_STOP_Msk         (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */\n#define DBGMCU_CR_DBG_CAN1_STOP             DBGMCU_CR_DBG_CAN1_STOP_Msk        /*!< Debug CAN1 stopped when Core is halted */\n#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)                             \n#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */\n#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\n#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)                             \n#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */\n#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */\n\n/******************************************************************************/\n/*                                                                            */\n/*                      FLASH and Option Bytes Registers                      */\n/*                                                                            */\n/******************************************************************************/\n/*******************  Bit definition for FLASH_ACR register  ******************/\n#define FLASH_ACR_LATENCY_Pos               (0U)                               \n#define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000007 */\n#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< LATENCY[2:0] bits (Latency) */\n#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000001 */\n#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000002 */\n#define FLASH_ACR_LATENCY_2                 (0x4UL << FLASH_ACR_LATENCY_Pos)    /*!< 0x00000004 */\n\n#define FLASH_ACR_HLFCYA_Pos                (3U)                               \n#define FLASH_ACR_HLFCYA_Msk                (0x1UL << FLASH_ACR_HLFCYA_Pos)     /*!< 0x00000008 */\n#define FLASH_ACR_HLFCYA                    FLASH_ACR_HLFCYA_Msk               /*!< Flash Half Cycle Access Enable */\n#define FLASH_ACR_PRFTBE_Pos                (4U)                               \n#define FLASH_ACR_PRFTBE_Msk                (0x1UL << FLASH_ACR_PRFTBE_Pos)     /*!< 0x00000010 */\n#define FLASH_ACR_PRFTBE                    FLASH_ACR_PRFTBE_Msk               /*!< Prefetch Buffer Enable */\n#define FLASH_ACR_PRFTBS_Pos                (5U)                               \n#define FLASH_ACR_PRFTBS_Msk                (0x1UL << FLASH_ACR_PRFTBS_Pos)     /*!< 0x00000020 */\n#define FLASH_ACR_PRFTBS                    FLASH_ACR_PRFTBS_Msk               /*!< Prefetch Buffer Status */\n\n/******************  Bit definition for FLASH_KEYR register  ******************/\n#define FLASH_KEYR_FKEYR_Pos                (0U)                               \n#define FLASH_KEYR_FKEYR_Msk                (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_KEYR_FKEYR                    FLASH_KEYR_FKEYR_Msk               /*!< FPEC Key */\n\n#define RDP_KEY_Pos                         (0U)                               \n#define RDP_KEY_Msk                         (0xA5UL << RDP_KEY_Pos)             /*!< 0x000000A5 */\n#define RDP_KEY                             RDP_KEY_Msk                        /*!< RDP Key */\n#define FLASH_KEY1_Pos                      (0U)                               \n#define FLASH_KEY1_Msk                      (0x45670123UL << FLASH_KEY1_Pos)    /*!< 0x45670123 */\n#define FLASH_KEY1                          FLASH_KEY1_Msk                     /*!< FPEC Key1 */\n#define FLASH_KEY2_Pos                      (0U)                               \n#define FLASH_KEY2_Msk                      (0xCDEF89ABUL << FLASH_KEY2_Pos)    /*!< 0xCDEF89AB */\n#define FLASH_KEY2                          FLASH_KEY2_Msk                     /*!< FPEC Key2 */\n\n/*****************  Bit definition for FLASH_OPTKEYR register  ****************/\n#define FLASH_OPTKEYR_OPTKEYR_Pos           (0U)                               \n#define FLASH_OPTKEYR_OPTKEYR_Msk           (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_OPTKEYR_OPTKEYR               FLASH_OPTKEYR_OPTKEYR_Msk          /*!< Option Byte Key */\n\n#define  FLASH_OPTKEY1                       FLASH_KEY1                    /*!< Option Byte Key1 */\n#define  FLASH_OPTKEY2                       FLASH_KEY2                    /*!< Option Byte Key2 */\n\n/******************  Bit definition for FLASH_SR register  ********************/\n#define FLASH_SR_BSY_Pos                    (0U)                               \n#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)         /*!< 0x00000001 */\n#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Busy */\n#define FLASH_SR_PGERR_Pos                  (2U)                               \n#define FLASH_SR_PGERR_Msk                  (0x1UL << FLASH_SR_PGERR_Pos)       /*!< 0x00000004 */\n#define FLASH_SR_PGERR                      FLASH_SR_PGERR_Msk                 /*!< Programming Error */\n#define FLASH_SR_WRPRTERR_Pos               (4U)                               \n#define FLASH_SR_WRPRTERR_Msk               (0x1UL << FLASH_SR_WRPRTERR_Pos)    /*!< 0x00000010 */\n#define FLASH_SR_WRPRTERR                   FLASH_SR_WRPRTERR_Msk              /*!< Write Protection Error */\n#define FLASH_SR_EOP_Pos                    (5U)                               \n#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)         /*!< 0x00000020 */\n#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of operation */\n\n/*******************  Bit definition for FLASH_CR register  *******************/\n#define FLASH_CR_PG_Pos                     (0U)                               \n#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)          /*!< 0x00000001 */\n#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Programming */\n#define FLASH_CR_PER_Pos                    (1U)                               \n#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)         /*!< 0x00000002 */\n#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page Erase */\n#define FLASH_CR_MER_Pos                    (2U)                               \n#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)         /*!< 0x00000004 */\n#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass Erase */\n#define FLASH_CR_OPTPG_Pos                  (4U)                               \n#define FLASH_CR_OPTPG_Msk                  (0x1UL << FLASH_CR_OPTPG_Pos)       /*!< 0x00000010 */\n#define FLASH_CR_OPTPG                      FLASH_CR_OPTPG_Msk                 /*!< Option Byte Programming */\n#define FLASH_CR_OPTER_Pos                  (5U)                               \n#define FLASH_CR_OPTER_Msk                  (0x1UL << FLASH_CR_OPTER_Pos)       /*!< 0x00000020 */\n#define FLASH_CR_OPTER                      FLASH_CR_OPTER_Msk                 /*!< Option Byte Erase */\n#define FLASH_CR_STRT_Pos                   (6U)                               \n#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)        /*!< 0x00000040 */\n#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start */\n#define FLASH_CR_LOCK_Pos                   (7U)                               \n#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)        /*!< 0x00000080 */\n#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Lock */\n#define FLASH_CR_OPTWRE_Pos                 (9U)                               \n#define FLASH_CR_OPTWRE_Msk                 (0x1UL << FLASH_CR_OPTWRE_Pos)      /*!< 0x00000200 */\n#define FLASH_CR_OPTWRE                     FLASH_CR_OPTWRE_Msk                /*!< Option Bytes Write Enable */\n#define FLASH_CR_ERRIE_Pos                  (10U)                              \n#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)       /*!< 0x00000400 */\n#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error Interrupt Enable */\n#define FLASH_CR_EOPIE_Pos                  (12U)                              \n#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)       /*!< 0x00001000 */\n#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable */\n\n/*******************  Bit definition for FLASH_AR register  *******************/\n#define FLASH_AR_FAR_Pos                    (0U)                               \n#define FLASH_AR_FAR_Msk                    (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)  /*!< 0xFFFFFFFF */\n#define FLASH_AR_FAR                        FLASH_AR_FAR_Msk                   /*!< Flash Address */\n\n/******************  Bit definition for FLASH_OBR register  *******************/\n#define FLASH_OBR_OPTERR_Pos                (0U)                               \n#define FLASH_OBR_OPTERR_Msk                (0x1UL << FLASH_OBR_OPTERR_Pos)     /*!< 0x00000001 */\n#define FLASH_OBR_OPTERR                    FLASH_OBR_OPTERR_Msk               /*!< Option Byte Error */\n#define FLASH_OBR_RDPRT_Pos                 (1U)                               \n#define FLASH_OBR_RDPRT_Msk                 (0x1UL << FLASH_OBR_RDPRT_Pos)      /*!< 0x00000002 */\n#define FLASH_OBR_RDPRT                     FLASH_OBR_RDPRT_Msk                /*!< Read protection */\n\n#define FLASH_OBR_IWDG_SW_Pos               (2U)                               \n#define FLASH_OBR_IWDG_SW_Msk               (0x1UL << FLASH_OBR_IWDG_SW_Pos)    /*!< 0x00000004 */\n#define FLASH_OBR_IWDG_SW                   FLASH_OBR_IWDG_SW_Msk              /*!< IWDG SW */\n#define FLASH_OBR_nRST_STOP_Pos             (3U)                               \n#define FLASH_OBR_nRST_STOP_Msk             (0x1UL << FLASH_OBR_nRST_STOP_Pos)  /*!< 0x00000008 */\n#define FLASH_OBR_nRST_STOP                 FLASH_OBR_nRST_STOP_Msk            /*!< nRST_STOP */\n#define FLASH_OBR_nRST_STDBY_Pos            (4U)                               \n#define FLASH_OBR_nRST_STDBY_Msk            (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */\n#define FLASH_OBR_nRST_STDBY                FLASH_OBR_nRST_STDBY_Msk           /*!< nRST_STDBY */\n#define FLASH_OBR_USER_Pos                  (2U)                               \n#define FLASH_OBR_USER_Msk                  (0x7UL << FLASH_OBR_USER_Pos)       /*!< 0x0000001C */\n#define FLASH_OBR_USER                      FLASH_OBR_USER_Msk                 /*!< User Option Bytes */\n#define FLASH_OBR_DATA0_Pos                 (10U)                              \n#define FLASH_OBR_DATA0_Msk                 (0xFFUL << FLASH_OBR_DATA0_Pos)     /*!< 0x0003FC00 */\n#define FLASH_OBR_DATA0                     FLASH_OBR_DATA0_Msk                /*!< Data0 */\n#define FLASH_OBR_DATA1_Pos                 (18U)                              \n#define FLASH_OBR_DATA1_Msk                 (0xFFUL << FLASH_OBR_DATA1_Pos)     /*!< 0x03FC0000 */\n#define FLASH_OBR_DATA1                     FLASH_OBR_DATA1_Msk                /*!< Data1 */\n\n/******************  Bit definition for FLASH_WRPR register  ******************/\n#define FLASH_WRPR_WRP_Pos                  (0U)                               \n#define FLASH_WRPR_WRP_Msk                  (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */\n#define FLASH_WRPR_WRP                      FLASH_WRPR_WRP_Msk                 /*!< Write Protect */\n\n/*----------------------------------------------------------------------------*/\n\n/******************  Bit definition for FLASH_RDP register  *******************/\n#define FLASH_RDP_RDP_Pos                   (0U)                               \n#define FLASH_RDP_RDP_Msk                   (0xFFUL << FLASH_RDP_RDP_Pos)       /*!< 0x000000FF */\n#define FLASH_RDP_RDP                       FLASH_RDP_RDP_Msk                  /*!< Read protection option byte */\n#define FLASH_RDP_nRDP_Pos                  (8U)                               \n#define FLASH_RDP_nRDP_Msk                  (0xFFUL << FLASH_RDP_nRDP_Pos)      /*!< 0x0000FF00 */\n#define FLASH_RDP_nRDP                      FLASH_RDP_nRDP_Msk                 /*!< Read protection complemented option byte */\n\n/******************  Bit definition for FLASH_USER register  ******************/\n#define FLASH_USER_USER_Pos                 (16U)                              \n#define FLASH_USER_USER_Msk                 (0xFFUL << FLASH_USER_USER_Pos)     /*!< 0x00FF0000 */\n#define FLASH_USER_USER                     FLASH_USER_USER_Msk                /*!< User option byte */\n#define FLASH_USER_nUSER_Pos                (24U)                              \n#define FLASH_USER_nUSER_Msk                (0xFFUL << FLASH_USER_nUSER_Pos)    /*!< 0xFF000000 */\n#define FLASH_USER_nUSER                    FLASH_USER_nUSER_Msk               /*!< User complemented option byte */\n\n/******************  Bit definition for FLASH_Data0 register  *****************/\n#define FLASH_DATA0_DATA0_Pos               (0U)                               \n#define FLASH_DATA0_DATA0_Msk               (0xFFUL << FLASH_DATA0_DATA0_Pos)   /*!< 0x000000FF */\n#define FLASH_DATA0_DATA0                   FLASH_DATA0_DATA0_Msk              /*!< User data storage option byte */\n#define FLASH_DATA0_nDATA0_Pos              (8U)                               \n#define FLASH_DATA0_nDATA0_Msk              (0xFFUL << FLASH_DATA0_nDATA0_Pos)  /*!< 0x0000FF00 */\n#define FLASH_DATA0_nDATA0                  FLASH_DATA0_nDATA0_Msk             /*!< User data storage complemented option byte */\n\n/******************  Bit definition for FLASH_Data1 register  *****************/\n#define FLASH_DATA1_DATA1_Pos               (16U)                              \n#define FLASH_DATA1_DATA1_Msk               (0xFFUL << FLASH_DATA1_DATA1_Pos)   /*!< 0x00FF0000 */\n#define FLASH_DATA1_DATA1                   FLASH_DATA1_DATA1_Msk              /*!< User data storage option byte */\n#define FLASH_DATA1_nDATA1_Pos              (24U)                              \n#define FLASH_DATA1_nDATA1_Msk              (0xFFUL << FLASH_DATA1_nDATA1_Pos)  /*!< 0xFF000000 */\n#define FLASH_DATA1_nDATA1                  FLASH_DATA1_nDATA1_Msk             /*!< User data storage complemented option byte */\n\n/******************  Bit definition for FLASH_WRP0 register  ******************/\n#define FLASH_WRP0_WRP0_Pos                 (0U)                               \n#define FLASH_WRP0_WRP0_Msk                 (0xFFUL << FLASH_WRP0_WRP0_Pos)     /*!< 0x000000FF */\n#define FLASH_WRP0_WRP0                     FLASH_WRP0_WRP0_Msk                /*!< Flash memory write protection option bytes */\n#define FLASH_WRP0_nWRP0_Pos                (8U)                               \n#define FLASH_WRP0_nWRP0_Msk                (0xFFUL << FLASH_WRP0_nWRP0_Pos)    /*!< 0x0000FF00 */\n#define FLASH_WRP0_nWRP0                    FLASH_WRP0_nWRP0_Msk               /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP1 register  ******************/\n#define FLASH_WRP1_WRP1_Pos                 (16U)                              \n#define FLASH_WRP1_WRP1_Msk                 (0xFFUL << FLASH_WRP1_WRP1_Pos)     /*!< 0x00FF0000 */\n#define FLASH_WRP1_WRP1                     FLASH_WRP1_WRP1_Msk                /*!< Flash memory write protection option bytes */\n#define FLASH_WRP1_nWRP1_Pos                (24U)                              \n#define FLASH_WRP1_nWRP1_Msk                (0xFFUL << FLASH_WRP1_nWRP1_Pos)    /*!< 0xFF000000 */\n#define FLASH_WRP1_nWRP1                    FLASH_WRP1_nWRP1_Msk               /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP2 register  ******************/\n#define FLASH_WRP2_WRP2_Pos                 (0U)                               \n#define FLASH_WRP2_WRP2_Msk                 (0xFFUL << FLASH_WRP2_WRP2_Pos)     /*!< 0x000000FF */\n#define FLASH_WRP2_WRP2                     FLASH_WRP2_WRP2_Msk                /*!< Flash memory write protection option bytes */\n#define FLASH_WRP2_nWRP2_Pos                (8U)                               \n#define FLASH_WRP2_nWRP2_Msk                (0xFFUL << FLASH_WRP2_nWRP2_Pos)    /*!< 0x0000FF00 */\n#define FLASH_WRP2_nWRP2                    FLASH_WRP2_nWRP2_Msk               /*!< Flash memory write protection complemented option bytes */\n\n/******************  Bit definition for FLASH_WRP3 register  ******************/\n#define FLASH_WRP3_WRP3_Pos                 (16U)                              \n#define FLASH_WRP3_WRP3_Msk                 (0xFFUL << FLASH_WRP3_WRP3_Pos)     /*!< 0x00FF0000 */\n#define FLASH_WRP3_WRP3                     FLASH_WRP3_WRP3_Msk                /*!< Flash memory write protection option bytes */\n#define FLASH_WRP3_nWRP3_Pos                (24U)                              \n#define FLASH_WRP3_nWRP3_Msk                (0xFFUL << FLASH_WRP3_nWRP3_Pos)    /*!< 0xFF000000 */\n#define FLASH_WRP3_nWRP3                    FLASH_WRP3_nWRP3_Msk               /*!< Flash memory write protection complemented option bytes */\n\n\n\n/**\n  * @}\n*/\n\n/**\n  * @}\n*/ \n\n/** @addtogroup Exported_macro\n  * @{\n  */\n\n/****************************** ADC Instances *********************************/\n#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \\\n                                       ((INSTANCE) == ADC2))\n\n#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)\n\n#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n#define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\n\n/****************************** CAN Instances *********************************/    \n#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)\n\n/****************************** CRC Instances *********************************/\n#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)\n\n/****************************** DAC Instances *********************************/\n\n/****************************** DMA Instances *********************************/\n#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \\\n                                       ((INSTANCE) == DMA1_Channel2) || \\\n                                       ((INSTANCE) == DMA1_Channel3) || \\\n                                       ((INSTANCE) == DMA1_Channel4) || \\\n                                       ((INSTANCE) == DMA1_Channel5) || \\\n                                       ((INSTANCE) == DMA1_Channel6) || \\\n                                       ((INSTANCE) == DMA1_Channel7))\n  \n/******************************* GPIO Instances *******************************/\n#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \\\n                                        ((INSTANCE) == GPIOB) || \\\n                                        ((INSTANCE) == GPIOC) || \\\n                                        ((INSTANCE) == GPIOD) || \\\n                                        ((INSTANCE) == GPIOE))\n\n/**************************** GPIO Alternate Function Instances ***************/\n#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/**************************** GPIO Lock Instances *****************************/\n#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)\n\n/******************************** I2C Instances *******************************/\n#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \\\n                                       ((INSTANCE) == I2C2))\n\n/******************************* SMBUS Instances ******************************/\n#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE\n\n/****************************** IWDG Instances ********************************/\n#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)\n\n/******************************** SPI Instances *******************************/\n#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \\\n                                       ((INSTANCE) == SPI2))\n\n/****************************** START TIM Instances ***************************/\n/****************************** TIM Instances *********************************/\n#define IS_TIM_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)\n\n#define IS_TIM_CC1_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CC2_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CC3_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CC4_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_XOR_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_MASTER_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_BREAK_INSTANCE(INSTANCE)\\\n  ((INSTANCE) == TIM1)\n\n#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \\\n   ((((INSTANCE) == TIM1) &&                  \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM2) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM3) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4)))           \\\n    ||                                         \\\n    (((INSTANCE) == TIM4) &&                   \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_3) ||          \\\n      ((CHANNEL) == TIM_CHANNEL_4))))\n\n#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \\\n    (((INSTANCE) == TIM1) &&                    \\\n     (((CHANNEL) == TIM_CHANNEL_1) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_2) ||           \\\n      ((CHANNEL) == TIM_CHANNEL_3)))\n\n#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\\\n  ((INSTANCE) == TIM1)\n\n#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n\n#define IS_TIM_DMA_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n    \n#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\\\n  (((INSTANCE) == TIM1)    || \\\n   ((INSTANCE) == TIM2)    || \\\n   ((INSTANCE) == TIM3)    || \\\n   ((INSTANCE) == TIM4))\n    \n#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\\\n  ((INSTANCE) == TIM1)\n\n#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)    || \\\n                                        ((INSTANCE) == TIM2)    || \\\n                                        ((INSTANCE) == TIM3)    || \\\n                                        ((INSTANCE) == TIM4))\n\n#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \\\n                                                         ((INSTANCE) == TIM2)    || \\\n                                                         ((INSTANCE) == TIM3)    || \\\n                                                         ((INSTANCE) == TIM4))\n\n#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)           0U\n\n/****************************** END TIM Instances *****************************/\n\n\n/******************** USART Instances : Synchronous mode **********************/                                           \n#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                     ((INSTANCE) == USART2) || \\\n                                     ((INSTANCE) == USART3))\n\n/******************** UART Instances : Asynchronous mode **********************/\n#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3))\n\n/******************** UART Instances : Half-Duplex mode **********************/\n#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                               ((INSTANCE) == USART2) || \\\n                                               ((INSTANCE) == USART3))\n\n/******************** UART Instances : LIN mode **********************/\n#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                        ((INSTANCE) == USART2) || \\\n                                        ((INSTANCE) == USART3))\n\n/****************** UART Instances : Hardware Flow control ********************/                                    \n#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                           ((INSTANCE) == USART2) || \\\n                                           ((INSTANCE) == USART3))\n\n/********************* UART Instances : Smard card mode ***********************/\n#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                         ((INSTANCE) == USART2) || \\\n                                         ((INSTANCE) == USART3))\n\n/*********************** UART Instances : IRDA mode ***************************/\n#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                    ((INSTANCE) == USART2) || \\\n                                    ((INSTANCE) == USART3))\n\n/***************** UART Instances : Multi-Processor mode **********************/\n#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                                   ((INSTANCE) == USART2) || \\\n                                                   ((INSTANCE) == USART3))\n\n/***************** UART Instances : DMA mode available **********************/\n#define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \\\n                                        ((INSTANCE) == USART2) || \\\n                                        ((INSTANCE) == USART3))\n\n/****************************** RTC Instances *********************************/\n#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)\n\n/**************************** WWDG Instances *****************************/\n#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)\n\n/****************************** USB Instances ********************************/\n#define IS_PCD_ALL_INSTANCE(INSTANCE)   ((INSTANCE) == USB)\n\n\n\n#define RCC_HSE_MIN         4000000U\n#define RCC_HSE_MAX        16000000U\n\n#define RCC_MAX_FREQUENCY  72000000U\n\n/**\n  * @}\n  */ \n/******************************************************************************/\n/*  For a painless codes migration between the STM32F1xx device product       */\n/*  lines, the aliases defined below are put in place to overcome the         */\n/*  differences in the interrupt handlers and IRQn definitions.               */\n/*  No need to update developed interrupt code when moving across             */ \n/*  product lines within the same STM32F1 Family                              */\n/******************************************************************************/\n\n/* Aliases for __IRQn */\n#define ADC1_IRQn               ADC1_2_IRQn\n#define TIM1_BRK_TIM15_IRQn     TIM1_BRK_IRQn\n#define TIM9_IRQn               TIM1_BRK_IRQn\n#define TIM1_BRK_TIM9_IRQn      TIM1_BRK_IRQn\n#define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn\n#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn\n#define TIM11_IRQn              TIM1_TRG_COM_IRQn\n#define TIM10_IRQn              TIM1_UP_IRQn\n#define TIM1_UP_TIM16_IRQn      TIM1_UP_IRQn\n#define TIM1_UP_TIM10_IRQn      TIM1_UP_IRQn\n#define OTG_FS_WKUP_IRQn        USBWakeUp_IRQn\n#define CEC_IRQn                USBWakeUp_IRQn\n#define CAN1_TX_IRQn            USB_HP_CAN1_TX_IRQn\n#define USB_HP_IRQn             USB_HP_CAN1_TX_IRQn\n#define CAN1_RX0_IRQn           USB_LP_CAN1_RX0_IRQn\n#define USB_LP_IRQn             USB_LP_CAN1_RX0_IRQn\n\n\n/* Aliases for __IRQHandler */\n#define ADC1_IRQHandler               ADC1_2_IRQHandler\n#define TIM1_BRK_TIM15_IRQHandler     TIM1_BRK_IRQHandler\n#define TIM9_IRQHandler               TIM1_BRK_IRQHandler\n#define TIM1_BRK_TIM9_IRQHandler      TIM1_BRK_IRQHandler\n#define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler\n#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler\n#define TIM11_IRQHandler              TIM1_TRG_COM_IRQHandler\n#define TIM10_IRQHandler              TIM1_UP_IRQHandler\n#define TIM1_UP_TIM16_IRQHandler      TIM1_UP_IRQHandler\n#define TIM1_UP_TIM10_IRQHandler      TIM1_UP_IRQHandler\n#define OTG_FS_WKUP_IRQHandler        USBWakeUp_IRQHandler\n#define CEC_IRQHandler                USBWakeUp_IRQHandler\n#define CAN1_TX_IRQHandler            USB_HP_CAN1_TX_IRQHandler\n#define USB_HP_IRQHandler             USB_HP_CAN1_TX_IRQHandler\n#define CAN1_RX0_IRQHandler           USB_LP_CAN1_RX0_IRQHandler\n#define USB_LP_IRQHandler             USB_LP_CAN1_RX0_IRQHandler\n\n\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n\n\n#ifdef __cplusplus\n  }\n#endif /* __cplusplus */\n  \n#endif /* __STM32F103xB_H */\n  \n  \n  \n  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    stm32f1xx.h\n  * @author  MCD Application Team\n  * @brief   CMSIS STM32F1xx Device Peripheral Access Layer Header File. \n  *\n  *          The file is the unique include file that the application programmer\n  *          is using in the C source code, usually in main.c. This file contains:\n  *            - Configuration section that allows to select:\n  *              - The STM32F1xx device used in the target application\n  *              - To use or not the peripherals drivers in application code(i.e. \n  *                code will be based on direct access to peripherals registers \n  *                rather than drivers API), this option is controlled by \n  *                \"#define USE_HAL_DRIVER\"\n  *  \n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f1xx\n  * @{\n  */\n    \n#ifndef __STM32F1XX_H\n#define __STM32F1XX_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif /* __cplusplus */\n  \n/** @addtogroup Library_configuration_section\n  * @{\n  */\n\n/**\n  * @brief STM32 Family\n  */\n#if !defined (STM32F1)\n#define STM32F1\n#endif /* STM32F1 */\n\n/* Uncomment the line below according to the target STM32L device used in your \n   application \n  */\n\n#if !defined (STM32F100xB) && !defined (STM32F100xE) && !defined (STM32F101x6) && \\\n    !defined (STM32F101xB) && !defined (STM32F101xE) && !defined (STM32F101xG) && !defined (STM32F102x6) && !defined (STM32F102xB) && !defined (STM32F103x6) && \\\n    !defined (STM32F103xB) && !defined (STM32F103xE) && !defined (STM32F103xG) && !defined (STM32F105xC) && !defined (STM32F107xC)\n  /* #define STM32F100xB  */   /*!< STM32F100C4, STM32F100R4, STM32F100C6, STM32F100R6, STM32F100C8, STM32F100R8, STM32F100V8, STM32F100CB, STM32F100RB and STM32F100VB */\n  /* #define STM32F100xE */    /*!< STM32F100RC, STM32F100VC, STM32F100ZC, STM32F100RD, STM32F100VD, STM32F100ZD, STM32F100RE, STM32F100VE and STM32F100ZE */\n  /* #define STM32F101x6  */   /*!< STM32F101C4, STM32F101R4, STM32F101T4, STM32F101C6, STM32F101R6 and STM32F101T6 Devices */\n  /* #define STM32F101xB  */   /*!< STM32F101C8, STM32F101R8, STM32F101T8, STM32F101V8, STM32F101CB, STM32F101RB, STM32F101TB and STM32F101VB */\n  /* #define STM32F101xE */    /*!< STM32F101RC, STM32F101VC, STM32F101ZC, STM32F101RD, STM32F101VD, STM32F101ZD, STM32F101RE, STM32F101VE and STM32F101ZE */ \n  /* #define STM32F101xG  */   /*!< STM32F101RF, STM32F101VF, STM32F101ZF, STM32F101RG, STM32F101VG and STM32F101ZG */\n  /* #define STM32F102x6 */    /*!< STM32F102C4, STM32F102R4, STM32F102C6 and STM32F102R6 */\n  /* #define STM32F102xB  */   /*!< STM32F102C8, STM32F102R8, STM32F102CB and STM32F102RB */\n  /* #define STM32F103x6  */   /*!< STM32F103C4, STM32F103R4, STM32F103T4, STM32F103C6, STM32F103R6 and STM32F103T6 */\n  /* #define STM32F103xB  */   /*!< STM32F103C8, STM32F103R8, STM32F103T8, STM32F103V8, STM32F103CB, STM32F103RB, STM32F103TB and STM32F103VB */\n  /* #define STM32F103xE */    /*!< STM32F103RC, STM32F103VC, STM32F103ZC, STM32F103RD, STM32F103VD, STM32F103ZD, STM32F103RE, STM32F103VE and STM32F103ZE */\n  /* #define STM32F103xG  */   /*!< STM32F103RF, STM32F103VF, STM32F103ZF, STM32F103RG, STM32F103VG and STM32F103ZG */\n  /* #define STM32F105xC */    /*!< STM32F105R8, STM32F105V8, STM32F105RB, STM32F105VB, STM32F105RC and STM32F105VC */\n  /* #define STM32F107xC  */   /*!< STM32F107RB, STM32F107VB, STM32F107RC and STM32F107VC */  \n#endif\n\n/*  Tip: To avoid modifying this file each time you need to switch between these\n        devices, you can define the device in your toolchain compiler preprocessor.\n  */\n  \n#if !defined  (USE_HAL_DRIVER)\n/**\n * @brief Comment the line below if you will not use the peripherals drivers.\n   In this case, these drivers will not be included and the application code will \n   be based on direct access to peripherals registers \n   */\n  /*#define USE_HAL_DRIVER */\n#endif /* USE_HAL_DRIVER */\n\n/**\n  * @brief CMSIS Device version number V4.3.3\n  */\n#define __STM32F1_CMSIS_VERSION_MAIN   (0x04) /*!< [31:24] main version */\n#define __STM32F1_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */\n#define __STM32F1_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */\n#define __STM32F1_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ \n#define __STM32F1_CMSIS_VERSION        ((__STM32F1_CMSIS_VERSION_MAIN << 24)\\\n                                       |(__STM32F1_CMSIS_VERSION_SUB1 << 16)\\\n                                       |(__STM32F1_CMSIS_VERSION_SUB2 << 8 )\\\n                                       |(__STM32F1_CMSIS_VERSION_RC))\n\n/**\n  * @}\n  */\n\n/** @addtogroup Device_Included\n  * @{\n  */\n\n#if defined(STM32F100xB)\n  #include \"stm32f100xb.h\"\n#elif defined(STM32F100xE)\n  #include \"stm32f100xe.h\"\n#elif defined(STM32F101x6)\n  #include \"stm32f101x6.h\"\n#elif defined(STM32F101xB)\n  #include \"stm32f101xb.h\"\n#elif defined(STM32F101xE)\n  #include \"stm32f101xe.h\"\n#elif defined(STM32F101xG)\n  #include \"stm32f101xg.h\"\n#elif defined(STM32F102x6)\n  #include \"stm32f102x6.h\"\n#elif defined(STM32F102xB)\n  #include \"stm32f102xb.h\"\n#elif defined(STM32F103x6)\n  #include \"stm32f103x6.h\"\n#elif defined(STM32F103xB)\n  #include \"stm32f103xb.h\"\n#elif defined(STM32F103xE)\n  #include \"stm32f103xe.h\"\n#elif defined(STM32F103xG)\n  #include \"stm32f103xg.h\"\n#elif defined(STM32F105xC)\n  #include \"stm32f105xc.h\"\n#elif defined(STM32F107xC)\n  #include \"stm32f107xc.h\"\n#else\n #error \"Please select first the target STM32F1xx device used in your application (in stm32f1xx.h file)\"\n#endif\n\n/**\n  * @}\n  */\n\n/** @addtogroup Exported_types\n  * @{\n  */  \ntypedef enum \n{\n  RESET = 0, \n  SET = !RESET\n} FlagStatus, ITStatus;\n\ntypedef enum \n{\n  DISABLE = 0, \n  ENABLE = !DISABLE\n} FunctionalState;\n#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\n\ntypedef enum\n{\n  SUCCESS = 0U,\n  ERROR = !SUCCESS\n} ErrorStatus;\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup Exported_macros\n  * @{\n  */\n#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\n\n#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\n\n#define READ_BIT(REG, BIT)    ((REG) & (BIT))\n\n#define CLEAR_REG(REG)        ((REG) = (0x0))\n\n#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\n\n#define READ_REG(REG)         ((REG))\n\n#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\n\n#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) \n\n/* Use of CMSIS compiler intrinsics for register exclusive access */\n/* Atomic 32-bit register access macro to set one or several bits */\n#define ATOMIC_SET_BIT(REG, BIT)                             \\\n  do {                                                       \\\n    uint32_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEAR_BIT(REG, BIT)                           \\\n  do {                                                       \\\n    uint32_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 32-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \\\n  do {                                                                     \\\n    uint32_t val;                                                          \\\n    do {                                                                   \\\n      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\\n    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to set one or several bits */\n#define ATOMIC_SETH_BIT(REG, BIT)                            \\\n  do {                                                       \\\n    uint16_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to clear one or several bits */\n#define ATOMIC_CLEARH_BIT(REG, BIT)                          \\\n  do {                                                       \\\n    uint16_t val;                                            \\\n    do {                                                     \\\n      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\\n  } while(0)\n\n/* Atomic 16-bit register access macro to clear and set one or several bits */\n#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \\\n  do {                                                                     \\\n    uint16_t val;                                                          \\\n    do {                                                                   \\\n      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\\n    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \\\n  } while(0)\n\n\n/**\n  * @}\n  */\n\n#if defined (USE_HAL_DRIVER)\n #include \"stm32f1xx_hal.h\"\n#endif /* USE_HAL_DRIVER */\n\n\n#ifdef __cplusplus\n}\n#endif /* __cplusplus */\n\n#endif /* __STM32F1xx_H */\n/**\n  * @}\n  */\n\n/**\n  * @}\n  */\n  \n\n\n\n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h",
    "content": "/**\n  ******************************************************************************\n  * @file    system_stm32f10x.h\n  * @author  MCD Application Team\n  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.\n  ******************************************************************************\n  * @attention\n  *\n  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.\n  * All rights reserved.</center></h2>\n  *\n  * This software component is licensed by ST under BSD 3-Clause license,\n  * the \"License\"; You may not use this file except in compliance with the\n  * License. You may obtain a copy of the License at:\n  *                        opensource.org/licenses/BSD-3-Clause\n  *\n  ******************************************************************************\n  */\n\n/** @addtogroup CMSIS\n  * @{\n  */\n\n/** @addtogroup stm32f10x_system\n  * @{\n  */  \n  \n/**\n  * @brief Define to prevent recursive inclusion\n  */\n#ifndef __SYSTEM_STM32F10X_H\n#define __SYSTEM_STM32F10X_H\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif \n\n/** @addtogroup STM32F10x_System_Includes\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n\n/** @addtogroup STM32F10x_System_Exported_types\n  * @{\n  */\n\nextern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */\nextern const uint8_t  AHBPrescTable[16U];  /*!< AHB prescalers table values */\nextern const uint8_t  APBPrescTable[8U];   /*!< APB prescalers table values */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Constants\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Macros\n  * @{\n  */\n\n/**\n  * @}\n  */\n\n/** @addtogroup STM32F10x_System_Exported_Functions\n  * @{\n  */\n  \nextern void SystemInit(void);\nextern void SystemCoreClockUpdate(void);\n/**\n  * @}\n  */\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /*__SYSTEM_STM32F10X_H */\n\n/**\n  * @}\n  */\n  \n/**\n  * @}\n  */  \n/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/cmsis_armclang.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_armclang.h\n * @brief    CMSIS compiler armclang (Arm Compiler 6) header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */\n\n#ifndef __CMSIS_ARMCLANG_H\n#define __CMSIS_ARMCLANG_H\n\n#pragma clang system_header   /* treat file as system include file */\n\n#ifndef __ARM_COMPAT_H\n#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               __inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static __inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma clang diagnostic push\n  #pragma clang diagnostic ignored \"-Wpacked\"\n/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma clang diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __enable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n/* intrinsic void __disable_irq();  see arm_compat.h */\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr\n#else\n#define __get_FPSCR()      ((uint32_t)0U)\n#endif\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#define __set_FPSCR      __builtin_arm_set_fpscr\n#else\n#define __set_FPSCR(x)      ((void)(x))\n#endif\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP          __builtin_arm_nop\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI          __builtin_arm_wfi\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE          __builtin_arm_wfe\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV          __builtin_arm_sev\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n#define __ISB()        __builtin_arm_isb(0xF);\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n#define __DSB()        __builtin_arm_dsb(0xF);\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n#define __DMB()        __builtin_arm_dmb(0xF);\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV(value)   __builtin_bswap32(value)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REV16(value) __ROR(__REV(value), 16)\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __REVSH(value) (int16_t)__builtin_bswap16(value)\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)     __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n#define __RBIT            __builtin_arm_rbit\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define __LDREXB        (uint8_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define __LDREXH        (uint16_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define __LDREXW        (uint32_t)__builtin_arm_ldrex\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXB        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXH        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define __STREXW        (uint32_t)__builtin_arm_strex\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n#define __CLREX             __builtin_arm_clrex\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT             __builtin_arm_ssat\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT             __builtin_arm_usat\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n  uint32_t result;\n\n  __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n  return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n  __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n  __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n  __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXB                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEXH                 (uint32_t)__builtin_arm_stlex\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n#define     __STLEX                  (uint32_t)__builtin_arm_stlex\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n  int32_t result;\n\n  __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#endif /* __CMSIS_ARMCLANG_H */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/cmsis_compiler.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_compiler.h\n * @brief    CMSIS compiler generic header file\n * @version  V5.0.4\n * @date     10. January 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_COMPILER_H\n#define __CMSIS_COMPILER_H\n\n#include <stdint.h>\n\n/*\n * Arm Compiler 4/5\n */\n#if   defined ( __CC_ARM )\n  #include \"cmsis_armcc.h\"\n\n\n/*\n * Arm Compiler 6 (armclang)\n */\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #include \"cmsis_armclang.h\"\n\n\n/*\n * GNU Compiler\n */\n#elif defined ( __GNUC__ )\n  #include \"cmsis_gcc.h\"\n\n\n/*\n * IAR Compiler\n */\n#elif defined ( __ICCARM__ )\n  #include <cmsis_iccarm.h>\n\n\n/*\n * TI Arm Compiler\n */\n#elif defined ( __TI_ARM__ )\n  #include <cmsis_ccs.h>\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __attribute__((packed))\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __attribute__((packed))\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)                           __attribute__((aligned(x)))\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * TASKING Compiler\n */\n#elif defined ( __TASKING__ )\n  /*\n   * The CMSIS functions have been implemented as intrinsics in the compiler.\n   * Please use \"carm -?i\" to get an up to date list of all intrinsics,\n   * Including the CMSIS ones.\n   */\n\n  #ifndef   __ASM\n    #define __ASM                                  __asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    #define __NO_RETURN                            __attribute__((noreturn))\n  #endif\n  #ifndef   __USED\n    #define __USED                                 __attribute__((used))\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __attribute__((weak))\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               __packed__\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        struct __packed__\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         union __packed__\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    struct __packed__ T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #define __ALIGNED(x)              __align(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n/*\n * COSMIC Compiler\n */\n#elif defined ( __CSMC__ )\n   #include <cmsis_csm.h>\n\n #ifndef   __ASM\n    #define __ASM                                  _asm\n  #endif\n  #ifndef   __INLINE\n    #define __INLINE                               inline\n  #endif\n  #ifndef   __STATIC_INLINE\n    #define __STATIC_INLINE                        static inline\n  #endif\n  #ifndef   __STATIC_FORCEINLINE\n    #define __STATIC_FORCEINLINE                   __STATIC_INLINE\n  #endif\n  #ifndef   __NO_RETURN\n    // NO RETURN is automatically detected hence no warning here\n    #define __NO_RETURN\n  #endif\n  #ifndef   __USED\n    #warning No compiler specific solution for __USED. __USED is ignored.\n    #define __USED\n  #endif\n  #ifndef   __WEAK\n    #define __WEAK                                 __weak\n  #endif\n  #ifndef   __PACKED\n    #define __PACKED                               @packed\n  #endif\n  #ifndef   __PACKED_STRUCT\n    #define __PACKED_STRUCT                        @packed struct\n  #endif\n  #ifndef   __PACKED_UNION\n    #define __PACKED_UNION                         @packed union\n  #endif\n  #ifndef   __UNALIGNED_UINT32        /* deprecated */\n    @packed struct T_UINT32 { uint32_t v; };\n    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT16_WRITE\n    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT16_READ\n    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __UNALIGNED_UINT32_WRITE\n    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n  #endif\n  #ifndef   __UNALIGNED_UINT32_READ\n    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n  #endif\n  #ifndef   __ALIGNED\n    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.\n    #define __ALIGNED(x)\n  #endif\n  #ifndef   __RESTRICT\n    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.\n    #define __RESTRICT\n  #endif\n\n\n#else\n  #error Unknown compiler.\n#endif\n\n\n#endif /* __CMSIS_COMPILER_H */\n\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/cmsis_gcc.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_gcc.h\n * @brief    CMSIS compiler GCC header file\n * @version  V5.0.4\n * @date     09. April 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#ifndef __CMSIS_GCC_H\n#define __CMSIS_GCC_H\n\n/* ignore some GCC warnings */\n#pragma GCC diagnostic push\n#pragma GCC diagnostic ignored \"-Wsign-conversion\"\n#pragma GCC diagnostic ignored \"-Wconversion\"\n#pragma GCC diagnostic ignored \"-Wunused-parameter\"\n\n/* Fallback for __has_builtin */\n#ifndef __has_builtin\n  #define __has_builtin(x) (0)\n#endif\n\n/* CMSIS compiler specific defines */\n#ifndef   __ASM\n  #define __ASM                                  __asm\n#endif\n#ifndef   __INLINE\n  #define __INLINE                               inline\n#endif\n#ifndef   __STATIC_INLINE\n  #define __STATIC_INLINE                        static inline\n#endif\n#ifndef   __STATIC_FORCEINLINE                 \n  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline\n#endif                                           \n#ifndef   __NO_RETURN\n  #define __NO_RETURN                            __attribute__((__noreturn__))\n#endif\n#ifndef   __USED\n  #define __USED                                 __attribute__((used))\n#endif\n#ifndef   __WEAK\n  #define __WEAK                                 __attribute__((weak))\n#endif\n#ifndef   __PACKED\n  #define __PACKED                               __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_STRUCT\n  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __PACKED_UNION\n  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))\n#endif\n#ifndef   __UNALIGNED_UINT32        /* deprecated */\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  struct __attribute__((packed)) T_UINT32 { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)\n#endif\n#ifndef   __UNALIGNED_UINT16_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT16_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __UNALIGNED_UINT32_WRITE\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))\n#endif\n#ifndef   __UNALIGNED_UINT32_READ\n  #pragma GCC diagnostic push\n  #pragma GCC diagnostic ignored \"-Wpacked\"\n  #pragma GCC diagnostic ignored \"-Wattributes\"\n  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };\n  #pragma GCC diagnostic pop\n  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)\n#endif\n#ifndef   __ALIGNED\n  #define __ALIGNED(x)                           __attribute__((aligned(x)))\n#endif\n#ifndef   __RESTRICT\n  #define __RESTRICT                             __restrict\n#endif\n\n\n/* ###########################  Core Function Access  ########################### */\n/** \\ingroup  CMSIS_Core_FunctionInterface\n    \\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\n  @{\n */\n\n/**\n  \\brief   Enable IRQ Interrupts\n  \\details Enables IRQ interrupts by clearing the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_irq(void)\n{\n  __ASM volatile (\"cpsie i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable IRQ Interrupts\n  \\details Disables IRQ interrupts by setting the I-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_irq(void)\n{\n  __ASM volatile (\"cpsid i\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Control Register\n  \\details Returns the content of the Control Register.\n  \\return               Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Control Register (non-secure)\n  \\details Returns the content of the non-secure Control Register when in secure mode.\n  \\return               non-secure Control Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, control_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Control Register\n  \\details Writes the given value to the Control Register.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)\n{\n  __ASM volatile (\"MSR control, %0\" : : \"r\" (control) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Control Register (non-secure)\n  \\details Writes the given value to the non-secure Control Register when in secure state.\n  \\param [in]    control  Control Register value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)\n{\n  __ASM volatile (\"MSR control_ns, %0\" : : \"r\" (control) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Get IPSR Register\n  \\details Returns the content of the IPSR Register.\n  \\return               IPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_IPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, ipsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get APSR Register\n  \\details Returns the content of the APSR Register.\n  \\return               APSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_APSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, apsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get xPSR Register\n  \\details Returns the content of the xPSR Register.\n  \\return               xPSR Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_xPSR(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, xpsr\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Get Process Stack Pointer\n  \\details Returns the current value of the Process Stack Pointer (PSP).\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp\"  : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\return               PSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, psp_ns\"  : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer\n  \\details Assigns the given value to the Process Stack Pointer (PSP).\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp, %0\" : : \"r\" (topOfProcStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.\n  \\param [in]    topOfProcStack  Process Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)\n{\n  __ASM volatile (\"MSR psp_ns, %0\" : : \"r\" (topOfProcStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer\n  \\details Returns the current value of the Main Stack Pointer (MSP).\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSP(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Main Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\return               MSP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, msp_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer\n  \\details Assigns the given value to the Main Stack Pointer (MSP).\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp, %0\" : : \"r\" (topOfMainStack) : );\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Main Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.\n  \\param [in]    topOfMainStack  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)\n{\n  __ASM volatile (\"MSR msp_ns, %0\" : : \"r\" (topOfMainStack) : );\n}\n#endif\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Stack Pointer (non-secure)\n  \\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.\n  \\return               SP Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, sp_ns\" : \"=r\" (result) );\n  return(result);\n}\n\n\n/**\n  \\brief   Set Stack Pointer (non-secure)\n  \\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.\n  \\param [in]    topOfStack  Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)\n{\n  __ASM volatile (\"MSR sp_ns, %0\" : : \"r\" (topOfStack) : );\n}\n#endif\n\n\n/**\n  \\brief   Get Priority Mask\n  \\details Returns the current state of the priority mask bit from the Priority Mask Register.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Priority Mask (non-secure)\n  \\details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.\n  \\return               Priority Mask value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, primask_ns\" : \"=r\" (result) :: \"memory\");\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Priority Mask\n  \\details Assigns the given value to the Priority Mask Register.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask, %0\" : : \"r\" (priMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Priority Mask (non-secure)\n  \\details Assigns the given value to the non-secure Priority Mask Register when in secure state.\n  \\param [in]    priMask  Priority Mask\n */\n__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)\n{\n  __ASM volatile (\"MSR primask_ns, %0\" : : \"r\" (priMask) : \"memory\");\n}\n#endif\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Enable FIQ\n  \\details Enables FIQ interrupts by clearing the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __enable_fault_irq(void)\n{\n  __ASM volatile (\"cpsie f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Disable FIQ\n  \\details Disables FIQ interrupts by setting the F-bit in the CPSR.\n           Can only be executed in Privileged modes.\n */\n__STATIC_FORCEINLINE void __disable_fault_irq(void)\n{\n  __ASM volatile (\"cpsid f\" : : : \"memory\");\n}\n\n\n/**\n  \\brief   Get Base Priority\n  \\details Returns the current value of the Base Priority register.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Base Priority (non-secure)\n  \\details Returns the current value of the non-secure Base Priority register when in secure state.\n  \\return               Base Priority register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, basepri_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority\n  \\details Assigns the given value to the Base Priority register.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Base Priority (non-secure)\n  \\details Assigns the given value to the non-secure Base Priority register when in secure state.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_ns, %0\" : : \"r\" (basePri) : \"memory\");\n}\n#endif\n\n\n/**\n  \\brief   Set Base Priority with condition\n  \\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\n           or the new value increases the BASEPRI priority level.\n  \\param [in]    basePri  Base Priority value to set\n */\n__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)\n{\n  __ASM volatile (\"MSR basepri_max, %0\" : : \"r\" (basePri) : \"memory\");\n}\n\n\n/**\n  \\brief   Get Fault Mask\n  \\details Returns the current value of the Fault Mask register.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask\" : \"=r\" (result) );\n  return(result);\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Fault Mask (non-secure)\n  \\details Returns the current value of the non-secure Fault Mask register when in secure state.\n  \\return               Fault Mask register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)\n{\n  uint32_t result;\n\n  __ASM volatile (\"MRS %0, faultmask_ns\" : \"=r\" (result) );\n  return(result);\n}\n#endif\n\n\n/**\n  \\brief   Set Fault Mask\n  \\details Assigns the given value to the Fault Mask register.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Set Fault Mask (non-secure)\n  \\details Assigns the given value to the non-secure Fault Mask register when in secure state.\n  \\param [in]    faultMask  Fault Mask value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)\n{\n  __ASM volatile (\"MSR faultmask_ns, %0\" : : \"r\" (faultMask) : \"memory\");\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n\n/**\n  \\brief   Get Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n  \n  \\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n    // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n\n#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))\n/**\n  \\brief   Get Process Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\return               PSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, psplim_ns\"  : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Process Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n  \n  \\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim, %0\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Process Stack Pointer (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.\n  \\param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure PSPLIM is RAZ/WI\n  (void)ProcStackPtrLimit;\n#else\n  __ASM volatile (\"MSR psplim_ns, %0\\n\" : : \"r\" (ProcStackPtrLimit));\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Get Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always in non-secure\n  mode.\n\n  \\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim\" : \"=r\" (result) );\n  return result;\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Get Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence zero is returned always.\n\n  \\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.\n  \\return               MSPLIM Register value\n */\n__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  return 0U;\n#else\n  uint32_t result;\n  __ASM volatile (\"MRS %0, msplim_ns\" : \"=r\" (result) );\n  return result;\n#endif\n}\n#endif\n\n\n/**\n  \\brief   Set Main Stack Pointer Limit\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored in non-secure\n  mode.\n\n  \\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set\n */\n__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \\\n    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n\n\n#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))\n/**\n  \\brief   Set Main Stack Pointer Limit (non-secure)\n  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure\n  Stack Pointer Limit register hence the write is silently ignored.\n\n  \\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.\n  \\param [in]    MainStackPtrLimit  Main Stack Pointer value to set\n */\n__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)\n{\n#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))\n  // without main extensions, the non-secure MSPLIM is RAZ/WI\n  (void)MainStackPtrLimit;\n#else\n  __ASM volatile (\"MSR msplim_ns, %0\" : : \"r\" (MainStackPtrLimit));\n#endif\n}\n#endif\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n/**\n  \\brief   Get FPSCR\n  \\details Returns the current value of the Floating Point Status/Control register.\n  \\return               Floating Point Status/Control register value\n */\n__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_get_fpscr) \n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  return __builtin_arm_get_fpscr();\n#else\n  uint32_t result;\n\n  __ASM volatile (\"VMRS %0, fpscr\" : \"=r\" (result) );\n  return(result);\n#endif\n#else\n  return(0U);\n#endif\n}\n\n\n/**\n  \\brief   Set FPSCR\n  \\details Assigns the given value to the Floating Point Status/Control register.\n  \\param [in]    fpscr  Floating Point Status/Control value to set\n */\n__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)\n{\n#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \\\n     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )\n#if __has_builtin(__builtin_arm_set_fpscr)\n// Re-enable using built-in when GCC has been fixed\n// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)\n  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */\n  __builtin_arm_set_fpscr(fpscr);\n#else\n  __ASM volatile (\"VMSR fpscr, %0\" : : \"r\" (fpscr) : \"vfpcc\", \"memory\");\n#endif\n#else\n  (void)fpscr;\n#endif\n}\n\n\n/*@} end of CMSIS_Core_RegAccFunctions */\n\n\n/* ##########################  Core Instruction Access  ######################### */\n/** \\defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\n  Access to dedicated instructions\n  @{\n*/\n\n/* Define macros for porting to both thumb1 and thumb2.\n * For thumb1, use low register (r0-r7), specified by constraint \"l\"\n * Otherwise, use general registers, specified by constraint \"r\" */\n#if defined (__thumb__) && !defined (__thumb2__)\n#define __CMSIS_GCC_OUT_REG(r) \"=l\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+l\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"l\" (r)\n#else\n#define __CMSIS_GCC_OUT_REG(r) \"=r\" (r)\n#define __CMSIS_GCC_RW_REG(r) \"+r\" (r)\n#define __CMSIS_GCC_USE_REG(r) \"r\" (r)\n#endif\n\n/**\n  \\brief   No Operation\n  \\details No Operation does nothing. This instruction can be used for code alignment purposes.\n */\n#define __NOP()                             __ASM volatile (\"nop\")\n\n/**\n  \\brief   Wait For Interrupt\n  \\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\n */\n#define __WFI()                             __ASM volatile (\"wfi\")\n\n\n/**\n  \\brief   Wait For Event\n  \\details Wait For Event is a hint instruction that permits the processor to enter\n           a low-power state until one of a number of events occurs.\n */\n#define __WFE()                             __ASM volatile (\"wfe\")\n\n\n/**\n  \\brief   Send Event\n  \\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\n */\n#define __SEV()                             __ASM volatile (\"sev\")\n\n\n/**\n  \\brief   Instruction Synchronization Barrier\n  \\details Instruction Synchronization Barrier flushes the pipeline in the processor,\n           so that all instructions following the ISB are fetched from cache or memory,\n           after the instruction has been completed.\n */\n__STATIC_FORCEINLINE void __ISB(void)\n{\n  __ASM volatile (\"isb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Synchronization Barrier\n  \\details Acts as a special kind of Data Memory Barrier.\n           It completes when all explicit memory accesses before this instruction complete.\n */\n__STATIC_FORCEINLINE void __DSB(void)\n{\n  __ASM volatile (\"dsb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Data Memory Barrier\n  \\details Ensures the apparent order of the explicit memory operations before\n           and after the instruction, without ensuring their completion.\n */\n__STATIC_FORCEINLINE void __DMB(void)\n{\n  __ASM volatile (\"dmb 0xF\":::\"memory\");\n}\n\n\n/**\n  \\brief   Reverse byte order (32 bit)\n  \\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\n  return __builtin_bswap32(value);\n#else\n  uint32_t result;\n\n  __ASM volatile (\"rev %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rev16 %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n}\n\n\n/**\n  \\brief   Reverse byte order (16 bit)\n  \\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)\n{\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n  return (int16_t)__builtin_bswap16(value);\n#else\n  int16_t result;\n\n  __ASM volatile (\"revsh %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return result;\n#endif\n}\n\n\n/**\n  \\brief   Rotate Right in unsigned value (32 bit)\n  \\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\n  \\param [in]    op1  Value to rotate\n  \\param [in]    op2  Number of Bits to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\n{\n  op2 %= 32U;\n  if (op2 == 0U)\n  {\n    return op1;\n  }\n  return (op1 >> op2) | (op1 << (32U - op2));\n}\n\n\n/**\n  \\brief   Breakpoint\n  \\details Causes the processor to enter Debug state.\n           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\n  \\param [in]    value  is ignored by the processor.\n                 If required, a debugger can use it to store additional information about the breakpoint.\n */\n#define __BKPT(value)                       __ASM volatile (\"bkpt \"#value)\n\n\n/**\n  \\brief   Reverse bit order of value\n  \\details Reverses the bit order of the given value.\n  \\param [in]    value  Value to reverse\n  \\return               Reversed value\n */\n__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)\n{\n  uint32_t result;\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n   __ASM volatile (\"rbit %0, %1\" : \"=r\" (result) : \"r\" (value) );\n#else\n  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */\n\n  result = value;                      /* r will be reversed bits of v; first get LSB of v */\n  for (value >>= 1U; value != 0U; value >>= 1U)\n  {\n    result <<= 1U;\n    result |= value & 1U;\n    s--;\n  }\n  result <<= s;                        /* shift when v's highest bits are zero */\n#endif\n  return result;\n}\n\n\n/**\n  \\brief   Count leading zeros\n  \\details Counts the number of leading zeros of a data value.\n  \\param [in]  value  Value to count the leading zeros\n  \\return             number of leading zeros in value\n */\n#define __CLZ             (uint8_t)__builtin_clz\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   LDR Exclusive (8 bit)\n  \\details Executes a exclusive LDR instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexb %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexb %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (16 bit)\n  \\details Executes a exclusive LDR instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrexh %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrexh %0, [%1]\" : \"=r\" (result) : \"r\" (addr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDR Exclusive (32 bit)\n  \\details Executes a exclusive LDR instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrex %0, %1\" : \"=r\" (result) : \"Q\" (*addr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (8 bit)\n  \\details Executes a exclusive STR instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (16 bit)\n  \\details Executes a exclusive STR instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   STR Exclusive (32 bit)\n  \\details Executes a exclusive STR instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"strex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*addr) : \"r\" (value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Remove the exclusive lock\n  \\details Removes the exclusive lock which is created by LDREX.\n */\n__STATIC_FORCEINLINE void __CLREX(void)\n{\n  __ASM volatile (\"clrex\" ::: \"memory\");\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n#define __SSAT(ARG1,ARG2) \\\n__extension__ \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  ARG1  Value to be saturated\n  \\param [in]  ARG2  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n#define __USAT(ARG1,ARG2) \\\n __extension__ \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n\n/**\n  \\brief   Rotate Right with Extend (32 bit)\n  \\details Moves each bit of a bitstring right by one bit.\n           The carry input is shifted in at the left end of the bitstring.\n  \\param [in]    value  Value to rotate\n  \\return               Rotated value\n */\n__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)\n{\n  uint32_t result;\n\n  __ASM volatile (\"rrx %0, %1\" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\n  return(result);\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged LDRT instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrbt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrbt %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint8_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged LDRT instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\n   __ASM volatile (\"ldrht %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n#else\n    /* Prior to GCC 4.8, \"Q\" will be expanded to [rx, #0] which is not\n       accepted by assembler. So has to use following less efficient pattern.\n    */\n   __ASM volatile (\"ldrht %0, [%1]\" : \"=r\" (result) : \"r\" (ptr) : \"memory\" );\n#endif\n   return ((uint16_t) result);    /* Add explicit type cast here */\n}\n\n\n/**\n  \\brief   LDRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged LDRT instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldrt %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   STRT Unprivileged (8 bit)\n  \\details Executes a Unprivileged STRT instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"strbt %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (16 bit)\n  \\details Executes a Unprivileged STRT instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"strht %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   STRT Unprivileged (32 bit)\n  \\details Executes a Unprivileged STRT instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"strt %1, %0\" : \"=Q\" (*ptr) : \"r\" (value) );\n}\n\n#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n/**\n  \\brief   Signed Saturate\n  \\details Saturates a signed value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (1..32)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)\n{\n  if ((sat >= 1U) && (sat <= 32U))\n  {\n    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);\n    const int32_t min = -1 - max ;\n    if (val > max)\n    {\n      return max;\n    }\n    else if (val < min)\n    {\n      return min;\n    }\n  }\n  return val;\n}\n\n/**\n  \\brief   Unsigned Saturate\n  \\details Saturates an unsigned value.\n  \\param [in]  value  Value to be saturated\n  \\param [in]    sat  Bit position to saturate to (0..31)\n  \\return             Saturated value\n */\n__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)\n{\n  if (sat <= 31U)\n  {\n    const uint32_t max = ((1U << sat) - 1U);\n    if (val > (int32_t)max)\n    {\n      return max;\n    }\n    else if (val < 0)\n    {\n      return 0U;\n    }\n  }\n  return (uint32_t)val;\n}\n\n#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \\\n           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \\\n           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */\n\n\n#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )\n/**\n  \\brief   Load-Acquire (8 bit)\n  \\details Executes a LDAB instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldab %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (16 bit)\n  \\details Executes a LDAH instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldah %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire (32 bit)\n  \\details Executes a LDA instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"lda %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release (8 bit)\n  \\details Executes a STLB instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)\n{\n   __ASM volatile (\"stlb %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (16 bit)\n  \\details Executes a STLH instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)\n{\n   __ASM volatile (\"stlh %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Store-Release (32 bit)\n  \\details Executes a STL instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n */\n__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)\n{\n   __ASM volatile (\"stl %1, %0\" : \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (8 bit)\n  \\details Executes a LDAB exclusive instruction for 8 bit value.\n  \\param [in]    ptr  Pointer to data\n  \\return             value of type uint8_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexb %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint8_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (16 bit)\n  \\details Executes a LDAH exclusive instruction for 16 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint16_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaexh %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return ((uint16_t) result);\n}\n\n\n/**\n  \\brief   Load-Acquire Exclusive (32 bit)\n  \\details Executes a LDA exclusive instruction for 32 bit values.\n  \\param [in]    ptr  Pointer to data\n  \\return        value of type uint32_t at (*ptr)\n */\n__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)\n{\n    uint32_t result;\n\n   __ASM volatile (\"ldaex %0, %1\" : \"=r\" (result) : \"Q\" (*ptr) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (8 bit)\n  \\details Executes a STLB exclusive instruction for 8 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexb %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (16 bit)\n  \\details Executes a STLH exclusive instruction for 16 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlexh %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n\n/**\n  \\brief   Store-Release Exclusive (32 bit)\n  \\details Executes a STL exclusive instruction for 32 bit values.\n  \\param [in]  value  Value to store\n  \\param [in]    ptr  Pointer to location\n  \\return          0  Function succeeded\n  \\return          1  Function failed\n */\n__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)\n{\n   uint32_t result;\n\n   __ASM volatile (\"stlex %0, %2, %1\" : \"=&r\" (result), \"=Q\" (*ptr) : \"r\" ((uint32_t)value) );\n   return(result);\n}\n\n#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \\\n           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */\n\n/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\n\n\n/* ###################  Compiler specific Intrinsics  ########################### */\n/** \\defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\n  Access to dedicated SIMD instructions\n  @{\n*/\n\n#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))\n\n__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n\n__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhadd16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsub16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhasx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"ssax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"qsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"shsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uqsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uhsax %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usad8 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"usada8 %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n#define __SSAT16(ARG1,ARG2) \\\n({                          \\\n  int32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"ssat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n#define __USAT16(ARG1,ARG2) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1); \\\n  __ASM (\"usat16 %0, %1, %2\" : \"=r\" (__RES) :  \"I\" (ARG2), \"r\" (__ARG1) ); \\\n  __RES; \\\n })\n\n__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"uxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtb16 %0, %1\" : \"=r\" (result) : \"r\" (op1));\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sxtab16 %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuad %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smuadx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlad %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smladx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlald %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlaldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smusdx %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsd %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\n{\n  uint32_t result;\n\n  __ASM volatile (\"smlsdx %0, %1, %2, %3\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2), \"r\" (op3) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsld %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\n{\n  union llreg_u{\n    uint32_t w32[2];\n    uint64_t w64;\n  } llr;\n  llr.w64 = acc;\n\n#ifndef __ARMEB__   /* Little endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[0]), \"=r\" (llr.w32[1]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[0]), \"1\" (llr.w32[1]) );\n#else               /* Big endian */\n  __ASM volatile (\"smlsldx %0, %1, %2, %3\" : \"=r\" (llr.w32[1]), \"=r\" (llr.w32[0]): \"r\" (op1), \"r\" (op2) , \"0\" (llr.w32[1]), \"1\" (llr.w32[0]) );\n#endif\n\n  return(llr.w64);\n}\n\n__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\n{\n  uint32_t result;\n\n  __ASM volatile (\"sel %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qadd %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\n{\n  int32_t result;\n\n  __ASM volatile (\"qsub %0, %1, %2\" : \"=r\" (result) : \"r\" (op1), \"r\" (op2) );\n  return(result);\n}\n\n#if 0\n#define __PKHBT(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  __ASM (\"pkhbt %0, %1, %2, lsl %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n\n#define __PKHTB(ARG1,ARG2,ARG3) \\\n({                          \\\n  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\\n  if (ARG3 == 0) \\\n    __ASM (\"pkhtb %0, %1, %2\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2)  ); \\\n  else \\\n    __ASM (\"pkhtb %0, %1, %2, asr %3\" : \"=r\" (__RES) :  \"r\" (__ARG1), \"r\" (__ARG2), \"I\" (ARG3)  ); \\\n  __RES; \\\n })\n#endif\n\n#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \\\n                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )\n\n#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \\\n                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )\n\n__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\n{\n int32_t result;\n\n __ASM volatile (\"smmla %0, %1, %2, %3\" : \"=r\" (result): \"r\"  (op1), \"r\" (op2), \"r\" (op3) );\n return(result);\n}\n\n#endif /* (__ARM_FEATURE_DSP == 1) */\n/*@} end of group CMSIS_SIMD_intrinsics */\n\n\n#pragma GCC diagnostic pop\n\n#endif /* __CMSIS_GCC_H */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/cmsis_version.h",
    "content": "/**************************************************************************//**\n * @file     cmsis_version.h\n * @brief    CMSIS Core(M) Version definitions\n * @version  V5.0.2\n * @date     19. April 2017\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2017 ARM Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CMSIS_VERSION_H\n#define __CMSIS_VERSION_H\n\n/*  CMSIS Version definitions */\n#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */\n#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */\n#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \\\n                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */\n#endif\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/core_cm0.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0.h\n * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File\n * @version  V5.0.5\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0_H_GENERIC\n#define __CORE_CM0_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M0\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0 definitions */\n#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0_H_DEPENDANT\n#define __CORE_CM0_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0_REV\n    #define __CM0_REV               0x0000U\n    #warning \"__CM0_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M0 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/core_cm0plus.h",
    "content": "/**************************************************************************//**\n * @file     core_cm0plus.h\n * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File\n * @version  V5.0.6\n * @date     28. May 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM0PLUS_H_GENERIC\n#define __CORE_CM0PLUS_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex-M0+\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM0+ definitions */\n#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \\\n                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM0PLUS_H_DEPENDANT\n#define __CORE_CM0PLUS_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM0PLUS_REV\n    #define __CM0PLUS_REV             0x0000U\n    #warning \"__CM0PLUS_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex-M0+ */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M0+ header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n    uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM0PLUS_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/core_cm1.h",
    "content": "/**************************************************************************//**\n * @file     core_cm1.h\n * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File\n * @version  V1.0.0\n * @date     23. July 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM1_H_GENERIC\n#define __CORE_CM1_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M1\n  @{\n */\n\n#include \"cmsis_version.h\"\n \n/*  CMSIS CM1 definitions */\n#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM1_H_DEPENDANT\n#define __CORE_CM1_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM1_REV\n    #define __CM1_REV               0x0100U\n    #warning \"__CM1_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M1 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[31U];\n  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[31U];\n  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[31U];\n  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[31U];\n        uint32_t RESERVED4[64U];\n  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n        uint32_t RESERVED0;\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n} SCnSCB_Type;\n\n/* Auxiliary Control Register Definitions */\n#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */\n\n#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */\n#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.\n            Therefore they are not covered by the Cortex-M1 header file.\n  @{\n */\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           Address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)0x0U;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM1_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/core_cm23.h",
    "content": "/**************************************************************************//**\n * @file     core_cm23.h\n * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File\n * @version  V5.0.7\n * @date     22. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM23_H_GENERIC\n#define __CORE_CM23_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M23\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS definitions */\n#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \\\n                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM23_H_DEPENDANT\n#define __CORE_CM23_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM23_REV\n    #define __CM23_REV                0x0000U\n    #warning \"__CM23_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __FPU_PRESENT\n    #define __FPU_PRESENT             0U\n    #warning \"__FPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __SAUREGION_PRESENT\n    #define __SAUREGION_PRESENT       0U\n    #warning \"__SAUREGION_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __VTOR_PRESENT\n    #define __VTOR_PRESENT            0U\n    #warning \"__VTOR_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          2U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __ETM_PRESENT\n    #define __ETM_PRESENT             0U\n    #warning \"__ETM_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MTB_PRESENT\n    #define __MTB_PRESENT             0U\n    #warning \"__MTB_PRESENT not defined in device header file; using default!\"\n  #endif\n\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M23 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n  - Core SAU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */\n    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[16U];\n  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[16U];\n  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[16U];\n  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[16U];\n  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[16U];\n  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */\n        uint32_t RESERVED5[16U];\n  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */\n}  NVIC_Type;\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n#else\n        uint32_t RESERVED0;\n#endif\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n        uint32_t RESERVED1;\n  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */\n#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */\n\n#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */\n#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */\n\n#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */\n#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */\n#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n/* SCB Vector Table Offset Register Definitions */\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */\n#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */\n\n#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */\n#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */\n\n#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */\n#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */\n#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */\n#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */\n\n#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */\n#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */\n\n#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */\n#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */\n\n#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */\n#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */\n#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */\n#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */\n\n#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */\n#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n        uint32_t RESERVED0[6U];\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n        uint32_t RESERVED3[1U];\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n        uint32_t RESERVED5[1U];\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED6[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n        uint32_t RESERVED7[1U];\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n        uint32_t RESERVED8[1U];\n  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */\n        uint32_t RESERVED9[1U];\n  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */\n        uint32_t RESERVED10[1U];\n  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */\n        uint32_t RESERVED11[1U];\n  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */\n        uint32_t RESERVED12[1U];\n  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */\n        uint32_t RESERVED13[1U];\n  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */\n        uint32_t RESERVED14[1U];\n  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */\n        uint32_t RESERVED15[1U];\n  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */\n        uint32_t RESERVED16[1U];\n  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */\n        uint32_t RESERVED17[1U];\n  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */\n        uint32_t RESERVED18[1U];\n  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */\n        uint32_t RESERVED19[1U];\n  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */\n        uint32_t RESERVED20[1U];\n  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */\n        uint32_t RESERVED21[1U];\n  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */\n        uint32_t RESERVED22[1U];\n  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */\n        uint32_t RESERVED23[1U];\n  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */\n        uint32_t RESERVED24[1U];\n  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */\n        uint32_t RESERVED25[1U];\n  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */\n        uint32_t RESERVED26[1U];\n  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */\n        uint32_t RESERVED27[1U];\n  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */\n        uint32_t RESERVED28[1U];\n  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */\n        uint32_t RESERVED29[1U];\n  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */\n        uint32_t RESERVED30[1U];\n  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */\n        uint32_t RESERVED31[1U];\n  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */\n#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */\n\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */\n#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */\n\n#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */\n#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */\n  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */\n  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */\n#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration Test FIFO Test Data 0 Register Definitions */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */\n#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */\n#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */\n#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */\n\n#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */\n#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 2 Register Definitions */\n#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */\n#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */\n#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */\n#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */\n\n#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */\n#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */\n\n/* TPI Integration Test FIFO Test Data 1 Register Definitions */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */\n#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */\n#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */\n\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */\n#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */\n#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */\n#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */\n\n#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */\n#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */\n\n/* TPI Integration Test ATB Control Register 0 Definitions */\n#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */\n#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */\n\n#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */\n#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */\n\n#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */\n#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */\n\n#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */\n#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */\n#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */\n        uint32_t RESERVED0[7U];\n  union {\n  __IOM uint32_t MAIR[2];\n  struct {\n  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */\n  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */\n  };\n  };\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  1U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */\n#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */\n\n#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */\n#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */\n\n#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */\n#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */\n\n#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */\n#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */\n\n/* MPU Region Limit Address Register Definitions */\n#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */\n#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */\n\n#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */\n#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */\n\n#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */\n#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */\n\n/* MPU Memory Attribute Indirection Register 0 Definitions */\n#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */\n#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */\n\n#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */\n#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */\n\n#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */\n#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */\n\n#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */\n#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */\n\n/* MPU Memory Attribute Indirection Register 1 Definitions */\n#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */\n#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */\n\n#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */\n#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */\n\n#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */\n#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */\n\n#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */\n#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SAU     Security Attribution Unit (SAU)\n  \\brief    Type definitions for the Security Attribution Unit (SAU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Security Attribution Unit (SAU).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */\n  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */\n#endif\n} SAU_Type;\n\n/* SAU Control Register Definitions */\n#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */\n#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */\n\n#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */\n#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */\n\n/* SAU Type Register Definitions */\n#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */\n#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */\n\n#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)\n/* SAU Region Number Register Definitions */\n#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */\n#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */\n\n/* SAU Region Base Address Register Definitions */\n#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */\n#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */\n\n/* SAU Region Limit Address Register Definitions */\n#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */\n#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */\n\n#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */\n#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */\n\n#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */\n#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */\n\n#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */\n\n/*@} end of group CMSIS_SAU */\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n        uint32_t RESERVED4[1U];\n  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */\n  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */\n#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register */\n#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */\n#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/* Debug Authentication Control Register Definitions */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */\n#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */\n\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */\n\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */\n#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */\n\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */\n#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */\n\n/* Debug Security Control and Status Register Definitions */\n#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */\n#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */\n\n#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */\n#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */\n\n#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */\n#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */\n  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */\n  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */\n  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */\n  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */\n  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */\n  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */\n\n\n  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */\n  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */\n  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */\n  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */\n  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */\n  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */\n    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */\n  #endif\n\n  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */\n    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */\n  #endif\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */\n  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */\n  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */\n  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */\n  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */\n\n  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */\n  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */\n  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */\n  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */\n\n  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */\n    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */\n  #endif\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */\n/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */\n\n/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ \n#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */\n\n/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */\n#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */\n#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */\n#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */\n#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */\n#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */\n#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */\n#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */\n\n/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */\n#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */\n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */\n#else \n#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */\n#endif\n\n\t\n/* Interrupt Priorities are WORD accessible only under Armv6-M                  */\n/* The following MACROS handle generation of the register offset and byte masks */\n#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)\n#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )\n#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )\n\n#define __NVIC_SetPriorityGrouping(X) (void)(X)\n#define __NVIC_GetPriorityGrouping()  (0U)\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Get Interrupt Target State\n  \\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n  \\return             1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Target State\n  \\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Clear Interrupt Target State\n  \\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  if interrupt is assigned to Secure\n                      1  if interrupt is assigned to Non Secure\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));\n    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n           If VTOR is not present address 0 must be mapped to SRAM.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n#else\n  uint32_t *vectors = (uint32_t *)0x0U;\n#endif\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                 SCB_AIRCR_SYSRESETREQ_Msk);\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   Enable Interrupt (non-secure)\n  \\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status (non-secure)\n  \\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt (non-secure)\n  \\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt (non-secure)\n  \\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt (non-secure)\n  \\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt (non-secure)\n  \\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt (non-secure)\n  \\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority (non-secure)\n  \\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every non-secure processor exception.\n */\n__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n  else\n  {\n    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |\n       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority (non-secure)\n  \\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv8.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##########################   SAU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SAUFunctions SAU Functions\n  \\brief    Functions that configure the SAU.\n  @{\n */\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n\n/**\n  \\brief   Enable SAU\n  \\details Enables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Enable(void)\n{\n    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);\n}\n\n\n\n/**\n  \\brief   Disable SAU\n  \\details Disables the Security Attribution Unit (SAU).\n */\n__STATIC_INLINE void TZ_SAU_Disable(void)\n{\n    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);\n}\n\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n/*@} end of CMSIS_Core_SAUFunctions */\n\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)\n/**\n  \\brief   System Tick Configuration (non-secure)\n  \\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n\n */\n__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                         /* Reload value impossible */\n  }\n\n  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */\n  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */\n  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                      SysTick_CTRL_TICKINT_Msk   |\n                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                           /* Function successful */\n}\n#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM23_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  },
  {
    "path": "2.Firmware/Ctrl-Step-Driver-STM32F1-fw/Drivers/CMSIS/Include/core_cm3.h",
    "content": "/**************************************************************************//**\n * @file     core_cm3.h\n * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File\n * @version  V5.0.8\n * @date     04. June 2018\n ******************************************************************************/\n/*\n * Copyright (c) 2009-2018 Arm Limited. All rights reserved.\n *\n * SPDX-License-Identifier: Apache-2.0\n *\n * Licensed under the Apache License, Version 2.0 (the License); you may\n * not use this file except in compliance with the License.\n * You may obtain a copy of the License at\n *\n * www.apache.org/licenses/LICENSE-2.0\n *\n * Unless required by applicable law or agreed to in writing, software\n * distributed under the License is distributed on an AS IS BASIS, WITHOUT\n * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n * See the License for the specific language governing permissions and\n * limitations under the License.\n */\n\n#if   defined ( __ICCARM__ )\n  #pragma system_include         /* treat file as system include file for MISRA check */\n#elif defined (__clang__)\n  #pragma clang system_header   /* treat file as system include file */\n#endif\n\n#ifndef __CORE_CM3_H_GENERIC\n#define __CORE_CM3_H_GENERIC\n\n#include <stdint.h>\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/**\n  \\page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions\n  CMSIS violates the following MISRA-C:2004 rules:\n\n   \\li Required Rule 8.5, object/function definition in header file.<br>\n     Function definitions in header files are used to allow 'inlining'.\n\n   \\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\n     Unions are used for effective representation of core registers.\n\n   \\li Advisory Rule 19.7, Function-like macro defined.<br>\n     Function-like macros are used to allow more efficient code.\n */\n\n\n/*******************************************************************************\n *                 CMSIS definitions\n ******************************************************************************/\n/**\n  \\ingroup Cortex_M3\n  @{\n */\n\n#include \"cmsis_version.h\"\n\n/*  CMSIS CM3 definitions */\n#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \\deprecated [31:16] CMSIS HAL main version */\n#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \\deprecated [15:0]  CMSIS HAL sub version */\n#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\\n                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \\deprecated CMSIS HAL version number */\n\n#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */\n\n/** __FPU_USED indicates whether an FPU is used or not.\n    This core does not support an FPU at all\n*/\n#define __FPU_USED       0U\n\n#if defined ( __CC_ARM )\n  #if defined __TARGET_FPU_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\n  #if defined __ARM_PCS_VFP\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __GNUC__ )\n  #if defined (__VFP_FP__) && !defined(__SOFTFP__)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __ICCARM__ )\n  #if defined __ARMVFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TI_ARM__ )\n  #if defined __TI_VFP_SUPPORT__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __TASKING__ )\n  #if defined __FPU_VFP__\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#elif defined ( __CSMC__ )\n  #if ( __CSMC__ & 0x400U)\n    #error \"Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)\"\n  #endif\n\n#endif\n\n#include \"cmsis_compiler.h\"               /* CMSIS compiler specific defines */\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_GENERIC */\n\n#ifndef __CMSIS_GENERIC\n\n#ifndef __CORE_CM3_H_DEPENDANT\n#define __CORE_CM3_H_DEPENDANT\n\n#ifdef __cplusplus\n extern \"C\" {\n#endif\n\n/* check device defines and use defaults */\n#if defined __CHECK_DEVICE_DEFINES\n  #ifndef __CM3_REV\n    #define __CM3_REV               0x0200U\n    #warning \"__CM3_REV not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __MPU_PRESENT\n    #define __MPU_PRESENT             0U\n    #warning \"__MPU_PRESENT not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __NVIC_PRIO_BITS\n    #define __NVIC_PRIO_BITS          3U\n    #warning \"__NVIC_PRIO_BITS not defined in device header file; using default!\"\n  #endif\n\n  #ifndef __Vendor_SysTickConfig\n    #define __Vendor_SysTickConfig    0U\n    #warning \"__Vendor_SysTickConfig not defined in device header file; using default!\"\n  #endif\n#endif\n\n/* IO definitions (access restrictions to peripheral registers) */\n/**\n    \\defgroup CMSIS_glob_defs CMSIS Global Defines\n\n    <strong>IO Type Qualifiers</strong> are used\n    \\li to specify the access to peripheral variables.\n    \\li for automatic generation of peripheral register debug information.\n*/\n#ifdef __cplusplus\n  #define   __I     volatile             /*!< Defines 'read only' permissions */\n#else\n  #define   __I     volatile const       /*!< Defines 'read only' permissions */\n#endif\n#define     __O     volatile             /*!< Defines 'write only' permissions */\n#define     __IO    volatile             /*!< Defines 'read / write' permissions */\n\n/* following defines should be used for structure members */\n#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */\n#define     __OM     volatile            /*! Defines 'write only' structure member permissions */\n#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */\n\n/*@} end of group Cortex_M3 */\n\n\n\n/*******************************************************************************\n *                 Register Abstraction\n  Core Register contain:\n  - Core Register\n  - Core NVIC Register\n  - Core SCB Register\n  - Core SysTick Register\n  - Core Debug Register\n  - Core MPU Register\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_core_register Defines and Type Definitions\n  \\brief Type definitions and defines for Cortex-M processor based devices.\n*/\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_CORE  Status and Control Registers\n  \\brief      Core Register type definitions.\n  @{\n */\n\n/**\n  \\brief  Union type to access the Application Program Status Register (APSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} APSR_Type;\n\n/* APSR Register Definitions */\n#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */\n#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */\n\n#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */\n#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */\n\n#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */\n#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */\n\n#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */\n#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */\n\n#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */\n#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */\n\n\n/**\n  \\brief  Union type to access the Interrupt Program Status Register (IPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} IPSR_Type;\n\n/* IPSR Register Definitions */\n#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */\n#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Special-Purpose Program Status Registers (xPSR).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */\n    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */\n    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */\n    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */\n    uint32_t T:1;                        /*!< bit:     24  Thumb bit */\n    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */\n    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */\n    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */\n    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */\n    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */\n    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} xPSR_Type;\n\n/* xPSR Register Definitions */\n#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */\n#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */\n\n#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */\n#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */\n\n#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */\n#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */\n\n#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */\n#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */\n\n#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */\n#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */\n\n#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */\n#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */\n\n#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */\n#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */\n\n#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */\n#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */\n\n#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */\n#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */\n\n\n/**\n  \\brief  Union type to access the Control Registers (CONTROL).\n */\ntypedef union\n{\n  struct\n  {\n    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */\n    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */\n    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */\n  } b;                                   /*!< Structure used for bit  access */\n  uint32_t w;                            /*!< Type      used for word access */\n} CONTROL_Type;\n\n/* CONTROL Register Definitions */\n#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */\n#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */\n\n#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */\n#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */\n\n/*@} end of group CMSIS_CORE */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)\n  \\brief      Type definitions for the NVIC Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).\n */\ntypedef struct\n{\n  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */\n        uint32_t RESERVED0[24U];\n  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */\n        uint32_t RSERVED1[24U];\n  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */\n        uint32_t RESERVED2[24U];\n  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */\n        uint32_t RESERVED3[24U];\n  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */\n        uint32_t RESERVED4[56U];\n  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */\n        uint32_t RESERVED5[644U];\n  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */\n}  NVIC_Type;\n\n/* Software Triggered Interrupt Register Definitions */\n#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */\n#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */\n\n/*@} end of group CMSIS_NVIC */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCB     System Control Block (SCB)\n  \\brief    Type definitions for the System Control Block Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control Block (SCB).\n */\ntypedef struct\n{\n  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */\n  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */\n  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */\n  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */\n  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */\n  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */\n  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */\n  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */\n  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */\n  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */\n  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */\n  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */\n  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */\n  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */\n  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */\n  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */\n  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */\n  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */\n  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */\n        uint32_t RESERVED0[5U];\n  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */\n} SCB_Type;\n\n/* SCB CPUID Register Definitions */\n#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */\n#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */\n\n#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */\n#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */\n\n#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */\n#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */\n\n#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */\n#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */\n\n#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */\n#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */\n\n/* SCB Interrupt Control State Register Definitions */\n#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */\n#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */\n\n#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */\n#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */\n\n#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */\n#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */\n\n#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */\n#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */\n\n#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */\n#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */\n\n#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */\n#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */\n\n#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */\n#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */\n\n#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */\n#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */\n\n#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */\n#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */\n\n#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */\n#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */\n\n/* SCB Vector Table Offset Register Definitions */\n#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */\n#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */\n#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */\n\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */\n#else\n#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */\n#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */\n#endif\n\n/* SCB Application Interrupt and Reset Control Register Definitions */\n#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */\n#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */\n\n#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */\n#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */\n\n#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */\n#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */\n\n#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */\n#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */\n\n#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */\n#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */\n\n#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */\n#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */\n\n#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */\n#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */\n\n/* SCB System Control Register Definitions */\n#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */\n#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */\n\n#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */\n#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */\n\n#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */\n#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */\n\n/* SCB Configuration Control Register Definitions */\n#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */\n#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */\n\n#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */\n#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */\n\n#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */\n#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */\n\n#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */\n#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */\n\n#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */\n#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */\n\n#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */\n#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */\n\n/* SCB System Handler Control and State Register Definitions */\n#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */\n#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */\n\n#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */\n#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */\n\n#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */\n#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */\n\n#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */\n#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */\n\n#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */\n#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */\n\n#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */\n#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */\n\n#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */\n#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */\n\n#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */\n#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */\n\n#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */\n#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */\n\n#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */\n#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */\n\n#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */\n#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */\n\n#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */\n#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */\n\n#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */\n#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */\n\n#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */\n#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */\n\n/* SCB Configurable Fault Status Register Definitions */\n#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */\n#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */\n\n#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */\n#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */\n\n#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */\n#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\n\n/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */\n#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */\n\n#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */\n#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */\n\n#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */\n#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */\n\n#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */\n#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */\n\n#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */\n#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */\n\n/* BusFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */\n#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */\n\n#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */\n#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */\n\n#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */\n#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */\n\n#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */\n#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */\n\n#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */\n#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */\n\n#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */\n#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */\n\n/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */\n#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */\n#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */\n\n#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */\n#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */\n\n#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */\n#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */\n\n#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */\n#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */\n\n#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */\n#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */\n\n#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */\n#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */\n\n/* SCB Hard Fault Status Register Definitions */\n#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */\n#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */\n\n#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */\n#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */\n\n#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */\n#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */\n\n/* SCB Debug Fault Status Register Definitions */\n#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */\n#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */\n\n#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */\n#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */\n\n#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */\n#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */\n\n#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */\n#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */\n\n#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */\n#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */\n\n/*@} end of group CMSIS_SCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\n  \\brief    Type definitions for the System Control and ID Register not in the SCB\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Control and ID Register not in the SCB.\n */\ntypedef struct\n{\n        uint32_t RESERVED0[1U];\n  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */\n#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)\n  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */\n#else\n        uint32_t RESERVED1[1U];\n#endif\n} SCnSCB_Type;\n\n/* Interrupt Controller Type Register Definitions */\n#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */\n#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */\n\n/* Auxiliary Control Register Definitions */\n\n#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */\n#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */\n\n#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */\n#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */\n\n#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */\n#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */\n\n/*@} end of group CMSIS_SCnotSCB */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_SysTick     System Tick Timer (SysTick)\n  \\brief    Type definitions for the System Timer Registers.\n  @{\n */\n\n/**\n  \\brief  Structure type to access the System Timer (SysTick).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */\n  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */\n  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */\n  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */\n} SysTick_Type;\n\n/* SysTick Control / Status Register Definitions */\n#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */\n#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */\n\n#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */\n#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */\n\n#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */\n#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */\n\n#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */\n#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */\n\n/* SysTick Reload Register Definitions */\n#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */\n#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */\n\n/* SysTick Current Register Definitions */\n#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */\n#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */\n\n/* SysTick Calibration Register Definitions */\n#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */\n#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */\n\n#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */\n#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */\n\n#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */\n#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */\n\n/*@} end of group CMSIS_SysTick */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)\n  \\brief    Type definitions for the Instrumentation Trace Macrocell (ITM)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).\n */\ntypedef struct\n{\n  __OM  union\n  {\n    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */\n    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */\n    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */\n  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */\n        uint32_t RESERVED0[864U];\n  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */\n        uint32_t RESERVED1[15U];\n  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */\n        uint32_t RESERVED2[15U];\n  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */\n        uint32_t RESERVED3[29U];\n  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */\n  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */\n  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */\n        uint32_t RESERVED4[43U];\n  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */\n  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */\n        uint32_t RESERVED5[6U];\n  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */\n  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */\n  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */\n  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */\n  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */\n  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */\n  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */\n  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */\n  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */\n  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */\n  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */\n  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */\n} ITM_Type;\n\n/* ITM Trace Privilege Register Definitions */\n#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */\n#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */\n\n/* ITM Trace Control Register Definitions */\n#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */\n#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */\n\n#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */\n#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */\n\n#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */\n#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */\n\n#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */\n#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */\n\n#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */\n#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */\n\n#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */\n#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */\n\n#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */\n#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */\n\n#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */\n#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */\n\n#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */\n#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */\n\n/* ITM Integration Write Register Definitions */\n#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */\n#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */\n\n/* ITM Integration Read Register Definitions */\n#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */\n#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */\n\n/* ITM Integration Mode Control Register Definitions */\n#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */\n#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */\n\n/* ITM Lock Status Register Definitions */\n#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */\n#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */\n\n#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */\n#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */\n\n#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */\n#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */\n\n/*@}*/ /* end of group CMSIS_ITM */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)\n  \\brief    Type definitions for the Data Watchpoint and Trace (DWT)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Data Watchpoint and Trace Register (DWT).\n */\ntypedef struct\n{\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */\n  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */\n  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */\n  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */\n  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */\n  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */\n  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */\n  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */\n  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */\n  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */\n  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */\n        uint32_t RESERVED0[1U];\n  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */\n  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */\n  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */\n        uint32_t RESERVED1[1U];\n  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */\n  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */\n  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */\n        uint32_t RESERVED2[1U];\n  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */\n  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */\n  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */\n} DWT_Type;\n\n/* DWT Control Register Definitions */\n#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */\n#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */\n\n#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */\n#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */\n\n#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */\n#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */\n\n#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */\n#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */\n\n#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */\n#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */\n\n#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */\n#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */\n\n#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */\n#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */\n\n#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */\n#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */\n\n#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */\n#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */\n\n#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */\n#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */\n\n#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */\n#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */\n\n#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */\n#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */\n\n#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */\n#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */\n\n#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */\n#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */\n\n#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */\n#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */\n\n#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */\n#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */\n\n#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */\n#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */\n\n#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */\n#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */\n\n/* DWT CPI Count Register Definitions */\n#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */\n#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */\n\n/* DWT Exception Overhead Count Register Definitions */\n#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */\n#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */\n\n/* DWT Sleep Count Register Definitions */\n#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */\n#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */\n\n/* DWT LSU Count Register Definitions */\n#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */\n#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */\n\n/* DWT Folded-instruction Count Register Definitions */\n#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */\n#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */\n\n/* DWT Comparator Mask Register Definitions */\n#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */\n#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */\n\n/* DWT Comparator Function Register Definitions */\n#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */\n#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */\n\n#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */\n#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */\n\n#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */\n#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */\n\n#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */\n#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */\n\n#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */\n#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */\n\n#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */\n#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */\n\n#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */\n#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */\n\n#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */\n#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */\n\n#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */\n#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */\n\n/*@}*/ /* end of group CMSIS_DWT */\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_TPI     Trace Port Interface (TPI)\n  \\brief    Type definitions for the Trace Port Interface (TPI)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Trace Port Interface Register (TPI).\n */\ntypedef struct\n{\n  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */\n  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */\n        uint32_t RESERVED0[2U];\n  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */\n        uint32_t RESERVED1[55U];\n  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */\n        uint32_t RESERVED2[131U];\n  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */\n  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */\n  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */\n        uint32_t RESERVED3[759U];\n  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */\n  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */\n  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */\n        uint32_t RESERVED4[1U];\n  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */\n  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */\n  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */\n        uint32_t RESERVED5[39U];\n  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */\n  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */\n        uint32_t RESERVED7[8U];\n  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */\n  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */\n} TPI_Type;\n\n/* TPI Asynchronous Clock Prescaler Register Definitions */\n#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */\n#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */\n\n/* TPI Selected Pin Protocol Register Definitions */\n#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */\n#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */\n\n/* TPI Formatter and Flush Status Register Definitions */\n#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */\n#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */\n\n#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */\n#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */\n\n#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */\n#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */\n\n#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */\n#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */\n\n/* TPI Formatter and Flush Control Register Definitions */\n#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */\n#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */\n\n#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */\n#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */\n\n/* TPI TRIGGER Register Definitions */\n#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */\n#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */\n\n/* TPI Integration ETM Data Register Definitions (FIFO0) */\n#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */\n#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */\n\n#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */\n#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */\n\n#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */\n#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */\n\n#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */\n#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */\n\n#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */\n#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */\n\n#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */\n#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */\n\n#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */\n#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */\n\n/* TPI ITATBCTR2 Register Definitions */\n#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */\n#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */\n\n#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */\n#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */\n\n/* TPI Integration ITM Data Register Definitions (FIFO1) */\n#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */\n#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */\n\n#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */\n#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */\n\n#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */\n#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */\n\n#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */\n#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */\n\n#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */\n#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */\n\n#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */\n#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */\n\n#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */\n#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */\n\n/* TPI ITATBCTR0 Register Definitions */\n#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */\n#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */\n\n#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */\n#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */\n\n/* TPI Integration Mode Control Register Definitions */\n#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */\n#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */\n\n/* TPI DEVID Register Definitions */\n#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */\n#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */\n\n#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */\n#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */\n\n#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */\n#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */\n\n#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */\n#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */\n\n#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */\n#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */\n\n#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */\n#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */\n\n/* TPI DEVTYPE Register Definitions */\n#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */\n#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */\n\n#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */\n#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */\n\n/*@}*/ /* end of group CMSIS_TPI */\n\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_MPU     Memory Protection Unit (MPU)\n  \\brief    Type definitions for the Memory Protection Unit (MPU)\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Memory Protection Unit (MPU).\n */\ntypedef struct\n{\n  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */\n  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */\n  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */\n  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */\n  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */\n  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */\n  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */\n  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */\n  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */\n} MPU_Type;\n\n#define MPU_TYPE_RALIASES                  4U\n\n/* MPU Type Register Definitions */\n#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */\n#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */\n\n#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */\n#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */\n\n#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */\n#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */\n\n/* MPU Control Register Definitions */\n#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */\n#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */\n\n#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */\n#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */\n\n#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */\n#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */\n\n/* MPU Region Number Register Definitions */\n#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */\n#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */\n\n/* MPU Region Base Address Register Definitions */\n#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */\n#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */\n\n#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */\n#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */\n\n#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */\n#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */\n\n/* MPU Region Attribute and Size Register Definitions */\n#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */\n#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */\n\n#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */\n#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */\n\n#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */\n#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */\n\n#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */\n#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */\n\n#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */\n#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */\n\n#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */\n#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */\n\n#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */\n#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */\n\n#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */\n#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */\n\n#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */\n#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */\n\n#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */\n#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */\n\n/*@} end of group CMSIS_MPU */\n#endif\n\n\n/**\n  \\ingroup  CMSIS_core_register\n  \\defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)\n  \\brief    Type definitions for the Core Debug Registers\n  @{\n */\n\n/**\n  \\brief  Structure type to access the Core Debug Register (CoreDebug).\n */\ntypedef struct\n{\n  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */\n  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */\n  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */\n  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */\n} CoreDebug_Type;\n\n/* Debug Halting Control and Status Register Definitions */\n#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */\n#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */\n\n#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */\n#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */\n\n#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\n#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\n\n#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */\n#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */\n\n#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */\n#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */\n\n#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */\n#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */\n\n#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */\n#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */\n\n#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\n#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\n\n#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */\n#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */\n\n#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */\n#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */\n\n#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */\n#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */\n\n#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */\n#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\n\n/* Debug Core Register Selector Register Definitions */\n#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */\n#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */\n\n#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */\n#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */\n\n/* Debug Exception and Monitor Control Register Definitions */\n#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */\n#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */\n\n#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */\n#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */\n\n#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */\n#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */\n\n#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */\n#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */\n\n#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */\n#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */\n\n#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */\n#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */\n\n#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */\n#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */\n\n#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */\n#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */\n\n#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */\n#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */\n\n#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */\n#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */\n\n#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */\n#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\n\n#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */\n#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */\n\n#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */\n#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */\n\n/*@} end of group CMSIS_CoreDebug */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_bitfield     Core register bit field macros\n  \\brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\n  @{\n */\n\n/**\n  \\brief   Mask and shift a bit field value for use in a register bit range.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted value.\n*/\n#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)\n\n/**\n  \\brief     Mask and shift a register value to extract a bit filed value.\n  \\param[in] field  Name of the register bit field.\n  \\param[in] value  Value of register. This parameter is interpreted as an uint32_t type.\n  \\return           Masked and shifted bit field value.\n*/\n#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)\n\n/*@} end of group CMSIS_core_bitfield */\n\n\n/**\n  \\ingroup    CMSIS_core_register\n  \\defgroup   CMSIS_core_base     Core Definitions\n  \\brief      Definitions for base addresses, unions, and structures.\n  @{\n */\n\n/* Memory mapping of Core Hardware */\n#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */\n#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */\n#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */\n#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */\n#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */\n#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */\n#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */\n#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */\n\n#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */\n#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */\n#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */\n#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */\n#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */\n#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */\n#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */\n#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */\n  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */\n#endif\n\n/*@} */\n\n\n\n/*******************************************************************************\n *                Hardware Abstraction Layer\n  Core Function Interface contains:\n  - Core NVIC Functions\n  - Core SysTick Functions\n  - Core Debug Functions\n  - Core Register Access Functions\n ******************************************************************************/\n/**\n  \\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\n*/\n\n\n\n/* ##########################   NVIC functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_NVICFunctions NVIC Functions\n  \\brief    Functions that manage interrupts and exceptions via the NVIC.\n  @{\n */\n\n#ifdef CMSIS_NVIC_VIRTUAL\n  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE\n    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE \"cmsis_nvic_virtual.h\"\n  #endif\n  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping\n  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping\n  #define NVIC_EnableIRQ              __NVIC_EnableIRQ\n  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ\n  #define NVIC_DisableIRQ             __NVIC_DisableIRQ\n  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ\n  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ\n  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ\n  #define NVIC_GetActive              __NVIC_GetActive\n  #define NVIC_SetPriority            __NVIC_SetPriority\n  #define NVIC_GetPriority            __NVIC_GetPriority\n  #define NVIC_SystemReset            __NVIC_SystemReset\n#endif /* CMSIS_NVIC_VIRTUAL */\n\n#ifdef CMSIS_VECTAB_VIRTUAL\n  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE \"cmsis_vectab_virtual.h\"\n  #endif\n  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE\n#else\n  #define NVIC_SetVector              __NVIC_SetVector\n  #define NVIC_GetVector              __NVIC_GetVector\n#endif  /* (CMSIS_VECTAB_VIRTUAL) */\n\n#define NVIC_USER_IRQ_OFFSET          16\n\n\n/* The following EXC_RETURN values are saved the LR on exception entry */\n#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */\n#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */\n#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */\n\n\n/**\n  \\brief   Set Priority Grouping\n  \\details Sets the priority grouping field using the required unlock sequence.\n           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\n           Only values from 0..7 are used.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]      PriorityGroup  Priority grouping field.\n */\n__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\n{\n  uint32_t reg_value;\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */\n\n  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */\n  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */\n  reg_value  =  (reg_value                                   |\n                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\n                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */\n  SCB->AIRCR =  reg_value;\n}\n\n\n/**\n  \\brief   Get Priority Grouping\n  \\details Reads the priority grouping field from the NVIC Interrupt Controller.\n  \\return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)\n{\n  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\n}\n\n\n/**\n  \\brief   Enable Interrupt\n  \\details Enables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Enable status\n  \\details Returns a device specific interrupt enable status from the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt is not enabled.\n  \\return             1  Interrupt is enabled.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Disable Interrupt\n  \\details Disables a device specific interrupt in the NVIC interrupt controller.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n    __DSB();\n    __ISB();\n  }\n}\n\n\n/**\n  \\brief   Get Pending Interrupt\n  \\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not pending.\n  \\return             1  Interrupt status is pending.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Pending Interrupt\n  \\details Sets the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Clear Pending Interrupt\n  \\details Clears the pending bit of a device specific interrupt in the NVIC pending register.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));\n  }\n}\n\n\n/**\n  \\brief   Get Active Interrupt\n  \\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.\n  \\param [in]      IRQn  Device specific interrupt number.\n  \\return             0  Interrupt status is not active.\n  \\return             1  Interrupt status is active.\n  \\note    IRQn must not be negative.\n */\n__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\n  }\n  else\n  {\n    return(0U);\n  }\n}\n\n\n/**\n  \\brief   Set Interrupt Priority\n  \\details Sets the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]      IRQn  Interrupt number.\n  \\param [in]  priority  Priority to set.\n  \\note    The priority cannot be set for every processor exception.\n */\n__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\n{\n  if ((int32_t)(IRQn) >= 0)\n  {\n    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n  else\n  {\n    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\n  }\n}\n\n\n/**\n  \\brief   Get Interrupt Priority\n  \\details Reads the priority of a device specific interrupt or a processor exception.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn  Interrupt number.\n  \\return             Interrupt Priority.\n                      Value is aligned automatically to the implemented priority bits of the microcontroller.\n */\n__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)\n{\n\n  if ((int32_t)(IRQn) >= 0)\n  {\n    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));\n  }\n  else\n  {\n    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\n  }\n}\n\n\n/**\n  \\brief   Encode Priority\n  \\details Encodes the priority for an interrupt with the given priority group,\n           preemptive priority value, and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [in]   PreemptPriority  Preemptive priority value (starting from 0).\n  \\param [in]       SubPriority  Subpriority value (starting from 0).\n  \\return                        Encoded priority. Value can be used in the function \\ref NVIC_SetPriority().\n */\n__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  return (\n           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\n           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))\n         );\n}\n\n\n/**\n  \\brief   Decode Priority\n  \\details Decodes an interrupt priority value with a given priority group to\n           preemptive priority value and subpriority value.\n           In case of a conflict between priority grouping and available\n           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\n  \\param [in]         Priority   Priority value, which can be retrieved with the function \\ref NVIC_GetPriority().\n  \\param [in]     PriorityGroup  Used priority group.\n  \\param [out] pPreemptPriority  Preemptive priority value (starting from 0).\n  \\param [out]     pSubPriority  Subpriority value (starting from 0).\n */\n__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\n{\n  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */\n  uint32_t PreemptPriorityBits;\n  uint32_t SubPriorityBits;\n\n  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\n  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\n\n  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\n  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);\n}\n\n\n/**\n  \\brief   Set Interrupt Vector\n  \\details Sets an interrupt vector in SRAM based interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n           VTOR must been relocated to SRAM before.\n  \\param [in]   IRQn      Interrupt number\n  \\param [in]   vector    Address of interrupt handler function\n */\n__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;\n}\n\n\n/**\n  \\brief   Get Interrupt Vector\n  \\details Reads an interrupt vector from interrupt vector table.\n           The interrupt number can be positive to specify a device specific interrupt,\n           or negative to specify a processor exception.\n  \\param [in]   IRQn      Interrupt number.\n  \\return                 Address of interrupt handler function\n */\n__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)\n{\n  uint32_t *vectors = (uint32_t *)SCB->VTOR;\n  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];\n}\n\n\n/**\n  \\brief   System Reset\n  \\details Initiates a system reset request to reset the MCU.\n */\n__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)\n{\n  __DSB();                                                          /* Ensure all outstanding memory accesses included\n                                                                       buffered write are completed before reset */\n  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |\n                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\n                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */\n  __DSB();                                                          /* Ensure completion of memory access */\n\n  for(;;)                                                           /* wait until reset */\n  {\n    __NOP();\n  }\n}\n\n/*@} end of CMSIS_Core_NVICFunctions */\n\n/* ##########################  MPU functions  #################################### */\n\n#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)\n\n#include \"mpu_armv7.h\"\n\n#endif\n\n/* ##########################  FPU functions  #################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_FpuFunctions FPU Functions\n  \\brief    Function that provides FPU type.\n  @{\n */\n\n/**\n  \\brief   get FPU type\n  \\details returns the FPU type\n  \\returns\n   - \\b  0: No FPU\n   - \\b  1: Single precision FPU\n   - \\b  2: Double + Single precision FPU\n */\n__STATIC_INLINE uint32_t SCB_GetFPUType(void)\n{\n    return 0U;           /* No FPU */\n}\n\n\n/*@} end of CMSIS_Core_FpuFunctions */\n\n\n\n/* ##################################    SysTick function  ############################################ */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_Core_SysTickFunctions SysTick Functions\n  \\brief    Functions that configure the System.\n  @{\n */\n\n#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)\n\n/**\n  \\brief   System Tick Configuration\n  \\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\n           Counter is in free running mode to generate periodic interrupts.\n  \\param [in]  ticks  Number of ticks between two interrupts.\n  \\return          0  Function succeeded.\n  \\return          1  Function failed.\n  \\note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\n           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\n           must contain a vendor-specific implementation of this function.\n */\n__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\n{\n  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\n  {\n    return (1UL);                                                   /* Reload value impossible */\n  }\n\n  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */\n  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\n  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */\n  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |\n                   SysTick_CTRL_TICKINT_Msk   |\n                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */\n  return (0UL);                                                     /* Function successful */\n}\n\n#endif\n\n/*@} end of CMSIS_Core_SysTickFunctions */\n\n\n\n/* ##################################### Debug In/Output function ########################################### */\n/**\n  \\ingroup  CMSIS_Core_FunctionInterface\n  \\defgroup CMSIS_core_DebugFunctions ITM Functions\n  \\brief    Functions that access the ITM debug interface.\n  @{\n */\n\nextern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */\n#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \\ref ITM_RxBuffer is ready for next character. */\n\n\n/**\n  \\brief   ITM Send Character\n  \\details Transmits a character via the ITM channel 0, and\n           \\li Just returns when no debugger is connected that has booked the output.\n           \\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\n  \\param [in]     ch  Character to transmit.\n  \\returns            Character to transmit.\n */\n__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\n{\n  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */\n      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */\n  {\n    while (ITM->PORT[0U].u32 == 0UL)\n    {\n      __NOP();\n    }\n    ITM->PORT[0U].u8 = (uint8_t)ch;\n  }\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Receive Character\n  \\details Inputs a character via the external variable \\ref ITM_RxBuffer.\n  \\return             Received character.\n  \\return         -1  No character pending.\n */\n__STATIC_INLINE int32_t ITM_ReceiveChar (void)\n{\n  int32_t ch = -1;                           /* no character available */\n\n  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\n  {\n    ch = ITM_RxBuffer;\n    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */\n  }\n\n  return (ch);\n}\n\n\n/**\n  \\brief   ITM Check Character\n  \\details Checks whether a character is pending for reading in the variable \\ref ITM_RxBuffer.\n  \\return          0  No character available.\n  \\return          1  Character available.\n */\n__STATIC_INLINE int32_t ITM_CheckChar (void)\n{\n\n  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\n  {\n    return (0);                              /* no character available */\n  }\n  else\n  {\n    return (1);                              /*    character available */\n  }\n}\n\n/*@} end of CMSIS_core_DebugFunctions */\n\n\n\n\n#ifdef __cplusplus\n}\n#endif\n\n#endif /* __CORE_CM3_H_DEPENDANT */\n\n#endif /* __CMSIS_GENERIC */\n"
  }
]